device/arm: clear pending interrupts before enabling them

Without this change, a pending interrupt would spuriously trigger
immediately after enabling. This happens if an interrupt is triggered
during flashing (e.g. by DMA), which survives the subsequent reset.

This behaviour matches e.g. `machine.irqSet` in machine_rp2_rp2350.go.

See 7f970a4, whose symptoms were likely caused by spurious interrupts.

Author: eliasnaur

src/device/arm/arm.go

@@ -148,7 +148,13 @@ const (
 
 // Enable the given interrupt number.
 func EnableIRQ(irq uint32) {
-	NVIC.ISER[irq>>5].Set(1 << (irq & 0x1F))
+	idx := irq / 32
+	mask := uint32(0b1) << (irq % 32)
+
+	// Clear pending.
+	NVIC.ICPR[idx].Set(mask)
+	// Enable.
+	NVIC.ISER[idx].Set(mask)
 }
 
 // Disable the given interrupt number.