A RISC-V 5-stage pipelined CPU that supports vector instructions. Tape-out with U18 technology.
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Dec 2, 2019 - Verilog
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place-and-route
Here are 6 public repositories matching this topic...
SymbiFlow WIP changes for Verilog to Routing -- Open Source CAD Flow for FPGA Research
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Aug 21, 2024 - C++
Electronic design automation for Minecraft
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May 3, 2019 - Python
Open-Source VHDL Synthesis for Alhambra II FPGA Board
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Jan 19, 2025 - VHDL
LangChain based VLSI flow that is able to generate required HDL, testbench, design creation and implementaion scripts.
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Jul 15, 2023 - Makefile
Lark based DEF file parser
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Jun 4, 2023 - Python
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