From 5307260a7e90f6536e894301e78fd474f5b7f20c Mon Sep 17 00:00:00 2001 From: Lukas Baischer Date: Wed, 17 Jun 2020 13:40:41 +0200 Subject: [PATCH] Modifications for adjustable activation width --- .../src/3x3_Kernel_log2/log2_multiplier.vhd | 19 ++++++++++--------- .../src/3x3_Kernel_log2/quantized_adder.vhd | 7 ++++--- 2 files changed, 14 insertions(+), 12 deletions(-) diff --git a/vivado/NN_IP/EggNet_1.0/src/3x3_Kernel_log2/log2_multiplier.vhd b/vivado/NN_IP/EggNet_1.0/src/3x3_Kernel_log2/log2_multiplier.vhd index 3193cc7..5b7d02b 100644 --- a/vivado/NN_IP/EggNet_1.0/src/3x3_Kernel_log2/log2_multiplier.vhd +++ b/vivado/NN_IP/EggNet_1.0/src/3x3_Kernel_log2/log2_multiplier.vhd @@ -29,9 +29,10 @@ entity log2_multiplier is end log2_multiplier; architecture Behavioral of log2_multiplier is - signal x_signed : std_logic_vector(INPUT_WIDTH downto 0); - signal carry : std_logic_vector(INPUT_WIDTH downto 0) := (others => '0'); - signal x_shift : std_logic_vector(INPUT_WIDTH - 1 downto 0); + signal x_signed : std_logic_vector(INPUT_WIDTH downto 0) := (others => '0'); + signal adder_out : std_logic_vector(((INPUT_WIDTH-1)/4)*4+4 downto 0) := (others => '0'); + signal carry : std_logic_vector(((INPUT_WIDTH-1)/4)*4+4 downto 0) := (others => '0'); + signal x_shift : std_logic_vector(((INPUT_WIDTH-1)/4)*4+4 downto 0) := (others => '0'); begin @@ -55,9 +56,9 @@ begin x_shift <= (others => '0'); else if S_Sign_i = "1" then - x_shift <= not std_logic_vector(SHIFT_RIGHT(unsigned(S_X_data_i), to_integer(unsigned(S_Shift_i)))); + x_shift(INPUT_WIDTH-1 downto 0) <= not std_logic_vector(SHIFT_RIGHT(unsigned(S_X_data_i), to_integer(unsigned(S_Shift_i)))); else - x_shift <= std_logic_vector(SHIFT_RIGHT(unsigned(S_X_data_i), to_integer(unsigned(S_Shift_i)))); + x_shift(INPUT_WIDTH-1 downto 0) <= std_logic_vector(SHIFT_RIGHT(unsigned(S_X_data_i), to_integer(unsigned(S_Shift_i)))); end if; end if; end process; @@ -68,15 +69,15 @@ begin CARRY4_inst : CARRY4 port map( CO => carry(4 * i + 3 + 1 downto 4 * i + 1), -- 4-bit carry out - O => x_signed(4 * i + 3 downto 4 * i), -- 4-bit carry chain XOR data out + O => adder_out(4 * i + 3 downto 4 * i), -- 4-bit carry chain XOR data out CI => carry(4 * i), -- 1-bit carry cascade input CYINIT => '0', -- 1-bit carry initialization DI => x_shift(4 * i + 3 downto 4 * i), -- 4-bit carry-MUX data in S => x_shift(4 * i + 3 downto 4 * i) -- 4-bit carry-MUX select input ); end generate; - - x_signed(x_signed'left) <= S_Sign_i(0); + x_signed(INPUT_WIDTH-1 downto 0) <= adder_out(INPUT_WIDTH-1 downto 0); + x_signed(INPUT_WIDTH) <= S_Sign_i(0); Register_Yo : for i in 0 to INPUT_WIDTH generate FDRE_inst : FDRE generic map( @@ -85,7 +86,7 @@ begin Q => M_Weighted_X(i), -- Data output C => Clk_i, -- Clock input CE => M_Ready_i, -- Clock enable input - R => carry(carry'left) and M_Ready_i, -- Synchronous reset input + R => carry(INPUT_WIDTH) and M_Ready_i, -- Synchronous reset input D => x_signed(i) -- Data input ); end generate; diff --git a/vivado/NN_IP/EggNet_1.0/src/3x3_Kernel_log2/quantized_adder.vhd b/vivado/NN_IP/EggNet_1.0/src/3x3_Kernel_log2/quantized_adder.vhd index 8b28958..c1c04b2 100644 --- a/vivado/NN_IP/EggNet_1.0/src/3x3_Kernel_log2/quantized_adder.vhd +++ b/vivado/NN_IP/EggNet_1.0/src/3x3_Kernel_log2/quantized_adder.vhd @@ -26,11 +26,12 @@ architecture Behavioral of quantized_adder is constant ZERO_BIT : bit := '0'; constant ZERO_STD_ULOGIC : std_ulogic := '0'; signal carry : std_logic_vector(((INPUT_WIDTH-1)/4)*4+4 downto 0) := (others => '0'); -- Divide by 4 and then multiply by 4 is used to get a multiple of 4 as result - signal sum : std_logic_vector(((INPUT_WIDTH-1)/4)*4+4 downto 0) := (others => '0'); + signal chain_out : std_logic_vector(((INPUT_WIDTH-1)/4)*4+4 downto 0) := (others => '0'); signal a_sig : std_logic_vector(((INPUT_WIDTH-1)/4)*4+3 downto 0) := (others => '0'); signal a_xor_b : std_logic_vector(((INPUT_WIDTH-1)/4)*4+3 downto 0) := (others => '0'); signal sum_R : std_logic_vector(OUTPUT_WIDTH-1 downto 0) := (others => '0'); signal shift :std_logic_vector(OUTPUT_WIDTH-1 downto 0) := (others => '0'); + signal sum :std_logic_vector(INPUT_WIDTH downto 0); signal overflow_neg : std_ulogic := '0'; signal underflow_neg :std_ulogic := '0'; signal overflow_pos_R : std_ulogic := '0'; @@ -46,15 +47,15 @@ CARRY_chain: for i in 0 to (INPUT_WIDTH-1)/4 generate CARRY4_inst : CARRY4 port map ( CO => carry(4*i+3+1 downto 4*i+1), -- 4-bit carry out - O => sum(4*i+3 downto 4*i), -- 4-bit carry chain XOR data out + O => chain_out(4*i+3 downto 4*i), -- 4-bit carry chain XOR data out CI => carry(4*i), -- 1-bit carry cascade input CYINIT => carry(0), -- 1-bit carry initialization DI => a_sig(4*i+3 downto 4*i), -- 4-bit carry-MUX data in S => a_xor_b(4*i+3 downto 4*i) -- 4-bit carry-MUX select input ); end generate; +sum(INPUT_WIDTH-1 downto 0) <= chain_out(INPUT_WIDTH-1 downto 0); sum(INPUT_WIDTH) <= carry(INPUT_WIDTH) xor a_xor_b(INPUT_WIDTH-1); - -- ***** Overflow detection and Quantization ******* -- Overflow can occur if -- - Overflow in Carry chain is detected