diff --git a/.buildinfo b/.buildinfo new file mode 100644 index 0000000000..caa395a639 --- /dev/null +++ b/.buildinfo @@ -0,0 +1,4 @@ +# Sphinx build info version 1 +# This file hashes the configuration used when building these files. When it is not found, a full rebuild will be done. +config: 5ee66292091ff32fcf1050388dd8a28f +tags: 645f666f9bcd5a90fca523b33c5a78b7 diff --git a/.nojekyll b/.nojekyll new file mode 100644 index 0000000000..e69de29bb2 diff --git a/_sources/compatibility/board.rst.txt b/_sources/compatibility/board.rst.txt new file mode 100644 index 0000000000..664e9ff1a0 --- /dev/null +++ b/_sources/compatibility/board.rst.txt @@ -0,0 +1,20 @@ +.. _compatibility:boards: + +Boards +###### + +.. NOTE:: + `arty` can be any of the board names from the first column. + +.. code-block:: bash + + openFPGALoader -b arty bitstream.bit # Loading in SRAM (volatile) + openFPGALoader -b arty -f bitstream.bit # Writing in flash (non-volatile) + +.. include:: boards.inc + +* IF: Internal Flash +* EF: External Flash +* AS: Active Serial flash mode +* NA: Not Available +* NT: Not Tested diff --git a/_sources/compatibility/cable.rst.txt b/_sources/compatibility/cable.rst.txt new file mode 100644 index 0000000000..9defcbef0a --- /dev/null +++ b/_sources/compatibility/cable.rst.txt @@ -0,0 +1,6 @@ +.. _compatibility:cables: + +Cables +###### + +.. include:: cable.inc diff --git a/_sources/compatibility/fpga.rst.txt b/_sources/compatibility/fpga.rst.txt new file mode 100644 index 0000000000..cb61eddf18 --- /dev/null +++ b/_sources/compatibility/fpga.rst.txt @@ -0,0 +1,11 @@ +.. _compatibility:fpgas: + +FPGAs +##### + +.. include:: fpga.inc + +* IF: Internal Flash +* AS: Active Serial flash mode +* NA: Not Available +* NT: Not Tested diff --git a/_sources/guide/advanced.rst.txt b/_sources/guide/advanced.rst.txt new file mode 100644 index 0000000000..c375a86e36 --- /dev/null +++ b/_sources/guide/advanced.rst.txt @@ -0,0 +1,101 @@ +.. _advanced-usage: + +Advanced usage of openFPGALoader +################################ + +Resetting an FPGA +================= + +.. code-block:: bash + + openFPGALoader [options] -r + +Using negative edge for TDO's sampling +====================================== + +If transaction are unstable you can try to change read edge by using + +.. code-block:: bash + + openFPGALoader [options] --invert-read-edge + +Reading the bitstream from STDIN +================================ + +.. code-block:: bash + + cat /path/to/bitstream.ext | openFPGALoader --file-type ext [options] + +``--file-type`` is required to detect file type. + +.. NOTE:: + It's possible to load a bitstream through network: + + .. code-block:: bash + + # FPGA side + nc -lp port | openFPGALoader --file-type xxx [option + + # Bitstream side + nc -q 0 host port < /path/to/bitstream.ext + +Automatic file type detection bypass +==================================== + +Default behavior is to use file extension to determine file parser. +To avoid this mechanism ``--file-type type`` must be used. + +FT231/FT232 bitbang mode and pins configuration +=============================================== + +FT232R and ft231X may be used as JTAG programmer. +JTAG communications are emulated in bitbang mode. + +To use these devices user needs to provides both the cable and the pin mapping: + +.. code-block:: bash + + openFPGALoader [options] -cft23XXX --pins=TDI:TDO:TCK:TMS /path/to/bitstream.ext + +where: + +* ft23XXX may be ``ft232RL`` or ``ft231X``. +* TDI:TDO:TCK:TMS may be the pin ID (0 <= id <= 7) or string value. + +allowed values are: + +===== == +value ID +===== == + TXD 0 + RXD 1 + RTS 2 + CTS 3 + DTR 4 + DSR 5 + DCD 6 + RI 7 +===== == + +Writing to an arbitrary address in flash memory +=============================================== + +With FPGA using an external SPI flash (*xilinx*, *lattice ECP5/nexus/ice40*, *anlogic*, *efinix*) option ``-o`` allows +one to write raw binary file to an arbitrary adress in FLASH. + +Using an alternative directory for *spiOverJtag* +================================================ + +By setting ``OPENFPGALOADER_SOJ_DIR`` it's possible to override default +*spiOverJtag* bitstreams directory: + +.. code-block:: bash + + export OPENFPGALOADER_SOJ_DIR=/somewhere + openFPGALoader xxxx + +or + +.. code-block:: bash + + OPENFPGALOADER_SOJ_DIR=/somewhere openFPGALoader xxxx diff --git a/_sources/guide/first-steps.rst.txt b/_sources/guide/first-steps.rst.txt new file mode 100644 index 0000000000..5586db5f5a --- /dev/null +++ b/_sources/guide/first-steps.rst.txt @@ -0,0 +1,65 @@ +.. _first-steps: + +First steps with openFPGALoader +############################### + +Install +======= + +Packages are available for Linux distributions, Windows (MSYS2) and macOS: + +* *Arch Linux*: ``sudo pacman -S openfpgaloader`` + +* *Fedora*: ``sudo dnf copr enable mobicarte/openFPGALoader; sudo dnf install openFPGALoader`` + +* *MSYS2*: ``pacman -S mingw-w64-ucrt-x86_64-openFPGALoader`` + +* *macOS*: ``brew install openfpgaloader`` + +More instructions for other installation scenarios are available in :ref:`install`. + +Programming a development board +=============================== + +Just simply replace ``my_fpga_board`` with any FPGA board from :ref:`compatibility:boards` +(or ``openFPGALoader --list-boards``) in any of the two commands below, depending on if you want to program the volatile +part of your FPGA (faster but not persistent) or the flash part of your FPGA (slower but persistent): + +.. code-block:: bash + + openFPGALoader -b my_fpga_board my_bitstream.bit # Program to SRAM + openFPGALoader -b my_fpga_board -f my_bitstream.bit # Program to flash + +.. NOTE:: + When a bitstream file is compatible with both memory load and FLASH write, the default behavior is to load bitstream + in memory. + +Programming an "standalone" FPGA +================================ + +If your FPGA doesn't come with a built-in programmer or if you prefer to use an external cable, you can specify a cable +to use from :ref:`compatibility:cables` (or ``openFPGALoader --list-cables``): + +.. code-block:: bash + + openFPGALoader -c my_cable my_bitstream.bit # Program to SRAM + openFPGALoader -c my_cable -f my_bitstream.bit # Program to flash + +.. NOTE:: + For some cable (like digilent adapters) signals from the converter are not just directly to the FPGA. + For this case, the ``-c`` must be added. + +.. HINT:: + FTDI/FTDI-compatible cable users: the ``-d`` option lets you specify a specific FTDI device: + + .. code-block:: bash + + openFPGALoader -d /dev/ttyUSBX + + When the ``-d`` option is not provided, openFPGALoader will opens the first FTDI adapter it finds. + Therefore it is preferable to use this flag if your computer is connected to multiple FTDI devices. + +Troubleshooting +=============== + +Please refer to :ref:`troubleshooting`. diff --git a/_sources/guide/install.rst.txt b/_sources/guide/install.rst.txt new file mode 100644 index 0000000000..4d204461e1 --- /dev/null +++ b/_sources/guide/install.rst.txt @@ -0,0 +1,181 @@ +.. _install: + +Installing openFPGALoader +######################### + +Linux +===== + +Arch Linux +---------- + +openFPGALoader is available in the default repositories: + +.. code-block:: bash + + sudo pacman -S openfpgaloader + +Alternatively, you could build from source. First: install required libraries: + +.. code-block:: bash + + sudo pacman -S git cmake make gcc pkgconf libftdi libusb zlib hidapi gzip + +Build step is similar as Debian + +Fedora +------ + +openFPGALoader is available as a Copr repository: + +.. code-block:: bash + + sudo dnf copr enable mobicarte/openFPGALoader + sudo dnf install openFPGALoader + +From source (Debian, Ubuntu) +---------------------------- + +This application uses ``libftdi1``, so this library must be installed (and, depending on the distribution, headers too): + +.. code-block:: bash + + sudo apt install \ + git \ + gzip \ + libftdi1-2 \ + libftdi1-dev \ + libhidapi-hidraw0 \ + libhidapi-dev \ + libudev-dev \ + zlib1g-dev \ + cmake \ + pkg-config \ + make \ + g++ + +.. HINT:: + ``libudev-dev`` is optional, may be replaced by ``eudev-dev`` or just not installed. + +By default, ``(e)udev`` support is enabled (used to open a device by his ``/dev/xx`` node). +If you don't want this option, use: + +.. code-block:: bash + + -DENABLE_UDEV=OFF + +By default, ``cmsisdap`` support is enabled (used for colorlight I5, I9). +If you don't want this option, use: + +.. code-block:: bash + + -DENABLE_CMSISDAP=OFF + +Alternatively you can manually specify the location of ``libusb`` and ``libftdi1``: + +.. code-block:: bash + + -DUSE_PKGCONFIG=OFF \ + -DLIBUSB_LIBRARIES= \ + -DLIBFTDI_LIBRARIES= \ + -DLIBFTDI_VERSION= \ + -DCMAKE_CXX_FLAGS="-I -I" + +You may also need to add this if you see link errors between ``libusb`` and ``pthread``: + +.. code-block:: bash + + -DLINK_CMAKE_THREADS=ON + +By default, ``libgpiod`` support is enabled +If you don't want this option, use: + +.. code-block:: bash + + -DENABLE_LIBGPIOD=OFF + +Additionaly you have to install ``libgpiod`` + +To build the app: + +.. code-block:: bash + + git clone https://github.com/trabucayre/openFPGALoader + cd openFPGALoader + mkdir build + cd build + cmake .. # add -DBUILD_STATIC=ON to build a static version + # add -DENABLE_UDEV=OFF to disable udev support and -d /dev/xxx + # add -DENABLE_CMSISDAP=OFF to disable CMSIS DAP support + cmake --build . + # or + make -j$(nproc) + +To install + +.. code-block:: bash + + $ sudo make install + +The default install path is ``/usr/local``, to change it, use ``-DCMAKE_INSTALL_PREFIX=myInstallDir`` in cmake invokation. + +Udev rules +---------- + +By default, users have no access to converters. +A rule file (:ghsrc:`99-openfpgaloader.rules <99-openfpgaloader.rules>`) for ``udev`` is provided at the root directory +of this repository. +These rules set access right and group (``plugdev``) when a converter is plugged. + +.. code-block:: bash + + sudo cp 99-openfpgaloader.rules /etc/udev/rules.d/ + sudo udevadm control --reload-rules && sudo udevadm trigger # force udev to take new rule + sudo usermod -a $USER -G plugdev # add user to plugdev group + +After that you need to unplug and replug your device. + +.. HINT:: + ``usermod`` is used to add ``$USER`` as a member of ``plugdev`` group. + However this update is not taken into account immediately: it's required to + logout from current session and login again. + Check, by using ``id $USER``, if ``plugdev`` is mentioned after ``groups=``. + An alternate (and temporary) solution is to use ``sudo - $USER`` to have + your user seen as a member of ``plugdev`` group (works only for the current terminal). + +macOS +===== + +openFPGALoader is available as a `Homebrew `__ formula: + +.. code-block:: bash + + brew install openfpgaloader + +Alternatively, if you want to build it by hand: + +.. code-block:: bash + + brew install --only-dependencies openfpgaloader + brew install cmake pkg-config zlib gzip + git clone https://github.com/trabucayre/openFPGALoader + cd openFPGALoader + mkdir build + cd build + cmake .. + make -j + +Windows +======= + +Common +====== + +Bitstreams for *XC2C (coolrunner-II)* needs to be remapped using ``.map`` shipped with *ISE*. +*ISE* path is set at configure time using: + +.. code-block:: bash + + -DISE_PATH=/somewhere/Xilinx/ISE_VERS/ + +default: ``/opt/Xilinx/14.7``. diff --git a/_sources/guide/troubleshooting.rst.txt b/_sources/guide/troubleshooting.rst.txt new file mode 100644 index 0000000000..10767b15f0 --- /dev/null +++ b/_sources/guide/troubleshooting.rst.txt @@ -0,0 +1,45 @@ +.. _troubleshooting: + +Troubleshooting +############### + +I installed openFPGALoader but it says `command not found` when I try to launch it +================================================================================== + +The correct spelling of the program is *openFPGALoader* with FPGA and the "L" of "Loader" in uppercase. +Ensure the spelling of the program is correct. + +Gowin device could not communicate since last bitstream flashed. (issue `#206 `_) +========================================================================================================================================== + +Gowin's FPGA may fails to be detected if **JTAGSEL_N** (pin 08 for *GW1N-4K*) is used as a GPIO. +To recover you have to pull down this pin (before power up) to recover JTAG interface (*UG292 - JTAGSELL_N section*). + +JTAG init failed +================ + +Avoid using USB hubs and connect it directly to your PC USB port. + + +Tang Primer 20k program slow and stucked (issue `#250 `_) +================================================================================================================== + +Check your openFPGALoader version: + +.. code:: bash + + openFPGALoader -V + +If it is older than release then v0.9.0, install the most recent version (from commit `f5b89bff68a5e2147404a895c075773884077438 `_ or later). + +Cannot flash Tang Nano 9k (issue `#251 `_) +=================================================================================================== + +This is a device issue, erase its Embedded Flash using Official GoWin Programmer (preferentially in Windows) and SRAM too, then you can use openFPGALoader again. + +Unable to open FTDI device: -4 (usb_open() failed) (issue `#245 `_) +============================================================================================================================ + +Edit your `/etc/udev/rules.d/99-ftdi.rules` file exchanging your programming device permissions. + +For more information, check the udev section from `this guide `_ \ No newline at end of file diff --git a/_sources/index.rst.txt b/_sources/index.rst.txt new file mode 100644 index 0000000000..7a937231d0 --- /dev/null +++ b/_sources/index.rst.txt @@ -0,0 +1,59 @@ +openFPGALoader: universal utility for programming FPGA +###################################################### + +Welcome to the documentation of openFPGALoader! + +openFPGALoader is a universal utility for programming FPGAs. +Compatible with many boards, cables and FPGA from major manufacturers (Xilinx, Altera/Intel, Lattice, Gowin, Efinix, Anlogic, Cologne Chip). +openFPGALoader works on Linux, Windows and macOS. + +Not sure if your hardware is supported? Check the hardware compatibility lists: + +* :ref:`compatibility:fpgas` +* :ref:`compatibility:boards` +* :ref:`compatibility:cables` + +Also checkout the vendor-specific documentation: + +* `Anlogic `__ +* `Cologne Chip `__ +* `Efinix `__ +* `Gowin `__ +* `Intel/Altera `__ +* `Lattice `__ +* `Xilinx `__ + +.. toctree:: + :caption: User Guide + :hidden: + + guide/first-steps + guide/install + guide/troubleshooting + guide/advanced + +.. toctree:: + :caption: Compatibility + :hidden: + + compatibility/fpga + compatibility/board + compatibility/cable + +.. toctree:: + :caption: Vendors + :hidden: + + vendors/anlogic + vendors/colognechip + vendors/efinix + vendors/gowin + vendors/intel + vendors/lattice + vendors/xilinx + +.. toctree:: + :caption: Development + :hidden: + + todo diff --git a/_sources/todo.rst.txt b/_sources/todo.rst.txt new file mode 100644 index 0000000000..ea81bb95d9 --- /dev/null +++ b/_sources/todo.rst.txt @@ -0,0 +1,31 @@ +.. _todo: + +To Do +##### + +Global +====== + +* improve error message (be more precise) +* catch all exception +* documentation (code + API) + +Cable +===== + +* fix *ch552* (*Sipeed tangNano*): works with *SRAM*, fails with *Flash* +* *busblaster* support +* *anlogic* cable support + +Devices/boards +============== + +* improve frequency configuration. Use FPGA, cable or --freq args maximum frequency +* rework *cyclone10* eeprom access to avoid using FT2232 interfaceB Spi emulation (only supported by trenz board) +* fix checksum computation with *gowin GW2A* +* add support for *tangPrimer* (*anlogic EG4S20*) + +Misc +==== + +* fix spiFlash class to be able to write everywhere (currently offset is hardcoded to 0) diff --git a/_sources/vendors/anlogic.rst.txt b/_sources/vendors/anlogic.rst.txt new file mode 100644 index 0000000000..99eb042e35 --- /dev/null +++ b/_sources/vendors/anlogic.rst.txt @@ -0,0 +1,53 @@ +.. _anlogic: + +Anlogic notes +############# + +Sipeed Lichee Tang +================== + +For this target, *openFPGALoader* supports *svf* and *bit*. + +bit file load (memory) +---------------------- + +.. code-block:: bash + + openFPGALoader -m -b licheeTang /somewhere/project/prj/*.bit + +Since ``-m`` is the default, this argument is optional. + +bit file load (spi flash) +------------------------- + +.. code-block:: bash + + openFPGALoader -f -b licheeTang /somewhere/project/prj/*.bit + +svf file load +------------- + +It's possible to produce this file by using *TD*: + +* Tools->Device Chain +* Add your bit file +* Option : Create svf + +or by using `prjtang project `__: + +.. code-block:: bash + + mkdir build + cd build + cmake ../ + make + +Now a file called *tangbit* is present in current directory and has to be used as follows: + +.. code-block:: bash + + tangbit --input /somewhere.bit --svf bitstream.svf + +.. code-block:: bash + + openFPGALoader -b licheeTang /somewhere/*.svf diff --git a/_sources/vendors/colognechip.rst.txt b/_sources/vendors/colognechip.rst.txt new file mode 100644 index 0000000000..19ba453bd9 --- /dev/null +++ b/_sources/vendors/colognechip.rst.txt @@ -0,0 +1,95 @@ +.. _colognechip: + +Cologne Chip notes +################## + +Supported Boards/Cables +======================= + +* GateMate Evaluation Board using board parameters ``-b gatemate_evb_jtag`` or ``-b gatemate_evb_spi`` +* GateMate Programmer using cable parameter ``-c gatemate_pgm`` + +Programming Modes +================= + +Supported configuration files are bitfiles ``*.bit`` and it's ASCII equivalents ``*.cfg``. + +JTAG Configuration +------------------ + +Performs an active hardware reset and writes the configuration into the FPGA latches via JTAG. The configuration mode pins ``CFG_MD[3:0]`` must be set to 0xC (JTAG). + +1. Program using Evaluation Board: + +.. code-block:: bash + + openFPGALoader -b gatemate_evb_jtag .cfg.bit + +2. Program using Programmer Cable: + +.. code-block:: bash + + openFPGALoader -c gatemate_pgm .cfg.bit + +SPI Configuration +----------------- + +Performs an active hardware reset and writes the configuration into the FPGA latches via SPI. The configuration mode pins ``CFG_MD[3:0]`` must be set to 0x4 (SPI passive). + +1. Program using Evaluation Board: + +.. code-block:: bash + + openFPGALoader -b gatemate_evb_spi .cfg.bit + +2. Program using Programmer Cable: + +.. code-block:: bash + + openFPGALoader -b gatemate_pgm_spi .cfg.bit + +JTAG Flash Access +----------------- + +It is possible to access external flashes via the internal JTAG-SPI-bypass. The configuration mode pins ``CFG_MD[3:0]`` must be set to 0xC (JTAG). Note that the FPGA will not start automatically. + +1. Write to flash using Evaluation Board: + +.. code-block:: bash + + openFPGALoader -b gatemate_evb_jtag .cfg.bit + +2. Write to flash using Programmer Cable: + +.. code-block:: bash + + openFPGALoader -c gatemate_pgm -f .cfg.bit + +The `offset` parameter can be used to store data at any point in the flash, e.g.: + +.. code-block:: bash + + openFPGALoader -b gatemate_evb_jtag -o .cfg.bit + +SPI Flash Access +---------------- + +If the programming device and FPGA share the same SPI signals, it is possible to hold the FPGA in reset and write data to the flash. The configuration mode can be set as desired. If the FPGA should start from the external memory after reset, the configuration mode pins ``CFG_MD[3:0]`` set to 0x0 (SPI active). + +1. Write to flash using Evaluation Board: + +.. code-block:: bash + + openFPGALoader -b gatemate_evb_spi -f .cfg.bit + +2. Write to flash using Programmer Cable: + +.. code-block:: bash + + openFPGALoader -b gatemate_pgm_spi -f .cfg.bit + +The `offset` parameter can be used to store data at any point in the flash, e.g.: + +.. code-block:: bash + + openFPGALoader -b gatemate_evb_spi -o .cfg.bit diff --git a/_sources/vendors/efinix.rst.txt b/_sources/vendors/efinix.rst.txt new file mode 100644 index 0000000000..a47115b094 --- /dev/null +++ b/_sources/vendors/efinix.rst.txt @@ -0,0 +1,51 @@ +.. _efinix: + +Efinix notes +############ + +Firant and Xyloni boards (efinix trion T8) +========================================== + +``.hex`` file is the default format generated by *Efinity IDE*, so nothing special must be done to generates this file. + +*openFPGALoader* supports only active mode (SPI) (*JTAG* is WIP). + +hex file load +------------- + +.. code-block:: bash + + openFPGALoader -b fireant /somewhere/project/outflow/*.hex + +or, for xyloni board + +.. code-block:: bash + + openFPGALoader -b xyloni_spi /somewhere/project/outflow/*.hex + +Since openFPGALoader access the flash directly in SPI mode the ``-b fireant``, ``-b xyloni_spi`` is required (no +autodetection possible). + +Trion and Titanium JTAG usage +========================================== + +*openFPGALoader* supports loading to RAM and SPI Flash with JTAG + +Tested with J-Link BASE + +bin file load +------------- + +.. code-block:: bash + + openFPGALoader --cable jlink_base -m /somewhere/project/outflow/*.bin + +hex file flash +------------- + +Example for ti60f225. +NOTE: JTAG chains with more than one device (eg --index-chain) are currently not supported for writing to SPI flash + +.. code-block:: bash + + openFPGALoader --cable jlink_base --fpga-part ti60f225 -f /somewhere/project/outflow/*.hex \ No newline at end of file diff --git a/_sources/vendors/gowin.rst.txt b/_sources/vendors/gowin.rst.txt new file mode 100644 index 0000000000..63f4ac18ce --- /dev/null +++ b/_sources/vendors/gowin.rst.txt @@ -0,0 +1,64 @@ +.. _gowin: + +Gowin notes +########### + +GOWIN GW1N +========== + +.. NOTE:: + + * Trenz TEC0117 + * Sipeed Tang Nano + * Sipeed Tang Nano 4K + * Honeycomb + * RUNBER + +``.fs`` file is the default format generated by *Gowin IDE*, so nothing special must be done to generates this file. + +Since the same file is used for SRAM and Flash a CLI argument is used to specify the destination. + +Flash SRAM +---------- + +with ``-m``: + +.. code-block:: bash + + openFPGALoader -m -b BOARD_NAME impl/pnr/*.fs + +where ``BOARD_NAME`` is: + +* ``tec0117`` +* ``tangnano`` +* ``tangnano1k`` +* ``tangnano4k`` +* ``tangnano9k`` +* ``tangnano20k`` +* ``tangprimer20k`` +* ``runber`` + +Flash +----- + +.. ATTENTION:: + Only with Trenz TEC0117 and runber. + +with ``-f``, file load: + +.. code-block:: bash + + openFPGALoader -f -b BOARD_NAME impl/pnr/*.fs + +where ``BOARD_NAME`` is: + +* ``tec0117`` +* ``runber`` + +It's possible to flash external SPI Flash (connected to MSPI) in bscan mode by using ``--external-flash`` instead of +``-f``. + +.. NOTE:: + + Gowin's FPGA may fails to be detected if **JTAGSEL_N** (pin 08 for *GW1N-4K*) is used as a GPIO. + To recover you have to pull down this pin (before power up) to recover JTAG interface (*UG292 - JTAGSELL_N section*). diff --git a/_sources/vendors/intel.rst.txt b/_sources/vendors/intel.rst.txt new file mode 100644 index 0000000000..d87b997b55 --- /dev/null +++ b/_sources/vendors/intel.rst.txt @@ -0,0 +1,69 @@ +.. _intel: + +Intel notes +########### + +Intel/Altera +============ + +.. NOTE:: + + * CYC1000 + * C10LP-RefKit + * DE0 + * de0nano + +Loading a bitstream +------------------- + +SVF and RBF files are supported. + +``sof`` to ``svf`` generation: + +.. code-block:: bash + + quartus_cpf -c -q 12.0MHz -g 3.3 -n p project_name.sof project_name.svf + +``sof`` to ``rbf`` generation: + +.. code-block:: bash + + quartus_cpf --option=bitstream_compression=off -c project_name.sof project_name.rbf + +.. WARNING:: + As mentioned in ``cyclone`` handbooks, real-time decompression is not supported by FPGA in JTAG mode. + Keep in mind to disable this option. + +file load: + +.. code-block:: bash + + openFPGALoader -b boardname project_name.svf + # or + openFPGALoader -b boardname project_name.rbf + +with ``boardname`` = ``de0``, ``cyc1000``, ``c10lp-refkit``, ``de0nano``, ``de0nanoSoc`` or ``qmtechCycloneV``. + +SPI flash +--------- + +RPD and RBF are supported. + +``sof`` to ``rpd``: + +.. code-block:: bash + + # CYC1000 + quartus_cpf -o auto_create_rpd=on -c -d EPCQ16A -s 10CL025YU256C8G project_name.svf project_name.jic + # C10LP-RefKit + quartus_cpf -o auto_create_rpd=on -c -d EPCQ16A -s 10CL055YU484C8G project_name.svf project_name.jic + +file load: + +.. code-block:: bash + + openFPGALoader -b boardname -r project_name_auto.rpd + # or + openFPGALoader -b boardname -r project_name.rbf + +with ``boardname`` = ``cyc1000``, ``c10lp-refkit``. diff --git a/_sources/vendors/lattice.rst.txt b/_sources/vendors/lattice.rst.txt new file mode 100644 index 0000000000..85c881c50e --- /dev/null +++ b/_sources/vendors/lattice.rst.txt @@ -0,0 +1,104 @@ +.. _lattice: + +Lattice notes +############# + +MachXO2/MachXO3 +=============== + +Flash memory +------------ + +``.jed`` file is the default format generated by *Lattice Diamond*, so nothing special must be done to generates this +file. + +File load: + +.. code-block:: bash + + openFPGALoader [-b yourboard] [--flash-sector CFG0] impl1/*.jed + +where ``yourboard`` may be: + +* ``machX02EVN`` +* ``machX03EVN`` +* ``machXO3SK`` + +and where ``--flash-sector CFG0`` is needed for the MachXO3D Breakout Board. + +``.bit`` may also be used for *machXO2* + +SRAM +---- + +To generates ``.bit`` file *Bitstream file* must be checked under *Exports Files* in *Lattice Diamond* left panel. + +File load: + +.. code-block:: bash + + openFPGALoader [-b yourboard] impl1/*.bit + +where ``yourboard`` may be: + +* ``machX02EVN`` +* ``machX03EVN`` +* ``machXO3SK`` + +iCE40 +===== + +``.bin`` is the default format generated by *nextpnr*, so nothing special must be done. + +Since most ice40 boards uses the same pinout between *FTDI* and *SPI flash* a generic *ice40_generic* board is provided. + +For the specific case of the *iCE40HXXK-EVB* where no onboard programmer is present, please use this: + +============= =============== + FTDI iCE40HXXK-EVB +============= =============== +SI (ADBUS1) Pin 8 +SCK (ADBUS0) Pin 9 +SO (ADBUS2) Pin 7 +CS (ABDUS4) Pin 10 +RST (ADBUS6 Pin 6 +DONE (ADBUS7) Pin 5 +============= =============== + +Bin file load: + +.. code-block:: bash + + openFPGALoader -b ice40_generic /somewhere/*.bin + +Since it's a direct access to the flash (SPI) the ``-b`` option is required. + +ECP5/Crosslink-NX +================= + +SRAM +---- + +.. code-block:: bash + + openFPGALoader [-b yourBoard] [-c yourCable] -m project_name/*.bit + +.. HINT:: + By default, openFPGALoader loads bitstream in memory, so the ``-m`` argument is optional. + +SPI Flash +--------- + +BIT: + +.. code-block:: bash + + openFPGALoader [-b yourBoard] [-c yourCable] -f project_name/*.bit # or *.bin + +MCS: + +To generate ``.mcs`` file *PROM File* must be checked under *Exports Files* in *Lattice Diamond* left panel. + +.. code-block:: bash + + openFPGALoader [-b yourBoard] [-c yourCable] project_name/*.mcs diff --git a/_sources/vendors/xilinx.rst.txt b/_sources/vendors/xilinx.rst.txt new file mode 100644 index 0000000000..82a339211c --- /dev/null +++ b/_sources/vendors/xilinx.rst.txt @@ -0,0 +1,124 @@ +.. _xilinx: + +Xilinx notes +############ + +To simplify further explanations, we consider the project is generated in the current directory. + +.. NOTE:: + 1. Spartan Edge Accelerator Board has only pinheader, so the cable must be provided + + 2. A *JTAG* <-> *SPI* bridge (used to write bitstream in FLASH) is available for some device, see + :ghsrc:`spiOverJtag ` to check if your model is supported. + + 3. Board provides the device/package model, but if the targeted board is not officially supported but the FPGA yes, + you can use ``--fpga-part`` to provide the model. + + 4. With spartan3, the flash is an independent JTAG device. + User has to use ``--index-chain`` to access FPGA (RAM only) or flash (write/read only). + +.. WARNING:: + ``*.bin`` may be loaded in memory or in flash, but this extension is a classic extension for CPU firmware and, by + default, *openFPGALoader* loads file in memory. + Double check ``-m`` / ``-f`` when you want to use a firmware for a softcore (or anything, other than a bitstream) to + write somewhere in the FLASH device). + +``.bit`` file is the default format generated by *vivado*, so nothing special task must be done to generate this +bitstream. + +``.bin`` is not, by default, produced. +To have access to this file you need to configure the tool: + +- GUI: *Tools* -> *Settings* -> *Bitstreams* -> check ``-bin_file``. +- TCL: append your *TCL* file with ``set_property STEPS.WRITE_BITSTREAM.ARGS.BIN_FILE true [get_runs impl_1]``. + +.. WARNING:: + For alchitry board the bitstream must be configured with a buswidth of 1 or 2. + Quad mode can't be used with alchitry's FLASH. + +.. WARNING:: + For boards based on a Zynq (7000 or MPSoC), boot mode must be configured for JTAG (for Zedboard JP7->JP11 must be + to GND). + +Loading a bitstream +=================== + +``.bit`` and ``.bin`` are allowed to be loaded in memory. + +File load: + +.. code-block:: bash + + openFPGALoader [-m] -b arty *.runs/impl_1/*.bit (or *.bin) + +or + +.. code-block:: bash + + openFPGALoader [-m] -b spartanEdgeAccelBoard -c digilent_hs2 *.runs/impl_1/*.bit (or *.bin) + + +SPI flash +--------- + +.. NOTE:: + ``.bit``, ``.bin``, and ``.mcs`` are supported for FLASH. + +``.mcs`` must be generated through Vivado with a tcl script like: + +.. WARNING:: + For boards based on Zynq device (7000 and MPSoC) SPI flash is not accessible through PL. + +.. code-block:: tcl + + set project [lindex $argv 0] + + set bitfile "${project}.runs/impl_1/${project}.bit" + set mcsfile "${project}.runs/impl_1/${project}.mcs" + + write_cfgmem -format mcs -interface spix4 -size 16 \ + -loadbit "up 0x0 $bitfile" -loaddata "" \ + -file $mcsfile -force + +.. NOTE:: + ``-interface spix4`` and ``-size 16`` depends on SPI flash capability and size. + +The tcl script is used with: + +.. code-block:: bash + + vivado -nolog -nojournal -mode batch -source script.tcl -tclargs myproject + +File load: + +.. code-block:: bash + + openFPGALoader [--fpga-part xxxx] -f -b arty *.runs/impl_1/*.mcs (or .bit / .bin) + +.. NOTE:: + ``-f`` is required to write bitstream (without them ``.bit`` and ``.bin`` are loaded in memory). + +.. NOTE:: + ``--fpga-part`` is only required if this information is not provided at ``board.hpp`` level or if the board is not + officially supported. + device/package format is something like xc7a35tcsg324 (arty model). + See :ghsrc:`src/board.hpp `, or :ghsrc:`spiOverJtag ` directory for examples. + +Some boards with UltraScale FPGAs, like the VCU118 and KCU16, support the SPIx8 (Dual Quad SPI) configuration. +In this case, the ``spix8`` option ``write_cfgmem`` on the above example can be used to generate two ``.mcs`` files, +to fit bigger designs or for faster programming. Only ``.mcs`` files can be used to program the FPGA in this case. + +In this case, to load the two ``.mcs`` files: + +.. code-block:: bash + + openFPGALoader --board vcu118 -f --target-flash both --bitstream *.runs/impl_1/*_primary.mcs --secondary-bitstream *.runs/impl_1/*_secondary.mcs + +On these boards, each SPI flash can be programmed independently with the ``--target-flash`` option. +The default target is the ``primary`` flash. + +For example, to program only the secondary flash with arbitrary data not related to FPGA configuration: + +.. code-block:: bash + + openFPGALoader --board vcu118 -f --target-flash secondary --bitstream arbitrary_data diff --git a/_static/basic.css b/_static/basic.css new file mode 100644 index 0000000000..30fee9d0f7 --- /dev/null +++ b/_static/basic.css @@ -0,0 +1,925 @@ +/* + * basic.css + * ~~~~~~~~~ + * + * Sphinx stylesheet -- basic theme. + * + * :copyright: Copyright 2007-2023 by the Sphinx team, see AUTHORS. + * :license: BSD, see LICENSE for details. + * + */ + +/* -- main layout ----------------------------------------------------------- */ + +div.clearer { + clear: both; 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// [C]VC[V] is m=1 + var mgr1 = "^(" + C + ")?" + V + C + V + C; // [C]VCVC... is m>1 + var s_v = "^(" + C + ")?" + v; // vowel in stem + + this.stemWord = function (w) { + var stem; + var suffix; + var firstch; + var origword = w; + + if (w.length < 3) + return w; + + var re; + var re2; + var re3; + var re4; + + firstch = w.substr(0,1); + if (firstch == "y") + w = firstch.toUpperCase() + w.substr(1); + + // Step 1a + re = /^(.+?)(ss|i)es$/; + re2 = /^(.+?)([^s])s$/; + + if (re.test(w)) + w = w.replace(re,"$1$2"); + else if (re2.test(w)) + w = w.replace(re2,"$1$2"); + + // Step 1b + re = /^(.+?)eed$/; + re2 = /^(.+?)(ed|ing)$/; + if (re.test(w)) { + var fp = re.exec(w); + re = new RegExp(mgr0); + if (re.test(fp[1])) { + re = /.$/; + w = w.replace(re,""); + } + } + else if (re2.test(w)) { + var fp = re2.exec(w); + stem = fp[1]; + re2 = new RegExp(s_v); + if (re2.test(stem)) { + w = stem; + re2 = /(at|bl|iz)$/; + re3 = new RegExp("([^aeiouylsz])\\1$"); + re4 = new RegExp("^" + C + v + "[^aeiouwxy]$"); + if (re2.test(w)) + w = w + "e"; + else if (re3.test(w)) { + re = /.$/; + w = w.replace(re,""); + } + else if (re4.test(w)) + w = w + "e"; + } + } + + // Step 1c + re = /^(.+?)y$/; + if (re.test(w)) { + var fp = re.exec(w); + stem = fp[1]; + re = new RegExp(s_v); + if (re.test(stem)) + w = stem + "i"; + } + + // Step 2 + re = /^(.+?)(ational|tional|enci|anci|izer|bli|alli|entli|eli|ousli|ization|ation|ator|alism|iveness|fulness|ousness|aliti|iviti|biliti|logi)$/; + if (re.test(w)) { + var fp = re.exec(w); + stem = fp[1]; + suffix = fp[2]; + re = new RegExp(mgr0); + if (re.test(stem)) + w = stem + step2list[suffix]; + } + + // Step 3 + re = /^(.+?)(icate|ative|alize|iciti|ical|ful|ness)$/; + if (re.test(w)) { + var fp = re.exec(w); + stem = fp[1]; + suffix = fp[2]; + re = new RegExp(mgr0); + if (re.test(stem)) + w = stem + step3list[suffix]; + } + + // Step 4 + re = /^(.+?)(al|ance|ence|er|ic|able|ible|ant|ement|ment|ent|ou|ism|ate|iti|ous|ive|ize)$/; + re2 = /^(.+?)(s|t)(ion)$/; + if (re.test(w)) { + var fp = re.exec(w); + stem = fp[1]; + re = new RegExp(mgr1); + if (re.test(stem)) + w = stem; + } + else if (re2.test(w)) { + var fp = re2.exec(w); + stem = fp[1] + fp[2]; + re2 = new RegExp(mgr1); + if (re2.test(stem)) + w = stem; + } + + // Step 5 + re = /^(.+?)e$/; + if (re.test(w)) { + var fp = re.exec(w); + stem = fp[1]; + re = new RegExp(mgr1); + re2 = new RegExp(meq1); + re3 = new RegExp("^" + C + v + "[^aeiouwxy]$"); + if (re.test(stem) || (re2.test(stem) && !(re3.test(stem)))) + w = stem; + } + re = /ll$/; + re2 = new RegExp(mgr1); + if (re.test(w) && re2.test(w)) { + re = /.$/; + w = w.replace(re,""); + } + + // and turn initial Y back to y + if (firstch == "y") + w = firstch.toLowerCase() + w.substr(1); + return w; + } +} + diff --git a/_static/minus.png b/_static/minus.png new file mode 100644 index 0000000000..d96755fdaf Binary files /dev/null and b/_static/minus.png differ diff --git a/_static/plus.png b/_static/plus.png new file mode 100644 index 0000000000..7107cec93a Binary files /dev/null and b/_static/plus.png differ diff --git a/_static/pygments.css b/_static/pygments.css new file mode 100644 index 0000000000..6bae782c52 --- /dev/null +++ b/_static/pygments.css @@ -0,0 +1,85 @@ +pre { line-height: 125%; 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+} + +const _removeChildren = (element) => { + while (element && element.lastChild) element.removeChild(element.lastChild); +}; + +/** + * See https://developer.mozilla.org/en-US/docs/Web/JavaScript/Guide/Regular_Expressions#escaping + */ +const _escapeRegExp = (string) => + string.replace(/[.*+\-?^${}()|[\]\\]/g, "\\$&"); // $& means the whole matched string + +const _displayItem = (item, searchTerms, highlightTerms) => { + const docBuilder = DOCUMENTATION_OPTIONS.BUILDER; + const docFileSuffix = DOCUMENTATION_OPTIONS.FILE_SUFFIX; + const docLinkSuffix = DOCUMENTATION_OPTIONS.LINK_SUFFIX; + const showSearchSummary = DOCUMENTATION_OPTIONS.SHOW_SEARCH_SUMMARY; + const contentRoot = document.documentElement.dataset.content_root; + + const [docName, title, anchor, descr, score, _filename] = item; + + let listItem = document.createElement("li"); + let requestUrl; + let linkUrl; + if (docBuilder === "dirhtml") { + // dirhtml builder + let dirname = docName + "/"; + if (dirname.match(/\/index\/$/)) + dirname = dirname.substring(0, dirname.length - 6); + else if (dirname === "index/") dirname = ""; + requestUrl = contentRoot + dirname; + linkUrl = requestUrl; + } else { + // normal html builders + requestUrl = contentRoot + docName + docFileSuffix; + linkUrl = docName + docLinkSuffix; + } + let linkEl = listItem.appendChild(document.createElement("a")); + linkEl.href = linkUrl + anchor; + linkEl.dataset.score = score; + linkEl.innerHTML = title; + if (descr) { + listItem.appendChild(document.createElement("span")).innerHTML = + " (" + descr + ")"; + // highlight search terms in the description + if (SPHINX_HIGHLIGHT_ENABLED) // set in sphinx_highlight.js + highlightTerms.forEach((term) => _highlightText(listItem, term, "highlighted")); + } + else if (showSearchSummary) + fetch(requestUrl) + .then((responseData) => responseData.text()) + .then((data) => { + if (data) + listItem.appendChild( + Search.makeSearchSummary(data, searchTerms) + ); + // highlight search terms in the summary + if (SPHINX_HIGHLIGHT_ENABLED) // set in sphinx_highlight.js + highlightTerms.forEach((term) => _highlightText(listItem, term, "highlighted")); + }); + Search.output.appendChild(listItem); +}; +const _finishSearch = (resultCount) => { + Search.stopPulse(); + Search.title.innerText = _("Search Results"); + if (!resultCount) + Search.status.innerText = Documentation.gettext( + "Your search did not match any documents. Please make sure that all words are spelled correctly and that you've selected enough categories." + ); + else + Search.status.innerText = _( + `Search finished, found ${resultCount} page(s) matching the search query.` + ); +}; +const _displayNextItem = ( + results, + resultCount, + searchTerms, + highlightTerms, +) => { + // results left, load the summary and display it + // this is intended to be dynamic (don't sub resultsCount) + if (results.length) { + _displayItem(results.pop(), searchTerms, highlightTerms); + setTimeout( + () => _displayNextItem(results, resultCount, searchTerms, highlightTerms), + 5 + ); + } + // search finished, update title and status message + else _finishSearch(resultCount); +}; + +/** + * Default splitQuery function. Can be overridden in ``sphinx.search`` with a + * custom function per language. + * + * The regular expression works by splitting the string on consecutive characters + * that are not Unicode letters, numbers, underscores, or emoji characters. + * This is the same as ``\W+`` in Python, preserving the surrogate pair area. + */ +if (typeof splitQuery === "undefined") { + var splitQuery = (query) => query + .split(/[^\p{Letter}\p{Number}_\p{Emoji_Presentation}]+/gu) + .filter(term => term) // remove remaining empty strings +} + +/** + * Search Module + */ +const Search = { + _index: null, + _queued_query: null, + _pulse_status: -1, + + htmlToText: (htmlString) => { + const htmlElement = new DOMParser().parseFromString(htmlString, 'text/html'); + htmlElement.querySelectorAll(".headerlink").forEach((el) => { el.remove() }); + const docContent = htmlElement.querySelector('[role="main"]'); + if (docContent !== undefined) return docContent.textContent; + console.warn( + "Content block not found. Sphinx search tries to obtain it via '[role=main]'. Could you check your theme or template." + ); + return ""; + }, + + init: () => { + const query = new URLSearchParams(window.location.search).get("q"); + document + .querySelectorAll('input[name="q"]') + .forEach((el) => (el.value = query)); + if (query) Search.performSearch(query); + }, + + loadIndex: (url) => + (document.body.appendChild(document.createElement("script")).src = url), + + setIndex: (index) => { + Search._index = index; + if (Search._queued_query !== null) { + const query = Search._queued_query; + Search._queued_query = null; + Search.query(query); + } + }, + + hasIndex: () => Search._index !== null, + + deferQuery: (query) => (Search._queued_query = query), + + stopPulse: () => (Search._pulse_status = -1), + + startPulse: () => { + if (Search._pulse_status >= 0) return; + + const pulse = () => { + Search._pulse_status = (Search._pulse_status + 1) % 4; + Search.dots.innerText = ".".repeat(Search._pulse_status); + if (Search._pulse_status >= 0) window.setTimeout(pulse, 500); + }; + pulse(); + }, + + /** + * perform a search for something (or wait until index is loaded) + */ + performSearch: (query) => { + // create the required interface elements + const searchText = document.createElement("h2"); + searchText.textContent = _("Searching"); + const searchSummary = document.createElement("p"); + searchSummary.classList.add("search-summary"); + searchSummary.innerText = ""; + const searchList = document.createElement("ul"); + searchList.classList.add("search"); + + const out = document.getElementById("search-results"); + Search.title = out.appendChild(searchText); + Search.dots = Search.title.appendChild(document.createElement("span")); + Search.status = out.appendChild(searchSummary); + Search.output = out.appendChild(searchList); + + const searchProgress = document.getElementById("search-progress"); + // Some themes don't use the search progress node + if (searchProgress) { + searchProgress.innerText = _("Preparing search..."); + } + Search.startPulse(); + + // index already loaded, the browser was quick! + if (Search.hasIndex()) Search.query(query); + else Search.deferQuery(query); + }, + + /** + * execute search (requires search index to be loaded) + */ + query: (query) => { + const filenames = Search._index.filenames; + const docNames = Search._index.docnames; + const titles = Search._index.titles; + const allTitles = Search._index.alltitles; + const indexEntries = Search._index.indexentries; + + // stem the search terms and add them to the correct list + const stemmer = new Stemmer(); + const searchTerms = new Set(); + const excludedTerms = new Set(); + const highlightTerms = new Set(); + const objectTerms = new Set(splitQuery(query.toLowerCase().trim())); + splitQuery(query.trim()).forEach((queryTerm) => { + const queryTermLower = queryTerm.toLowerCase(); + + // maybe skip this "word" + // stopwords array is from language_data.js + if ( + stopwords.indexOf(queryTermLower) !== -1 || + queryTerm.match(/^\d+$/) + ) + return; + + // stem the word + let word = stemmer.stemWord(queryTermLower); + // select the correct list + if (word[0] === "-") excludedTerms.add(word.substr(1)); + else { + searchTerms.add(word); + highlightTerms.add(queryTermLower); + } + }); + + if (SPHINX_HIGHLIGHT_ENABLED) { // set in sphinx_highlight.js + localStorage.setItem("sphinx_highlight_terms", [...highlightTerms].join(" ")) + } + + // console.debug("SEARCH: searching for:"); + // console.info("required: ", [...searchTerms]); + // console.info("excluded: ", [...excludedTerms]); + + // array of [docname, title, anchor, descr, score, filename] + let results = []; + _removeChildren(document.getElementById("search-progress")); + + const queryLower = query.toLowerCase(); + for (const [title, foundTitles] of Object.entries(allTitles)) { + if (title.toLowerCase().includes(queryLower) && (queryLower.length >= title.length/2)) { + for (const [file, id] of foundTitles) { + let score = Math.round(100 * queryLower.length / title.length) + results.push([ + docNames[file], + titles[file] !== title ? `${titles[file]} > ${title}` : title, + id !== null ? "#" + id : "", + null, + score, + filenames[file], + ]); + } + } + } + + // search for explicit entries in index directives + for (const [entry, foundEntries] of Object.entries(indexEntries)) { + if (entry.includes(queryLower) && (queryLower.length >= entry.length/2)) { + for (const [file, id] of foundEntries) { + let score = Math.round(100 * queryLower.length / entry.length) + results.push([ + docNames[file], + titles[file], + id ? "#" + id : "", + null, + score, + filenames[file], + ]); + } + } + } + + // lookup as object + objectTerms.forEach((term) => + results.push(...Search.performObjectSearch(term, objectTerms)) + ); + + // lookup as search terms in fulltext + results.push(...Search.performTermsSearch(searchTerms, excludedTerms)); + + // let the scorer override scores with a custom scoring function + if (Scorer.score) results.forEach((item) => (item[4] = Scorer.score(item))); + + // now sort the results by score (in opposite order of appearance, since the + // display function below uses pop() to retrieve items) and then + // alphabetically + results.sort((a, b) => { + const leftScore = a[4]; + const rightScore = b[4]; + if (leftScore === rightScore) { + // same score: sort alphabetically + const leftTitle = a[1].toLowerCase(); + const rightTitle = b[1].toLowerCase(); + if (leftTitle === rightTitle) return 0; + return leftTitle > rightTitle ? -1 : 1; // inverted is intentional + } + return leftScore > rightScore ? 1 : -1; + }); + + // remove duplicate search results + // note the reversing of results, so that in the case of duplicates, the highest-scoring entry is kept + let seen = new Set(); + results = results.reverse().reduce((acc, result) => { + let resultStr = result.slice(0, 4).concat([result[5]]).map(v => String(v)).join(','); + if (!seen.has(resultStr)) { + acc.push(result); + seen.add(resultStr); + } + return acc; + }, []); + + results = results.reverse(); + + // for debugging + //Search.lastresults = results.slice(); // a copy + // console.info("search results:", Search.lastresults); + + // print the results + _displayNextItem(results, results.length, searchTerms, highlightTerms); + }, + + /** + * search for object names + */ + performObjectSearch: (object, objectTerms) => { + const filenames = Search._index.filenames; + const docNames = Search._index.docnames; + const objects = Search._index.objects; + const objNames = Search._index.objnames; + const titles = Search._index.titles; + + const results = []; + + const objectSearchCallback = (prefix, match) => { + const name = match[4] + const fullname = (prefix ? prefix + "." : "") + name; + const fullnameLower = fullname.toLowerCase(); + if (fullnameLower.indexOf(object) < 0) return; + + let score = 0; + const parts = fullnameLower.split("."); + + // check for different match types: exact matches of full name or + // "last name" (i.e. last dotted part) + if (fullnameLower === object || parts.slice(-1)[0] === object) + score += Scorer.objNameMatch; + else if (parts.slice(-1)[0].indexOf(object) > -1) + score += Scorer.objPartialMatch; // matches in last name + + const objName = objNames[match[1]][2]; + const title = titles[match[0]]; + + // If more than one term searched for, we require other words to be + // found in the name/title/description + const otherTerms = new Set(objectTerms); + otherTerms.delete(object); + if (otherTerms.size > 0) { + const haystack = `${prefix} ${name} ${objName} ${title}`.toLowerCase(); + if ( + [...otherTerms].some((otherTerm) => haystack.indexOf(otherTerm) < 0) + ) + return; + } + + let anchor = match[3]; + if (anchor === "") anchor = fullname; + else if (anchor === "-") anchor = objNames[match[1]][1] + "-" + fullname; + + const descr = objName + _(", in ") + title; + + // add custom score for some objects according to scorer + if (Scorer.objPrio.hasOwnProperty(match[2])) + score += Scorer.objPrio[match[2]]; + else score += Scorer.objPrioDefault; + + results.push([ + docNames[match[0]], + fullname, + "#" + anchor, + descr, + score, + filenames[match[0]], + ]); + }; + Object.keys(objects).forEach((prefix) => + objects[prefix].forEach((array) => + objectSearchCallback(prefix, array) + ) + ); + return results; + }, + + /** + * search for full-text terms in the index + */ + performTermsSearch: (searchTerms, excludedTerms) => { + // prepare search + const terms = Search._index.terms; + const titleTerms = Search._index.titleterms; + const filenames = Search._index.filenames; + const docNames = Search._index.docnames; + const titles = Search._index.titles; + + const scoreMap = new Map(); + const fileMap = new Map(); + + // perform the search on the required terms + searchTerms.forEach((word) => { + const files = []; + const arr = [ + { files: terms[word], score: Scorer.term }, + { files: titleTerms[word], score: Scorer.title }, + ]; + // add support for partial matches + if (word.length > 2) { + const escapedWord = _escapeRegExp(word); + Object.keys(terms).forEach((term) => { + if (term.match(escapedWord) && !terms[word]) + arr.push({ files: terms[term], score: Scorer.partialTerm }); + }); + Object.keys(titleTerms).forEach((term) => { + if (term.match(escapedWord) && !titleTerms[word]) + arr.push({ files: titleTerms[word], score: Scorer.partialTitle }); + }); + } + + // no match but word was a required one + if (arr.every((record) => record.files === undefined)) return; + + // found search word in contents + arr.forEach((record) => { + if (record.files === undefined) return; + + let recordFiles = record.files; + if (recordFiles.length === undefined) recordFiles = [recordFiles]; + files.push(...recordFiles); + + // set score for the word in each file + recordFiles.forEach((file) => { + if (!scoreMap.has(file)) scoreMap.set(file, {}); + scoreMap.get(file)[word] = record.score; + }); + }); + + // create the mapping + files.forEach((file) => { + if (fileMap.has(file) && fileMap.get(file).indexOf(word) === -1) + fileMap.get(file).push(word); + else fileMap.set(file, [word]); + }); + }); + + // now check if the files don't contain excluded terms + const results = []; + for (const [file, wordList] of fileMap) { + // check if all requirements are matched + + // as search terms with length < 3 are discarded + const filteredTermCount = [...searchTerms].filter( + (term) => term.length > 2 + ).length; + if ( + wordList.length !== searchTerms.size && + wordList.length !== filteredTermCount + ) + continue; + + // ensure that none of the excluded terms is in the search result + if ( + [...excludedTerms].some( + (term) => + terms[term] === file || + titleTerms[term] === file || + (terms[term] || []).includes(file) || + (titleTerms[term] || []).includes(file) + ) + ) + break; + + // select one (max) score for the file. + const score = Math.max(...wordList.map((w) => scoreMap.get(file)[w])); + // add result to the result list + results.push([ + docNames[file], + titles[file], + "", + null, + score, + filenames[file], + ]); + } + return results; + }, + + /** + * helper function to return a node containing the + * search summary for a given text. keywords is a list + * of stemmed words. + */ + makeSearchSummary: (htmlText, keywords) => { + const text = Search.htmlToText(htmlText); + if (text === "") return null; + + const textLower = text.toLowerCase(); + const actualStartPosition = [...keywords] + .map((k) => textLower.indexOf(k.toLowerCase())) + .filter((i) => i > -1) + .slice(-1)[0]; + const startWithContext = Math.max(actualStartPosition - 120, 0); + + const top = startWithContext === 0 ? "" : "..."; + const tail = startWithContext + 240 < text.length ? "..." : ""; + + let summary = document.createElement("p"); + summary.classList.add("context"); + summary.textContent = top + text.substr(startWithContext, 240).trim() + tail; + + return summary; + }, +}; + +_ready(Search.init); diff --git a/_static/sphinx_highlight.js b/_static/sphinx_highlight.js new file mode 100644 index 0000000000..8a96c69a19 --- /dev/null +++ b/_static/sphinx_highlight.js @@ -0,0 +1,154 @@ +/* Highlighting utilities for Sphinx HTML documentation. */ +"use strict"; + +const SPHINX_HIGHLIGHT_ENABLED = true + +/** + * highlight a given string on a node by wrapping it in + * span elements with the given class name. + */ +const _highlight = (node, addItems, text, className) => { + if (node.nodeType === Node.TEXT_NODE) { + const val = node.nodeValue; + const parent = node.parentNode; + const pos = val.toLowerCase().indexOf(text); + if ( + pos >= 0 && + !parent.classList.contains(className) && + !parent.classList.contains("nohighlight") + ) { + let span; + + const closestNode = parent.closest("body, svg, foreignObject"); + const isInSVG = closestNode && closestNode.matches("svg"); + if (isInSVG) { + span = document.createElementNS("http://www.w3.org/2000/svg", "tspan"); + } else { + span = document.createElement("span"); + span.classList.add(className); + } + + span.appendChild(document.createTextNode(val.substr(pos, text.length))); + const rest = document.createTextNode(val.substr(pos + text.length)); + parent.insertBefore( + span, + parent.insertBefore( + rest, + node.nextSibling + ) + ); + node.nodeValue = val.substr(0, pos); + /* There may be more occurrences of search term in this node. So call this + * function recursively on the remaining fragment. + */ + _highlight(rest, addItems, text, className); + + if (isInSVG) { + const rect = document.createElementNS( + "http://www.w3.org/2000/svg", + "rect" + ); + const bbox = parent.getBBox(); + rect.x.baseVal.value = bbox.x; + rect.y.baseVal.value = bbox.y; + rect.width.baseVal.value = bbox.width; + rect.height.baseVal.value = bbox.height; + rect.setAttribute("class", className); + addItems.push({ parent: parent, target: rect }); + } + } + } else if (node.matches && !node.matches("button, select, textarea")) { + node.childNodes.forEach((el) => _highlight(el, addItems, text, className)); + } +}; +const _highlightText = (thisNode, text, className) => { + let addItems = []; + _highlight(thisNode, addItems, text, className); + addItems.forEach((obj) => + obj.parent.insertAdjacentElement("beforebegin", obj.target) + ); +}; + +/** + * Small JavaScript module for the documentation. + */ +const SphinxHighlight = { + + /** + * highlight the search words provided in localstorage in the text + */ + highlightSearchWords: () => { + if (!SPHINX_HIGHLIGHT_ENABLED) return; // bail if no highlight + + // get and clear terms from localstorage + const url = new URL(window.location); + const highlight = + localStorage.getItem("sphinx_highlight_terms") + || url.searchParams.get("highlight") + || ""; + localStorage.removeItem("sphinx_highlight_terms") + url.searchParams.delete("highlight"); + window.history.replaceState({}, "", url); + + // get individual terms from highlight string + const terms = highlight.toLowerCase().split(/\s+/).filter(x => x); + if (terms.length === 0) return; // nothing to do + + // There should never be more than one element matching "div.body" + const divBody = document.querySelectorAll("div.body"); + const body = divBody.length ? divBody[0] : document.querySelector("body"); + window.setTimeout(() => { + terms.forEach((term) => _highlightText(body, term, "highlighted")); + }, 10); + + const searchBox = document.getElementById("searchbox"); + if (searchBox === null) return; + searchBox.appendChild( + document + .createRange() + .createContextualFragment( + '

' + + '' + + _("Hide Search Matches") + + "

" + ) + ); + }, + + /** + * helper function to hide the search marks again + */ + hideSearchWords: () => { + document + .querySelectorAll("#searchbox .highlight-link") + .forEach((el) => el.remove()); + document + .querySelectorAll("span.highlighted") + .forEach((el) => el.classList.remove("highlighted")); + localStorage.removeItem("sphinx_highlight_terms") + }, + + initEscapeListener: () => { + // only install a listener if it is really needed + if (!DOCUMENTATION_OPTIONS.ENABLE_SEARCH_SHORTCUTS) return; + + document.addEventListener("keydown", (event) => { + // bail for input elements + if (BLACKLISTED_KEY_CONTROL_ELEMENTS.has(document.activeElement.tagName)) return; + // bail with special keys + if (event.shiftKey || event.altKey || event.ctrlKey || event.metaKey) return; + if (DOCUMENTATION_OPTIONS.ENABLE_SEARCH_SHORTCUTS && (event.key === "Escape")) { + SphinxHighlight.hideSearchWords(); + event.preventDefault(); + } + }); + }, +}; + +_ready(() => { + /* Do not call highlightSearchWords() when we are on the search page. + * It will highlight words from the *previous* search query. + */ + if (typeof Search === "undefined") SphinxHighlight.highlightSearchWords(); + SphinxHighlight.initEscapeListener(); +}); diff --git a/compatibility/board.html b/compatibility/board.html new file mode 100644 index 0000000000..99716ce21c --- /dev/null +++ b/compatibility/board.html @@ -0,0 +1,1068 @@ + + + + + + + Boards — openFPGALoader: universal utility for programming FPGA latest documentation + + + + + + + + + + + + + + + +
+ + +
+ +
+
+ + +
+ +
+
+ +
+
+ +
+

Boards

+
+

Note

+

arty can be any of the board names from the first column.

+
+
openFPGALoader -b arty bitstream.bit # Loading in SRAM (volatile)
+openFPGALoader -b arty -f bitstream.bit # Writing in flash (non-volatile)
+
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Board name

Description

FPGA

Memory

Flash

Constraints

ac701

Xilinx Artix-7 FPGA AC701 Evaluation Kit

Artix xc7a200t2fbg676c

OK

NT

AC701 ➚

acornCle215

Acorn CLE 215+

Artix xc7a200tsbg484

OK

OK

litex-acorn-baseboard-mini

The LiteX-Acorn-Baseboards are baseboards developed around the SQRL’s Acorn board (or Nite/LiteFury)

Artix xc7a200tsbg484

OK

OK

alchitry_au

Alchitry Au

Artix xc7a35tftg256

OK

OK

alchitry_au_plus

Alchitry Au+ (Plus)

Artix xc7a100tftg256

OK

OK

alinx_ax516

ALINX AX516

Spartan6 xc6slx16csg324

OK

OK

alinx_ax7101

ALINX AX/7101

Artix xc7a100tfgg484

OK

OK

alinx_ax7102

ALINX AX/7102

Artix xc7a100tfgg484

OK

OK

analogMax

Trenz TEI0010 - AnalogMax

Max 10 10M08SAU169C8G

SVF

SVF

antmicro_ddr4_tester

Antmicro Data Center DRAM Tester

Kintex7 xc7k160t

OK

OK

antmicro_ddr5_tester

Antmicro DDR5 Tester

Kintex7 xc7k160t

OK

OK

antmicro_lpddr4_tester

Antmicro LPDDR4 Test Board

Kintex7 xc7k70t

OK

OK

arty_a7_35t

Digilent Arty A7

Artix xc7a35ticsg324

OK

OK

Arty-A7-35T ➚

arty_a7_100t

Digilent Arty A7

Artix xc7a100tcsg324

OK

OK

Arty-A7-100T ➚

arty_s7_25

Digilent Arty S7

Spartan7 xc7s25csga324

OK

OK

Arty-S7-25 ➚

arty_s7_50

Digilent Arty S7

Spartan7 xc7s50csga324

OK

OK

Arty-S7-50 ➚

arty_z7_10

Digilent Arty S7

Zynq7000 xc7z010csg400

OK

NA

arty_z7_20

Digilent Arty S7

Zynq7000 xc7z020csg400

OK

NA

arty

Digilent Analog Discovery 2

Spartan6 xc6slx25

OK

NT

arty

Digilent Digital Discovery

Spartan6 xc6slx25

OK

NT

axu2cga

Alinx AXU2CGA Zynq MPSoC Dev Board

ZynqMPSoC XCZU2CG

OK

NA

basys3

Digilent Basys3

Artix xc7a35tcpg236

OK

OK

cmod_s7

Digilent Cmod S7

Spartan7 xc7s25csga225

NA

OK

gatemate_evb_jtag

Cologne Chip GateMate FPGA Evaluation Board (JTAG mode)

Cologne Chip GateMate Series

OK

OK

gatemate_evb_spi

Cologne Chip GateMate FPGA Evaluation Board (SPI mode)

Cologne Chip GateMate Series

OK

OK

gatemate_pgm_spi

Cologne Chip GateMate FPGA Programmer (SPI mode)

Cologne Chip GateMate Series

OK

OK

certusnx_versa_evn

Certus-NX Versa Evaluation Board

Certus LFD2NX-40

OK

OK

certuspronx_evn

CertusPro-NX Evaluation Board

CertusPro-NX LFCPNX-100

OK

OK

certuspronx_versa_evn

CertusPro-NX Versa

CertusPro-NX LFCPNX-100

OK

OK

cmoda7_15t

Digilent CmodA7

Artix xc7a15tcpg236

OK

OK

cmoda7_35t

Digilent CmodA7

Artix xc7a35tcpg236

OK

OK

colorlight

Colorlight 5A-75B (version 7)

ECP5 LFE5U-25F-6BG256C

OK

OK

colorlight-i5

Colorlight I5

ECP5 LFE5U-25F-6BG381C

OK

OK

Colorlight-i5-v7.0 ➚

colorlight-i9

Colorlight I9

ECP5 LFE5U-45F-6BG381C

OK

OK

Colorlight-i9-v7.2 ➚

colorlight-i9+

Colorlight I9+

Artix xc7a50tfgg484

OK

OK

crosslinknx_evn

Lattice CrossLink-NX Evaluation Board

Nexus LIFCL-40

OK

OK

cyc1000

Trenz cyc1000

Cyclone 10 LP 10CL025YU256C8G

OK

OK

c10lp-refkit

Trenz c10lp-refkit

Cyclone 10 LP 10CL055YU484C8G

OK

OK

c5g

Terasic C5G (Cyclone V GX Starter Kit)

Cyclone V GX 5CGXFC5C6F27C7N

OK

NT

de0

Terasic DE0

Cyclone III EP3C16F484C6

OK

NT

de0nano

Terasic de0nano

Cyclone IV E EP4CE22F17C6

OK

OK

de0nanoSoc

Terasic de0nanoSoc

Cyclone V SoC 5CSEMA4U23C6

OK

de10lite

Terasic de10lite

MAX 10 10M50DAF484C7G

OK

de10nano

Terasic de10Nano

Cyclone V SoC 5CSEBA6U23I7

OK

de1Soc

Terasic DE1-SoC

Cyclone V SoC 5CSEMA5F31C6

OK

deca

Arrow/Terasic DECA

MAX 10 10M50DAF484C6GES

OK

ecp5_evn

Lattice ECP5 5G Evaluation Board

ECP5G LFE5UM5G-85F

OK

OK

ECP5-EVN ➚

ecpix5

LambdaConcept ECPIX-5 (FT2232)

ECP5 LFE5UM5G-85F

OK

OK

ECPIX-5-45F ➚ ECPIX-5-85F ➚

ecpix5_r03

LambdaConcept ECPIX-5 (FT4232)

ECP5 LFE5UM5G-85F

OK

OK

ECPIX-5-45F ➚ ECPIX-5-85F ➚

fireant

Fireant Trion T8

Trion T8F81

NA

AS

fomu

Fomu PVT

iCE40UltraPlus UP5K

NA

OK

Fomu-PVT ➚

gr740-mini

GR740-MINI

CertusPro-NX LFCPNX-100

OK

NA

honeycomb

honeycomb

littleBee GW1NS-2C

OK

IF

hseda-xc6slx16

XILINX SPARTAN6 XC6SLX16 Microblaze SDRAM USB2.0 FPGA

Spartan6 xc6slx16-ftg256

OK

OK

ice40_generic

iCEBreaker

iCE40UltraPlus UP5K

NA

AS

iCEBreaker ➚

icebreaker-bitsy

iCEBreaker-bitsy

iCE40UltraPlus UP5K

NA

OK

iCEBreaker-bitsy-v0 ➚ iCEBreaker-bitsy-v1 ➚

ice40_generic

icestick

iCE40 HX1k

NA

AS

IceStick ➚

ice40_generic

iCE40-HX8K

iCE40 HX8k

OK

AS

iCE40-HX8K ➚

ice40_generic

Olimex iCE40HX1K-EVB

iCE40 HX1k

NT

AS

iCE40HX1K-EVB ➚

ice40_generic

Olimex iCE40HX8K-EVB

iCE40 HX8k

NT

AS

iCE40HX8K-EVB ➚

ice40_generic

iCE40 UltraPlus Breakout Board (iCE40UP5K-B-EVN)

iCE40-UP5K

NT

AS

iCE40-UP ➚

ice40_generic

Icezum Alhambra II

iCE40 HX4k

NT

AS

IceZumAlhambraII ➚

kc705

Xilinx KC705

Kintex7 xc7k325t

OK

NT

KC705 ➚

kcu105

Xilinx KCU105

Kintex UltraScale xcku040-ffva1156

OK

OK

kcu116

Xilinx KCU116

Kintex UltraScale+ xcku5p-ffvb676

OK

OK

LD-KONFEKT

Lone Dynamics Corporation - Machdyne Konfekt computer

ECP5 LFE5U-12F-6BG256C

OK

OK

LD-SCHOKO

Lone Dynamics Corporation - Machdyne Schoko computer

ECP5 LFE5U-45F-6CABGA256

OK

OK

licheeTang

Sipeed Lichee Tang

eagle s20 EG4S20BG256

OK

OK

machXO2EVN

Lattice MachXO2 Breakout Board Evaluation Kit

MachXO2 LCMXO2-7000HE

OK

OK

machXO3EVN

Lattice MachXO3D Development Board

MachXO3D LCMXO3D-9400HC

OK

NT

machXO3SK

Lattice MachXO3LF Starter Kit

MachXO3 LCMX03LF-6900C

OK

OK

mini_itx

Avnet Mini-ITX Base Kit

AMD Xilinx XC7Z045/XC7Z100-2FFG900

OK

NA

nexys_a7_50

Digilent Nexys A7(Nexys 4 DDR)

Artix xc7a50tcsg324

OK

OK

Nexys4DDR ➚

nexys_a7_100

Digilent Nexys A7(Nexys 4 DDR)

Artix nexys_a7_100

OK

OK

Nexys4DDR ➚

nexysVideo

Digilent Nexys Video

Artix xc7a200tsbg484

OK

OK

xem8320

Opal Kelly XEM8320

Artix UltraScale+ xcau25p-2ffvb676e

OK

TBD

olimex_gatemateevb

Olimex CCGMA1 Cologne Chip GateMate FPGA Evaluation Board

Cologne Chip GateMate Series (GM1A1)

OK

NT

orbtrace_dfu

ORBTrace mini (dfu mode)

ECP5 LFE5U-25F-8BG256C

NA

OK (DFU)

orangeCrab

Orange Crab

ECP5 LFE5U-25F-8MG285C

OK (JTAG)

OK (DFU)

OrangeCrab-r0.2 ➚

papilio_one

Papilio One

Spartan3E xc3s500e-vq100

OK

OK

pipistrello

Saanlima Pipistrello LX45

Spartan6 xc6slx45-csg324

OK

OK

pynq_z1

PYNQ-Z1

Zynq7000 xc7z020clg400

OK

NA

pynq_z2

PYNQ-Z2

Zynq7000 xc7z020clg400

OK

NA

qmtechCyclone10

QMTech Cyclone 10 Starter Kit

Cyclone 10 LP 10CL016YU484C8G

OK

OK

qmtechCycloneIV

QMTech CycloneIV Core Board

Cyclone IV EP4CE15F23C8N

OK

OK

qmtechCycloneV

QMTech CycloneV Core Board

Cyclone V 5CEFA2F23I7

OK

OK

qmtechCycloneV_5ce523

QMTech CycloneV Core Board

Cyclone V 5CEFA5F23I7

OK

OK

qmtechKintex7

QMTech Kintex7 Core Board

Kintex xc7k325tffg676

OK

OK

genesys2

Digilent Kintex7 Evaluation Board

Kintex xc7k325tffg900

OK

OK

redpitaya14

Redpitaya/STEMlab xc7z7010 with 125MHz 14 bits ADC

Zynq7000 xc7z010clg400

OK

NA

runber

SeeedStudio Gowin RUNBER

littleBee GW1N-4

OK

IF/EF

runber

Scarab Hardware MiniSpartan6+

Spartan6 xc6slx25-3-ftg256

OK

NT

spartanEdgeAccelBoard

SeeedStudio Spartan Edge Accelerator Board

Spartan7 xc7s15ftgb196

OK

NA

SPEC150

CERN Simple PCIe FMC carrier SPEC

Spartan6 xc6slx150Tfgg484

OK

OK

stlv7325

Sitlinv STLV7325 Board

Kintex xc7k325tffg676

OK

OK

tangnano

Sipeed Tang Nano

littleBee GW1N-1

OK

tangnano1k

Sipeed Tang Nano 1K

littleBee GW1NZ-1

OK

IF

tangnano4k

Sipeed Tang Nano 4K

littleBee GW1NSR-4C

OK

IF/EF

tangnano9k

Sipeed Tang Nano 9K

littleBee GW1NR-9C

OK

IF/EF

tangnano20k

Sipeed Tang Nano 20k

Gowin Arora GW2A(R)-18(C)

OK

EF

tangprimer20k

Sipeed Tang Primer 20k

Gowin Arora GW2A(R)-18(C)

OK

EF

tangprimer25k

Sipeed Tang Primer 25k

Gowin Arora V GW5A-25A (GW5A-LV25MG121)

OK

TBD

tangmega138k

Sipeed Tang Mega 138k

Gowin Arora V GW5AST-138B (GW5AST-LV138FPG676A)

OK

TBD

te0712_8

Trenz Electronic TE0712 FPGA-Module mit AMD Artix™ 7(TE0712)

XC7A200TFBG484

OK

OK

tec0117

Trenz Gowin LittleBee (TEC0117)

littleBee GW1NR-9

OK

IF

trion_t20_bga256_jtag

Efinix Trion T20 BGA256 Dev Kit

Trion T20BGA256

OK

NT

tec0330

PCIe FMC Carrier with Xilinx Virtex-7 FPGA (TEC0330)

XC7VX330T-2FFG1157C

OK

OK

trion_t120_bga576

Efinix Trion T120 BGA576 Dev Kit (SPI mode)

Trion T120BGA576

NA

AS

trion_t120_bga576_jtag

Efinix Trion T120 BGA576 Dev Kit (JTAG mode)

Trion T120BGA576

OK

OK

trion_ti60_f225

Efinix Titanium F225 Dev Kit (SPI mode)

Titanium Ti60F225

NA

AS

trion_ti60_f225_jtag

Efinix Titanium F225 Dev Kit (JTAG mode)

Titanium Ti60F225

OK

OK

ulx3s

Radiona ULX3S

ECP5 LFE5U

OK

OK

ULX3S-12F ➚ ULX3S-25F ➚ ULX3S-45F ➚ ULX3S-85F ➚

ulx3s_dfu

Radiona ULX3S DFU mode

ECP5 LFE5U

NA

OK

vec_v6

Xilinx VCU118

xc6vlx130tff784

OK

OK

vcu118

Xilinx VCU118

Virtex UltraScale+ xcvu9p-flga2104

OK

OK

vcu128

Xilinx VCU128

Virtex UltraScale+ xcvu37p-fsvh2892

OK

OK

vcu1525

AMD Virtex UltraScale+ FPGA VCU1525 Acceleration Development Kit

Virtex UltraScale+ xcvu9p-fsgd2104

OK

NT

xtrx

FairWaves XTRXPro

Artix xc7a50tcpg236

OK

OK

xyloni_spi

Efinix Xyloni

Trion T8F81

NA

AS

usrpx300

Ettus Research USRP X300

Kintex xc7k325tffg900

OK

NA

usrpx310

Ettus Research USRP X300

Kintex xc7k410tffg900

OK

NA

xmf3

PLDkit XMF3

Xilinx xc3s200ft256, xcf01s

OK

OK

zc702

Xilinx ZC702

zynq7000 xc7z020clg484

OK

NA

zc706

Xilinx ZC706

zynq7000 xc7z045ffg900

OK

NA

ZC706 ➚

zcu102

Xilinx ZCU102

zynqMPSoC XCZU9EG

OK

NA

zcu106

Xilinx ZCU106

zynqMPSoC XCZU7EV

OK

NA

zedboard

Avnet ZedBoard

zynq7000 xc7z020clg484

OK

NA

ZedBoard ➚

zybo_z7_10

Digilent Zybo Z7-10

zynq7000 xc7z010clg400

OK

NA

zybo_z7_20

Digilent Zybo Z7-20

zynq7000 xc7z020clg400

OK

NA

VMM3

CERN board with VMM3

xc7s50csga324?

OK

OK

+
    +

  • IF: Internal Flash

    • +

  • EF: External Flash

    • +

  • AS: Active Serial flash mode

    • +

  • NA: Not Available

    • +

  • NT: Not Tested

    • +
+
+ + +
+
+ +
+
+
+
+ + + + \ No newline at end of file diff --git a/compatibility/cable.html b/compatibility/cable.html new file mode 100644 index 0000000000..22b5b8276d --- /dev/null +++ b/compatibility/cable.html @@ -0,0 +1,336 @@ + + + + + + + Cables — openFPGALoader: universal utility for programming FPGA latest documentation + + + + + + + + + + + + + + + +
+ + +
+ +
+
+ + +
+ +
+
+ +
+
+ +
+

Cables

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

keyword

Name

Description

anlogicCable

anlogic JTAG adapter

JTAG adapter firmware for stm32

arm-usb-ocd-h

Olimex ARM-USB-OCD-H adapter

High-speed 3-IN-1 fast USB ARM JTAG, USB-to-RS232 virtual port and power supply 5VDC device

bus_blaster

Dangerousprototypes Bus Blaster

Jtag adapter based on ft2232

bus_blaster_b

Dangerousprototypes Bus Blaster

Jtag adapter based on ft2232 (interface B)

ch347_jtag

ch347 JTAG adapter

QinHeng Electronics USB To UART+JTAG (mode 3)

ch552_jtag

ch552 JTAG adapter

Tang Nano USB-JTAG interface. FT2232C clone firmware for CH552 microcontroler

cmsisdap

ARM CMSIS DAP protocol interface

ARM CMSIS DAP protocol interface (hid only)

gatemate_pgm

gatemate pgm

Cologne Chip GateMate FPGA Programmer. FT232H-based JTAG/SPI programmer cable

gatemate_evb_jtag

gatemate evb JTAG

Cologne Chip GateMate JTAG programmer

gatemate_evb_spi

gatemate evb spi

Cologne Chip GateMate SPI programmer

dfu

DFU interface

DFU (Device Firmware Upgrade) USB device compatible with DFU protocol

digilent

digilent cable

FT2232 JTAG / UART cable

diglent_b

digilent cable

digilent FT2232 JTAG / UART cable (interface B)

digilent_hs2

digilent hs2 cable

FT232H JTAG programmer cable from digilent

digilent_hs3

digilent hs3

JTAG programmer cable from digilent

dirtyJtag

dirty Jtag

JTAG probe firmware for STM32F1

efinix_spi_ft4232

efinix SPI (ft4232)

efinix SPI interface (FTDI4232 interface A)

efinix_jtag_ft4232

efinix JTAG (ft4232)

efinix JTAG interface (FTDI4232 interface B)

efinix_spi_ft2232

efinix SPI (ft2232)

efinix SPI interface (FTDI2232 interface A)

efinix_jtag_ft2232

efinix JTAG (ft2232)

efinix JTAG interface (FTDI2232 interface B)

ft2232

FT2232 C/D/H

generic programmer cable based on Ftdi FT2232 (interface A)

ft2232

Tang Nano (1k, 4k, 8k) USB-JTAG interface

USB-JTAG/UART debugger based on BL702 microcontroler.

ft2232

Sipeed RV-Debugger-BL702

RV-Debugger-BL702 is an opensource project that implement a JTAG+UART debugger with BL702C-A0.

ft2232

honeycomb USB-JTAG interface.

FT2232C clone based on STM32F042 microcontroler

ft2232_b

FT2232 C/D/H

generic programmer cable based on Ftdi FT2232 (interface B)

ft231X

FT231X

generic USB<->UART converters in bitbang mode (with some limitations and workaround)

ft232

FT232H

generic programmer cable based on Ftdi FT232Hx. One interface, MPSSE capable

ft232RL

FT232RL

generic USB<->UART converters in bitbang mode (with some limitations and workaround)

ft4232

FT4232

quad interface programmer cable. MPSSE capable.

ft4232hp

FT4232HP (interface A)

quad interface programmer cable. MPSSE capable. High Speed USB Bridge with Type-C/PD3.0 Controller

ft4232hp_b

FT4232HP (interface B)

quad interface programmer cable. MPSSE capable. High Speed USB Bridge with Type-C/PD3.0 Controller

ecpix5-debug

ecpix5-debug

LambdaConcept ECPIX5 (45k/85k) UART/JTAG interface

jlink

jlink

SEGGER J-Link Debug Probes

jlink

jlink_base

SEGGER J-Link BASE Debug Probes

jlink

jtrace_pro

SEGGER J-Trace PRO Debug Probes

jtag-smt2-nc

jtag-smt2-nc

JTAG-SMT2-NC Surface-mount Programming Module

lpc-link2

lpc-link2

LPC-Link2 (OM13054) cmsisDAP firmware

orbtrace

orbtrace interface

Open source FPGA-based debug and trace interface

papilio

papilio

Papilio FPGA Platform

steppenprobe

steppenprobe

Open Source Hardware JTAG/SWD/UART/SWO interface board based on FTDI FT2232H

remote-bitgang

OpenOCD remote bitbang

The remote_bitbang JTAG driver is used to drive JTAG from a remote (TCP) process

tigard

tigard

SWD/JTAG/UART/SPI programmer based on Ftdi FT2232HQ

usb-blaster

intel USB Blaster I interface

JTAG programmer cable from intel/altera (FT245 + EPM7064)

usb-blasterII

intel USB Blaster II interface

JTAG programmer cable from intel/altera (EZ-USB FX2 + EPM570)

xvc-client

Xilinx Virtual Cable

Xilinx Virtual Cable (XVC) is a TCP/IP-based protocol that acts like a JTAG cable.

xvc-server

Xilinx Virtual Cable (server side)

Xilinx Virtual Cable (XVC) is a TCP/IP-based protocol that acts like a JTAG cable.

libgpiod

Bitbang GPIO

Bitbang GPIO pins on Linux host.

jetson-nano-gpio

Bitbang GPIO

Bitbang GPIO pins on Jetson Nano Linux host. Use /dev/mem to have a faster clock.

ch347

CH347

CH347 is a USB HS bus converter with UART, I2C, SPI and JTAG interfaces

+
+ + +
+
+ +
+
+
+
+ + + + \ No newline at end of file diff --git a/compatibility/fpga.html b/compatibility/fpga.html new file mode 100644 index 0000000000..56fb4d7cbb --- /dev/null +++ b/compatibility/fpga.html @@ -0,0 +1,358 @@ + + + + + + + FPGAs — openFPGALoader: universal utility for programming FPGA latest documentation + + + + + + + + + + + + + + + +
+ + +
+ +
+
+ + +
+ +
+
+ +
+
+ +
+

FPGAs

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

Vendor

Description

Model

Memory

Flash

Anlogic

EG4

S20

OK

AS

Anlogic

SALELF 2

EF2M45

OK

OK

Cologne Chip

GateMate Series

CCGM1A1, CCGM1A2, CCGM1A4, CCGM1A9, CCGM1A16, CCGM1A25

OK

OK

Efinix

Trion

T8

NA

OK

Efinix

Titanium

Ti60

NA

OK

Gowin

GW1N

GW1N-1, GW1N-4, GW1NR-9, GW1NR-9C, GW1NS-2C, GW1NSR-4C, GW1NZ-1, GW2A-18C, GW5AST-138, GW5AT-138, GW5A-25

OK

IF / EF

Intel

Cyclone III

EP3C16

OK

OK

Intel

Cyclone IV CE

EP4CE22, EP4CE115

OK

OK

Intel

Cyclone V E

5CEA2, 5CEA5, 5CEBA4, 5CEBA9

OK

OK

Intel

Cyclone V SE SoC

5CSEBA6, 5CSEMA4, 5CSEMA5

OK

NT

Intel

Cyclone 10 LP

10CL025

OK

OK

Intel

Max 10

10M08

SVF

SVF

Lattice

Certus-NX

LFD2NX-40

OK

OK

Lattice

CertusPro-NX

LFCPNX-100

OK

OK

Lattice

CrossLink-NX

LIFCL-40

OK

OK

Lattice

ECP5

LFE5U-12, LFE5U-25, LFE5U-45, LFE5U-85, LFE5UM-25, LFE5UM-45, LFE5UM-85, LFE5UM5G-25, LFE5UM5G-45, LFE5UM5G-85

OK

OK

Lattice

iCE40

HX1K, HX4K, HX8K, UP5K

OK

AS

Lattice

MachXO2

256, 640, 640U, 1200, 1200U, 2000, 2000U, 4000, 7000

OK

OK

Lattice

MachXO3D

4300, 9400

OK

OK

Lattice

MachXO3LF

640, 1300, 2100, 4300, 6900, 9400

OK

OK

Xilinx

Artix 7

xc7a25t, xc7a35ti, xc7a50t, xc7a75t, xc7a100t, xc7a200t

OK

OK

Xilinx

Kintex 7

xc7k70t, xc7k160t, xc7k325t, xc7k410t, xc7k420t

OK

OK

Xilinx

Virtex 7

xc7v585t, xc7v2000t, xc7vx330t, xc7vx415t, xc7vx485t, xc7vx550t, xc7vx690t, xc7vx980t, xc7vx1140t, xc7vh580t, xc7vh870t

OK

OK

Xilinx

Artix UltraScale+

xcau25p

OK

TBD

Xilinx

Kintex UltraScale

xcku035, xcku040, xcku060, xcku115

OK

NA

Xilinx

Virtex 6

xc6vlx130t

OK

OK

Xilinx

Virtex UltraScale+

xcvu9p

OK

OK

Xilinx

Spartan 3

xc3s200, xc3s500e

OK

OK

Xilinx

Spartan 6

xc6slx9, xc6slx16, xc6slx25, xc6slx45, xc6slx150T

OK

OK

Xilinx

Spartan 7

xc7s15, xc7s25, xc7s50

OK

OK

Xilinx

XC9500XL

xc9536xl, xc9572xl, xc95144xl, xc95188xl

NA

OK

Xilinx

XC2C/XA2C (coolrunner II)

xc2c32a, xa2c64a

TBD

OK

Xilinx

XCF

xcf01s, xcf02s, xcf04s

NA

OK

Xilinx

Zynq7000

xc7z010, xc7z020

OK

NA

Xilinx

ZynqMPSoC

xczu2cg, xczu9eg, xczu11eg, xczu17eg

OK

NA

+
    +

  • IF: Internal Flash

    • +

  • AS: Active Serial flash mode

    • +

  • NA: Not Available

    • +

  • NT: Not Tested

    • +
+
+ + +
+
+ +
+
+
+
+ + + + \ No newline at end of file diff --git a/genindex.html b/genindex.html new file mode 100644 index 0000000000..09a0f508f6 --- /dev/null +++ b/genindex.html @@ -0,0 +1,127 @@ + + + + + + Index — openFPGALoader: universal utility for programming FPGA latest documentation + + + + + + + + + + + + + +
+ + +
+ +
+
+ + +
+ +
+
+ +
+
+ + +

Index

+ +
+ +
+ + +
+
+
+ +
+ +
+

© Copyright 2019-2022, Gwenhael Goavec-Merou and contributors.

+
Built with Sphinx using a + theme + provided by Build the Docs. + + +
+
+
+
+
+ + + + \ No newline at end of file diff --git a/guide/advanced.html b/guide/advanced.html new file mode 100644 index 0000000000..c4d04e29bb --- /dev/null +++ b/guide/advanced.html @@ -0,0 +1,241 @@ + + + + + + + Advanced usage of openFPGALoader — openFPGALoader: universal utility for programming FPGA latest documentation + + + + + + + + + + + + + + + +
+ + +
+ +
+
+ + +
+ +
+
+ +
+
+ +
+

Advanced usage of openFPGALoader

+
+

Resetting an FPGA

+
openFPGALoader [options] -r
+
+
+
+
+

Using negative edge for TDO’s sampling

+

If transaction are unstable you can try to change read edge by using

+
openFPGALoader [options] --invert-read-edge
+
+
+
+
+

Reading the bitstream from STDIN

+
cat /path/to/bitstream.ext | openFPGALoader --file-type ext [options]
+
+
+

--file-type is required to detect file type.

+
+

Note

+

It’s possible to load a bitstream through network:

+
# FPGA side
+nc -lp port | openFPGALoader --file-type xxx [option
+
+# Bitstream side
+nc -q 0 host port < /path/to/bitstream.ext
+
+
+
+
+
+

Automatic file type detection bypass

+

Default behavior is to use file extension to determine file parser. +To avoid this mechanism --file-type type must be used.

+
+
+

FT231/FT232 bitbang mode and pins configuration

+

FT232R and ft231X may be used as JTAG programmer. +JTAG communications are emulated in bitbang mode.

+

To use these devices user needs to provides both the cable and the pin mapping:

+
openFPGALoader [options] -cft23XXX --pins=TDI:TDO:TCK:TMS /path/to/bitstream.ext
+
+
+

where:

+
    +

  • ft23XXX may be ft232RL or ft231X.

    • +

  • TDI:TDO:TCK:TMS may be the pin ID (0 <= id <= 7) or string value.

    • +
+

allowed values are:

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

value

ID

TXD

0

RXD

1

RTS

2

CTS

3

DTR

4

DSR

5

DCD

6

RI

7

+
+
+

Writing to an arbitrary address in flash memory

+

With FPGA using an external SPI flash (xilinx, lattice ECP5/nexus/ice40, anlogic, efinix) option -o allows +one to write raw binary file to an arbitrary adress in FLASH.

+
+
+

Using an alternative directory for spiOverJtag

+

By setting OPENFPGALOADER_SOJ_DIR it’s possible to override default +spiOverJtag bitstreams directory:

+
export OPENFPGALOADER_SOJ_DIR=/somewhere
+openFPGALoader xxxx
+
+
+

or

+
OPENFPGALOADER_SOJ_DIR=/somewhere openFPGALoader xxxx
+
+
+
+
+ + +
+
+ +
+
+
+
+ + + + \ No newline at end of file diff --git a/guide/first-steps.html b/guide/first-steps.html new file mode 100644 index 0000000000..bb5b4ebe3f --- /dev/null +++ b/guide/first-steps.html @@ -0,0 +1,189 @@ + + + + + + + First steps with openFPGALoader — openFPGALoader: universal utility for programming FPGA latest documentation + + + + + + + + + + + + + + + +
+ + +
+ +
+
+ + +
+ +
+
+ +
+
+ +
+

First steps with openFPGALoader

+
+

Install

+

Packages are available for Linux distributions, Windows (MSYS2) and macOS:

+
    +

  • Arch Linux: sudo pacman -S openfpgaloader

    • +

  • Fedora: sudo dnf copr enable mobicarte/openFPGALoader; sudo dnf install openFPGALoader

    • +

  • MSYS2: pacman -S mingw-w64-ucrt-x86_64-openFPGALoader

    • +

  • macOS: brew install openfpgaloader

    • +
+

More instructions for other installation scenarios are available in Installing openFPGALoader.

+
+
+

Programming a development board

+

Just simply replace my_fpga_board with any FPGA board from Boards +(or openFPGALoader --list-boards) in any of the two commands below, depending on if you want to program the volatile +part of your FPGA (faster but not persistent) or the flash part of your FPGA (slower but persistent):

+
openFPGALoader -b my_fpga_board my_bitstream.bit # Program to SRAM
+openFPGALoader -b my_fpga_board -f my_bitstream.bit # Program to flash
+
+
+
+

Note

+

When a bitstream file is compatible with both memory load and FLASH write, the default behavior is to load bitstream +in memory.

+
+
+
+

Programming an “standalone” FPGA

+

If your FPGA doesn’t come with a built-in programmer or if you prefer to use an external cable, you can specify a cable +to use from Cables (or openFPGALoader --list-cables):

+
openFPGALoader -c my_cable my_bitstream.bit # Program to SRAM
+openFPGALoader -c my_cable -f my_bitstream.bit # Program to flash
+
+
+
+

Note

+

For some cable (like digilent adapters) signals from the converter are not just directly to the FPGA. +For this case, the -c must be added.

+
+
+

Hint

+

FTDI/FTDI-compatible cable users: the -d option lets you specify a specific FTDI device:

+
openFPGALoader -d /dev/ttyUSBX
+
+
+

When the -d option is not provided, openFPGALoader will opens the first FTDI adapter it finds. +Therefore it is preferable to use this flag if your computer is connected to multiple FTDI devices.

+
+
+
+

Troubleshooting

+

Please refer to Troubleshooting.

+
+
+ + +
+
+ +
+
+
+
+ + + + \ No newline at end of file diff --git a/guide/install.html b/guide/install.html new file mode 100644 index 0000000000..9a84d8c8bd --- /dev/null +++ b/guide/install.html @@ -0,0 +1,286 @@ + + + + + + + Installing openFPGALoader — openFPGALoader: universal utility for programming FPGA latest documentation + + + + + + + + + + + + + + + +
+ + +
+ +
+
+ + +
+ +
+
+ +
+
+ +
+

Installing openFPGALoader

+
+

Linux

+
+

Arch Linux

+

openFPGALoader is available in the default repositories:

+
sudo pacman -S openfpgaloader
+
+
+

Alternatively, you could build from source. First: install required libraries:

+
sudo pacman -S git cmake make gcc pkgconf libftdi libusb zlib hidapi gzip
+
+
+

Build step is similar as Debian

+
+
+

Fedora

+

openFPGALoader is available as a Copr repository:

+
sudo dnf copr enable mobicarte/openFPGALoader
+sudo dnf install openFPGALoader
+
+
+
+
+

From source (Debian, Ubuntu)

+

This application uses libftdi1, so this library must be installed (and, depending on the distribution, headers too):

+
sudo apt install \
+  git \
+  gzip \
+  libftdi1-2 \
+  libftdi1-dev \
+  libhidapi-hidraw0 \
+  libhidapi-dev \
+  libudev-dev \
+  zlib1g-dev \
+  cmake \
+  pkg-config \
+  make \
+  g++
+
+
+
+

Hint

+

libudev-dev is optional, may be replaced by eudev-dev or just not installed.

+
+

By default, (e)udev support is enabled (used to open a device by his /dev/xx node). +If you don’t want this option, use:

+
-DENABLE_UDEV=OFF
+
+
+

By default, cmsisdap support is enabled (used for colorlight I5, I9). +If you don’t want this option, use:

+
-DENABLE_CMSISDAP=OFF
+
+
+

Alternatively you can manually specify the location of libusb and libftdi1:

+
-DUSE_PKGCONFIG=OFF \
+-DLIBUSB_LIBRARIES=<path_to_libusb> \
+-DLIBFTDI_LIBRARIES=<path_to_libftdi> \
+-DLIBFTDI_VERSION=<version> \
+-DCMAKE_CXX_FLAGS="-I<libusb_include_dir> -I<libftdi1_include_dir>"
+
+
+

You may also need to add this if you see link errors between libusb and pthread:

+
-DLINK_CMAKE_THREADS=ON
+
+
+

By default, libgpiod support is enabled +If you don’t want this option, use:

+
-DENABLE_LIBGPIOD=OFF
+
+
+

Additionaly you have to install libgpiod

+

To build the app:

+
git clone https://github.com/trabucayre/openFPGALoader
+cd openFPGALoader
+mkdir build
+cd build
+cmake .. # add -DBUILD_STATIC=ON to build a static version
+         # add -DENABLE_UDEV=OFF to disable udev support and -d /dev/xxx
+         # add -DENABLE_CMSISDAP=OFF to disable CMSIS DAP support
+cmake --build .
+# or
+make -j$(nproc)
+
+
+

To install

+
$ sudo make install
+
+
+

The default install path is /usr/local, to change it, use -DCMAKE_INSTALL_PREFIX=myInstallDir in cmake invokation.

+
+
+

Udev rules

+

By default, users have no access to converters. +A rule file (99-openfpgaloader.rules) for udev is provided at the root directory +of this repository. +These rules set access right and group (plugdev) when a converter is plugged.

+
sudo cp 99-openfpgaloader.rules /etc/udev/rules.d/
+sudo udevadm control --reload-rules && sudo udevadm trigger # force udev to take new rule
+sudo usermod -a $USER -G plugdev # add user to plugdev group
+
+
+

After that you need to unplug and replug your device.

+
+

Hint

+

usermod is used to add $USER as a member of plugdev group. +However this update is not taken into account immediately: it’s required to +logout from current session and login again. +Check, by using id $USER, if plugdev is mentioned after groups=. +An alternate (and temporary) solution is to use sudo - $USER to have +your user seen as a member of plugdev group (works only for the current terminal).

+
+
+
+
+

macOS

+

openFPGALoader is available as a Homebrew formula:

+
brew install openfpgaloader
+
+
+

Alternatively, if you want to build it by hand:

+
brew install --only-dependencies openfpgaloader
+brew install cmake pkg-config zlib gzip
+git clone https://github.com/trabucayre/openFPGALoader
+cd openFPGALoader
+mkdir build
+cd build
+cmake ..
+make -j
+
+
+
+
+

Windows

+
+
+

Common

+

Bitstreams for XC2C (coolrunner-II) needs to be remapped using .map shipped with ISE. +ISE path is set at configure time using:

+
-DISE_PATH=/somewhere/Xilinx/ISE_VERS/
+
+
+

default: /opt/Xilinx/14.7.

+
+
+ + +
+
+ +
+
+
+
+ + + + \ No newline at end of file diff --git a/guide/troubleshooting.html b/guide/troubleshooting.html new file mode 100644 index 0000000000..4dafe3848a --- /dev/null +++ b/guide/troubleshooting.html @@ -0,0 +1,169 @@ + + + + + + + Troubleshooting — openFPGALoader: universal utility for programming FPGA latest documentation + + + + + + + + + + + + + + + +
+ + +
+ +
+
+ + +
+ +
+
+ +
+
+ +
+

Troubleshooting

+
+

I installed openFPGALoader but it says command not found when I try to launch it

+

The correct spelling of the program is openFPGALoader with FPGA and the “L” of “Loader” in uppercase. +Ensure the spelling of the program is correct.

+
+
+

Gowin device could not communicate since last bitstream flashed. (issue #206)

+

Gowin’s FPGA may fails to be detected if JTAGSEL_N (pin 08 for GW1N-4K) is used as a GPIO. +To recover you have to pull down this pin (before power up) to recover JTAG interface (UG292 - JTAGSELL_N section).

+
+
+

JTAG init failed

+

Avoid using USB hubs and connect it directly to your PC USB port.

+
+
+

Tang Primer 20k program slow and stucked (issue #250)

+

Check your openFPGALoader version:

+
openFPGALoader -V
+
+
+

If it is older than release then v0.9.0, install the most recent version (from commit f5b89bff68a5e2147404a895c075773884077438 or later).

+
+
+

Cannot flash Tang Nano 9k (issue #251)

+

This is a device issue, erase its Embedded Flash using Official GoWin Programmer (preferentially in Windows) and SRAM too, then you can use openFPGALoader again.

+
+
+

Unable to open FTDI device: -4 (usb_open() failed) (issue #245)

+

Edit your /etc/udev/rules.d/99-ftdi.rules file exchanging your programming device permissions.

+

For more information, check the udev section from this guide

+
+
+ + +
+
+ +
+
+
+
+ + + + \ No newline at end of file diff --git a/index.html b/index.html new file mode 100644 index 0000000000..7b2521cd3b --- /dev/null +++ b/index.html @@ -0,0 +1,145 @@ + + + + + + + openFPGALoader: universal utility for programming FPGA — openFPGALoader: universal utility for programming FPGA latest documentation + + + + + + + + + + + + + + +
+ + +
+ +
+
+ + +
+
+ +
+

openFPGALoader: universal utility for programming FPGA

+

Welcome to the documentation of openFPGALoader!

+

openFPGALoader is a universal utility for programming FPGAs. +Compatible with many boards, cables and FPGA from major manufacturers (Xilinx, Altera/Intel, Lattice, Gowin, Efinix, Anlogic, Cologne Chip). +openFPGALoader works on Linux, Windows and macOS.

+

Not sure if your hardware is supported? Check the hardware compatibility lists:

+ +

Also checkout the vendor-specific documentation:

+ +
+
+
+
+
+
+
+
+
+ + +
+
+
+ +
+ +
+

© Copyright 2019-2022, Gwenhael Goavec-Merou and contributors.

+
Built with Sphinx using a + theme + provided by Build the Docs. + + +
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+ + + + \ No newline at end of file diff --git a/objects.inv b/objects.inv new file mode 100644 index 0000000000..2d58abc384 --- /dev/null +++ b/objects.inv @@ -0,0 +1,6 @@ +# Sphinx inventory version 2 +# Project: openFPGALoader: universal utility for programming FPGA +# Version: latest +# The remainder of this file is compressed using zlib. +xڅ ~ +ՍzmvWR+1F"epv5 O67a~ 7dy'ubIjVcݤwg=1CZ4/7B7:Ziv7kI[50lz5t(p<ȜIi宻Q9#A}%F?K:~Q>,;qoOY(U>,SٵB6T{_˧b Qqd?1;ުѺ:9XIx_C]4q'2BKYfgg2Chk'+qM[r o@kՋe#@Vq#L1=I"Uڏ&gQ9ZX #FF~>5*-LZܽ%*㤦Bkj$M½\$ _z ~1:4>W׃i+9sqf@@!?M1Ws0ś.zLjxs(IT-ٲ";&a2 R̙ )2g%c>s,#,Dds"hnsT*Y \ No newline at end of file diff --git a/search.html b/search.html new file mode 100644 index 0000000000..458e9b5bef --- /dev/null +++ b/search.html @@ -0,0 +1,141 @@ + + + + + + Search — openFPGALoader: universal utility for programming FPGA latest documentation + + + + + + + + + + + + + + + + +
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© Copyright 2019-2022, Gwenhael Goavec-Merou and contributors.

+
Built with Sphinx using a + theme + provided by Build the Docs. + + +
+
+
+
+
+ + + + + + + + + \ No newline at end of file diff --git a/searchindex.js b/searchindex.js new file mode 100644 index 0000000000..796a888cc4 --- /dev/null +++ b/searchindex.js @@ -0,0 +1 @@ +Search.setIndex({"docnames": ["compatibility/board", "compatibility/cable", "compatibility/fpga", "guide/advanced", "guide/first-steps", "guide/install", "guide/troubleshooting", "index", "todo", "vendors/anlogic", "vendors/colognechip", "vendors/efinix", "vendors/gowin", "vendors/intel", "vendors/lattice", "vendors/xilinx"], "filenames": ["compatibility/board.rst", "compatibility/cable.rst", "compatibility/fpga.rst", "guide/advanced.rst", "guide/first-steps.rst", "guide/install.rst", "guide/troubleshooting.rst", "index.rst", "todo.rst", "vendors/anlogic.rst", "vendors/colognechip.rst", "vendors/efinix.rst", "vendors/gowin.rst", "vendors/intel.rst", "vendors/lattice.rst", "vendors/xilinx.rst"], "titles": ["Boards", "Cables", "FPGAs", "Advanced usage of openFPGALoader", "First steps with openFPGALoader", "Installing openFPGALoader", "Troubleshooting", "openFPGALoader: universal utility for programming FPGA", "To Do", "Anlogic notes", "Cologne Chip notes", "Efinix notes", "Gowin notes", "Intel notes", "Lattice notes", "Xilinx notes"], "terms": {"arti": [0, 15], "can": [0, 3, 4, 5, 6, 10, 15], "ani": [0, 4, 10], "name": [0, 1], "from": [0, 1, 4, 6, 7, 10], "first": [0, 5], "column": 0, "openfpgaload": [0, 9, 10, 11, 12, 13, 14, 15], "b": [0, 1, 4, 9, 10, 11, 12, 13, 14, 15], "bitstream": [0, 4, 5, 9, 14], "bit": [0, 4, 10, 14, 15], "load": [0, 3, 4, 12, 14], "sram": [0, 4, 6, 8], "volatil": [0, 4], "f": [0, 4, 9, 10, 11, 12, 14, 15], "write": [0, 4, 8, 10, 11, 15], "flash": [0, 2, 4, 8], "non": 0, "descript": [0, 1, 2], "fpga": [0, 1, 6, 8, 10, 11, 12, 13, 15], "memori": [0, 2, 4, 10, 15], "constraint": 0, "ac701": 0, "xilinx": [0, 1, 2, 3, 5, 7], "artix": [0, 2], "7": [0, 2, 3, 5, 14], "evalu": [0, 10], "kit": 0, "xc7a200t2fbg676c": 0, "ok": [0, 2], "nt": [0, 2], "acorncle215": 0, "acorn": 0, "cle": 0, "215": 0, "xc7a200tsbg484": 0, "litex": 0, "baseboard": 0, "mini": 0, "The": [0, 1, 5, 6, 10, 15], "ar": [0, 3, 4, 10, 11, 13, 15], "develop": 0, "around": 0, "sqrl": 0, "": [0, 4, 5, 6, 9, 10, 12, 13, 14, 15], "nite": 0, "litefuri": 0, "alchitry_au": 0, "alchitri": [0, 15], "au": 0, "xc7a35tftg256": 0, "alchitry_au_plu": 0, "plu": 0, "xc7a100tftg256": 0, "alinx_ax516": 0, "alinx": 0, "ax516": 0, "spartan6": 0, "xc6slx16csg324": 0, "alinx_ax7101": 0, "ax": 0, "7101": 0, "xc7a100tfgg484": 0, "alinx_ax7102": 0, "7102": 0, "analogmax": 0, "trenz": [0, 8, 12], "tei0010": 0, "max": [0, 2], "10": [0, 2, 14], "10m08sau169c8g": 0, "svf": [0, 2, 13], "antmicro_ddr4_test": 0, "antmicro": 0, "data": [0, 10, 15], "center": 0, "dram": 0, "tester": 0, "kintex7": 0, "xc7k160t": [0, 2], "antmicro_ddr5_test": 0, "ddr5": 0, "antmicro_lpddr4_test": 0, "lpddr4": 0, "test": [0, 2, 11], "xc7k70t": [0, 2], "arty_a7_35t": 0, "digil": [0, 1, 4], "a7": 0, "xc7a35ticsg324": 0, "35t": 0, "arty_a7_100t": 0, "xc7a100tcsg324": 0, "100t": 0, "arty_s7_25": 0, "s7": 0, "spartan7": 0, "xc7s25csga324": 0, "25": [0, 2], "arty_s7_50": 0, "xc7s50csga324": 0, "50": 0, "arty_z7_10": 0, "zynq7000": [0, 2], "xc7z010csg400": 0, "na": [0, 2], "arty_z7_20": 0, "xc7z020csg400": 0, "analog": 0, "discoveri": 0, "2": [0, 2, 3, 5, 15], "xc6slx25": [0, 2], "digit": 0, "axu2cga": 0, "zynq": [0, 15], "mpsoc": [0, 15], "dev": [0, 1, 4, 5], "zynqmpsoc": [0, 2], "xczu2cg": [0, 2], "basys3": 0, "xc7a35tcpg236": 0, "cmod_s7": 0, "cmod": 0, "xc7s25csga225": 0, "gatemate_evb_jtag": [0, 1, 10], "cologn": [0, 1, 2, 7], "chip": [0, 1, 2, 7], "gatem": [0, 1, 2, 10], "jtag": [0, 1, 3, 12, 13, 15], "mode": [0, 1, 2, 11, 12, 13, 15], "seri": [0, 2], "gatemate_evb_spi": [0, 1, 10], "spi": [0, 1, 3, 8, 11, 12], "gatemate_pgm_spi": [0, 10], "programm": [0, 1, 3, 4, 6, 10, 14], "certusnx_versa_evn": 0, "certu": [0, 2], "nx": [0, 2], "versa": 0, "lfd2nx": [0, 2], "40": [0, 2], "certuspronx_evn": 0, "certuspro": [0, 2], "lfcpnx": [0, 2], "100": [0, 2], "certuspronx_versa_evn": 0, "cmoda7_15t": 0, "cmoda7": 0, "xc7a15tcpg236": 0, "cmoda7_35t": 0, "colorlight": [0, 5], "5a": 0, "75b": 0, "version": [0, 5, 6], "ecp5": [0, 2, 3], "lfe5u": [0, 2], "25f": 0, "6bg256c": 0, "i5": [0, 5], "6bg381c": 0, "v7": 0, "0": [0, 1, 3, 6, 8, 10, 15], "i9": [0, 5], "45f": 0, "xc7a50tfgg484": 0, "crosslinknx_evn": 0, "lattic": [0, 2, 3, 7], "crosslink": [0, 2], "nexu": [0, 3], "lifcl": [0, 2], "cyc1000": [0, 13], "cyclon": [0, 2, 13], "lp": [0, 2, 3], "10cl025yu256c8g": [0, 13], "c10lp": [0, 13], "refkit": [0, 13], "10cl055yu484c8g": [0, 13], "c5g": 0, "teras": 0, "v": [0, 2, 6], "gx": 0, "starter": 0, "5cgxfc5c6f27c7n": 0, "de0": [0, 13], "iii": [0, 2], "ep3c16f484c6": 0, "de0nano": [0, 13], "iv": [0, 2], "e": [0, 2, 5, 10], "ep4ce22f17c6": 0, "de0nanosoc": [0, 13], "soc": [0, 2], "5csema4u23c6": 0, "de10lit": 0, "10m50daf484c7g": 0, "de10nano": 0, "5cseba6u23i7": 0, "de1soc": 0, "de1": 0, "5csema5f31c6": 0, "deca": 0, "arrow": 0, "10m50daf484c6g": 0, "ecp5_evn": 0, "5g": 0, "ecp5g": 0, "lfe5um5g": [0, 2], "85f": 0, "evn": 0, "ecpix5": [0, 1], "lambdaconcept": [0, 1], "ecpix": 0, "5": [0, 3, 14], "ft2232": [0, 1, 8], "ecpix5_r03": 0, "ft4232": [0, 1], "fireant": [0, 11], "trion": [0, 2], "t8": [0, 2], "t8f81": 0, "AS": [0, 2], "fomu": 0, "pvt": 0, "ice40ultraplu": 0, "up5k": [0, 2], "gr740": 0, "honeycomb": [0, 1, 12], "littlebe": 0, "gw1n": [0, 2, 6], "2c": [0, 2], "IF": [0, 2], "hseda": 0, "xc6slx16": [0, 2], "microblaz": 0, "sdram": 0, "usb2": 0, "ftg256": 0, "ice40_gener": [0, 14], "icebreak": 0, "bitsi": 0, "v0": [0, 6], "v1": 0, "icestick": 0, "ice40": [0, 2, 3], "hx1k": [0, 2], "hx8k": [0, 2], "olimex": [0, 1], "ice40hx1k": 0, "evb": [0, 1, 14], "ice40hx8k": 0, "ultraplu": 0, "breakout": [0, 14], "ice40up5k": 0, "up": [0, 6, 12, 15], "icezum": 0, "alhambra": 0, "ii": [0, 1, 2, 5], "hx4k": [0, 2], "icezumalhambraii": 0, "kc705": 0, "xc7k325t": [0, 2], "kcu105": 0, "kintex": [0, 2], "ultrascal": [0, 2, 15], "xcku040": [0, 2], "ffva1156": 0, "kcu116": 0, "xcku5p": 0, "ffvb676": 0, "ld": 0, "konfekt": 0, "lone": 0, "dynam": 0, "corpor": 0, "machdyn": 0, "comput": [0, 4, 8], "12f": 0, "schoko": 0, "6cabga256": 0, "licheetang": [0, 9], "sipe": [0, 1, 8, 12], "liche": 0, "tang": [0, 1, 12], "eagl": 0, "s20": [0, 2], "eg4s20bg256": 0, "machxo2evn": 0, "machxo2": [0, 2], "lcmxo2": 0, "7000he": 0, "machxo3evn": 0, "machxo3d": [0, 2, 14], "lcmxo3d": 0, "9400hc": 0, "machxo3sk": [0, 14], "machxo3lf": [0, 2], "machxo3": 0, "lcmx03lf": 0, "6900c": 0, "mini_itx": 0, "avnet": 0, "itx": 0, "base": [0, 1, 11, 15], "amd": 0, "xc7z045": 0, "xc7z100": 0, "2ffg900": 0, "nexys_a7_50": 0, "nexi": 0, "4": [0, 2, 3], "ddr": 0, "xc7a50tcsg324": 0, "nexys4ddr": 0, "nexys_a7_100": 0, "nexysvideo": 0, "video": 0, "xem8320": 0, "opal": 0, "kelli": 0, "xcau25p": [0, 2], "2ffvb676e": 0, "tbd": [0, 2], "olimex_gatemateevb": 0, "ccgma1": 0, "gm1a1": 0, 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"devic": [6, 8], "could": 6, "commun": 6, "sinc": 6, "last": 6, "issu": 6, "206": 6, "jtag": [6, 10, 11], "init": 6, "fail": 6, "tang": [6, 9], "primer": 6, "20k": 6, "slow": 6, "stuck": 6, "250": 6, "cannot": 6, "nano": 6, "9k": 6, "251": 6, "unabl": 6, "open": 6, "ftdi": 6, "4": 6, "usb_open": 6, "245": 6, "univers": 7, "util": 7, "To": 8, "do": 8, "global": 8, "misc": 8, "anlog": 9, "note": [9, 10, 11, 12, 13, 14, 15], "sipe": 9, "liche": 9, "bit": 9, "load": [9, 11, 13, 15], "spi": [9, 10, 13, 14, 15], "svf": 9, "cologn": 10, "chip": 10, "support": 10, "access": 10, "efinix": 11, "firant": 11, "xyloni": 11, "trion": 11, "t8": 11, "hex": 11, "titanium": 11, "bin": 11, "gw1n": 12, "sram": [12, 14], "intel": 13, "altera": 13, "lattic": 14, "machxo2": 14, "machxo3": 14, "ice40": 14, "ecp5": 14, "crosslink": 14, "nx": 14, "xilinx": 15}, "envversion": {"sphinx.domains.c": 3, "sphinx.domains.changeset": 1, "sphinx.domains.citation": 1, "sphinx.domains.cpp": 9, "sphinx.domains.index": 1, "sphinx.domains.javascript": 3, "sphinx.domains.math": 2, "sphinx.domains.python": 4, "sphinx.domains.rst": 2, "sphinx.domains.std": 2, "sphinx.ext.intersphinx": 1, "sphinx": 60}, "alltitles": {"Boards": [[0, "boards"]], "Cables": [[1, "cables"]], "FPGAs": [[2, "fpgas"]], "Advanced usage of openFPGALoader": [[3, "advanced-usage-of-openfpgaloader"]], "Resetting an FPGA": [[3, "resetting-an-fpga"]], "Using negative edge for TDO\u2019s sampling": [[3, "using-negative-edge-for-tdo-s-sampling"]], "Reading the bitstream from STDIN": [[3, "reading-the-bitstream-from-stdin"]], "Automatic file type detection bypass": [[3, "automatic-file-type-detection-bypass"]], "FT231/FT232 bitbang mode and pins configuration": [[3, "ft231-ft232-bitbang-mode-and-pins-configuration"]], "Writing to an arbitrary address in flash memory": [[3, "writing-to-an-arbitrary-address-in-flash-memory"]], "Using an alternative directory for spiOverJtag": [[3, "using-an-alternative-directory-for-spioverjtag"]], "First steps with openFPGALoader": [[4, "first-steps-with-openfpgaloader"]], "Install": [[4, "install"]], "Programming a development board": [[4, "programming-a-development-board"]], "Programming an \u201cstandalone\u201d FPGA": [[4, "programming-an-standalone-fpga"]], "Troubleshooting": [[4, "troubleshooting"], [6, "troubleshooting"]], "Installing openFPGALoader": [[5, "installing-openfpgaloader"]], "Linux": [[5, "linux"]], "Arch Linux": [[5, "arch-linux"]], "Fedora": [[5, "fedora"]], "From source (Debian, Ubuntu)": [[5, "from-source-debian-ubuntu"]], "Udev rules": [[5, "udev-rules"]], "macOS": [[5, "macos"]], "Windows": [[5, "windows"]], "Common": [[5, "common"]], "I installed openFPGALoader but it says command not found when I try to launch it": [[6, "i-installed-openfpgaloader-but-it-says-command-not-found-when-i-try-to-launch-it"]], "Gowin device could not communicate since last bitstream flashed. (issue #206)": [[6, "gowin-device-could-not-communicate-since-last-bitstream-flashed-issue-206"]], "JTAG init failed": [[6, "jtag-init-failed"]], "Tang Primer 20k program slow and stucked (issue #250)": [[6, "tang-primer-20k-program-slow-and-stucked-issue-250"]], "Cannot flash Tang Nano 9k (issue #251)": [[6, "cannot-flash-tang-nano-9k-issue-251"]], "Unable to open FTDI device: -4 (usb_open() failed) (issue #245)": [[6, "unable-to-open-ftdi-device-4-usb-open-failed-issue-245"]], "openFPGALoader: universal utility for programming FPGA": [[7, "openfpgaloader-universal-utility-for-programming-fpga"]], "To Do": [[8, "to-do"]], "Global": [[8, "global"]], "Cable": [[8, "cable"]], "Devices/boards": [[8, "devices-boards"]], "Misc": [[8, "misc"]], "Anlogic notes": [[9, "anlogic-notes"]], "Sipeed Lichee Tang": [[9, "sipeed-lichee-tang"]], "bit file load (memory)": [[9, "bit-file-load-memory"]], "bit file load (spi flash)": [[9, "bit-file-load-spi-flash"]], "svf file load": [[9, "svf-file-load"]], "Cologne Chip notes": [[10, "cologne-chip-notes"]], "Supported Boards/Cables": [[10, "supported-boards-cables"]], "Programming Modes": [[10, "programming-modes"]], "JTAG Configuration": [[10, "jtag-configuration"]], "SPI Configuration": [[10, "spi-configuration"]], "JTAG Flash Access": [[10, "jtag-flash-access"]], "SPI Flash Access": [[10, "spi-flash-access"]], "Efinix notes": [[11, "efinix-notes"]], "Firant and Xyloni boards (efinix trion T8)": [[11, "firant-and-xyloni-boards-efinix-trion-t8"]], "hex file load": [[11, "hex-file-load"]], "Trion and Titanium JTAG usage": [[11, "trion-and-titanium-jtag-usage"]], "bin file load": [[11, "bin-file-load"]], "hex file flash": [[11, "hex-file-flash"]], "Gowin notes": [[12, "gowin-notes"]], "GOWIN GW1N": [[12, "gowin-gw1n"]], "Flash SRAM": [[12, "flash-sram"]], "Flash": [[12, "flash"]], "Intel notes": [[13, "intel-notes"]], "Intel/Altera": [[13, "intel-altera"]], "Loading a bitstream": [[13, "loading-a-bitstream"], [15, "loading-a-bitstream"]], "SPI flash": [[13, "spi-flash"], [15, "spi-flash"]], "Lattice notes": [[14, "lattice-notes"]], "MachXO2/MachXO3": [[14, "machxo2-machxo3"]], "Flash memory": [[14, "flash-memory"]], "SRAM": [[14, "sram"], [14, "id1"]], "iCE40": [[14, "ice40"]], "ECP5/Crosslink-NX": [[14, "ecp5-crosslink-nx"]], "SPI Flash": [[14, "spi-flash"]], "Xilinx notes": [[15, "xilinx-notes"]]}, "indexentries": {}}) \ No newline at end of file diff --git a/todo.html b/todo.html new file mode 100644 index 0000000000..c303c04cd8 --- /dev/null +++ b/todo.html @@ -0,0 +1,165 @@ + + + + + + + To Do — openFPGALoader: universal utility for programming FPGA latest documentation + + + + + + + + + + + + + + +
+ + +
+ +
+
+ + +
+ +
+
+ +
+
+ +
+

To Do

+
+

Global

+
    +

  • improve error message (be more precise)

    • +

  • catch all exception

    • +

  • documentation (code + API)

    • +
+
+
+

Cable

+
    +

  • fix ch552 (Sipeed tangNano): works with SRAM, fails with Flash

    • +

  • busblaster support

    • +

  • anlogic cable support

    • +
+
+
+

Devices/boards

+
    +

  • improve frequency configuration. Use FPGA, cable or –freq args maximum frequency

    • +

  • rework cyclone10 eeprom access to avoid using FT2232 interfaceB Spi emulation (only supported by trenz board)

    • +

  • fix checksum computation with gowin GW2A

    • +

  • add support for tangPrimer (anlogic EG4S20)

    • +
+
+
+

Misc

+
    +

  • fix spiFlash class to be able to write everywhere (currently offset is hardcoded to 0)

    • +
+
+
+ + +
+
+ +
+
+
+
+ + + + \ No newline at end of file diff --git a/vendors/anlogic.html b/vendors/anlogic.html new file mode 100644 index 0000000000..2e70d824ca --- /dev/null +++ b/vendors/anlogic.html @@ -0,0 +1,178 @@ + + + + + + + Anlogic notes — openFPGALoader: universal utility for programming FPGA latest documentation + + + + + + + + + + + + + + + +
+ + +
+ +
+
+ + +
+ +
+
+ +
+
+ +
+

Anlogic notes

+
+

Sipeed Lichee Tang

+

For this target, openFPGALoader supports svf and bit.

+
+

bit file load (memory)

+
openFPGALoader -m -b licheeTang /somewhere/project/prj/*.bit
+
+
+

Since -m is the default, this argument is optional.

+
+
+

bit file load (spi flash)

+
openFPGALoader -f -b licheeTang /somewhere/project/prj/*.bit
+
+
+
+
+

svf file load

+

It’s possible to produce this file by using TD:

+
    +

  • Tools->Device Chain

    • +

  • Add your bit file

    • +

  • Option : Create svf

    • +
+

or by using prjtang project:

+
mkdir build
+cd build
+cmake ../
+make
+
+
+

Now a file called tangbit is present in current directory and has to be used as follows:

+
tangbit --input /somewhere.bit --svf bitstream.svf
+
+
+
openFPGALoader -b licheeTang /somewhere/*.svf
+
+
+
+
+
+ + +
+
+ +
+
+
+
+ + + + \ No newline at end of file diff --git a/vendors/colognechip.html b/vendors/colognechip.html new file mode 100644 index 0000000000..d2f09add95 --- /dev/null +++ b/vendors/colognechip.html @@ -0,0 +1,223 @@ + + + + + + + Cologne Chip notes — openFPGALoader: universal utility for programming FPGA latest documentation + + + + + + + + + + + + + + + +
+ + +
+ +
+
+ + +
+ +
+
+ +
+
+ +
+

Cologne Chip notes

+
+

Supported Boards/Cables

+
    +

  • GateMate Evaluation Board using board parameters -b gatemate_evb_jtag or -b gatemate_evb_spi

    • +

  • GateMate Programmer using cable parameter -c gatemate_pgm

    • +
+
+
+

Programming Modes

+

Supported configuration files are bitfiles *.bit and it’s ASCII equivalents *.cfg.

+
+

JTAG Configuration

+

Performs an active hardware reset and writes the configuration into the FPGA latches via JTAG. The configuration mode pins CFG_MD[3:0] must be set to 0xC (JTAG).

+
    +

  1. Program using Evaluation Board:

    2. +
+
openFPGALoader -b gatemate_evb_jtag <bitfile>.cfg.bit
+
+
+
    +

  1. Program using Programmer Cable:

    2. +
+
openFPGALoader -c gatemate_pgm <bitfile>.cfg.bit
+
+
+
+
+

SPI Configuration

+

Performs an active hardware reset and writes the configuration into the FPGA latches via SPI. The configuration mode pins CFG_MD[3:0] must be set to 0x4 (SPI passive).

+
    +

  1. Program using Evaluation Board:

    2. +
+
openFPGALoader -b gatemate_evb_spi <bitfile>.cfg.bit
+
+
+
    +

  1. Program using Programmer Cable:

    2. +
+
openFPGALoader -b gatemate_pgm_spi <bitfile>.cfg.bit
+
+
+
+
+

JTAG Flash Access

+

It is possible to access external flashes via the internal JTAG-SPI-bypass. The configuration mode pins CFG_MD[3:0] must be set to 0xC (JTAG). Note that the FPGA will not start automatically.

+
    +

  1. Write to flash using Evaluation Board:

    2. +
+
openFPGALoader -b gatemate_evb_jtag <bitfile>.cfg.bit
+
+
+
    +

  1. Write to flash using Programmer Cable:

    2. +
+
openFPGALoader -c gatemate_pgm -f <bitfile>.cfg.bit
+
+
+

The offset parameter can be used to store data at any point in the flash, e.g.:

+
openFPGALoader -b gatemate_evb_jtag -o <offset> <bitfile>.cfg.bit
+
+
+
+
+

SPI Flash Access

+

If the programming device and FPGA share the same SPI signals, it is possible to hold the FPGA in reset and write data to the flash. The configuration mode can be set as desired. If the FPGA should start from the external memory after reset, the configuration mode pins CFG_MD[3:0] set to 0x0 (SPI active).

+
    +

  1. Write to flash using Evaluation Board:

    2. +
+
openFPGALoader -b gatemate_evb_spi -f <bitfile>.cfg.bit
+
+
+
    +

  1. Write to flash using Programmer Cable:

    2. +
+
openFPGALoader -b gatemate_pgm_spi -f <bitfile>.cfg.bit
+
+
+

The offset parameter can be used to store data at any point in the flash, e.g.:

+
openFPGALoader -b gatemate_evb_spi -o <offset> <bitfile>.cfg.bit
+
+
+
+
+
+ + +
+
+ +
+
+
+
+ + + + \ No newline at end of file diff --git a/vendors/efinix.html b/vendors/efinix.html new file mode 100644 index 0000000000..1310b60e9e --- /dev/null +++ b/vendors/efinix.html @@ -0,0 +1,177 @@ + + + + + + + Efinix notes — openFPGALoader: universal utility for programming FPGA latest documentation + + + + + + + + + + + + + + + +
+ + +
+ +
+
+ + +
+ +
+
+ +
+
+ +
+

Efinix notes

+
+

Firant and Xyloni boards (efinix trion T8)

+

.hex file is the default format generated by Efinity IDE, so nothing special must be done to generates this file.

+

openFPGALoader supports only active mode (SPI) (JTAG is WIP).

+
+

hex file load

+
openFPGALoader -b fireant /somewhere/project/outflow/*.hex
+
+
+

or, for xyloni board

+
openFPGALoader -b xyloni_spi /somewhere/project/outflow/*.hex
+
+
+

Since openFPGALoader access the flash directly in SPI mode the -b fireant, -b xyloni_spi is required (no +autodetection possible).

+
+
+
+

Trion and Titanium JTAG usage

+

openFPGALoader supports loading to RAM and SPI Flash with JTAG

+

Tested with J-Link BASE

+
+

bin file load

+
openFPGALoader --cable jlink_base -m  /somewhere/project/outflow/*.bin
+
+
+
+
+

hex file flash

+

Example for ti60f225. +NOTE: JTAG chains with more than one device (eg –index-chain) are currently not supported for writing to SPI flash

+
openFPGALoader --cable jlink_base --fpga-part ti60f225 -f  /somewhere/project/outflow/*.hex
+
+
+
+
+
+ + +
+
+ +
+
+
+
+ + + + \ No newline at end of file diff --git a/vendors/gowin.html b/vendors/gowin.html new file mode 100644 index 0000000000..78c6b47aa6 --- /dev/null +++ b/vendors/gowin.html @@ -0,0 +1,193 @@ + + + + + + + Gowin notes — openFPGALoader: universal utility for programming FPGA latest documentation + + + + + + + + + + + + + + + +
+ + +
+ +
+
+ + +
+ +
+
+ +
+
+ +
+

Gowin notes

+
+

GOWIN GW1N

+
+

Note

+
    +

  • Trenz TEC0117

    • +

  • Sipeed Tang Nano

    • +

  • Sipeed Tang Nano 4K

    • +

  • Honeycomb

    • +

  • RUNBER

    • +
+
+

.fs file is the default format generated by Gowin IDE, so nothing special must be done to generates this file.

+

Since the same file is used for SRAM and Flash a CLI argument is used to specify the destination.

+
+

Flash SRAM

+

with -m:

+
openFPGALoader -m -b BOARD_NAME impl/pnr/*.fs
+
+
+

where BOARD_NAME is:

+
    +

  • tec0117

    • +

  • tangnano

    • +

  • tangnano1k

    • +

  • tangnano4k

    • +

  • tangnano9k

    • +

  • tangnano20k

    • +

  • tangprimer20k

    • +

  • runber

    • +
+
+
+

Flash

+
+

Attention

+

Only with Trenz TEC0117 and runber.

+
+

with -f, file load:

+
openFPGALoader -f -b BOARD_NAME impl/pnr/*.fs
+
+
+

where BOARD_NAME is:

+
    +

  • tec0117

    • +

  • runber

    • +
+

It’s possible to flash external SPI Flash (connected to MSPI) in bscan mode by using --external-flash instead of +-f.

+
+

Note

+

Gowin’s FPGA may fails to be detected if JTAGSEL_N (pin 08 for GW1N-4K) is used as a GPIO. +To recover you have to pull down this pin (before power up) to recover JTAG interface (UG292 - JTAGSELL_N section).

+
+
+
+
+ + +
+
+ +
+
+
+
+ + + + \ No newline at end of file diff --git a/vendors/intel.html b/vendors/intel.html new file mode 100644 index 0000000000..2f0b1bcdde --- /dev/null +++ b/vendors/intel.html @@ -0,0 +1,191 @@ + + + + + + + Intel notes — openFPGALoader: universal utility for programming FPGA latest documentation + + + + + + + + + + + + + + + +
+ + +
+ +
+
+ + +
+ +
+
+ +
+
+ +
+

Intel notes

+
+

Intel/Altera

+
+

Note

+
    +

  • CYC1000

    • +

  • C10LP-RefKit

    • +

  • DE0

    • +

  • de0nano

    • +
+
+
+

Loading a bitstream

+

SVF and RBF files are supported.

+

sof to svf generation:

+
quartus_cpf -c -q 12.0MHz -g 3.3 -n p project_name.sof project_name.svf
+
+
+

sof to rbf generation:

+
quartus_cpf  --option=bitstream_compression=off -c project_name.sof project_name.rbf
+
+
+
+

Warning

+

As mentioned in cyclone handbooks, real-time decompression is not supported by FPGA in JTAG mode. +Keep in mind to disable this option.

+
+

file load:

+
openFPGALoader -b boardname project_name.svf
+# or
+openFPGALoader -b boardname project_name.rbf
+
+
+

with boardname = de0, cyc1000, c10lp-refkit, de0nano, de0nanoSoc or qmtechCycloneV.

+
+
+

SPI flash

+

RPD and RBF are supported.

+

sof to rpd:

+
# CYC1000
+quartus_cpf -o auto_create_rpd=on -c -d EPCQ16A -s 10CL025YU256C8G project_name.svf project_name.jic
+# C10LP-RefKit
+quartus_cpf -o auto_create_rpd=on -c -d EPCQ16A -s 10CL055YU484C8G project_name.svf project_name.jic
+
+
+

file load:

+
openFPGALoader -b boardname -r project_name_auto.rpd
+# or
+openFPGALoader -b boardname -r project_name.rbf
+
+
+

with boardname = cyc1000, c10lp-refkit.

+
+
+
+ + +
+
+ +
+
+
+
+ + + + \ No newline at end of file diff --git a/vendors/lattice.html b/vendors/lattice.html new file mode 100644 index 0000000000..5cbeba81ce --- /dev/null +++ b/vendors/lattice.html @@ -0,0 +1,240 @@ + + + + + + + Lattice notes — openFPGALoader: universal utility for programming FPGA latest documentation + + + + + + + + + + + + + + + +
+ + +
+ +
+
+ + +
+ +
+
+ +
+
+ +
+

Lattice notes

+
+

MachXO2/MachXO3

+
+

Flash memory

+

.jed file is the default format generated by Lattice Diamond, so nothing special must be done to generates this +file.

+

File load:

+
openFPGALoader [-b yourboard] [--flash-sector CFG0] impl1/*.jed
+
+
+

where yourboard may be:

+
    +

  • machX02EVN

    • +

  • machX03EVN

    • +

  • machXO3SK

    • +
+

and where --flash-sector CFG0 is needed for the MachXO3D Breakout Board.

+

.bit may also be used for machXO2

+
+
+

SRAM

+

To generates .bit file Bitstream file must be checked under Exports Files in Lattice Diamond left panel.

+

File load:

+
openFPGALoader [-b yourboard] impl1/*.bit
+
+
+

where yourboard may be:

+
    +

  • machX02EVN

    • +

  • machX03EVN

    • +

  • machXO3SK

    • +
+
+
+
+

iCE40

+

.bin is the default format generated by nextpnr, so nothing special must be done.

+

Since most ice40 boards uses the same pinout between FTDI and SPI flash a generic ice40_generic board is provided.

+

For the specific case of the iCE40HXXK-EVB where no onboard programmer is present, please use this:

+ + + + + + + + + + + + + + + + + + + + + + + + + + +

FTDI

iCE40HXXK-EVB

SI (ADBUS1)

Pin 8

SCK (ADBUS0)

Pin 9

SO (ADBUS2)

Pin 7

CS (ABDUS4)

Pin 10

RST (ADBUS6

Pin 6

DONE (ADBUS7)

Pin 5

+

Bin file load:

+
openFPGALoader -b ice40_generic /somewhere/*.bin
+
+
+

Since it’s a direct access to the flash (SPI) the -b option is required.

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Xilinx notes

+

To simplify further explanations, we consider the project is generated in the current directory.

+
+

Note

+
    +

  1. Spartan Edge Accelerator Board has only pinheader, so the cable must be provided

    2. +

  2. A JTAG <-> SPI bridge (used to write bitstream in FLASH) is available for some device, see +spiOverJtag to check if your model is supported.

    3. +

  3. Board provides the device/package model, but if the targeted board is not officially supported but the FPGA yes, +you can use --fpga-part to provide the model.

    4. +

  4. With spartan3, the flash is an independent JTAG device. +User has to use --index-chain to access FPGA (RAM only) or flash (write/read only).

    5. +
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+
+

Warning

+

*.bin may be loaded in memory or in flash, but this extension is a classic extension for CPU firmware and, by +default, openFPGALoader loads file in memory. +Double check -m / -f when you want to use a firmware for a softcore (or anything, other than a bitstream) to +write somewhere in the FLASH device).

+
+

.bit file is the default format generated by vivado, so nothing special task must be done to generate this +bitstream.

+

.bin is not, by default, produced. +To have access to this file you need to configure the tool:

+
    +

  • GUI: Tools -> Settings -> Bitstreams -> check -bin_file.

    • +

  • TCL: append your TCL file with set_property STEPS.WRITE_BITSTREAM.ARGS.BIN_FILE true [get_runs impl_1].

    • +
+
+

Warning

+

For alchitry board the bitstream must be configured with a buswidth of 1 or 2. +Quad mode can’t be used with alchitry’s FLASH.

+
+
+

Warning

+

For boards based on a Zynq (7000 or MPSoC), boot mode must be configured for JTAG (for Zedboard JP7->JP11 must be +to GND).

+
+
+

Loading a bitstream

+

.bit and .bin are allowed to be loaded in memory.

+

File load:

+
openFPGALoader [-m] -b arty *.runs/impl_1/*.bit (or *.bin)
+
+
+

or

+
openFPGALoader [-m] -b spartanEdgeAccelBoard -c digilent_hs2 *.runs/impl_1/*.bit (or *.bin)
+
+
+
+

SPI flash

+
+

Note

+

.bit, .bin, and .mcs are supported for FLASH.

+
+

.mcs must be generated through Vivado with a tcl script like:

+
+

Warning

+

For boards based on Zynq device (7000 and MPSoC) SPI flash is not accessible through PL.

+
+
set project [lindex $argv 0]
+
+set bitfile "${project}.runs/impl_1/${project}.bit"
+set mcsfile "${project}.runs/impl_1/${project}.mcs"
+
+write_cfgmem -format mcs -interface spix4 -size 16 \
+   -loadbit "up 0x0 $bitfile" -loaddata "" \
+   -file $mcsfile -force
+
+
+
+

Note

+

-interface spix4 and -size 16 depends on SPI flash capability and size.

+
+

The tcl script is used with:

+
vivado -nolog -nojournal -mode batch -source script.tcl -tclargs myproject
+
+
+

File load:

+
openFPGALoader [--fpga-part xxxx] -f -b arty *.runs/impl_1/*.mcs (or .bit / .bin)
+
+
+
+

Note

+

-f is required to write bitstream (without them .bit and .bin are loaded in memory).

+
+
+

Note

+

--fpga-part is only required if this information is not provided at board.hpp level or if the board is not +officially supported. +device/package format is something like xc7a35tcsg324 (arty model). +See src/board.hpp, or spiOverJtag directory for examples.

+
+

Some boards with UltraScale FPGAs, like the VCU118 and KCU16, support the SPIx8 (Dual Quad SPI) configuration. +In this case, the spix8 option write_cfgmem on the above example can be used to generate two .mcs files, +to fit bigger designs or for faster programming. Only .mcs files can be used to program the FPGA in this case.

+

In this case, to load the two .mcs files:

+
openFPGALoader --board vcu118 -f --target-flash both --bitstream *.runs/impl_1/*_primary.mcs --secondary-bitstream *.runs/impl_1/*_secondary.mcs
+
+
+

On these boards, each SPI flash can be programmed independently with the --target-flash option. +The default target is the primary flash.

+

For example, to program only the secondary flash with arbitrary data not related to FPGA configuration:

+
openFPGALoader --board vcu118 -f --target-flash secondary --bitstream arbitrary_data
+
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