diff --git a/spiOverJtag/Makefile b/spiOverJtag/Makefile index e22a0416df..cbfe00a1b9 100644 --- a/spiOverJtag/Makefile +++ b/spiOverJtag/Makefile @@ -9,7 +9,7 @@ XILINX_PARTS := xc3s500evq100 \ xc7a50tcsg324 xc7a50tfgg484 xc7a50tcpg236 xc7a75tfgg484 \ xc7a100tcsg324 xc7a100tfgg484 xc7a100tfgg676\ xc7a200tsbg484 xc7a200tfbg484 xc7a200tfbg676\ - xc7s25csga225 xc7s25csga324 xc7s50csga324 \ + xc7s6ftgb196 xc7s25csga225 xc7s25csga324 xc7s50csga324 \ xc7k70tfbg484 xc7k70tfbg676 \ xc7k160tffg676 \ xc7k325tffg676 xc7k325tffg900 \ diff --git a/spiOverJtag/build.py b/spiOverJtag/build.py index beccf8d2c0..5118d9b1e6 100755 --- a/spiOverJtag/build.py +++ b/spiOverJtag/build.py @@ -106,6 +106,7 @@ "xc7k325tffg900" : "xc7k_ffg900", "xc7k420tffg901" : "xc7k_ffg901", "xc7vx330tffg1157" : "xc7v_ffg1157", + "xc7s6ftgb196" : "xc7s_ftgb196", "xc7s25csga225" : "xc7s_csga225", "xc7s25csga324" : "xc7s_csga324", "xc7s50csga324" : "xc7s_csga324", diff --git a/spiOverJtag/constr_xc7s_ftgb196.xdc b/spiOverJtag/constr_xc7s_ftgb196.xdc new file mode 100644 index 0000000000..3eaa20acc4 --- /dev/null +++ b/spiOverJtag/constr_xc7s_ftgb196.xdc @@ -0,0 +1,10 @@ +set_property CFGBVS VCCO [current_design] +set_property CONFIG_VOLTAGE 3.3 [current_design] +set_property BITSTREAM.CONFIG.SPI_BUSWIDTH {4} [current_design] +set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] + +set_property -dict {PACKAGE_PIN C11 IOSTANDARD LVCMOS33} [get_ports {csn}]; +set_property -dict {PACKAGE_PIN B11 IOSTANDARD LVCMOS33} [get_ports {sdi_dq0}]; +set_property -dict {PACKAGE_PIN B12 IOSTANDARD LVCMOS33} [get_ports {sdo_dq1}]; +set_property -dict {PACKAGE_PIN D10 IOSTANDARD LVCMOS33} [get_ports {wpn_dq2}]; +set_property -dict {PACKAGE_PIN C10 IOSTANDARD LVCMOS33} [get_ports {hldn_dq3}]; diff --git a/spiOverJtag/spiOverJtag_xc7s6ftgb196.bit.gz b/spiOverJtag/spiOverJtag_xc7s6ftgb196.bit.gz new file mode 100644 index 0000000000..833a28a6f1 Binary files /dev/null and b/spiOverJtag/spiOverJtag_xc7s6ftgb196.bit.gz differ