spiOverJtag: update xcku040 and xcku060 constraints

trabucayre · Sep 23, 2024 · e2e97c4 · e2e97c4
1 parent e941144
commit e2e97c4
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Showing 2 changed files with 14 additions and 14 deletions.
diff --git a/spiOverJtag/constr_xcku040_ffva1156.xdc b/spiOverJtag/constr_xcku040_ffva1156.xdc
@@ -1,16 +1,16 @@
 set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
 set_property CONFIG_VOLTAGE 1.8 [current_design]
-# Table 1-2 from UG570
+# Table 1-5 from UG917
 set_property CFGBVS GND [current_design]
 
 # Primary QSPI flash
 # Connection done through the STARTUPE3 block
-# sdi_dq0  - PACKAGE_PIN AC7      - QSPI0_DQ0                 Bank   0 - D00_MOSI_0
-# sdo_dq1  - PACKAGE_PIN AB7      - QSPI0_DQ1                 Bank   0 - D01_DIN_0
-# wpn_dq2  - PACKAGE_PIN AA7      - QSPI0_DQ2                 Bank   0 - D02_0
-# hldn_dq3 - PACKAGE_PIN Y7       - QSPI0_DQ3                 Bank   0 - D03_0
-# csn      - PACKAGE_PIN U7       - QSPI0_CS_B                Bank   0 - RDWR_FCS_B_0
-# sck      - PACKAGE_PIN AA9      - QSPI_CCLK                 Bank   0 - CCLK_0
+# sdi_dq0  - PACKAGE_PIN AC7      - QSPI0_IO0                 Bank   0 - D00_MOSI_0
+# sdo_dq1  - PACKAGE_PIN AB7      - QSPI0_IO1                 Bank   0 - D01_DIN_0
+# wpn_dq2  - PACKAGE_PIN AA7      - QSPI0_IO2                 Bank   0 - D02_0
+# hldn_dq3 - PACKAGE_PIN Y7       - QSPI0_IO3                 Bank   0 - D03_0
+# csn      - PACKAGE_PIN U7       - QSPI0_CSB                 Bank   0 - RDWR_FCS_B_0
+# sck      - PACKAGE_PIN AA9      - FPGA_CCLK                 Bank   0 - CCLK_0
 
 # Secondary QSPI flash
 set_property PACKAGE_PIN M20       [get_ports "sdi_sec_dq0"] ;# Bank  65 VCCO - VCC1V8   - IO_L22P_T3U_N6_DBC_AD0P_D04_65

diff --git a/spiOverJtag/constr_xcku060_ffva1156.xdc b/spiOverJtag/constr_xcku060_ffva1156.xdc
@@ -1,16 +1,16 @@
 set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
 set_property CONFIG_VOLTAGE 1.8 [current_design]
-# Table 1-2 from UG570
+# Table 1-5 from UG917
 set_property CFGBVS GND [current_design]
 
 # Primary QSPI flash
 # Connection done through the STARTUPE3 block
-# sdi_dq0  - PACKAGE_PIN AC7      - QSPI0_DQ0                 Bank   0 - D00_MOSI_0
-# sdo_dq1  - PACKAGE_PIN AB7      - QSPI0_DQ1                 Bank   0 - D01_DIN_0
-# wpn_dq2  - PACKAGE_PIN AA7      - QSPI0_DQ2                 Bank   0 - D02_0
-# hldn_dq3 - PACKAGE_PIN Y7       - QSPI0_DQ3                 Bank   0 - D03_0
-# csn      - PACKAGE_PIN U7       - QSPI0_CS_B                Bank   0 - RDWR_FCS_B_0
-# sck      - PACKAGE_PIN AA9      - QSPI_CCLK                 Bank   0 - CCLK_0
+# sdi_dq0  - PACKAGE_PIN AC7      - QSPI0_IO0                 Bank   0 - D00_MOSI_0
+# sdo_dq1  - PACKAGE_PIN AB7      - QSPI0_IO1                 Bank   0 - D01_DIN_0
+# wpn_dq2  - PACKAGE_PIN AA7      - QSPI0_IO2                 Bank   0 - D02_0
+# hldn_dq3 - PACKAGE_PIN Y7       - QSPI0_IO3                 Bank   0 - D03_0
+# csn      - PACKAGE_PIN U7       - QSPI0_CSB                 Bank   0 - RDWR_FCS_B_0
+# sck      - PACKAGE_PIN AA9      - FPGA_CCLK                 Bank   0 - CCLK_0
 
 # Secondary QSPI flash
 set_property PACKAGE_PIN M20       [get_ports "sdi_sec_dq0"] ;# Bank  65 VCCO - VCC1V8   - IO_L22P_T3U_N6_DBC_AD0P_D04_65