From f6f48a7b2792218b0035a6afff5be7c56b68b116 Mon Sep 17 00:00:00 2001
From: Nicolas Schodet <nico@ni.fr.eu.org>
Date: Tue, 12 Nov 2024 23:51:55 +0100
Subject: [PATCH] Add support for VCU108 board and Virtex UltraScale

---
 doc/FPGAs.yml  | 7 +++++++
 doc/boards.yml | 7 +++++++
 src/board.hpp  | 1 +
 src/part.hpp   | 3 +++
 src/xilinx.cpp | 2 ++
 src/xilinx.hpp | 1 +
 6 files changed, 21 insertions(+)

diff --git a/doc/FPGAs.yml b/doc/FPGAs.yml
index e188fd540..9f17d9771 100644
--- a/doc/FPGAs.yml
+++ b/doc/FPGAs.yml
@@ -290,6 +290,13 @@ Xilinx:
     Memory: OK
     Flash: OK
 
+  - Description: Virtex UltraScale
+    Model:
+      - xcvu095
+    URL: https://www.amd.com/en/products/adaptive-socs-and-fpgas/fpga/virtex-ultrascale.html#productTable
+    Memory: OK
+    Flash: TBD
+
   - Description: Virtex UltraScale+
     Model:
       - xcvu9p
diff --git a/doc/boards.yml b/doc/boards.yml
index 7058fd991..1da46b6b7 100644
--- a/doc/boards.yml
+++ b/doc/boards.yml
@@ -867,6 +867,13 @@
   Memory: OK
   Flash: NA
 
+- ID: vcu108
+  Description: Xilinx VCU108
+  URL: https://www.xilinx.com/products/boards-and-kits/vcu108.html
+  FPGA: Virtex UltraScale xcvu095-ffva2104
+  Memory: OK
+  Flash: TBD
+
 - ID: vcu118
   Description: Xilinx VCU118
   URL: https://www.xilinx.com/products/boards-and-kits/vcu118.html
diff --git a/src/board.hpp b/src/board.hpp
index 0e19d9f8a..04763f5ec 100644
--- a/src/board.hpp
+++ b/src/board.hpp
@@ -236,6 +236,7 @@ static std::map <std::string, target_board_t> board_list = {
 	JTAG_BOARD("usrpx310",        "xc7k410tffg900", "digilent", 0, 0, CABLE_MHZ(15)),
 	JTAG_BOARD("vec_v6",          "xc6vlx130tff784", "ft2232", 0, 0, CABLE_DEFAULT),
 	JTAG_BOARD("vc709", 		  "xc7vx690tffg1761", "digilent", 0, 0, CABLE_MHZ(15)),
+	JTAG_BOARD("vcu108",          "xcvu095-ffva2104", "jtag-smt2-nc", 0, 0, CABLE_DEFAULT),
 	JTAG_BOARD("vcu118",          "xcvu9p-flga2104", "jtag-smt2-nc", 0, 0, CABLE_DEFAULT),
 	JTAG_BOARD("vcu128",          "xcvu37p-fsvh2892", "ft4232", 0, 0, CABLE_DEFAULT),
 	JTAG_BOARD("vcu1525",         "xcvu9p-fsgd2104",  "ft4232", 0, 0, CABLE_MHZ(15)),
diff --git a/src/part.hpp b/src/part.hpp
index 6cf2a5cdb..4b3dfffc9 100644
--- a/src/part.hpp
+++ b/src/part.hpp
@@ -106,6 +106,9 @@ static std::map <uint32_t, fpga_model> fpga_list = {
 	{0x13919093, {"xilinx", "kintexus", "xcku060", 6}},
 	{0x1390d093, {"xilinx", "kintexus", "xcku115", 6}},
 
+	/* Xilinx Ultrascale / Virtex */
+	{0x03842093, {"xilinx", "virtexus", "xcvu095", 6}},
+
 	/* Xilinx Ultrascale+ / Artix */
 	{0x04AC2093, {"xilinx", "artixusp", "xcau15p", 6}},
 	{0x04A64093, {"xilinx", "artixusp", "xcau25p", 6}},
diff --git a/src/xilinx.cpp b/src/xilinx.cpp
index 0cfb15ff4..b33e498d9 100644
--- a/src/xilinx.cpp
+++ b/src/xilinx.cpp
@@ -356,6 +356,8 @@ Xilinx::Xilinx(Jtag *jtag, const std::string &filename,
 		_fpga_family = KINTEXUSP_FAMILY;
 	} else if (family == "artixusp") {
 		_fpga_family = ARTIXUSP_FAMILY;
+	} else if (family == "virtexus") {
+		_fpga_family = VIRTEXUS_FAMILY;
 	} else if (family == "virtexusp") {
 		_fpga_family = VIRTEXUSP_FAMILY;
 		_ircode_map = ircode_mapping.at("virtexusp");
diff --git a/src/xilinx.hpp b/src/xilinx.hpp
index 8993fb49b..b0fec7c7e 100644
--- a/src/xilinx.hpp
+++ b/src/xilinx.hpp
@@ -194,6 +194,7 @@ class Xilinx: public Device, SPIInterface {
 			ZYNQMP_FAMILY,
 			XCF_FAMILY,
 			ARTIXUSP_FAMILY,
+			VIRTEXUS_FAMILY,
 			VIRTEXUSP_FAMILY,
 			UNKNOWN_FAMILY  = 999
 		};