diff --git a/src/hammer-vlsi/technology/asap7/__init__.py b/src/hammer-vlsi/technology/asap7/__init__.py
index 46b7786e3..e50aeb3aa 100644
--- a/src/hammer-vlsi/technology/asap7/__init__.py
+++ b/src/hammer-vlsi/technology/asap7/__init__.py
@@ -35,165 +35,6 @@ def post_install_script(self) -> None:
                 self.logger.error("Check your gdspy v1.4 installation! Unable to hack ASAP7 PDK.")
                 shutil.rmtree(self.cache_dir)
                 sys.exit()
-        self.generate_multi_vt_gds()
-        self.fix_icg_libs()
-
-    def generate_multi_vt_gds(self) -> None:
-        """
-        PDK GDS only contains RVT cells.
-        This patch will generate the other 3(LVT, SLVT, SRAM) VT GDS files.
-        """
-        try:
-            os.makedirs(os.path.join(self.cache_dir, "GDS"))
-        except:
-            self.logger.info("Multi-VT GDS's already created")
-            return None
-
-        try:
-            self.logger.info("Generating GDS for Multi-VT cells using {}...".format(self.gds_tool.__name__))
-
-            stdcell_dir = self.get_setting("technology.asap7.stdcell_install_dir")
-            orig_gds = os.path.join(stdcell_dir, "GDS/asap7sc7p5t_27_R_201211.gds")
-
-            if self.gds_tool.__name__ == 'gdstk':
-                # load original GDS
-                asap7_original_gds = self.gds_tool.read_gds(infile=orig_gds)
-                original_cells = asap7_original_gds.cells
-                cell_list = list(map(lambda c: c.name, original_cells))
-                # required libs
-                multi_libs = {
-                    "L": {
-                        "lib": self.gds_tool.Library(),
-                        "mvt_layer": 98
-                        },
-                    "SL": {
-                        "lib": self.gds_tool.Library(),
-                        "mvt_layer": 97
-                        },
-                    "SRAM": {
-                        "lib": self.gds_tool.Library(),
-                        "mvt_layer": 110
-                        },
-                }
-                # create new libs
-                for vt, multi_lib in multi_libs.items():
-                    multi_lib['lib'].name = asap7_original_gds.name.replace('R', vt)
-
-                for cell in original_cells:
-                    # extract polygon from layer 100(the boundary for cell)
-                    boundary_polygon = next(filter(lambda p: p.layer==100, cell.polygons))
-                    for vt, multi_lib in multi_libs.items():
-                        new_cell_name = cell.name.rstrip('R') + vt
-                        cell_list.append(new_cell_name)
-                        mvt_layer = multi_lib['mvt_layer']
-                        # copy boundary_polygon to mvt_layer to mark the this cell is a mvt cell.
-                        mvt_polygon = self.gds_tool.Polygon(boundary_polygon.points, multi_lib['mvt_layer'], 0)
-                        mvt_cell = cell.copy(name=new_cell_name, deep_copy=True).add(mvt_polygon)
-                        # add mvt_cell to corresponding multi_lib
-                        multi_lib['lib'].add(mvt_cell)
-
-                for vt, multi_lib in multi_libs.items():
-                    # write multi_lib
-                    new_gds = os.path.basename(orig_gds).replace('R', vt)
-                    multi_lib['lib'].write_gds(os.path.join(self.cache_dir, 'GDS', new_gds))
-
-            elif self.gds_tool.__name__ == 'gdspy':
-                # load original GDS
-                asap7_original_gds = self.gds_tool.GdsLibrary().read_gds(infile=orig_gds, units='import')
-                original_cells = asap7_original_gds.cell_dict
-                cell_list = list(map(lambda c: c.name, original_cells.values()))
-                # required libs
-                multi_libs = {
-                    "L": {
-                        "lib": self.gds_tool.GdsLibrary(),
-                        "mvt_layer": 98
-                        },
-                    "SL": {
-                        "lib": self.gds_tool.GdsLibrary(),
-                        "mvt_layer": 97
-                        },
-                    "SRAM": {
-                        "lib": self.gds_tool.GdsLibrary(),
-                        "mvt_layer": 110
-                        },
-                }
-                # create new libs
-                for vt, multi_lib in multi_libs.items():
-                    multi_lib['lib'].name = asap7_original_gds.name.replace('R', vt)
-
-                for cell in original_cells.values():
-                    poly_dict = cell.get_polygons(by_spec=True)
-                    # extract polygon from layer 100(the boundary for cell)
-                    boundary_polygon = poly_dict[(100, 0)]
-                    for vt, multi_lib in multi_libs.items():
-                        new_cell_name = cell.name.rstrip('R') + vt
-                        cell_list.append(new_cell_name)
-                        mvt_layer = multi_lib['mvt_layer']
-                        # copy boundary_polygon to mvt_layer to mark the this cell is a mvt cell.
-                        mvt_polygon = self.gds_tool.PolygonSet(boundary_polygon, multi_lib['mvt_layer'], 0)
-                        mvt_cell = cell.copy(name=new_cell_name, exclude_from_current=True, deep_copy=True).add(mvt_polygon)
-                        # add mvt_cell to corresponding multi_lib
-                        multi_lib['lib'].add(mvt_cell)
-
-                for vt, multi_lib in multi_libs.items():
-                    # write multi_lib
-                    new_gds = os.path.basename(orig_gds).replace('R', vt)
-                    multi_lib['lib'].write_gds(os.path.join(self.cache_dir, 'GDS', new_gds))
-
-            # Write out cell list for scaling script
-            with open(os.path.join(self.cache_dir, 'stdcells.txt'), 'w') as f:
-                f.writelines('{}\n'.format(cell) for cell in cell_list)
-
-        except:
-            os.rmdir(os.path.join(self.cache_dir, "GDS"))
-            self.logger.error("GDS patching failed! Check your gdstk, gdspy, and/or ASAP7 PDK installation.")
-            sys.exit()
-
-    def fix_icg_libs(self) -> None:
-        """
-        ICG cells are missing statetable.
-        """
-        try:
-            os.makedirs(os.path.join(self.cache_dir, "LIB/NLDM"))
-        except:
-            self.logger.info("ICG LIBs already fixed")
-            return None
-
-        try:
-            self.logger.info("Fixing ICG LIBs...")
-            statetable_text = "\\n".join([
-               '\    statetable ("CLK ENA SE", "IQ") {',
-                '      table : "L L L : - : L ,  L L H : - : H , L H L : - : H , L H H : - : H , H - - : - : N ";',
-                '    }'])
-            gclk_func = "CLK & IQ"
-            lib_dir = os.path.join(self.get_setting("technology.asap7.stdcell_install_dir"), "LIB/NLDM")
-            old_libs = glob.glob(os.path.join(lib_dir, "*SEQ*"))
-            new_libs = list(map(lambda l: os.path.join(self.cache_dir, "LIB/NLDM", os.path.basename(l)), old_libs))
-
-            for olib, nlib in zip(old_libs, new_libs):
-                # Use gzip and sed directly rather than gzip python module
-                # Add the statetable to ICG cells
-                # Change function to state_function for pin GCLK
-                subprocess.call(["gzip -cd {olib} | sed '/ICGx*/a {stbl}' | sed '/CLK & IQ/s/function/state_function/g' | gzip > {nlib}".format(olib=olib, stbl=statetable_text, nlib=nlib)], shell=True)
-        except:
-            os.rmdir(os.path.join(self.cache_dir, "LIB/NLDM"))
-            os.rmdir(os.path.join(self.cache_dir, "LIB"))
-            self.logger.error("Failed to fix ICG LIBs. Check your ASAP7 installation!")
-            sys.exit()
-
-    def get_tech_par_hooks(self, tool_name: str) -> List[HammerToolHookAction]:
-        hooks = {"innovus": [
-            HammerTool.make_post_persistent_hook("init_design", asap7_innovus_settings),
-            HammerTool.make_post_insertion_hook("floorplan_design", asap7_update_floorplan),
-            HammerTool.make_post_insertion_hook("write_design", asap7_scale_final_gds)
-            ]}
-        return hooks.get(tool_name, [])
-
-    def get_tech_drc_hooks(self, tool_name: str) -> List[HammerToolHookAction]:
-        hooks = {"calibre": [
-            HammerTool.make_replacement_hook("generate_drc_run_file", asap7_generate_drc_run_file)
-            ]}
-        return hooks.get(tool_name, [])
 
 def asap7_innovus_settings(ht: HammerTool) -> bool:
     assert isinstance(ht, HammerPlaceAndRouteTool), "Innovus settings only for par"
@@ -244,16 +85,13 @@ def asap7_scale_final_gds(ht: HammerTool) -> bool:
     Scale the final GDS by a factor of 4
     scale_gds_script writes the actual Python script to execute from the Tcl interpreter
     """
-    # This is from the Cadence tools
-    cadence_output_gds_name = ht.output_gds_filename  # type: ignore
-
     ht.append('''
 # Innovus <19.1 appends some bad LD_LIBRARY_PATHS, so remove them before executing python
 set env(LD_LIBRARY_PATH) [join [lsearch -not -all -inline [split $env(LD_LIBRARY_PATH) ":"] "*INNOVUS*"] ":"]
 {scale_script} {stdcells_file} {gds_file}
 '''.format(scale_script = os.path.join(os.path.dirname(__file__), 'gds_scale.py'),
            stdcells_file = os.path.join(ht.technology.cache_dir, 'stdcells.txt'),
-           gds_file = cadence_output_gds_name))
+           gds_file = ht.output_gds_filename))
     return True
 
 def asap7_generate_drc_run_file(ht: HammerTool) -> bool:
@@ -263,17 +101,12 @@ def asap7_generate_drc_run_file(ht: HammerTool) -> bool:
     Replace drc_run_file to prevent conflicting SVRF statements
     Symlink DRC GDS to test.gds as expected by deck and results directories
     """
-    # These are from the Calibre tools
-    ht_drc_run_file = ht.drc_run_file  # type: ignore
-    ht_max_drc_results = ht.max_drc_results  # type: ignore
-    ht_virtual_connect_colon = ht.virtual_connect_colon  # type: ignore
-
     new_layout_file = os.path.join(ht.run_dir, 'test.gds')
     if not os.path.lexists(new_layout_file):
         os.symlink(os.path.splitext(ht.layout_file)[0] + '_drc.gds', new_layout_file)
     ht.layout_file = new_layout_file
 
-    with open(ht_drc_run_file, "w") as f:
+    with open(ht.drc_run_file, "w") as f:
         f.write(textwrap.dedent("""
         // Generated by HAMMER
 
@@ -285,8 +118,8 @@ def asap7_generate_drc_run_file(ht: HammerTool) -> bool:
         VIRTUAL CONNECT COLON {virtual_connect}
         VIRTUAL CONNECT REPORT NO
         """).format(
-            max_results=ht_max_drc_results,
-            virtual_connect="YES" if ht_virtual_connect_colon else "NO"
+            max_results=ht.max_drc_results,
+            virtual_connect="YES" if ht.virtual_connect_colon else "NO"
         )
         )
         # Include paths to all supplied decks
diff --git a/src/hammer-vlsi/technology/asap7/asap7.tech.json b/src/hammer-vlsi/technology/asap7/asap7.tech.json
index fdb8a2f86..3c14ea9f1 100644
--- a/src/hammer-vlsi/technology/asap7/asap7.tech.json
+++ b/src/hammer-vlsi/technology/asap7/asap7.tech.json
@@ -53,11 +53,11 @@
       ]
     },
     {
-      "nldm liberty file": "$STDCELLS/LIB/NLDM/asap7sc7p5t_SIMPLE_RVT_TT_nldm_201020.lib.gz",
+      "nldm liberty file": "$STDCELLS/LIB/NLDM/asap7sc7p5t_SIMPLE_RVT_TT_nldm_211120.lib.gz",
       "verilog sim": "$STDCELLS/Verilog/asap7sc7p5t_SIMPLE_RVT_TT_201020.v",
-      "lef file": "$STDCELLS/LEF/scaled/asap7sc7p5t_27_R_4x_201211.lef",
-      "spice file": "$STDCELLS/CDL/LVS/asap7sc7p5t_27_R.cdl",
-      "gds file": "$STDCELLS/GDS/asap7sc7p5t_27_R_201211.gds",
+      "lef file": "$STDCELLS/LEF/scaled/asap7sc7p5t_28_R_4x_220121a.lef",
+      "spice file": "$STDCELLS/CDL/LVS/asap7sc7p5t_28_R.cdl",
+      "gds file": "$STDCELLS/GDS/asap7sc7p5t_28_R_220121a.gds",
       "qrc techfile": "$STDCELLS/qrc/qrcTechFile_typ03_scaled4xV06",
       "spice model file": {
         "path": "$PDK/models/hspice/7nm_TT.pm"
@@ -79,10 +79,10 @@
       ]
     },
     {
-      "nldm liberty file": "$STDCELLS/LIB/NLDM/asap7sc7p5t_SIMPLE_RVT_SS_nldm_201020.lib.gz",
-      "lef file": "$STDCELLS/LEF/scaled/asap7sc7p5t_27_R_4x_201211.lef",
-      "spice file": "$STDCELLS/CDL/LVS/asap7sc7p5t_27_R.cdl",
-      "gds file": "$STDCELLS/GDS/asap7sc7p5t_27_R_201211.gds",
+      "nldm liberty file": "$STDCELLS/LIB/NLDM/asap7sc7p5t_SIMPLE_RVT_SS_nldm_211120.lib.gz",
+      "lef file": "$STDCELLS/LEF/scaled/asap7sc7p5t_28_R_4x_220121a.lef",
+      "spice file": "$STDCELLS/CDL/LVS/asap7sc7p5t_28_R.cdl",
+      "gds file": "$STDCELLS/GDS/asap7sc7p5t_28_R_220121a.gds",
       "qrc techfile": "$STDCELLS/qrc/qrcTechFile_typ03_scaled4xV06",
       "spice model file": {
         "path": "$PDK/models/hspice/7nm_SS.pm"
@@ -104,10 +104,10 @@
       ]
     },
     {
-      "nldm liberty file": "$STDCELLS/LIB/NLDM/asap7sc7p5t_SIMPLE_RVT_FF_nldm_201020.lib.gz",
-      "lef file": "$STDCELLS/LEF/scaled/asap7sc7p5t_27_R_4x_201211.lef",
-      "spice file": "$STDCELLS/CDL/LVS/asap7sc7p5t_27_R.cdl",
-      "gds file": "$STDCELLS/GDS/asap7sc7p5t_27_R_201211.gds",
+      "nldm liberty file": "$STDCELLS/LIB/NLDM/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz",
+      "lef file": "$STDCELLS/LEF/scaled/asap7sc7p5t_28_R_4x_220121a.lef",
+      "spice file": "$STDCELLS/CDL/LVS/asap7sc7p5t_28_R.cdl",
+      "gds file": "$STDCELLS/GDS/asap7sc7p5t_28_R_220121a.gds",
       "qrc techfile": "$STDCELLS/qrc/qrcTechFile_typ03_scaled4xV06",
       "spice model file": {
         "path": "$PDK/models/hspice/7nm_FF.pm"
@@ -129,11 +129,11 @@
       ]
     },
     {
-      "nldm liberty file": "$STDCELLS/LIB/NLDM/asap7sc7p5t_SIMPLE_LVT_TT_nldm_201020.lib.gz",
+      "nldm liberty file": "$STDCELLS/LIB/NLDM/asap7sc7p5t_SIMPLE_LVT_TT_nldm_211120.lib.gz",
       "verilog sim": "$STDCELLS/Verilog/asap7sc7p5t_SIMPLE_LVT_TT_201020.v",
-      "lef file": "$STDCELLS/LEF/scaled/asap7sc7p5t_27_L_4x_201211.lef",
-      "spice file": "$STDCELLS/CDL/LVS/asap7sc7p5t_27_L.cdl",
-      "gds file": "tech-asap7-cache/GDS/asap7sc7p5t_27_L_201211.gds",
+      "lef file": "$STDCELLS/LEF/scaled/asap7sc7p5t_28_L_4x_220121a.lef",
+      "spice file": "$STDCELLS/CDL/LVS/asap7sc7p5t_28_L.cdl",
+      "gds file": "$STDCELLS/GDS/asap7sc7p5t_28_L_220121a.gds",
       "qrc techfile": "$STDCELLS/qrc/qrcTechFile_typ03_scaled4xV06",
       "spice model file": {
         "path": "$PDK/models/hspice/7nm_TT.pm"
@@ -155,10 +155,10 @@
       ]
     },
     {
-      "nldm liberty file": "$STDCELLS/LIB/NLDM/asap7sc7p5t_SIMPLE_LVT_SS_nldm_201020.lib.gz",
-      "lef file": "$STDCELLS/LEF/scaled/asap7sc7p5t_27_L_4x_201211.lef",
-      "spice file": "$STDCELLS/CDL/LVS/asap7sc7p5t_27_L.cdl",
-      "gds file": "tech-asap7-cache/GDS/asap7sc7p5t_27_L_201211.gds",
+      "nldm liberty file": "$STDCELLS/LIB/NLDM/asap7sc7p5t_SIMPLE_LVT_SS_nldm_211120.lib.gz",
+      "lef file": "$STDCELLS/LEF/scaled/asap7sc7p5t_28_L_4x_220121a.lef",
+      "spice file": "$STDCELLS/CDL/LVS/asap7sc7p5t_28_L.cdl",
+      "gds file": "$STDCELLS/GDS/asap7sc7p5t_28_L_220121a.gds",
       "qrc techfile": "$STDCELLS/qrc/qrcTechFile_typ03_scaled4xV06",
       "spice model file": {
         "path": "$PDK/models/hspice/7nm_SS.pm"
@@ -180,10 +180,10 @@
       ]
     },
     {
-      "nldm liberty file": "$STDCELLS/LIB/NLDM/asap7sc7p5t_SIMPLE_LVT_FF_nldm_201020.lib.gz",
-      "lef file": "$STDCELLS/LEF/scaled/asap7sc7p5t_27_L_4x_201211.lef",
-      "spice file": "$STDCELLS/CDL/LVS/asap7sc7p5t_27_L.cdl",
-      "gds file": "tech-asap7-cache/GDS/asap7sc7p5t_27_L_201211.gds",
+      "nldm liberty file": "$STDCELLS/LIB/NLDM/asap7sc7p5t_SIMPLE_LVT_FF_nldm_211120.lib.gz",
+      "lef file": "$STDCELLS/LEF/scaled/asap7sc7p5t_28_L_4x_220121a.lef",
+      "spice file": "$STDCELLS/CDL/LVS/asap7sc7p5t_28_L.cdl",
+      "gds file": "$STDCELLS/GDS/asap7sc7p5t_28_L_220121a.gds",
       "qrc techfile": "$STDCELLS/qrc/qrcTechFile_typ03_scaled4xV06",
       "spice model file": {
         "path": "$PDK/models/hspice/7nm_FF.pm"
@@ -205,11 +205,11 @@
       ]
     },
     {
-      "nldm liberty file": "$STDCELLS/LIB/NLDM/asap7sc7p5t_SIMPLE_SLVT_TT_nldm_201020.lib.gz",
+      "nldm liberty file": "$STDCELLS/LIB/NLDM/asap7sc7p5t_SIMPLE_SLVT_TT_nldm_211120.lib.gz",
       "verilog sim": "$STDCELLS/Verilog/asap7sc7p5t_SIMPLE_SLVT_TT_201020.v",
-      "lef file": "$STDCELLS/LEF/scaled/asap7sc7p5t_27_SL_4x_201211.lef",
-      "spice file": "$STDCELLS/CDL/LVS/asap7sc7p5t_27_SL.cdl",
-      "gds file": "tech-asap7-cache/GDS/asap7sc7p5t_27_SL_201211.gds",
+      "lef file": "$STDCELLS/LEF/scaled/asap7sc7p5t_28_SL_4x_220121a.lef",
+      "spice file": "$STDCELLS/CDL/LVS/asap7sc7p5t_28_SL.cdl",
+      "gds file": "$STDCELLS/GDS/asap7sc7p5t_28_SL_220121a.gds",
       "qrc techfile": "$STDCELLS/qrc/qrcTechFile_typ03_scaled4xV06",
       "spice model file": {
         "path": "$PDK/models/hspice/7nm_TT.pm"
@@ -231,10 +231,10 @@
       ]
     },
     {
-      "nldm liberty file": "$STDCELLS/LIB/NLDM/asap7sc7p5t_SIMPLE_SLVT_SS_nldm_201020.lib.gz",
-      "lef file": "$STDCELLS/LEF/scaled/asap7sc7p5t_27_SL_4x_201211.lef",
-      "spice file": "$STDCELLS/CDL/LVS/asap7sc7p5t_27_SL.cdl",
-      "gds file": "tech-asap7-cache/GDS/asap7sc7p5t_27_SL_201211.gds",
+      "nldm liberty file": "$STDCELLS/LIB/NLDM/asap7sc7p5t_SIMPLE_SLVT_SS_nldm_211120.lib.gz",
+      "lef file": "$STDCELLS/LEF/scaled/asap7sc7p5t_28_SL_4x_220121a.lef",
+      "spice file": "$STDCELLS/CDL/LVS/asap7sc7p5t_28_SL.cdl",
+      "gds file": "$STDCELLS/GDS/asap7sc7p5t_28_SL_220121a.gds",
       "qrc techfile": "$STDCELLS/qrc/qrcTechFile_typ03_scaled4xV06",
       "spice model file": {
         "path": "$PDK/models/hspice/7nm_SS.pm"
@@ -256,10 +256,10 @@
       ]
     },
     {
-      "nldm liberty file": "$STDCELLS/LIB/NLDM/asap7sc7p5t_SIMPLE_SLVT_FF_nldm_201020.lib.gz",
-      "lef file": "$STDCELLS/LEF/scaled/asap7sc7p5t_27_SL_4x_201211.lef",
-      "spice file": "$STDCELLS/CDL/LVS/asap7sc7p5t_27_SL.cdl",
-      "gds file": "tech-asap7-cache/GDS/asap7sc7p5t_27_SL_201211.gds",
+      "nldm liberty file": "$STDCELLS/LIB/NLDM/asap7sc7p5t_SIMPLE_SLVT_FF_nldm_211120.lib.gz",
+      "lef file": "$STDCELLS/LEF/scaled/asap7sc7p5t_28_SL_4x_220121a.lef",
+      "spice file": "$STDCELLS/CDL/LVS/asap7sc7p5t_28_SL.cdl",
+      "gds file": "$STDCELLS/GDS/asap7sc7p5t_28_SL_220121a.gds",
       "qrc techfile": "$STDCELLS/qrc/qrcTechFile_typ03_scaled4xV06",
       "spice model file": {
         "path": "$PDK/models/hspice/7nm_FF.pm"
@@ -281,11 +281,11 @@
       ]
     },
     {
-      "nldm liberty file": "$STDCELLS/LIB/NLDM/asap7sc7p5t_SIMPLE_SRAM_TT_nldm_201020.lib.gz",
+      "nldm liberty file": "$STDCELLS/LIB/NLDM/asap7sc7p5t_SIMPLE_SRAM_TT_nldm_211120.lib.gz",
       "verilog sim": "$STDCELLS/Verilog/asap7sc7p5t_SIMPLE_SRAM_TT_201020.v",
-      "lef file": "$STDCELLS/LEF/scaled/asap7sc7p5t_27_SRAM_4x_201211.lef",
-      "spice file": "$STDCELLS/CDL/LVS/asap7sc7p5t_27_SRAM.cdl",
-      "gds file": "tech-asap7-cache/GDS/asap7sc7p5t_27_SRAM_201211.gds",
+      "lef file": "$STDCELLS/LEF/scaled/asap7sc7p5t_28_SRAM_4x_220121a.lef",
+      "spice file": "$STDCELLS/CDL/LVS/asap7sc7p5t_28_SRAM.cdl",
+      "gds file": "$STDCELLS/GDS/asap7sc7p5t_28_SRAM_220121a.gds",
       "qrc techfile": "$STDCELLS/qrc/qrcTechFile_typ03_scaled4xV06",
       "spice model file": {
         "path": "$PDK/models/hspice/7nm_TT.pm"
@@ -301,10 +301,10 @@
       }
     },
     {
-      "nldm liberty file": "$STDCELLS/LIB/NLDM/asap7sc7p5t_SIMPLE_SRAM_SS_nldm_201020.lib.gz",
-      "lef file": "$STDCELLS/LEF/scaled/asap7sc7p5t_27_SRAM_4x_201211.lef",
-      "spice file": "$STDCELLS/CDL/LVS/asap7sc7p5t_27_SRAM.cdl",
-      "gds file": "tech-asap7-cache/GDS/asap7sc7p5t_27_SRAM_201211.gds",
+      "nldm liberty file": "$STDCELLS/LIB/NLDM/asap7sc7p5t_SIMPLE_SRAM_SS_nldm_211120.lib.gz",
+      "lef file": "$STDCELLS/LEF/scaled/asap7sc7p5t_28_SRAM_4x_220121a.lef",
+      "spice file": "$STDCELLS/CDL/LVS/asap7sc7p5t_28_SRAM.cdl",
+      "gds file": "$STDCELLS/GDS/asap7sc7p5t_28_SRAM_220121a.gds",
       "qrc techfile": "$STDCELLS/qrc/qrcTechFile_typ03_scaled4xV06",
       "spice model file": {
         "path": "$PDK/models/hspice/7nm_SS.pm"
@@ -320,10 +320,10 @@
       }
     },
     {
-      "nldm liberty file": "$STDCELLS/LIB/NLDM/asap7sc7p5t_SIMPLE_SRAM_FF_nldm_201020.lib.gz",
-      "lef file": "$STDCELLS/LEF/scaled/asap7sc7p5t_27_SRAM_4x_201211.lef",
-      "spice file": "$STDCELLS/CDL/LVS/asap7sc7p5t_27_SRAM.cdl",
-      "gds file": "tech-asap7-cache/GDS/asap7sc7p5t_27_SRAM_201211.gds",
+      "nldm liberty file": "$STDCELLS/LIB/NLDM/asap7sc7p5t_SIMPLE_SRAM_FF_nldm_211120.lib.gz",
+      "lef file": "$STDCELLS/LEF/scaled/asap7sc7p5t_28_SRAM_4x_220121a.lef",
+      "spice file": "$STDCELLS/CDL/LVS/asap7sc7p5t_28_SRAM.cdl",
+      "gds file": "$STDCELLS/GDS/asap7sc7p5t_28_SRAM_220121a.gds",
       "qrc techfile": "$STDCELLS/qrc/qrcTechFile_typ03_scaled4xV06",
       "spice model file": {
         "path": "$PDK/models/hspice/7nm_FF.pm"
@@ -339,11 +339,11 @@
       }
     },
     {
-      "nldm liberty file": "$STDCELLS/LIB/NLDM/asap7sc7p5t_AO_RVT_TT_nldm_201020.lib.gz",
+      "nldm liberty file": "$STDCELLS/LIB/NLDM/asap7sc7p5t_AO_RVT_TT_nldm_211120.lib.gz",
       "verilog sim": "$STDCELLS/Verilog/asap7sc7p5t_AO_RVT_TT_201020.v",
-      "lef file": "$STDCELLS/LEF/scaled/asap7sc7p5t_27_R_4x_201211.lef",
-      "spice file": "$STDCELLS/CDL/LVS/asap7sc7p5t_27_R.cdl",
-      "gds file": "$STDCELLS/GDS/asap7sc7p5t_27_R_201211.gds",
+      "lef file": "$STDCELLS/LEF/scaled/asap7sc7p5t_28_R_4x_220121a.lef",
+      "spice file": "$STDCELLS/CDL/LVS/asap7sc7p5t_28_R.cdl",
+      "gds file": "$STDCELLS/GDS/asap7sc7p5t_28_R_220121a.gds",
       "qrc techfile": "$STDCELLS/qrc/qrcTechFile_typ03_scaled4xV06",
       "corner": {
         "nmos": "typical",
@@ -362,10 +362,10 @@
       ]
     },
     {
-      "nldm liberty file": "$STDCELLS/LIB/NLDM/asap7sc7p5t_AO_RVT_SS_nldm_201020.lib.gz",
-      "lef file": "$STDCELLS/LEF/scaled/asap7sc7p5t_27_R_4x_201211.lef",
-      "spice file": "$STDCELLS/CDL/LVS/asap7sc7p5t_27_R.cdl",
-      "gds file": "$STDCELLS/GDS/asap7sc7p5t_27_R_201211.gds",
+      "nldm liberty file": "$STDCELLS/LIB/NLDM/asap7sc7p5t_AO_RVT_SS_nldm_211120.lib.gz",
+      "lef file": "$STDCELLS/LEF/scaled/asap7sc7p5t_28_R_4x_220121a.lef",
+      "spice file": "$STDCELLS/CDL/LVS/asap7sc7p5t_28_R.cdl",
+      "gds file": "$STDCELLS/GDS/asap7sc7p5t_28_R_220121a.gds",
       "qrc techfile": "$STDCELLS/qrc/qrcTechFile_typ03_scaled4xV06",
       "corner": {
         "nmos": "slow",
@@ -384,10 +384,10 @@
       ]
     },
     {
-      "nldm liberty file": "$STDCELLS/LIB/NLDM/asap7sc7p5t_AO_RVT_FF_nldm_201020.lib.gz",
-      "lef file": "$STDCELLS/LEF/scaled/asap7sc7p5t_27_R_4x_201211.lef",
-      "spice file": "$STDCELLS/CDL/LVS/asap7sc7p5t_27_R.cdl",
-      "gds file": "$STDCELLS/GDS/asap7sc7p5t_27_R_201211.gds",
+      "nldm liberty file": "$STDCELLS/LIB/NLDM/asap7sc7p5t_AO_RVT_FF_nldm_211120.lib.gz",
+      "lef file": "$STDCELLS/LEF/scaled/asap7sc7p5t_28_R_4x_220121a.lef",
+      "spice file": "$STDCELLS/CDL/LVS/asap7sc7p5t_28_R.cdl",
+      "gds file": "$STDCELLS/GDS/asap7sc7p5t_28_R_220121a.gds",
       "qrc techfile": "$STDCELLS/qrc/qrcTechFile_typ03_scaled4xV06",
       "corner": {
         "nmos": "fast",
@@ -406,11 +406,11 @@
       ]
     },
     {
-      "nldm liberty file": "$STDCELLS/LIB/NLDM/asap7sc7p5t_AO_LVT_TT_nldm_201020.lib.gz",
+      "nldm liberty file": "$STDCELLS/LIB/NLDM/asap7sc7p5t_AO_LVT_TT_nldm_211120.lib.gz",
       "verilog sim": "$STDCELLS/Verilog/asap7sc7p5t_AO_LVT_TT_201020.v",
-      "lef file": "$STDCELLS/LEF/scaled/asap7sc7p5t_27_L_4x_201211.lef",
-      "spice file": "$STDCELLS/CDL/LVS/asap7sc7p5t_27_L.cdl",
-      "gds file": "tech-asap7-cache/GDS/asap7sc7p5t_27_L_201211.gds",
+      "lef file": "$STDCELLS/LEF/scaled/asap7sc7p5t_28_L_4x_220121a.lef",
+      "spice file": "$STDCELLS/CDL/LVS/asap7sc7p5t_28_L.cdl",
+      "gds file": "$STDCELLS/GDS/asap7sc7p5t_28_L_220121a.gds",
       "qrc techfile": "$STDCELLS/qrc/qrcTechFile_typ03_scaled4xV06",
       "corner": {
         "nmos": "typical",
@@ -429,10 +429,10 @@
       ]
     },
     {
-      "nldm liberty file": "$STDCELLS/LIB/NLDM/asap7sc7p5t_AO_LVT_SS_nldm_201020.lib.gz",
-      "lef file": "$STDCELLS/LEF/scaled/asap7sc7p5t_27_L_4x_201211.lef",
-      "spice file": "$STDCELLS/CDL/LVS/asap7sc7p5t_27_L.cdl",
-      "gds file": "tech-asap7-cache/GDS/asap7sc7p5t_27_L_201211.gds",
+      "nldm liberty file": "$STDCELLS/LIB/NLDM/asap7sc7p5t_AO_LVT_SS_nldm_211120.lib.gz",
+      "lef file": "$STDCELLS/LEF/scaled/asap7sc7p5t_28_L_4x_220121a.lef",
+      "spice file": "$STDCELLS/CDL/LVS/asap7sc7p5t_28_L.cdl",
+      "gds file": "$STDCELLS/GDS/asap7sc7p5t_28_L_220121a.gds",
       "qrc techfile": "$STDCELLS/qrc/qrcTechFile_typ03_scaled4xV06",
       "corner": {
         "nmos": "slow",
@@ -451,10 +451,10 @@
       ]
     },
     {
-      "nldm liberty file": "$STDCELLS/LIB/NLDM/asap7sc7p5t_AO_LVT_FF_nldm_201020.lib.gz",
-      "lef file": "$STDCELLS/LEF/scaled/asap7sc7p5t_27_L_4x_201211.lef",
-      "spice file": "$STDCELLS/CDL/LVS/asap7sc7p5t_27_L.cdl",
-      "gds file": "tech-asap7-cache/GDS/asap7sc7p5t_27_L_201211.gds",
+      "nldm liberty file": "$STDCELLS/LIB/NLDM/asap7sc7p5t_AO_LVT_FF_nldm_211120.lib.gz",
+      "lef file": "$STDCELLS/LEF/scaled/asap7sc7p5t_28_L_4x_220121a.lef",
+      "spice file": "$STDCELLS/CDL/LVS/asap7sc7p5t_28_L.cdl",
+      "gds file": "$STDCELLS/GDS/asap7sc7p5t_28_L_220121a.gds",
       "qrc techfile": "$STDCELLS/qrc/qrcTechFile_typ03_scaled4xV06",
       "corner": {
         "nmos": "fast",
@@ -473,11 +473,11 @@
       ]
     },
     {
-      "nldm liberty file": "$STDCELLS/LIB/NLDM/asap7sc7p5t_AO_SLVT_TT_nldm_201020.lib.gz",
+      "nldm liberty file": "$STDCELLS/LIB/NLDM/asap7sc7p5t_AO_SLVT_TT_nldm_211120.lib.gz",
       "verilog sim": "$STDCELLS/Verilog/asap7sc7p5t_AO_SLVT_TT_201020.v",
-      "lef file": "$STDCELLS/LEF/scaled/asap7sc7p5t_27_SL_4x_201211.lef",
-      "spice file": "$STDCELLS/CDL/LVS/asap7sc7p5t_27_SL.cdl",
-      "gds file": "tech-asap7-cache/GDS/asap7sc7p5t_27_SL_201211.gds",
+      "lef file": "$STDCELLS/LEF/scaled/asap7sc7p5t_28_SL_4x_220121a.lef",
+      "spice file": "$STDCELLS/CDL/LVS/asap7sc7p5t_28_SL.cdl",
+      "gds file": "$STDCELLS/GDS/asap7sc7p5t_28_SL_220121a.gds",
       "qrc techfile": "$STDCELLS/qrc/qrcTechFile_typ03_scaled4xV06",
       "corner": {
         "nmos": "typical",
@@ -496,10 +496,10 @@
       ]
     },
     {
-      "nldm liberty file": "$STDCELLS/LIB/NLDM/asap7sc7p5t_AO_SLVT_SS_nldm_201020.lib.gz",
-      "lef file": "$STDCELLS/LEF/scaled/asap7sc7p5t_27_SL_4x_201211.lef",
-      "spice file": "$STDCELLS/CDL/LVS/asap7sc7p5t_27_SL.cdl",
-      "gds file": "tech-asap7-cache/GDS/asap7sc7p5t_27_SL_201211.gds",
+      "nldm liberty file": "$STDCELLS/LIB/NLDM/asap7sc7p5t_AO_SLVT_SS_nldm_211120.lib.gz",
+      "lef file": "$STDCELLS/LEF/scaled/asap7sc7p5t_28_SL_4x_220121a.lef",
+      "spice file": "$STDCELLS/CDL/LVS/asap7sc7p5t_28_SL.cdl",
+      "gds file": "$STDCELLS/GDS/asap7sc7p5t_28_SL_220121a.gds",
       "qrc techfile": "$STDCELLS/qrc/qrcTechFile_typ03_scaled4xV06",
       "corner": {
         "nmos": "slow",
@@ -518,10 +518,10 @@
       ]
     },
     {
-      "nldm liberty file": "$STDCELLS/LIB/NLDM/asap7sc7p5t_AO_SLVT_FF_nldm_201020.lib.gz",
-      "lef file": "$STDCELLS/LEF/scaled/asap7sc7p5t_27_SL_4x_201211.lef",
-      "spice file": "$STDCELLS/CDL/LVS/asap7sc7p5t_27_SL.cdl",
-      "gds file": "tech-asap7-cache/GDS/asap7sc7p5t_27_SL_201211.gds",
+      "nldm liberty file": "$STDCELLS/LIB/NLDM/asap7sc7p5t_AO_SLVT_FF_nldm_211120.lib.gz",
+      "lef file": "$STDCELLS/LEF/scaled/asap7sc7p5t_28_SL_4x_220121a.lef",
+      "spice file": "$STDCELLS/CDL/LVS/asap7sc7p5t_28_SL.cdl",
+      "gds file": "$STDCELLS/GDS/asap7sc7p5t_28_SL_220121a.gds",
       "qrc techfile": "$STDCELLS/qrc/qrcTechFile_typ03_scaled4xV06",
       "corner": {
         "nmos": "fast",
@@ -540,11 +540,11 @@
       ]
     },
     {
-      "nldm liberty file": "$STDCELLS/LIB/NLDM/asap7sc7p5t_AO_SRAM_TT_nldm_201020.lib.gz",
+      "nldm liberty file": "$STDCELLS/LIB/NLDM/asap7sc7p5t_AO_SRAM_TT_nldm_211120.lib.gz",
       "verilog sim": "$STDCELLS/Verilog/asap7sc7p5t_AO_SRAM_TT_201020.v",
-      "lef file": "$STDCELLS/LEF/scaled/asap7sc7p5t_27_SRAM_4x_201211.lef",
-      "spice file": "$STDCELLS/CDL/LVS/asap7sc7p5t_27_SRAM.cdl",
-      "gds file": "tech-asap7-cache/GDS/asap7sc7p5t_27_SRAM_201211.gds",
+      "lef file": "$STDCELLS/LEF/scaled/asap7sc7p5t_28_SRAM_4x_220121a.lef",
+      "spice file": "$STDCELLS/CDL/LVS/asap7sc7p5t_28_SRAM.cdl",
+      "gds file": "$STDCELLS/GDS/asap7sc7p5t_28_SRAM_220121a.gds",
       "qrc techfile": "$STDCELLS/qrc/qrcTechFile_typ03_scaled4xV06",
       "corner": {
         "nmos": "typical",
@@ -557,10 +557,10 @@
       }
     },
     {
-      "nldm liberty file": "$STDCELLS/LIB/NLDM/asap7sc7p5t_AO_SRAM_SS_nldm_201020.lib.gz",
-      "lef file": "$STDCELLS/LEF/scaled/asap7sc7p5t_27_SRAM_4x_201211.lef",
-      "spice file": "$STDCELLS/CDL/LVS/asap7sc7p5t_27_SRAM.cdl",
-      "gds file": "tech-asap7-cache/GDS/asap7sc7p5t_27_SRAM_201211.gds",
+      "nldm liberty file": "$STDCELLS/LIB/NLDM/asap7sc7p5t_AO_SRAM_SS_nldm_211120.lib.gz",
+      "lef file": "$STDCELLS/LEF/scaled/asap7sc7p5t_28_SRAM_4x_220121a.lef",
+      "spice file": "$STDCELLS/CDL/LVS/asap7sc7p5t_28_SRAM.cdl",
+      "gds file": "$STDCELLS/GDS/asap7sc7p5t_28_SRAM_220121a.gds",
       "qrc techfile": "$STDCELLS/qrc/qrcTechFile_typ03_scaled4xV06",
       "corner": {
         "nmos": "slow",
@@ -573,10 +573,10 @@
       }
     },
     {
-      "nldm liberty file": "$STDCELLS/LIB/NLDM/asap7sc7p5t_AO_SRAM_FF_nldm_201020.lib.gz",
-      "lef file": "$STDCELLS/LEF/scaled/asap7sc7p5t_27_SRAM_4x_201211.lef",
-      "spice file": "$STDCELLS/CDL/LVS/asap7sc7p5t_27_SRAM.cdl",
-      "gds file": "tech-asap7-cache/GDS/asap7sc7p5t_27_SRAM_201211.gds",
+      "nldm liberty file": "$STDCELLS/LIB/NLDM/asap7sc7p5t_AO_SRAM_FF_nldm_211120.lib.gz",
+      "lef file": "$STDCELLS/LEF/scaled/asap7sc7p5t_28_SRAM_4x_220121a.lef",
+      "spice file": "$STDCELLS/CDL/LVS/asap7sc7p5t_28_SRAM.cdl",
+      "gds file": "$STDCELLS/GDS/asap7sc7p5t_28_SRAM_220121a.gds",
       "qrc techfile": "$STDCELLS/qrc/qrcTechFile_typ03_scaled4xV06",
       "corner": {
         "nmos": "fast",
@@ -589,11 +589,11 @@
       }
     },
     {
-      "nldm liberty file": "$STDCELLS/LIB/NLDM/asap7sc7p5t_OA_RVT_TT_nldm_201020.lib.gz",
+      "nldm liberty file": "$STDCELLS/LIB/NLDM/asap7sc7p5t_OA_RVT_TT_nldm_211120.lib.gz",
       "verilog sim": "$STDCELLS/Verilog/asap7sc7p5t_OA_RVT_TT_201020.v",
-      "lef file": "$STDCELLS/LEF/scaled/asap7sc7p5t_27_R_4x_201211.lef",
-      "spice file": "$STDCELLS/CDL/LVS/asap7sc7p5t_27_R.cdl",
-      "gds file": "$STDCELLS/GDS/asap7sc7p5t_27_R_201211.gds",
+      "lef file": "$STDCELLS/LEF/scaled/asap7sc7p5t_28_R_4x_220121a.lef",
+      "spice file": "$STDCELLS/CDL/LVS/asap7sc7p5t_28_R.cdl",
+      "gds file": "$STDCELLS/GDS/asap7sc7p5t_28_R_220121a.gds",
       "qrc techfile": "$STDCELLS/qrc/qrcTechFile_typ03_scaled4xV06",
       "corner": {
         "nmos": "typical",
@@ -612,10 +612,10 @@
       ]
     },
     {
-      "nldm liberty file": "$STDCELLS/LIB/NLDM/asap7sc7p5t_OA_RVT_SS_nldm_201020.lib.gz",
-      "lef file": "$STDCELLS/LEF/scaled/asap7sc7p5t_27_R_4x_201211.lef",
-      "spice file": "$STDCELLS/CDL/LVS/asap7sc7p5t_27_R.cdl",
-      "gds file": "$STDCELLS/GDS/asap7sc7p5t_27_R_201211.gds",
+      "nldm liberty file": "$STDCELLS/LIB/NLDM/asap7sc7p5t_OA_RVT_SS_nldm_211120.lib.gz",
+      "lef file": "$STDCELLS/LEF/scaled/asap7sc7p5t_28_R_4x_220121a.lef",
+      "spice file": "$STDCELLS/CDL/LVS/asap7sc7p5t_28_R.cdl",
+      "gds file": "$STDCELLS/GDS/asap7sc7p5t_28_R_220121a.gds",
       "qrc techfile": "$STDCELLS/qrc/qrcTechFile_typ03_scaled4xV06",
       "corner": {
         "nmos": "slow",
@@ -634,10 +634,10 @@
       ]
     },
     {
-      "nldm liberty file": "$STDCELLS/LIB/NLDM/asap7sc7p5t_OA_RVT_FF_nldm_201020.lib.gz",
-      "lef file": "$STDCELLS/LEF/scaled/asap7sc7p5t_27_R_4x_201211.lef",
-      "spice file": "$STDCELLS/CDL/LVS/asap7sc7p5t_27_R.cdl",
-      "gds file": "$STDCELLS/GDS/asap7sc7p5t_27_R_201211.gds",
+      "nldm liberty file": "$STDCELLS/LIB/NLDM/asap7sc7p5t_OA_RVT_FF_nldm_211120.lib.gz",
+      "lef file": "$STDCELLS/LEF/scaled/asap7sc7p5t_28_R_4x_220121a.lef",
+      "spice file": "$STDCELLS/CDL/LVS/asap7sc7p5t_28_R.cdl",
+      "gds file": "$STDCELLS/GDS/asap7sc7p5t_28_R_220121a.gds",
       "qrc techfile": "$STDCELLS/qrc/qrcTechFile_typ03_scaled4xV06",
       "corner": {
         "nmos": "fast",
@@ -656,11 +656,11 @@
       ]
     },
     {
-      "nldm liberty file": "$STDCELLS/LIB/NLDM/asap7sc7p5t_OA_LVT_TT_nldm_201020.lib.gz",
+      "nldm liberty file": "$STDCELLS/LIB/NLDM/asap7sc7p5t_OA_LVT_TT_nldm_211120.lib.gz",
       "verilog sim": "$STDCELLS/Verilog/asap7sc7p5t_OA_LVT_TT_201020.v",
-      "lef file": "$STDCELLS/LEF/scaled/asap7sc7p5t_27_L_4x_201211.lef",
-      "spice file": "$STDCELLS/CDL/LVS/asap7sc7p5t_27_L.cdl",
-      "gds file": "tech-asap7-cache/GDS/asap7sc7p5t_27_L_201211.gds",
+      "lef file": "$STDCELLS/LEF/scaled/asap7sc7p5t_28_L_4x_220121a.lef",
+      "spice file": "$STDCELLS/CDL/LVS/asap7sc7p5t_28_L.cdl",
+      "gds file": "$STDCELLS/GDS/asap7sc7p5t_28_L_220121a.gds",
       "qrc techfile": "$STDCELLS/qrc/qrcTechFile_typ03_scaled4xV06",
       "corner": {
         "nmos": "typical",
@@ -679,10 +679,10 @@
       ]
     },
     {
-      "nldm liberty file": "$STDCELLS/LIB/NLDM/asap7sc7p5t_OA_LVT_SS_nldm_201020.lib.gz",
-      "lef file": "$STDCELLS/LEF/scaled/asap7sc7p5t_27_L_4x_201211.lef",
-      "spice file": "$STDCELLS/CDL/LVS/asap7sc7p5t_27_L.cdl",
-      "gds file": "tech-asap7-cache/GDS/asap7sc7p5t_27_L_201211.gds",
+      "nldm liberty file": "$STDCELLS/LIB/NLDM/asap7sc7p5t_OA_LVT_SS_nldm_211120.lib.gz",
+      "lef file": "$STDCELLS/LEF/scaled/asap7sc7p5t_28_L_4x_220121a.lef",
+      "spice file": "$STDCELLS/CDL/LVS/asap7sc7p5t_28_L.cdl",
+      "gds file": "$STDCELLS/GDS/asap7sc7p5t_28_L_220121a.gds",
       "qrc techfile": "$STDCELLS/qrc/qrcTechFile_typ03_scaled4xV06",
       "corner": {
         "nmos": "slow",
@@ -701,10 +701,10 @@
       ]
     },
     {
-      "nldm liberty file": "$STDCELLS/LIB/NLDM/asap7sc7p5t_OA_LVT_FF_nldm_201020.lib.gz",
-      "lef file": "$STDCELLS/LEF/scaled/asap7sc7p5t_27_L_4x_201211.lef",
-      "spice file": "$STDCELLS/CDL/LVS/asap7sc7p5t_27_L.cdl",
-      "gds file": "tech-asap7-cache/GDS/asap7sc7p5t_27_L_201211.gds",
+      "nldm liberty file": "$STDCELLS/LIB/NLDM/asap7sc7p5t_OA_LVT_FF_nldm_211120.lib.gz",
+      "lef file": "$STDCELLS/LEF/scaled/asap7sc7p5t_28_L_4x_220121a.lef",
+      "spice file": "$STDCELLS/CDL/LVS/asap7sc7p5t_28_L.cdl",
+      "gds file": "$STDCELLS/GDS/asap7sc7p5t_28_L_220121a.gds",
       "qrc techfile": "$STDCELLS/qrc/qrcTechFile_typ03_scaled4xV06",
       "corner": {
         "nmos": "fast",
@@ -723,11 +723,11 @@
       ]
     },
     {
-      "nldm liberty file": "$STDCELLS/LIB/NLDM/asap7sc7p5t_OA_SLVT_TT_nldm_201020.lib.gz",
+      "nldm liberty file": "$STDCELLS/LIB/NLDM/asap7sc7p5t_OA_SLVT_TT_nldm_211120.lib.gz",
       "verilog sim": "$STDCELLS/Verilog/asap7sc7p5t_OA_SLVT_TT_201020.v",
-      "lef file": "$STDCELLS/LEF/scaled/asap7sc7p5t_27_SL_4x_201211.lef",
-      "spice file": "$STDCELLS/CDL/LVS/asap7sc7p5t_27_SL.cdl",
-      "gds file": "tech-asap7-cache/GDS/asap7sc7p5t_27_SL_201211.gds",
+      "lef file": "$STDCELLS/LEF/scaled/asap7sc7p5t_28_SL_4x_220121a.lef",
+      "spice file": "$STDCELLS/CDL/LVS/asap7sc7p5t_28_SL.cdl",
+      "gds file": "$STDCELLS/GDS/asap7sc7p5t_28_SL_220121a.gds",
       "qrc techfile": "$STDCELLS/qrc/qrcTechFile_typ03_scaled4xV06",
       "corner": {
         "nmos": "typical",
@@ -746,10 +746,10 @@
       ]
     },
     {
-      "nldm liberty file": "$STDCELLS/LIB/NLDM/asap7sc7p5t_OA_SLVT_SS_nldm_201020.lib.gz",
-      "lef file": "$STDCELLS/LEF/scaled/asap7sc7p5t_27_SL_4x_201211.lef",
-      "spice file": "$STDCELLS/CDL/LVS/asap7sc7p5t_27_SL.cdl",
-      "gds file": "tech-asap7-cache/GDS/asap7sc7p5t_27_SL_201211.gds",
+      "nldm liberty file": "$STDCELLS/LIB/NLDM/asap7sc7p5t_OA_SLVT_SS_nldm_211120.lib.gz",
+      "lef file": "$STDCELLS/LEF/scaled/asap7sc7p5t_28_SL_4x_220121a.lef",
+      "spice file": "$STDCELLS/CDL/LVS/asap7sc7p5t_28_SL.cdl",
+      "gds file": "$STDCELLS/GDS/asap7sc7p5t_28_SL_220121a.gds",
       "qrc techfile": "$STDCELLS/qrc/qrcTechFile_typ03_scaled4xV06",
       "corner": {
         "nmos": "slow",
@@ -768,10 +768,10 @@
       ]
     },
     {
-      "nldm liberty file": "$STDCELLS/LIB/NLDM/asap7sc7p5t_OA_SLVT_FF_nldm_201020.lib.gz",
-      "lef file": "$STDCELLS/LEF/scaled/asap7sc7p5t_27_SL_4x_201211.lef",
-      "spice file": "$STDCELLS/CDL/LVS/asap7sc7p5t_27_SL.cdl",
-      "gds file": "tech-asap7-cache/GDS/asap7sc7p5t_27_SL_201211.gds",
+      "nldm liberty file": "$STDCELLS/LIB/NLDM/asap7sc7p5t_OA_SLVT_FF_nldm_211120.lib.gz",
+      "lef file": "$STDCELLS/LEF/scaled/asap7sc7p5t_28_SL_4x_220121a.lef",
+      "spice file": "$STDCELLS/CDL/LVS/asap7sc7p5t_28_SL.cdl",
+      "gds file": "$STDCELLS/GDS/asap7sc7p5t_28_SL_220121a.gds",
       "qrc techfile": "$STDCELLS/qrc/qrcTechFile_typ03_scaled4xV06",
       "corner": {
         "nmos": "fast",
@@ -790,11 +790,11 @@
       ]
     },
     {
-      "nldm liberty file": "$STDCELLS/LIB/NLDM/asap7sc7p5t_OA_SRAM_TT_nldm_201020.lib.gz",
+      "nldm liberty file": "$STDCELLS/LIB/NLDM/asap7sc7p5t_OA_SRAM_TT_nldm_211120.lib.gz",
       "verilog sim": "$STDCELLS/Verilog/asap7sc7p5t_OA_SRAM_TT_201020.v",
-      "lef file": "$STDCELLS/LEF/scaled/asap7sc7p5t_27_SRAM_4x_201211.lef",
-      "spice file": "$STDCELLS/CDL/LVS/asap7sc7p5t_27_SRAM.cdl",
-      "gds file": "tech-asap7-cache/GDS/asap7sc7p5t_27_SRAM_201211.gds",
+      "lef file": "$STDCELLS/LEF/scaled/asap7sc7p5t_28_SRAM_4x_220121a.lef",
+      "spice file": "$STDCELLS/CDL/LVS/asap7sc7p5t_28_SRAM.cdl",
+      "gds file": "$STDCELLS/GDS/asap7sc7p5t_28_SRAM_220121a.gds",
       "qrc techfile": "$STDCELLS/qrc/qrcTechFile_typ03_scaled4xV06",
       "corner": {
         "nmos": "typical",
@@ -807,10 +807,10 @@
       }
     },
     {
-      "nldm liberty file": "$STDCELLS/LIB/NLDM/asap7sc7p5t_OA_SRAM_SS_nldm_201020.lib.gz",
-      "lef file": "$STDCELLS/LEF/scaled/asap7sc7p5t_27_SRAM_4x_201211.lef",
-      "spice file": "$STDCELLS/CDL/LVS/asap7sc7p5t_27_SRAM.cdl",
-      "gds file": "tech-asap7-cache/GDS/asap7sc7p5t_27_SRAM_201211.gds",
+      "nldm liberty file": "$STDCELLS/LIB/NLDM/asap7sc7p5t_OA_SRAM_SS_nldm_211120.lib.gz",
+      "lef file": "$STDCELLS/LEF/scaled/asap7sc7p5t_28_SRAM_4x_220121a.lef",
+      "spice file": "$STDCELLS/CDL/LVS/asap7sc7p5t_28_SRAM.cdl",
+      "gds file": "$STDCELLS/GDS/asap7sc7p5t_28_SRAM_220121a.gds",
       "qrc techfile": "$STDCELLS/qrc/qrcTechFile_typ03_scaled4xV06",
       "corner": {
         "nmos": "slow",
@@ -823,10 +823,10 @@
       }
     },
     {
-      "nldm liberty file": "$STDCELLS/LIB/NLDM/asap7sc7p5t_OA_SRAM_FF_nldm_201020.lib.gz",
-      "lef file": "$STDCELLS/LEF/scaled/asap7sc7p5t_27_SRAM_4x_201211.lef",
-      "spice file": "$STDCELLS/CDL/LVS/asap7sc7p5t_27_SRAM.cdl",
-      "gds file": "tech-asap7-cache/GDS/asap7sc7p5t_27_SRAM_201211.gds",
+      "nldm liberty file": "$STDCELLS/LIB/NLDM/asap7sc7p5t_OA_SRAM_FF_nldm_211120.lib.gz",
+      "lef file": "$STDCELLS/LEF/scaled/asap7sc7p5t_28_SRAM_4x_220121a.lef",
+      "spice file": "$STDCELLS/CDL/LVS/asap7sc7p5t_28_SRAM.cdl",
+      "gds file": "$STDCELLS/GDS/asap7sc7p5t_28_SRAM_220121a.gds",
       "qrc techfile": "$STDCELLS/qrc/qrcTechFile_typ03_scaled4xV06",
       "corner": {
         "nmos": "fast",
@@ -839,11 +839,11 @@
       }
     },
     {
-      "nldm liberty file": "tech-asap7-cache/LIB/NLDM/asap7sc7p5t_SEQ_RVT_TT_nldm_201020.lib.gz",
-      "verilog sim": "$STDCELLS/Verilog/asap7sc7p5t_SEQ_RVT_TT_201020.v",
-      "lef file": "$STDCELLS/LEF/scaled/asap7sc7p5t_27_R_4x_201211.lef",
-      "spice file": "$STDCELLS/CDL/LVS/asap7sc7p5t_27_R.cdl",
-      "gds file": "$STDCELLS/GDS/asap7sc7p5t_27_R_201211.gds",
+      "nldm liberty file": "$STDCELLS/LIB/NLDM/asap7sc7p5t_SEQ_RVT_TT_nldm_220123.lib.gz",
+      "verilog sim": "$STDCELLS/Verilog/asap7sc7p5t_SEQ_RVT_TT_220101.v",
+      "lef file": "$STDCELLS/LEF/scaled/asap7sc7p5t_28_R_4x_220121a.lef",
+      "spice file": "$STDCELLS/CDL/LVS/asap7sc7p5t_28_R.cdl",
+      "gds file": "$STDCELLS/GDS/asap7sc7p5t_28_R_220121a.gds",
       "qrc techfile": "$STDCELLS/qrc/qrcTechFile_typ03_scaled4xV06",
       "corner": {
         "nmos": "typical",
@@ -862,10 +862,10 @@
       ]
     },
     {
-      "nldm liberty file": "tech-asap7-cache/LIB/NLDM/asap7sc7p5t_SEQ_RVT_SS_nldm_201020.lib.gz",
-      "lef file": "$STDCELLS/LEF/scaled/asap7sc7p5t_27_R_4x_201211.lef",
-      "spice file": "$STDCELLS/CDL/LVS/asap7sc7p5t_27_R.cdl",
-      "gds file": "$STDCELLS/GDS/asap7sc7p5t_27_R_201211.gds",
+      "nldm liberty file": "$STDCELLS/LIB/NLDM/asap7sc7p5t_SEQ_RVT_SS_nldm_220123.lib.gz",
+      "lef file": "$STDCELLS/LEF/scaled/asap7sc7p5t_28_R_4x_220121a.lef",
+      "spice file": "$STDCELLS/CDL/LVS/asap7sc7p5t_28_R.cdl",
+      "gds file": "$STDCELLS/GDS/asap7sc7p5t_28_R_220121a.gds",
       "qrc techfile": "$STDCELLS/qrc/qrcTechFile_typ03_scaled4xV06",
       "corner": {
         "nmos": "slow",
@@ -884,10 +884,10 @@
       ]
     },
     {
-      "nldm liberty file": "tech-asap7-cache/LIB/NLDM/asap7sc7p5t_SEQ_RVT_FF_nldm_201020.lib.gz",
-      "lef file": "$STDCELLS/LEF/scaled/asap7sc7p5t_27_R_4x_201211.lef",
-      "spice file": "$STDCELLS/CDL/LVS/asap7sc7p5t_27_R.cdl",
-      "gds file": "$STDCELLS/GDS/asap7sc7p5t_27_R_201211.gds",
+      "nldm liberty file": "$STDCELLS/LIB/NLDM/asap7sc7p5t_SEQ_RVT_FF_nldm_220123.lib.gz",
+      "lef file": "$STDCELLS/LEF/scaled/asap7sc7p5t_28_R_4x_220121a.lef",
+      "spice file": "$STDCELLS/CDL/LVS/asap7sc7p5t_28_R.cdl",
+      "gds file": "$STDCELLS/GDS/asap7sc7p5t_28_R_220121a.gds",
       "qrc techfile": "$STDCELLS/qrc/qrcTechFile_typ03_scaled4xV06",
       "corner": {
         "nmos": "fast",
@@ -906,11 +906,11 @@
       ]
     },
     {
-      "nldm liberty file": "tech-asap7-cache/LIB/NLDM/asap7sc7p5t_SEQ_LVT_TT_nldm_201020.lib.gz",
-      "verilog sim": "$STDCELLS/Verilog/asap7sc7p5t_SEQ_LVT_TT_201020.v",
-      "lef file": "$STDCELLS/LEF/scaled/asap7sc7p5t_27_L_4x_201211.lef",
-      "spice file": "$STDCELLS/CDL/LVS/asap7sc7p5t_27_L.cdl",
-      "gds file": "tech-asap7-cache/GDS/asap7sc7p5t_27_L_201211.gds",
+      "nldm liberty file": "$STDCELLS/LIB/NLDM/asap7sc7p5t_SEQ_LVT_TT_nldm_220123.lib.gz",
+      "verilog sim": "$STDCELLS/Verilog/asap7sc7p5t_SEQ_LVT_TT_220101.v",
+      "lef file": "$STDCELLS/LEF/scaled/asap7sc7p5t_28_L_4x_220121a.lef",
+      "spice file": "$STDCELLS/CDL/LVS/asap7sc7p5t_28_L.cdl",
+      "gds file": "$STDCELLS/GDS/asap7sc7p5t_28_L_220121a.gds",
       "qrc techfile": "$STDCELLS/qrc/qrcTechFile_typ03_scaled4xV06",
       "corner": {
         "nmos": "typical",
@@ -929,10 +929,10 @@
       ]
     },
     {
-      "nldm liberty file": "tech-asap7-cache/LIB/NLDM/asap7sc7p5t_SEQ_LVT_SS_nldm_201020.lib.gz",
-      "lef file": "$STDCELLS/LEF/scaled/asap7sc7p5t_27_L_4x_201211.lef",
-      "spice file": "$STDCELLS/CDL/LVS/asap7sc7p5t_27_L.cdl",
-      "gds file": "tech-asap7-cache/GDS/asap7sc7p5t_27_L_201211.gds",
+      "nldm liberty file": "$STDCELLS/LIB/NLDM/asap7sc7p5t_SEQ_LVT_SS_nldm_220123.lib.gz",
+      "lef file": "$STDCELLS/LEF/scaled/asap7sc7p5t_28_L_4x_220121a.lef",
+      "spice file": "$STDCELLS/CDL/LVS/asap7sc7p5t_28_L.cdl",
+      "gds file": "$STDCELLS/GDS/asap7sc7p5t_28_L_220121a.gds",
       "qrc techfile": "$STDCELLS/qrc/qrcTechFile_typ03_scaled4xV06",
       "corner": {
         "nmos": "slow",
@@ -951,10 +951,10 @@
       ]
     },
     {
-      "nldm liberty file": "tech-asap7-cache/LIB/NLDM/asap7sc7p5t_SEQ_LVT_FF_nldm_201020.lib.gz",
-      "lef file": "$STDCELLS/LEF/scaled/asap7sc7p5t_27_L_4x_201211.lef",
-      "spice file": "$STDCELLS/CDL/LVS/asap7sc7p5t_27_L.cdl",
-      "gds file": "tech-asap7-cache/GDS/asap7sc7p5t_27_L_201211.gds",
+      "nldm liberty file": "$STDCELLS/LIB/NLDM/asap7sc7p5t_SEQ_LVT_FF_nldm_220123.lib.gz",
+      "lef file": "$STDCELLS/LEF/scaled/asap7sc7p5t_28_L_4x_220121a.lef",
+      "spice file": "$STDCELLS/CDL/LVS/asap7sc7p5t_28_L.cdl",
+      "gds file": "$STDCELLS/GDS/asap7sc7p5t_28_L_220121a.gds",
       "qrc techfile": "$STDCELLS/qrc/qrcTechFile_typ03_scaled4xV06",
       "corner": {
         "nmos": "fast",
@@ -973,11 +973,11 @@
       ]
     },
     {
-      "nldm liberty file": "tech-asap7-cache/LIB/NLDM/asap7sc7p5t_SEQ_SLVT_TT_nldm_201020.lib.gz",
-      "verilog sim": "$STDCELLS/Verilog/asap7sc7p5t_SEQ_SLVT_TT_201020.v",
-      "lef file": "$STDCELLS/LEF/scaled/asap7sc7p5t_27_SL_4x_201211.lef",
-      "spice file": "$STDCELLS/CDL/LVS/asap7sc7p5t_27_SL.cdl",
-      "gds file": "tech-asap7-cache/GDS/asap7sc7p5t_27_SL_201211.gds",
+      "nldm liberty file": "$STDCELLS/LIB/NLDM/asap7sc7p5t_SEQ_SLVT_TT_nldm_220123.lib.gz",
+      "verilog sim": "$STDCELLS/Verilog/asap7sc7p5t_SEQ_SLVT_TT_220101.v",
+      "lef file": "$STDCELLS/LEF/scaled/asap7sc7p5t_28_SL_4x_220121a.lef",
+      "spice file": "$STDCELLS/CDL/LVS/asap7sc7p5t_28_SL.cdl",
+      "gds file": "$STDCELLS/GDS/asap7sc7p5t_28_SL_220121a.gds",
       "qrc techfile": "$STDCELLS/qrc/qrcTechFile_typ03_scaled4xV06",
       "corner": {
         "nmos": "typical",
@@ -996,10 +996,10 @@
       ]
     },
     {
-      "nldm liberty file": "tech-asap7-cache/LIB/NLDM/asap7sc7p5t_SEQ_SLVT_SS_nldm_201020.lib.gz",
-      "lef file": "$STDCELLS/LEF/scaled/asap7sc7p5t_27_SL_4x_201211.lef",
-      "spice file": "$STDCELLS/CDL/LVS/asap7sc7p5t_27_SL.cdl",
-      "gds file": "tech-asap7-cache/GDS/asap7sc7p5t_27_SL_201211.gds",
+      "nldm liberty file": "$STDCELLS/LIB/NLDM/asap7sc7p5t_SEQ_SLVT_SS_nldm_220123.lib.gz",
+      "lef file": "$STDCELLS/LEF/scaled/asap7sc7p5t_28_SL_4x_220121a.lef",
+      "spice file": "$STDCELLS/CDL/LVS/asap7sc7p5t_28_SL.cdl",
+      "gds file": "$STDCELLS/GDS/asap7sc7p5t_28_SL_220121a.gds",
       "qrc techfile": "$STDCELLS/qrc/qrcTechFile_typ03_scaled4xV06",
       "corner": {
         "nmos": "slow",
@@ -1018,10 +1018,10 @@
       ]
     },
     {
-      "nldm liberty file": "tech-asap7-cache/LIB/NLDM/asap7sc7p5t_SEQ_SLVT_FF_nldm_201020.lib.gz",
-      "lef file": "$STDCELLS/LEF/scaled/asap7sc7p5t_27_SL_4x_201211.lef",
-      "spice file": "$STDCELLS/CDL/LVS/asap7sc7p5t_27_SL.cdl",
-      "gds file": "tech-asap7-cache/GDS/asap7sc7p5t_27_SL_201211.gds",
+      "nldm liberty file": "$STDCELLS/LIB/NLDM/asap7sc7p5t_SEQ_SLVT_FF_nldm_220123.lib.gz",
+      "lef file": "$STDCELLS/LEF/scaled/asap7sc7p5t_28_SL_4x_220121a.lef",
+      "spice file": "$STDCELLS/CDL/LVS/asap7sc7p5t_28_SL.cdl",
+      "gds file": "$STDCELLS/GDS/asap7sc7p5t_28_SL_220121a.gds",
       "qrc techfile": "$STDCELLS/qrc/qrcTechFile_typ03_scaled4xV06",
       "corner": {
         "nmos": "fast",
@@ -1040,11 +1040,11 @@
       ]
     },
     {
-      "nldm liberty file": "tech-asap7-cache/LIB/NLDM/asap7sc7p5t_SEQ_SRAM_TT_nldm_201020.lib.gz",
-      "verilog sim": "$STDCELLS/Verilog/asap7sc7p5t_SEQ_SRAM_TT_201020.v",
-      "lef file": "$STDCELLS/LEF/scaled/asap7sc7p5t_27_SRAM_4x_201211.lef",
-      "spice file": "$STDCELLS/CDL/LVS/asap7sc7p5t_27_SRAM.cdl",
-      "gds file": "tech-asap7-cache/GDS/asap7sc7p5t_27_SRAM_201211.gds",
+      "nldm liberty file": "$STDCELLS/LIB/NLDM/asap7sc7p5t_SEQ_SRAM_TT_nldm_220123.lib.gz",
+      "verilog sim": "$STDCELLS/Verilog/asap7sc7p5t_SEQ_SRAM_TT_220101.v",
+      "lef file": "$STDCELLS/LEF/scaled/asap7sc7p5t_28_SRAM_4x_220121a.lef",
+      "spice file": "$STDCELLS/CDL/LVS/asap7sc7p5t_28_SRAM.cdl",
+      "gds file": "$STDCELLS/GDS/asap7sc7p5t_28_SRAM_220121a.gds",
       "qrc techfile": "$STDCELLS/qrc/qrcTechFile_typ03_scaled4xV06",
       "corner": {
         "nmos": "typical",
@@ -1057,10 +1057,10 @@
       }
     },
     {
-      "nldm liberty file": "tech-asap7-cache/LIB/NLDM/asap7sc7p5t_SEQ_SRAM_SS_nldm_201020.lib.gz",
-      "lef file": "$STDCELLS/LEF/scaled/asap7sc7p5t_27_SRAM_4x_201211.lef",
-      "spice file": "$STDCELLS/CDL/LVS/asap7sc7p5t_27_SRAM.cdl",
-      "gds file": "tech-asap7-cache/GDS/asap7sc7p5t_27_SRAM_201211.gds",
+      "nldm liberty file": "$STDCELLS/LIB/NLDM/asap7sc7p5t_SEQ_SRAM_SS_nldm_220123.lib.gz",
+      "lef file": "$STDCELLS/LEF/scaled/asap7sc7p5t_28_SRAM_4x_220121a.lef",
+      "spice file": "$STDCELLS/CDL/LVS/asap7sc7p5t_28_SRAM.cdl",
+      "gds file": "$STDCELLS/GDS/asap7sc7p5t_28_SRAM_220121a.gds",
       "qrc techfile": "$STDCELLS/qrc/qrcTechFile_typ03_scaled4xV06",
       "corner": {
         "nmos": "slow",
@@ -1073,10 +1073,10 @@
       }
     },
     {
-      "nldm liberty file": "tech-asap7-cache/LIB/NLDM/asap7sc7p5t_SEQ_SRAM_FF_nldm_201020.lib.gz",
-      "lef file": "$STDCELLS/LEF/scaled/asap7sc7p5t_27_SRAM_4x_201211.lef",
-      "spice file": "$STDCELLS/CDL/LVS/asap7sc7p5t_27_SRAM.cdl",
-      "gds file": "tech-asap7-cache/GDS/asap7sc7p5t_27_SRAM_201211.gds",
+      "nldm liberty file": "$STDCELLS/LIB/NLDM/asap7sc7p5t_SEQ_SRAM_FF_nldm_220123.lib.gz",
+      "lef file": "$STDCELLS/LEF/scaled/asap7sc7p5t_28_SRAM_4x_220121a.lef",
+      "spice file": "$STDCELLS/CDL/LVS/asap7sc7p5t_28_SRAM.cdl",
+      "gds file": "$STDCELLS/GDS/asap7sc7p5t_28_SRAM_220121a.gds",
       "qrc techfile": "$STDCELLS/qrc/qrcTechFile_typ03_scaled4xV06",
       "corner": {
         "nmos": "fast",
@@ -1089,11 +1089,11 @@
       }
     },
     {
-      "nldm liberty file": "$STDCELLS/LIB/NLDM/asap7sc7p5t_INVBUF_RVT_TT_nldm_201020.lib.gz",
+      "nldm liberty file": "$STDCELLS/LIB/NLDM/asap7sc7p5t_INVBUF_RVT_TT_nldm_220122.lib.gz",
       "verilog sim": "$STDCELLS/Verilog/asap7sc7p5t_INVBUF_RVT_TT_201020.v",
-      "lef file": "$STDCELLS/LEF/scaled/asap7sc7p5t_27_R_4x_201211.lef",
-      "spice file": "$STDCELLS/CDL/LVS/asap7sc7p5t_27_R.cdl",
-      "gds file": "$STDCELLS/GDS/asap7sc7p5t_27_R_201211.gds",
+      "lef file": "$STDCELLS/LEF/scaled/asap7sc7p5t_28_R_4x_220121a.lef",
+      "spice file": "$STDCELLS/CDL/LVS/asap7sc7p5t_28_R.cdl",
+      "gds file": "$STDCELLS/GDS/asap7sc7p5t_28_R_220121a.gds",
       "qrc techfile": "$STDCELLS/qrc/qrcTechFile_typ03_scaled4xV06",
       "corner": {
         "nmos": "typical",
@@ -1112,10 +1112,10 @@
       ]
     },
     {
-      "nldm liberty file": "$STDCELLS/LIB/NLDM/asap7sc7p5t_INVBUF_RVT_SS_nldm_201020.lib.gz",
-      "lef file": "$STDCELLS/LEF/scaled/asap7sc7p5t_27_R_4x_201211.lef",
-      "spice file": "$STDCELLS/CDL/LVS/asap7sc7p5t_27_R.cdl",
-      "gds file": "$STDCELLS/GDS/asap7sc7p5t_27_R_201211.gds",
+      "nldm liberty file": "$STDCELLS/LIB/NLDM/asap7sc7p5t_INVBUF_RVT_SS_nldm_220122.lib.gz",
+      "lef file": "$STDCELLS/LEF/scaled/asap7sc7p5t_28_R_4x_220121a.lef",
+      "spice file": "$STDCELLS/CDL/LVS/asap7sc7p5t_28_R.cdl",
+      "gds file": "$STDCELLS/GDS/asap7sc7p5t_28_R_220121a.gds",
       "qrc techfile": "$STDCELLS/qrc/qrcTechFile_typ03_scaled4xV06",
       "corner": {
         "nmos": "slow",
@@ -1134,10 +1134,10 @@
       ]
     },
     {
-      "nldm liberty file": "$STDCELLS/LIB/NLDM/asap7sc7p5t_INVBUF_RVT_FF_nldm_201020.lib.gz",
-      "lef file": "$STDCELLS/LEF/scaled/asap7sc7p5t_27_R_4x_201211.lef",
-      "spice file": "$STDCELLS/CDL/LVS/asap7sc7p5t_27_R.cdl",
-      "gds file": "$STDCELLS/GDS/asap7sc7p5t_27_R_201211.gds",
+      "nldm liberty file": "$STDCELLS/LIB/NLDM/asap7sc7p5t_INVBUF_RVT_FF_nldm_220122.lib.gz",
+      "lef file": "$STDCELLS/LEF/scaled/asap7sc7p5t_28_R_4x_220121a.lef",
+      "spice file": "$STDCELLS/CDL/LVS/asap7sc7p5t_28_R.cdl",
+      "gds file": "$STDCELLS/GDS/asap7sc7p5t_28_R_220121a.gds",
       "qrc techfile": "$STDCELLS/qrc/qrcTechFile_typ03_scaled4xV06",
       "corner": {
         "nmos": "fast",
@@ -1156,11 +1156,11 @@
       ]
     },
     {
-      "nldm liberty file": "$STDCELLS/LIB/NLDM/asap7sc7p5t_INVBUF_LVT_TT_nldm_201020.lib.gz",
+      "nldm liberty file": "$STDCELLS/LIB/NLDM/asap7sc7p5t_INVBUF_LVT_TT_nldm_220122.lib.gz",
       "verilog sim": "$STDCELLS/Verilog/asap7sc7p5t_INVBUF_LVT_TT_201020.v",
-      "lef file": "$STDCELLS/LEF/scaled/asap7sc7p5t_27_L_4x_201211.lef",
-      "spice file": "$STDCELLS/CDL/LVS/asap7sc7p5t_27_L.cdl",
-      "gds file": "tech-asap7-cache/GDS/asap7sc7p5t_27_L_201211.gds",
+      "lef file": "$STDCELLS/LEF/scaled/asap7sc7p5t_28_L_4x_220121a.lef",
+      "spice file": "$STDCELLS/CDL/LVS/asap7sc7p5t_28_L.cdl",
+      "gds file": "$STDCELLS/GDS/asap7sc7p5t_28_L_220121a.gds",
       "qrc techfile": "$STDCELLS/qrc/qrcTechFile_typ03_scaled4xV06",
       "corner": {
         "nmos": "typical",
@@ -1179,10 +1179,10 @@
       ]
     },
     {
-      "nldm liberty file": "$STDCELLS/LIB/NLDM/asap7sc7p5t_INVBUF_LVT_SS_nldm_201020.lib.gz",
-      "lef file": "$STDCELLS/LEF/scaled/asap7sc7p5t_27_L_4x_201211.lef",
-      "spice file": "$STDCELLS/CDL/LVS/asap7sc7p5t_27_L.cdl",
-      "gds file": "tech-asap7-cache/GDS/asap7sc7p5t_27_L_201211.gds",
+      "nldm liberty file": "$STDCELLS/LIB/NLDM/asap7sc7p5t_INVBUF_LVT_SS_nldm_220122.lib.gz",
+      "lef file": "$STDCELLS/LEF/scaled/asap7sc7p5t_28_L_4x_220121a.lef",
+      "spice file": "$STDCELLS/CDL/LVS/asap7sc7p5t_28_L.cdl",
+      "gds file": "$STDCELLS/GDS/asap7sc7p5t_28_L_220121a.gds",
       "qrc techfile": "$STDCELLS/qrc/qrcTechFile_typ03_scaled4xV06",
       "corner": {
         "nmos": "slow",
@@ -1201,10 +1201,10 @@
       ]
     },
     {
-      "nldm liberty file": "$STDCELLS/LIB/NLDM/asap7sc7p5t_INVBUF_LVT_FF_nldm_201020.lib.gz",
-      "lef file": "$STDCELLS/LEF/scaled/asap7sc7p5t_27_L_4x_201211.lef",
-      "spice file": "$STDCELLS/CDL/LVS/asap7sc7p5t_27_L.cdl",
-      "gds file": "tech-asap7-cache/GDS/asap7sc7p5t_27_L_201211.gds",
+      "nldm liberty file": "$STDCELLS/LIB/NLDM/asap7sc7p5t_INVBUF_LVT_FF_nldm_220122.lib.gz",
+      "lef file": "$STDCELLS/LEF/scaled/asap7sc7p5t_28_L_4x_220121a.lef",
+      "spice file": "$STDCELLS/CDL/LVS/asap7sc7p5t_28_L.cdl",
+      "gds file": "$STDCELLS/GDS/asap7sc7p5t_28_L_220121a.gds",
       "qrc techfile": "$STDCELLS/qrc/qrcTechFile_typ03_scaled4xV06",
       "corner": {
         "nmos": "fast",
@@ -1223,11 +1223,11 @@
       ]
     },
     {
-      "nldm liberty file": "$STDCELLS/LIB/NLDM/asap7sc7p5t_INVBUF_SLVT_TT_nldm_201020.lib.gz",
+      "nldm liberty file": "$STDCELLS/LIB/NLDM/asap7sc7p5t_INVBUF_SLVT_TT_nldm_220122.lib.gz",
       "verilog sim": "$STDCELLS/Verilog/asap7sc7p5t_INVBUF_SLVT_TT_201020.v",
-      "lef file": "$STDCELLS/LEF/scaled/asap7sc7p5t_27_SL_4x_201211.lef",
-      "spice file": "$STDCELLS/CDL/LVS/asap7sc7p5t_27_SL.cdl",
-      "gds file": "tech-asap7-cache/GDS/asap7sc7p5t_27_SL_201211.gds",
+      "lef file": "$STDCELLS/LEF/scaled/asap7sc7p5t_28_SL_4x_220121a.lef",
+      "spice file": "$STDCELLS/CDL/LVS/asap7sc7p5t_28_SL.cdl",
+      "gds file": "$STDCELLS/GDS/asap7sc7p5t_28_SL_220121a.gds",
       "qrc techfile": "$STDCELLS/qrc/qrcTechFile_typ03_scaled4xV06",
       "corner": {
         "nmos": "typical",
@@ -1246,10 +1246,10 @@
       ]
     },
     {
-      "nldm liberty file": "$STDCELLS/LIB/NLDM/asap7sc7p5t_INVBUF_SLVT_SS_nldm_201020.lib.gz",
-      "lef file": "$STDCELLS/LEF/scaled/asap7sc7p5t_27_SL_4x_201211.lef",
-      "spice file": "$STDCELLS/CDL/LVS/asap7sc7p5t_27_SL.cdl",
-      "gds file": "tech-asap7-cache/GDS/asap7sc7p5t_27_SL_201211.gds",
+      "nldm liberty file": "$STDCELLS/LIB/NLDM/asap7sc7p5t_INVBUF_SLVT_SS_nldm_220122.lib.gz",
+      "lef file": "$STDCELLS/LEF/scaled/asap7sc7p5t_28_SL_4x_220121a.lef",
+      "spice file": "$STDCELLS/CDL/LVS/asap7sc7p5t_28_SL.cdl",
+      "gds file": "$STDCELLS/GDS/asap7sc7p5t_28_SL_220121a.gds",
       "qrc techfile": "$STDCELLS/qrc/qrcTechFile_typ03_scaled4xV06",
       "corner": {
         "nmos": "slow",
@@ -1268,10 +1268,10 @@
       ]
     },
     {
-      "nldm liberty file": "$STDCELLS/LIB/NLDM/asap7sc7p5t_INVBUF_SLVT_FF_nldm_201020.lib.gz",
-      "lef file": "$STDCELLS/LEF/scaled/asap7sc7p5t_27_SL_4x_201211.lef",
-      "spice file": "$STDCELLS/CDL/LVS/asap7sc7p5t_27_SL.cdl",
-      "gds file": "tech-asap7-cache/GDS/asap7sc7p5t_27_SL_201211.gds",
+      "nldm liberty file": "$STDCELLS/LIB/NLDM/asap7sc7p5t_INVBUF_SLVT_FF_nldm_220122.lib.gz",
+      "lef file": "$STDCELLS/LEF/scaled/asap7sc7p5t_28_SL_4x_220121a.lef",
+      "spice file": "$STDCELLS/CDL/LVS/asap7sc7p5t_28_SL.cdl",
+      "gds file": "$STDCELLS/GDS/asap7sc7p5t_28_SL_220121a.gds",
       "qrc techfile": "$STDCELLS/qrc/qrcTechFile_typ03_scaled4xV06",
       "corner": {
         "nmos": "fast",
@@ -1290,11 +1290,11 @@
       ]
     },
     {
-      "nldm liberty file": "$STDCELLS/LIB/NLDM/asap7sc7p5t_INVBUF_SRAM_TT_nldm_201020.lib.gz",
+      "nldm liberty file": "$STDCELLS/LIB/NLDM/asap7sc7p5t_INVBUF_SRAM_TT_nldm_220122.lib.gz",
       "verilog sim": "$STDCELLS/Verilog/asap7sc7p5t_INVBUF_SRAM_TT_201020.v",
-      "lef file": "$STDCELLS/LEF/scaled/asap7sc7p5t_27_SRAM_4x_201211.lef",
-      "spice file": "$STDCELLS/CDL/LVS/asap7sc7p5t_27_SRAM.cdl",
-      "gds file": "tech-asap7-cache/GDS/asap7sc7p5t_27_SRAM_201211.gds",
+      "lef file": "$STDCELLS/LEF/scaled/asap7sc7p5t_28_SRAM_4x_220121a.lef",
+      "spice file": "$STDCELLS/CDL/LVS/asap7sc7p5t_28_SRAM.cdl",
+      "gds file": "$STDCELLS/GDS/asap7sc7p5t_28_SRAM_220121a.gds",
       "qrc techfile": "$STDCELLS/qrc/qrcTechFile_typ03_scaled4xV06",
       "corner": {
         "nmos": "typical",
@@ -1307,10 +1307,10 @@
       }
     },
     {
-      "nldm liberty file": "$STDCELLS/LIB/NLDM/asap7sc7p5t_INVBUF_SRAM_SS_nldm_201020.lib.gz",
-      "lef file": "$STDCELLS/LEF/scaled/asap7sc7p5t_27_SRAM_4x_201211.lef",
-      "spice file": "$STDCELLS/CDL/LVS/asap7sc7p5t_27_SRAM.cdl",
-      "gds file": "tech-asap7-cache/GDS/asap7sc7p5t_27_SRAM_201211.gds",
+      "nldm liberty file": "$STDCELLS/LIB/NLDM/asap7sc7p5t_INVBUF_SRAM_SS_nldm_220122.lib.gz",
+      "lef file": "$STDCELLS/LEF/scaled/asap7sc7p5t_28_SRAM_4x_220121a.lef",
+      "spice file": "$STDCELLS/CDL/LVS/asap7sc7p5t_28_SRAM.cdl",
+      "gds file": "$STDCELLS/GDS/asap7sc7p5t_28_SRAM_220121a.gds",
       "qrc techfile": "$STDCELLS/qrc/qrcTechFile_typ03_scaled4xV06",
       "corner": {
         "nmos": "slow",
@@ -1323,10 +1323,10 @@
       }
     },
     {
-      "nldm liberty file": "$STDCELLS/LIB/NLDM/asap7sc7p5t_INVBUF_SRAM_FF_nldm_201020.lib.gz",
-      "lef file": "$STDCELLS/LEF/scaled/asap7sc7p5t_27_SRAM_4x_201211.lef",
-      "spice file": "$STDCELLS/CDL/LVS/asap7sc7p5t_27_SRAM.cdl",
-      "gds file": "tech-asap7-cache/GDS/asap7sc7p5t_27_SRAM_201211.gds",
+      "nldm liberty file": "$STDCELLS/LIB/NLDM/asap7sc7p5t_INVBUF_SRAM_FF_nldm_220122.lib.gz",
+      "lef file": "$STDCELLS/LEF/scaled/asap7sc7p5t_28_SRAM_4x_220121a.lef",
+      "spice file": "$STDCELLS/CDL/LVS/asap7sc7p5t_28_SRAM.cdl",
+      "gds file": "$STDCELLS/GDS/asap7sc7p5t_28_SRAM_220121a.gds",
       "qrc techfile": "$STDCELLS/qrc/qrcTechFile_typ03_scaled4xV06",
       "corner": {
         "nmos": "fast",
@@ -1339,29 +1339,7 @@
       }
     }
   ],
-  "dont use list": [
-      "ICGx*DC*",
-      "AND4x1*",
-      "SDFLx2*",
-      "AO21x1*",
-      "XOR2x2*",
-      "OAI31xp33*",
-      "OAI221xp5*",
-      "SDFLx3*",
-      "SDFLx1*",
-      "AOI211xp5*",
-      "OAI322xp33*",
-      "OR2x6*",
-      "A2O1A1O1Ixp25*",
-      "XNOR2x1*",
-      "OAI32xp33*",
-      "FAx1*",
-      "OAI21x1*",
-      "OAI31xp67*",
-      "OAI33xp33*",
-      "AO21x2*",
-      "AOI32xp33*"
-  ],
+  "dont use list": [],
   "stackups": [
     {
       "name": "asap7_3Ma_2Mb_2Mc_2Md",
diff --git a/src/hammer-vlsi/technology/asap7/defaults.yml b/src/hammer-vlsi/technology/asap7/defaults.yml
index c41e5f249..95c358d8e 100644
--- a/src/hammer-vlsi/technology/asap7/defaults.yml
+++ b/src/hammer-vlsi/technology/asap7/defaults.yml
@@ -6,7 +6,7 @@ technology.asap7:
   pdk_install_dir: "${technology.asap7.tarball_dir}/asap7PDK_r1p7"
   pdk_install_dir_meta: lazysubst
   # Path to the directory containing the standard cell collateral
-  stdcell_install_dir: "${technology.asap7.tarball_dir}/asap7sc7p5t_27"
+  stdcell_install_dir: "${technology.asap7.tarball_dir}/asap7sc7p5t_28"
   stdcell_install_dir_meta: lazysubst
 
 # Set some defaults for this technology.
@@ -102,4 +102,4 @@ mentor.layerprops: "calibre.layerprops"
 mentor.layerprops_meta: "prependlocal"
 # 2017-year only Calibre supported by decks
 drc.calibre.version: "2017.3_38.30"
-lvs.calibre.version: "2017.3_38.30"
+lvs.calibre.version: "2017.3_38.30"
\ No newline at end of file