From 2f0554f27b1db496a28ac9f1591302f437cb0615 Mon Sep 17 00:00:00 2001 From: Ice Unjitwattana Date: Sun, 22 Oct 2023 17:12:28 -0700 Subject: [PATCH 1/9] single lane scrambler --- src/main/scala/Scrambler.scala | 25 +++++++++++++++++++++++++ src/test/scala/Scrambler.scala | 25 +++++++++++++++++++++++++ 2 files changed, 50 insertions(+) create mode 100644 src/main/scala/Scrambler.scala create mode 100644 src/test/scala/Scrambler.scala diff --git a/src/main/scala/Scrambler.scala b/src/main/scala/Scrambler.scala new file mode 100644 index 0000000..9dd1ec3 --- /dev/null +++ b/src/main/scala/Scrambler.scala @@ -0,0 +1,25 @@ +package edu.berkeley.cs.ucie.digital + +import chisel3._ +import chisel3.util._ +import chisel3.util.random._ + +// + +class Scrambler extends Module { + val io = IO(new Bundle { + val L0_in = Input(UInt(16.W)) + val valid = Input(Bool()) + val rst = Input(Bool()) + val L0_out = Output(UInt(16.W)) + }) + val L0_LFSR = Module(new FibonacciLFSR(23, Set(23,21,18,15,7,2,1), Some(BigInt(1949628)), XOR, 16, false)) + L0_LFSR.io.increment := io.valid + L0_LFSR.io.seed.bits := VecInit(1949628.U(23.W).asBools) + L0_LFSR.io.seed.valid := (reset.asBool || io.rst) + + val L0_LFSR_result = L0_LFSR.io.out + printf(cf"$L0_LFSR_result.asUInt") + io.L0_out := L0_LFSR_result.asUInt ^ io.L0_in +} + diff --git a/src/test/scala/Scrambler.scala b/src/test/scala/Scrambler.scala new file mode 100644 index 0000000..337982e --- /dev/null +++ b/src/test/scala/Scrambler.scala @@ -0,0 +1,25 @@ +package edu.berkeley.cs.ucie.digital + +import chisel3._ +import chiseltest._ +import org.scalatest.funspec.AnyFunSpec + +class ScramblerTest extends AnyFunSpec with ChiselScalatestTester { + describe("Scrambler") { + it("should scramble one lane") { + test(new Scrambler()) { c => + c.io.rst.poke(true.B) + c.clock.step() + c.clock.step() + c.io.rst.poke(false.B) + c.clock.step() + c.io.valid.poke(true.B) + c.io.L0_in.poke(9628) + c.io.L0_out.expect(39456) + c.clock.step() + c.io.L0_in.poke(13458) + c.io.L0_out.expect(48271) + } + } + } +} \ No newline at end of file From 71ba809d151c24453993af808455993f2ec79bcd Mon Sep 17 00:00:00 2001 From: Ice Unjitwattana Date: Wed, 8 Nov 2023 10:58:14 -0800 Subject: [PATCH 2/9] Scrambler done, pending testing --- src/main/scala/Scrambler.scala | 46 ++++++++++++++++++++++++++-------- src/test/scala/Scrambler.scala | 16 ++++++------ 2 files changed, 44 insertions(+), 18 deletions(-) diff --git a/src/main/scala/Scrambler.scala b/src/main/scala/Scrambler.scala index 9dd1ec3..45e856c 100644 --- a/src/main/scala/Scrambler.scala +++ b/src/main/scala/Scrambler.scala @@ -1,4 +1,5 @@ package edu.berkeley.cs.ucie.digital +package interfaces import chisel3._ import chisel3.util._ @@ -6,20 +7,43 @@ import chisel3.util.random._ // -class Scrambler extends Module { +class Scrambler ( + afeParams: AfeParams, + width: Int, + seed: BigInt +) extends Module { val io = IO(new Bundle { - val L0_in = Input(UInt(16.W)) + val data_in = Input(UInt(afeParams.mbSerializerRatio.W)) val valid = Input(Bool()) - val rst = Input(Bool()) - val L0_out = Output(UInt(16.W)) + val seed = Input(UInt(23.W)) + val data_out = Output(UInt(afeParams.mbSerializerRatio.W)) }) - val L0_LFSR = Module(new FibonacciLFSR(23, Set(23,21,18,15,7,2,1), Some(BigInt(1949628)), XOR, 16, false)) - L0_LFSR.io.increment := io.valid - L0_LFSR.io.seed.bits := VecInit(1949628.U(23.W).asBools) - L0_LFSR.io.seed.valid := (reset.asBool || io.rst) + val LFSR = Module(new FibonacciLFSR(23, Set(23,21,18,15,7,2,1), Some(seed), XOR, width, false)) + LFSR.io.increment := io.valid + LFSR.io.seed.bits := VecInit(io.seed.asBools) + LFSR.io.seed.valid := (reset.asBool) + val LFSR_result = LFSR.io.out + //printf(cf"$LFSR_result.asUInt") + io.data_out := LFSR_result.asUInt ^ io.data_in +} + +class UCIeScrambler ( + afeParams: AfeParams, + width: Int +) extends Module { + val io = IO(new Bundle { + val data_in = Input(Vec(12, UInt(afeParams.mbSerializerRatio.W))) + val valid = Input(Bool()) + val data_out = Output(Vec(12, UInt(afeParams.mbSerializerRatio.W))) + }) + val seeds = List("1DBFBC", "0607BB", "1EC760", "18C0DB", "010F12", "19CFC9", "0277CE", "1BB807", "18C0DB", "010F12", "18C0DB", "010F12") + val scramblers = seeds.map(seed => Module(new Scrambler(afeParams, width, BigInt(seed, 16)))); - val L0_LFSR_result = L0_LFSR.io.out - printf(cf"$L0_LFSR_result.asUInt") - io.L0_out := L0_LFSR_result.asUInt ^ io.L0_in + for (i <- 0 until scramblers.length) { + scramblers.apply(i).io.data_in := io.data_in(0); + scramblers.apply(i).io.valid := io.valid; + scramblers.apply(i).io.seed := seeds.apply(i).U(23.W); + io.data_out(i) := scramblers.apply(i).io.data_out + } } diff --git a/src/test/scala/Scrambler.scala b/src/test/scala/Scrambler.scala index 337982e..da73d1e 100644 --- a/src/test/scala/Scrambler.scala +++ b/src/test/scala/Scrambler.scala @@ -1,4 +1,5 @@ package edu.berkeley.cs.ucie.digital +package interfaces import chisel3._ import chiseltest._ @@ -7,18 +8,19 @@ import org.scalatest.funspec.AnyFunSpec class ScramblerTest extends AnyFunSpec with ChiselScalatestTester { describe("Scrambler") { it("should scramble one lane") { + test(new Scrambler()) { c => - c.io.rst.poke(true.B) + c.reset.poke(true.B) c.clock.step() c.clock.step() - c.io.rst.poke(false.B) + c.reset.poke(false.B) c.clock.step() c.io.valid.poke(true.B) - c.io.L0_in.poke(9628) - c.io.L0_out.expect(39456) - c.clock.step() - c.io.L0_in.poke(13458) - c.io.L0_out.expect(48271) + c.io.data_in.poke(9628) + c.io.data_out.expect(39456) + // c.clock.step() + // c.io.data_in.poke(13458) + // c.io.data_out.expect(48271) } } } From c2e5dd76de63542bc67bb01c123af2535dde48d2 Mon Sep 17 00:00:00 2001 From: Ice Unjitwattana Date: Wed, 15 Nov 2023 10:13:42 -0800 Subject: [PATCH 3/9] Scrambler --- src/main/scala/Scrambler.scala | 21 ++++++++++++--------- 1 file changed, 12 insertions(+), 9 deletions(-) diff --git a/src/main/scala/Scrambler.scala b/src/main/scala/Scrambler.scala index 45e856c..3b6913d 100644 --- a/src/main/scala/Scrambler.scala +++ b/src/main/scala/Scrambler.scala @@ -29,20 +29,23 @@ class Scrambler ( class UCIeScrambler ( afeParams: AfeParams, - width: Int + width: Int, + numLanes: Int ) extends Module { val io = IO(new Bundle { - val data_in = Input(Vec(12, UInt(afeParams.mbSerializerRatio.W))) + val data_in = Input(Vec(numLanes, UInt(afeParams.mbSerializerRatio.W))) val valid = Input(Bool()) - val data_out = Output(Vec(12, UInt(afeParams.mbSerializerRatio.W))) + val data_out = Output(Vec(numLanes, UInt(afeParams.mbSerializerRatio.W))) }) - val seeds = List("1DBFBC", "0607BB", "1EC760", "18C0DB", "010F12", "19CFC9", "0277CE", "1BB807", "18C0DB", "010F12", "18C0DB", "010F12") - val scramblers = seeds.map(seed => Module(new Scrambler(afeParams, width, BigInt(seed, 16)))); + val UCIe_seeds = List("1dbfbc", "0607bb", "1ec760", "18c0db", "010f12", "19cfc9", "0277ce", "1bb807") + val seeds = (for (i <- 0 to numLanes) yield UCIe_seeds.apply(i % 8)).toList + val scramblers = seeds.map(seed => Module(new Scrambler(afeParams, width, BigInt(seed, 16)))) - for (i <- 0 until scramblers.length) { - scramblers.apply(i).io.data_in := io.data_in(0); - scramblers.apply(i).io.valid := io.valid; - scramblers.apply(i).io.seed := seeds.apply(i).U(23.W); + for (i <- 0 to scramblers.length) { + scramblers.apply(i).io.data_in := io.data_in(0) + scramblers.apply(i).io.valid := io.valid + //seeds.apply returns a string. currently cannot cast to Chisel Uint + scramblers.apply(i).io.seed := ("h" + seeds.apply(i)).U(23.W) io.data_out(i) := scramblers.apply(i).io.data_out } } From 74f84a8277da1be13d49e462275a54a3aac37fbb Mon Sep 17 00:00:00 2001 From: Ice Unjitwattana Date: Wed, 15 Nov 2023 10:34:31 -0800 Subject: [PATCH 4/9] scrambler without test --- src/main/scala/Scrambler.scala | 9 ++++----- src/test/scala/Scrambler.scala | 36 ++++++++++++++++++++++------------ 2 files changed, 27 insertions(+), 18 deletions(-) diff --git a/src/main/scala/Scrambler.scala b/src/main/scala/Scrambler.scala index 3b6913d..6da6812 100644 --- a/src/main/scala/Scrambler.scala +++ b/src/main/scala/Scrambler.scala @@ -38,13 +38,12 @@ class UCIeScrambler ( val data_out = Output(Vec(numLanes, UInt(afeParams.mbSerializerRatio.W))) }) val UCIe_seeds = List("1dbfbc", "0607bb", "1ec760", "18c0db", "010f12", "19cfc9", "0277ce", "1bb807") - val seeds = (for (i <- 0 to numLanes) yield UCIe_seeds.apply(i % 8)).toList + val seeds = (for (i <- 0 until numLanes) yield UCIe_seeds.apply(i % 8)).toList val scramblers = seeds.map(seed => Module(new Scrambler(afeParams, width, BigInt(seed, 16)))) - - for (i <- 0 to scramblers.length) { - scramblers.apply(i).io.data_in := io.data_in(0) + + for (i <- 0 until scramblers.length) { + scramblers.apply(i).io.data_in := io.data_in(i) scramblers.apply(i).io.valid := io.valid - //seeds.apply returns a string. currently cannot cast to Chisel Uint scramblers.apply(i).io.seed := ("h" + seeds.apply(i)).U(23.W) io.data_out(i) := scramblers.apply(i).io.data_out } diff --git a/src/test/scala/Scrambler.scala b/src/test/scala/Scrambler.scala index da73d1e..a4204ca 100644 --- a/src/test/scala/Scrambler.scala +++ b/src/test/scala/Scrambler.scala @@ -5,22 +5,32 @@ import chisel3._ import chiseltest._ import org.scalatest.funspec.AnyFunSpec +// Test doesn't work + class ScramblerTest extends AnyFunSpec with ChiselScalatestTester { describe("Scrambler") { - it("should scramble one lane") { - - test(new Scrambler()) { c => - c.reset.poke(true.B) - c.clock.step() - c.clock.step() - c.reset.poke(false.B) - c.clock.step() - c.io.valid.poke(true.B) - c.io.data_in.poke(9628) - c.io.data_out.expect(39456) + it("4 lane scrambler test") { + test(new UCIeScrambler(new AfeParams(1,16,16), 16, 4)) { c => + val in = Vec(4, UInt(16.W)) + val out = Vec(4, UInt(16.W)) + // in(0) := 1.U(23.W) + // in(1) := 1012.U(23.W) + // in(2) := 823.U(23.W) + // in(3) := 134.U(23.W) + // out(0) := 49085.U(23.W) + // out(1) := 1103.U(23.W) + // out(2) := 50263.U(23.W) + // out(3) := 49245.U(23.W) + + // c.reset.poke(true.B) + // c.clock.step() // c.clock.step() - // c.io.data_in.poke(13458) - // c.io.data_out.expect(48271) + // c.reset.poke(false.B) + // c.clock.step() + // c.io.valid.poke(true.B) + + // c.io.data_in.poke(in) + // c.io.data_out.expect(out) } } } From 60a7c86fb9b009a253535a95ef1c681959480946 Mon Sep 17 00:00:00 2001 From: Ice Unjitwattana Date: Wed, 15 Nov 2023 12:06:25 -0800 Subject: [PATCH 5/9] scrambler with test --- src/main/scala/Scrambler.scala | 3 ++- src/test/scala/Scrambler.scala | 40 ++++++++++++++++++---------------- 2 files changed, 23 insertions(+), 20 deletions(-) diff --git a/src/main/scala/Scrambler.scala b/src/main/scala/Scrambler.scala index 6da6812..45567d7 100644 --- a/src/main/scala/Scrambler.scala +++ b/src/main/scala/Scrambler.scala @@ -40,10 +40,11 @@ class UCIeScrambler ( val UCIe_seeds = List("1dbfbc", "0607bb", "1ec760", "18c0db", "010f12", "19cfc9", "0277ce", "1bb807") val seeds = (for (i <- 0 until numLanes) yield UCIe_seeds.apply(i % 8)).toList val scramblers = seeds.map(seed => Module(new Scrambler(afeParams, width, BigInt(seed, 16)))) - for (i <- 0 until scramblers.length) { scramblers.apply(i).io.data_in := io.data_in(i) scramblers.apply(i).io.valid := io.valid + scramblers.apply(i).reset := reset + scramblers.apply(i).clock := clock scramblers.apply(i).io.seed := ("h" + seeds.apply(i)).U(23.W) io.data_out(i) := scramblers.apply(i).io.data_out } diff --git a/src/test/scala/Scrambler.scala b/src/test/scala/Scrambler.scala index a4204ca..ab646c6 100644 --- a/src/test/scala/Scrambler.scala +++ b/src/test/scala/Scrambler.scala @@ -4,33 +4,35 @@ package interfaces import chisel3._ import chiseltest._ import org.scalatest.funspec.AnyFunSpec +import chisel3.experimental.VecLiterals._ // Test doesn't work class ScramblerTest extends AnyFunSpec with ChiselScalatestTester { + describe("Scrambler") { it("4 lane scrambler test") { - test(new UCIeScrambler(new AfeParams(1,16,16), 16, 4)) { c => - val in = Vec(4, UInt(16.W)) - val out = Vec(4, UInt(16.W)) - // in(0) := 1.U(23.W) - // in(1) := 1012.U(23.W) - // in(2) := 823.U(23.W) - // in(3) := 134.U(23.W) - // out(0) := 49085.U(23.W) - // out(1) := 1103.U(23.W) - // out(2) := 50263.U(23.W) - // out(3) := 49245.U(23.W) + test(new UCIeScrambler(new AfeParams(), 16, 4)) { c => + // val in = Vec(4, UInt(16.W)) + // val out = Vec(4, UInt(16.W)) + // in := Vec.Lit(1.U(16.W), 1012.U(16.W), 823.U(16.W), 134.U(16.W)) + // out := Vec.Lit(49085.U(16.W), 1103.U(16.W), 50263.U(16.W), 49245.U(16.W)) + c.reset.poke(true.B) + c.clock.step() + c.clock.step() + c.reset.poke(false.B) + c.clock.step() + c.io.valid.poke(true.B) - // c.reset.poke(true.B) - // c.clock.step() - // c.clock.step() - // c.reset.poke(false.B) - // c.clock.step() - // c.io.valid.poke(true.B) + c.io.data_in(0).poke(1.U(16.W)) + c.io.data_in(1).poke(1012.U(16.W)) + c.io.data_in(2).poke(823.U(16.W)) + c.io.data_in(3).poke(134.U(16.W)) + c.io.data_out(0).expect(49085.U(16.W)) + c.io.data_out(1).expect(1103.U(16.W)) + c.io.data_out(2).expect(50263.U(16.W)) + c.io.data_out(3).expect(49245.U(16.W)) - // c.io.data_in.poke(in) - // c.io.data_out.expect(out) } } } From bd5863b8b6a6994c2583dd17823713dade0f3a7f Mon Sep 17 00:00:00 2001 From: Ice Unjitwattana Date: Wed, 15 Nov 2023 17:26:22 -0800 Subject: [PATCH 6/9] removed .apply() in scrambler --- src/main/scala/Scrambler.scala | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/src/main/scala/Scrambler.scala b/src/main/scala/Scrambler.scala index 45567d7..f2fc654 100644 --- a/src/main/scala/Scrambler.scala +++ b/src/main/scala/Scrambler.scala @@ -38,15 +38,15 @@ class UCIeScrambler ( val data_out = Output(Vec(numLanes, UInt(afeParams.mbSerializerRatio.W))) }) val UCIe_seeds = List("1dbfbc", "0607bb", "1ec760", "18c0db", "010f12", "19cfc9", "0277ce", "1bb807") - val seeds = (for (i <- 0 until numLanes) yield UCIe_seeds.apply(i % 8)).toList + val seeds = (for (i <- 0 until numLanes) yield UCIe_seeds(i % 8)).toList val scramblers = seeds.map(seed => Module(new Scrambler(afeParams, width, BigInt(seed, 16)))) for (i <- 0 until scramblers.length) { - scramblers.apply(i).io.data_in := io.data_in(i) - scramblers.apply(i).io.valid := io.valid - scramblers.apply(i).reset := reset - scramblers.apply(i).clock := clock - scramblers.apply(i).io.seed := ("h" + seeds.apply(i)).U(23.W) - io.data_out(i) := scramblers.apply(i).io.data_out + scramblers(i).io.data_in := io.data_in(i) + scramblers(i).io.valid := io.valid + scramblers(i).reset := reset + scramblers(i).clock := clock + scramblers(i).io.seed := ("h" + seeds(i)).U(23.W) + io.data_out(i) := scramblers(i).io.data_out } } From aad805b1a9b9a0faffa3eb6cfb568ddc148bbe53 Mon Sep 17 00:00:00 2001 From: Ice Unjitwattana Date: Fri, 17 Nov 2023 22:29:37 -0800 Subject: [PATCH 7/9] scrambler reformatted --- src/main/scala/Scrambler.scala | 47 ++++++++++++++++++++++------------ src/test/scala/Scrambler.scala | 8 +----- 2 files changed, 32 insertions(+), 23 deletions(-) diff --git a/src/main/scala/Scrambler.scala b/src/main/scala/Scrambler.scala index f2fc654..69bbc3f 100644 --- a/src/main/scala/Scrambler.scala +++ b/src/main/scala/Scrambler.scala @@ -2,15 +2,12 @@ package edu.berkeley.cs.ucie.digital package interfaces import chisel3._ -import chisel3.util._ import chisel3.util.random._ -// - -class Scrambler ( - afeParams: AfeParams, - width: Int, - seed: BigInt +class Scrambler( + afeParams: AfeParams, + width: Int, + seed: BigInt, ) extends Module { val io = IO(new Bundle { val data_in = Input(UInt(afeParams.mbSerializerRatio.W)) @@ -18,28 +15,47 @@ class Scrambler ( val seed = Input(UInt(23.W)) val data_out = Output(UInt(afeParams.mbSerializerRatio.W)) }) - val LFSR = Module(new FibonacciLFSR(23, Set(23,21,18,15,7,2,1), Some(seed), XOR, width, false)) + val LFSR = Module( + new FibonacciLFSR( + 23, + Set(23, 21, 18, 15, 7, 2, 1), + Some(seed), + XOR, + width, + false, + ), + ) LFSR.io.increment := io.valid LFSR.io.seed.bits := VecInit(io.seed.asBools) LFSR.io.seed.valid := (reset.asBool) val LFSR_result = LFSR.io.out - //printf(cf"$LFSR_result.asUInt") + // printf(cf"$LFSR_result.asUInt") io.data_out := LFSR_result.asUInt ^ io.data_in } -class UCIeScrambler ( - afeParams: AfeParams, - width: Int, - numLanes: Int +class UCIeScrambler( + afeParams: AfeParams, + width: Int, + numLanes: Int, ) extends Module { val io = IO(new Bundle { val data_in = Input(Vec(numLanes, UInt(afeParams.mbSerializerRatio.W))) val valid = Input(Bool()) val data_out = Output(Vec(numLanes, UInt(afeParams.mbSerializerRatio.W))) }) - val UCIe_seeds = List("1dbfbc", "0607bb", "1ec760", "18c0db", "010f12", "19cfc9", "0277ce", "1bb807") + val UCIe_seeds = List( + "1dbfbc", + "0607bb", + "1ec760", + "18c0db", + "010f12", + "19cfc9", + "0277ce", + "1bb807", + ) val seeds = (for (i <- 0 until numLanes) yield UCIe_seeds(i % 8)).toList - val scramblers = seeds.map(seed => Module(new Scrambler(afeParams, width, BigInt(seed, 16)))) + val scramblers = + seeds.map(seed => Module(new Scrambler(afeParams, width, BigInt(seed, 16)))) for (i <- 0 until scramblers.length) { scramblers(i).io.data_in := io.data_in(i) scramblers(i).io.valid := io.valid @@ -49,4 +65,3 @@ class UCIeScrambler ( io.data_out(i) := scramblers(i).io.data_out } } - diff --git a/src/test/scala/Scrambler.scala b/src/test/scala/Scrambler.scala index ab646c6..9d6dfb0 100644 --- a/src/test/scala/Scrambler.scala +++ b/src/test/scala/Scrambler.scala @@ -6,17 +6,11 @@ import chiseltest._ import org.scalatest.funspec.AnyFunSpec import chisel3.experimental.VecLiterals._ -// Test doesn't work - class ScramblerTest extends AnyFunSpec with ChiselScalatestTester { describe("Scrambler") { it("4 lane scrambler test") { test(new UCIeScrambler(new AfeParams(), 16, 4)) { c => - // val in = Vec(4, UInt(16.W)) - // val out = Vec(4, UInt(16.W)) - // in := Vec.Lit(1.U(16.W), 1012.U(16.W), 823.U(16.W), 134.U(16.W)) - // out := Vec.Lit(49085.U(16.W), 1103.U(16.W), 50263.U(16.W), 49245.U(16.W)) c.reset.poke(true.B) c.clock.step() c.clock.step() @@ -36,4 +30,4 @@ class ScramblerTest extends AnyFunSpec with ChiselScalatestTester { } } } -} \ No newline at end of file +} From f51c262a19a733173c13b793659da064edcd299a Mon Sep 17 00:00:00 2001 From: Ice Unjitwattana Date: Fri, 17 Nov 2023 22:29:54 -0800 Subject: [PATCH 8/9] scrambler reformatted --- src/test/scala/Scrambler.scala | 1 - 1 file changed, 1 deletion(-) diff --git a/src/test/scala/Scrambler.scala b/src/test/scala/Scrambler.scala index 9d6dfb0..c0b309f 100644 --- a/src/test/scala/Scrambler.scala +++ b/src/test/scala/Scrambler.scala @@ -4,7 +4,6 @@ package interfaces import chisel3._ import chiseltest._ import org.scalatest.funspec.AnyFunSpec -import chisel3.experimental.VecLiterals._ class ScramblerTest extends AnyFunSpec with ChiselScalatestTester { From 7e38993d40e51225a418bc27d7edfc1356696321 Mon Sep 17 00:00:00 2001 From: Ice Unjitwattana Date: Wed, 29 Nov 2023 10:19:28 -0800 Subject: [PATCH 9/9] missing python test script --- src/main/scala/Scrambler.scala | 4 +--- src/test/scala/Scrambler.scala | 10 +++++++++- 2 files changed, 10 insertions(+), 4 deletions(-) diff --git a/src/main/scala/Scrambler.scala b/src/main/scala/Scrambler.scala index 69bbc3f..2455757 100644 --- a/src/main/scala/Scrambler.scala +++ b/src/main/scala/Scrambler.scala @@ -28,9 +28,7 @@ class Scrambler( LFSR.io.increment := io.valid LFSR.io.seed.bits := VecInit(io.seed.asBools) LFSR.io.seed.valid := (reset.asBool) - val LFSR_result = LFSR.io.out - // printf(cf"$LFSR_result.asUInt") - io.data_out := LFSR_result.asUInt ^ io.data_in + io.data_out := LFSR.io.out.asUInt ^ io.data_in } class UCIeScrambler( diff --git a/src/test/scala/Scrambler.scala b/src/test/scala/Scrambler.scala index c0b309f..80a4d14 100644 --- a/src/test/scala/Scrambler.scala +++ b/src/test/scala/Scrambler.scala @@ -25,7 +25,15 @@ class ScramblerTest extends AnyFunSpec with ChiselScalatestTester { c.io.data_out(1).expect(1103.U(16.W)) c.io.data_out(2).expect(50263.U(16.W)) c.io.data_out(3).expect(49245.U(16.W)) - + c.clock.step() + c.io.data_in(0).poke(203.U(16.W)) + c.io.data_in(1).poke(176.U(16.W)) + c.io.data_in(2).poke(21.U(16.W)) + c.io.data_in(3).poke(5847.U(16.W)) + c.io.data_out(0).expect(65321.U(16.W)) + c.io.data_out(1).expect(56489.U(16.W)) + c.io.data_out(2).expect(11245.U(16.W)) + c.io.data_out(3).expect(57654.U(16.W)) } } }