Put conversion in SdramCntl.py

[gw0]

In my opinion it would make sense to put the conversion to VHDL and Verilog from Conversion.py in relevant files, to make it obvious what it converts.

In this case at the bottom of SdramCntl.py something like:

if __name__ == '__main__':
    # signals
    clk_i = Signal(bool(0))
    rst_i = ResetSignal(0,active=1,async=True)

    # modules
    clkDriver_Inst      = clkDriver(clk_i)
    sd_intf_Inst        = sd_intf()
    host_intf_Inst      = host_intf()

    sdramCntl_Inst = MySdramCntl(clk_i, host_intf_Inst, sd_intf_Inst)

    # convert to Verilog and VHDL
    toVerilog(MySdramCntl, clk_i, host_intf_Inst, sd_intf_Inst)
    toVHDL(MySdramCntl, clk_i, host_intf_Inst, sd_intf_Inst)