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adc.par
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Release 11.1 par L.33 (nt)
Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.
PC245486007190:: Mon Mar 01 10:08:38 2010
par -ise EE314project.ise -w -intstyle ise -ol std -t 1 adc_map.ncd adc.ncd
adc.pcf
Constraints file: adc.pcf.
Loading device for application Rf_Device from file '3s1200e.nph' in environment D:\Xilinx\11.1\ISE.
"adc" is an NCD, version 3.2, device xc3s1200e, package fg320, speed -4
Initializing temperature to 85.000 Celsius. (default - Range: -40.000 to 100.000 Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.320 Volts)
INFO:Par:282 - No user timing constraints were detected or you have set the option to ignore timing constraints ("par
-x"). Place and Route will run in "Performance Evaluation Mode" to automatically improve the performance of all
internal clocks in this design. Because there are not defined timing requirements, a timing score will not be
reported in the PAR report in this mode. The PAR timing summary will list the performance achieved for each clock.
Note: For the fastest runtime, set the effort level to "std". For best performance, set the effort level to "high".
Device speed data version: "PRODUCTION 1.27 2009-03-03".
Design Summary Report:
Number of External IOBs 16 out of 250 6%
Number of External Input IOBs 2
Number of External Input IBUFs 2
Number of External Output IOBs 14
Number of External Output IOBs 14
Number of External Bidir IOBs 0
Number of BUFGMUXs 2 out of 24 8%
Number of Slices 53 out of 8672 1%
Number of SLICEMs 0 out of 4336 0%
Overall effort level (-ol): Standard
Placer effort level (-pl): High
Placer cost table entry (-t): 1
Router effort level (-rl): Standard
Starting initial Timing Analysis. REAL time: 8 secs
Finished initial Timing Analysis. REAL time: 8 secs
Starting Placer
Total REAL time at the beginning of Placer: 9 secs
Total CPU time at the beginning of Placer: 2 secs
Phase 1.1 Initial Placement Analysis
Phase 1.1 Initial Placement Analysis (Checksum:9ba) REAL time: 11 secs
Phase 2.7 Design Feasibility Check
Phase 2.7 Design Feasibility Check (Checksum:9ba) REAL time: 11 secs
Phase 3.31 Local Placement Optimization
Phase 3.31 Local Placement Optimization (Checksum:9ba) REAL time: 11 secs
Phase 4.2 Initial Clock and IO Placement
............
Phase 4.2 Initial Clock and IO Placement (Checksum:86a344db) REAL time: 11 secs
Phase 5.30 Global Clock Region Assignment
Phase 5.30 Global Clock Region Assignment (Checksum:86a344db) REAL time: 11 secs
Phase 6.3 Local Placement Optimization
............
Phase 6.3 Local Placement Optimization (Checksum:8777146b) REAL time: 12 secs
Phase 7.5 Local Placement Optimization
Phase 7.5 Local Placement Optimization (Checksum:8777146b) REAL time: 12 secs
Phase 8.8 Global Placement
............
Phase 8.8 Global Placement (Checksum:4bb828b) REAL time: 15 secs
Phase 9.5 Local Placement Optimization
Phase 9.5 Local Placement Optimization (Checksum:4bb828b) REAL time: 15 secs
Phase 10.18 Placement Optimization
Phase 10.18 Placement Optimization (Checksum:f95a7100) REAL time: 15 secs
Phase 11.5 Local Placement Optimization
Phase 11.5 Local Placement Optimization (Checksum:f95a7100) REAL time: 15 secs
Total REAL time to Placer completion: 15 secs
Total CPU time to Placer completion: 7 secs
Writing design to file adc.ncd
Starting Router
Phase 1 : 288 unrouted; REAL time: 20 secs
Phase 2 : 241 unrouted; REAL time: 21 secs
Phase 3 : 51 unrouted; REAL time: 21 secs
Phase 4 : 56 unrouted; (Par is working to improve performance) REAL time: 22 secs
Phase 5 : 0 unrouted; (Par is working to improve performance) REAL time: 22 secs
Updating file: adc.ncd with current fully routed design.
Phase 6 : 0 unrouted; (Par is working to improve performance) REAL time: 23 secs
Phase 7 : 0 unrouted; (Par is working to improve performance) REAL time: 23 secs
Phase 8 : 0 unrouted; (Par is working to improve performance) REAL time: 23 secs
Phase 9 : 0 unrouted; (Par is working to improve performance) REAL time: 23 secs
Phase 10 : 0 unrouted; (Par is working to improve performance) REAL time: 23 secs
Total REAL time to Router completion: 23 secs
Total CPU time to Router completion: 14 secs
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
Generating "PAR" statistics.
**************************
Generating Clock Report
**************************
+---------------------+--------------+------+------+------------+-------------+
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
| MCLK_BUFGP | BUFGMUX_X2Y10| No | 17 | 0.015 | 0.298 |
+---------------------+--------------+------+------+------------+-------------+
| clkx | BUFGMUX_X1Y10| No | 24 | 0.047 | 0.372 |
+---------------------+--------------+------+------+------------+-------------+
* Net Skew is the difference between the minimum and maximum routing
only delays for the net. Note this is different from Clock Skew which
is reported in TRCE timing report. Clock Skew is the difference between
the minimum and maximum path delays which includes logic delays.
Timing Score: 0 (Setup: 0, Hold: 0)
Asterisk (*) preceding a constraint indicates it was not met.
This may be due to a setup or hold violation.
----------------------------------------------------------------------------------------------------------
Constraint | Check | Worst Case | Best Case | Timing | Timing
| | Slack | Achievable | Errors | Score
----------------------------------------------------------------------------------------------------------
Autotimespec constraint for clock net MCL | SETUP | N/A| 5.782ns| N/A| 0
K_BUFGP | HOLD | 1.286ns| | 0| 0
------------------------------------------------------------------------------------------------------
Autotimespec constraint for clock net clk | SETUP | N/A| 6.326ns| N/A| 0
x | HOLD | 0.927ns| | 0| 0
------------------------------------------------------------------------------------------------------
All constraints were met.
INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the
constraint does not cover any paths or that it has no requested value.
Generating Pad Report.
All signals are completely routed.
Total REAL time to PAR completion: 24 secs
Total CPU time to PAR completion: 15 secs
Peak Memory Usage: 168 MB
Placement: Completed - No errors found.
Routing: Completed - No errors found.
Number of error messages: 0
Number of warning messages: 0
Number of info messages: 1
Writing design to file adc.ncd
PAR done!