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This repository has been archived by the owner on Sep 18, 2019. It is now read-only.
The FSM Designer is a tool for interactive design of finite state machines. It allows you to create your FSMs via a graphical user interface including states, transitions, hypertransitions, links and joins. Additionally, you are able to verify your FSMs directly at any point in time during the development. Finally, your FSMs are translated to Verilog, a hardware description language.