forked from chipsalliance/verible
-
Notifications
You must be signed in to change notification settings - Fork 0
/
Copy pathdimensions.cc
54 lines (43 loc) · 1.75 KB
/
dimensions.cc
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
// Copyright 2017-2020 The Verible Authors.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include "verilog/CST/dimensions.h"
#include <vector>
#include "common/analysis/matcher/matcher.h"
#include "common/analysis/matcher/matcher_builders.h"
#include "common/analysis/syntax_tree_search.h"
#include "common/text/concrete_syntax_tree.h"
#include "common/text/symbol.h"
#include "common/text/tree_utils.h"
#include "verilog/CST/verilog_matchers.h" // IWYU pragma: keep
namespace verilog {
using verible::Symbol;
std::vector<verible::TreeSearchMatch> FindAllPackedDimensions(
const Symbol& root) {
return SearchSyntaxTree(root, NodekPackedDimensions());
}
std::vector<verible::TreeSearchMatch> FindAllUnpackedDimensions(
const Symbol& root) {
return SearchSyntaxTree(root, NodekUnpackedDimensions());
}
std::vector<verible::TreeSearchMatch> FindAllDeclarationDimensions(
const Symbol& root) {
return SearchSyntaxTree(root, NodekDeclarationDimensions());
}
const Symbol* GetDimensionRangeLeftBound(const Symbol& s) {
return verible::GetSubtreeAsSymbol(s, NodeEnum::kDimensionRange, 1);
}
const Symbol* GetDimensionRangeRightBound(const verible::Symbol& s) {
return verible::GetSubtreeAsSymbol(s, NodeEnum::kDimensionRange, 3);
}
} // namespace verilog