diff --git a/alu_u32/src/com/columns.rs b/alu_u32/src/com/columns.rs index 7cc56950..a759bf83 100644 --- a/alu_u32/src/com/columns.rs +++ b/alu_u32/src/com/columns.rs @@ -21,8 +21,6 @@ pub struct Com32Cols { pub is_ne: T, pub is_eq: T, - pub is_ne: T, - pub is_eq: T, } pub const NUM_COM_COLS: usize = size_of::>(); diff --git a/alu_u32/src/com/mod.rs b/alu_u32/src/com/mod.rs index 441470d0..e04d6fd9 100644 --- a/alu_u32/src/com/mod.rs +++ b/alu_u32/src/com/mod.rs @@ -7,13 +7,14 @@ use core::iter; use core::mem::transmute; use valida_bus::MachineWithGeneralBus; use valida_cpu::MachineWithCpuChip; +use valida_machine::config::StarkConfig; use valida_machine::{ instructions, Chip, Instruction, Interaction, Operands, Word, MEMORY_CELL_BYTES, }; use valida_opcodes::{EQ32, NE32}; use p3_air::VirtualPairCol; -use p3_field::PrimeField; +use p3_field::{AbstractField, Field, PrimeField}; use p3_matrix::dense::RowMajorMatrix; use p3_maybe_rayon::*; use valida_util::pad_to_power_of_two; @@ -25,7 +26,6 @@ pub mod stark; pub enum Operation { Ne32(Word, Word, Word), // (dst, src1, src2) Eq32(Word, Word, Word), // (dst, src1, src2) - Eq32(Word, Word, Word), // (dst, src1, src2) } #[derive(Default)] @@ -33,12 +33,12 @@ pub struct Com32Chip { pub operations: Vec, } -impl Chip for Com32Chip +impl Chip for Com32Chip where - F: PrimeField, - M: MachineWithGeneralBus, + M: MachineWithGeneralBus, + SC: StarkConfig, { - fn generate_trace(&self, _machine: &M) -> RowMajorMatrix { + fn generate_trace(&self, _machine: &M) -> RowMajorMatrix { let rows = self .operations .par_iter() @@ -48,30 +48,23 @@ where let mut trace = RowMajorMatrix::new(rows.into_iter().flatten().collect::>(), NUM_COM_COLS); - pad_to_power_of_two::(&mut trace.values); + pad_to_power_of_two::(&mut trace.values); trace } - fn global_receives(&self, machine: &M) -> Vec> { - let opcode = VirtualPairCol::new_main( - vec![ - (COM_COL_MAP.is_ne, M::F::from_canonical_u32(NE32)), - (COM_COL_MAP.is_eq, M::F::from_canonical_u32(EQ32)), - ], - M::F::zero(), - ); + fn global_receives(&self, machine: &M) -> Vec> { let opcode = VirtualPairCol::new_main( vec![ - (COM_COL_MAP.is_ne, M::F::from_canonical_u32(NE32)), - (COM_COL_MAP.is_eq, M::F::from_canonical_u32(EQ32)), + (COM_COL_MAP.is_ne, SC::Val::from_canonical_u32(NE32)), + (COM_COL_MAP.is_eq, SC::Val::from_canonical_u32(EQ32)), ], - M::F::zero(), + SC::Val::zero(), ); let input_1 = COM_COL_MAP.input_1.0.map(VirtualPairCol::single_main); let input_2 = COM_COL_MAP.input_2.0.map(VirtualPairCol::single_main); let output = (0..MEMORY_CELL_BYTES - 1) - .map(|_| VirtualPairCol::constant(M::F::zero())) + .map(|_| VirtualPairCol::constant(SC::Val::zero())) .chain(iter::once(VirtualPairCol::single_main(COM_COL_MAP.output))); let mut fields = vec![opcode]; @@ -84,7 +77,6 @@ where let receive = Interaction { fields, count: is_real, - count: is_real, argument_index: machine.general_bus(), }; vec![receive] @@ -111,22 +103,22 @@ impl Com32Chip { } } -pub trait MachineWithCom32Chip: MachineWithCpuChip { +pub trait MachineWithCom32Chip: MachineWithCpuChip { fn com_u32(&self) -> &Com32Chip; fn com_u32_mut(&mut self) -> &mut Com32Chip; } -instructions!(Ne32Instruction, Eq32Instruction); instructions!(Ne32Instruction, Eq32Instruction); -impl Instruction for Ne32Instruction +impl Instruction for Ne32Instruction where - M: MachineWithCom32Chip, + M: MachineWithCom32Chip, + F: Field, { const OPCODE: u32 = NE32; fn execute(state: &mut M, ops: Operands) { - let opcode = >::OPCODE; + let opcode = >::OPCODE; let clk = state.cpu().clock; let pc = state.cpu().pc; let mut imm: Option> = None; @@ -157,36 +149,36 @@ where .com_u32_mut() .operations .push(Operation::Ne32(dst, src1, src2)); - state - .com_u32_mut() - .operations - .push(Operation::Eq32(dst, src1, src2)); state.cpu_mut().push_bus_op(imm, opcode, ops); } } - -impl Instruction for Eq32Instruction +impl Instruction for Eq32Instruction where - M: MachineWithCom32Chip, + M: MachineWithCom32Chip, + F: Field, { const OPCODE: u32 = EQ32; fn execute(state: &mut M, ops: Operands) { - let opcode = >::OPCODE; + let opcode = >::OPCODE; let clk = state.cpu().clock; let pc = state.cpu().pc; let mut imm: Option> = None; let read_addr_1 = (state.cpu().fp as i32 + ops.b()) as u32; let write_addr = (state.cpu().fp as i32 + ops.a()) as u32; - let src1 = state.mem_mut().read(clk, read_addr_1, true, pc, opcode, 0, ""); + let src1 = state + .mem_mut() + .read(clk, read_addr_1, true, pc, opcode, 0, ""); let src2 = if ops.is_imm() == 1 { let c = (ops.c() as u32).into(); imm = Some(c); c } else { let read_addr_2 = (state.cpu().fp as i32 + ops.c()) as u32; - state.mem_mut().read(clk, read_addr_2, true, pc, opcode, 1, "") + state + .mem_mut() + .read(clk, read_addr_2, true, pc, opcode, 1, "") }; let dst = if src1 == src2 { @@ -200,8 +192,6 @@ where .com_u32_mut() .operations .push(Operation::Eq32(dst, src1, src2)); - state - .cpu_mut() - .push_bus_op(imm, opcode, ops); + state.cpu_mut().push_bus_op(imm, opcode, ops); } } diff --git a/basic/src/lib.rs b/basic/src/lib.rs index 4554cd81..18987c89 100644 --- a/basic/src/lib.rs +++ b/basic/src/lib.rs @@ -14,7 +14,6 @@ use valida_alu_u32::{ com::{Com32Chip, Eq32Instruction, MachineWithCom32Chip, Ne32Instruction}, div::{Div32Chip, Div32Instruction, MachineWithDiv32Chip, SDiv32Instruction}, lt::{Lt32Chip, Lt32Instruction, MachineWithLt32Chip}, - com::{Com32Chip, Ne32Instruction, Eq32Instruction, MachineWithCom32Chip}, mul::{ MachineWithMul32Chip, Mul32Chip, Mul32Instruction, Mulhs32Instruction, Mulhu32Instruction, }, @@ -92,8 +91,6 @@ pub struct BasicMachine { ne32: Ne32Instruction, #[instruction(com_u32)] eq32: Eq32Instruction, - #[instruction(com_u32)] - eq32: Eq32Instruction, #[instruction(bitwise_u32)] and32: And32Instruction, #[instruction(bitwise_u32)] @@ -260,9 +257,7 @@ impl MachineWithCom32Chip for BasicMachine } } -impl> MachineWithShift32Chip - for BasicMachine -{ +impl MachineWithShift32Chip for BasicMachine { fn shift_u32(&self) -> &Shift32Chip { &self.shift_u32 }