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Test #9949: Scheduled
December 20, 2024 00:56 1h 16m 1s master
December 20, 2024 00:56 1h 16m 1s
Merge pull request #2845 from w0lek/master
Test #9948: Commit c954e57 pushed by AlexandreSinger
December 19, 2024 18:42 1h 14m 42s master
December 19, 2024 18:42 1h 14m 42s
Test
Test #9947: Scheduled
December 19, 2024 00:59 1h 7m 0s master
December 19, 2024 00:59 1h 7m 0s
Merge pull request #2843 from verilog-to-routing/ipin_cost
Test #9946: Commit e49ddc4 pushed by vaughnbetz
December 18, 2024 15:02 1h 15m 17s master
December 18, 2024 15:02 1h 15m 17s
Test
Test #9945: Scheduled
December 18, 2024 00:58 1h 13m 24s master
December 18, 2024 00:58 1h 13m 24s
[WIP] VIB Upgrades for Tileable Routing Resource Graph on OpenFPGA
Test #9944: Pull request #2637 synchronize by Wang-Yuanqi-source
December 17, 2024 06:25 Action required Wang-Yuanqi-source:patch-1
December 17, 2024 06:25 Action required
Test
Test #9942: Scheduled
December 17, 2024 01:01 1h 24m 30s master
December 17, 2024 01:01 1h 24m 30s
December 16, 2024 23:59 1h 9m 49s
Merge pull request #2844 from verilog-to-routing/read_write_simple_lo…
Test #9940: Commit 231438e pushed by vaughnbetz
December 16, 2024 18:08 1h 18m 58s master
December 16, 2024 18:08 1h 18m 58s
Simple Place Delay Model Read/Write
Test #9939: Pull request #2844 synchronize by amin1377
December 16, 2024 16:56 1h 15m 7s read_write_simple_lookahead
December 16, 2024 16:56 1h 15m 7s
[WIP] Synlig, new system-verilog tool integration
Test #9938: Pull request #2841 synchronize by amirarjmand93
December 16, 2024 04:33 1h 13m 31s vtr+synlig
December 16, 2024 04:33 1h 13m 31s
[WIP] Synlig, new system-verilog tool integration
Test #9937: Pull request #2841 synchronize by amirarjmand93
December 16, 2024 04:24 9m 40s vtr+synlig
December 16, 2024 04:24 9m 40s
[WIP] Synlig, new system-verilog tool integration
Test #9936: Pull request #2841 synchronize by amirarjmand93
December 16, 2024 04:12 5m 18s vtr+synlig
December 16, 2024 04:12 5m 18s
Test
Test #9935: Scheduled
December 16, 2024 01:03 1h 12m 54s master
December 16, 2024 01:03 1h 12m 54s
Test
Test #9934: Scheduled
December 15, 2024 01:06 1h 14m 59s master
December 15, 2024 01:06 1h 14m 59s
Test
Test #9933: Scheduled
December 14, 2024 00:59 1h 14m 37s master
December 14, 2024 00:59 1h 14m 37s
Simple Place Delay Model Read/Write
Test #9932: Pull request #2844 opened by amin1377
December 13, 2024 21:45 1h 18m 45s read_write_simple_lookahead
December 13, 2024 21:45 1h 18m 45s
IPIN Cost Multiplier
Test #9931: Pull request #2843 synchronize by amin1377
December 13, 2024 16:20 1h 21m 1s ipin_cost
December 13, 2024 16:20 1h 21m 1s
IPIN Cost Multiplier
Test #9930: Pull request #2843 opened by amin1377
December 13, 2024 16:19 1m 11s ipin_cost
December 13, 2024 16:19 1m 11s
Test
Test #9929: Scheduled
December 13, 2024 01:02 1h 13m 27s master
December 13, 2024 01:02 1h 13m 27s
Test
Test #9928: Scheduled
December 12, 2024 01:01 1h 14m 30s master
December 12, 2024 01:01 1h 14m 30s
Test
Test #9927: Scheduled
December 11, 2024 01:01 1h 12m 51s master
December 11, 2024 01:01 1h 12m 51s
[WIP] Synlig, new system-verilog tool integration
Test #9926: Pull request #2841 synchronize by amirarjmand93
December 10, 2024 17:40 1h 14m 12s vtr+synlig
December 10, 2024 17:40 1h 14m 12s
[WIP] Synlig, new system-verilog tool integration
Test #9925: Pull request #2841 synchronize by amirarjmand93
December 10, 2024 17:08 32m 27s vtr+synlig
December 10, 2024 17:08 32m 27s