Update golden_results.txt

vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_two_chains/config/golden_results.txt

@@ -1,2 +1,2 @@
- arch	  circuit	  script_params	  vtr_flow_elapsed_time	  vtr_max_mem_stage	  vtr_max_mem	  error	  odin_synth_time	  max_odin_mem	  parmys_synth_time	  max_parmys_mem	  abc_depth	  abc_synth_time	  abc_cec_time	  abc_sec_time	  max_abc_mem	  ace_time	  max_ace_mem	  num_clb	  num_io	  num_memories	  num_mult	  vpr_status	  vpr_revision	  vpr_build_info	  vpr_compiler	  vpr_compiled	  hostname	  rundir	  max_vpr_mem	  num_primary_inputs	  num_primary_outputs	  num_pre_packed_nets	  num_pre_packed_blocks	  num_netlist_clocks	  num_post_packed_nets	  num_post_packed_blocks	  device_width	  device_height	  device_grid_tiles	  device_limiting_resources	  device_name	  pack_mem	  pack_time	  placed_wirelength_est	  place_mem	  place_time	  place_quench_time	  placed_CPD_est	  placed_setup_TNS_est	  placed_setup_WNS_est	  placed_geomean_nonvirtual_intradomain_critical_path_delay_est	  place_delay_matrix_lookup_time	  place_quench_timing_analysis_time	  place_quench_sta_time	  place_total_timing_analysis_time	  place_total_sta_time	  min_chan_width	  routed_wirelength	  min_chan_width_route_success_iteration	  logic_block_area_total	  logic_block_area_used	  min_chan_width_routing_area_total	  min_chan_width_routing_area_per_tile	  min_chan_width_route_time	  min_chan_width_total_timing_analysis_time	  min_chan_width_total_sta_time	  crit_path_routed_wirelength	  crit_path_route_success_iteration	  crit_path_total_nets_routed	  crit_path_total_connections_routed	  crit_path_total_heap_pushes	  crit_path_total_heap_pops	  critical_path_delay	  geomean_nonvirtual_intradomain_critical_path_delay	  setup_TNS	  setup_WNS	  hold_TNS	  hold_WNS	  crit_path_routing_area_total	  crit_path_routing_area_per_tile	  router_lookahead_computation_time	  crit_path_route_time	  crit_path_total_timing_analysis_time	  crit_path_total_sta_time	  num_le	  num_luts	  num_add_blocks	  max_add_chain_length	  num_sub_blocks	  max_sub_chain_length	 
- k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml	  diffeq2.v	  common	  15.33	  vpr	  67.04 MiB	  	  -1	  -1	  0.22	  25508	  5	  0.13	  -1	  -1	  37112	  -1	  -1	  20	  66	  0	  -1	  success	  v8.0.0-6989-g4a9293e1e-dirty	  release IPO VTR_ASSERT_LEVEL=3	  GNU 11.3.0 on Linux-5.15.0-58-generic x86_64	  2023-02-04T01:37:29	  dev	  /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing	  68652	  66	  96	  979	  693	  1	  573	  194	  16	  16	  256	  mult_27	  auto	  29.0 MiB	  0.44	  4603	  67.0 MiB	  0.41	  0.01	  14.521	  -875.561	  -14.521	  14.521	  0.69	  0.00114902	  0.00103798	  0.120695	  0.109525	  60	  12753	  30	  4.83877e+06	  1.10888e+06	  1.27241e+06	  4970.35	  11.04	  0.678618	  0.621526	  10670	  21	  3983	  8885	  2811513	  745110	  17.1299	  17.1299	  -1141.38	  -17.1299	  0	  0	  1.57401e+06	  6148.46	  0.34	  0.46	  0.0715366	  0.0672789	  184	  196	  -1	  -1	  -1	  -1	 
+arch	circuit	script_params	vtr_flow_elapsed_time	vtr_max_mem_stage	vtr_max_mem	error	odin_synth_time	max_odin_mem	parmys_synth_time	max_parmys_mem	abc_depth	abc_synth_time	abc_cec_time	abc_sec_time	max_abc_mem	ace_time	max_ace_mem	num_clb	num_io	num_memories	num_mult	vpr_status	vpr_revision	vpr_build_info	vpr_compiler	vpr_compiled	hostname	rundir	max_vpr_mem	num_primary_inputs	num_primary_outputs	num_pre_packed_nets	num_pre_packed_blocks	num_netlist_clocks	num_post_packed_nets	num_post_packed_blocks	device_width	device_height	device_grid_tiles	device_limiting_resources	device_name	pack_mem	pack_time	placed_wirelength_est	total_swap	accepted_swap	rejected_swap	aborted_swap	place_mem	place_time	place_quench_time	placed_CPD_est	placed_setup_TNS_est	placed_setup_WNS_est	placed_geomean_nonvirtual_intradomain_critical_path_delay_est	place_delay_matrix_lookup_time	place_quench_timing_analysis_time	place_quench_sta_time	place_total_timing_analysis_time	place_total_sta_time	min_chan_width	routed_wirelength	min_chan_width_route_success_iteration	logic_block_area_total	logic_block_area_used	min_chan_width_routing_area_total	min_chan_width_routing_area_per_tile	min_chan_width_route_time	min_chan_width_total_timing_analysis_time	min_chan_width_total_sta_time	crit_path_num_rr_graph_nodes	crit_path_num_rr_graph_edges	crit_path_collapsed_nodes	crit_path_routed_wirelength	crit_path_route_success_iteration	crit_path_total_nets_routed	crit_path_total_connections_routed	crit_path_total_heap_pushes	crit_path_total_heap_pops	critical_path_delay	geomean_nonvirtual_intradomain_critical_path_delay	setup_TNS	setup_WNS	hold_TNS	hold_WNS	crit_path_routing_area_total	crit_path_routing_area_per_tile	router_lookahead_computation_time	crit_path_route_time	crit_path_create_rr_graph_time	crit_path_create_intra_cluster_rr_graph_time	crit_path_tile_lookahead_computation_time	crit_path_router_lookahead_computation_time	crit_path_total_timing_analysis_time	crit_path_total_sta_time	num_le	num_luts	num_add_blocks	max_add_chain_length	num_sub_blocks	max_sub_chain_length	
+k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml	diffeq2.v	common	12.35	vpr	67.75 MiB		-1	-1	0.26	25376	5	0.11	-1	-1	37884	-1	-1	16	66	0	-1	success	v8.0.0-10476-g8192a19e5-dirty	release IPO VTR_ASSERT_LEVEL=2	GNU 11.4.0 on Linux-6.5.0-41-generic x86_64	2024-06-20T15:31:36	amir-virtual-machine	/home/amir/Projects/vtr-yosys42/vtr-verilog-to-routing/vtr_flow/scripts	69376	66	96	983	697	1	554	190	16	16	256	mult_27	auto	29.8 MiB	0.84	4389	47146	15236	27549	4361	67.8 MiB	0.31	0.00	15.1086	-820.39	-15.1086	15.1086	0.72	0.00110442	0.00100643	0.101639	0.0920184	62	10821	24	4.83877e+06	1.00808e+06	1.31386e+06	5132.27	7.57	0.480015	0.438933	39852	267778	-1	9504	19	3117	6464	1896676	526697	17.8558	17.8558	-1048.3	-17.8558	0	0	1.60318e+06	6262.42	0.41	0.35	0.16	-1	-1	0.41	0.0732219	0.0697232	139	200	-1	-1	-1	-1