From 4712f0959efaae253a6d2168de34a22e72f3e09a Mon Sep 17 00:00:00 2001 From: Alessandro Comodi Date: Thu, 21 Oct 2021 09:41:01 +0200 Subject: [PATCH] libarch: interchange: fixed model ports reading Signed-off-by: Alessandro Comodi --- libs/libarchfpga/src/read_fpga_interchange_arch.cpp | 8 ++++++++ vpr/test/test_interchange_netlist.cpp | 2 +- 2 files changed, 9 insertions(+), 1 deletion(-) diff --git a/libs/libarchfpga/src/read_fpga_interchange_arch.cpp b/libs/libarchfpga/src/read_fpga_interchange_arch.cpp index 61e6d5b3232..88a9e782df3 100644 --- a/libs/libarchfpga/src/read_fpga_interchange_arch.cpp +++ b/libs/libarchfpga/src/read_fpga_interchange_arch.cpp @@ -221,6 +221,14 @@ struct ArchReader { "Model output ports can not have combinational sink ports"); } + model_port->min_size = 1; + model_port->size = 1; + if (port.isBus()) { + int s = port.getBus().getBusStart(); + int e = port.getBus().getBusEnd(); + model_port->size = std::abs(e - s) + 1; + } + port_names.insert(std::pair(model_port->name, dir)); //Add the port if (dir == IN_PORT) { diff --git a/vpr/test/test_interchange_netlist.cpp b/vpr/test/test_interchange_netlist.cpp index e77668b17e4..bc1a60dac20 100644 --- a/vpr/test/test_interchange_netlist.cpp +++ b/vpr/test/test_interchange_netlist.cpp @@ -21,7 +21,7 @@ TEST_CASE("read_interchange_netlist", "[vpr]") { std::vector physical_tile_types; std::vector logical_block_types; - FPGAInterchangeReadArch(kArchFile, &arch, physical_tile_types, logical_block_types); + FPGAInterchangeReadArch(kArchFile, /*timing_enabled=*/true, &arch, physical_tile_types, logical_block_types); vpr_setup.user_models = arch.models; vpr_setup.library_models = arch.model_library;