Merge pull request #2648 from verilog-to-routing/temp_add_golden

Add golden results for 3d regression test
verilog-to-routing · Aug 15, 2024 · 4cfadb4 · 4cfadb4
2 parents 3ac6d17 + ac4f788
commit 4cfadb4
Show file tree

Hide file tree

Showing 2 changed files with 5 additions and 1 deletion.
diff --git a/...low/tasks/regression_tests/vtr_reg_nightly_test5/vpr_tight_floorplan_3d/config/config.txt b/...low/tasks/regression_tests/vtr_reg_nightly_test5/vpr_tight_floorplan_3d/config/config.txt
@@ -21,7 +21,7 @@ parse_file=vpr_standard.txt
 qor_parse_file=qor_standard.txt
 
 # Pass requirements
-#pass_requirements_file=pass_requirements.txt
+pass_requirements_file=pass_requirements.txt
 
 # Script parameters
 script_params_common =-starting_stage vpr --route_chan_width 300 --max_router_iterations 400 --router_lookahead map --initial_pres_fac 1.0 --router_profiler_astar_fac 1.5 --seed 3 --device neuron3d

diff --git a/...s/regression_tests/vtr_reg_nightly_test5/vpr_tight_floorplan_3d/config/golden_results.txt b/...s/regression_tests/vtr_reg_nightly_test5/vpr_tight_floorplan_3d/config/golden_results.txt
@@ -0,0 +1,4 @@
+arch	circuit	script_params	vtr_flow_elapsed_time	vtr_max_mem_stage	vtr_max_mem	error	odin_synth_time	max_odin_mem	parmys_synth_time	max_parmys_mem	abc_depth	abc_synth_time	abc_cec_time	abc_sec_time	max_abc_mem	ace_time	max_ace_mem	num_clb	num_io	num_memories	num_mult	vpr_status	vpr_revision	vpr_build_info	vpr_compiler	vpr_compiled	hostname	rundir	max_vpr_mem	num_primary_inputs	num_primary_outputs	num_pre_packed_nets	num_pre_packed_blocks	num_netlist_clocks	num_post_packed_nets	num_post_packed_blocks	device_width	device_height	device_grid_tiles	device_limiting_resources	device_name	pack_mem	pack_time	placed_wirelength_est	total_swap	accepted_swap	rejected_swap	aborted_swap	place_mem	place_time	place_quench_time	placed_CPD_est	placed_setup_TNS_est	placed_setup_WNS_est	placed_geomean_nonvirtual_intradomain_critical_path_delay_est	place_delay_matrix_lookup_time	place_quench_timing_analysis_time	place_quench_sta_time	place_total_timing_analysis_time	place_total_sta_time	min_chan_width	routed_wirelength	min_chan_width_route_success_iteration	logic_block_area_total	logic_block_area_used	min_chan_width_routing_area_total	min_chan_width_routing_area_per_tile	min_chan_width_route_time	min_chan_width_total_timing_analysis_time	min_chan_width_total_sta_time	crit_path_num_rr_graph_nodes	crit_path_num_rr_graph_edges	crit_path_collapsed_nodes	crit_path_routed_wirelength	crit_path_route_success_iteration	crit_path_total_nets_routed	crit_path_total_connections_routed	crit_path_total_heap_pushes	crit_path_total_heap_pops	critical_path_delay	geomean_nonvirtual_intradomain_critical_path_delay	setup_TNS	setup_WNS	hold_TNS	hold_WNS	crit_path_routing_area_total	crit_path_routing_area_per_tile	router_lookahead_computation_time	crit_path_route_time	crit_path_create_rr_graph_time	crit_path_create_intra_cluster_rr_graph_time	crit_path_tile_lookahead_computation_time	crit_path_router_lookahead_computation_time	crit_path_total_timing_analysis_time	crit_path_total_sta_time	
+3d_full_OPIN_inter_die_stratixiv_arch.timing.xml	neuron_stratixiv_arch_timing.blif	common_-sdc_file_sdc/samples/neuron_stratixiv_arch_timing.sdc_-read_vpr_constraints_tasks/regression_tests/vtr_reg_nightly_test5/vpr_tight_floorplan_3d/one_big_partition.xml	835.38	vpr	2.86 GiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	42	-1	-1	success	16adbfa-dirty	release IPO VTR_ASSERT_LEVEL=2	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-07-15T00:59:58	gh-actions-runner-vtr-auto-spawned49	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	2998168	42	35	119888	86875	1	50931	3418	92	68	12512	-1	neuron3d	1871.5 MiB	125.92	471295	2911586	1070954	1811088	29544	2883.9 MiB	225.67	2.10	7.73071	-71900.2	-6.73071	5.03261	0.22	0.369023	0.308324	43.731	35.9598	-1	672628	24	0	0	2.71622e+08	21708.9	79.02	68.1319	57.7539	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	
+3d_full_OPIN_inter_die_stratixiv_arch.timing.xml	neuron_stratixiv_arch_timing.blif	common_-sdc_file_sdc/samples/neuron_stratixiv_arch_timing.sdc_-read_vpr_constraints_tasks/regression_tests/vtr_reg_nightly_test5/vpr_tight_floorplan_3d/half_blocks_right_left.xml	820.30	vpr	2.86 GiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	42	-1	-1	success	16adbfa-dirty	release IPO VTR_ASSERT_LEVEL=2	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-07-15T00:59:58	gh-actions-runner-vtr-auto-spawned49	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	2995656	42	35	119888	86875	1	50982	3427	92	68	12512	-1	neuron3d	1869.5 MiB	127.02	455014	2973417	1101001	1762977	109439	2881.6 MiB	223.03	1.76	7.42684	-70436.4	-6.42684	5.75387	0.23	0.367143	0.304401	44.7203	37.4852	-1	654498	28	0	0	2.71622e+08	21708.9	78.86	71.0006	61.0273	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	
+3d_full_OPIN_inter_die_stratixiv_arch.timing.xml	neuron_stratixiv_arch_timing.blif	common_-sdc_file_sdc/samples/neuron_stratixiv_arch_timing.sdc_-read_vpr_constraints_tasks/regression_tests/vtr_reg_nightly_test5/vpr_tight_floorplan_3d/half_blocks_up_down.xml	812.45	vpr	2.86 GiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	42	-1	-1	success	16adbfa-dirty	release IPO VTR_ASSERT_LEVEL=2	GNU 9.5.0 on Linux-5.10.35-v8 x86_64	2024-07-15T00:59:58	gh-actions-runner-vtr-auto-spawned49	/root/vtr-verilog-to-routing/vtr-verilog-to-routing	2995760	42	35	119888	86875	1	50982	3427	92	68	12512	-1	neuron3d	1869.6 MiB	125.77	465634	3050895	1119051	1501125	430719	2881.9 MiB	206.05	1.47	7.58328	-72552.7	-6.58328	5.5951	0.22	0.365879	0.300546	45.7365	37.5853	-1	663695	23	0	0	2.71622e+08	21708.9	79.71	69.6049	58.853	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1