diff --git a/dev/subtree_config.xml b/dev/subtree_config.xml index a1dc1c57d70..3d230120ed7 100644 --- a/dev/subtree_config.xml +++ b/dev/subtree_config.xml @@ -58,7 +58,7 @@ name="yosys" internal_path="yosys" external_url="https://github.com/YosysHQ/yosys.git" - default_external_ref="yosys-0.26"/> + default_external_ref="yosys-0.32"/> ( @@ -216,34 +216,47 @@ class t_rr_graph_storage { */ const char* node_side_string(RRNodeId id) const; - /* PTC get methods */ + /** @brief PTC get methods */ int node_ptc_num(RRNodeId id) const; int node_pin_num(RRNodeId id) const; //Same as ptc_num() but checks that type() is consistent int node_track_num(RRNodeId id) const; //Same as ptc_num() but checks that type() is consistent int node_class_num(RRNodeId id) const; //Same as ptc_num() but checks that type() is consistent - /* Retrieve fan_in for RRNodeId, init_fan_in must have been called first. */ + /** @brief Retrieve fan_in for RRNodeId, init_fan_in must have been called first. */ t_edge_size fan_in(RRNodeId id) const { return node_fan_in_[id]; } - /* Find the layer number that RRNodeId is located at. + /** @brief Find the layer number that RRNodeId is located at. * it is zero if the FPGA only has one die. * The layer number start from the base die (base die: 0, the die above it: 1, etc.) - * */ + */ short node_layer(RRNodeId id) const{ return node_layer_[id]; } - // This prefetechs hot RR node data required for optimization. - // - // Note: This is optional, but may lower time spent on memory stalls in - // some circumstances. - inline void prefetch_node(RRNodeId id) const { - VTR_PREFETCH(&node_storage_[id], 0, 0); + /** @brief Find the twist number that RR node uses to change ptc number across the same track. + * By default this number is zero, meaning that ptc number across the same track should be the same. + * This number is only meaningful for CHANX/CHANY nodes, not the other nodes. + */ + short node_ptc_twist(RRNodeId id) const{ + //check whether node_ptc_twist_incr has been allocated + if(node_ptc_twist_incr_.empty()){ + return 0; + } + return node_ptc_twist_incr_[id]; } - /* Edge accessors + /** @brief This prefetechs hot RR node data required for optimization. + * + * Note: This is optional, but may lower time spent on memory stalls in + * some circumstances. + */ + inline void prefetch_node(RRNodeId id) const { + VTR_PREFETCH(&node_storage_[id], 0, 0); + } + + /** @brief Edge accessors * * Preferred access methods: * - first_edge(RRNodeId) @@ -263,7 +276,8 @@ class t_rr_graph_storage { * - edge_sink_node(RRNodeId, t_edge_size) * - edge_switch(RRNodeId, t_edge_size) * - * Only call these methods after partition_edges has been invoked. */ + * Only call these methods after partition_edges has been invoked. + */ edge_idx_range edges(const RRNodeId& id) const { return vtr::make_range(edge_idx_iterator(0), edge_idx_iterator(num_edges(id))); } @@ -282,37 +296,39 @@ class t_rr_graph_storage { t_edge_size num_configurable_edges(RRNodeId node, const vtr::vector& rr_switches) const; t_edge_size num_non_configurable_edges(RRNodeId node, const vtr::vector& rr_switches) const; - // Get the first and last RREdgeId for the specified RRNodeId. - // - // The edges belonging to RRNodeId is [first_edge, last_edge), excluding - // last_edge. - // - // If first_edge == last_edge, then a RRNodeId has no edges. - RREdgeId first_edge(const RRNodeId& id) const { + /** @brief Get the first and last RREdgeId for the specified RRNodeId. + * + * The edges belonging to RRNodeId is [first_edge, last_edge), excluding + * last_edge. + * + * If first_edge == last_edge, then a RRNodeId has no edges. + */ + RREdgeId first_edge(const RRNodeId& id) const { return node_first_edge_[id]; } - // Return the first_edge of the next rr_node, which is one past the edge - // id range for the node we care about. - // - // This implies we have one dummy rr_node at the end of first_edge_, and - // we always allocate that dummy node. We also assume that the edges have - // been sorted by rr_node, which is true after partition_edges(). + /** @brief the first_edge of the next rr_node, which is one past the edge id range for the node we care about. + * This implies we have one dummy rr_node at the end of first_edge_, and + * we always allocate that dummy node. We also assume that the edges have + * been sorted by rr_node, which is true after partition_edges(). + */ RREdgeId last_edge(const RRNodeId& id) const { return (&node_first_edge_[id])[1]; } - // Returns a range of RREdgeId's belonging to RRNodeId id. - // - // If this range is empty, then RRNodeId id has no edges. + /** @brief Returns a range of RREdgeId's belonging to RRNodeId id. + * + * If this range is empty, then RRNodeId id has no edges. + */ vtr::StrongIdRange edge_range(const RRNodeId id) const { return vtr::StrongIdRange(first_edge(id), last_edge(id)); } - // Retrieve the RREdgeId for iedge'th edge in RRNodeId. - // - // This method should generally not be used, and instead first_edge and - // last_edge should be used. + /** @brief Retrieve the RREdgeId for iedge'th edge in RRNodeId. + * + * This method should generally not be used, and instead first_edge and + * last_edge should be used. + */ RREdgeId edge_id(const RRNodeId& id, t_edge_size iedge) const { RREdgeId first_edge = this->first_edge(id); RREdgeId ret(size_t(first_edge) + iedge); @@ -320,12 +336,12 @@ class t_rr_graph_storage { return ret; } - // Get the destination node for the specified edge. + /** @brief Get the destination node for the specified edge. */ RRNodeId edge_sink_node(const RREdgeId& edge) const { return edge_dest_node_[edge]; } - // Call the `apply` function with the edge id, source, and sink nodes of every edge. + /** @brief Call the `apply` function with the edge id, source, and sink nodes of every edge. */ void for_each_edge(std::function apply) const { for (size_t i = 0; i < edge_dest_node_.size(); i++) { RREdgeId edge(i); @@ -333,28 +349,30 @@ class t_rr_graph_storage { } } - // Get the destination node for the iedge'th edge from specified RRNodeId. - // - // This method should generally not be used, and instead first_edge and - // last_edge should be used. + /** @brief Get the destination node for the iedge'th edge from specified RRNodeId. + * + * This method should generally not be used, and instead first_edge and + * last_edge should be used. + */ RRNodeId edge_sink_node(const RRNodeId& id, t_edge_size iedge) const { return edge_sink_node(edge_id(id, iedge)); } - // Get the switch used for the specified edge. + /** @brief Get the switch used for the specified edge. */ short edge_switch(const RREdgeId& edge) const { return edge_switch_[edge]; } - // Get the switch used for the iedge'th edge from specified RRNodeId. - // - // This method should generally not be used, and instead first_edge and - // last_edge should be used. + /** @brief Get the switch used for the iedge'th edge from specified RRNodeId. + * + * This method should generally not be used, and instead first_edge and + * last_edge should be used. + */ short edge_switch(const RRNodeId& id, t_edge_size iedge) const { return edge_switch(edge_id(id, iedge)); } - /* + /** @brief * Node proxy methods * * The following methods implement an interface that appears to be @@ -373,7 +391,7 @@ class t_rr_graph_storage { * These methods should not be used by new VPR code, and instead access * methods that use RRNodeId and RREdgeId should be used. * - **********************/ + */ node_idx_iterator begin() const; @@ -393,19 +411,21 @@ class t_rr_graph_storage { * Node allocation methods * ***************************/ - // Makes room in storage for RRNodeId in amoritized O(1) fashion. - // - // This results in an allocation pattern similiar to what would happen - // if push_back(x) / emplace_back() were used if underlying storage - // was not preallocated. + /** @brief + * Makes room in storage for RRNodeId in amoritized O(1) fashion. + * This results in an allocation pattern similiar to what would happen + * if push_back(x) / emplace_back() were used if underlying storage + * was not pre-allocated. + */ void make_room_for_node(RRNodeId elem_position) { make_room_in_vector(&node_storage_, size_t(elem_position)); node_ptc_.reserve(node_storage_.capacity()); node_ptc_.resize(node_storage_.size()); node_layer_.resize(node_storage_.size()); + node_ptc_twist_incr_.resize(node_storage_.size()); } - // Reserve storage for RR nodes. + /** @brief Reserve storage for RR nodes. */ void reserve(size_t size) { // No edges can be assigned if mutating the rr node array. VTR_ASSERT(!edges_read_); @@ -414,7 +434,7 @@ class t_rr_graph_storage { node_layer_.reserve(size); } - // Resize node storage to accomidate size RR nodes. + /** @brief Resize node storage to accomidate size RR nodes. */ void resize(size_t size) { // No edges can be assigned if mutating the rr node array. VTR_ASSERT(!edges_read_); @@ -423,25 +443,31 @@ class t_rr_graph_storage { node_layer_.resize(size); } - // Number of RR nodes that can be accessed. + /** @brief We only allocate the ptc twist increment array while building tileable rr-graphs */ + void resize_ptc_twist_incr(size_t size){ + node_ptc_twist_incr_.resize(size); + } + + /** @brief Number of RR nodes that can be accessed. */ size_t size() const { return node_storage_.size(); } - // Is the RR graph currently empty? + /** @brief Is the RR graph currently empty? */ bool empty() const { return node_storage_.empty(); } - // Remove all nodes and edges from the RR graph. - // - // This method re-enables graph mutation if the graph was read-only. + /** @brief Remove all nodes and edges from the RR graph. + * This method re-enables graph mutation if the graph was read-only. + */ void clear() { node_storage_.clear(); node_ptc_.clear(); node_first_edge_.clear(); node_fan_in_.clear(); node_layer_.clear(); + node_ptc_twist_incr_.clear(); edge_src_node_.clear(); edge_dest_node_.clear(); edge_switch_.clear(); @@ -451,35 +477,38 @@ class t_rr_graph_storage { remapped_edges_ = false; } - // Clear the data structures that are mainly used during RR graph construction. - // After RR Graph is build, we no longer need these data structures. + /** @brief + * Clear the data structures that are mainly used during RR graph construction. + * After RR Graph is build, we no longer need these data structures. + */ void clear_temp_storage() { edge_remapped_.clear(); } - // Clear edge_remap data structure, and then initialize it with the given value + /** @brief Clear edge_remap data structure, and then initialize it with the given value */ void init_edge_remap(bool val) { edge_remapped_.clear(); edge_remapped_.resize(edge_switch_.size(), val); } - // Shrink memory usage of the RR graph storage. - // - // Note that this will temporarily increase the amount of storage required - // to allocate the small array and copy the data. + /** @brief Shrink memory usage of the RR graph storage. + * Note that this will temporarily increase the amount of storage required + * to allocate the small array and copy the data. + */ void shrink_to_fit() { node_storage_.shrink_to_fit(); node_ptc_.shrink_to_fit(); node_first_edge_.shrink_to_fit(); node_fan_in_.shrink_to_fit(); node_layer_.shrink_to_fit(); + node_ptc_twist_incr_.shrink_to_fit(); edge_src_node_.shrink_to_fit(); edge_dest_node_.shrink_to_fit(); edge_switch_.shrink_to_fit(); edge_remapped_.shrink_to_fit(); } - // Append 1 more RR node to the RR graph. + /** @brief Append 1 more RR node to the RR graph.*/ void emplace_back() { // No edges can be assigned if mutating the rr node array. VTR_ASSERT(!edges_read_); @@ -488,15 +517,16 @@ class t_rr_graph_storage { node_layer_.emplace_back(); } - // Given `order`, a vector mapping each RRNodeId to a new one (old -> new), - // and `inverse_order`, its inverse (new -> old), update the t_rr_graph_storage - // data structure to an isomorphic graph using the new RRNodeId's. - // NOTE: Re-ordering will invalidate any external references, so this - // should generally be called before creating such references. + /** @brief Given `order`, a vector mapping each RRNodeId to a new one (old -> new), + * and `inverse_order`, its inverse (new -> old), update the t_rr_graph_storage + * data structure to an isomorphic graph using the new RRNodeId's. + * NOTE: Re-ordering will invalidate any external references, so this + * should generally be called before creating such references. + */ void reorder(const vtr::vector& order, const vtr::vector& inverse_order); - /* PTC set methods */ + /** @brief PTC set methods */ void set_node_ptc_num(RRNodeId id, int); void set_node_pin_num(RRNodeId id, int); //Same as set_ptc_num() by checks type() is consistent void set_node_track_num(RRNodeId id, int); //Same as set_ptc_num() by checks type() is consistent @@ -505,12 +535,14 @@ class t_rr_graph_storage { void set_node_type(RRNodeId id, t_rr_type new_type); void set_node_coordinates(RRNodeId id, short x1, short y1, short x2, short y2); void set_node_layer(RRNodeId id, short layer); + void set_node_ptc_twist_incr(RRNodeId id, short twist); void set_node_cost_index(RRNodeId, RRIndexedDataId new_cost_index); void set_node_rc_index(RRNodeId, NodeRCIndex new_rc_index); void set_node_capacity(RRNodeId, short new_capacity); void set_node_direction(RRNodeId, Direction new_direction); - /* Add a side to the node abbributes + /** @brief + * Add a side to the node abbributes * This is the function to use when you just add a new side WITHOUT reseting side attributes */ void add_node_side(RRNodeId, e_side new_side); @@ -568,7 +600,7 @@ class t_rr_graph_storage { /* Edge mutators */ - // Reserve at least num_edges in the edge backing arrays. + /** @brief Reserve at least num_edges in the edge backing arrays. */ void reserve_edges(size_t num_edges); /*** @@ -584,36 +616,41 @@ class t_rr_graph_storage { */ void emplace_back_edge(RRNodeId src, RRNodeId dest, short edge_switch, bool remapped); - // Adds a batch of edges. + /** @brief Adds a batch of edges.*/ void alloc_and_load_edges(const t_rr_edge_info_set* rr_edges_to_create); /* Edge finalization methods */ - // Counts the number of rr switches needed based on fan in to support mux - // size dependent switch delays. - // - // init_fan_in does not need to be invoked before this method. - size_t count_rr_switches( + /** @brief Counts the number of rr switches needed based on fan in to support mux + * size dependent switch delays. + * + * init_fan_in does not need to be invoked before this method. + */ + size_t count_rr_switches( const std::vector& arch_switch_inf, t_arch_switch_fanin& arch_switch_fanins); - // Maps arch_switch_inf indicies to rr_switch_inf indicies. - // - // This must be called before partition_edges if edges were created with - // arch_switch_inf indicies. + /** @brief Maps arch_switch_inf indicies to rr_switch_inf indicies. + * + * This must be called before partition_edges if edges were created with + * arch_switch_inf indicies. + */ void remap_rr_node_switch_indices(const t_arch_switch_fanin& switch_fanin); - // Marks that edge switch values are rr switch indicies. - // - // This must be called before partition_edges if edges were created with - // rr_switch_inf indicies. + /** @brief Marks that edge switch values are rr switch indicies. + * + * This must be called before partition_edges if edges were created with + * rr_switch_inf indicies. + */ void mark_edges_as_rr_switch_ids(); - // Sorts edge data such that configurable edges appears before - // non-configurable edges. + /** @brief + * Sorts edge data such that configurable edges appears before + * non-configurable edges. + */ void partition_edges(const vtr::vector& rr_switches); - // Validate that edge data is partitioned correctly. + /** @brief Validate that edge data is partitioned correctly.*/ bool validate_node(RRNodeId node_id, const vtr::vector& rr_switches) const; bool validate(const vtr::vector& rr_switches) const; @@ -621,9 +658,8 @@ class t_rr_graph_storage { * Fan-in methods * ******************/ - /* Init per node fan-in data. Should only be called after all edges have - * been allocated - * + /** @brief Init per node fan-in data. + * Should only be called after all edges have been allocated * This is an expensive, O(N), operation so it should be called once you * have a complete rr-graph and not called often.*/ void init_fan_in(); @@ -664,11 +700,13 @@ class t_rr_graph_storage { friend class edge_compare_dest_node; friend class edge_compare_src_node_and_configurable_first; - // Take allocated edges in edge_src_node_/ edge_dest_node_ / edge_switch_ - // sort, and assign the first edge for each + /** @brief + * Take allocated edges in edge_src_node_/ edge_dest_node_ / edge_switch_ + * sort, and assign the first edge for each + */ void assign_first_edges(); - // Verify that first_edge_ array correctly partitions rr edge data. + /** @brief Verify that first_edge_ array correctly partitions rr edge data. */ bool verify_first_edges() const; /***************** @@ -687,33 +725,51 @@ class t_rr_graph_storage { * *****************/ - // storage_ stores the core RR node data used by the router and is **very** - // hot. + /** @brief + * storage_ stores the core RR node data used by the router and is **very** + * hot. + */ vtr::vector> node_storage_; - // The PTC data is cold data, and is generally not used during the inner - // loop of either the placer or router. + /**@brief + * The PTC data is cold data, and is generally not used during the inner + * loop of either the placer or router. + */ vtr::vector node_ptc_; - // This array stores the first edge of each RRNodeId. Not that the length - // of this vector is always storage_.size() + 1, where the last value is - // always equal to the number of edges in the final graph. + /** @brief + * This array stores the first edge of each RRNodeId. Not that the length + * of this vector is always storage_.size() + 1, where the last value is + * always equal to the number of edges in the final graph. + */ vtr::vector node_first_edge_; - // Fan in counts for each RR node. + /** @brief Fan in counts for each RR node. */ vtr::vector node_fan_in_; - // Layer number that each RR node is located at - // Layer number refers to the die that the node belongs to. The layer number of base die is zero and die above it one, etc. - // This data is also considered as a hot data since it is used in inner loop of router, but since it didn't fit nicely into t_rr_node_data due to alignment issues, we had to store it - // in a separate vector. + /** @brief + * Layer number that each RR node is located at + * Layer number refers to the die that the node belongs to. The layer number of base die is zero and die above it one, etc. + * This data is also considered as a hot data since it is used in inner loop of router, but since it didn't fit nicely into t_rr_node_data due to alignment issues, we had to store it + *in a separate vector. + */ vtr::vector node_layer_; - // Edge storage. + /** @brief + *Twist Increment number is defined for CHANX/CHANY nodes; it is useful for layout of tileable FPGAs used by openFPGA. + *It gives us a new track index in each tile a longer wire crosses, which enables us to make long wires with a repeated single-tile pattern that "twists" the wires as they cross the tile. + *For example, an L4 wire would change tracks 4 times with metal shorts [e.g. 0, 2, 4, 6] and track 6 would drive a switch -- together this implements an L4 wire with only one layout tile. + * Twist increment number is only meaningful for CHANX and CHANY nodes; it is 0 for other node types. + * We also don't bother allocating this storage if the FPGA is not specified to be tileable; instead in that case the twist for all nodes will always be returned as 0. + */ + vtr::vector node_ptc_twist_incr_; + + /** @brief Edge storage */ vtr::vector edge_src_node_; vtr::vector edge_dest_node_; vtr::vector edge_switch_; - /** + + /** @brief * The delay of certain switches specified in the architecture file depends on the number of inputs of the edge's sink node (pins or tracks). * For example, in the case of a MUX switch, the delay increases as the number of inputs increases. * During the construction of the RR Graph, switch IDs are assigned to the edges according to the order specified in the architecture file. @@ -736,25 +792,27 @@ class t_rr_graph_storage { ***************/ public: /* Since rr_node_storage is an internal data of RRGraphView and RRGraphBuilder, expose these flags as public */ - // Has any edges been read? - // - // Any method that mutates edge storage will be locked out after this - // variable is set. - // - // Reading any of the following members should set this flag: - // - edge_src_node_ - // - edge_dest_node_ - // - edge_switch_ + /** @brief Has any edges been read? + * + * Any method that mutates edge storage will be locked out after this + * variable is set. + * + * Reading any of the following members should set this flag: + * - edge_src_node_ + * - edge_dest_node_ + * - edge_switch_ + */ mutable bool edges_read_; - // Set after either remap_rr_node_switch_indices or mark_edges_as_rr_switch_ids - // has been called. - // - // remap_rr_node_switch_indices converts indices to arch_switch_inf into - // indices to rr_switch_inf. + /** @brief Set after either remap_rr_node_switch_indices or mark_edges_as_rr_switch_ids + * has been called. + * + * remap_rr_node_switch_indices converts indices to arch_switch_inf into + * indices to rr_switch_inf. + */ bool remapped_edges_; - // Set after partition_edges has been called. + /** @brief Set after partition_edges has been called. */ bool partitioned_; }; @@ -775,6 +833,7 @@ class t_rr_graph_view { const vtr::array_view_id node_first_edge, const vtr::array_view_id node_fan_in, const vtr::array_view_id node_layer, + const vtr::array_view_id node_ptc_twist_incr, const vtr::array_view_id edge_src_node, const vtr::array_view_id edge_dest_node, const vtr::array_view_id edge_switch) @@ -783,6 +842,7 @@ class t_rr_graph_view { , node_first_edge_(node_first_edge) , node_fan_in_(node_fan_in) , node_layer_(node_layer) + , node_ptc_twist_incr_(node_ptc_twist_incr) , edge_src_node_(edge_src_node) , edge_dest_node_(edge_dest_node) , edge_switch_(edge_switch) {} @@ -844,6 +904,15 @@ class t_rr_graph_view { return node_layer_[id]; } + /* Retrieve twist number (if available) that RRNodeId used for its ptc number */ + short node_ptc_twist_incr(RRNodeId id) const{ + //check if ptc twist increment allocated + if(node_ptc_twist_incr_.empty()){ + return 0; //if it is not allocated we just assume that is zero + } + return node_ptc_twist_incr_[id]; + } + // This prefetechs hot RR node data required for optimization. // // Note: This is optional, but may lower time spent on memory stalls in @@ -885,6 +954,7 @@ class t_rr_graph_view { vtr::array_view_id node_first_edge_; vtr::array_view_id node_fan_in_; vtr::array_view_id node_layer_; + vtr::array_view_id node_ptc_twist_incr_; vtr::array_view_id edge_src_node_; vtr::array_view_id edge_dest_node_; vtr::array_view_id edge_switch_; diff --git a/libs/librrgraph/src/base/rr_graph_view.h b/libs/librrgraph/src/base/rr_graph_view.h index 3d808b23c71..1ff9a33115e 100644 --- a/libs/librrgraph/src/base/rr_graph_view.h +++ b/libs/librrgraph/src/base/rr_graph_view.h @@ -164,6 +164,11 @@ class RRGraphView { inline short node_layer(RRNodeId node) const { return node_storage_.node_layer(node); } + + /** @brief Get the ptc number twist of a routing resource node. This function is inlined for runtime optimization. */ + inline short node_ptc_twist(RRNodeId node) const{ + return node_storage_.node_ptc_twist(node); + } /** @brief Get the first out coming edge of resource node. This function is inlined for runtime optimization. */ inline RREdgeId node_first_edge(RRNodeId node) const { diff --git a/libs/librrgraph/src/io/gen/rr_graph_uxsdcxx.h b/libs/librrgraph/src/io/gen/rr_graph_uxsdcxx.h index 20f24fcd4f6..5099e2309e8 100644 --- a/libs/librrgraph/src/io/gen/rr_graph_uxsdcxx.h +++ b/libs/librrgraph/src/io/gen/rr_graph_uxsdcxx.h @@ -4,9 +4,9 @@ * https://github.com/duck2/uxsdcxx * Modify only if your build process doesn't involve regenerating this file. * - * Cmdline: uxsdcxx/uxsdcxx.py /home/amin/Desktop/vtr-verilog-to-routing/libs/librrgraph/src/io/rr_graph.xsd - * Input file: /home/amin/Desktop/vtr-verilog-to-routing/libs/librrgraph/src/io/rr_graph.xsd - * md5sum of input file: 38649d034e0edccbcb511ddb8915cdff + * Cmdline: uxsdcxx/uxsdcxx.py /home/smahmoudi/Desktop/vtr/vtr-verilog-to-routing/libs/librrgraph/src/io/rr_graph.xsd + * Input file: /home/smahmoudi/Desktop/vtr/vtr-verilog-to-routing/libs/librrgraph/src/io/rr_graph.xsd + * md5sum of input file: bf49388f038e0d0e4a12403ebb964b42 */ #include @@ -275,8 +275,8 @@ constexpr const char *atok_lookup_t_grid_loc[] = {"block_type_id", "height_offse enum class gtok_t_grid_locs {GRID_LOC}; constexpr const char *gtok_lookup_t_grid_locs[] = {"grid_loc"}; -enum class atok_t_node_loc {LAYER, PTC, SIDE, XHIGH, XLOW, YHIGH, YLOW}; -constexpr const char *atok_lookup_t_node_loc[] = {"layer", "ptc", "side", "xhigh", "xlow", "yhigh", "ylow"}; +enum class atok_t_node_loc {LAYER, PTC, SIDE, TWIST, XHIGH, XLOW, YHIGH, YLOW}; +constexpr const char *atok_lookup_t_node_loc[] = {"layer", "ptc", "side", "twist", "xhigh", "xlow", "yhigh", "ylow"}; enum class atok_t_node_timing {C, R}; @@ -1138,6 +1138,14 @@ inline atok_t_node_loc lex_attr_t_node_loc(const char *in, const std::function * report_error){ - std::bitset<7> astate = 0; + std::bitset<8> astate = 0; for(pugi::xml_attribute attr = root.first_attribute(); attr; attr = attr.next_attribute()){ atok_t_node_loc in = lex_attr_t_node_loc(attr.name(), report_error); if(astate[(int)in] == 0) astate[(int)in] = 1; @@ -2354,6 +2362,9 @@ inline void load_node_loc_required_attributes(const pugi::xml_node &root, int * case atok_t_node_loc::SIDE: /* Attribute side set after element init */ break; + case atok_t_node_loc::TWIST: + /* Attribute twist set after element init */ + break; case atok_t_node_loc::XHIGH: *xhigh = load_int(attr.value(), report_error); break; @@ -2369,7 +2380,7 @@ inline void load_node_loc_required_attributes(const pugi::xml_node &root, int * default: break; /* Not possible. */ } } - std::bitset<7> test_astate = astate | std::bitset<7>(0b0000101); + std::bitset<8> test_astate = astate | std::bitset<8>(0b00001101); if(!test_astate.all()) attr_error(test_astate, atok_lookup_t_node_loc, report_error); } @@ -3281,6 +3292,9 @@ inline void load_node_loc(const pugi::xml_node &root, T &out, Context &context, case atok_t_node_loc::SIDE: out.set_node_loc_side(lex_enum_loc_side(attr.value(), true, report_error), context); break; + case atok_t_node_loc::TWIST: + out.set_node_loc_twist(load_int(attr.value(), report_error), context); + break; case atok_t_node_loc::XHIGH: /* Attribute xhigh is already set */ break; @@ -4011,6 +4025,8 @@ inline void write_node(T &in, std::ostream &os, Context &context){ os << " ptc=\"" << in.get_node_loc_ptc(child_context) << "\""; if((bool)in.get_node_loc_side(child_context)) os << " side=\"" << lookup_loc_side[(int)in.get_node_loc_side(child_context)] << "\""; + if((bool)in.get_node_loc_twist(child_context)) + os << " twist=\"" << in.get_node_loc_twist(child_context) << "\""; os << " xhigh=\"" << in.get_node_loc_xhigh(child_context) << "\""; os << " xlow=\"" << in.get_node_loc_xlow(child_context) << "\""; os << " yhigh=\"" << in.get_node_loc_yhigh(child_context) << "\""; diff --git a/libs/librrgraph/src/io/gen/rr_graph_uxsdcxx_capnp.h b/libs/librrgraph/src/io/gen/rr_graph_uxsdcxx_capnp.h index 8bea9c7c033..c523a6d7f42 100644 --- a/libs/librrgraph/src/io/gen/rr_graph_uxsdcxx_capnp.h +++ b/libs/librrgraph/src/io/gen/rr_graph_uxsdcxx_capnp.h @@ -4,9 +4,9 @@ * https://github.com/duck2/uxsdcxx * Modify only if your build process doesn't involve regenerating this file. * - * Cmdline: uxsdcxx/uxsdcap.py /home/amin/Desktop/vtr-verilog-to-routing/libs/librrgraph/src/io/rr_graph.xsd - * Input file: /home/amin/Desktop/vtr-verilog-to-routing/libs/librrgraph/src/io/rr_graph.xsd - * md5sum of input file: 38649d034e0edccbcb511ddb8915cdff + * Cmdline: uxsdcxx/uxsdcap.py /home/smahmoudi/Desktop/vtr/vtr-verilog-to-routing/libs/librrgraph/src/io/rr_graph.xsd + * Input file: /home/smahmoudi/Desktop/vtr/vtr-verilog-to-routing/libs/librrgraph/src/io/rr_graph.xsd + * md5sum of input file: bf49388f038e0d0e4a12403ebb964b42 */ #include @@ -707,6 +707,7 @@ inline void load_node_loc_capnp_type(const ucap::NodeLoc::Reader &root, T &out, out.set_node_loc_layer(root.getLayer(), context); out.set_node_loc_side(conv_enum_loc_side(root.getSide(), report_error), context); + out.set_node_loc_twist(root.getTwist(), context); } template @@ -1160,6 +1161,8 @@ inline void write_node_capnp_type(T &in, ucap::Node::Builder &root, Context &con node_loc.setPtc(in.get_node_loc_ptc(child_context)); if((bool)in.get_node_loc_side(child_context)) node_loc.setSide(conv_to_enum_loc_side(in.get_node_loc_side(child_context))); + if((bool)in.get_node_loc_twist(child_context)) + node_loc.setTwist(in.get_node_loc_twist(child_context)); node_loc.setXhigh(in.get_node_loc_xhigh(child_context)); node_loc.setXlow(in.get_node_loc_xlow(child_context)); node_loc.setYhigh(in.get_node_loc_yhigh(child_context)); diff --git a/libs/librrgraph/src/io/gen/rr_graph_uxsdcxx_interface.h b/libs/librrgraph/src/io/gen/rr_graph_uxsdcxx_interface.h index d31082159a7..1fa575acf1a 100644 --- a/libs/librrgraph/src/io/gen/rr_graph_uxsdcxx_interface.h +++ b/libs/librrgraph/src/io/gen/rr_graph_uxsdcxx_interface.h @@ -4,9 +4,9 @@ * https://github.com/duck2/uxsdcxx * Modify only if your build process doesn't involve regenerating this file. * - * Cmdline: uxsdcxx/uxsdcxx.py /home/amin/Desktop/vtr-verilog-to-routing/libs/librrgraph/src/io/rr_graph.xsd - * Input file: /home/amin/Desktop/vtr-verilog-to-routing/libs/librrgraph/src/io/rr_graph.xsd - * md5sum of input file: 38649d034e0edccbcb511ddb8915cdff + * Cmdline: uxsdcxx/uxsdcxx.py /home/smahmoudi/Desktop/vtr/vtr-verilog-to-routing/libs/librrgraph/src/io/rr_graph.xsd + * Input file: /home/smahmoudi/Desktop/vtr/vtr-verilog-to-routing/libs/librrgraph/src/io/rr_graph.xsd + * md5sum of input file: bf49388f038e0d0e4a12403ebb964b42 */ #include @@ -368,6 +368,7 @@ class RrGraphBase { * * * + * * */ virtual inline int get_node_loc_layer(typename ContextTypes::NodeLocReadContext &ctx) = 0; @@ -375,6 +376,8 @@ class RrGraphBase { virtual inline int get_node_loc_ptc(typename ContextTypes::NodeLocReadContext &ctx) = 0; virtual inline enum_loc_side get_node_loc_side(typename ContextTypes::NodeLocReadContext &ctx) = 0; virtual inline void set_node_loc_side(enum_loc_side side, typename ContextTypes::NodeLocWriteContext &ctx) = 0; + virtual inline int get_node_loc_twist(typename ContextTypes::NodeLocReadContext &ctx) = 0; + virtual inline void set_node_loc_twist(int twist, typename ContextTypes::NodeLocWriteContext &ctx) = 0; virtual inline int get_node_loc_xhigh(typename ContextTypes::NodeLocReadContext &ctx) = 0; virtual inline int get_node_loc_xlow(typename ContextTypes::NodeLocReadContext &ctx) = 0; virtual inline int get_node_loc_yhigh(typename ContextTypes::NodeLocReadContext &ctx) = 0; diff --git a/libs/librrgraph/src/io/rr_graph.xsd b/libs/librrgraph/src/io/rr_graph.xsd index 17dfe09a7e0..6b6650e100c 100644 --- a/libs/librrgraph/src/io/rr_graph.xsd +++ b/libs/librrgraph/src/io/rr_graph.xsd @@ -266,6 +266,7 @@ + diff --git a/libs/librrgraph/src/io/rr_graph_uxsdcxx_serializer.h b/libs/librrgraph/src/io/rr_graph_uxsdcxx_serializer.h index 9154e353643..736ea358a81 100644 --- a/libs/librrgraph/src/io/rr_graph_uxsdcxx_serializer.h +++ b/libs/librrgraph/src/io/rr_graph_uxsdcxx_serializer.h @@ -713,6 +713,9 @@ class RrGraphSerializer final : public uxsd::RrGraphBase { inline int get_node_loc_layer(const t_rr_node& node) final { return rr_graph_->node_layer(node.id()); } + inline int get_node_loc_twist(const t_rr_node& node) final{ + return rr_graph_->node_ptc_twist(node.id()); + } inline int get_node_loc_xhigh(const t_rr_node& node) final { return rr_graph_->node_xhigh(node.id()); } @@ -756,6 +759,13 @@ class RrGraphSerializer final : public uxsd::RrGraphBase { } } } + + inline void set_node_loc_twist(int twist, int& inode) final { + auto node = (*rr_nodes_)[inode]; + RRNodeId node_id = node.id(); + rr_graph_builder_->set_node_ptc_twist_incr(node_id,twist); + } + inline uxsd::enum_loc_side get_node_loc_side(const t_rr_node& node) final { const auto& rr_graph = (*rr_graph_); if (rr_graph.node_type(node.id()) == IPIN || rr_graph.node_type(node.id()) == OPIN) { diff --git a/libs/libvtrcapnproto/gen/rr_graph_uxsdcxx.capnp b/libs/libvtrcapnproto/gen/rr_graph_uxsdcxx.capnp index 9c99d068554..bba305feef1 100644 --- a/libs/libvtrcapnproto/gen/rr_graph_uxsdcxx.capnp +++ b/libs/libvtrcapnproto/gen/rr_graph_uxsdcxx.capnp @@ -2,11 +2,11 @@ # https://github.com/duck2/uxsdcxx # Modify only if your build process doesn't involve regenerating this file. # -# Cmdline: uxsdcxx/uxsdcap.py /home/amin/Desktop/vtr-verilog-to-routing/libs/librrgraph/src/io/rr_graph.xsd -# Input file: /home/amin/Desktop/vtr-verilog-to-routing/libs/librrgraph/src/io/rr_graph.xsd -# md5sum of input file: 38649d034e0edccbcb511ddb8915cdff +# Cmdline: uxsdcxx/uxsdcap.py /home/smahmoudi/Desktop/vtr/vtr-verilog-to-routing/libs/librrgraph/src/io/rr_graph.xsd +# Input file: /home/smahmoudi/Desktop/vtr/vtr-verilog-to-routing/libs/librrgraph/src/io/rr_graph.xsd +# md5sum of input file: bf49388f038e0d0e4a12403ebb964b42 -@0xd7cc43f5845f4c7f; +@0xf7009c96d0510b05; using Cxx = import "/capnp/c++.capnp"; $Cxx.namespace("ucap"); @@ -165,10 +165,11 @@ struct NodeLoc { layer @0 :Int32 = 0; ptc @1 :Int32; side @2 :LocSide; - xhigh @3 :Int32; - xlow @4 :Int32; - yhigh @5 :Int32; - ylow @6 :Int32; + twist @3 :Int32; + xhigh @4 :Int32; + xlow @5 :Int32; + yhigh @6 :Int32; + ylow @7 :Int32; } struct NodeTiming { diff --git a/vpr/src/draw/draw.cpp b/vpr/src/draw/draw.cpp index f2e1dcb5876..d4e22cd3c95 100644 --- a/vpr/src/draw/draw.cpp +++ b/vpr/src/draw/draw.cpp @@ -983,10 +983,66 @@ static void draw_router_expansion_costs(ezgl::renderer* g) { } } +/** + * @brief Highlights the block that was clicked on, looking from the top layer downwards for 3D devices (chooses the block on the top visible layer for overlapping blocks) + * It highlights the block green, as well as its fanin and fanout to blue and red respectively by updating the draw_state variables responsible for holding the + * color of the block as well as its fanout and fanin. + * @param x + * @param y + */ static void highlight_blocks(double x, double y) { t_draw_coords* draw_coords = get_draw_coords_vars(); + t_draw_state* draw_state = get_draw_state_vars(); char msg[vtr::bufsize]; + ClusterBlockId clb_index = get_cluster_block_id_from_xy_loc(x, y); + if (clb_index == EMPTY_BLOCK_ID || clb_index == ClusterBlockId::INVALID()) { + return; /* Nothing was found on any layer*/ + } + + auto& cluster_ctx = g_vpr_ctx.clustering(); + auto& place_ctx = g_vpr_ctx.placement(); + + VTR_ASSERT(clb_index != EMPTY_BLOCK_ID); + + ezgl::rectangle clb_bbox = draw_coords->get_absolute_clb_bbox(clb_index, cluster_ctx.clb_nlist.block_type(clb_index)); + // note: this will clear the selected sub-block if show_blk_internal is 0, + // or if it doesn't find anything + ezgl::point2d point_in_clb = ezgl::point2d(x, y) - clb_bbox.bottom_left(); + highlight_sub_block(point_in_clb, clb_index, + cluster_ctx.clb_nlist.block_pb(clb_index)); + + if (get_selected_sub_block_info().has_selection()) { + t_pb* selected_subblock = get_selected_sub_block_info().get_selected_pb(); + sprintf(msg, "sub-block %s (a \"%s\") selected", + selected_subblock->name, + selected_subblock->pb_graph_node->pb_type->name); + } else { + /* Highlight block and fan-in/fan-outs. */ + draw_highlight_blocks_color(cluster_ctx.clb_nlist.block_type(clb_index), + clb_index); + sprintf(msg, "Block #%zu (%s) at (%d, %d) selected.", size_t(clb_index), + cluster_ctx.clb_nlist.block_name(clb_index).c_str(), + place_ctx.block_locs[clb_index].loc.x, + place_ctx.block_locs[clb_index].loc.y); + } + + //If manual moves is activated, then user can select block from the grid. + if (draw_state->manual_moves_state.manual_move_enabled) { + draw_state->manual_moves_state.user_highlighted_block = true; + if (!draw_state->manual_moves_state.manual_move_window_is_open) { + draw_manual_moves_window(std::to_string(size_t(clb_index))); + } + } + + application.update_message(msg); + application.refresh_drawing(); + return; +} + +ClusterBlockId get_cluster_block_id_from_xy_loc(double x, double y) { + t_draw_coords* draw_coords = get_draw_coords_vars(); + t_draw_state* draw_state = get_draw_state_vars(); ClusterBlockId clb_index = EMPTY_BLOCK_ID; auto& device_ctx = g_vpr_ctx.device(); auto& cluster_ctx = g_vpr_ctx.clustering(); @@ -995,8 +1051,11 @@ static void highlight_blocks(double x, double y) { /// determine block /// ezgl::rectangle clb_bbox; - //iterate over grid z (layers) first, so we draw from bottom to top die. This makes partial transparency of layers draw properly. - for (int layer_num = 0; layer_num < device_ctx.grid.get_num_layers(); layer_num++) { + //iterate over grid z (layers) first. Start search of the block at the top layer to prioritize highlighting of blocks at higher levels during overlapping of layers. + for (int layer_num = device_ctx.grid.get_num_layers() - 1; layer_num >= 0; layer_num--) { + if (!draw_state->draw_layer_display[layer_num].visible) { + continue; /* Don't check for blocks on non-visible layers*/ + } // iterate over grid x for (int i = 0; i < (int)device_ctx.grid.width(); ++i) { if (draw_coords->tile_x[i] > x) { @@ -1015,61 +1074,17 @@ static void highlight_blocks(double x, double y) { clb_bbox = draw_coords->get_absolute_clb_bbox(clb_index, cluster_ctx.clb_nlist.block_type(clb_index)); if (clb_bbox.contains({x, y})) { - break; + return clb_index; // we've found the clb } else { clb_index = EMPTY_BLOCK_ID; } } } - if (clb_index != EMPTY_BLOCK_ID) { - break; // we've found something - } - } - if (clb_index != EMPTY_BLOCK_ID) { - break; // we've found something } } - - if (clb_index == EMPTY_BLOCK_ID || clb_index == ClusterBlockId::INVALID()) { - //Nothing found - return; - } - - VTR_ASSERT(clb_index != EMPTY_BLOCK_ID); - - // note: this will clear the selected sub-block if show_blk_internal is 0, - // or if it doesn't find anything - ezgl::point2d point_in_clb = ezgl::point2d(x, y) - clb_bbox.bottom_left(); - highlight_sub_block(point_in_clb, clb_index, - cluster_ctx.clb_nlist.block_pb(clb_index)); - - if (get_selected_sub_block_info().has_selection()) { - t_pb* selected_subblock = get_selected_sub_block_info().get_selected_pb(); - sprintf(msg, "sub-block %s (a \"%s\") selected", - selected_subblock->name, - selected_subblock->pb_graph_node->pb_type->name); - } else { - /* Highlight block and fan-in/fan-outs. */ - draw_highlight_blocks_color(cluster_ctx.clb_nlist.block_type(clb_index), - clb_index); - sprintf(msg, "Block #%zu (%s) at (%d, %d) selected.", size_t(clb_index), - cluster_ctx.clb_nlist.block_name(clb_index).c_str(), - place_ctx.block_locs[clb_index].loc.x, - place_ctx.block_locs[clb_index].loc.y); - } - - //If manual moves is activated, then user can select block from the grid. - t_draw_state* draw_state = get_draw_state_vars(); - if (draw_state->manual_moves_state.manual_move_enabled) { - draw_state->manual_moves_state.user_highlighted_block = true; - if (!draw_state->manual_moves_state.manual_move_window_is_open) { - draw_manual_moves_window(std::to_string(size_t(clb_index))); - } - } - - application.update_message(msg); - application.refresh_drawing(); } + // Searched all layers and found no clb at specified location, returning clb_index = EMPTY_BLOCK_ID. + return clb_index; } static void setup_default_ezgl_callbacks(ezgl::application* app) { @@ -1450,8 +1465,8 @@ t_draw_layer_display get_element_visibility_and_transparency(int src_layer, int element_visibility.visible = true; bool cross_layer_enabled = draw_state->cross_layer_display.visible; - //To only show primitive nets that are connected to currently active layers on the screen - if (!draw_state->draw_layer_display[sink_layer].visible || (!cross_layer_enabled && src_layer != sink_layer)) { + //To only show elements (net flylines,noc links,etc...) that are connected to currently active layers on the screen + if (!draw_state->draw_layer_display[sink_layer].visible || !draw_state->draw_layer_display[src_layer].visible || (!cross_layer_enabled && src_layer != sink_layer)) { element_visibility.visible = false; /* Don't Draw */ } diff --git a/vpr/src/draw/draw.h b/vpr/src/draw/draw.h index 7e799eb8a97..1c39f12f49b 100644 --- a/vpr/src/draw/draw.h +++ b/vpr/src/draw/draw.h @@ -155,6 +155,17 @@ bool rgb_is_same(ezgl::color color1, ezgl::color color2); */ t_draw_layer_display get_element_visibility_and_transparency(int src_layer, int sink_layer); +/** + * @brief takes in the x and y world coordinates of where the user clicked on the screen and returns the corresponding clusterBlockId that represents + * the clb clicked upon by the user on a currently visible FPGA layer. Search for the clb begins from the top layer to ensure it + * returns the clusterBlockId of a clb on a higher layer during instances of overlap between clb blocks. + * @param x + * @param y + * @return returns the ClusterBlockId of the clb at the specified (x,y) location (in world coordinates) as seen by looking downwards from the top of a 3D FPGA. + * Chooses the clb on the top visible layer if there are overlapping blocks. Returns EMPTY_BLOCK_ID (-1) otherwise,if clb is not found on any visible layer. + */ +ClusterBlockId get_cluster_block_id_from_xy_loc(double x, double y); + #endif /* NO_GRAPHICS */ #endif /* DRAW_H */ diff --git a/vpr/src/draw/draw_basic.cpp b/vpr/src/draw/draw_basic.cpp index c1b8715c1c7..e35ebcef0a6 100644 --- a/vpr/src/draw/draw_basic.cpp +++ b/vpr/src/draw/draw_basic.cpp @@ -653,25 +653,31 @@ void draw_partial_route(const std::vector& rr_nodes_to_draw, ezgl::ren auto rr_type = rr_graph.node_type(inode); RRNodeId prev_node = rr_nodes_to_draw[i - 1]; - RRNodeId prev_rr_node = prev_node; auto prev_type = rr_graph.node_type(RRNodeId(prev_node)); auto iedge = find_edge(prev_node, inode); auto switch_type = rr_graph.edge_switch(RRNodeId(prev_node), iedge); + int current_node_layer = rr_graph.node_layer(inode); + int prev_node_layer = rr_graph.node_layer(prev_node); + t_draw_layer_display edge_visibility = get_element_visibility_and_transparency(prev_node_layer, current_node_layer); + //Don't draw node if the layer of the node is not set to visible on screen - if (!draw_state->draw_layer_display[rr_graph.node_layer(inode)].visible) { + if (!draw_state->draw_layer_display[current_node_layer].visible) { continue; } + ezgl::color color = draw_state->draw_rr_node[inode].color; + switch (rr_type) { case OPIN: { - draw_rr_pin(inode, draw_state->draw_rr_node[inode].color, g); + draw_rr_pin(inode, color, g); break; } case IPIN: { - draw_rr_pin(inode, draw_state->draw_rr_node[inode].color, g); - if (is_edge_valid_to_draw(inode, prev_rr_node)) { + draw_rr_pin(inode, color, g); + if (edge_visibility.visible) { + g->set_color(color, edge_visibility.alpha); if (rr_graph.node_type(prev_node) == OPIN) { draw_pin_to_pin(prev_node, inode, g); } else { @@ -684,8 +690,9 @@ void draw_partial_route(const std::vector& rr_nodes_to_draw, ezgl::ren if (draw_state->draw_route_type == GLOBAL) chanx_track[rr_graph.node_xlow(inode)][rr_graph.node_ylow(inode)]++; - draw_rr_chan(inode, draw_state->draw_rr_node[inode].color, g); - if (is_edge_valid_to_draw(inode, prev_rr_node)) { + draw_rr_chan(inode, color, g); + if (edge_visibility.visible) { + g->set_color(color, edge_visibility.alpha); switch (prev_type) { case CHANX: { draw_chanx_to_chanx_edge(prev_node, inode, switch_type, g); @@ -713,9 +720,10 @@ void draw_partial_route(const std::vector& rr_nodes_to_draw, ezgl::ren if (draw_state->draw_route_type == GLOBAL) chany_track[rr_graph.node_xlow(inode)][rr_graph.node_ylow(inode)]++; - draw_rr_chan(inode, draw_state->draw_rr_node[inode].color, g); + draw_rr_chan(inode, color, g); - if (is_edge_valid_to_draw(inode, prev_rr_node)) { + if (edge_visibility.visible) { + g->set_color(color, edge_visibility.alpha); switch (prev_type) { case CHANX: { draw_chanx_to_chany_edge(prev_node, inode, @@ -1049,12 +1057,14 @@ void draw_crit_path(ezgl::renderer* g) { int src_block_layer = get_timing_path_node_layer_num(node); int sink_block_layer = get_timing_path_node_layer_num(prev_node); + t_draw_layer_display flyline_visibility = get_element_visibility_and_transparency(src_block_layer, sink_block_layer); + if (draw_state->show_crit_path == DRAW_CRIT_PATH_FLYLINES || draw_state->show_crit_path == DRAW_CRIT_PATH_FLYLINES_DELAYS) { // FLylines for critical path are drawn based on the layer visibility of the source and sink - if (is_flyline_valid_to_draw(src_block_layer, sink_block_layer)) { - g->set_color(color); + if (flyline_visibility.visible) { + g->set_color(color, flyline_visibility.alpha); g->set_line_dash(ezgl::line_dash::none); g->set_line_width(4); draw_flyline_timing_edge(tnode_draw_coord(prev_node), @@ -1070,10 +1080,10 @@ void draw_crit_path(ezgl::renderer* g) { draw_routed_timing_edge_connection(prev_node, node, color, g); // FLylines for critical path are drawn based on the layer visibility of the source and sink - if (is_flyline_valid_to_draw(src_block_layer, sink_block_layer)) { + if (flyline_visibility.visible) { g->set_line_dash(ezgl::line_dash::asymmetric_5_3); g->set_line_width(3); - g->set_color(color); + g->set_color(color, flyline_visibility.alpha); draw_flyline_timing_edge((ezgl::point2d)tnode_draw_coord(prev_node), (ezgl::point2d)tnode_draw_coord(node), (float)delay, diff --git a/vpr/src/draw/draw_rr.cpp b/vpr/src/draw/draw_rr.cpp index ad58bd40604..fa04c388cfe 100644 --- a/vpr/src/draw/draw_rr.cpp +++ b/vpr/src/draw/draw_rr.cpp @@ -682,7 +682,10 @@ void draw_expand_non_configurable_rr_nodes_recurr(RRNodeId from_node, /* This is a helper function for highlight_rr_nodes(). It determines whether * a routing resource has been clicked on by computing a bounding box for that - * and checking if the mouse click hit inside its bounding box. + * and checking if the mouse click hit inside its bounding box. The function does not check + * routing resources that are on currently invisible layers (layer view is toggled off) to ensure that + * only resources on visible layers are set to be highlighted. There is no priority based on FPGA layer + * for highlighting routing resources (Does not iterate through nodes by order of layer a node is located on). * * It returns the hit RR node's ID (or OPEN if no hit) */ @@ -691,16 +694,20 @@ RRNodeId draw_check_rr_node_hit(float click_x, float click_y) { ezgl::rectangle bound_box; t_draw_coords* draw_coords = get_draw_coords_vars(); + t_draw_state* draw_state = get_draw_state_vars(); auto& device_ctx = g_vpr_ctx.device(); const auto& rr_graph = device_ctx.rr_graph; for (const RRNodeId& inode : device_ctx.rr_graph.nodes()) { + int layer_num = rr_graph.node_layer(inode); + if (!draw_state->draw_layer_display[layer_num].visible) { + continue; /* Don't check RR nodes on currently invisible layers*/ + } switch (rr_graph.node_type(inode)) { case IPIN: case OPIN: { int i = rr_graph.node_xlow(inode); int j = rr_graph.node_ylow(inode); - int layer_num = rr_graph.node_layer(inode); t_physical_tile_type_ptr type = device_ctx.grid.get_physical_type({i, j, layer_num}); int width_offset = device_ctx.grid.get_width_offset({i, j, layer_num}); int height_offset = device_ctx.grid.get_height_offset({i, j, layer_num}); diff --git a/vpr/src/route/rr_graph.cpp b/vpr/src/route/rr_graph.cpp index a046361c926..0b0bb8f90ab 100644 --- a/vpr/src/route/rr_graph.cpp +++ b/vpr/src/route/rr_graph.cpp @@ -1367,6 +1367,26 @@ static void build_rr_graph(const t_graph_type graph_type, } } + /*Update rr_nodes ptc_twist_incr number if we are creating tileable graph*/ + if (graph_type == GRAPH_UNIDIR_TILEABLE) { + device_ctx.rr_graph_builder.resize_ptc_twist_incr(num_rr_nodes); + for (int rr_node_id = 0; rr_node_id < num_rr_nodes; rr_node_id++) { + auto node_type = rr_graph.node_type(RRNodeId(rr_node_id)); + auto node_dir = rr_graph.node_direction(RRNodeId(rr_node_id)); + if (node_type != CHANX && node_type != CHANY) { //SRC/SINK/IPIN/OPIN + device_ctx.rr_graph_builder.set_node_ptc_twist_incr(RRNodeId(rr_node_id), 0); + } else { + //The current ptc twist increment number in UNDIR TILEABLE RRGraph is 2 and -2 + //The assumption should be synced up with openFPGA branch + if (node_dir == Direction::INC) { + device_ctx.rr_graph_builder.set_node_ptc_twist_incr(RRNodeId(rr_node_id), 2); + } else { + device_ctx.rr_graph_builder.set_node_ptc_twist_incr(RRNodeId(rr_node_id), -2); + } + } + } + } + update_chan_width(&nodes_per_chan); /* Allocate and load routing resource switches, which are derived from the switches from the architecture file, @@ -2089,6 +2109,7 @@ static std::function alloc_and_load_rr_graph(RRGraphBuilder num_edges = 0; /* Build channels */ VTR_ASSERT(Fs % 3 == 0); + for (int layer = 0; layer < grid.get_num_layers(); ++layer) { auto& device_ctx = g_vpr_ctx.device(); /* Skip the current die if architecture file specifies that it doesn't require inter-cluster programmable resource routing */ @@ -2214,6 +2235,7 @@ static void alloc_and_load_intra_cluster_rr_graph(RRGraphBuilder& rr_graph_build bool load_rr_graph) { t_rr_edge_info_set rr_edges_to_create; int num_edges = 0; + for (int layer = 0; layer < grid.get_num_layers(); layer++) { for (int i = 0; i < (int)grid.width(); ++i) { for (int j = 0; j < (int)grid.height(); ++j) { diff --git a/vtr_flow/scripts/qor_compare.py b/vtr_flow/scripts/qor_compare.py index 8d4b3464007..f595d97b672 100755 --- a/vtr_flow/scripts/qor_compare.py +++ b/vtr_flow/scripts/qor_compare.py @@ -35,6 +35,7 @@ "geomean_nonvirtual_intradomain_critical_path_delay", # VTR/Titan # Run-time Metrics "odin_synth_time", + "parmys_synth_time", "abc_synth_time", "pack_time", "place_time", diff --git a/vtr_flow/scripts/run_vtr_flow.py b/vtr_flow/scripts/run_vtr_flow.py index 118ab030186..3d584274e3f 100755 --- a/vtr_flow/scripts/run_vtr_flow.py +++ b/vtr_flow/scripts/run_vtr_flow.py @@ -10,6 +10,7 @@ import socket from datetime import datetime from collections import OrderedDict +import os # pylint: disable=wrong-import-position, import-error sys.path.insert(0, str(Path(__file__).resolve().parent / "python_libs")) @@ -186,8 +187,8 @@ def vtr_command_argparser(prog=None): house_keeping.add_argument( "-temp_dir", - default=None, - help="Directory to run the flow in (will be created if non-existent).", + default=os.getcwd() + "/temp", + help="Absolute Directory to run the flow in (will be created if non-existent).", ) house_keeping.add_argument("-name", default=None, help="Name for this run to be output.") @@ -521,10 +522,9 @@ def vtr_command_main(arg_list, prog=None): # Load the arguments args, unknown_args = vtr_command_argparser(prog).parse_known_args(arg_list) error_status = "Error" - if args.temp_dir is None: - temp_dir = Path("./temp") - else: - temp_dir = Path(args.temp_dir) + + assert args.temp_dir + temp_dir = Path(args.temp_dir) # Specify how command should be run command_runner = vtr.CommandRunner( track_memory=args.track_memory_usage, diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/figure_8/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/figure_8/config/golden_results.txt index 409b54bfb50..8b656e52590 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/figure_8/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/figure_8/config/golden_results.txt @@ -1,221 +1,221 @@ -arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops crit_path_total_internal_heap_pushes crit_path_total_internal_heap_pops crit_path_total_external_heap_pushes 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0.000716111 0.000564 30 347 10 6.55708e+06 36165 526063. 1820.29 1.08 0.0092215 0.00747239 21886 126133 -1 334 6 74 86 5926 1401 0 0 5926 1401 86 83 0 0 311 244 0 0 403 338 0 0 86 86 0 0 2737 327 0 0 2303 323 0 0 86 0 0 12 12 0 134 0 0 1.50711 1.50711 -19.3364 -1.50711 0 0 666494. 2306.21 0.19 0.00 0.07 -1 -1 0.19 0.000858386 0.000776219 19 9 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_007bits.v common 3.22 vpr 51.39 MiB -1 -1 0.08 16308 3 0.03 -1 -1 31264 -1 -1 3 15 0 0 success v8.0.0-7663-gb6a96700f release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-24T17:35:35 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_final/vtr-verilog-to-routing/vtr_flow/tasks 52628 15 8 47 55 1 38 26 17 17 289 -1 unnamed_device 12.8 MiB 0.01 108 51.4 MiB 0.00 0.00 1.05785 -14.4718 -1.05785 1.05785 0.59 2.2402e-05 1.6068e-05 0.00063625 0.000506325 24 340 9 6.55708e+06 36165 448715. 1552.65 1.03 0.00560887 0.00458319 20734 103517 -1 311 13 156 183 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VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-24T17:35:35 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_final/vtr-verilog-to-routing/vtr_flow/tasks 52672 25 13 83 96 1 66 44 17 17 289 -1 unnamed_device 12.9 MiB 0.02 322 51.4 MiB 0.01 0.00 1.53464 -31.8396 -1.53464 1.53464 0.59 3.8155e-05 2.8906e-05 0.00219144 0.00174302 26 789 15 6.55708e+06 72330 477104. 1650.88 0.46 0.00921264 0.00767276 21022 109990 -1 722 18 329 478 34105 8356 0 0 34105 8356 478 376 0 0 1796 1503 0 0 3034 2334 0 0 478 384 0 0 13956 1951 0 0 14363 1808 0 0 478 0 0 149 146 169 1296 0 0 1.94871 1.94871 -41.905 -1.94871 0 0 585099. 2024.56 0.26 0.02 0.10 -1 -1 0.26 0.00430535 0.00376831 40 21 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_013bits.v common 3.01 vpr 51.50 MiB -1 -1 0.07 16500 5 0.04 -1 -1 31136 -1 -1 7 27 0 0 success v8.0.0-7663-gb6a96700f release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-24T17:35:35 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_final/vtr-verilog-to-routing/vtr_flow/tasks 52736 27 14 91 105 1 70 48 17 17 289 -1 unnamed_device 12.9 MiB 0.02 247 51.5 MiB 0.01 0.00 1.49544 -30.0023 -1.49544 1.49544 0.68 4.7422e-05 3.6657e-05 0.00257237 0.0020522 26 783 19 6.55708e+06 84385 477104. 1650.88 0.54 0.0114883 0.00955196 21022 109990 -1 590 13 298 432 21773 7067 0 0 21773 7067 432 346 0 0 1629 1328 0 0 2498 1976 0 0 432 356 0 0 7727 1657 0 0 9055 1404 0 0 432 0 0 134 159 97 1212 0 0 1.62931 1.62931 -37.8693 -1.62931 0 0 585099. 2024.56 0.17 0.01 0.06 -1 -1 0.17 0.00260046 0.00233049 42 24 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_014bits.v common 4.12 vpr 51.64 MiB -1 -1 0.10 16588 6 0.06 -1 -1 31264 -1 -1 7 29 0 0 success v8.0.0-7663-gb6a96700f release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-24T17:35:35 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_final/vtr-verilog-to-routing/vtr_flow/tasks 52884 29 15 95 110 1 74 51 17 17 289 -1 unnamed_device 13.0 MiB 0.04 434 51.6 MiB 0.01 0.00 2.15556 -41.7282 -2.15556 2.15556 0.60 5.2368e-05 4.1623e-05 0.00158307 0.00131226 30 867 10 6.55708e+06 84385 526063. 1820.29 1.78 0.0147871 0.0124608 21886 126133 -1 776 10 218 310 19113 4690 0 0 19113 4690 310 242 0 0 1118 908 0 0 1462 1207 0 0 310 253 0 0 8237 1019 0 0 7676 1061 0 0 310 0 0 92 54 90 794 0 0 2.15556 2.15556 -48.5012 -2.15556 0 0 666494. 2306.21 0.19 0.01 0.06 -1 -1 0.19 0.00229314 0.00207873 45 23 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_015bits.v common 4.51 vpr 51.67 MiB -1 -1 0.10 16576 6 0.04 -1 -1 31084 -1 -1 10 31 0 0 success v8.0.0-7663-gb6a96700f release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-24T17:35:35 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_final/vtr-verilog-to-routing/vtr_flow/tasks 52912 31 16 104 120 1 81 57 17 17 289 -1 unnamed_device 13.2 MiB 0.04 457 51.7 MiB 0.03 0.00 1.73384 -42.1415 -1.73384 1.73384 1.01 9.3e-05 7.3288e-05 0.00550591 0.00447827 26 1079 15 6.55708e+06 120550 477104. 1650.88 1.55 0.0246976 0.0206429 21022 109990 -1 917 12 298 446 29635 7301 0 0 29635 7301 446 344 0 0 1715 1326 0 0 2503 1994 0 0 446 348 0 0 12317 1657 0 0 12208 1632 0 0 446 0 0 148 144 159 1351 0 0 1.85404 1.85404 -49.7161 -1.85404 0 0 585099. 2024.56 0.16 0.01 0.08 -1 -1 0.16 0.00287334 0.00259517 50 27 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_016bits.v common 3.30 vpr 51.78 MiB -1 -1 0.07 16604 7 0.05 -1 -1 31376 -1 -1 7 33 0 0 success v8.0.0-7663-gb6a96700f release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-24T17:35:35 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_final/vtr-verilog-to-routing/vtr_flow/tasks 53024 33 17 112 129 1 86 57 17 17 289 -1 unnamed_device 13.3 MiB 0.05 407 51.8 MiB 0.03 0.00 2.2223 -46.1898 -2.2223 2.2223 0.96 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v8.0.0-7663-gb6a96700f release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-24T17:35:35 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_final/vtr-verilog-to-routing/vtr_flow/tasks 54660 97 49 340 389 1 266 170 17 17 289 -1 unnamed_device 14.6 MiB 0.26 1615 53.4 MiB 0.09 0.00 6.37519 -251.831 -6.37519 6.37519 0.62 0.000378717 0.00031665 0.0163962 0.0139542 30 3196 18 6.55708e+06 289320 526063. 1820.29 2.31 0.0944594 0.0833689 21886 126133 -1 2841 10 820 1140 69688 16617 0 0 69688 16617 1140 879 0 0 3950 3056 0 0 5323 4269 0 0 1140 920 0 0 29536 3795 0 0 28599 3698 0 0 1140 0 0 320 237 298 2743 0 0 6.85599 6.85599 -281.28 -6.85599 0 0 666494. 2306.21 0.18 0.02 0.06 -1 -1 0.18 0.00839726 0.00779976 161 98 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_064bits.v common 3.99 vpr 53.93 MiB -1 -1 0.15 17380 26 0.10 -1 -1 31836 -1 -1 35 129 0 0 success v8.0.0-7663-gb6a96700f release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-24T17:35:35 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_final/vtr-verilog-to-routing/vtr_flow/tasks 55224 129 65 453 518 1 353 229 17 17 289 -1 unnamed_device 15.0 MiB 0.23 2142 53.9 MiB 0.12 0.00 8.91496 -417.948 -8.91496 8.91496 0.75 0.000481669 0.000407888 0.0244448 0.0212925 32 4416 22 6.55708e+06 421925 554710. 1919.41 0.69 0.0777397 0.0695121 22174 131602 -1 4003 60 1496 2154 573874 302738 0 0 573874 302738 2154 1711 0 0 8651 7109 0 0 22395 15070 0 0 2154 1768 0 0 274216 142066 0 0 264304 135014 0 0 2154 0 0 658 761 739 5854 0 0 9.03516 9.03516 -457.134 -9.03516 0 0 701300. 2426.64 0.19 0.16 0.07 -1 -1 0.19 0.0411339 0.0372742 213 131 -1 -1 -1 -1 -fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_003bits.v common 0.40 abc 28.64 MiB -1 -1 0.06 16248 1 0.01 -1 -1 29328 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-7663-gb6a96700f release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-24T17:35:35 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_final/vtr-verilog-to-routing/vtr_flow/tasks 13312 7 4 24 25 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_004bits.v common 0.44 abc 28.76 MiB -1 -1 0.09 16480 1 0.01 -1 -1 29452 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-7663-gb6a96700f release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-24T17:35:35 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_final/vtr-verilog-to-routing/vtr_flow/tasks 13384 9 5 30 31 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 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-1 0.10 16376 1 0.00 -1 -1 29464 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-7663-gb6a96700f release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-24T17:35:35 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_final/vtr-verilog-to-routing/vtr_flow/tasks 13304 13 7 42 43 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_007bits.v common 0.45 abc 28.82 MiB -1 -1 0.09 16412 1 0.01 -1 -1 29508 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-7663-gb6a96700f release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-24T17:35:35 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_final/vtr-verilog-to-routing/vtr_flow/tasks 13276 15 8 49 50 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_008bits.v common 0.47 abc 28.88 MiB -1 -1 0.09 16472 1 0.01 -1 -1 29568 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-7663-gb6a96700f release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-24T17:35:35 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_final/vtr-verilog-to-routing/vtr_flow/tasks 13348 17 9 55 56 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 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exited with return code 134 v8.0.0-7663-gb6a96700f release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-24T17:35:35 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_final/vtr-verilog-to-routing/vtr_flow/tasks 13312 21 11 67 68 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_011bits.v common 0.63 abc 28.75 MiB -1 -1 0.10 16756 1 0.01 -1 -1 29440 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-7663-gb6a96700f release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-24T17:35:35 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_final/vtr-verilog-to-routing/vtr_flow/tasks 13404 23 12 74 75 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_012bits.v common 0.50 abc 28.76 MiB -1 -1 0.10 16604 1 0.00 -1 -1 29448 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-7663-gb6a96700f release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-24T17:35:35 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_final/vtr-verilog-to-routing/vtr_flow/tasks 13328 25 13 80 81 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_013bits.v common 0.49 abc 28.88 MiB -1 -1 0.10 16604 1 0.00 -1 -1 29568 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-7663-gb6a96700f release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-24T17:35:35 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_final/vtr-verilog-to-routing/vtr_flow/tasks 13388 27 14 86 87 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_014bits.v common 0.54 abc 28.80 MiB -1 -1 0.10 16760 1 0.02 -1 -1 29496 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-7663-gb6a96700f release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-24T17:35:35 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_final/vtr-verilog-to-routing/vtr_flow/tasks 13408 29 15 92 93 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_015bits.v common 0.41 abc 28.76 MiB -1 -1 0.09 16628 1 0.01 -1 -1 29448 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-7663-gb6a96700f release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-24T17:35:35 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_final/vtr-verilog-to-routing/vtr_flow/tasks 13468 31 16 99 100 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_016bits.v common 0.45 abc 28.70 MiB -1 -1 0.11 16748 1 0.01 -1 -1 29388 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-7663-gb6a96700f release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-24T17:35:35 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_final/vtr-verilog-to-routing/vtr_flow/tasks 13484 33 17 105 106 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_018bits.v common 0.42 abc 28.74 MiB -1 -1 0.09 16652 1 0.01 -1 -1 29432 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-7663-gb6a96700f release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-24T17:35:35 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_final/vtr-verilog-to-routing/vtr_flow/tasks 13612 37 19 117 118 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_020bits.v common 0.42 abc 28.76 MiB -1 -1 0.11 16588 1 0.01 -1 -1 29448 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-7663-gb6a96700f release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-24T17:35:35 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_final/vtr-verilog-to-routing/vtr_flow/tasks 13512 41 21 130 131 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_022bits.v common 0.40 abc 28.76 MiB -1 -1 0.08 16556 1 0.01 -1 -1 29448 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-7663-gb6a96700f release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-24T17:35:35 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_final/vtr-verilog-to-routing/vtr_flow/tasks 13636 45 23 142 143 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 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abc 28.83 MiB -1 -1 0.11 16588 1 0.01 -1 -1 29520 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-7663-gb6a96700f release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-24T17:35:35 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_final/vtr-verilog-to-routing/vtr_flow/tasks 13764 57 29 180 181 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_032bits.v common 0.49 abc 28.91 MiB -1 -1 0.12 16800 1 0.01 -1 -1 29608 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-7663-gb6a96700f release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-24T17:35:35 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_final/vtr-verilog-to-routing/vtr_flow/tasks 13780 65 33 205 206 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_048bits.v common 0.48 abc 28.98 MiB -1 -1 0.12 17004 1 0.01 -1 -1 29680 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-7663-gb6a96700f release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-24T17:35:35 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_final/vtr-verilog-to-routing/vtr_flow/tasks 14060 97 49 305 306 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 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-1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-7663-gb6a96700f release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-24T17:35:35 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_final/vtr-verilog-to-routing/vtr_flow/tasks 13044 7 4 24 25 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_004bits.v common 0.42 abc 28.80 MiB -1 -1 0.10 16308 1 0.01 -1 -1 29496 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-7663-gb6a96700f release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-24T17:35:35 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_final/vtr-verilog-to-routing/vtr_flow/tasks 13088 9 5 30 31 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_005bits.v common 0.40 abc 28.66 MiB -1 -1 0.10 16488 1 0.00 -1 -1 29352 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-7663-gb6a96700f release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-24T17:35:35 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_final/vtr-verilog-to-routing/vtr_flow/tasks 13200 11 6 36 37 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 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-1 -1 29336 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-7663-gb6a96700f release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-24T17:35:35 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_final/vtr-verilog-to-routing/vtr_flow/tasks 13132 15 8 49 50 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_008bits.v common 0.39 abc 28.85 MiB -1 -1 0.08 16224 1 0.00 -1 -1 29544 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-7663-gb6a96700f release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-24T17:35:35 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_final/vtr-verilog-to-routing/vtr_flow/tasks 13148 17 9 55 56 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_009bits.v common 0.43 abc 28.83 MiB -1 -1 0.09 16436 1 0.00 -1 -1 29520 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-7663-gb6a96700f release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-24T17:35:35 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_final/vtr-verilog-to-routing/vtr_flow/tasks 13056 19 10 61 62 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 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0.01 -1 -1 29496 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-7663-gb6a96700f release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-24T17:35:35 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_final/vtr-verilog-to-routing/vtr_flow/tasks 13236 23 12 74 75 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_012bits.v common 0.42 abc 28.84 MiB -1 -1 0.10 16648 1 0.01 -1 -1 29532 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-7663-gb6a96700f release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-24T17:35:35 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_final/vtr-verilog-to-routing/vtr_flow/tasks 13216 25 13 80 81 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_013bits.v common 0.39 abc 28.82 MiB -1 -1 0.07 16656 1 0.01 -1 -1 29508 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-7663-gb6a96700f release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-24T17:35:35 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_final/vtr-verilog-to-routing/vtr_flow/tasks 13348 27 14 86 87 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 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0.01 -1 -1 29336 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-7663-gb6a96700f release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-24T17:35:35 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_final/vtr-verilog-to-routing/vtr_flow/tasks 13344 31 16 99 100 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_016bits.v common 0.40 abc 28.73 MiB -1 -1 0.07 16764 1 0.00 -1 -1 29420 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-7663-gb6a96700f release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-24T17:35:35 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_final/vtr-verilog-to-routing/vtr_flow/tasks 13336 33 17 105 106 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_018bits.v common 0.41 abc 28.94 MiB -1 -1 0.10 16740 1 0.01 -1 -1 29632 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-7663-gb6a96700f release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-24T17:35:35 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_final/vtr-verilog-to-routing/vtr_flow/tasks 13256 37 19 117 118 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_020bits.v common 0.35 abc 28.92 MiB -1 -1 0.06 16576 1 0.01 -1 -1 29616 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-7663-gb6a96700f release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-24T17:35:35 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_final/vtr-verilog-to-routing/vtr_flow/tasks 13220 41 21 130 131 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_022bits.v common 0.40 abc 28.77 MiB -1 -1 0.08 16588 1 0.02 -1 -1 29464 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-7663-gb6a96700f release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-24T17:35:35 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_final/vtr-verilog-to-routing/vtr_flow/tasks 13396 45 23 142 143 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_024bits.v common 0.37 abc 28.88 MiB -1 -1 0.07 16660 1 0.02 -1 -1 29568 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-7663-gb6a96700f release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-24T17:35:35 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_final/vtr-verilog-to-routing/vtr_flow/tasks 13372 49 25 155 156 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_028bits.v common 0.42 abc 28.81 MiB -1 -1 0.12 16764 1 0.01 -1 -1 29504 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-7663-gb6a96700f release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-24T17:35:35 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_final/vtr-verilog-to-routing/vtr_flow/tasks 13676 57 29 180 181 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_032bits.v common 0.44 abc 28.89 MiB -1 -1 0.11 16800 1 0.01 -1 -1 29588 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-7663-gb6a96700f release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-24T17:35:35 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_final/vtr-verilog-to-routing/vtr_flow/tasks 13672 65 33 205 206 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_048bits.v common 0.47 abc 28.99 MiB -1 -1 0.11 17000 1 0.02 -1 -1 29684 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-7663-gb6a96700f release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-24T17:35:35 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_final/vtr-verilog-to-routing/vtr_flow/tasks 13784 97 49 305 306 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_064bits.v common 0.40 abc 29.20 MiB -1 -1 0.13 17116 1 0.02 -1 -1 29904 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-7663-gb6a96700f release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-24T17:35:35 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_final/vtr-verilog-to-routing/vtr_flow/tasks 14076 129 65 405 406 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_003bits.v common 3.43 vpr 51.61 MiB -1 -1 0.10 16324 1 0.01 -1 -1 29464 -1 -1 2 7 0 0 success v8.0.0-7663-gb6a96700f release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-24T17:35:35 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_final/vtr-verilog-to-routing/vtr_flow/tasks 52848 7 4 27 28 1 14 13 17 17 289 -1 unnamed_device 13.1 MiB 0.01 34 51.6 MiB 0.00 0.00 0.649848 -5.97153 -0.649848 0.649848 0.73 1.9406e-05 1.3367e-05 0.000443455 0.000345241 18 97 8 6.64007e+06 25116 355633. 1230.56 1.21 0.00634506 0.00503227 20242 81429 -1 62 5 24 24 771 282 0 0 771 282 24 24 0 0 82 44 0 0 110 83 0 0 24 24 0 0 206 68 0 0 325 39 0 0 24 0 0 0 0 0 24 0 0 0.71851 0.71851 -6.45233 -0.71851 0 0 448715. 1552.65 0.16 0.00 0.04 -1 -1 0.16 0.000565158 0.000489226 10 -1 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_004bits.v common 4.03 vpr 51.49 MiB -1 -1 0.07 16476 1 0.01 -1 -1 29400 -1 -1 2 9 0 0 success v8.0.0-7663-gb6a96700f release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-24T17:35:35 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_final/vtr-verilog-to-routing/vtr_flow/tasks 52728 9 5 34 35 1 20 16 17 17 289 -1 unnamed_device 13.0 MiB 0.01 100 51.5 MiB 0.00 0.00 0.671848 -9.12622 -0.671848 0.671848 0.99 2.4309e-05 1.7397e-05 0.000529278 0.000425464 14 203 9 6.64007e+06 25116 279208. 966.117 1.37 0.0046741 0.00377536 19378 63921 -1 194 10 85 85 4940 1319 0 0 4940 1319 85 85 0 0 315 241 0 0 416 350 0 0 85 85 0 0 1990 311 0 0 2049 247 0 0 85 0 0 0 0 0 85 0 0 0.912248 0.912248 -11.7706 -0.912248 0 0 355633. 1230.56 0.12 0.01 0.04 -1 -1 0.12 0.00138051 0.00120442 13 -1 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_005bits.v common 3.93 vpr 51.62 MiB -1 -1 0.07 16344 1 0.01 -1 -1 29416 -1 -1 2 11 0 0 success v8.0.0-7663-gb6a96700f release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-24T17:35:35 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_final/vtr-verilog-to-routing/vtr_flow/tasks 52860 11 6 41 42 1 26 19 17 17 289 -1 unnamed_device 13.0 MiB 0.01 57 51.6 MiB 0.01 0.00 0.682848 -9.10125 -0.682848 0.682848 0.85 2.9971e-05 2.2215e-05 0.00108702 0.000841119 26 200 22 6.64007e+06 25116 477104. 1650.88 1.53 0.012159 0.00961778 21682 110474 -1 174 26 245 245 13494 4563 0 0 13494 4563 245 245 0 0 992 850 0 0 1624 1277 0 0 245 245 0 0 4679 1023 0 0 5709 923 0 0 245 0 0 0 0 0 245 0 0 1.03245 1.03245 -12.551 -1.03245 0 0 585099. 2024.56 0.25 0.01 0.10 -1 -1 0.25 0.0024198 0.00200859 16 -1 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_006bits.v common 4.18 vpr 51.71 MiB -1 -1 0.09 16316 1 0.01 -1 -1 29412 -1 -1 4 13 0 0 success v8.0.0-7663-gb6a96700f release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-24T17:35:35 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_final/vtr-verilog-to-routing/vtr_flow/tasks 52948 13 7 48 49 1 32 24 17 17 289 -1 unnamed_device 13.1 MiB 0.01 85 51.7 MiB 0.01 0.00 0.704848 -11.2793 -0.704848 0.704848 0.99 3.4563e-05 2.5696e-05 0.0016475 0.00126273 26 245 18 6.64007e+06 50232 477104. 1650.88 1.36 0.0129122 0.0102843 21682 110474 -1 244 15 196 196 10705 3403 0 0 10705 3403 196 196 0 0 739 594 0 0 1100 845 0 0 196 196 0 0 3762 839 0 0 4712 733 0 0 196 0 0 0 0 0 196 0 0 1.03245 1.03245 -15.5887 -1.03245 0 0 585099. 2024.56 0.18 0.01 0.09 -1 -1 0.18 0.00133794 0.00114169 20 -1 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_007bits.v common 5.25 vpr 51.72 MiB -1 -1 0.08 16312 1 0.01 -1 -1 29396 -1 -1 3 15 0 0 success v8.0.0-7663-gb6a96700f release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-24T17:35:35 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_final/vtr-verilog-to-routing/vtr_flow/tasks 52960 15 8 55 56 1 38 26 17 17 289 -1 unnamed_device 13.1 MiB 0.02 112 51.7 MiB 0.01 0.00 0.944958 -13.8003 -0.944958 0.944958 0.97 3.7581e-05 2.8339e-05 0.00199616 0.00156684 30 262 12 6.64007e+06 37674 526063. 1820.29 2.32 0.0162609 0.0131904 22546 126617 -1 220 14 137 137 7084 2138 0 0 7084 2138 137 137 0 0 504 409 0 0 635 530 0 0 137 137 0 0 2944 445 0 0 2727 480 0 0 137 0 0 0 0 0 137 0 0 0.921248 0.921248 -16.862 -0.921248 0 0 666494. 2306.21 0.30 0.01 0.11 -1 -1 0.30 0.00218017 0.00188913 22 -1 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_008bits.v common 4.88 vpr 51.67 MiB -1 -1 0.09 16352 1 0.01 -1 -1 29496 -1 -1 4 17 0 0 success v8.0.0-7663-gb6a96700f release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-24T17:35:35 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_final/vtr-verilog-to-routing/vtr_flow/tasks 52908 17 9 62 63 1 41 30 17 17 289 -1 unnamed_device 13.0 MiB 0.02 119 51.7 MiB 0.01 0.00 0.955958 -15.611 -0.955958 0.955958 0.97 4.4266e-05 3.3272e-05 0.00250205 0.00195171 32 299 13 6.64007e+06 50232 554710. 1919.41 2.14 0.0178376 0.0143864 22834 132086 -1 247 14 182 182 9380 2772 0 0 9380 2772 182 182 0 0 653 542 0 0 995 789 0 0 182 182 0 0 3790 502 0 0 3578 575 0 0 182 0 0 0 0 0 182 0 0 0.965248 0.965248 -19.2538 -0.965248 0 0 701300. 2426.64 0.20 0.01 0.07 -1 -1 0.20 0.00152927 0.0013337 25 -1 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_009bits.v common 3.59 vpr 51.66 MiB -1 -1 0.09 16680 1 0.01 -1 -1 29572 -1 -1 4 19 0 0 success v8.0.0-7663-gb6a96700f release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-24T17:35:35 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_final/vtr-verilog-to-routing/vtr_flow/tasks 52900 19 10 69 70 1 44 33 17 17 289 -1 unnamed_device 13.2 MiB 0.03 130 51.7 MiB 0.02 0.00 0.966958 -17.6732 -0.966958 0.966958 1.00 4.9615e-05 3.7648e-05 0.00276879 0.00217001 26 359 11 6.64007e+06 50232 477104. 1650.88 0.71 0.010417 0.00853087 21682 110474 -1 325 14 185 185 10874 3133 0 0 10874 3133 185 185 0 0 733 587 0 0 1024 853 0 0 185 185 0 0 4230 677 0 0 4517 646 0 0 185 0 0 0 0 0 185 0 0 0.965248 0.965248 -22.5784 -0.965248 0 0 585099. 2024.56 0.24 0.01 0.07 -1 -1 0.24 0.00268672 0.00234275 28 -1 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_010bits.v common 5.29 vpr 51.82 MiB -1 -1 0.07 16624 1 0.00 -1 -1 29420 -1 -1 5 21 0 0 success v8.0.0-7663-gb6a96700f release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-24T17:35:35 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_final/vtr-verilog-to-routing/vtr_flow/tasks 53060 21 11 76 77 1 49 37 17 17 289 -1 unnamed_device 13.3 MiB 0.03 230 51.8 MiB 0.01 0.00 0.977958 -21.7897 -0.977958 0.977958 1.00 5.8501e-05 4.5747e-05 0.00172842 0.00140564 32 474 13 6.64007e+06 62790 554710. 1919.41 2.38 0.021818 0.0179631 22834 132086 -1 437 13 188 188 13181 3469 0 0 13181 3469 188 188 0 0 749 626 0 0 1051 846 0 0 188 188 0 0 5279 869 0 0 5726 752 0 0 188 0 0 0 0 0 188 0 0 0.976248 0.976248 -27.7891 -0.976248 0 0 701300. 2426.64 0.27 0.01 0.12 -1 -1 0.27 0.00182026 0.00160724 31 -1 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_011bits.v common 4.26 vpr 51.86 MiB -1 -1 0.08 16764 1 0.01 -1 -1 29536 -1 -1 5 23 0 0 success v8.0.0-7663-gb6a96700f release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-24T17:35:35 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_final/vtr-verilog-to-routing/vtr_flow/tasks 53108 23 12 83 84 1 55 40 17 17 289 -1 unnamed_device 13.4 MiB 0.02 180 51.9 MiB 0.02 0.00 0.988958 -22.9122 -0.988958 0.988958 1.01 5.9794e-05 4.5425e-05 0.0032612 0.00260475 28 511 23 6.64007e+06 62790 500653. 1732.36 1.68 0.0243614 0.0200658 21970 115934 -1 387 16 273 273 16423 4672 0 0 16423 4672 273 273 0 0 1030 828 0 0 1495 1224 0 0 273 273 0 0 5912 1132 0 0 7440 942 0 0 273 0 0 0 0 0 273 0 0 0.987248 0.987248 -27.7079 -0.987248 0 0 612192. 2118.31 0.20 0.02 0.08 -1 -1 0.20 0.00343916 0.00297146 34 -1 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_012bits.v common 5.17 vpr 51.77 MiB -1 -1 0.10 16628 1 0.02 -1 -1 29460 -1 -1 5 25 0 0 success v8.0.0-7663-gb6a96700f release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-24T17:35:35 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_final/vtr-verilog-to-routing/vtr_flow/tasks 53008 25 13 90 91 1 61 43 17 17 289 -1 unnamed_device 13.2 MiB 0.03 207 51.8 MiB 0.02 0.00 0.999958 -24.4064 -0.999958 0.999958 1.00 6.7938e-05 5.2413e-05 0.00326926 0.00260521 32 547 23 6.64007e+06 62790 554710. 1919.41 2.19 0.0278171 0.0228467 22834 132086 -1 449 26 414 414 24702 7019 0 0 24702 7019 414 414 0 0 1516 1177 0 0 2424 1818 0 0 414 414 0 0 9362 1676 0 0 10572 1520 0 0 414 0 0 0 0 0 414 0 0 1.15265 1.15265 -31.2581 -1.15265 0 0 701300. 2426.64 0.29 0.02 0.07 -1 -1 0.29 0.00485491 0.00415395 37 -1 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_013bits.v common 3.78 vpr 51.86 MiB -1 -1 0.11 16588 1 0.01 -1 -1 29456 -1 -1 6 27 0 0 success v8.0.0-7663-gb6a96700f release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-24T17:35:35 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_final/vtr-verilog-to-routing/vtr_flow/tasks 53100 27 14 97 98 1 67 47 17 17 289 -1 unnamed_device 13.3 MiB 0.03 203 51.9 MiB 0.03 0.00 1.01096 -26.1519 -1.01096 1.01096 1.03 6.9709e-05 5.384e-05 0.00437797 0.00351053 28 659 23 6.64007e+06 75348 500653. 1732.36 0.81 0.01703 0.0141187 21970 115934 -1 553 26 525 525 39081 10795 0 0 39081 10795 525 525 0 0 1970 1626 0 0 2867 2351 0 0 525 525 0 0 15600 2927 0 0 17594 2841 0 0 525 0 0 0 0 0 525 0 0 1.17465 1.17465 -34.9025 -1.17465 0 0 612192. 2118.31 0.23 0.02 0.08 -1 -1 0.23 0.00370361 0.0031885 40 -1 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_014bits.v common 4.66 vpr 51.93 MiB -1 -1 0.10 16624 1 0.01 -1 -1 29396 -1 -1 7 29 0 0 success v8.0.0-7663-gb6a96700f release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-24T17:35:35 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_final/vtr-verilog-to-routing/vtr_flow/tasks 53176 29 15 104 105 1 73 51 17 17 289 -1 unnamed_device 13.3 MiB 0.02 264 51.9 MiB 0.01 0.00 1.02196 -29.1104 -1.02196 1.02196 0.83 3.9738e-05 2.9832e-05 0.0023155 0.00181773 32 689 16 6.64007e+06 87906 554710. 1919.41 1.83 0.0203992 0.0168772 22834 132086 -1 561 13 329 329 20243 5424 0 0 20243 5424 329 329 0 0 1243 1010 0 0 1931 1451 0 0 329 329 0 0 7455 1322 0 0 8956 983 0 0 329 0 0 0 0 0 329 0 0 1.10745 1.10745 -36.3626 -1.10745 0 0 701300. 2426.64 0.29 0.01 0.13 -1 -1 0.29 0.0028819 0.00256945 44 -1 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_015bits.v common 5.23 vpr 51.83 MiB -1 -1 0.09 16592 1 0.01 -1 -1 29480 -1 -1 7 31 0 0 success v8.0.0-7663-gb6a96700f release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-24T17:35:35 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_final/vtr-verilog-to-routing/vtr_flow/tasks 53072 31 16 111 112 1 79 54 17 17 289 -1 unnamed_device 13.2 MiB 0.02 289 51.8 MiB 0.03 0.00 1.26207 -31.2273 -1.26207 1.26207 0.99 7.9629e-05 6.2182e-05 0.00463084 0.00367323 32 651 14 6.64007e+06 87906 554710. 1919.41 2.25 0.0332905 0.0276876 22834 132086 -1 556 8 255 255 14489 4029 0 0 14489 4029 255 255 0 0 914 759 0 0 1455 1096 0 0 255 255 0 0 5683 873 0 0 5927 791 0 0 255 0 0 0 0 0 255 0 0 1.04025 1.04025 -37.1254 -1.04025 0 0 701300. 2426.64 0.29 0.01 0.11 -1 -1 0.29 0.00333327 0.00301709 46 -1 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_016bits.v common 5.35 vpr 51.99 MiB -1 -1 0.10 16576 1 0.01 -1 -1 29460 -1 -1 7 33 0 0 success v8.0.0-7663-gb6a96700f release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-24T17:35:35 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_final/vtr-verilog-to-routing/vtr_flow/tasks 53240 33 17 118 119 1 82 57 17 17 289 -1 unnamed_device 13.6 MiB 0.03 303 52.0 MiB 0.03 0.00 1.27307 -33.9561 -1.27307 1.27307 0.84 8.0016e-05 6.2554e-05 0.00568394 0.00455597 36 637 14 6.64007e+06 87906 612192. 2118.31 2.68 0.0331724 0.0276307 23410 145293 -1 576 14 323 323 20245 5336 0 0 20245 5336 323 323 0 0 1180 936 0 0 1606 1290 0 0 323 323 0 0 8545 1271 0 0 8268 1193 0 0 323 0 0 0 0 0 323 0 0 1.23865 1.23865 -40.8042 -1.23865 0 0 782063. 2706.10 0.33 0.02 0.13 -1 -1 0.33 0.00429908 0.00382202 49 -1 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_018bits.v common 4.79 vpr 52.23 MiB -1 -1 0.08 16764 1 0.01 -1 -1 29508 -1 -1 8 37 0 0 success v8.0.0-7663-gb6a96700f release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-24T17:35:35 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_final/vtr-verilog-to-routing/vtr_flow/tasks 53484 37 19 132 133 1 90 64 17 17 289 -1 unnamed_device 13.7 MiB 0.04 340 52.2 MiB 0.02 0.00 1.29507 -38.7256 -1.29507 1.29507 0.80 5.3128e-05 4.0376e-05 0.0031003 0.00245843 30 888 16 6.64007e+06 100464 526063. 1820.29 2.01 0.028652 0.0238487 22546 126617 -1 703 12 345 345 21697 5911 0 0 21697 5911 345 345 0 0 1234 990 0 0 1553 1300 0 0 345 345 0 0 8410 1626 0 0 9810 1305 0 0 345 0 0 0 0 0 345 0 0 1.08425 1.08425 -46.8799 -1.08425 0 0 666494. 2306.21 0.23 0.01 0.10 -1 -1 0.23 0.00331003 0.00299795 55 -1 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_020bits.v common 4.90 vpr 52.19 MiB -1 -1 0.10 16580 1 0.00 -1 -1 29520 -1 -1 8 41 0 0 success v8.0.0-7663-gb6a96700f release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-24T17:35:35 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_final/vtr-verilog-to-routing/vtr_flow/tasks 53440 41 21 146 147 1 102 70 17 17 289 -1 unnamed_device 13.6 MiB 0.04 384 52.2 MiB 0.04 0.00 1.31707 -43.6593 -1.31707 1.31707 0.87 0.000110548 8.795e-05 0.00706216 0.0057593 32 992 37 6.64007e+06 100464 554710. 1919.41 2.22 0.0355902 0.0298617 22834 132086 -1 801 15 484 484 35417 9604 0 0 35417 9604 484 484 0 0 1902 1622 0 0 2686 2119 0 0 484 484 0 0 14319 2557 0 0 15542 2338 0 0 484 0 0 0 0 0 484 0 0 1.24845 1.24845 -55.372 -1.24845 0 0 701300. 2426.64 0.26 0.02 0.08 -1 -1 0.26 0.00357355 0.00317661 61 -1 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_022bits.v common 5.51 vpr 52.24 MiB -1 -1 0.09 16580 1 0.01 -1 -1 29440 -1 -1 10 45 0 0 success v8.0.0-7663-gb6a96700f release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-24T17:35:35 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_final/vtr-verilog-to-routing/vtr_flow/tasks 53492 45 23 160 161 1 114 78 17 17 289 -1 unnamed_device 13.6 MiB 0.03 438 52.2 MiB 0.05 0.00 1.33907 -48.8774 -1.33907 1.33907 0.92 0.000123631 9.9151e-05 0.00812127 0.00662795 32 1278 24 6.64007e+06 125580 554710. 1919.41 2.78 0.04997 0.042556 22834 132086 -1 949 18 691 691 52057 13771 0 0 52057 13771 691 691 0 0 2589 2153 0 0 4007 3065 0 0 691 691 0 0 21701 3653 0 0 22378 3518 0 0 691 0 0 0 0 0 691 0 0 1.31685 1.31685 -60.8202 -1.31685 0 0 701300. 2426.64 0.25 0.03 0.08 -1 -1 0.25 0.00646311 0.0056862 68 -1 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_024bits.v common 4.76 vpr 52.46 MiB -1 -1 0.11 16576 1 0.01 -1 -1 29488 -1 -1 10 49 0 0 success v8.0.0-7663-gb6a96700f release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-24T17:35:35 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_final/vtr-verilog-to-routing/vtr_flow/tasks 53720 49 25 174 175 1 123 84 17 17 289 -1 unnamed_device 13.9 MiB 0.03 770 52.5 MiB 0.04 0.00 1.59018 -62.8916 -1.59018 1.59018 0.90 7.9107e-05 6.3022e-05 0.00620355 0.00505757 28 1454 14 6.64007e+06 125580 500653. 1732.36 2.20 0.0521052 0.0446513 21970 115934 -1 1321 16 613 613 53018 12080 0 0 53018 12080 613 613 0 0 2371 1902 0 0 3225 2630 0 0 613 613 0 0 23987 3241 0 0 22209 3081 0 0 613 0 0 0 0 0 613 0 0 1.26845 1.26845 -73.4983 -1.26845 0 0 612192. 2118.31 0.24 0.03 0.08 -1 -1 0.24 0.00673762 0.00597204 73 -1 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_028bits.v common 4.94 vpr 52.46 MiB -1 -1 0.10 16924 1 0.02 -1 -1 29468 -1 -1 11 57 0 0 success v8.0.0-7663-gb6a96700f release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-24T17:35:35 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_final/vtr-verilog-to-routing/vtr_flow/tasks 53716 57 29 202 203 1 143 97 17 17 289 -1 unnamed_device 13.9 MiB 0.05 915 52.5 MiB 0.07 0.00 1.63418 -74.8248 -1.63418 1.63418 0.81 0.000156397 0.000125774 0.0111944 0.00915368 28 1650 17 6.64007e+06 138138 500653. 1732.36 2.02 0.0663474 0.0571796 21970 115934 -1 1516 14 631 631 54365 12379 0 0 54365 12379 631 631 0 0 2326 1855 0 0 3194 2638 0 0 631 631 0 0 25161 3311 0 0 22422 3313 0 0 631 0 0 0 0 0 631 0 0 1.21425 1.21425 -83.3424 -1.21425 0 0 612192. 2118.31 0.28 0.02 0.11 -1 -1 0.28 0.00520632 0.00461195 85 -1 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_032bits.v common 5.25 vpr 52.78 MiB -1 -1 0.07 16848 1 0.01 -1 -1 29684 -1 -1 13 65 0 0 success v8.0.0-7663-gb6a96700f release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-24T17:35:35 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_final/vtr-verilog-to-routing/vtr_flow/tasks 54044 65 33 230 231 1 164 111 17 17 289 -1 unnamed_device 14.2 MiB 0.05 873 52.8 MiB 0.07 0.00 1.90729 -84.1469 -1.90729 1.90729 1.01 0.000186991 0.000153297 0.0094987 0.00788332 28 1947 30 6.64007e+06 163254 500653. 1732.36 2.24 0.0701247 0.0608298 21970 115934 -1 1628 15 711 711 67345 16229 0 0 67345 16229 711 711 0 0 2765 2218 0 0 3701 3115 0 0 711 711 0 0 29768 4488 0 0 29689 4986 0 0 711 0 0 0 0 0 711 0 0 1.42045 1.42045 -99.8589 -1.42045 0 0 612192. 2118.31 0.19 0.02 0.06 -1 -1 0.19 0.00567555 0.00504595 97 -1 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_048bits.v common 3.95 vpr 53.62 MiB -1 -1 0.11 17012 1 0.01 -1 -1 29748 -1 -1 19 97 0 0 success v8.0.0-7663-gb6a96700f release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-24T17:35:35 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_final/vtr-verilog-to-routing/vtr_flow/tasks 54908 97 49 342 343 1 246 165 17 17 289 -1 unnamed_device 14.7 MiB 0.05 1531 53.6 MiB 0.17 0.00 2.54151 -147.13 -2.54151 2.54151 0.84 0.000286534 0.000242044 0.0246237 0.020926 32 2870 15 6.64007e+06 238602 554710. 1919.41 0.97 0.0728358 0.0638497 22834 132086 -1 2658 20 1099 1099 107262 24115 0 0 107262 24115 1099 1099 0 0 4195 3440 0 0 6669 5031 0 0 1099 1099 0 0 48750 6526 0 0 45450 6920 0 0 1099 0 0 0 0 0 1099 0 0 1.55045 1.55045 -151.998 -1.55045 0 0 701300. 2426.64 0.30 0.06 0.12 -1 -1 0.30 0.0175525 0.0158425 145 -1 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_064bits.v common 4.36 vpr 54.13 MiB -1 -1 0.13 17292 1 0.02 -1 -1 29892 -1 -1 25 129 0 0 success v8.0.0-7663-gb6a96700f release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-24T17:35:35 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_final/vtr-verilog-to-routing/vtr_flow/tasks 55432 129 65 454 455 1 328 219 17 17 289 -1 unnamed_device 15.5 MiB 0.08 2046 54.1 MiB 0.26 0.01 3.17573 -212.447 -3.17573 3.17573 0.96 0.000446247 0.000387562 0.0373267 0.0324437 32 3925 17 6.64007e+06 313950 554710. 1919.41 0.88 0.087792 0.0781194 22834 132086 -1 3379 16 1314 1314 107802 25432 0 0 107802 25432 1314 1314 0 0 5056 4098 0 0 7658 5876 0 0 1314 1314 0 0 45926 6641 0 0 46534 6189 0 0 1314 0 0 0 0 0 1314 0 0 1.68825 1.68825 -198.514 -1.68825 0 0 701300. 2426.64 0.30 0.07 0.12 -1 -1 0.30 0.0208623 0.0191534 193 -1 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_003bits.v common 2.75 vpr 51.41 MiB -1 -1 0.08 16432 1 0.00 -1 -1 29500 -1 -1 2 7 0 0 success v8.0.0-7663-gb6a96700f release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-24T17:35:35 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_final/vtr-verilog-to-routing/vtr_flow/tasks 52640 7 4 27 28 1 14 13 17 17 289 -1 unnamed_device 12.9 MiB 0.00 30 51.4 MiB 0.00 0.00 0.649848 -5.93533 -0.649848 0.649848 0.87 1.139e-05 7.636e-06 0.000315036 0.000245504 14 114 8 6.65987e+06 25356 279208. 966.117 0.33 0.00252286 0.00195897 19378 63921 -1 109 16 78 78 5736 1764 0 0 5736 1764 78 78 0 0 349 302 0 0 399 380 0 0 78 78 0 0 1948 521 0 0 2884 405 0 0 78 0 0 0 0 0 78 0 0 0.83871 0.83871 -7.97873 -0.83871 0 0 355633. 1230.56 0.17 0.01 0.05 -1 -1 0.17 0.00141948 0.00120178 10 -1 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_004bits.v common 4.07 vpr 51.39 MiB -1 -1 0.08 16468 1 0.01 -1 -1 29492 -1 -1 2 9 0 0 success v8.0.0-7663-gb6a96700f release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-24T17:35:35 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_final/vtr-verilog-to-routing/vtr_flow/tasks 52628 9 5 34 35 1 20 16 17 17 289 -1 unnamed_device 12.8 MiB 0.01 69 51.4 MiB 0.00 0.00 0.660848 -7.41736 -0.660848 0.660848 0.74 2.567e-05 1.8311e-05 0.000607636 0.000487735 26 168 6 6.65987e+06 25356 477104. 1650.88 1.72 0.0084885 0.00676341 21682 110474 -1 155 7 60 60 4507 1260 0 0 4507 1260 60 60 0 0 279 225 0 0 330 296 0 0 60 60 0 0 1936 323 0 0 1842 296 0 0 60 0 0 0 0 0 60 0 0 0.71851 0.71851 -10.0618 -0.71851 0 0 585099. 2024.56 0.26 0.01 0.10 -1 -1 0.26 0.00102297 0.000903227 13 -1 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_005bits.v common 4.08 vpr 51.53 MiB -1 -1 0.07 16364 1 0.01 -1 -1 29420 -1 -1 2 11 0 0 success v8.0.0-7663-gb6a96700f release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-24T17:35:35 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_final/vtr-verilog-to-routing/vtr_flow/tasks 52764 11 6 41 42 1 26 19 17 17 289 -1 unnamed_device 12.9 MiB 0.01 57 51.5 MiB 0.01 0.00 0.682848 -9.10125 -0.682848 0.682848 0.84 2.8738e-05 2.1198e-05 0.00109179 0.000852543 26 186 35 6.65987e+06 25356 477104. 1650.88 1.75 0.0132085 0.0105041 21682 110474 -1 169 42 237 237 12100 3761 0 0 12100 3761 237 237 0 0 831 636 0 0 1217 971 0 0 237 237 0 0 4452 817 0 0 5126 863 0 0 237 0 0 0 0 0 237 0 0 1.03245 1.03245 -12.6712 -1.03245 0 0 585099. 2024.56 0.25 0.02 0.10 -1 -1 0.25 0.00328217 0.00271096 16 -1 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_006bits.v common 4.50 vpr 51.48 MiB -1 -1 0.09 16376 1 0.01 -1 -1 29344 -1 -1 4 13 0 0 success v8.0.0-7663-gb6a96700f release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-24T17:35:35 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_final/vtr-verilog-to-routing/vtr_flow/tasks 52712 13 7 48 49 1 32 24 17 17 289 -1 unnamed_device 12.8 MiB 0.01 92 51.5 MiB 0.01 0.00 0.704848 -11.3995 -0.704848 0.704848 0.94 3.1981e-05 2.3373e-05 0.00117187 0.000914341 26 274 11 6.65987e+06 50712 477104. 1650.88 1.80 0.0130604 0.0104442 21682 110474 -1 259 15 144 144 12472 3342 0 0 12472 3342 144 144 0 0 608 496 0 0 995 845 0 0 144 144 0 0 5195 851 0 0 5386 862 0 0 144 0 0 0 0 0 144 0 0 1.09259 1.09259 -17.4602 -1.09259 0 0 585099. 2024.56 0.20 0.01 0.06 -1 -1 0.20 0.0013362 0.00115177 20 -1 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_007bits.v common 4.60 vpr 51.55 MiB -1 -1 0.09 16372 1 0.01 -1 -1 29500 -1 -1 3 15 0 0 success v8.0.0-7663-gb6a96700f release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-24T17:35:35 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_final/vtr-verilog-to-routing/vtr_flow/tasks 52784 15 8 55 56 1 38 26 17 17 289 -1 unnamed_device 12.9 MiB 0.01 111 51.5 MiB 0.01 0.00 0.944958 -13.8003 -0.944958 0.944958 1.00 4.0945e-05 3.028e-05 0.00191951 0.00149669 26 305 13 6.65987e+06 38034 477104. 1650.88 1.75 0.0159314 0.0128676 21682 110474 -1 259 11 161 161 9271 2872 0 0 9271 2872 161 161 0 0 656 544 0 0 1041 883 0 0 161 161 0 0 3294 636 0 0 3958 487 0 0 161 0 0 0 0 0 161 0 0 1.09645 1.09645 -19.1204 -1.09645 0 0 585099. 2024.56 0.27 0.01 0.10 -1 -1 0.27 0.00199441 0.00175653 22 -1 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_008bits.v common 3.19 vpr 51.47 MiB -1 -1 0.06 16316 1 0.01 -1 -1 29508 -1 -1 4 17 0 0 success v8.0.0-7663-gb6a96700f release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-24T17:35:35 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_final/vtr-verilog-to-routing/vtr_flow/tasks 52704 17 9 62 63 1 41 30 17 17 289 -1 unnamed_device 12.8 MiB 0.01 121 51.5 MiB 0.02 0.00 0.955958 -15.9716 -0.955958 0.955958 0.85 4.4222e-05 3.3144e-05 0.00261502 0.00203481 26 321 18 6.65987e+06 50712 477104. 1650.88 0.71 0.0106052 0.00864775 21682 110474 -1 290 17 195 195 14022 3952 0 0 14022 3952 195 195 0 0 807 673 0 0 1359 1086 0 0 195 195 0 0 5524 904 0 0 5942 899 0 0 195 0 0 0 0 0 195 0 0 1.07445 1.07445 -20.9549 -1.07445 0 0 585099. 2024.56 0.27 0.01 0.10 -1 -1 0.27 0.00271088 0.00234323 25 -1 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_009bits.v common 4.11 vpr 51.52 MiB -1 -1 0.10 16328 1 0.01 -1 -1 29452 -1 -1 4 19 0 0 success v8.0.0-7663-gb6a96700f release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-24T17:35:35 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_final/vtr-verilog-to-routing/vtr_flow/tasks 52760 19 10 69 70 1 44 33 17 17 289 -1 unnamed_device 13.1 MiB 0.01 130 51.5 MiB 0.02 0.00 0.966958 -17.6732 -0.966958 0.966958 0.81 4.8762e-05 3.6649e-05 0.00312277 0.00245206 32 364 15 6.65987e+06 50712 554710. 1919.41 1.65 0.0171943 0.0140684 22834 132086 -1 318 16 181 181 16758 4339 0 0 16758 4339 181 181 0 0 721 591 0 0 1409 1092 0 0 181 181 0 0 6895 1195 0 0 7371 1099 0 0 181 0 0 0 0 0 181 0 0 1.22765 1.22765 -24.888 -1.22765 0 0 701300. 2426.64 0.19 0.01 0.07 -1 -1 0.19 0.00252149 0.00217769 28 -1 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_010bits.v common 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v8.0.0-7663-gb6a96700f release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-24T17:35:35 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_final/vtr-verilog-to-routing/vtr_flow/tasks 52764 23 12 83 84 1 55 40 17 17 289 -1 unnamed_device 13.0 MiB 0.01 186 51.5 MiB 0.02 0.00 0.988958 -22.792 -0.988958 0.988958 0.84 5.8815e-05 4.495e-05 0.00303517 0.00241101 26 551 20 6.65987e+06 63390 477104. 1650.88 0.81 0.0140151 0.0115804 21682 110474 -1 427 15 253 253 20964 5762 0 0 20964 5762 253 253 0 0 1049 856 0 0 1741 1452 0 0 253 253 0 0 8269 1540 0 0 9399 1408 0 0 253 0 0 0 0 0 253 0 0 1.14045 1.14045 -30.5211 -1.14045 0 0 585099. 2024.56 0.26 0.01 0.10 -1 -1 0.26 0.00324929 0.00285139 34 -1 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_012bits.v common 4.61 vpr 51.69 MiB -1 -1 0.10 16632 1 0.01 -1 -1 29500 -1 -1 5 25 0 0 success v8.0.0-7663-gb6a96700f release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-24T17:35:35 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_final/vtr-verilog-to-routing/vtr_flow/tasks 52928 25 13 90 91 1 61 43 17 17 289 -1 unnamed_device 13.2 MiB 0.01 184 51.7 MiB 0.01 0.00 0.999958 -24.6468 -0.999958 0.999958 0.63 3.4062e-05 2.5206e-05 0.00189315 0.00146924 30 556 23 6.65987e+06 63390 526063. 1820.29 2.26 0.0259999 0.0212945 22546 126617 -1 458 17 355 355 20023 5892 0 0 20023 5892 355 355 0 0 1288 1071 0 0 1883 1551 0 0 355 355 0 0 7381 1405 0 0 8761 1155 0 0 355 0 0 0 0 0 355 0 0 1.16365 1.16365 -30.7419 -1.16365 0 0 666494. 2306.21 0.27 0.01 0.09 -1 -1 0.27 0.00231221 0.00202388 37 -1 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_013bits.v common 4.08 vpr 51.70 MiB -1 -1 0.09 16624 1 0.02 -1 -1 29536 -1 -1 6 27 0 0 success v8.0.0-7663-gb6a96700f release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-24T17:35:35 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_final/vtr-verilog-to-routing/vtr_flow/tasks 52940 27 14 97 98 1 67 47 17 17 289 -1 unnamed_device 13.1 MiB 0.01 242 51.7 MiB 0.01 0.00 1.01096 -26.8731 -1.01096 1.01096 0.65 4.0374e-05 3.07e-05 0.00233009 0.00181096 32 601 28 6.65987e+06 76068 554710. 1919.41 1.80 0.0230813 0.0189132 22834 132086 -1 508 17 313 313 25760 6870 0 0 25760 6870 313 313 0 0 1314 1070 0 0 2405 1929 0 0 313 313 0 0 11188 1537 0 0 10227 1708 0 0 313 0 0 0 0 0 313 0 0 1.15145 1.15145 -34.7701 -1.15145 0 0 701300. 2426.64 0.31 0.02 0.13 -1 -1 0.31 0.00424393 0.00371315 40 -1 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_014bits.v common 4.08 vpr 51.89 MiB -1 -1 0.08 16632 1 0.01 -1 -1 29448 -1 -1 7 29 0 0 success v8.0.0-7663-gb6a96700f release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-24T17:35:35 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_final/vtr-verilog-to-routing/vtr_flow/tasks 53140 29 15 104 105 1 73 51 17 17 289 -1 unnamed_device 13.3 MiB 0.02 264 51.9 MiB 0.01 0.00 1.02196 -29.2306 -1.02196 1.02196 0.88 4.126e-05 3.0994e-05 0.002453 0.00193098 28 764 22 6.65987e+06 88746 500653. 1732.36 1.30 0.0242442 0.0201099 21970 115934 -1 617 16 341 341 32858 8352 0 0 32858 8352 341 341 0 0 1432 1208 0 0 2136 1803 0 0 341 341 0 0 14161 2454 0 0 14447 2205 0 0 341 0 0 0 0 0 341 0 0 1.29365 1.29365 -41.501 -1.29365 0 0 612192. 2118.31 0.27 0.02 0.11 -1 -1 0.27 0.00418561 0.00365138 44 -1 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_015bits.v common 3.58 vpr 51.89 MiB -1 -1 0.08 16740 1 0.01 -1 -1 29336 -1 -1 7 31 0 0 success v8.0.0-7663-gb6a96700f release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-24T17:35:35 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_final/vtr-verilog-to-routing/vtr_flow/tasks 53140 31 16 111 112 1 79 54 17 17 289 -1 unnamed_device 13.2 MiB 0.02 288 51.9 MiB 0.03 0.00 1.26207 -31.2273 -1.26207 1.26207 0.96 7.5871e-05 5.9239e-05 0.00438916 0.00349614 32 749 19 6.65987e+06 88746 554710. 1919.41 0.70 0.0162353 0.0135504 22834 132086 -1 607 15 366 366 29491 7623 0 0 29491 7623 366 366 0 0 1477 1210 0 0 2467 1886 0 0 366 366 0 0 11887 2017 0 0 12928 1778 0 0 366 0 0 0 0 0 366 0 0 1.20445 1.20445 -41.3966 -1.20445 0 0 701300. 2426.64 0.29 0.02 0.08 -1 -1 0.29 0.00449173 0.00396792 46 -1 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_016bits.v common 4.32 vpr 51.93 MiB -1 -1 0.09 16536 1 0.01 -1 -1 29372 -1 -1 7 33 0 0 success v8.0.0-7663-gb6a96700f release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-24T17:35:35 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_final/vtr-verilog-to-routing/vtr_flow/tasks 53180 33 17 118 119 1 82 57 17 17 289 -1 unnamed_device 13.5 MiB 0.02 303 51.9 MiB 0.02 0.00 1.27307 -33.5955 -1.27307 1.27307 0.59 4.9876e-05 3.8624e-05 0.00387513 0.00306541 32 787 40 6.65987e+06 88746 554710. 1919.41 2.26 0.0293186 0.0244782 22834 132086 -1 670 27 416 416 88792 47693 0 0 88792 47693 416 416 0 0 1658 1398 0 0 4067 2855 0 0 416 416 0 0 42699 20996 0 0 39536 21612 0 0 416 0 0 0 0 0 416 0 0 1.20959 1.20959 -43.9988 -1.20959 0 0 701300. 2426.64 0.19 0.03 0.07 -1 -1 0.19 0.00400642 0.00347754 49 -1 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_018bits.v common 4.88 vpr 51.92 MiB -1 -1 0.08 16732 1 0.01 -1 -1 29408 -1 -1 8 37 0 0 success v8.0.0-7663-gb6a96700f release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-24T17:35:35 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_final/vtr-verilog-to-routing/vtr_flow/tasks 53168 37 19 132 133 1 90 64 17 17 289 -1 unnamed_device 13.4 MiB 0.02 338 51.9 MiB 0.02 0.00 1.29507 -38.4852 -1.29507 1.29507 0.82 5.526e-05 4.3011e-05 0.00331354 0.00267113 32 960 27 6.65987e+06 101424 554710. 1919.41 2.22 0.0382813 0.0321595 22834 132086 -1 727 14 420 420 34815 9029 0 0 34815 9029 420 420 0 0 1707 1420 0 0 2794 2233 0 0 420 420 0 0 14503 2300 0 0 14971 2236 0 0 420 0 0 0 0 0 420 0 0 1.09525 1.09525 -47.5498 -1.09525 0 0 701300. 2426.64 0.32 0.02 0.12 -1 -1 0.32 0.00510908 0.00452156 55 -1 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_020bits.v common 3.72 vpr 51.99 MiB -1 -1 0.09 16736 1 0.01 -1 -1 29404 -1 -1 8 41 0 0 success v8.0.0-7663-gb6a96700f release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-24T17:35:35 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_final/vtr-verilog-to-routing/vtr_flow/tasks 53240 41 21 146 147 1 102 70 17 17 289 -1 unnamed_device 13.4 MiB 0.02 384 52.0 MiB 0.04 0.00 1.31707 -44.0199 -1.31707 1.31707 0.94 0.000106519 8.4922e-05 0.00681105 0.00555779 32 1072 22 6.65987e+06 101424 554710. 1919.41 0.79 0.0234177 0.0195696 22834 132086 -1 905 18 552 552 50728 13103 0 0 50728 13103 552 552 0 0 2312 1948 0 0 3605 2908 0 0 552 552 0 0 21893 3568 0 0 21814 3575 0 0 552 0 0 0 0 0 552 0 0 1.16245 1.16245 -55.2101 -1.16245 0 0 701300. 2426.64 0.27 0.03 0.12 -1 -1 0.27 0.00654728 0.00578343 61 -1 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_022bits.v common 5.71 vpr 52.08 MiB -1 -1 0.07 16672 1 0.01 -1 -1 29428 -1 -1 10 45 0 0 success v8.0.0-7663-gb6a96700f release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-24T17:35:35 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_final/vtr-verilog-to-routing/vtr_flow/tasks 53332 45 23 160 161 1 114 78 17 17 289 -1 unnamed_device 13.7 MiB 0.03 444 52.1 MiB 0.05 0.00 1.33907 -49.1178 -1.33907 1.33907 0.96 0.000116242 9.2428e-05 0.00780789 0.00638389 34 1333 23 6.65987e+06 126780 585099. 2024.56 2.88 0.0456981 0.038803 23122 138558 -1 961 23 660 660 57558 15052 0 0 57558 15052 660 660 0 0 2593 2125 0 0 4161 3348 0 0 660 660 0 0 24159 4240 0 0 25325 4019 0 0 660 0 0 0 0 0 660 0 0 1.17739 1.17739 -59.0308 -1.17739 0 0 742403. 2568.87 0.20 0.02 0.09 -1 -1 0.20 0.00480241 0.0042204 68 -1 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_024bits.v common 4.00 vpr 52.15 MiB -1 -1 0.09 16604 1 0.02 -1 -1 29456 -1 -1 10 49 0 0 success v8.0.0-7663-gb6a96700f release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-24T17:35:35 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_final/vtr-verilog-to-routing/vtr_flow/tasks 53404 49 25 174 175 1 123 84 17 17 289 -1 unnamed_device 13.6 MiB 0.03 795 52.2 MiB 0.06 0.00 1.59018 -63.132 -1.59018 1.59018 0.95 0.000127303 0.000102982 0.00984658 0.0080563 32 1455 27 6.65987e+06 126780 554710. 1919.41 0.94 0.0344959 0.0293499 22834 132086 -1 1347 18 550 550 54304 12297 0 0 54304 12297 550 550 0 0 2230 1852 0 0 3610 2913 0 0 550 550 0 0 24763 3256 0 0 22601 3176 0 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adder_064bits.v common 3.45 vpr 54.05 MiB -1 -1 0.12 17264 1 0.02 -1 -1 29996 -1 -1 25 129 0 0 success v8.0.0-7663-gb6a96700f release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-24T17:35:35 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_final/vtr-verilog-to-routing/vtr_flow/tasks 55348 129 65 454 455 1 328 219 17 17 289 -1 unnamed_device 15.3 MiB 0.06 2038 54.1 MiB 0.15 0.00 3.17573 -213.889 -3.17573 3.17573 0.60 0.000263403 0.00022992 0.022915 0.0200013 32 3908 17 6.65987e+06 316950 554710. 1919.41 0.69 0.0688575 0.0615303 22834 132086 -1 3507 29 1480 1480 192588 66144 0 0 192588 66144 1480 1480 0 0 5949 4957 0 0 10788 8088 0 0 1480 1480 0 0 85222 25041 0 0 87669 25098 0 0 1480 0 0 0 0 0 1480 0 0 1.75939 1.75939 -206.712 -1.75939 0 0 701300. 2426.64 0.29 0.11 0.12 -1 -1 0.29 0.0325392 0.0295588 193 -1 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml adder_003bits.v common 3.31 vpr 52.29 MiB -1 -1 0.06 16304 1 0.01 -1 -1 29440 -1 -1 1 7 0 0 success v8.0.0-7663-gb6a96700f release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-24T17:35:35 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_final/vtr-verilog-to-routing/vtr_flow/tasks 53544 7 4 27 28 1 12 12 17 17 289 -1 unnamed_device 13.8 MiB 0.02 37 52.3 MiB 0.01 0.00 0.712895 -6.47614 -0.712895 0.712895 0.96 1.5211e-05 9.342e-06 0.00039064 0.000362534 8 92 5 6.95648e+06 14475.7 166176. 575.005 0.74 0.00236468 0.00197058 20866 45572 -1 77 9 41 41 1638 700 0 0 1638 700 41 41 0 0 165 148 0 0 188 179 0 0 41 41 0 0 509 150 0 0 694 141 0 0 41 0 0 0 0 0 41 0 0 0.87204 0.87204 -7.97974 -0.87204 0 0 202963. 702.294 0.07 0.00 0.03 -1 -1 0.07 0.000644496 0.000556733 5 -1 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml adder_004bits.v common 4.00 vpr 52.28 MiB -1 -1 0.08 16456 1 0.00 -1 -1 29356 -1 -1 1 9 0 0 success v8.0.0-7663-gb6a96700f release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-24T17:35:35 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_final/vtr-verilog-to-routing/vtr_flow/tasks 53532 9 5 34 35 1 15 15 17 17 289 -1 unnamed_device 13.8 MiB 0.02 34 52.3 MiB 0.01 0.00 0.512442 -7.49947 -0.512442 0.512442 0.97 2.5249e-05 1.8146e-05 0.000924746 0.000706749 16 118 7 6.95648e+06 14475.7 332735. 1151.33 1.30 0.00644688 0.00515068 22306 75877 -1 87 12 64 64 6435 1823 0 0 6435 1823 64 64 0 0 292 256 0 0 342 296 0 0 64 64 0 0 2251 655 0 0 3422 488 0 0 64 0 0 0 0 0 64 0 0 0.87204 0.87204 -9.00307 -0.87204 0 0 414966. 1435.87 0.18 0.01 0.06 -1 -1 0.18 0.00146972 0.0012864 7 -1 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml adder_005bits.v common 3.48 vpr 52.33 MiB -1 -1 0.09 16468 1 0.01 -1 -1 29364 -1 -1 1 11 0 0 success v8.0.0-7663-gb6a96700f release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-24T17:35:35 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_final/vtr-verilog-to-routing/vtr_flow/tasks 53588 11 6 41 42 1 19 18 17 17 289 -1 unnamed_device 13.8 MiB 0.03 45 52.3 MiB 0.01 0.00 0.701895 -10.0315 -0.701895 0.701895 0.98 2.9856e-05 2.1932e-05 0.00105458 0.000830139 26 146 11 6.95648e+06 14475.7 503264. 1741.40 0.68 0.00577677 0.00469901 24322 120374 -1 132 8 55 55 3717 1148 0 0 3717 1148 55 55 0 0 234 196 0 0 289 245 0 0 55 55 0 0 1426 303 0 0 1658 294 0 0 55 0 0 0 0 0 55 0 0 0.74674 0.74674 -12.4122 -0.74674 0 0 618332. 2139.56 0.24 0.01 0.11 -1 -1 0.24 0.00132396 0.00117757 8 -1 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml adder_006bits.v common 4.41 vpr 52.42 MiB -1 -1 0.06 16360 1 0.00 -1 -1 29344 -1 -1 2 13 0 0 success v8.0.0-7663-gb6a96700f release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-24T17:35:35 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_final/vtr-verilog-to-routing/vtr_flow/tasks 53680 13 7 48 49 1 25 22 17 17 289 -1 unnamed_device 13.8 MiB 0.04 58 52.4 MiB 0.01 0.00 0.745895 -12.7431 -0.745895 0.745895 0.99 3.445e-05 2.5377e-05 0.00168321 0.00129637 26 158 12 6.95648e+06 28951.4 503264. 1741.40 1.55 0.0121163 0.00970932 24322 120374 -1 157 7 75 75 4018 1372 0 0 4018 1372 75 75 0 0 301 251 0 0 423 372 0 0 75 75 0 0 1334 349 0 0 1810 250 0 0 75 0 0 0 0 0 75 0 0 0.87204 0.87204 -14.299 -0.87204 0 0 618332. 2139.56 0.25 0.01 0.10 -1 -1 0.25 0.0014302 0.00128504 10 -1 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml adder_007bits.v common 3.58 vpr 52.21 MiB -1 -1 0.10 16360 1 0.01 -1 -1 29500 -1 -1 2 15 0 0 success v8.0.0-7663-gb6a96700f release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-24T17:35:35 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_final/vtr-verilog-to-routing/vtr_flow/tasks 53468 15 8 55 56 1 32 25 17 17 289 -1 unnamed_device 13.6 MiB 0.03 78 52.2 MiB 0.01 0.00 0.727332 -14.3024 -0.727332 0.727332 0.98 3.9561e-05 2.9564e-05 0.00161353 0.00127067 26 272 23 6.95648e+06 28951.4 503264. 1741.40 0.70 0.00875095 0.00715081 24322 120374 -1 268 14 189 189 14113 4458 0 0 14113 4458 189 189 0 0 823 733 0 0 1273 1051 0 0 189 189 0 0 5223 1229 0 0 6416 1067 0 0 189 0 0 0 0 0 189 0 0 1.18933 1.18933 -20.6612 -1.18933 0 0 618332. 2139.56 0.25 0.01 0.11 -1 -1 0.25 0.00221295 0.00193045 11 -1 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml adder_008bits.v common 2.96 vpr 52.39 MiB -1 -1 0.10 16304 1 0.01 -1 -1 29484 -1 -1 2 17 0 0 success v8.0.0-7663-gb6a96700f release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-24T17:35:35 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_final/vtr-verilog-to-routing/vtr_flow/tasks 53648 17 9 62 63 1 37 28 17 17 289 -1 unnamed_device 14.0 MiB 0.04 98 52.4 MiB 0.00 0.00 0.732132 -16.1501 -0.732132 0.732132 0.66 2.3477e-05 1.6926e-05 0.000643887 0.000527015 26 346 36 6.95648e+06 28951.4 503264. 1741.40 0.47 0.00647318 0.00528663 24322 120374 -1 279 18 270 270 14343 4758 0 0 14343 4758 270 270 0 0 1070 912 0 0 1676 1325 0 0 270 270 0 0 5092 935 0 0 5965 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IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-24T17:35:35 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_final/vtr-verilog-to-routing/vtr_flow/tasks 53768 25 13 90 91 1 60 41 17 17 289 -1 unnamed_device 13.9 MiB 0.04 173 52.5 MiB 0.01 0.00 0.793332 -24.4477 -0.793332 0.793332 0.80 3.6821e-05 2.8096e-05 0.00127898 0.00105074 32 586 27 6.95648e+06 43427 586450. 2029.24 1.06 0.0143097 0.0118407 25474 144626 -1 509 14 313 313 24741 7098 0 0 24741 7098 313 313 0 0 1219 1062 0 0 2112 1460 0 0 313 313 0 0 9221 1851 0 0 11563 2099 0 0 313 0 0 0 0 0 313 0 0 1.11903 1.11903 -35.1164 -1.11903 0 0 744469. 2576.02 0.29 0.02 0.12 -1 -1 0.29 0.00337603 0.00298253 19 -1 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml adder_013bits.v common 5.51 vpr 52.61 MiB -1 -1 0.09 16748 1 0.01 -1 -1 29416 -1 -1 3 27 0 0 success v8.0.0-7663-gb6a96700f release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-24T17:35:35 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_final/vtr-verilog-to-routing/vtr_flow/tasks 53872 27 14 97 98 1 66 44 17 17 289 -1 unnamed_device 14.0 MiB 0.03 185 52.6 MiB 0.01 0.00 0.826332 -26.4591 -0.826332 0.826332 0.93 3.5946e-05 2.668e-05 0.00194217 0.00153958 36 563 22 6.95648e+06 43427 648988. 2245.63 2.60 0.0272747 0.0225672 26050 158493 -1 465 14 411 411 24037 7608 0 0 24037 7608 411 411 0 0 1577 1397 0 0 2559 1949 0 0 411 411 0 0 8946 1755 0 0 10133 1685 0 0 411 0 0 0 0 0 411 0 0 1.27253 1.27253 -35.6079 -1.27253 0 0 828058. 2865.25 0.29 0.01 0.14 -1 -1 0.29 0.0027341 0.00245169 20 -1 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml adder_014bits.v common 3.85 vpr 52.54 MiB -1 -1 0.06 16608 1 0.00 -1 -1 29372 -1 -1 4 29 0 0 success v8.0.0-7663-gb6a96700f release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-24T17:35:35 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_final/vtr-verilog-to-routing/vtr_flow/tasks 53804 29 15 104 105 1 72 48 17 17 289 -1 unnamed_device 13.9 MiB 0.03 283 52.5 MiB 0.02 0.00 0.826332 -29.9889 -0.826332 0.826332 0.78 7.6085e-05 5.9546e-05 0.00392244 0.00318469 34 768 14 6.95648e+06 57902.7 618332. 2139.56 1.26 0.0252236 0.0210767 25762 151098 -1 655 13 377 377 37978 8699 0 0 37978 8699 377 377 0 0 1405 1203 0 0 2355 1661 0 0 377 377 0 0 15916 2816 0 0 17548 2265 0 0 377 0 0 0 0 0 377 0 0 1.25533 1.25533 -43.2489 -1.25533 0 0 787024. 2723.27 0.30 0.02 0.13 -1 -1 0.30 0.00375301 0.00334273 23 -1 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml adder_015bits.v common 5.86 vpr 52.73 MiB -1 -1 0.10 16720 1 0.01 -1 -1 29448 -1 -1 3 31 0 0 success v8.0.0-7663-gb6a96700f release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-24T17:35:35 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_final/vtr-verilog-to-routing/vtr_flow/tasks 53996 31 16 111 112 1 78 50 17 17 289 -1 unnamed_device 14.3 MiB 0.05 264 52.7 MiB 0.03 0.00 1.08336 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GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-24T17:35:35 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_final/vtr-verilog-to-routing/vtr_flow/tasks 54636 65 33 230 231 1 162 105 17 17 289 -1 unnamed_device 14.8 MiB 0.09 760 53.4 MiB 0.07 0.00 1.50539 -80.1968 -1.50539 1.50539 0.98 0.000173245 0.00014157 0.011933 0.00987039 38 1787 37 6.95648e+06 101330 678818. 2348.85 1.95 0.0744398 0.0652822 26626 170182 -1 1449 21 965 965 103324 22748 0 0 103324 22748 965 965 0 0 3285 2935 0 0 5660 3808 0 0 965 965 0 0 45920 7212 0 0 46529 6863 0 0 965 0 0 0 0 0 965 0 0 1.40103 1.40103 -97.7791 -1.40103 0 0 902133. 3121.57 0.34 0.05 0.15 -1 -1 0.34 0.0118209 0.0106167 49 -1 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml adder_048bits.v common 15.46 vpr 54.12 MiB -1 -1 0.08 16908 1 0.01 -1 -1 29732 -1 -1 10 97 0 0 success v8.0.0-7663-gb6a96700f release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-24T17:35:35 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_final/vtr-verilog-to-routing/vtr_flow/tasks 55424 97 49 342 343 1 243 156 17 17 289 -1 unnamed_device 15.3 MiB 0.11 1635 54.1 MiB 0.13 0.00 1.91642 -141.865 -1.91642 1.91642 0.97 0.000264775 0.000225822 0.0234511 0.0199592 44 3056 26 6.95648e+06 144757 787024. 2723.27 12.02 0.194066 0.172337 27778 195446 -1 2674 23 1244 1244 134880 27002 0 0 134880 27002 1244 1244 0 0 4192 3716 0 0 7367 4911 0 0 1244 1244 0 0 63077 7902 0 0 57756 7985 0 0 1244 0 0 0 0 0 1244 0 0 1.56403 1.56403 -161.04 -1.56403 0 0 997811. 3452.63 0.39 0.07 0.18 -1 -1 0.39 0.0190318 0.0171975 73 -1 -1 -1 -1 -1 -fixed_k6_frac_2ripple_N8_22nm.xml adder_064bits.v common 15.63 vpr 54.80 MiB -1 -1 0.13 17072 1 0.02 -1 -1 29932 -1 -1 13 129 0 0 success v8.0.0-7663-gb6a96700f release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-24T17:35:35 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_final/vtr-verilog-to-routing/vtr_flow/tasks 56120 129 65 454 455 1 324 207 17 17 289 -1 unnamed_device 15.8 MiB 0.08 2046 54.8 MiB 0.21 0.01 2.32745 -199.458 -2.32745 2.32745 0.79 0.00041552 0.000355007 0.0380517 0.0331811 50 3850 44 6.95648e+06 188184 902133. 3121.57 12.48 0.274602 0.247248 28642 213929 -1 3500 31 1617 1617 439794 201828 0 0 439794 201828 1617 1617 0 0 5598 4911 0 0 13546 7985 0 0 1617 1617 0 0 208643 93339 0 0 208773 92359 0 0 1617 0 0 0 0 0 1617 0 0 1.74423 1.74423 -218.604 -1.74423 0 0 1.08113e+06 3740.92 0.38 0.13 0.20 -1 -1 0.38 0.0245029 0.0225234 97 -1 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml adder_003bits.v common 3.45 vpr 51.91 MiB -1 -1 0.06 16308 1 0.01 -1 -1 29408 -1 -1 1 7 0 0 success v8.0.0-7663-gb6a96700f release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-24T17:35:35 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_final/vtr-verilog-to-routing/vtr_flow/tasks 53156 7 4 27 28 1 12 12 17 17 289 -1 unnamed_device 13.5 MiB 0.01 37 51.9 MiB 0.00 0.00 0.589542 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VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-24T17:35:35 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_final/vtr-verilog-to-routing/vtr_flow/tasks 53548 19 10 69 70 1 44 31 17 17 289 -1 unnamed_device 13.8 MiB 0.02 276 52.3 MiB 0.01 0.00 0.743132 -23.8011 -0.743132 0.743132 0.99 4.8042e-05 3.6886e-05 0.00243934 0.00193001 28 538 22 6.99608e+06 29431.4 531479. 1839.03 2.43 0.0182907 0.0149541 24610 126494 -1 519 12 220 220 23985 5297 0 0 23985 5297 220 220 0 0 870 744 0 0 1219 1005 0 0 220 220 0 0 10995 1608 0 0 10461 1500 0 0 220 0 0 0 0 0 220 0 0 0.949732 0.949732 -28.2293 -0.949732 0 0 648988. 2245.63 0.26 0.01 0.11 -1 -1 0.26 0.00248311 0.00218828 14 -1 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml adder_010bits.v common 5.08 vpr 52.27 MiB -1 -1 0.10 16664 1 0.00 -1 -1 29400 -1 -1 2 21 0 0 success v8.0.0-7663-gb6a96700f release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-24T17:35:35 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_final/vtr-verilog-to-routing/vtr_flow/tasks 53520 21 11 76 77 1 48 34 17 17 289 -1 unnamed_device 13.8 MiB 0.02 159 52.3 MiB 0.01 0.00 0.743132 -20.8848 -0.743132 0.743132 1.00 5.5025e-05 4.2043e-05 0.00184045 0.00148397 30 378 13 6.99608e+06 29431.4 556674. 1926.21 2.20 0.0155977 0.0128176 25186 138497 -1 289 13 259 259 13646 4379 0 0 13646 4379 259 259 0 0 1028 923 0 0 1346 1144 0 0 259 259 0 0 5033 958 0 0 5721 836 0 0 259 0 0 0 0 0 259 0 0 0.857432 0.857432 -25.065 -0.857432 0 0 706193. 2443.58 0.24 0.01 0.08 -1 -1 0.24 0.00279804 0.00247623 16 -1 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml adder_011bits.v common 3.39 vpr 52.30 MiB -1 -1 0.10 16572 1 0.01 -1 -1 29428 -1 -1 3 23 0 0 success v8.0.0-7663-gb6a96700f release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-24T17:35:35 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_final/vtr-verilog-to-routing/vtr_flow/tasks 53560 23 12 83 84 1 54 38 17 17 289 -1 unnamed_device 13.8 MiB 0.02 207 52.3 MiB 0.02 0.00 0.87204 -24.0372 -0.87204 0.87204 0.97 5.7807e-05 4.4449e-05 0.0031012 0.00243182 28 556 17 6.99608e+06 44147 531479. 1839.03 0.75 0.0124743 0.0102848 24610 126494 -1 485 13 259 259 19807 5350 0 0 19807 5350 259 259 0 0 1018 905 0 0 1590 1253 0 0 259 259 0 0 7840 1385 0 0 8841 1289 0 0 259 0 0 0 0 0 259 0 0 0.99734 0.99734 -32.4022 -0.99734 0 0 648988. 2245.63 0.26 0.01 0.11 -1 -1 0.26 0.00298143 0.00265118 17 -1 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml adder_012bits.v common 3.98 vpr 52.34 MiB -1 -1 0.10 16660 1 0.01 -1 -1 29324 -1 -1 3 25 0 0 success v8.0.0-7663-gb6a96700f release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-24T17:35:35 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_final/vtr-verilog-to-routing/vtr_flow/tasks 53600 25 13 90 91 1 60 41 17 17 289 -1 unnamed_device 13.8 MiB 0.02 184 52.3 MiB 0.01 0.00 0.776132 -24.2677 -0.776132 0.776132 0.97 6.3152e-05 4.9046e-05 0.00204223 0.00168456 32 605 20 6.99608e+06 44147 586450. 2029.24 1.21 0.0162045 0.0136479 25474 144626 -1 538 15 327 327 26392 7495 0 0 26392 7495 327 327 0 0 1228 1061 0 0 2233 1632 0 0 327 327 0 0 10177 1900 0 0 12100 2248 0 0 327 0 0 0 0 0 327 0 0 1.14103 1.14103 -35.8076 -1.14103 0 0 744469. 2576.02 0.29 0.02 0.13 -1 -1 0.29 0.00349289 0.0030754 19 -1 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml adder_013bits.v common 5.26 vpr 52.55 MiB -1 -1 0.11 16572 1 0.02 -1 -1 29348 -1 -1 3 27 0 0 success v8.0.0-7663-gb6a96700f release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-24T17:35:35 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_final/vtr-verilog-to-routing/vtr_flow/tasks 53812 27 14 97 98 1 66 44 17 17 289 -1 unnamed_device 13.9 MiB 0.02 211 52.6 MiB 0.02 0.00 0.787132 -26.7604 -0.787132 0.787132 0.97 7.0188e-05 5.4255e-05 0.00338223 0.00271001 34 710 22 6.99608e+06 44147 618332. 2139.56 2.35 0.0269562 0.0221336 25762 151098 -1 585 17 382 382 38126 9583 0 0 38126 9583 382 382 0 0 1366 1173 0 0 2376 1646 0 0 382 382 0 0 15590 3038 0 0 18030 2962 0 0 382 0 0 0 0 0 382 0 0 1.35863 1.35863 -40.1147 -1.35863 0 0 787024. 2723.27 0.23 0.01 0.13 -1 -1 0.23 0.00296452 0.00261558 20 -1 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml adder_014bits.v common 6.18 vpr 52.53 MiB -1 -1 0.09 16588 1 0.00 -1 -1 29340 -1 -1 4 29 0 0 success v8.0.0-7663-gb6a96700f release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-24T17:35:35 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_final/vtr-verilog-to-routing/vtr_flow/tasks 53788 29 15 104 105 1 72 48 17 17 289 -1 unnamed_device 13.9 MiB 0.02 211 52.5 MiB 0.02 0.00 0.798132 -28.3603 -0.798132 0.798132 0.98 7.1328e-05 5.6082e-05 0.00355953 0.00286876 38 600 33 6.99608e+06 58862.7 678818. 2348.85 3.15 0.0391469 0.0329089 26626 170182 -1 464 24 576 576 35853 10518 0 0 35853 10518 576 576 0 0 1872 1655 0 0 3253 2131 0 0 576 576 0 0 14372 2672 0 0 15204 2908 0 0 576 0 0 0 0 0 576 0 0 1.20418 1.20418 -37.5361 -1.20418 0 0 902133. 3121.57 0.34 0.02 0.12 -1 -1 0.34 0.0052935 0.00457805 23 -1 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml adder_015bits.v common 4.84 vpr 52.45 MiB -1 -1 0.10 16732 1 0.01 -1 -1 29464 -1 -1 3 31 0 0 success v8.0.0-7663-gb6a96700f release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-24T17:35:35 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_final/vtr-verilog-to-routing/vtr_flow/tasks 53712 31 16 111 112 1 78 50 17 17 289 -1 unnamed_device 13.8 MiB 0.02 264 52.5 MiB 0.02 0.00 1.04416 -31.4091 -1.04416 1.04416 0.72 4.3113e-05 3.2421e-05 0.00280376 0.00223204 34 795 33 6.99608e+06 44147 618332. 2139.56 2.33 0.0314213 0.0260826 25762 151098 -1 595 16 419 419 32158 8277 0 0 32158 8277 419 419 0 0 1534 1353 0 0 2437 1778 0 0 419 419 0 0 13848 2045 0 0 13501 2263 0 0 419 0 0 0 0 0 419 0 0 1.19403 1.19403 -42.5776 -1.19403 0 0 787024. 2723.27 0.30 0.02 0.13 -1 -1 0.30 0.00437826 0.00386668 24 -1 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml adder_016bits.v common 4.82 vpr 52.42 MiB -1 -1 0.10 16744 1 0.01 -1 -1 29460 -1 -1 4 33 0 0 success v8.0.0-7663-gb6a96700f release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-24T17:35:35 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_final/vtr-verilog-to-routing/vtr_flow/tasks 53680 33 17 118 119 1 81 54 17 17 289 -1 unnamed_device 13.8 MiB 0.02 281 52.4 MiB 0.03 0.00 1.05516 -34.8802 -1.05516 1.05516 0.86 8.5488e-05 6.7546e-05 0.0046812 0.00380003 36 805 24 6.99608e+06 58862.7 648988. 2245.63 2.24 0.0319259 0.0265749 26050 158493 -1 597 16 467 467 31595 8647 0 0 31595 8647 467 467 0 0 1642 1435 0 0 2638 1903 0 0 467 467 0 0 12353 2270 0 0 14028 2105 0 0 467 0 0 0 0 0 467 0 0 1.30833 1.30833 -45.67 -1.30833 0 0 828058. 2865.25 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adder_020bits.v common 5.70 vpr 52.69 MiB -1 -1 0.08 16496 1 0.00 -1 -1 29584 -1 -1 4 41 0 0 success v8.0.0-7663-gb6a96700f release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-24T17:35:35 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_final/vtr-verilog-to-routing/vtr_flow/tasks 53956 41 21 146 147 1 94 66 17 17 289 -1 unnamed_device 14.2 MiB 0.02 350 52.7 MiB 0.02 0.00 1.09916 -43.2906 -1.09916 1.09916 0.60 6.0135e-05 4.6788e-05 0.00408364 0.00329915 36 1040 38 6.99608e+06 58862.7 648988. 2245.63 3.42 0.0451626 0.0378439 26050 158493 -1 799 20 588 588 53831 12839 0 0 53831 12839 588 588 0 0 2087 1840 0 0 3647 2426 0 0 588 588 0 0 23098 3643 0 0 23823 3754 0 0 588 0 0 0 0 0 588 0 0 1.19403 1.19403 -54.8307 -1.19403 0 0 828058. 2865.25 0.32 0.03 0.14 -1 -1 0.32 0.00654715 0.0057574 31 -1 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml adder_022bits.v common 5.98 vpr 52.81 MiB -1 -1 0.09 16696 1 0.01 -1 -1 29436 -1 -1 5 45 0 0 success v8.0.0-7663-gb6a96700f release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-24T17:35:35 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_final/vtr-verilog-to-routing/vtr_flow/tasks 54076 45 23 160 161 1 107 73 17 17 289 -1 unnamed_device 14.2 MiB 0.02 397 52.8 MiB 0.04 0.00 1.12116 -47.9377 -1.12116 1.12116 0.98 0.000109798 8.7279e-05 0.007734 0.0063206 36 1088 43 6.99608e+06 73578.4 648988. 2245.63 3.07 0.064081 0.0550887 26050 158493 -1 870 17 588 588 51618 13224 0 0 51618 13224 588 588 0 0 2105 1836 0 0 3351 2348 0 0 588 588 0 0 21992 3962 0 0 22994 3902 0 0 588 0 0 0 0 0 588 0 0 1.41548 1.41548 -64.6601 -1.41548 0 0 828058. 2865.25 0.26 0.03 0.13 -1 -1 0.26 0.00691048 0.00610689 34 -1 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml adder_024bits.v common 7.01 vpr 52.83 MiB -1 -1 0.07 16660 1 0.01 -1 -1 29460 -1 -1 5 49 0 0 success v8.0.0-7663-gb6a96700f release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-24T17:35:35 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_final/vtr-verilog-to-routing/vtr_flow/tasks 54100 49 25 174 175 1 118 79 17 17 289 -1 unnamed_device 14.4 MiB 0.03 454 52.8 MiB 0.05 0.00 1.14316 -52.1276 -1.14316 1.14316 0.99 0.000123631 9.8726e-05 0.00826176 0.00677195 38 1333 27 6.99608e+06 73578.4 678818. 2348.85 3.90 0.0702038 0.0598865 26626 170182 -1 1061 16 724 724 65888 16603 0 0 65888 16603 724 724 0 0 2522 2182 0 0 3858 2757 0 0 724 724 0 0 27061 5404 0 0 30999 4812 0 0 724 0 0 0 0 0 724 0 0 1.40733 1.40733 -73.7274 -1.40733 0 0 902133. 3121.57 0.33 0.02 0.15 -1 -1 0.33 0.00494507 0.00443417 37 -1 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml adder_028bits.v common 7.14 vpr 52.97 MiB -1 -1 0.10 16932 1 0.01 -1 -1 29480 -1 -1 6 57 0 0 success v8.0.0-7663-gb6a96700f release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-24T17:35:35 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_final/vtr-verilog-to-routing/vtr_flow/tasks 54244 57 29 202 203 1 141 92 17 17 289 -1 unnamed_device 14.4 MiB 0.04 636 53.0 MiB 0.04 0.00 1.18716 -65.4009 -1.18716 1.18716 0.93 8.5347e-05 6.8549e-05 0.00693585 0.00572188 40 1406 22 6.99608e+06 88294.1 706193. 2443.58 3.95 0.0836353 0.0723593 26914 176310 -1 1139 18 727 727 63659 15180 0 0 63659 15180 727 727 0 0 2644 2286 0 0 4066 3039 0 0 727 727 0 0 28541 4101 0 0 26954 4300 0 0 727 0 0 0 0 0 727 0 0 1.24903 1.24903 -81.2373 -1.24903 0 0 926341. 3205.33 0.36 0.03 0.16 -1 -1 0.36 0.0084417 0.00753384 43 -1 -1 -1 -1 -1 -fixed_k6_frac_2uripple_N8_22nm.xml adder_032bits.v common 5.17 vpr 53.09 MiB -1 -1 0.11 16888 1 0.01 -1 -1 29600 -1 -1 7 65 0 0 success v8.0.0-7663-gb6a96700f release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-24T17:35:35 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_final/vtr-verilog-to-routing/vtr_flow/tasks 54364 65 33 230 231 1 162 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2023-04-24T17:35:35 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_final/vtr-verilog-to-routing/vtr_flow/tasks 52932 15 8 47 55 1 36 25 17 17 289 -1 unnamed_device 13.1 MiB 0.01 92 51.7 MiB 0.01 0.00 1.13784 -16.052 -1.13784 1.13784 0.98 4.4392e-05 3.4118e-05 0.00178121 0.00140351 24 439 27 6.79088e+06 26944 470940. 1629.55 1.38 0.0120353 0.00985047 23374 113417 -1 284 15 188 207 11746 4028 0 0 11746 4028 207 198 0 0 789 676 0 0 1153 870 0 0 207 199 0 0 3946 1150 0 0 5444 935 0 0 207 0 0 19 9 12 285 0 0 1.13784 1.13784 -20.3983 -1.13784 0 0 586450. 2029.24 0.23 0.01 0.09 -1 -1 0.23 0.00242374 0.00212738 13 10 -1 -1 -1 -1 -fixed_k6_frac_N8_22nm.xml adder_008bits.v common 4.99 vpr 51.79 MiB -1 -1 0.09 16700 3 0.04 -1 -1 31300 -1 -1 2 17 0 0 success v8.0.0-7663-gb6a96700f release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-24T17:35:35 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_final/vtr-verilog-to-routing/vtr_flow/tasks 53028 17 9 56 65 1 43 28 17 17 289 -1 unnamed_device 13.2 MiB 0.04 275 51.8 MiB 0.01 0.00 1.27433 -22.6877 -1.27433 1.27433 0.95 4.8085e-05 3.6595e-05 0.00140482 0.00115519 34 541 11 6.79088e+06 26944 618332. 2139.56 2.35 0.0115091 0.00958495 25102 150614 -1 494 7 131 150 10447 2433 0 0 10447 2433 150 139 0 0 532 412 0 0 819 633 0 0 150 139 0 0 4463 583 0 0 4333 527 0 0 150 0 0 19 12 12 239 0 0 1.27433 1.27433 -26.572 -1.27433 0 0 787024. 2723.27 0.20 0.01 0.08 -1 -1 0.20 0.00142829 0.00129374 16 14 -1 -1 -1 -1 -fixed_k6_frac_N8_22nm.xml adder_009bits.v common 4.56 vpr 51.82 MiB -1 -1 0.10 16592 4 0.04 -1 -1 31380 -1 -1 3 19 0 0 success v8.0.0-7663-gb6a96700f release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-24T17:35:35 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_final/vtr-verilog-to-routing/vtr_flow/tasks 53068 19 10 60 70 1 49 32 17 17 289 -1 unnamed_device 13.1 MiB 0.05 313 51.8 MiB 0.01 0.00 1.1736 -26.515 -1.1736 1.1736 0.67 2.7979e-05 2.0948e-05 0.00125512 0.0010008 30 638 14 6.79088e+06 40416 556674. 1926.21 2.06 0.0160498 0.0131719 24526 138013 -1 557 9 159 168 13878 3020 0 0 13878 3020 168 160 0 0 600 475 0 0 752 625 0 0 168 161 0 0 6341 853 0 0 5849 746 0 0 168 0 0 9 9 10 214 0 0 1.1736 1.1736 -30.274 -1.1736 0 0 706193. 2443.58 0.29 0.01 0.12 -1 -1 0.29 0.00234745 0.00211119 17 13 -1 -1 -1 -1 -fixed_k6_frac_N8_22nm.xml adder_010bits.v common 4.59 vpr 51.90 MiB -1 -1 0.10 16560 4 0.05 -1 -1 31436 -1 -1 3 21 0 0 success v8.0.0-7663-gb6a96700f release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-24T17:35:35 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_final/vtr-verilog-to-routing/vtr_flow/tasks 53148 21 11 69 80 1 55 35 17 17 289 -1 unnamed_device 13.4 MiB 0.18 146 51.9 MiB 0.01 0.00 1.60338 -26.0076 -1.60338 1.60338 0.92 3.2925e-05 2.4646e-05 0.00270802 0.0021628 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31 0 0 success v8.0.0-7663-gb6a96700f release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-24T17:35:35 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_final/vtr-verilog-to-routing/vtr_flow/tasks 53364 31 16 104 120 1 82 52 17 17 289 -1 unnamed_device 13.5 MiB 0.46 242 52.1 MiB 0.03 0.00 2.14389 -43.0554 -2.14389 2.14389 0.71 8.5923e-05 6.8328e-05 0.00565233 0.00454864 38 796 21 6.79088e+06 67360 678818. 2348.85 3.38 0.0486361 0.0415709 25966 169698 -1 545 13 383 529 21129 6754 0 0 21129 6754 529 417 0 0 1745 1490 0 0 2762 1967 0 0 529 428 0 0 7002 1332 0 0 8562 1120 0 0 529 0 0 146 147 73 1255 0 0 2.14389 2.14389 -46.7752 -2.14389 0 0 902133. 3121.57 0.26 0.01 0.09 -1 -1 0.26 0.003129 0.00284008 31 27 -1 -1 -1 -1 -fixed_k6_frac_N8_22nm.xml adder_016bits.v common 5.99 vpr 52.10 MiB -1 -1 0.05 16732 7 0.06 -1 -1 31328 -1 -1 5 33 0 0 success v8.0.0-7663-gb6a96700f release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-24T17:35:35 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_final/vtr-verilog-to-routing/vtr_flow/tasks 53352 33 17 112 129 1 88 55 17 17 289 -1 unnamed_device 13.7 MiB 0.81 534 52.1 MiB 0.02 0.00 2.39454 -55.7365 -2.39454 2.39454 0.70 5.3996e-05 4.2168e-05 0.00354929 0.00295012 34 1164 20 6.79088e+06 67360 618332. 2139.56 2.46 0.0387727 0.0330849 25102 150614 -1 962 12 368 469 34965 7923 0 0 34965 7923 469 393 0 0 1662 1407 0 0 2663 1925 0 0 469 412 0 0 14758 1960 0 0 14944 1826 0 0 469 0 0 101 55 109 978 0 0 2.48064 2.48064 -63.9587 -2.48064 0 0 787024. 2723.27 0.32 0.02 0.13 -1 -1 0.32 0.00533234 0.0048458 32 30 -1 -1 -1 -1 -fixed_k6_frac_N8_22nm.xml adder_018bits.v common 7.44 vpr 52.21 MiB -1 -1 0.10 16748 7 0.06 -1 -1 31456 -1 -1 6 37 0 0 success v8.0.0-7663-gb6a96700f release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-24T17:35:35 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_final/vtr-verilog-to-routing/vtr_flow/tasks 53460 37 19 127 146 1 99 62 17 17 289 -1 unnamed_device 13.7 MiB 1.22 318 52.2 MiB 0.03 0.00 3.00001 -60.316 -3.00001 3.00001 0.95 0.000109241 8.6679e-05 0.00622408 0.00511708 36 970 48 6.79088e+06 80832 648988. 2245.63 3.18 0.0605658 0.0520732 25390 158009 -1 758 13 401 485 34946 9987 0 0 34946 9987 485 424 0 0 1790 1535 0 0 2781 2079 0 0 485 436 0 0 14434 2746 0 0 14971 2767 0 0 485 0 0 84 79 65 881 0 0 3.25061 3.25061 -70.2147 -3.25061 0 0 828058. 2865.25 0.31 0.02 0.14 -1 -1 0.31 0.00558963 0.00503143 37 35 -1 -1 -1 -1 -fixed_k6_frac_N8_22nm.xml adder_020bits.v common 4.42 vpr 52.19 MiB -1 -1 0.10 16564 8 0.06 -1 -1 31288 -1 -1 6 41 0 0 success v8.0.0-7663-gb6a96700f release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-24T17:35:35 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_final/vtr-verilog-to-routing/vtr_flow/tasks 53440 41 21 139 160 1 106 68 17 17 289 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x86_64 2023-04-24T17:35:35 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_final/vtr-verilog-to-routing/vtr_flow/tasks 53228 9 5 34 35 1 20 16 17 17 289 -1 unnamed_device 13.5 MiB 0.04 44 52.0 MiB 0.00 0.00 0.663773 -8.20792 -0.663773 0.663773 0.62 1.6322e-05 1.1844e-05 0.000557986 0.000440216 16 149 14 6.87369e+06 27947.7 332735. 1151.33 0.98 0.00557085 0.00439667 22306 75877 -1 116 19 140 140 5006 1848 0 0 5006 1848 140 140 0 0 476 376 0 0 603 481 0 0 140 140 0 0 1422 437 0 0 2225 274 0 0 140 0 0 0 0 0 140 0 0 1.03967 1.03967 -10.0874 -1.03967 0 0 414966. 1435.87 0.11 0.01 0.06 -1 -1 0.11 0.00122182 0.00102028 10 -1 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml adder_005bits.v common 3.75 vpr 51.93 MiB -1 -1 0.08 16204 1 0.01 -1 -1 29356 -1 -1 3 11 0 0 success v8.0.0-7663-gb6a96700f release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-24T17:35:35 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_final/vtr-verilog-to-routing/vtr_flow/tasks 53176 11 6 41 42 1 27 20 17 17 289 -1 unnamed_device 13.4 MiB 0.05 168 51.9 MiB 0.00 0.00 0.856592 -13.2218 -0.856592 0.856592 0.85 3.1166e-05 2.3248e-05 0.00042665 0.00035886 18 347 13 6.87369e+06 41921.5 376052. 1301.22 1.27 0.00648132 0.00528805 22882 88689 -1 308 7 84 84 6728 1668 0 0 6728 1668 84 84 0 0 344 275 0 0 457 369 0 0 84 84 0 0 2918 399 0 0 2841 457 0 0 84 0 0 0 0 0 84 0 0 1.06167 1.06167 -17.8579 -1.06167 0 0 470940. 1629.55 0.15 0.00 0.08 -1 -1 0.15 0.000810076 0.000716085 13 -1 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml adder_006bits.v common 4.96 vpr 52.06 MiB -1 -1 0.07 16456 1 0.00 -1 -1 29240 -1 -1 3 13 0 0 success v8.0.0-7663-gb6a96700f release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-24T17:35:35 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_final/vtr-verilog-to-routing/vtr_flow/tasks 53312 13 7 48 49 1 33 23 17 17 289 -1 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VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-24T17:35:35 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_final/vtr-verilog-to-routing/vtr_flow/tasks 53568 27 14 97 98 1 67 45 17 17 289 -1 unnamed_device 13.8 MiB 0.07 308 52.3 MiB 0.01 0.00 1.0198 -32.4993 -1.0198 1.0198 0.65 3.6731e-05 2.7693e-05 0.00184339 0.00144735 30 669 21 6.87369e+06 55895.4 556674. 1926.21 1.12 0.0144926 0.0118383 25186 138497 -1 616 12 254 254 16092 4130 0 0 16092 4130 254 254 0 0 900 752 0 0 1116 928 0 0 254 254 0 0 6028 1104 0 0 7540 838 0 0 254 0 0 0 0 0 254 0 0 1.01137 1.01137 -39.5837 -1.01137 0 0 706193. 2443.58 0.28 0.01 0.12 -1 -1 0.28 0.00318043 0.00282636 28 -1 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml adder_014bits.v common 5.62 vpr 52.36 MiB -1 -1 0.09 16544 1 0.00 -1 -1 29188 -1 -1 5 29 0 0 success v8.0.0-7663-gb6a96700f release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-24T17:35:35 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_final/vtr-verilog-to-routing/vtr_flow/tasks 53616 29 15 104 105 1 74 49 17 17 289 -1 unnamed_device 13.8 MiB 0.12 227 52.4 MiB 0.03 0.00 1.0308 -30.5404 -1.0308 1.0308 0.95 7.4618e-05 5.8329e-05 0.00477554 0.00378608 34 801 40 6.87369e+06 69869.2 618332. 2139.56 2.87 0.0315166 0.0259298 25762 151098 -1 583 19 452 452 38701 9999 0 0 38701 9999 452 452 0 0 1779 1555 0 0 2801 2203 0 0 452 452 0 0 15255 2899 0 0 17962 2438 0 0 452 0 0 0 0 0 452 0 0 1.18067 1.18067 -39.9512 -1.18067 0 0 787024. 2723.27 0.31 0.02 0.14 -1 -1 0.31 0.00438084 0.00378533 31 -1 -1 -1 -1 -1 -fixed_k6_frac_ripple_N8_22nm.xml adder_015bits.v common 4.11 vpr 51.70 MiB -1 -1 0.10 16380 1 0.00 -1 -1 29352 -1 -1 5 31 0 0 success v8.0.0-7663-gb6a96700f release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-24T17:35:35 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_final/vtr-verilog-to-routing/vtr_flow/tasks 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29380 -1 -1 3 21 0 0 success v8.0.0-7663-gb6a96700f release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-24T17:35:35 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_final/vtr-verilog-to-routing/vtr_flow/tasks 52704 21 11 76 77 1 48 35 17 17 289 -1 unnamed_device 12.8 MiB 0.07 144 51.5 MiB 0.02 0.00 0.986803 -22.178 -0.986803 0.986803 1.01 5.2501e-05 4.0404e-05 0.00270903 0.00215104 32 418 17 6.89349e+06 42281.5 586450. 2029.24 2.16 0.0186528 0.0152089 25474 144626 -1 349 13 230 230 18968 5032 0 0 18968 5032 230 230 0 0 922 772 0 0 1346 1091 0 0 230 230 0 0 8080 1334 0 0 8160 1375 0 0 230 0 0 0 0 0 230 0 0 1.25097 1.25097 -29.8957 -1.25097 0 0 744469. 2576.02 0.30 0.01 0.13 -1 -1 0.30 0.00259953 0.00227091 22 -1 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml adder_011bits.v common 3.97 vpr 51.45 MiB -1 -1 0.09 16272 1 0.01 -1 -1 29300 -1 -1 4 23 0 0 success v8.0.0-7663-gb6a96700f release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on 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/home/mahmo494/Desktop/RLplace_final/vtr-verilog-to-routing/vtr_flow/tasks 52848 25 13 90 91 1 60 42 17 17 289 -1 unnamed_device 12.8 MiB 0.06 190 51.6 MiB 0.01 0.00 1.0088 -26.851 -1.0088 1.0088 0.60 3.4868e-05 2.5816e-05 0.0021322 0.00162464 30 563 22 6.89349e+06 56375.4 556674. 1926.21 1.80 0.0169151 0.0137322 25186 138497 -1 439 15 294 294 18101 5027 0 0 18101 5027 294 294 0 0 1088 905 0 0 1455 1212 0 0 294 294 0 0 7836 1065 0 0 7134 1257 0 0 294 0 0 0 0 0 294 0 0 1.16967 1.16967 -34.9552 -1.16967 0 0 706193. 2443.58 0.19 0.01 0.07 -1 -1 0.19 0.0020782 0.00181354 26 -1 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml adder_013bits.v common 5.20 vpr 51.61 MiB -1 -1 0.10 16440 1 0.01 -1 -1 29172 -1 -1 4 27 0 0 success v8.0.0-7663-gb6a96700f release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-24T17:35:35 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_final/vtr-verilog-to-routing/vtr_flow/tasks 52848 27 14 97 98 1 67 45 17 17 289 -1 unnamed_device 13.1 MiB 0.08 271 51.6 MiB 0.02 0.00 1.0198 -31.143 -1.0198 1.0198 1.00 6.742e-05 5.2626e-05 0.00277153 0.00224251 26 683 13 6.89349e+06 56375.4 503264. 1741.40 2.04 0.0229235 0.019203 24322 120374 -1 652 13 347 347 32206 8270 0 0 32206 8270 347 347 0 0 1533 1324 0 0 2418 2042 0 0 347 347 0 0 12948 2200 0 0 14613 2010 0 0 347 0 0 0 0 0 347 0 0 1.05732 1.05732 -40.3169 -1.05732 0 0 618332. 2139.56 0.26 0.02 0.10 -1 -1 0.26 0.00327299 0.00289003 28 -1 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml adder_014bits.v common 4.38 vpr 51.54 MiB -1 -1 0.10 16456 1 0.01 -1 -1 29252 -1 -1 5 29 0 0 success v8.0.0-7663-gb6a96700f release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-24T17:35:35 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_final/vtr-verilog-to-routing/vtr_flow/tasks 52776 29 15 104 105 1 74 49 17 17 289 -1 unnamed_device 13.0 MiB 0.07 228 51.5 MiB 0.01 0.00 1.0308 -31.5428 -1.0308 1.0308 0.61 4.2478e-05 3.1947e-05 0.00288642 0.0022669 36 661 12 6.89349e+06 70469.2 648988. 2245.63 1.93 0.019055 0.0155251 26050 158493 -1 565 22 495 495 42358 11128 0 0 42358 11128 495 495 0 0 1881 1581 0 0 2972 2378 0 0 495 495 0 0 17045 3253 0 0 19470 2926 0 0 495 0 0 0 0 0 495 0 0 1.08562 1.08562 -38.2351 -1.08562 0 0 828058. 2865.25 0.33 0.02 0.14 -1 -1 0.33 0.00479964 0.00411935 31 -1 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml adder_015bits.v common 3.95 vpr 51.65 MiB -1 -1 0.10 16508 1 0.00 -1 -1 29192 -1 -1 5 31 0 0 success v8.0.0-7663-gb6a96700f release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-24T17:35:35 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_final/vtr-verilog-to-routing/vtr_flow/tasks 52892 31 16 111 112 1 80 52 17 17 289 -1 unnamed_device 13.1 MiB 0.14 290 51.7 MiB 0.03 0.00 1.27683 -33.446 -1.27683 1.27683 0.98 7.7556e-05 6.038e-05 0.00473053 0.00379487 30 697 16 6.89349e+06 70469.2 556674. 1926.21 0.69 0.0145141 0.0120391 25186 138497 -1 542 11 345 345 18507 5274 0 0 18507 5274 345 345 0 0 1250 1016 0 0 1600 1364 0 0 345 345 0 0 7876 1048 0 0 7091 1156 0 0 345 0 0 0 0 0 345 0 0 0.97402 0.97402 -39.2208 -0.97402 0 0 706193. 2443.58 0.29 0.01 0.12 -1 -1 0.29 0.00328005 0.00291293 33 -1 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml adder_016bits.v common 4.05 vpr 51.69 MiB -1 -1 0.12 16512 1 0.01 -1 -1 29192 -1 -1 5 33 0 0 success v8.0.0-7663-gb6a96700f release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-24T17:35:35 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_final/vtr-verilog-to-routing/vtr_flow/tasks 52928 33 17 118 119 1 83 55 17 17 289 -1 unnamed_device 13.1 MiB 0.12 305 51.7 MiB 0.03 0.00 1.28783 -37.1498 -1.28783 1.28783 0.98 8.2832e-05 6.4488e-05 0.00493121 0.00396236 30 827 25 6.89349e+06 70469.2 556674. 1926.21 0.82 0.0196534 0.01631 25186 138497 -1 620 13 382 382 27279 7187 0 0 27279 7187 382 382 0 0 1464 1232 0 0 1875 1606 0 0 382 382 0 0 12243 1723 0 0 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v8.0.0-7663-gb6a96700f release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-24T17:35:35 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_final/vtr-verilog-to-routing/vtr_flow/tasks 53092 49 25 174 175 1 124 81 17 17 289 -1 unnamed_device 13.3 MiB 0.12 568 51.8 MiB 0.04 0.00 1.61086 -62.0353 -1.61086 1.61086 1.00 0.000127018 0.000102593 0.00694067 0.00568239 36 1398 28 6.89349e+06 98656.9 648988. 2245.63 3.71 0.060387 0.0514879 26050 158493 -1 1138 13 555 555 43570 11213 0 0 43570 11213 555 555 0 0 2086 1708 0 0 2896 2391 0 0 555 555 0 0 18741 2763 0 0 18737 3241 0 0 555 0 0 0 0 0 555 0 0 1.34167 1.34167 -75.7577 -1.34167 0 0 828058. 2865.25 0.28 0.02 0.14 -1 -1 0.28 0.00365783 0.00325636 50 -1 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml adder_028bits.v common 6.57 vpr 52.16 MiB -1 -1 0.09 16580 1 0.01 -1 -1 29276 -1 -1 8 57 0 0 success v8.0.0-7663-gb6a96700f release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-24T17:35:35 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_final/vtr-verilog-to-routing/vtr_flow/tasks 53416 57 29 202 203 1 143 94 17 17 289 -1 unnamed_device 13.6 MiB 0.12 726 52.2 MiB 0.04 0.00 1.65486 -75.3659 -1.65486 1.65486 1.01 0.000142048 0.000114705 0.0051345 0.00424051 36 1545 20 6.89349e+06 112751 648988. 2245.63 3.21 0.0547218 0.0472415 26050 158493 -1 1371 17 646 646 67977 14978 0 0 67977 14978 646 646 0 0 2381 1962 0 0 3833 3041 0 0 646 646 0 0 29060 4699 0 0 31411 3984 0 0 646 0 0 0 0 0 646 0 0 1.27767 1.27767 -84.0909 -1.27767 0 0 828058. 2865.25 0.31 0.03 0.14 -1 -1 0.31 0.00763345 0.00672937 58 -1 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml adder_032bits.v common 3.15 vpr 52.21 MiB -1 -1 0.13 16764 1 0.01 -1 -1 29400 -1 -1 9 65 0 0 success v8.0.0-7663-gb6a96700f release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-24T17:35:35 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_final/vtr-verilog-to-routing/vtr_flow/tasks 53468 65 33 230 231 1 165 107 17 17 289 -1 unnamed_device 13.6 MiB 0.08 1037 52.2 MiB 0.05 0.00 1.93389 -96.5219 -1.93389 1.93389 0.60 9.7529e-05 7.8952e-05 0.00804384 0.00662507 34 2062 15 6.89349e+06 126845 618332. 2139.56 0.83 0.03408 0.0289981 25762 151098 -1 1894 16 749 749 76949 16585 0 0 76949 16585 749 749 0 0 2948 2404 0 0 4237 3435 0 0 749 749 0 0 35211 4644 0 0 33055 4604 0 0 749 0 0 0 0 0 749 0 0 1.43867 1.43867 -108.822 -1.43867 0 0 787024. 2723.27 0.20 0.02 0.08 -1 -1 0.20 0.00545182 0.00487487 66 -1 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml adder_048bits.v common 4.77 vpr 53.02 MiB -1 -1 0.12 16932 1 0.01 -1 -1 29572 -1 -1 13 97 0 0 success v8.0.0-7663-gb6a96700f release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-24T17:35:35 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_final/vtr-verilog-to-routing/vtr_flow/tasks 54288 97 49 342 343 1 247 159 17 17 289 -1 unnamed_device 14.2 MiB 0.14 1521 53.0 MiB 0.16 0.00 2.57995 -156.332 -2.57995 2.57995 0.97 0.00027293 0.000229277 0.0237117 0.0200695 34 2988 21 6.89349e+06 183220 618332. 2139.56 1.30 0.0883928 0.0769443 25762 151098 -1 2708 18 1174 1174 103455 23495 0 0 103455 23495 1174 1174 0 0 4506 3714 0 0 6900 5440 0 0 1174 1174 0 0 45797 5866 0 0 43904 6127 0 0 1174 0 0 0 0 0 1174 0 0 1.54037 1.54037 -159.774 -1.54037 0 0 787024. 2723.27 0.29 0.05 0.10 -1 -1 0.29 0.014465 0.0129392 98 -1 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml adder_064bits.v common 6.08 vpr 53.78 MiB -1 -1 0.15 17048 1 0.01 -1 -1 29780 -1 -1 17 129 0 0 success v8.0.0-7663-gb6a96700f release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-24T17:35:35 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_final/vtr-verilog-to-routing/vtr_flow/tasks 55068 129 65 454 455 1 329 211 17 17 289 -1 unnamed_device 14.9 MiB 0.14 2007 53.8 MiB 0.23 0.00 3.22602 -228.735 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device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops crit_path_total_internal_heap_pushes crit_path_total_internal_heap_pops crit_path_total_external_heap_pushes crit_path_total_external_heap_pops crit_path_total_external_SOURCE_pushes crit_path_total_external_SOURCE_pops crit_path_total_internal_SOURCE_pushes crit_path_total_internal_SOURCE_pops crit_path_total_external_SINK_pushes crit_path_total_external_SINK_pops crit_path_total_internal_SINK_pushes crit_path_total_internal_SINK_pops crit_path_total_external_IPIN_pushes crit_path_total_external_IPIN_pops crit_path_total_internal_IPIN_pushes crit_path_total_internal_IPIN_pops crit_path_total_external_OPIN_pushes crit_path_total_external_OPIN_pops crit_path_total_internal_OPIN_pushes crit_path_total_internal_OPIN_pops crit_path_total_external_CHANX_pushes crit_path_total_external_CHANX_pops crit_path_total_internal_CHANX_pushes crit_path_total_internal_CHANX_pops crit_path_total_external_CHANY_pushes crit_path_total_external_CHANY_pops crit_path_total_internal_CHANY_pushes crit_path_total_internal_CHANY_pops crit_path_rt_node_SOURCE_pushes crit_path_rt_node_SINK_pushes crit_path_rt_node_IPIN_pushes crit_path_rt_node_OPIN_pushes crit_path_rt_node_CHANX_pushes crit_path_rt_node_CHANY_pushes crit_path_adding_all_rt crit_path_adding_high_fanout_rt crit_path_total_number_of_adding_all_rt_from_calling_high_fanout_rt critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_003bits.v common 2.50 vpr 61.55 MiB -1 -1 0.06 20088 1 0.03 -1 -1 35244 -1 -1 2 7 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 63024 7 4 21 25 1 15 13 17 17 289 -1 unnamed_device 23.2 MiB 0.00 55 61.5 MiB 0.00 0.00 0.581048 -5.66613 -0.581048 0.581048 0.69 1.4315e-05 9.705e-06 0.000468601 0.00035802 22 122 4 6.55708e+06 24110 420624. 1455.45 0.42 0.00231112 0.00181759 20158 92377 -1 120 3 25 25 1518 477 0 0 1518 477 25 25 0 0 102 80 0 0 121 110 0 0 25 25 0 0 653 112 0 0 592 125 0 0 25 0 0 0 0 0 25 0 0 0.71851 0.71851 -7.79053 -0.71851 0 0 500653. 1732.36 0.17 0.00 0.06 -1 -1 0.17 0.000381608 0.000338832 10 4 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_004bits.v common 2.79 vpr 61.42 MiB -1 -1 0.06 20060 2 0.04 -1 -1 34892 -1 -1 2 9 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 62892 9 5 28 33 1 21 16 17 17 289 -1 unnamed_device 23.0 MiB 0.01 135 61.4 MiB 0.00 0.00 0.819447 -9.91401 -0.819447 0.819447 0.77 1.6854e-05 1.1896e-05 0.000457886 0.000380645 20 237 7 6.55708e+06 24110 394039. 1363.46 0.38 0.00122463 0.00104305 19870 87366 -1 231 9 77 78 5534 1447 0 0 5534 1447 78 77 0 0 338 284 0 0 402 358 0 0 78 78 0 0 2379 349 0 0 2259 301 0 0 78 0 0 1 1 0 82 0 0 0.819447 0.819447 -11.9182 -0.819447 0 0 477104. 1650.88 0.16 0.00 0.05 -1 -1 0.16 0.000708773 0.000617175 13 6 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_005bits.v common 3.06 vpr 61.61 MiB -1 -1 0.07 19892 2 0.04 -1 -1 35008 -1 -1 2 11 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 63088 11 6 34 40 1 24 19 17 17 289 -1 unnamed_device 23.2 MiB 0.01 60 61.6 MiB 0.00 0.00 0.819447 -9.14504 -0.819447 0.819447 0.86 2.2575e-05 1.6691e-05 0.000752375 0.000578518 26 173 11 6.55708e+06 24110 477104. 1650.88 0.59 0.00390233 0.00310741 21022 109990 -1 150 7 73 77 3320 1212 0 0 3320 1212 77 74 0 0 281 224 0 0 400 337 0 0 77 77 0 0 1376 235 0 0 1109 265 0 0 77 0 0 4 4 0 93 0 0 0.821448 0.821448 -12.8712 -0.821448 0 0 585099. 2024.56 0.21 0.00 0.07 -1 -1 0.21 0.000844167 0.000746601 16 7 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_006bits.v common 3.94 vpr 61.72 MiB -1 -1 0.07 19824 3 0.03 -1 -1 35424 -1 -1 3 13 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 63204 13 7 41 48 1 32 23 17 17 289 -1 unnamed_device 23.2 MiB 0.01 111 61.7 MiB 0.01 0.00 1.50711 -14.1678 -1.50711 1.50711 0.76 2.6936e-05 2.0026e-05 0.000894816 0.000710741 26 279 12 6.55708e+06 36165 477104. 1650.88 1.53 0.00862662 0.00698278 21022 109990 -1 250 8 103 131 8867 2344 0 0 8867 2344 131 122 0 0 488 400 0 0 705 568 0 0 131 131 0 0 3331 638 0 0 4081 485 0 0 131 0 0 28 21 7 243 0 0 1.50711 1.50711 -17.4132 -1.50711 0 0 585099. 2024.56 0.20 0.00 0.07 -1 -1 0.20 0.00105267 0.000936601 19 9 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_007bits.v common 4.59 vpr 61.66 MiB -1 -1 0.07 19956 3 0.04 -1 -1 35480 -1 -1 3 15 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 63136 15 8 47 55 1 38 26 17 17 289 -1 unnamed_device 23.1 MiB 0.01 97 61.7 MiB 0.01 0.00 1.05785 -13.991 -1.05785 1.05785 0.75 2.8898e-05 2.1655e-05 0.00099176 0.000788272 26 349 21 6.55708e+06 36165 477104. 1650.88 2.06 0.0100615 0.00814744 21022 109990 -1 344 13 190 216 11678 3837 0 0 11678 3837 216 197 0 0 859 701 0 0 1313 1081 0 0 216 199 0 0 4111 867 0 0 4963 792 0 0 216 0 0 26 24 7 325 0 0 1.05785 1.05785 -20.1212 -1.05785 0 0 585099. 2024.56 0.37 0.01 0.07 -1 -1 0.37 0.0015175 0.00131536 23 10 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_008bits.v common 4.34 vpr 61.95 MiB -1 -1 0.08 19736 3 0.03 -1 -1 35192 -1 -1 4 17 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 63432 17 9 56 65 1 42 30 17 17 289 -1 unnamed_device 23.3 MiB 0.06 259 61.9 MiB 0.01 0.00 1.46791 -20.75 -1.46791 1.46791 0.76 3.5634e-05 2.7693e-05 0.00125439 0.00102946 26 483 17 6.55708e+06 48220 477104. 1650.88 1.88 0.0146136 0.0120219 21022 109990 -1 438 20 142 155 10559 2616 0 0 10559 2616 155 151 0 0 593 461 0 0 810 681 0 0 155 152 0 0 4949 514 0 0 3897 657 0 0 155 0 0 13 10 4 208 0 0 1.58811 1.58811 -25.3176 -1.58811 0 0 585099. 2024.56 0.21 0.01 0.07 -1 -1 0.21 0.00233355 0.00203733 25 14 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_009bits.v common 4.36 vpr 61.82 MiB -1 -1 0.08 19848 4 0.03 -1 -1 35192 -1 -1 4 19 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 63304 19 10 60 70 1 48 33 17 17 289 -1 unnamed_device 23.2 MiB 0.01 175 61.8 MiB 0.01 0.00 1.50711 -21.3868 -1.50711 1.50711 0.74 3.7691e-05 2.8558e-05 0.00229382 0.00181713 28 420 14 6.55708e+06 48220 500653. 1732.36 2.02 0.0122307 0.0101465 21310 115450 -1 380 11 159 186 9586 2818 0 0 9586 2818 186 165 0 0 707 539 0 0 964 784 0 0 186 175 0 0 3641 622 0 0 3902 533 0 0 186 0 0 27 16 25 320 0 0 1.50711 1.50711 -25.5938 -1.50711 0 0 612192. 2118.31 0.22 0.01 0.07 -1 -1 0.22 0.00177795 0.00158373 29 13 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_010bits.v common 4.75 vpr 61.95 MiB -1 -1 0.07 20084 4 0.04 -1 -1 35504 -1 -1 5 21 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 63440 21 11 69 80 1 53 37 17 17 289 -1 unnamed_device 23.6 MiB 0.02 200 62.0 MiB 0.01 0.00 1.46791 -23.299 -1.46791 1.46791 0.76 4.4863e-05 3.5164e-05 0.00193329 0.00162216 30 511 15 6.55708e+06 60275 526063. 1820.29 2.00 0.0164129 0.0136648 21886 126133 -1 433 13 170 223 12926 3564 0 0 12926 3564 223 180 0 0 853 660 0 0 1225 1037 0 0 223 203 0 0 4942 807 0 0 5460 677 0 0 223 0 0 53 49 9 456 0 0 1.46791 1.46791 -28.5878 -1.46791 0 0 666494. 2306.21 0.44 0.01 0.08 -1 -1 0.44 0.00211555 0.00188011 33 17 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_011bits.v common 3.12 vpr 62.02 MiB -1 -1 0.07 19856 5 0.05 -1 -1 34940 -1 -1 6 23 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 63504 23 12 76 88 1 61 41 17 17 289 -1 unnamed_device 23.5 MiB 0.01 208 62.0 MiB 0.01 0.00 1.7455 -26.3998 -1.7455 1.7455 0.77 4.8941e-05 3.7713e-05 0.00223528 0.00178346 26 580 13 6.55708e+06 72330 477104. 1650.88 0.55 0.00984164 0.00819163 21022 109990 -1 511 11 279 368 21714 6243 0 0 21714 6243 368 304 0 0 1462 1210 0 0 2213 1773 0 0 368 328 0 0 8153 1372 0 0 9150 1256 0 0 368 0 0 89 42 103 822 0 0 1.74951 1.74951 -33.3714 -1.74951 0 0 585099. 2024.56 0.35 0.03 0.07 -1 -1 0.35 0.00237044 0.00211827 37 19 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_012bits.v common 3.08 vpr 61.91 MiB -1 -1 0.07 20080 5 0.03 -1 -1 35084 -1 -1 6 25 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 63392 25 13 83 96 1 66 44 17 17 289 -1 unnamed_device 23.4 MiB 0.01 261 61.9 MiB 0.01 0.00 1.53464 -29.3154 -1.53464 1.53464 0.79 5.2238e-05 4.0697e-05 0.00163465 0.00133534 26 696 14 6.55708e+06 72330 477104. 1650.88 0.53 0.00969162 0.0081243 21022 109990 -1 604 14 275 391 20940 5867 0 0 20940 5867 391 319 0 0 1504 1214 0 0 2317 1808 0 0 391 332 0 0 7782 1150 0 0 8555 1044 0 0 391 0 0 116 91 114 978 0 0 1.82851 1.82851 -37.8047 -1.82851 0 0 585099. 2024.56 0.21 0.01 0.07 -1 -1 0.21 0.00271879 0.00241745 40 21 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_013bits.v common 2.84 vpr 61.88 MiB -1 -1 0.07 20440 5 0.04 -1 -1 35240 -1 -1 7 27 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 63368 27 14 91 105 1 70 48 17 17 289 -1 unnamed_device 23.4 MiB 0.01 318 61.9 MiB 0.02 0.00 1.49544 -32.4063 -1.49544 1.49544 0.73 5.7993e-05 4.5293e-05 0.00386642 0.00310411 26 733 12 6.55708e+06 84385 477104. 1650.88 0.52 0.0121193 0.0101209 21022 109990 -1 661 11 259 370 22109 6201 0 0 22109 6201 370 307 0 0 1435 1137 0 0 2125 1691 0 0 370 327 0 0 9191 1361 0 0 8618 1378 0 0 370 0 0 111 113 110 1018 0 0 1.61765 1.61765 -40.4365 -1.61765 0 0 585099. 2024.56 0.24 0.01 0.07 -1 -1 0.24 0.00258623 0.00232211 42 24 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_014bits.v common 4.07 vpr 62.10 MiB -1 -1 0.08 20164 6 0.04 -1 -1 35160 -1 -1 7 29 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 63592 29 15 95 110 1 74 51 17 17 289 -1 unnamed_device 23.6 MiB 0.03 426 62.1 MiB 0.01 0.00 2.15556 -41.608 -2.15556 2.15556 0.74 6.4749e-05 5.2103e-05 0.00196204 0.00164986 26 873 10 6.55708e+06 84385 477104. 1650.88 1.61 0.0200598 0.0169424 21022 109990 -1 809 8 240 320 21917 5232 0 0 21917 5232 320 247 0 0 1200 923 0 0 1699 1365 0 0 320 259 0 0 9379 1232 0 0 8999 1206 0 0 320 0 0 80 81 108 797 0 0 2.2243 2.2243 -49.3842 -2.2243 0 0 585099. 2024.56 0.26 0.01 0.07 -1 -1 0.26 0.00234489 0.00212828 45 23 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_015bits.v common 4.81 vpr 62.27 MiB -1 -1 0.08 20128 6 0.04 -1 -1 35288 -1 -1 10 31 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 63768 31 16 104 120 1 81 57 17 17 289 -1 unnamed_device 23.6 MiB 0.03 369 62.3 MiB 0.02 0.00 1.73384 -38.7759 -1.73384 1.73384 0.77 7.0185e-05 5.4585e-05 0.00330473 0.00266585 28 932 12 6.55708e+06 120550 500653. 1732.36 2.06 0.0206288 0.0173385 21310 115450 -1 835 12 345 513 31086 8016 0 0 31086 8016 513 387 0 0 1876 1430 0 0 2901 2305 0 0 513 417 0 0 12440 1806 0 0 12843 1671 0 0 513 0 0 168 164 175 1508 0 0 1.9467 1.9467 -47.3101 -1.9467 0 0 612192. 2118.31 0.25 0.01 0.08 -1 -1 0.25 0.00320021 0.00287124 50 27 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_016bits.v common 3.93 vpr 62.23 MiB -1 -1 0.08 20396 7 0.05 -1 -1 35292 -1 -1 7 33 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 63724 33 17 112 129 1 86 57 17 17 289 -1 unnamed_device 23.9 MiB 0.04 294 62.2 MiB 0.01 0.00 2.2223 -42.4636 -2.2223 2.2223 0.90 7.0214e-05 5.6131e-05 0.0026666 0.00220712 26 887 13 6.55708e+06 84385 477104. 1650.88 1.37 0.0257412 0.0218466 21022 109990 -1 716 13 316 421 24690 7048 0 0 24690 7048 421 338 0 0 1622 1247 0 0 2512 2049 0 0 421 365 0 0 9043 1655 0 0 10671 1394 0 0 421 0 0 105 108 18 888 0 0 2.3425 2.3425 -52.4402 -2.3425 0 0 585099. 2024.56 0.21 0.01 0.07 -1 -1 0.21 0.00341644 0.00306632 52 30 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_018bits.v common 4.04 vpr 62.42 MiB -1 -1 0.07 20328 7 0.04 -1 -1 35668 -1 -1 10 37 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 63920 37 19 127 146 1 99 66 17 17 289 -1 unnamed_device 23.9 MiB 0.02 498 62.4 MiB 0.03 0.00 2.75256 -61.0465 -2.75256 2.75256 0.74 8.8182e-05 7.1624e-05 0.00539847 0.00447629 26 1107 10 6.55708e+06 120550 477104. 1650.88 1.63 0.0480834 0.0385398 21022 109990 -1 1023 12 364 491 32777 8641 0 0 32777 8641 491 409 0 0 1923 1539 0 0 2940 2337 0 0 491 426 0 0 13551 1890 0 0 13381 2040 0 0 491 0 0 127 96 137 1173 0 0 2.87276 2.87276 -70.9029 -2.87276 0 0 585099. 2024.56 0.22 0.01 0.08 -1 -1 0.22 0.00380307 0.00344027 59 35 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_020bits.v common 3.31 vpr 62.45 MiB -1 -1 0.08 20228 8 0.06 -1 -1 35224 -1 -1 11 41 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 63948 41 21 139 160 1 110 73 17 17 289 -1 unnamed_device 23.9 MiB 0.04 579 62.4 MiB 0.03 0.00 2.4215 -62.5706 -2.4215 2.4215 0.75 8.8023e-05 7.0954e-05 0.00595745 0.00490814 26 1454 49 6.55708e+06 132605 477104. 1650.88 0.71 0.0266792 0.0226773 21022 109990 -1 1201 13 485 653 50243 12652 0 0 50243 12652 653 544 0 0 2388 1852 0 0 3706 2817 0 0 653 562 0 0 21702 3405 0 0 21141 3472 0 0 653 0 0 168 112 142 1457 0 0 2.5417 2.5417 -74.9513 -2.5417 0 0 585099. 2024.56 0.23 0.02 0.11 -1 -1 0.23 0.00511676 0.00468097 67 37 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_022bits.v common 4.65 vpr 62.57 MiB -1 -1 0.08 20228 9 0.05 -1 -1 35296 -1 -1 13 45 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64076 45 23 153 176 1 123 81 17 17 289 -1 unnamed_device 24.1 MiB 0.21 537 62.6 MiB 0.03 0.00 2.78916 -69.2589 -2.78916 2.78916 0.74 9.8634e-05 7.9712e-05 0.00612327 0.00505691 28 1337 37 6.55708e+06 156715 500653. 1732.36 1.92 0.0481541 0.0413727 21310 115450 -1 1162 17 548 696 44008 12243 0 0 44008 12243 696 609 0 0 2596 2073 0 0 3912 3100 0 0 696 623 0 0 17765 2997 0 0 18343 2841 0 0 696 0 0 148 95 127 1362 0 0 3.02956 3.02956 -85.4859 -3.02956 0 0 612192. 2118.31 0.22 0.02 0.07 -1 -1 0.22 0.00588433 0.00527486 74 41 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_024bits.v common 4.88 vpr 62.43 MiB -1 -1 0.09 20040 10 0.04 -1 -1 35132 -1 -1 12 49 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 63924 49 25 166 191 1 129 86 17 17 289 -1 unnamed_device 23.9 MiB 0.06 710 62.4 MiB 0.03 0.00 3.51862 -88.1514 -3.51862 3.51862 0.91 0.000106692 8.674e-05 0.00634728 0.00528218 28 1501 12 6.55708e+06 144660 500653. 1732.36 1.97 0.034654 0.0299512 21310 115450 -1 1351 9 477 636 50722 12433 0 0 50722 12433 636 532 0 0 2453 1939 0 0 3570 2929 0 0 636 546 0 0 22916 3249 0 0 20511 3238 0 0 636 0 0 159 90 171 1418 0 0 3.63882 3.63882 -100.893 -3.63882 0 0 612192. 2118.31 0.24 0.02 0.09 -1 -1 0.24 0.00463865 0.00426312 79 44 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_028bits.v common 5.21 vpr 62.57 MiB -1 -1 0.09 20048 11 0.06 -1 -1 35452 -1 -1 14 57 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64076 57 29 198 227 1 159 100 17 17 289 -1 unnamed_device 24.1 MiB 0.17 896 62.6 MiB 0.05 0.00 3.76868 -108.384 -3.76868 3.76868 0.75 0.000137892 0.000115367 0.00954169 0.00801579 26 1981 32 6.55708e+06 168770 477104. 1650.88 2.30 0.065232 0.0566756 21022 109990 -1 1779 59 755 1063 416437 286231 0 0 416437 286231 1063 872 0 0 4109 3413 0 0 12197 7333 0 0 1063 895 0 0 196004 138244 0 0 202001 135474 0 0 1063 0 0 308 326 294 2651 0 0 3.95762 3.95762 -127.018 -3.95762 0 0 585099. 2024.56 0.36 0.12 0.07 -1 -1 0.36 0.0185493 0.0162813 93 56 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_032bits.v common 4.77 vpr 62.75 MiB -1 -1 0.09 20416 13 0.06 -1 -1 34900 -1 -1 16 65 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64256 65 33 224 257 1 180 114 17 17 289 -1 unnamed_device 24.2 MiB 0.22 1005 62.8 MiB 0.06 0.00 4.06216 -130.977 -4.06216 4.06216 0.75 0.000159749 0.000134247 0.0121674 0.0102394 28 2028 28 6.55708e+06 192880 500653. 1732.36 2.04 0.0641105 0.0557099 21310 115450 -1 1856 15 673 922 60285 14629 0 0 60285 14629 922 746 0 0 3315 2612 0 0 5132 3870 0 0 922 782 0 0 25938 3242 0 0 24056 3377 0 0 922 0 0 249 173 260 2136 0 0 4.42276 4.42276 -152.012 -4.42276 0 0 612192. 2118.31 0.23 0.02 0.07 -1 -1 0.23 0.00767389 0.00696098 107 62 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_048bits.v common 3.70 vpr 63.83 MiB -1 -1 0.11 20520 19 0.08 -1 -1 35488 -1 -1 24 97 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65364 97 49 340 389 1 266 170 17 17 289 -1 unnamed_device 25.1 MiB 0.19 1490 63.8 MiB 0.11 0.00 6.49539 -245.46 -6.49539 6.49539 0.76 0.000252414 0.000213901 0.0222849 0.0190447 30 3055 16 6.55708e+06 289320 526063. 1820.29 0.73 0.0636615 0.0559481 21886 126133 -1 2579 16 879 1264 71520 18401 0 0 71520 18401 1264 990 0 0 4405 3451 0 0 6172 4896 0 0 1264 1028 0 0 29362 3929 0 0 29053 4107 0 0 1264 0 0 385 267 467 3313 0 0 6.85599 6.85599 -274.19 -6.85599 0 0 666494. 2306.21 0.23 0.04 0.08 -1 -1 0.23 0.0131021 0.0120146 161 98 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml adder_064bits.v common 6.01 vpr 64.80 MiB -1 -1 0.14 20804 26 0.10 -1 -1 35632 -1 -1 35 129 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 66352 129 65 453 518 1 353 229 17 17 289 -1 unnamed_device 26.1 MiB 0.20 2092 64.8 MiB 0.16 0.00 8.91496 -417.828 -8.91496 8.91496 0.76 0.000371318 0.000323636 0.0313651 0.0274748 36 3997 12 6.55708e+06 421925 612192. 2118.31 2.85 0.163346 0.147082 22750 144809 -1 3614 12 1158 1601 114563 26993 0 0 114563 26993 1601 1256 0 0 6027 4760 0 0 9249 7302 0 0 1601 1320 0 0 49191 6207 0 0 46894 6148 0 0 1601 0 0 443 334 393 3741 0 0 9.39576 9.39576 -457.615 -9.39576 0 0 782063. 2706.10 0.31 0.04 0.12 -1 -1 0.31 0.0160592 0.0149228 213 131 -1 -1 -1 -1 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_003bits.v common 0.39 abc 32.12 MiB -1 -1 0.07 19808 1 0.01 -1 -1 32892 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 24268 7 4 24 25 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_004bits.v common 0.37 abc 32.28 MiB -1 -1 0.06 19976 1 0.00 -1 -1 33056 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 24016 9 5 30 31 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_005bits.v common 0.44 abc 32.15 MiB -1 -1 0.07 19780 1 0.01 -1 -1 32924 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 24104 11 6 36 37 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_006bits.v common 0.35 abc 32.20 MiB -1 -1 0.07 19804 1 0.01 -1 -1 32976 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 24004 13 7 42 43 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_007bits.v common 0.51 abc 32.18 MiB -1 -1 0.06 20124 1 0.01 -1 -1 32952 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 24268 15 8 49 50 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_008bits.v common 0.40 abc 32.29 MiB -1 -1 0.07 20192 1 0.01 -1 -1 33064 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 24264 17 9 55 56 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_009bits.v common 0.43 abc 32.21 MiB -1 -1 0.07 19768 1 0.01 -1 -1 32988 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 24112 19 10 61 62 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_010bits.v common 0.34 abc 32.16 MiB -1 -1 0.07 19908 1 0.00 -1 -1 32936 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 24048 21 11 67 68 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_011bits.v common 0.37 abc 32.27 MiB -1 -1 0.06 20040 1 0.01 -1 -1 33040 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 24196 23 12 74 75 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_012bits.v common 0.35 abc 32.30 MiB -1 -1 0.07 20020 1 0.00 -1 -1 33076 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 24224 25 13 80 81 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_013bits.v common 0.38 abc 31.94 MiB -1 -1 0.07 20132 1 0.01 -1 -1 32708 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 24328 27 14 86 87 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_014bits.v common 0.41 abc 32.35 MiB -1 -1 0.07 20088 1 0.00 -1 -1 33128 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 24284 29 15 92 93 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_015bits.v common 0.40 abc 32.14 MiB -1 -1 0.07 19948 1 0.01 -1 -1 32908 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 24304 31 16 99 100 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_016bits.v common 0.47 abc 32.29 MiB -1 -1 0.08 19944 1 0.00 -1 -1 33068 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 24144 33 17 105 106 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_018bits.v common 0.35 abc 32.26 MiB -1 -1 0.07 20304 1 0.01 -1 -1 33032 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 24544 37 19 117 118 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_020bits.v common 0.47 abc 32.02 MiB -1 -1 0.07 20320 1 0.00 -1 -1 32792 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 24448 41 21 130 131 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_022bits.v common 0.54 abc 32.18 MiB -1 -1 0.08 20344 1 0.01 -1 -1 32948 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 24332 45 23 142 143 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_024bits.v common 0.49 abc 32.23 MiB -1 -1 0.07 20120 1 0.01 -1 -1 33000 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 24592 49 25 155 156 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_028bits.v common 0.44 abc 32.38 MiB -1 -1 0.07 20044 1 0.01 -1 -1 33156 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 24608 57 29 180 181 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_032bits.v common 0.47 abc 32.43 MiB -1 -1 0.08 20316 1 0.01 -1 -1 33208 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 24464 65 33 205 206 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_048bits.v common 0.39 abc 32.40 MiB -1 -1 0.09 20704 1 0.01 -1 -1 33176 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 24872 97 49 305 306 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml adder_064bits.v common 0.43 abc 32.65 MiB -1 -1 0.09 20400 1 0.02 -1 -1 33432 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 24900 129 65 405 406 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_003bits.v common 0.37 abc 32.29 MiB -1 -1 0.06 19812 1 0.01 -1 -1 33060 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 23948 7 4 24 25 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_004bits.v common 0.53 abc 32.33 MiB -1 -1 0.07 20020 1 0.00 -1 -1 33104 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 23812 9 5 30 31 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_005bits.v common 0.37 abc 32.15 MiB -1 -1 0.07 19812 1 0.01 -1 -1 32920 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 23676 11 6 36 37 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_006bits.v common 0.39 abc 32.12 MiB -1 -1 0.07 19696 1 0.00 -1 -1 32888 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 23968 13 7 42 43 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_007bits.v common 0.54 abc 32.08 MiB -1 -1 0.07 19832 1 0.01 -1 -1 32848 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 23944 15 8 49 50 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_008bits.v common 0.41 abc 32.43 MiB -1 -1 0.08 19868 1 0.00 -1 -1 33208 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 23992 17 9 55 56 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_009bits.v common 0.33 abc 32.18 MiB -1 -1 0.06 20132 1 0.01 -1 -1 32948 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 24000 19 10 61 62 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_010bits.v common 0.43 abc 32.19 MiB -1 -1 0.07 19820 1 0.00 -1 -1 32960 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 23860 21 11 67 68 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_011bits.v common 0.51 abc 32.41 MiB -1 -1 0.07 19920 1 0.01 -1 -1 33184 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 24144 23 12 74 75 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_012bits.v common 0.47 abc 32.23 MiB -1 -1 0.07 19776 1 0.01 -1 -1 33000 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 24112 25 13 80 81 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_013bits.v common 0.46 abc 32.13 MiB -1 -1 0.08 20016 1 0.01 -1 -1 32904 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 23900 27 14 86 87 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_014bits.v common 0.34 abc 32.19 MiB -1 -1 0.07 20052 1 0.01 -1 -1 32964 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 23860 29 15 92 93 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_015bits.v common 0.46 abc 32.23 MiB -1 -1 0.08 19812 1 0.01 -1 -1 33008 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 24016 31 16 99 100 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_016bits.v common 0.47 abc 32.32 MiB -1 -1 0.07 19916 1 0.01 -1 -1 33096 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 24272 33 17 105 106 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_018bits.v common 0.46 abc 32.30 MiB -1 -1 0.07 19880 1 0.01 -1 -1 33080 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 24312 37 19 117 118 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_020bits.v common 0.41 abc 32.31 MiB -1 -1 0.08 20264 1 0.01 -1 -1 33088 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 23948 41 21 130 131 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_022bits.v common 0.52 abc 32.20 MiB -1 -1 0.08 20280 1 0.01 -1 -1 32968 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 23944 45 23 142 143 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_024bits.v common 0.52 abc 32.30 MiB -1 -1 0.06 20252 1 0.01 -1 -1 33072 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 24084 49 25 155 156 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_028bits.v common 0.42 abc 32.19 MiB -1 -1 0.07 20412 1 0.00 -1 -1 32960 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 24516 57 29 180 181 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_032bits.v common 0.31 abc 32.32 MiB -1 -1 0.08 20348 1 0.01 -1 -1 33096 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 24332 65 33 205 206 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_048bits.v common 0.38 abc 32.63 MiB -1 -1 0.09 20452 1 0.01 -1 -1 33412 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 24460 97 49 305 306 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml adder_064bits.v common 0.47 abc 32.64 MiB -1 -1 0.09 20572 1 0.02 -1 -1 33424 -1 -1 -1 -1 -1 -1 exited with return code 134 v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 25064 129 65 405 406 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_003bits.v common 4.07 vpr 62.00 MiB -1 -1 0.07 20004 1 0.00 -1 -1 33064 -1 -1 2 7 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 63492 7 4 27 28 1 14 13 17 17 289 -1 unnamed_device 23.6 MiB 0.01 34 62.0 MiB 0.00 0.00 0.649848 -5.97153 -0.649848 0.649848 1.49 1.6441e-05 1.1554e-05 0.000365921 0.000284627 18 97 8 6.64007e+06 25116 355633. 1230.56 0.48 0.00266071 0.00210682 20242 81429 -1 62 5 24 24 771 282 0 0 771 282 24 24 0 0 82 44 0 0 110 83 0 0 24 24 0 0 206 68 0 0 325 39 0 0 24 0 0 0 0 0 24 0 0 0.71851 0.71851 -6.45233 -0.71851 0 0 448715. 1552.65 0.24 0.00 0.07 -1 -1 0.24 0.000563262 0.000495706 10 -1 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_004bits.v common 5.08 vpr 62.38 MiB -1 -1 0.07 19688 1 0.00 -1 -1 32988 -1 -1 2 9 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 63880 9 5 34 35 1 20 16 17 17 289 -1 unnamed_device 23.9 MiB 0.01 46 62.4 MiB 0.00 0.00 0.671848 -7.32322 -0.671848 0.671848 1.24 1.7917e-05 1.2869e-05 0.000653716 0.000498631 26 120 22 6.64007e+06 25116 477104. 1650.88 1.60 0.0161437 0.0142834 21682 110474 -1 111 12 101 101 3954 1441 0 0 3954 1441 101 101 0 0 385 319 0 0 585 478 0 0 101 101 0 0 1293 269 0 0 1489 173 0 0 101 0 0 0 0 0 101 0 0 0.890248 0.890248 -9.21042 -0.890248 0 0 585099. 2024.56 0.33 0.01 0.09 -1 -1 0.33 0.000991696 0.000846905 13 -1 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_005bits.v common 3.66 vpr 61.94 MiB -1 -1 0.07 20020 1 0.01 -1 -1 32896 -1 -1 2 11 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 63428 11 6 41 42 1 26 19 17 17 289 -1 unnamed_device 23.5 MiB 0.01 58 61.9 MiB 0.00 0.00 0.682848 -9.22145 -0.682848 0.682848 1.02 2.2701e-05 1.6544e-05 0.00085201 0.000652036 26 211 29 6.64007e+06 25116 477104. 1650.88 0.84 0.0171047 0.0160691 21682 110474 -1 174 26 232 232 13871 4498 0 0 13871 4498 232 232 0 0 944 809 0 0 1528 1180 0 0 232 232 0 0 4998 1099 0 0 5937 946 0 0 232 0 0 0 0 0 232 0 0 1.02145 1.02145 -12.529 -1.02145 0 0 585099. 2024.56 0.32 0.01 0.10 -1 -1 0.32 0.00160998 0.00132224 16 -1 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_006bits.v common 3.06 vpr 62.11 MiB -1 -1 0.07 19884 1 0.01 -1 -1 32924 -1 -1 4 13 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 63596 13 7 48 49 1 32 24 17 17 289 -1 unnamed_device 23.5 MiB 0.01 78 62.1 MiB 0.00 0.00 0.704848 -10.9187 -0.704848 0.704848 0.89 2.5633e-05 1.9305e-05 0.000751681 0.000596515 26 279 27 6.64007e+06 50232 477104. 1650.88 0.53 0.00539609 0.00436895 21682 110474 -1 220 16 180 180 14507 4652 0 0 14507 4652 180 180 0 0 706 547 0 0 1079 853 0 0 180 180 0 0 5656 1464 0 0 6706 1428 0 0 180 0 0 0 0 0 180 0 0 1.06545 1.06545 -16.3277 -1.06545 0 0 585099. 2024.56 0.28 0.02 0.07 -1 -1 0.28 0.00146245 0.00124459 20 -1 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_007bits.v common 4.64 vpr 62.23 MiB -1 -1 0.07 20096 1 0.00 -1 -1 32880 -1 -1 3 15 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 63728 15 8 55 56 1 38 26 17 17 289 -1 unnamed_device 23.7 MiB 0.01 109 62.2 MiB 0.01 0.00 0.944958 -13.5599 -0.944958 0.944958 0.75 2.6962e-05 1.9922e-05 0.00113682 0.000895722 32 232 11 6.64007e+06 37674 554710. 1919.41 2.16 0.00794336 0.00642038 22834 132086 -1 230 9 125 125 6580 1940 0 0 6580 1940 125 125 0 0 455 360 0 0 641 520 0 0 125 125 0 0 2537 422 0 0 2697 388 0 0 125 0 0 0 0 0 125 0 0 0.834048 0.834048 -16.5924 -0.834048 0 0 701300. 2426.64 0.27 0.00 0.10 -1 -1 0.27 0.00127474 0.00112686 22 -1 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_008bits.v common 4.10 vpr 62.17 MiB -1 -1 0.07 20024 1 0.00 -1 -1 32992 -1 -1 4 17 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 63660 17 9 62 63 1 41 30 17 17 289 -1 unnamed_device 23.5 MiB 0.04 125 62.2 MiB 0.01 0.00 0.955958 -15.7312 -0.955958 0.955958 0.81 3.2344e-05 2.4425e-05 0.00159967 0.00125043 28 334 11 6.64007e+06 50232 500653. 1732.36 1.53 0.0116894 0.00943068 21970 115934 -1 292 14 175 175 10074 3120 0 0 10074 3120 175 175 0 0 725 618 0 0 1012 865 0 0 175 175 0 0 3410 737 0 0 4577 550 0 0 175 0 0 0 0 0 175 0 0 0.943248 0.943248 -20.6052 -0.943248 0 0 612192. 2118.31 0.23 0.01 0.07 -1 -1 0.23 0.00168505 0.00146175 25 -1 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_009bits.v common 3.40 vpr 62.19 MiB -1 -1 0.08 19944 1 0.00 -1 -1 32888 -1 -1 4 19 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 63680 19 10 69 70 1 44 33 17 17 289 -1 unnamed_device 23.8 MiB 0.02 130 62.2 MiB 0.01 0.00 0.966958 -18.0338 -0.966958 0.966958 0.91 3.5677e-05 2.7166e-05 0.00139986 0.00111003 26 376 20 6.64007e+06 50232 477104. 1650.88 0.56 0.00739945 0.00604275 21682 110474 -1 325 13 180 180 10068 2780 0 0 10068 2780 180 180 0 0 661 493 0 0 870 698 0 0 180 180 0 0 3768 684 0 0 4409 545 0 0 180 0 0 0 0 0 180 0 0 1.09645 1.09645 -23.7262 -1.09645 0 0 585099. 2024.56 0.21 0.01 0.07 -1 -1 0.21 0.00171788 0.00149496 28 -1 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_010bits.v common 4.04 vpr 62.34 MiB -1 -1 0.07 19864 1 0.01 -1 -1 33124 -1 -1 5 21 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 63840 21 11 76 77 1 49 37 17 17 289 -1 unnamed_device 23.9 MiB 0.02 149 62.3 MiB 0.01 0.00 0.977958 -19.6261 -0.977958 0.977958 0.75 3.8141e-05 2.9107e-05 0.00159859 0.00127888 28 393 11 6.64007e+06 62790 500653. 1732.36 1.75 0.0202842 0.0178116 21970 115934 -1 379 14 262 262 20258 6291 0 0 20258 6291 262 262 0 0 1040 884 0 0 1421 1201 0 0 262 262 0 0 7880 1978 0 0 9393 1704 0 0 262 0 0 0 0 0 262 0 0 0.998248 0.998248 -26.8613 -0.998248 0 0 612192. 2118.31 0.23 0.01 0.07 -1 -1 0.23 0.00207764 0.00181124 31 -1 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_011bits.v common 3.05 vpr 62.27 MiB -1 -1 0.07 19872 1 0.01 -1 -1 32920 -1 -1 5 23 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 63764 23 12 83 84 1 55 40 17 17 289 -1 unnamed_device 23.8 MiB 0.02 183 62.3 MiB 0.01 0.00 0.988958 -22.3112 -0.988958 0.988958 0.74 4.1749e-05 3.1571e-05 0.0022251 0.00174344 28 435 15 6.64007e+06 62790 500653. 1732.36 0.61 0.00888342 0.00732586 21970 115934 -1 380 21 314 314 18524 5394 0 0 18524 5394 314 314 0 0 1173 902 0 0 1689 1355 0 0 314 314 0 0 6697 1400 0 0 8337 1109 0 0 314 0 0 0 0 0 314 0 0 1.02145 1.02145 -27.3237 -1.02145 0 0 612192. 2118.31 0.25 0.01 0.07 -1 -1 0.25 0.00259909 0.00224677 34 -1 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_012bits.v common 4.28 vpr 62.33 MiB -1 -1 0.08 20152 1 0.01 -1 -1 33080 -1 -1 5 25 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 63824 25 13 90 91 1 61 43 17 17 289 -1 unnamed_device 23.9 MiB 0.02 222 62.3 MiB 0.02 0.00 0.999958 -25.0074 -0.999958 0.999958 0.82 4.6142e-05 3.5519e-05 0.00269434 0.00215559 28 561 16 6.64007e+06 62790 500653. 1732.36 1.63 0.0220038 0.0188386 21970 115934 -1 491 11 255 255 19661 5101 0 0 19661 5101 255 255 0 0 1027 832 0 0 1343 1143 0 0 255 255 0 0 8066 1422 0 0 8715 1194 0 0 255 0 0 0 0 0 255 0 0 1.15145 1.15145 -33.2485 -1.15145 0 0 612192. 2118.31 0.40 0.01 0.07 -1 -1 0.40 0.00201505 0.00177679 37 -1 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_013bits.v common 3.37 vpr 62.34 MiB -1 -1 0.07 20048 1 0.01 -1 -1 33156 -1 -1 6 27 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 63832 27 14 97 98 1 67 47 17 17 289 -1 unnamed_device 23.8 MiB 0.02 203 62.3 MiB 0.02 0.00 1.01096 -26.5125 -1.01096 1.01096 0.83 4.9366e-05 3.7938e-05 0.00263216 0.00210475 28 633 24 6.64007e+06 75348 500653. 1732.36 0.61 0.0116219 0.00961623 21970 115934 -1 570 23 420 420 33504 9138 0 0 33504 9138 420 420 0 0 1633 1330 0 0 2308 1897 0 0 420 420 0 0 13267 2710 0 0 15456 2361 0 0 420 0 0 0 0 0 420 0 0 1.17465 1.17465 -36.1815 -1.17465 0 0 612192. 2118.31 0.21 0.01 0.07 -1 -1 0.21 0.00341635 0.00293719 40 -1 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_014bits.v common 4.15 vpr 62.64 MiB -1 -1 0.07 20132 1 0.01 -1 -1 33048 -1 -1 7 29 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64144 29 15 104 105 1 73 51 17 17 289 -1 unnamed_device 24.1 MiB 0.02 264 62.6 MiB 0.02 0.00 1.02196 -28.6296 -1.02196 1.02196 0.74 5.3687e-05 4.1661e-05 0.00317455 0.00253243 30 642 18 6.64007e+06 87906 526063. 1820.29 1.67 0.0255025 0.0219875 22546 126617 -1 475 11 253 253 12493 3725 0 0 12493 3725 253 253 0 0 901 741 0 0 1129 943 0 0 253 253 0 0 5019 782 0 0 4938 753 0 0 253 0 0 0 0 0 253 0 0 0.956248 0.956248 -33.521 -0.956248 0 0 666494. 2306.21 0.30 0.01 0.08 -1 -1 0.30 0.0022962 0.00203459 44 -1 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_015bits.v common 4.15 vpr 62.50 MiB -1 -1 0.07 20512 1 0.01 -1 -1 32724 -1 -1 7 31 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64000 31 16 111 112 1 79 54 17 17 289 -1 unnamed_device 23.9 MiB 0.03 288 62.5 MiB 0.02 0.00 1.26207 -31.7081 -1.26207 1.26207 0.74 5.8486e-05 4.5753e-05 0.00298297 0.00240088 28 665 12 6.64007e+06 87906 500653. 1732.36 1.70 0.0231936 0.0193728 21970 115934 -1 640 14 385 385 28824 7516 0 0 28824 7516 385 385 0 0 1452 1196 0 0 2008 1605 0 0 385 385 0 0 12026 2099 0 0 12568 1846 0 0 385 0 0 0 0 0 385 0 0 1.08425 1.08425 -39.9542 -1.08425 0 0 612192. 2118.31 0.24 0.01 0.07 -1 -1 0.24 0.00298908 0.00264054 46 -1 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_016bits.v common 4.19 vpr 62.61 MiB -1 -1 0.08 20360 1 0.01 -1 -1 32908 -1 -1 7 33 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64108 33 17 118 119 1 82 57 17 17 289 -1 unnamed_device 24.2 MiB 0.03 278 62.6 MiB 0.02 0.00 1.27307 -33.1147 -1.27307 1.27307 0.94 5.9755e-05 4.6761e-05 0.00307304 0.00249147 30 575 17 6.64007e+06 87906 526063. 1820.29 1.61 0.023346 0.0194181 22546 126617 -1 495 14 214 214 12161 3747 0 0 12161 3747 214 214 0 0 845 679 0 0 1022 887 0 0 214 214 0 0 4778 965 0 0 5088 788 0 0 214 0 0 0 0 0 214 0 0 0.964048 0.964048 -37.7696 -0.964048 0 0 666494. 2306.21 0.24 0.01 0.08 -1 -1 0.24 0.00297281 0.00264606 49 -1 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_018bits.v common 4.78 vpr 62.67 MiB -1 -1 0.07 20420 1 0.00 -1 -1 32940 -1 -1 8 37 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64176 37 19 132 133 1 90 64 17 17 289 -1 unnamed_device 24.2 MiB 0.03 450 62.7 MiB 0.02 0.00 1.29507 -41.7306 -1.29507 1.29507 0.85 6.8952e-05 5.4679e-05 0.00438265 0.00355566 32 922 12 6.64007e+06 100464 554710. 1919.41 2.14 0.0228023 0.0191226 22834 132086 -1 820 14 356 356 25781 6391 0 0 25781 6391 356 356 0 0 1364 1127 0 0 2057 1635 0 0 356 356 0 0 10948 1522 0 0 10700 1395 0 0 356 0 0 0 0 0 356 0 0 1.20445 1.20445 -50.2315 -1.20445 0 0 701300. 2426.64 0.25 0.01 0.08 -1 -1 0.25 0.00325038 0.00287761 55 -1 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_020bits.v common 4.26 vpr 62.61 MiB -1 -1 0.08 19980 1 0.01 -1 -1 32968 -1 -1 8 41 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64112 41 21 146 147 1 102 70 17 17 289 -1 unnamed_device 24.0 MiB 0.03 384 62.6 MiB 0.03 0.00 1.31707 -42.5775 -1.31707 1.31707 0.77 7.6622e-05 6.078e-05 0.00598531 0.00488994 30 981 24 6.64007e+06 100464 526063. 1820.29 1.67 0.0331684 0.0276836 22546 126617 -1 765 17 511 511 32242 9205 0 0 32242 9205 511 511 0 0 1867 1507 0 0 2416 2015 0 0 511 511 0 0 13085 2421 0 0 13852 2240 0 0 511 0 0 0 0 0 511 0 0 1.12945 1.12945 -50.6718 -1.12945 0 0 666494. 2306.21 0.24 0.01 0.08 -1 -1 0.24 0.00405642 0.00357854 61 -1 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_022bits.v common 3.26 vpr 62.67 MiB -1 -1 0.08 20276 1 0.01 -1 -1 33040 -1 -1 10 45 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64176 45 23 160 161 1 114 78 17 17 289 -1 unnamed_device 24.0 MiB 0.02 578 62.7 MiB 0.03 0.00 1.33907 -52.3632 -1.33907 1.33907 0.76 8.1982e-05 6.5734e-05 0.00589503 0.00482363 32 1138 16 6.64007e+06 125580 554710. 1919.41 0.63 0.0188743 0.0159271 22834 132086 -1 967 15 431 431 30195 7481 0 0 30195 7481 431 431 0 0 1625 1342 0 0 2204 1788 0 0 431 431 0 0 13858 1657 0 0 11646 1832 0 0 431 0 0 0 0 0 431 0 0 1.15025 1.15025 -59.8518 -1.15025 0 0 701300. 2426.64 0.25 0.01 0.14 -1 -1 0.25 0.00404252 0.00359121 68 -1 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_024bits.v common 4.75 vpr 62.80 MiB -1 -1 0.07 20124 1 0.01 -1 -1 33040 -1 -1 10 49 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64308 49 25 174 175 1 123 84 17 17 289 -1 unnamed_device 24.4 MiB 0.03 794 62.8 MiB 0.04 0.00 1.59018 -63.2522 -1.59018 1.59018 0.76 0.000101302 8.3557e-05 0.00627933 0.00517207 30 1432 16 6.64007e+06 125580 526063. 1820.29 2.18 0.0333449 0.028348 22546 126617 -1 1259 18 530 530 36366 8560 0 0 36366 8560 530 530 0 0 1881 1527 0 0 2376 1994 0 0 530 530 0 0 16881 1903 0 0 14168 2076 0 0 530 0 0 0 0 0 530 0 0 1.17025 1.17025 -71.1517 -1.17025 0 0 666494. 2306.21 0.30 0.02 0.08 -1 -1 0.30 0.00515217 0.00456815 73 -1 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_028bits.v common 4.69 vpr 62.86 MiB -1 -1 0.08 20148 1 0.00 -1 -1 32964 -1 -1 11 57 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64364 57 29 202 203 1 143 97 17 17 289 -1 unnamed_device 24.3 MiB 0.08 793 62.9 MiB 0.04 0.00 1.63418 -71.2188 -1.63418 1.63418 0.77 0.000111925 9.1778e-05 0.00712962 0.00587944 30 1571 17 6.64007e+06 138138 526063. 1820.29 2.22 0.039206 0.0334032 22546 126617 -1 1387 15 538 538 37863 9009 0 0 37863 9009 538 538 0 0 1934 1533 0 0 2335 2007 0 0 538 538 0 0 15424 2422 0 0 17094 1971 0 0 538 0 0 0 0 0 538 0 0 1.20325 1.20325 -79.9752 -1.20325 0 0 666494. 2306.21 0.24 0.02 0.08 -1 -1 0.24 0.00513032 0.00460288 85 -1 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_032bits.v common 3.55 vpr 63.08 MiB -1 -1 0.08 20016 1 0.01 -1 -1 32988 -1 -1 13 65 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64592 65 33 230 231 1 164 111 17 17 289 -1 unnamed_device 24.7 MiB 0.07 1052 63.1 MiB 0.06 0.00 1.90729 -88.9548 -1.90729 1.90729 0.92 0.000135708 0.000113344 0.0104943 0.00904605 28 1917 20 6.64007e+06 163254 500653. 1732.36 0.74 0.0339855 0.0296285 21970 115934 -1 1767 17 729 729 65975 15033 0 0 65975 15033 729 729 0 0 2805 2197 0 0 3844 3165 0 0 729 729 0 0 30086 4093 0 0 27782 4120 0 0 729 0 0 0 0 0 729 0 0 1.25625 1.25625 -96.6275 -1.25625 0 0 612192. 2118.31 0.24 0.04 0.07 -1 -1 0.24 0.00734537 0.00628097 97 -1 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_048bits.v common 3.63 vpr 63.79 MiB -1 -1 0.08 20580 1 0.02 -1 -1 33224 -1 -1 19 97 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65324 97 49 342 343 1 246 165 17 17 289 -1 unnamed_device 25.0 MiB 0.04 1578 63.8 MiB 0.12 0.00 2.54151 -146.769 -2.54151 2.54151 0.86 0.000214834 0.000181456 0.0177484 0.0151874 32 2859 14 6.64007e+06 238602 554710. 1919.41 0.71 0.050507 0.0444166 22834 132086 -1 2571 15 1103 1103 93954 21507 0 0 93954 21507 1103 1103 0 0 4270 3484 0 0 6018 4810 0 0 1103 1103 0 0 42578 5394 0 0 38882 5613 0 0 1103 0 0 0 0 0 1103 0 0 1.51745 1.51745 -149.472 -1.51745 0 0 701300. 2426.64 0.26 0.04 0.09 -1 -1 0.26 0.0095106 0.00859984 145 -1 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml adder_064bits.v common 3.93 vpr 64.48 MiB -1 -1 0.09 20716 1 0.01 -1 -1 33600 -1 -1 25 129 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 66032 129 65 454 455 1 328 219 17 17 289 -1 unnamed_device 25.9 MiB 0.06 1985 64.5 MiB 0.27 0.01 3.17573 -209.442 -3.17573 3.17573 0.76 0.000331329 0.000288144 0.0306229 0.0269238 32 4085 26 6.64007e+06 313950 554710. 1919.41 0.84 0.0885901 0.0793588 22834 132086 -1 3438 13 1324 1324 118678 27515 0 0 118678 27515 1324 1324 0 0 5166 4152 0 0 7087 5653 0 0 1324 1324 0 0 52251 7356 0 0 51526 7706 0 0 1324 0 0 0 0 0 1324 0 0 1.83045 1.83045 -211.548 -1.83045 0 0 701300. 2426.64 0.26 0.04 0.09 -1 -1 0.26 0.0128623 0.0118248 193 -1 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_003bits.v common 2.81 vpr 62.10 MiB -1 -1 0.06 20128 1 0.01 -1 -1 33104 -1 -1 2 7 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 63592 7 4 27 28 1 14 13 17 17 289 -1 unnamed_device 23.6 MiB 0.00 30 62.1 MiB 0.00 0.00 0.649848 -5.93533 -0.649848 0.649848 0.96 1.7867e-05 1.3093e-05 0.000418027 0.000328918 14 113 8 6.65987e+06 25356 279208. 966.117 0.33 0.00283539 0.00224662 19378 63921 -1 103 11 62 62 3397 1147 0 0 3397 1147 62 62 0 0 257 206 0 0 307 286 0 0 62 62 0 0 1089 310 0 0 1620 221 0 0 62 0 0 0 0 0 62 0 0 0.890248 0.890248 -7.97873 -0.890248 0 0 355633. 1230.56 0.13 0.00 0.04 -1 -1 0.13 0.00108386 0.000964278 10 -1 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_004bits.v common 3.35 vpr 61.80 MiB -1 -1 0.06 19980 1 0.00 -1 -1 33120 -1 -1 2 9 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 63280 9 5 34 35 1 20 16 17 17 289 -1 unnamed_device 23.3 MiB 0.01 43 61.8 MiB 0.00 0.00 0.660848 -7.17696 -0.660848 0.660848 0.75 1.9311e-05 1.4105e-05 0.000718818 0.000536827 18 153 10 6.65987e+06 25356 355633. 1230.56 1.06 0.0048621 0.00380332 20242 81429 -1 135 17 148 148 6812 2329 0 0 6812 2329 148 148 0 0 556 405 0 0 785 586 0 0 148 148 0 0 2255 508 0 0 2920 534 0 0 148 0 0 0 0 0 148 0 0 0.790989 0.790989 -10.324 -0.790989 0 0 448715. 1552.65 0.16 0.01 0.06 -1 -1 0.16 0.00107941 0.000896919 13 -1 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_005bits.v common 4.51 vpr 62.22 MiB -1 -1 0.07 19800 1 0.00 -1 -1 32892 -1 -1 2 11 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 63712 11 6 41 42 1 26 19 17 17 289 -1 unnamed_device 23.7 MiB 0.01 60 62.2 MiB 0.00 0.00 0.682848 -9.22145 -0.682848 0.682848 0.75 2.3203e-05 1.7082e-05 0.000898156 0.000694822 28 214 25 6.65987e+06 25356 500653. 1732.36 1.92 0.00882029 0.00692739 21970 115934 -1 164 20 198 198 9941 3205 0 0 9941 3205 198 198 0 0 717 589 0 0 1061 832 0 0 198 198 0 0 3391 804 0 0 4376 584 0 0 198 0 0 0 0 0 198 0 0 1.02145 1.02145 -11.5674 -1.02145 0 0 612192. 2118.31 0.33 0.01 0.07 -1 -1 0.33 0.00199016 0.00174176 16 -1 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_006bits.v common 4.91 vpr 62.06 MiB -1 -1 0.07 19880 1 0.01 -1 -1 32888 -1 -1 4 13 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 63552 13 7 48 49 1 32 24 17 17 289 -1 unnamed_device 23.5 MiB 0.02 105 62.1 MiB 0.00 0.00 0.704848 -11.7601 -0.704848 0.704848 0.76 2.3856e-05 1.7529e-05 0.000808604 0.000634251 32 253 15 6.65987e+06 50712 554710. 1919.41 1.99 0.00999329 0.00793827 22834 132086 -1 237 14 163 163 11129 3082 0 0 11129 3082 163 163 0 0 672 571 0 0 1072 868 0 0 163 163 0 0 4566 634 0 0 4493 683 0 0 163 0 0 0 0 0 163 0 0 0.972389 0.972389 -16.2582 -0.972389 0 0 701300. 2426.64 0.36 0.02 0.14 -1 -1 0.36 0.00147597 0.00126506 20 -1 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_007bits.v common 4.49 vpr 61.86 MiB -1 -1 0.07 19792 1 0.01 -1 -1 32824 -1 -1 3 15 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 63340 15 8 55 56 1 38 26 17 17 289 -1 unnamed_device 23.2 MiB 0.01 110 61.9 MiB 0.01 0.00 0.944958 -13.8003 -0.944958 0.944958 0.80 2.8446e-05 2.1096e-05 0.00114354 0.000896579 30 277 15 6.65987e+06 38034 526063. 1820.29 1.85 0.0110606 0.00883289 22546 126617 -1 213 13 122 122 5687 1781 0 0 5687 1781 122 122 0 0 441 349 0 0 606 517 0 0 122 122 0 0 2280 328 0 0 2116 343 0 0 122 0 0 0 0 0 122 0 0 0.834048 0.834048 -16.5924 -0.834048 0 0 666494. 2306.21 0.23 0.01 0.08 -1 -1 0.23 0.00151176 0.00131867 22 -1 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_008bits.v common 2.90 vpr 62.11 MiB -1 -1 0.07 20008 1 0.01 -1 -1 33140 -1 -1 4 17 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 63600 17 9 62 63 1 41 30 17 17 289 -1 unnamed_device 23.5 MiB 0.01 123 62.1 MiB 0.01 0.00 0.955958 -15.9716 -0.955958 0.955958 0.75 3.2026e-05 2.3608e-05 0.00175107 0.0013477 26 373 15 6.65987e+06 50712 477104. 1650.88 0.58 0.0174711 0.016006 21682 110474 -1 316 14 196 196 20827 5470 0 0 20827 5470 196 196 0 0 801 675 0 0 1564 1253 0 0 196 196 0 0 8627 1636 0 0 9443 1514 0 0 196 0 0 0 0 0 196 0 0 1.22765 1.22765 -23.126 -1.22765 0 0 585099. 2024.56 0.22 0.01 0.07 -1 -1 0.22 0.00170252 0.00147464 25 -1 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_009bits.v common 3.18 vpr 62.04 MiB -1 -1 0.06 19760 1 0.01 -1 -1 32960 -1 -1 4 19 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 63528 19 10 69 70 1 44 33 17 17 289 -1 unnamed_device 23.6 MiB 0.01 130 62.0 MiB 0.01 0.00 0.966958 -17.6732 -0.966958 0.966958 0.76 3.4655e-05 2.613e-05 0.00163591 0.00129254 32 388 16 6.65987e+06 50712 554710. 1919.41 0.79 0.00738058 0.00606041 22834 132086 -1 305 12 173 173 10957 3146 0 0 10957 3146 173 173 0 0 701 571 0 0 1076 882 0 0 173 173 0 0 3945 773 0 0 4889 574 0 0 173 0 0 0 0 0 173 0 0 1.07445 1.07445 -23.0152 -1.07445 0 0 701300. 2426.64 0.31 0.01 0.08 -1 -1 0.31 0.00177656 0.00157002 28 -1 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_010bits.v common 4.14 vpr 62.04 MiB -1 -1 0.07 19860 1 0.00 -1 -1 32968 -1 -1 5 21 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 63528 21 11 76 77 1 49 37 17 17 289 -1 unnamed_device 23.6 MiB 0.01 146 62.0 MiB 0.01 0.00 0.977958 -20.1069 -0.977958 0.977958 0.78 3.8089e-05 2.9087e-05 0.00227139 0.00178564 30 423 25 6.65987e+06 63390 526063. 1820.29 1.47 0.0149484 0.0121896 22546 126617 -1 334 14 240 240 12728 3903 0 0 12728 3903 240 240 0 0 917 784 0 0 1215 1058 0 0 240 240 0 0 5049 775 0 0 5067 806 0 0 240 0 0 0 0 0 240 0 0 0.987248 0.987248 -25.1256 -0.987248 0 0 666494. 2306.21 0.24 0.01 0.09 -1 -1 0.24 0.0019859 0.00173488 31 -1 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_011bits.v common 4.35 vpr 62.06 MiB -1 -1 0.06 20136 1 0.01 -1 -1 33068 -1 -1 5 23 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 63552 23 12 83 84 1 55 40 17 17 289 -1 unnamed_device 23.6 MiB 0.01 167 62.1 MiB 0.01 0.00 0.988958 -21.59 -0.988958 0.988958 0.75 4.2098e-05 3.2642e-05 0.00175093 0.00142586 32 462 21 6.65987e+06 63390 554710. 1919.41 2.08 0.0197578 0.0164197 22834 132086 -1 394 19 310 310 21728 6370 0 0 21728 6370 310 310 0 0 1359 1171 0 0 2221 1768 0 0 310 310 0 0 7975 1470 0 0 9553 1341 0 0 310 0 0 0 0 0 310 0 0 1.02025 1.02025 -27.8788 -1.02025 0 0 701300. 2426.64 0.24 0.01 0.08 -1 -1 0.24 0.0025492 0.00219966 34 -1 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_012bits.v common 3.09 vpr 62.24 MiB -1 -1 0.07 19904 1 0.01 -1 -1 33096 -1 -1 5 25 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 63736 25 13 90 91 1 61 43 17 17 289 -1 unnamed_device 23.7 MiB 0.02 219 62.2 MiB 0.01 0.00 0.999958 -24.6468 -0.999958 0.999958 0.74 4.4921e-05 3.4216e-05 0.00259812 0.00206854 30 494 18 6.65987e+06 63390 526063. 1820.29 0.59 0.0100002 0.00824473 22546 126617 -1 450 18 244 244 15168 4066 0 0 15168 4066 244 244 0 0 904 715 0 0 1215 1031 0 0 244 244 0 0 6540 912 0 0 6021 920 0 0 244 0 0 0 0 0 244 0 0 1.12945 1.12945 -32.1701 -1.12945 0 0 666494. 2306.21 0.28 0.01 0.08 -1 -1 0.28 0.00278625 0.00243423 37 -1 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_013bits.v common 3.91 vpr 62.55 MiB -1 -1 0.07 19916 1 0.01 -1 -1 32908 -1 -1 6 27 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64056 27 14 97 98 1 67 47 17 17 289 -1 unnamed_device 24.0 MiB 0.01 241 62.6 MiB 0.02 0.00 1.01096 -26.6327 -1.01096 1.01096 0.85 5.0297e-05 3.8875e-05 0.00272725 0.00220924 30 580 15 6.65987e+06 76068 526063. 1820.29 1.55 0.0178237 0.0148855 22546 126617 -1 472 13 300 300 16127 4843 0 0 16127 4843 300 300 0 0 1182 1019 0 0 1496 1337 0 0 300 300 0 0 6218 1015 0 0 6631 872 0 0 300 0 0 0 0 0 300 0 0 1.00925 1.00925 -32.6892 -1.00925 0 0 666494. 2306.21 0.25 0.01 0.08 -1 -1 0.25 0.0024604 0.00218426 40 -1 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_014bits.v common 4.92 vpr 62.11 MiB -1 -1 0.07 19952 1 0.01 -1 -1 32924 -1 -1 7 29 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 63600 29 15 104 105 1 73 51 17 17 289 -1 unnamed_device 23.5 MiB 0.01 264 62.1 MiB 0.02 0.00 1.02196 -29.1104 -1.02196 1.02196 0.90 5.3831e-05 4.1667e-05 0.0027004 0.00214936 30 584 17 6.65987e+06 88746 526063. 1820.29 2.14 0.0180588 0.014999 22546 126617 -1 505 14 298 298 16381 4655 0 0 16381 4655 298 298 0 0 1110 900 0 0 1470 1269 0 0 298 298 0 0 6992 895 0 0 6213 995 0 0 298 0 0 0 0 0 298 0 0 1.04225 1.04225 -35.946 -1.04225 0 0 666494. 2306.21 0.28 0.01 0.08 -1 -1 0.28 0.00280604 0.00249325 44 -1 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_015bits.v common 3.22 vpr 62.16 MiB -1 -1 0.07 20488 1 0.01 -1 -1 32932 -1 -1 7 31 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 63648 31 16 111 112 1 79 54 17 17 289 -1 unnamed_device 23.6 MiB 0.01 288 62.2 MiB 0.02 0.00 1.26207 -31.3475 -1.26207 1.26207 0.86 5.8077e-05 4.4132e-05 0.00288873 0.00228026 32 722 14 6.65987e+06 88746 554710. 1919.41 0.68 0.0118886 0.00993717 22834 132086 -1 614 17 373 373 32089 8455 0 0 32089 8455 373 373 0 0 1554 1324 0 0 2746 2252 0 0 373 373 0 0 13402 2104 0 0 13641 2029 0 0 373 0 0 0 0 0 373 0 0 1.28065 1.28065 -42.7998 -1.28065 0 0 701300. 2426.64 0.25 0.01 0.08 -1 -1 0.25 0.00338189 0.0029862 46 -1 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_016bits.v common 4.53 vpr 62.43 MiB -1 -1 0.08 20284 1 0.01 -1 -1 32924 -1 -1 7 33 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 63928 33 17 118 119 1 82 57 17 17 289 -1 unnamed_device 24.0 MiB 0.01 292 62.4 MiB 0.06 0.00 1.27307 -33.3551 -1.27307 1.27307 0.95 6.0357e-05 4.7151e-05 0.00460899 0.00395481 28 796 37 6.65987e+06 88746 500653. 1732.36 1.86 0.0313521 0.0255857 21970 115934 -1 652 16 373 373 31736 8443 0 0 31736 8443 373 373 0 0 1461 1214 0 0 2109 1758 0 0 373 373 0 0 13489 2531 0 0 13931 2194 0 0 373 0 0 0 0 0 373 0 0 1.20565 1.20565 -44.0458 -1.20565 0 0 612192. 2118.31 0.22 0.01 0.07 -1 -1 0.22 0.00338232 0.00298209 49 -1 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_018bits.v common 4.45 vpr 62.39 MiB -1 -1 0.07 20152 1 0.01 -1 -1 32984 -1 -1 8 37 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 63884 37 19 132 133 1 90 64 17 17 289 -1 unnamed_device 23.9 MiB 0.02 392 62.4 MiB 0.03 0.00 1.29507 -39.6872 -1.29507 1.29507 0.81 6.8064e-05 5.3897e-05 0.00449432 0.00364587 28 926 38 6.65987e+06 101424 500653. 1732.36 1.97 0.0337131 0.0283501 21970 115934 -1 754 14 382 382 31267 7884 0 0 31267 7884 382 382 0 0 1513 1256 0 0 2127 1799 0 0 382 382 0 0 13311 2125 0 0 13552 1940 0 0 382 0 0 0 0 0 382 0 0 1.08425 1.08425 -46.9422 -1.08425 0 0 612192. 2118.31 0.23 0.01 0.07 -1 -1 0.23 0.00364889 0.00326274 55 -1 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_020bits.v common 3.44 vpr 62.77 MiB -1 -1 0.07 20108 1 0.01 -1 -1 32928 -1 -1 8 41 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64276 41 21 146 147 1 102 70 17 17 289 -1 unnamed_device 24.2 MiB 0.02 386 62.8 MiB 0.03 0.00 1.31707 -43.4189 -1.31707 1.31707 0.77 7.7829e-05 6.2035e-05 0.00609323 0.00496568 32 1113 38 6.65987e+06 101424 554710. 1919.41 0.68 0.0221179 0.0186856 22834 132086 -1 870 17 515 515 46001 11695 0 0 46001 11695 515 515 0 0 2111 1780 0 0 3671 2903 0 0 515 515 0 0 19329 3077 0 0 19860 2905 0 0 515 0 0 0 0 0 515 0 0 1.36865 1.36865 -57.6558 -1.36865 0 0 701300. 2426.64 0.40 0.02 0.08 -1 -1 0.40 0.00412444 0.00364829 61 -1 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_022bits.v common 5.66 vpr 62.49 MiB -1 -1 0.08 20156 1 0.01 -1 -1 32904 -1 -1 10 45 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 63992 45 23 160 161 1 114 78 17 17 289 -1 unnamed_device 24.1 MiB 0.02 499 62.5 MiB 0.03 0.00 1.33907 -49.7188 -1.33907 1.33907 0.84 8.4397e-05 6.7519e-05 0.0064121 0.00530621 36 1011 19 6.65987e+06 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fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_048bits.v common 5.14 vpr 63.75 MiB -1 -1 0.08 20416 1 0.01 -1 -1 33160 -1 -1 19 97 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65280 97 49 342 343 1 246 165 17 17 289 -1 unnamed_device 24.9 MiB 0.03 1550 63.8 MiB 0.12 0.00 2.54151 -146.288 -2.54151 2.54151 0.76 0.000221626 0.000190527 0.0171015 0.0145444 36 2735 17 6.65987e+06 240882 612192. 2118.31 2.45 0.092384 0.0812177 23410 145293 -1 2474 16 921 921 74637 17068 0 0 74637 17068 921 921 0 0 3518 2787 0 0 4925 4058 0 0 921 921 0 0 33217 4274 0 0 31135 4107 0 0 921 0 0 0 0 0 921 0 0 1.52845 1.52845 -146.508 -1.52845 0 0 782063. 2706.10 0.33 0.03 0.09 -1 -1 0.33 0.0108476 0.00990369 145 -1 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml adder_064bits.v common 5.83 vpr 64.48 MiB -1 -1 0.09 20664 1 0.02 -1 -1 33296 -1 -1 25 129 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 66024 129 65 454 455 1 328 219 17 17 289 -1 unnamed_device 25.9 MiB 0.05 1949 64.5 MiB 0.18 0.00 3.17573 -211.846 -3.17573 3.17573 0.89 0.000353029 0.000310239 0.0285208 0.0249814 36 3778 18 6.65987e+06 316950 612192. 2118.31 2.64 0.156103 0.135419 23410 145293 -1 3242 15 1293 1293 106994 25701 0 0 106994 25701 1293 1293 0 0 4974 4074 0 0 6829 5669 0 0 1293 1293 0 0 46668 6468 0 0 45937 6904 0 0 1293 0 0 0 0 0 1293 0 0 1.77039 1.77039 -203.07 -1.77039 0 0 782063. 2706.10 0.27 0.05 0.09 -1 -1 0.27 0.0140198 0.0128862 193 -1 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml adder_003bits.v common 2.53 vpr 62.84 MiB -1 -1 0.06 20084 1 0.00 -1 -1 33108 -1 -1 1 7 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64348 7 4 27 28 1 12 12 17 17 289 -1 unnamed_device 24.4 MiB 0.01 77 62.8 MiB 0.00 0.00 0.942216 -8.23033 -0.942216 0.942216 0.86 2.0778e-05 1.3657e-05 0.000196851 0.000166374 8 125 9 6.95648e+06 14475.7 166176. 575.005 0.23 0.00102943 0.000869229 20866 45572 -1 121 5 20 20 1899 476 0 0 1899 476 20 20 0 0 79 54 0 0 88 79 0 0 20 20 0 0 845 145 0 0 847 158 0 0 20 0 0 0 0 0 20 0 0 0.942216 0.942216 -9.23274 -0.942216 0 0 202963. 702.294 0.08 0.00 0.03 -1 -1 0.08 0.000565629 0.000497204 5 -1 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml adder_004bits.v common 4.10 vpr 62.89 MiB -1 -1 0.07 19828 1 0.00 -1 -1 32980 -1 -1 1 9 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64400 9 5 34 35 1 15 15 17 17 289 -1 unnamed_device 24.4 MiB 0.02 33 62.9 MiB 0.00 0.00 0.583992 -7.62477 -0.583992 0.583992 0.94 1.8769e-05 1.3214e-05 0.000743785 0.00056405 18 138 11 6.95648e+06 14475.7 376052. 1301.22 1.25 0.00456886 0.00358671 22882 88689 -1 98 7 44 44 1942 698 0 0 1942 698 44 44 0 0 164 143 0 0 223 175 0 0 44 44 0 0 616 157 0 0 851 135 0 0 44 0 0 0 0 0 44 0 0 0.834592 0.834592 -9.50427 -0.834592 0 0 470940. 1629.55 0.18 0.00 0.06 -1 -1 0.18 0.000741296 0.000650684 7 -1 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml adder_005bits.v common 3.10 vpr 63.06 MiB -1 -1 0.08 20112 1 0.00 -1 -1 32892 -1 -1 1 11 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64576 11 6 41 42 1 19 18 17 17 289 -1 unnamed_device 24.5 MiB 0.03 45 63.1 MiB 0.00 0.00 0.701895 -10.0315 -0.701895 0.701895 0.91 2.1586e-05 1.554e-05 0.000827469 0.000648735 26 162 16 6.95648e+06 14475.7 503264. 1741.40 0.59 0.00454648 0.00366697 24322 120374 -1 138 10 66 66 4464 1386 0 0 4464 1386 66 66 0 0 274 235 0 0 342 295 0 0 66 66 0 0 1721 358 0 0 1995 366 0 0 66 0 0 0 0 0 66 0 0 0.74674 0.74674 -12.5375 -0.74674 0 0 618332. 2139.56 0.24 0.00 0.08 -1 -1 0.24 0.00109895 0.000963707 8 -1 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml adder_006bits.v common 3.18 vpr 62.66 MiB -1 -1 0.06 19780 1 0.01 -1 -1 32932 -1 -1 2 13 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64164 13 7 48 49 1 25 22 17 17 289 -1 unnamed_device 24.1 MiB 0.03 58 62.7 MiB 0.01 0.00 0.745895 -12.7431 -0.745895 0.745895 0.79 2.5224e-05 1.8445e-05 0.00111902 0.000863795 26 176 10 6.95648e+06 28951.4 503264. 1741.40 0.69 0.00515298 0.00417575 24322 120374 -1 166 10 89 89 3722 1353 0 0 3722 1353 89 89 0 0 337 285 0 0 471 393 0 0 89 89 0 0 1277 288 0 0 1459 209 0 0 89 0 0 0 0 0 89 0 0 0.802432 0.802432 -15.6773 -0.802432 0 0 618332. 2139.56 0.21 0.00 0.08 -1 -1 0.21 0.00124805 0.00110335 10 -1 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml adder_007bits.v common 3.96 vpr 62.85 MiB -1 -1 0.07 20128 1 0.01 -1 -1 32908 -1 -1 2 15 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64356 15 8 55 56 1 32 25 17 17 289 -1 unnamed_device 24.2 MiB 0.03 84 62.8 MiB 0.00 0.00 0.727332 -14.8036 -0.727332 0.727332 0.89 2.8649e-05 2.1705e-05 0.000881576 0.000714259 20 293 9 6.95648e+06 28951.4 414966. 1435.87 1.39 0.00767109 0.00624226 23170 95770 -1 267 11 161 161 10957 3380 0 0 10957 3380 161 161 0 0 680 582 0 0 896 747 0 0 161 161 0 0 3797 877 0 0 5262 852 0 0 161 0 0 0 0 0 161 0 0 1.04203 1.04203 -19.7843 -1.04203 0 0 503264. 1741.40 0.18 0.01 0.06 -1 -1 0.18 0.00138121 0.00120802 11 -1 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml adder_008bits.v common 4.89 vpr 62.81 MiB -1 -1 0.07 19944 1 0.00 -1 -1 32956 -1 -1 2 17 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64316 17 9 62 63 1 37 28 17 17 289 -1 unnamed_device 24.5 MiB 0.03 103 62.8 MiB 0.01 0.00 0.942216 -16.9019 -0.942216 0.942216 0.81 3.1956e-05 2.3766e-05 0.001046 0.000848463 32 327 24 6.95648e+06 28951.4 586450. 2029.24 2.27 0.0148055 0.0121329 25474 144626 -1 263 9 146 146 7662 2529 0 0 7662 2529 146 146 0 0 588 517 0 0 884 683 0 0 146 146 0 0 2777 544 0 0 3121 493 0 0 146 0 0 0 0 0 146 0 0 0.960732 0.960732 -20.9096 -0.960732 0 0 744469. 2576.02 0.25 0.01 0.09 -1 -1 0.25 0.00137963 0.00123131 13 -1 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml adder_009bits.v common 4.67 vpr 63.00 MiB -1 -1 0.08 20064 1 0.00 -1 -1 33068 -1 -1 2 19 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64512 19 10 69 70 1 44 31 17 17 289 -1 unnamed_device 24.6 MiB 0.03 168 63.0 MiB 0.01 0.00 0.760332 -18.4143 -0.760332 0.760332 0.85 3.4799e-05 2.6884e-05 0.00150125 0.00122015 30 419 15 6.95648e+06 28951.4 556674. 1926.21 1.97 0.0143203 0.011703 25186 138497 -1 405 16 253 253 18478 4518 0 0 18478 4518 253 253 0 0 908 747 0 0 1290 999 0 0 253 253 0 0 8360 1014 0 0 7414 1252 0 0 253 0 0 0 0 0 253 0 0 1.08603 1.08603 -26.1011 -1.08603 0 0 706193. 2443.58 0.26 0.01 0.08 -1 -1 0.26 0.00205937 0.00179515 14 -1 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml adder_010bits.v common 5.51 vpr 63.16 MiB -1 -1 0.06 19892 1 0.01 -1 -1 33000 -1 -1 2 21 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64676 21 11 76 77 1 49 34 17 17 289 -1 unnamed_device 24.7 MiB 0.03 127 63.2 MiB 0.01 0.00 0.771332 -20.8321 -0.771332 0.771332 0.80 4.2584e-05 3.2978e-05 0.00193603 0.00156216 36 432 32 6.95648e+06 28951.4 648988. 2245.63 2.93 0.0181196 0.0147541 26050 158493 -1 358 22 333 333 19934 6070 0 0 19934 6070 333 333 0 0 1184 1054 0 0 1901 1353 0 0 333 333 0 0 6868 1715 0 0 9315 1282 0 0 333 0 0 0 0 0 333 0 0 1.14723 1.14723 -27.3447 -1.14723 0 0 828058. 2865.25 0.28 0.01 0.10 -1 -1 0.28 0.00276904 0.00237989 16 -1 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml adder_011bits.v common 4.07 vpr 63.29 MiB -1 -1 0.08 20016 1 0.01 -1 -1 32908 -1 -1 3 23 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64812 23 12 83 84 1 55 38 17 17 289 -1 unnamed_device 24.8 MiB 0.03 285 63.3 MiB 0.01 0.00 0.765132 -25.7294 -0.765132 0.765132 0.78 4.2584e-05 3.1952e-05 0.00155378 0.00125338 30 659 23 6.95648e+06 43427 556674. 1926.21 1.48 0.0153849 0.0126151 25186 138497 -1 590 15 335 335 33884 7251 0 0 33884 7251 335 335 0 0 1200 1008 0 0 1818 1362 0 0 335 335 0 0 15567 2051 0 0 14629 2160 0 0 335 0 0 0 0 0 335 0 0 1.16733 1.16733 -33.6052 -1.16733 0 0 706193. 2443.58 0.24 0.01 0.09 -1 -1 0.24 0.00240645 0.00212247 17 -1 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml adder_012bits.v common 4.11 vpr 63.13 MiB -1 -1 0.07 20044 1 0.01 -1 -1 32964 -1 -1 3 25 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64644 25 13 90 91 1 60 41 17 17 289 -1 unnamed_device 24.6 MiB 0.03 204 63.1 MiB 0.01 0.00 0.816915 -24.4477 -0.816915 0.816915 0.85 4.3231e-05 3.3072e-05 0.00152426 0.00123845 30 596 19 6.95648e+06 43427 556674. 1926.21 1.47 0.017158 0.0139873 25186 138497 -1 477 16 318 318 20202 5759 0 0 20202 5759 318 318 0 0 1101 940 0 0 1667 1235 0 0 318 318 0 0 7533 1421 0 0 9265 1527 0 0 318 0 0 0 0 0 318 0 0 1.20033 1.20033 -35.5436 -1.20033 0 0 706193. 2443.58 0.25 0.01 0.08 -1 -1 0.25 0.00255272 0.00223926 19 -1 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml adder_013bits.v common 3.96 vpr 63.09 MiB -1 -1 0.07 19880 1 0.01 -1 -1 32904 -1 -1 3 27 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64600 27 14 97 98 1 66 44 17 17 289 -1 unnamed_device 24.6 MiB 0.03 436 63.1 MiB 0.03 0.00 0.826332 -34.4783 -0.826332 0.826332 0.88 5.3348e-05 4.1859e-05 0.00222185 0.00185062 34 880 16 6.95648e+06 43427 618332. 2139.56 1.25 0.0131852 0.0109946 25762 151098 -1 829 13 357 357 42262 8653 0 0 42262 8653 357 357 0 0 1363 1182 0 0 2290 1596 0 0 357 357 0 0 19459 2717 0 0 18436 2444 0 0 357 0 0 0 0 0 357 0 0 1.27733 1.27733 -45.9127 -1.27733 0 0 787024. 2723.27 0.27 0.01 0.10 -1 -1 0.27 0.00255998 0.0022649 20 -1 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml adder_014bits.v common 3.85 vpr 63.08 MiB -1 -1 0.08 19828 1 0.01 -1 -1 32884 -1 -1 4 29 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64596 29 15 104 105 1 72 48 17 17 289 -1 unnamed_device 24.6 MiB 0.02 469 63.1 MiB 0.01 0.00 0.826332 -37.0057 -0.826332 0.826332 0.89 5.1384e-05 4.1019e-05 0.00265928 0.00220733 34 972 14 6.95648e+06 57902.7 618332. 2139.56 1.13 0.0167619 0.0140226 25762 151098 -1 916 19 461 461 56404 11191 0 0 56404 11191 461 461 0 0 1608 1415 0 0 2791 1850 0 0 461 461 0 0 25783 3791 0 0 25300 3213 0 0 461 0 0 0 0 0 461 0 0 1.15203 1.15203 -48.5262 -1.15203 0 0 787024. 2723.27 0.33 0.02 0.11 -1 -1 0.33 0.00350085 0.00306696 23 -1 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml adder_015bits.v common 3.94 vpr 63.19 MiB -1 -1 0.07 20204 1 0.01 -1 -1 33032 -1 -1 3 31 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64704 31 16 111 112 1 78 50 17 17 289 -1 unnamed_device 24.9 MiB 0.04 264 63.2 MiB 0.02 0.00 1.08336 -32.6216 -1.08336 1.08336 0.77 5.6338e-05 4.4314e-05 0.00335799 0.00272262 32 898 31 6.95648e+06 43427 586450. 2029.24 1.20 0.0189299 0.0159762 25474 144626 -1 653 24 491 491 52434 12757 0 0 52434 12757 491 491 0 0 1781 1554 0 0 3129 2045 0 0 491 491 0 0 22848 4026 0 0 23694 4150 0 0 491 0 0 0 0 0 491 0 0 1.31453 1.31453 -46.3757 -1.31453 0 0 744469. 2576.02 0.25 0.02 0.09 -1 -1 0.25 0.00428191 0.00374381 24 -1 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml adder_016bits.v common 3.99 vpr 63.24 MiB -1 -1 0.06 20548 1 0.00 -1 -1 32996 -1 -1 4 33 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64756 33 17 118 119 1 81 54 17 17 289 -1 unnamed_device 24.8 MiB 0.06 280 63.2 MiB 0.02 0.00 1.09436 -35.1295 -1.09436 1.09436 0.79 6.3565e-05 5.0428e-05 0.00374796 0.00306497 34 867 18 6.95648e+06 57902.7 618332. 2139.56 1.15 0.0214524 0.0185472 25762 151098 -1 654 18 447 447 37952 9614 0 0 37952 9614 447 447 0 0 1632 1418 0 0 2744 1938 0 0 447 447 0 0 15127 2889 0 0 17555 2475 0 0 447 0 0 0 0 0 447 0 0 1.31933 1.31933 -49.0729 -1.31933 0 0 787024. 2723.27 0.27 0.01 0.10 -1 -1 0.27 0.00368181 0.00323176 25 -1 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml adder_018bits.v common 3.94 vpr 63.21 MiB -1 -1 0.07 20180 1 0.00 -1 -1 32720 -1 -1 4 37 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64724 37 19 132 133 1 87 60 17 17 289 -1 unnamed_device 24.8 MiB 0.07 310 63.2 MiB 0.03 0.00 1.11636 -39.6418 -1.11636 1.11636 0.84 9.7823e-05 8.1657e-05 0.00471496 0.00390367 34 889 28 6.95648e+06 57902.7 618332. 2139.56 1.23 0.0265108 0.0224273 25762 151098 -1 713 18 512 512 46721 11700 0 0 46721 11700 512 512 0 0 1898 1695 0 0 3254 2334 0 0 512 512 0 0 20329 3215 0 0 20216 3432 0 0 512 0 0 0 0 0 512 0 0 1.35233 1.35233 -54.2252 -1.35233 0 0 787024. 2723.27 0.26 0.02 0.10 -1 -1 0.26 0.00435942 0.00387072 28 -1 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml adder_020bits.v common 4.24 vpr 63.66 MiB -1 -1 0.08 20020 1 0.01 -1 -1 33128 -1 -1 4 41 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65192 41 21 146 147 1 96 66 17 17 289 -1 unnamed_device 25.1 MiB 0.07 350 63.7 MiB 0.02 0.00 1.13836 -44.3233 -1.13836 1.13836 0.76 7.5058e-05 5.9607e-05 0.00495286 0.00401632 34 1075 28 6.95648e+06 57902.7 618332. 2139.56 1.48 0.0298285 0.0251595 25762 151098 -1 833 17 513 513 52208 12213 0 0 52208 12213 513 513 0 0 1839 1599 0 0 3018 2030 0 0 513 513 0 0 22144 3947 0 0 24181 3611 0 0 513 0 0 0 0 0 513 0 0 1.27723 1.27723 -59.1063 -1.27723 0 0 787024. 2723.27 0.45 0.05 0.10 -1 -1 0.45 0.0214118 0.0208519 31 -1 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml adder_022bits.v common 4.06 vpr 63.26 MiB -1 -1 0.07 20340 1 0.01 -1 -1 33028 -1 -1 5 45 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64776 45 23 160 161 1 108 73 17 17 289 -1 unnamed_device 24.7 MiB 0.08 398 63.3 MiB 0.03 0.00 1.16036 -49.0488 -1.16036 1.16036 0.77 8.513e-05 6.8494e-05 0.0058991 0.00488477 36 1127 23 6.95648e+06 72378.4 648988. 2245.63 1.43 0.0325613 0.0276788 26050 158493 -1 944 22 661 661 70162 16241 0 0 70162 16241 661 661 0 0 2331 2052 0 0 3924 2707 0 0 661 661 0 0 30079 5227 0 0 32506 4933 0 0 661 0 0 0 0 0 661 0 0 1.41833 1.41833 -68.7529 -1.41833 0 0 828058. 2865.25 0.28 0.02 0.10 -1 -1 0.28 0.00794832 0.00722832 34 -1 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml adder_024bits.v common 4.51 vpr 63.79 MiB -1 -1 0.08 20124 1 0.01 -1 -1 32900 -1 -1 5 49 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65324 49 25 174 175 1 119 79 17 17 289 -1 unnamed_device 25.4 MiB 0.08 454 63.8 MiB 0.04 0.00 1.18236 -53.693 -1.18236 1.18236 1.03 9.0751e-05 7.2569e-05 0.00739754 0.00615064 38 1291 38 6.95648e+06 72378.4 678818. 2348.85 1.57 0.0399406 0.03423 26626 170182 -1 1033 18 725 725 60715 16971 0 0 60715 16971 725 725 0 0 2533 2236 0 0 3986 2817 0 0 725 725 0 0 24711 5491 0 0 28035 4977 0 0 725 0 0 0 0 0 725 0 0 1.47293 1.47293 -71.9016 -1.47293 0 0 902133. 3121.57 0.30 0.02 0.11 -1 -1 0.30 0.00579795 0.00519465 37 -1 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml adder_028bits.v common 6.64 vpr 63.35 MiB -1 -1 0.07 20320 1 0.01 -1 -1 32976 -1 -1 6 57 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64872 57 29 202 203 1 142 92 17 17 289 -1 unnamed_device 24.8 MiB 0.06 720 63.4 MiB 0.04 0.00 1.22636 -68.3761 -1.22636 1.22636 0.76 0.000105901 8.6762e-05 0.00799504 0.00663199 36 1630 50 6.95648e+06 86854.1 648988. 2245.63 4.13 0.0704574 0.0602201 26050 158493 -1 1337 17 770 770 85936 18635 0 0 85936 18635 770 770 0 0 2747 2410 0 0 4375 3198 0 0 770 770 0 0 39290 5945 0 0 37984 5542 0 0 770 0 0 0 0 0 770 0 0 1.45133 1.45133 -88.764 -1.45133 0 0 828058. 2865.25 0.28 0.02 0.10 -1 -1 0.28 0.00613179 0.00550864 43 -1 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml adder_032bits.v common 6.20 vpr 63.61 MiB -1 -1 0.08 20152 1 0.01 -1 -1 32992 -1 -1 7 65 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65132 65 33 230 231 1 162 105 17 17 289 -1 unnamed_device 25.2 MiB 0.07 753 63.6 MiB 0.05 0.00 1.50539 -78.0667 -1.50539 1.50539 0.90 0.000126253 0.000103192 0.00922406 0.00767664 44 1563 15 6.95648e+06 101330 787024. 2723.27 3.13 0.0589574 0.0508205 27778 195446 -1 1278 14 795 795 63045 14749 0 0 63045 14749 795 795 0 0 2718 2422 0 0 4499 3163 0 0 795 795 0 0 26727 3961 0 0 27511 3613 0 0 795 0 0 0 0 0 795 0 0 1.30393 1.30393 -90.3271 -1.30393 0 0 997811. 3452.63 0.42 0.04 0.12 -1 -1 0.42 0.0065108 0.00591406 49 -1 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml adder_048bits.v common 6.80 vpr 64.46 MiB -1 -1 0.09 20452 1 0.01 -1 -1 33396 -1 -1 10 97 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 66004 97 49 342 343 1 243 156 17 17 289 -1 unnamed_device 25.7 MiB 0.08 1453 64.5 MiB 0.09 0.00 1.91642 -137.228 -1.91642 1.91642 0.77 0.000213653 0.00018202 0.0160223 0.0137481 50 2733 37 6.95648e+06 144757 902133. 3121.57 3.90 0.148794 0.133909 28642 213929 -1 2443 17 1110 1110 118780 25374 0 0 118780 25374 1110 1110 0 0 4023 3507 0 0 6503 4756 0 0 1110 1110 0 0 53180 7140 0 0 52854 7751 0 0 1110 0 0 0 0 0 1110 0 0 1.59703 1.59703 -158.976 -1.59703 0 0 1.08113e+06 3740.92 0.37 0.04 0.16 -1 -1 0.37 0.0112007 0.0101985 73 -1 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml adder_064bits.v common 5.92 vpr 65.25 MiB -1 -1 0.10 20656 1 0.01 -1 -1 33468 -1 -1 13 129 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 66812 129 65 454 455 1 324 207 17 17 289 -1 unnamed_device 26.4 MiB 0.17 2042 65.2 MiB 0.13 0.00 2.32745 -201.714 -2.32745 2.32745 0.80 0.000333429 0.000291028 0.0222511 0.0195904 50 3914 48 6.95648e+06 188184 902133. 3121.57 2.63 0.154346 0.140807 28642 213929 -1 3483 19 1438 1438 159180 32034 0 0 159180 32034 1438 1438 0 0 5067 4384 0 0 8321 5842 0 0 1438 1438 0 0 71880 9691 0 0 71036 9241 0 0 1438 0 0 0 0 0 1438 0 0 1.73803 1.73803 -217.561 -1.73803 0 0 1.08113e+06 3740.92 0.36 0.06 0.14 -1 -1 0.36 0.0186169 0.0171151 97 -1 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml adder_003bits.v common 3.15 vpr 62.59 MiB -1 -1 0.07 20108 1 0.00 -1 -1 33132 -1 -1 1 7 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64092 7 4 27 28 1 13 12 17 17 289 -1 unnamed_device 24.2 MiB 0.01 62 62.6 MiB 0.00 0.00 0.816915 -8.12034 -0.816915 0.816915 0.90 2.1868e-05 1.4993e-05 0.000198598 0.000167496 14 112 10 6.99608e+06 14715.7 292583. 1012.40 0.59 0.00150327 0.00122895 22018 70521 -1 146 8 38 38 3136 964 0 0 3136 964 38 38 0 0 178 164 0 0 231 216 0 0 38 38 0 0 1158 286 0 0 1493 222 0 0 38 0 0 0 0 0 38 0 0 0.942216 0.942216 -10.8769 -0.942216 0 0 376052. 1301.22 0.13 0.00 0.05 -1 -1 0.13 0.000637288 0.00055024 5 -1 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml adder_004bits.v common 3.17 vpr 62.88 MiB -1 -1 0.07 19708 1 0.01 -1 -1 32964 -1 -1 1 9 0 0 exited with return code 2 v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64392 9 5 34 35 1 17 15 17 17 289 -1 unnamed_device 24.4 MiB 0.01 35 62.9 MiB 0.00 0.00 0.712895 -8.47096 -0.712895 0.712895 1.05 2.1394e-05 1.5874e-05 0.00083861 0.000653329 18 149 17 6.99608e+06 14715.7 376052. 1301.22 0.42 0.00205775 0.00167702 22882 88689 -1 -1 -1 363 363 733654 210989 0 0 733654 210989 363 363 0 0 1159 842 0 0 7695 1263 0 0 363 363 0 0 514294 99963 0 0 209780 108195 0 0 363 0 0 0 0 0 363 0 0 -1 -1 -1 -1 -1 -1 -1 -1 0.16 0.14 0.06 -1 -1 0.16 -1 -1 7 -1 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml adder_005bits.v common 3.04 vpr 62.69 MiB -1 -1 0.06 19952 1 0.00 -1 -1 32700 -1 -1 1 11 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64196 11 6 41 42 1 20 18 17 17 289 -1 unnamed_device 24.2 MiB 0.01 46 62.7 MiB 0.00 0.00 0.837432 -11.8241 -0.837432 0.837432 0.82 2.2253e-05 1.6154e-05 0.000663897 0.000529632 28 146 5 6.99608e+06 14715.7 531479. 1839.03 0.57 0.00358838 0.0029183 24610 126494 -1 143 6 41 41 3002 931 0 0 3002 931 41 41 0 0 176 156 0 0 224 196 0 0 41 41 0 0 1147 256 0 0 1373 241 0 0 41 0 0 0 0 0 41 0 0 0.837432 0.837432 -14.0795 -0.837432 0 0 648988. 2245.63 0.23 0.00 0.08 -1 -1 0.23 0.000838838 0.000749994 8 -1 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml adder_006bits.v common 3.40 vpr 62.94 MiB -1 -1 0.07 19916 1 0.01 -1 -1 32904 -1 -1 2 13 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64452 13 7 48 49 1 25 22 17 17 289 -1 unnamed_device 24.4 MiB 0.01 63 62.9 MiB 0.01 0.00 0.699132 -12.7017 -0.699132 0.699132 0.80 2.8326e-05 2.1437e-05 0.00140711 0.00109842 20 188 11 6.99608e+06 29431.4 414966. 1435.87 1.00 0.00882818 0.00707052 23170 95770 -1 163 11 108 108 5539 1901 0 0 5539 1901 108 108 0 0 432 373 0 0 537 468 0 0 108 108 0 0 1851 481 0 0 2503 363 0 0 108 0 0 0 0 0 108 0 0 0.74674 0.74674 -14.8318 -0.74674 0 0 503264. 1741.40 0.17 0.00 0.06 -1 -1 0.17 0.00116341 0.00101702 10 -1 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml adder_007bits.v common 4.57 vpr 62.70 MiB -1 -1 0.06 20156 1 0.00 -1 -1 32888 -1 -1 2 15 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64200 15 8 55 56 1 32 25 17 17 289 -1 unnamed_device 24.1 MiB 0.01 81 62.7 MiB 0.01 0.00 0.859432 -15.6972 -0.859432 0.859432 0.76 2.7965e-05 2.0756e-05 0.0010553 0.000836151 26 255 12 6.99608e+06 29431.4 503264. 1741.40 1.74 0.0115092 0.00927422 24322 120374 -1 229 12 151 151 13146 4002 0 0 13146 4002 151 151 0 0 653 566 0 0 892 750 0 0 151 151 0 0 4861 1308 0 0 6438 1076 0 0 151 0 0 0 0 0 151 0 0 0.99734 0.99734 -19.4185 -0.99734 0 0 618332. 2139.56 0.22 0.01 0.09 -1 -1 0.22 0.00138874 0.00120173 11 -1 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml adder_008bits.v common 4.09 vpr 62.80 MiB -1 -1 0.07 19856 1 0.01 -1 -1 33020 -1 -1 2 17 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64308 17 9 62 63 1 36 28 17 17 289 -1 unnamed_device 24.1 MiB 0.01 100 62.8 MiB 0.01 0.00 0.710132 -15.8578 -0.710132 0.710132 0.78 3.2491e-05 2.4159e-05 0.00105742 0.000816533 36 230 21 6.99608e+06 29431.4 648988. 2245.63 1.73 0.0143474 0.0115451 26050 158493 -1 224 14 186 186 8873 3042 0 0 8873 3042 186 186 0 0 735 629 0 0 1030 840 0 0 186 186 0 0 3283 602 0 0 3453 599 0 0 186 0 0 0 0 0 186 0 0 1.07503 1.07503 -19.8204 -1.07503 0 0 828058. 2865.25 0.28 0.01 0.10 -1 -1 0.28 0.00185702 0.00162904 13 -1 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml adder_009bits.v common 4.88 vpr 62.60 MiB -1 -1 0.07 20080 1 0.01 -1 -1 32720 -1 -1 2 19 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64104 19 10 69 70 1 44 31 17 17 289 -1 unnamed_device 24.2 MiB 0.01 116 62.6 MiB 0.01 0.00 0.743132 -18.2879 -0.743132 0.743132 0.75 3.5188e-05 2.685e-05 0.00129422 0.00103082 30 416 14 6.99608e+06 29431.4 556674. 1926.21 2.33 0.0110753 0.00895514 25186 138497 -1 318 14 214 214 12527 3787 0 0 12527 3787 214 214 0 0 763 628 0 0 1020 816 0 0 214 214 0 0 4509 954 0 0 5807 961 0 0 214 0 0 0 0 0 214 0 0 0.973679 0.973679 -24.4206 -0.973679 0 0 706193. 2443.58 0.26 0.01 0.23 -1 -1 0.26 0.00196644 0.00172217 14 -1 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml adder_010bits.v common 4.90 vpr 62.70 MiB -1 -1 0.07 19828 1 0.00 -1 -1 32824 -1 -1 2 21 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64200 21 11 76 77 1 49 34 17 17 289 -1 unnamed_device 24.2 MiB 0.01 128 62.7 MiB 0.01 0.00 0.732132 -20.0804 -0.732132 0.732132 0.77 3.9502e-05 3.0291e-05 0.00150579 0.00120551 34 442 39 6.99608e+06 29431.4 618332. 2139.56 2.31 0.0181121 0.0147241 25762 151098 -1 359 16 287 287 17623 5297 0 0 17623 5297 287 287 0 0 1013 850 0 0 1544 1122 0 0 287 287 0 0 6322 1508 0 0 8170 1243 0 0 287 0 0 0 0 0 287 0 0 1.08603 1.08603 -25.9857 -1.08603 0 0 787024. 2723.27 0.40 0.01 0.13 -1 -1 0.40 0.00213433 0.00184835 16 -1 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml adder_011bits.v common 4.88 vpr 62.78 MiB -1 -1 0.07 19920 1 0.01 -1 -1 32836 -1 -1 3 23 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64284 23 12 83 84 1 54 38 17 17 289 -1 unnamed_device 24.3 MiB 0.01 263 62.8 MiB 0.01 0.00 0.834592 -24.7199 -0.834592 0.834592 0.76 4.3525e-05 3.2374e-05 0.00171758 0.00137872 34 620 15 6.99608e+06 44147 618332. 2139.56 2.11 0.0160455 0.0131479 25762 151098 -1 559 13 220 220 19730 4552 0 0 19730 4552 220 220 0 0 821 677 0 0 1226 951 0 0 220 220 0 0 8623 1208 0 0 8620 1276 0 0 220 0 0 0 0 0 220 0 0 1.08603 1.08603 -32.2403 -1.08603 0 0 787024. 2723.27 0.27 0.01 0.10 -1 -1 0.27 0.00208377 0.0018335 17 -1 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml adder_012bits.v common 4.31 vpr 62.93 MiB -1 -1 0.08 19692 1 0.01 -1 -1 33028 -1 -1 3 25 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64444 25 13 90 91 1 60 41 17 17 289 -1 unnamed_device 24.5 MiB 0.01 197 62.9 MiB 0.01 0.00 0.765132 -24.2158 -0.765132 0.765132 0.98 4.2935e-05 3.3112e-05 0.00148999 0.00121165 26 723 17 6.99608e+06 44147 503264. 1741.40 1.69 0.0150449 0.0123237 24322 120374 -1 572 14 334 334 29884 8481 0 0 29884 8481 334 334 0 0 1334 1182 0 0 2034 1559 0 0 334 334 0 0 12169 2300 0 0 13679 2772 0 0 334 0 0 0 0 0 334 0 0 1.15398 1.15398 -37.0055 -1.15398 0 0 618332. 2139.56 0.21 0.01 0.08 -1 -1 0.21 0.00241772 0.00212353 19 -1 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml adder_013bits.v common 3.68 vpr 62.68 MiB -1 -1 0.07 20020 1 0.01 -1 -1 33028 -1 -1 3 27 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64188 27 14 97 98 1 66 44 17 17 289 -1 unnamed_device 24.2 MiB 0.01 432 62.7 MiB 0.01 0.00 0.787132 -33.7773 -0.787132 0.787132 0.76 4.7229e-05 3.7086e-05 0.00198104 0.00163001 34 884 12 6.99608e+06 44147 618332. 2139.56 1.10 0.0146612 0.0121414 25762 151098 -1 840 16 358 358 37993 7912 0 0 37993 7912 358 358 0 0 1280 1113 0 0 2182 1549 0 0 358 358 0 0 17105 2374 0 0 16710 2160 0 0 358 0 0 0 0 0 358 0 0 1.15203 1.15203 -43.3033 -1.15203 0 0 787024. 2723.27 0.40 0.01 0.14 -1 -1 0.40 0.00282319 0.00246392 20 -1 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml adder_014bits.v common 4.54 vpr 63.02 MiB -1 -1 0.07 19872 1 0.00 -1 -1 33120 -1 -1 4 29 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64532 29 15 104 105 1 72 48 17 17 289 -1 unnamed_device 24.4 MiB 0.01 521 63.0 MiB 0.01 0.00 0.798132 -35.6277 -0.798132 0.798132 0.78 5.1493e-05 4.0522e-05 0.00249584 0.00183271 34 972 14 6.99608e+06 58862.7 618332. 2139.56 1.94 0.0252505 0.0208742 25762 151098 -1 914 14 353 353 38898 8040 0 0 38898 8040 353 353 0 0 1347 1166 0 0 1991 1534 0 0 353 353 0 0 18805 2274 0 0 16049 2360 0 0 353 0 0 0 0 0 353 0 0 1.13003 1.13003 -46.7311 -1.13003 0 0 787024. 2723.27 0.27 0.01 0.12 -1 -1 0.27 0.00269864 0.00238043 23 -1 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml adder_015bits.v common 4.57 vpr 62.97 MiB -1 -1 0.08 20324 1 0.01 -1 -1 32992 -1 -1 3 31 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64480 31 16 111 112 1 78 50 17 17 289 -1 unnamed_device 24.4 MiB 0.02 266 63.0 MiB 0.02 0.00 1.04416 -32.4115 -1.04416 1.04416 0.83 5.7979e-05 4.5419e-05 0.00356962 0.00292961 30 879 32 6.99608e+06 44147 556674. 1926.21 1.95 0.0264354 0.022097 25186 138497 -1 550 14 360 360 19919 5402 0 0 19919 5402 360 360 0 0 1199 1041 0 0 1747 1270 0 0 360 360 0 0 7807 1227 0 0 8446 1144 0 0 360 0 0 0 0 0 360 0 0 1.16103 1.16103 -40.7421 -1.16103 0 0 706193. 2443.58 0.24 0.01 0.09 -1 -1 0.24 0.00291894 0.00258425 24 -1 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml adder_016bits.v common 3.81 vpr 62.94 MiB -1 -1 0.06 20092 1 0.01 -1 -1 32900 -1 -1 4 33 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64452 33 17 118 119 1 81 54 17 17 289 -1 unnamed_device 24.3 MiB 0.02 280 62.9 MiB 0.02 0.00 1.05516 -34.379 -1.05516 1.05516 0.90 5.965e-05 4.6796e-05 0.00358087 0.00289246 34 801 16 6.99608e+06 58862.7 618332. 2139.56 1.02 0.0163016 0.0136407 25762 151098 -1 613 18 394 394 36074 9197 0 0 36074 9197 394 394 0 0 1525 1370 0 0 2626 1839 0 0 394 394 0 0 14799 2646 0 0 16336 2554 0 0 394 0 0 0 0 0 394 0 0 1.34133 1.34133 -48.4889 -1.34133 0 0 787024. 2723.27 0.26 0.01 0.09 -1 -1 0.26 0.00364797 0.00321321 25 -1 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml adder_018bits.v common 3.83 vpr 63.00 MiB -1 -1 0.08 20320 1 0.01 -1 -1 32732 -1 -1 4 37 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64516 37 19 132 133 1 87 60 17 17 289 -1 unnamed_device 24.6 MiB 0.02 365 63.0 MiB 0.02 0.00 1.08816 -40.2538 -1.08816 1.08816 0.77 7.3611e-05 5.9625e-05 0.00445878 0.00364622 34 1005 50 6.99608e+06 58862.7 618332. 2139.56 1.25 0.0233505 0.019594 25762 151098 -1 767 14 430 430 39121 9099 0 0 39121 9099 430 430 0 0 1506 1316 0 0 2328 1702 0 0 430 430 0 0 16522 2782 0 0 17905 2439 0 0 430 0 0 0 0 0 430 0 0 1.24903 1.24903 -54.0538 -1.24903 0 0 787024. 2723.27 0.40 0.01 0.09 -1 -1 0.40 0.00345785 0.00308041 28 -1 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml adder_020bits.v common 3.84 vpr 63.11 MiB -1 -1 0.08 20136 1 0.01 -1 -1 32908 -1 -1 4 41 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64620 41 21 146 147 1 94 66 17 17 289 -1 unnamed_device 24.7 MiB 0.02 346 63.1 MiB 0.02 0.00 1.09916 -44.1677 -1.09916 1.09916 0.86 7.3764e-05 5.8453e-05 0.00475998 0.003878 34 1110 29 6.99608e+06 58862.7 618332. 2139.56 1.11 0.0232789 0.0196588 25762 151098 -1 792 21 529 529 52785 12921 0 0 52785 12921 529 529 0 0 1935 1691 0 0 3360 2202 0 0 529 529 0 0 22434 4042 0 0 23998 3928 0 0 529 0 0 0 0 0 529 0 0 1.19403 1.19403 -56.5346 -1.19403 0 0 787024. 2723.27 0.36 0.02 0.10 -1 -1 0.36 0.00481206 0.00424912 31 -1 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml adder_022bits.v common 5.37 vpr 63.21 MiB -1 -1 0.07 20240 1 0.01 -1 -1 33212 -1 -1 5 45 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64732 45 23 160 161 1 107 73 17 17 289 -1 unnamed_device 24.7 MiB 0.02 464 63.2 MiB 0.07 0.00 1.12116 -49.1907 -1.12116 1.12116 0.79 8.9899e-05 7.3912e-05 0.0163892 0.0152992 30 1288 29 6.99608e+06 73578.4 556674. 1926.21 2.80 0.0552934 0.0485105 25186 138497 -1 870 15 626 626 54005 16626 0 0 54005 16626 626 626 0 0 2308 2050 0 0 3076 2432 0 0 626 626 0 0 23493 5643 0 0 23876 5249 0 0 626 0 0 0 0 0 626 0 0 1.29498 1.29498 -67.0436 -1.29498 0 0 706193. 2443.58 0.24 0.02 0.09 -1 -1 0.24 0.00471483 0.00423295 34 -1 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml adder_024bits.v common 4.13 vpr 63.23 MiB -1 -1 0.08 20364 1 0.01 -1 -1 33036 -1 -1 5 49 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64752 49 25 174 175 1 118 79 17 17 289 -1 unnamed_device 24.8 MiB 0.02 443 63.2 MiB 0.04 0.00 1.14316 -53.0048 -1.14316 1.14316 0.76 9.6691e-05 7.877e-05 0.00693051 0.00568162 36 1373 24 6.99608e+06 73578.4 648988. 2245.63 1.39 0.0306227 0.026151 26050 158493 -1 1004 17 635 635 54060 13300 0 0 54060 13300 635 635 0 0 2284 1970 0 0 3626 2595 0 0 635 635 0 0 22713 3786 0 0 24167 3679 0 0 635 0 0 0 0 0 635 0 0 1.33033 1.33033 -69.9442 -1.33033 0 0 828058. 2865.25 0.28 0.02 0.10 -1 -1 0.28 0.00501991 0.0044766 37 -1 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml adder_028bits.v common 4.43 vpr 63.38 MiB -1 -1 0.08 20424 1 0.00 -1 -1 33096 -1 -1 6 57 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64900 57 29 202 203 1 141 92 17 17 289 -1 unnamed_device 24.8 MiB 0.03 563 63.4 MiB 0.04 0.00 1.18716 -62.7696 -1.18716 1.18716 0.78 0.000125862 0.000102292 0.00818708 0.0067827 40 1524 35 6.99608e+06 88294.1 706193. 2443.58 1.79 0.04703 0.0402429 26914 176310 -1 1229 17 847 847 85010 21210 0 0 85010 21210 847 847 0 0 3125 2723 0 0 5338 3738 0 0 847 847 0 0 36068 6649 0 0 38785 6406 0 0 847 0 0 0 0 0 847 0 0 1.35618 1.35618 -82.1548 -1.35618 0 0 926341. 3205.33 0.32 0.03 0.12 -1 -1 0.32 0.0064501 0.00580517 43 -1 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml adder_032bits.v common 4.85 vpr 63.63 MiB -1 -1 0.08 20208 1 0.01 -1 -1 33020 -1 -1 7 65 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65156 65 33 230 231 1 162 105 17 17 289 -1 unnamed_device 25.2 MiB 0.03 752 63.6 MiB 0.05 0.00 1.47719 -78.6599 -1.47719 1.47719 0.76 0.00012519 0.000102335 0.00907963 0.00750609 38 1746 50 6.99608e+06 103010 678818. 2348.85 1.96 0.0582654 0.0503493 26626 170182 -1 1428 16 820 820 80240 18069 0 0 80240 18069 820 820 0 0 2910 2541 0 0 4646 3301 0 0 820 820 0 0 36579 5180 0 0 34465 5407 0 0 820 0 0 0 0 0 820 0 0 1.44933 1.44933 -98.3496 -1.44933 0 0 902133. 3121.57 0.39 0.02 0.11 -1 -1 0.39 0.00673128 0.00605421 49 -1 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml adder_048bits.v common 7.10 vpr 64.55 MiB -1 -1 0.09 20420 1 0.02 -1 -1 33236 -1 -1 10 97 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 66096 97 49 342 343 1 243 156 17 17 289 -1 unnamed_device 25.8 MiB 0.11 1410 64.5 MiB 0.09 0.00 1.88822 -134.864 -1.88822 1.88822 0.89 0.000227693 0.000195479 0.0164655 0.0141915 52 2729 18 6.99608e+06 147157 926341. 3205.33 4.01 0.10151 0.089571 29218 227130 -1 2302 17 987 987 106104 21984 0 0 106104 21984 987 987 0 0 3540 2987 0 0 5567 4050 0 0 987 987 0 0 46175 6716 0 0 48848 6257 0 0 987 0 0 0 0 0 987 0 0 1.50903 1.50903 -150.391 -1.50903 0 0 1.14541e+06 3963.36 0.39 0.04 0.15 -1 -1 0.39 0.0115392 0.0105572 73 -1 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml adder_064bits.v common 5.35 vpr 64.95 MiB -1 -1 0.09 20576 1 0.02 -1 -1 33472 -1 -1 13 129 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 66504 129 65 454 455 1 324 207 17 17 289 -1 unnamed_device 26.2 MiB 0.06 2173 64.9 MiB 0.14 0.00 2.29925 -202.532 -2.29925 2.29925 0.86 0.000324211 0.000283473 0.0232953 0.0204609 52 3996 46 6.99608e+06 191304 926341. 3205.33 2.16 0.118497 0.106431 29218 227130 -1 3449 17 1441 1441 174648 34761 0 0 174648 34761 1441 1441 0 0 4961 4284 0 0 8691 5753 0 0 1441 1441 0 0 83299 10413 0 0 74815 11429 0 0 1441 0 0 0 0 0 1441 0 0 1.77103 1.77103 -220.94 -1.77103 0 0 1.14541e+06 3963.36 0.40 0.06 0.16 -1 -1 0.40 0.0174204 0.0160875 97 -1 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml adder_003bits.v common 3.03 vpr 61.98 MiB -1 -1 0.06 20020 1 0.03 -1 -1 35380 -1 -1 1 7 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 63464 7 4 21 25 1 11 12 17 17 289 -1 unnamed_device 23.6 MiB 0.00 64 62.0 MiB 0.01 0.00 0.942216 -7.18451 -0.942216 0.942216 1.03 1.9809e-05 1.2823e-05 0.000201231 0.000169788 18 95 2 6.79088e+06 13472 376052. 1301.22 0.42 0.000744669 0.000646915 22222 88205 -1 93 2 12 12 598 176 0 0 598 176 12 12 0 0 47 30 0 0 58 47 0 0 12 12 0 0 267 37 0 0 202 38 0 0 12 0 0 0 0 0 12 0 0 0.942216 0.942216 -7.93631 -0.942216 0 0 470940. 1629.55 0.16 0.00 0.06 -1 -1 0.16 0.000485788 0.000437432 6 4 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml adder_004bits.v common 3.15 vpr 62.24 MiB -1 -1 0.07 19800 2 0.03 -1 -1 35172 -1 -1 1 9 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 63732 9 5 28 33 1 16 15 17 17 289 -1 unnamed_device 23.8 MiB 0.01 35 62.2 MiB 0.00 0.00 0.883748 -8.8411 -0.883748 0.883748 0.87 2.047e-05 1.4909e-05 0.000776618 0.000603557 24 114 7 6.79088e+06 13472 470940. 1629.55 0.59 0.00332163 0.00264848 23374 113417 -1 87 8 46 46 1300 526 0 0 1300 526 46 46 0 0 161 118 0 0 230 182 0 0 46 46 0 0 335 102 0 0 482 32 0 0 46 0 0 0 0 0 46 0 0 0.883748 0.883748 -9.5929 -0.883748 0 0 586450. 2029.24 0.20 0.00 0.07 -1 -1 0.20 0.000789424 0.000694047 8 6 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml adder_005bits.v common 3.93 vpr 61.99 MiB -1 -1 0.07 19784 2 0.03 -1 -1 35132 -1 -1 2 11 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 63476 11 6 34 40 1 23 19 17 17 289 -1 unnamed_device 23.6 MiB 0.01 59 62.0 MiB 0.00 0.00 1.02368 -11.2072 -1.02368 1.02368 0.76 2.2705e-05 1.6338e-05 0.000610891 0.000491717 22 190 13 6.79088e+06 26944 443629. 1535.05 1.53 0.00717227 0.00571703 22798 101617 -1 167 8 60 68 3327 1053 0 0 3327 1053 68 62 0 0 237 201 0 0 320 257 0 0 68 63 0 0 1166 253 0 0 1468 217 0 0 68 0 0 8 6 2 100 0 0 1.02368 1.02368 -14.4258 -1.02368 0 0 531479. 1839.03 0.19 0.00 0.09 -1 -1 0.19 0.000946106 0.000837631 10 7 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml adder_006bits.v common 4.32 vpr 61.94 MiB -1 -1 0.07 19868 3 0.03 -1 -1 35156 -1 -1 2 13 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 63424 13 7 41 48 1 30 22 17 17 289 -1 unnamed_device 23.5 MiB 0.01 86 61.9 MiB 0.00 0.00 1.05944 -13.8628 -1.05944 1.05944 0.91 2.5001e-05 1.8634e-05 0.000577402 0.000472423 26 235 8 6.79088e+06 26944 503264. 1741.40 1.78 0.00807482 0.00650366 23662 119890 -1 214 10 93 97 5083 1675 0 0 5083 1675 97 94 0 0 387 332 0 0 546 451 0 0 97 96 0 0 1821 344 0 0 2135 358 0 0 97 0 0 4 2 2 113 0 0 1.05944 1.05944 -17.4181 -1.05944 0 0 618332. 2139.56 0.21 0.00 0.13 -1 -1 0.21 0.00116519 0.00102848 11 9 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml adder_007bits.v common 4.46 vpr 62.21 MiB -1 -1 0.07 19808 3 0.03 -1 -1 35356 -1 -1 2 15 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 63708 15 8 47 55 1 36 25 17 17 289 -1 unnamed_device 23.7 MiB 0.01 90 62.2 MiB 0.01 0.00 1.13784 -16.3026 -1.13784 1.13784 0.85 2.9669e-05 2.2385e-05 0.00114849 0.00091185 26 340 10 6.79088e+06 26944 503264. 1741.40 1.96 0.00799352 0.00651583 23662 119890 -1 271 10 158 179 7439 2692 0 0 7439 2692 179 170 0 0 633 515 0 0 1003 774 0 0 179 172 0 0 2354 582 0 0 3091 479 0 0 179 0 0 21 11 19 272 0 0 1.13784 1.13784 -19.2706 -1.13784 0 0 618332. 2139.56 0.21 0.01 0.07 -1 -1 0.21 0.00136675 0.00121308 13 10 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml adder_008bits.v common 4.26 vpr 62.33 MiB -1 -1 0.08 20036 3 0.04 -1 -1 35440 -1 -1 2 17 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 63828 17 9 56 65 1 43 28 17 17 289 -1 unnamed_device 23.8 MiB 0.04 259 62.3 MiB 0.01 0.00 1.27433 -22.4371 -1.27433 1.27433 0.89 3.6666e-05 2.8066e-05 0.00122118 0.000992798 28 512 12 6.79088e+06 26944 531479. 1839.03 1.58 0.0115094 0.00944994 23950 126010 -1 498 12 197 236 21242 4861 0 0 21242 4861 236 223 0 0 897 772 0 0 1405 1066 0 0 236 225 0 0 9541 1211 0 0 8927 1364 0 0 236 0 0 39 27 39 439 0 0 1.27433 1.27433 -27.1593 -1.27433 0 0 648988. 2245.63 0.34 0.01 0.11 -1 -1 0.34 0.00181355 0.00161511 16 14 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml adder_009bits.v common 4.41 vpr 62.14 MiB -1 -1 0.06 19736 4 0.03 -1 -1 35176 -1 -1 3 19 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 63628 19 10 60 70 1 49 32 17 17 289 -1 unnamed_device 23.6 MiB 0.04 132 62.1 MiB 0.01 0.00 1.1736 -20.6259 -1.1736 1.1736 0.94 3.8086e-05 2.9079e-05 0.00176592 0.00140821 28 481 45 6.79088e+06 40416 531479. 1839.03 1.68 0.0183592 0.014997 23950 126010 -1 400 12 244 254 15313 4813 0 0 15313 4813 254 247 0 0 942 829 0 0 1366 1088 0 0 254 249 0 0 5927 1210 0 0 6570 1190 0 0 254 0 0 10 11 14 309 0 0 1.34919 1.34919 -26.2115 -1.34919 0 0 648988. 2245.63 0.23 0.01 0.08 -1 -1 0.23 0.0018321 0.00161759 17 13 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml adder_010bits.v common 3.33 vpr 62.32 MiB -1 -1 0.07 20024 4 0.04 -1 -1 35112 -1 -1 3 21 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 63816 21 11 69 80 1 55 35 17 17 289 -1 unnamed_device 24.0 MiB 0.16 159 62.3 MiB 0.01 0.00 1.60338 -26.0076 -1.60338 1.60338 0.86 4.1426e-05 3.185e-05 0.00257023 0.00203649 28 598 26 6.79088e+06 40416 531479. 1839.03 0.65 0.0113728 0.00942098 23950 126010 -1 515 14 306 366 20049 6422 0 0 20049 6422 366 322 0 0 1338 1152 0 0 2133 1666 0 0 366 328 0 0 7378 1543 0 0 8468 1411 0 0 366 0 0 60 68 34 648 0 0 1.60338 1.60338 -32.3979 -1.60338 0 0 648988. 2245.63 0.21 0.01 0.08 -1 -1 0.21 0.00236702 0.0020968 21 17 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml adder_011bits.v common 3.50 vpr 62.22 MiB -1 -1 0.06 19928 5 0.05 -1 -1 34624 -1 -1 3 23 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 63712 23 12 76 88 1 61 38 17 17 289 -1 unnamed_device 23.8 MiB 0.09 207 62.2 MiB 0.01 0.00 1.67834 -28.9869 -1.67834 1.67834 0.74 5.1262e-05 4.035e-05 0.00223683 0.00184574 34 522 15 6.79088e+06 40416 618332. 2139.56 0.95 0.0145695 0.0121691 25102 150614 -1 468 11 230 278 16053 4659 0 0 16053 4659 278 253 0 0 1097 942 0 0 1629 1299 0 0 278 255 0 0 5566 1086 0 0 7205 824 0 0 278 0 0 48 50 10 490 0 0 1.72519 1.72519 -33.2384 -1.72519 0 0 787024. 2723.27 0.26 0.01 0.09 -1 -1 0.26 0.00239149 0.00215511 22 19 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml adder_012bits.v common 5.09 vpr 62.56 MiB -1 -1 0.07 20084 5 0.04 -1 -1 35100 -1 -1 3 25 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64064 25 13 83 96 1 66 41 17 17 289 -1 unnamed_device 24.1 MiB 0.16 395 62.6 MiB 0.01 0.00 1.67834 -38.0476 -1.67834 1.67834 0.74 5.5477e-05 4.4303e-05 0.00274077 0.00223234 34 812 13 6.79088e+06 40416 618332. 2139.56 2.40 0.0246888 0.0206201 25102 150614 -1 738 13 246 294 19211 4497 0 0 19211 4497 294 262 0 0 1047 834 0 0 1552 1202 0 0 294 266 0 0 8455 942 0 0 7569 991 0 0 294 0 0 48 15 43 496 0 0 1.68948 1.68948 -43.8671 -1.68948 0 0 787024. 2723.27 0.27 0.01 0.09 -1 -1 0.27 0.00273652 0.00244498 23 21 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml adder_013bits.v common 5.11 vpr 62.37 MiB -1 -1 0.08 20104 5 0.05 -1 -1 35212 -1 -1 4 27 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 63868 27 14 91 105 1 72 45 17 17 289 -1 unnamed_device 23.9 MiB 0.25 335 62.4 MiB 0.01 0.00 1.81483 -36.8868 -1.81483 1.81483 0.83 5.6195e-05 4.4292e-05 0.00279486 0.00228044 34 748 14 6.79088e+06 53888 618332. 2139.56 2.30 0.022438 0.0188421 25102 150614 -1 687 14 268 365 30390 7128 0 0 30390 7128 365 298 0 0 1304 1088 0 0 2333 1592 0 0 365 304 0 0 13217 1898 0 0 12806 1948 0 0 365 0 0 97 53 100 819 0 0 1.81483 1.81483 -44.0289 -1.81483 0 0 787024. 2723.27 0.36 0.03 0.10 -1 -1 0.36 0.00333413 0.00300244 27 24 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml adder_014bits.v common 4.88 vpr 62.43 MiB -1 -1 0.08 20380 6 0.04 -1 -1 35156 -1 -1 4 29 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 63924 29 15 95 110 1 77 48 17 17 289 -1 unnamed_device 23.9 MiB 0.18 230 62.4 MiB 0.02 0.00 2.06549 -38.9139 -2.06549 2.06549 1.00 6.3924e-05 5.1345e-05 0.00370408 0.00305221 30 764 49 6.79088e+06 53888 556674. 1926.21 2.01 0.0289213 0.0242351 24526 138013 -1 573 27 408 477 81681 51038 0 0 81681 51038 477 426 0 0 1665 1460 0 0 3766 2607 0 0 477 431 0 0 39220 23780 0 0 36076 22334 0 0 477 0 0 69 73 42 799 0 0 2.06549 2.06549 -45.9307 -2.06549 0 0 706193. 2443.58 0.24 0.03 0.09 -1 -1 0.24 0.00477458 0.00417776 28 23 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml adder_015bits.v common 4.23 vpr 62.51 MiB -1 -1 0.08 20168 6 0.04 -1 -1 35164 -1 -1 5 31 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64012 31 16 104 120 1 82 52 17 17 289 -1 unnamed_device 24.0 MiB 0.34 239 62.5 MiB 0.01 0.00 2.14389 -42.4289 -2.14389 2.14389 0.91 6.2211e-05 4.9396e-05 0.00307133 0.00254929 36 728 50 6.79088e+06 67360 648988. 2245.63 1.20 0.0218706 0.0183596 25390 158009 -1 591 16 393 555 31490 10203 0 0 31490 10203 555 414 0 0 1900 1620 0 0 3029 2216 0 0 555 426 0 0 12377 2741 0 0 13074 2786 0 0 555 0 0 162 183 105 1417 0 0 2.31598 2.31598 -50.8908 -2.31598 0 0 828058. 2865.25 0.33 0.01 0.13 -1 -1 0.33 0.00374942 0.00333443 31 27 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml adder_016bits.v common 4.12 vpr 62.59 MiB -1 -1 0.08 20212 7 0.04 -1 -1 35228 -1 -1 5 33 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64092 33 17 112 129 1 88 55 17 17 289 -1 unnamed_device 24.2 MiB 0.62 556 62.6 MiB 0.03 0.00 2.39454 -57.2401 -2.39454 2.39454 0.90 6.9486e-05 5.5494e-05 0.0052807 0.00434155 34 1114 15 6.79088e+06 67360 618332. 2139.56 0.97 0.0232246 0.0195951 25102 150614 -1 1022 12 344 445 36019 8191 0 0 36019 8191 445 386 0 0 1661 1390 0 0 2726 2004 0 0 445 406 0 0 15886 2038 0 0 14856 1967 0 0 445 0 0 101 98 86 978 0 0 2.39454 2.39454 -63.3406 -2.39454 0 0 787024. 2723.27 0.26 0.01 0.09 -1 -1 0.26 0.00386796 0.00348179 32 30 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml adder_018bits.v common 5.67 vpr 62.75 MiB -1 -1 0.09 20104 7 0.05 -1 -1 35396 -1 -1 6 37 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64252 37 19 127 146 1 99 62 17 17 289 -1 unnamed_device 24.3 MiB 1.09 365 62.7 MiB 0.01 0.00 3.00001 -61.4437 -3.00001 3.00001 0.83 8.5815e-05 7.0265e-05 0.00306396 0.00260118 26 1105 46 6.79088e+06 80832 503264. 1741.40 1.92 0.0282967 0.0242808 23662 119890 -1 926 11 377 462 28459 8277 0 0 28459 8277 462 398 0 0 1697 1397 0 0 2671 1933 0 0 462 416 0 0 10525 1976 0 0 12642 2157 0 0 462 0 0 85 83 67 867 0 0 3.12531 3.12531 -73.5978 -3.12531 0 0 618332. 2139.56 0.39 0.01 0.07 -1 -1 0.39 0.00434328 0.003977 37 35 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml adder_020bits.v common 3.68 vpr 62.73 MiB -1 -1 0.08 20252 8 0.04 -1 -1 35124 -1 -1 6 41 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64236 41 21 139 160 1 106 68 17 17 289 -1 unnamed_device 24.2 MiB 0.40 488 62.7 MiB 0.02 0.00 2.60599 -64.8181 -2.60599 2.60599 0.76 8.913e-05 7.241e-05 0.0036273 0.00305602 30 1266 30 6.79088e+06 80832 556674. 1926.21 0.72 0.0213524 0.0183555 24526 138013 -1 1073 14 469 593 48159 11835 0 0 48159 11835 593 505 0 0 2071 1777 0 0 3262 2422 0 0 593 510 0 0 20031 3313 0 0 21609 3308 0 0 593 0 0 124 72 141 1194 0 0 2.60599 2.60599 -77.3481 -2.60599 0 0 706193. 2443.58 0.34 0.02 0.10 -1 -1 0.34 0.00475294 0.00430766 41 37 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml adder_022bits.v common 3.99 vpr 62.74 MiB -1 -1 0.09 20356 9 0.05 -1 -1 35024 -1 -1 6 45 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64244 45 23 153 176 1 119 74 17 17 289 -1 unnamed_device 24.2 MiB 0.36 488 62.7 MiB 0.03 0.00 2.98195 -75.096 -2.98195 2.98195 0.74 9.6051e-05 7.7368e-05 0.00623628 0.00517535 34 1162 32 6.79088e+06 80832 618332. 2139.56 1.15 0.0297926 0.0256582 25102 150614 -1 990 16 406 495 33959 8793 0 0 33959 8793 495 427 0 0 1816 1562 0 0 2740 2082 0 0 495 434 0 0 14526 2117 0 0 13887 2171 0 0 495 0 0 89 55 87 932 0 0 2.98195 2.98195 -85.582 -2.98195 0 0 787024. 2723.27 0.27 0.02 0.10 -1 -1 0.27 0.00546738 0.00492702 43 41 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml adder_024bits.v common 6.90 vpr 62.95 MiB -1 -1 0.09 20220 10 0.05 -1 -1 35404 -1 -1 8 49 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64460 49 25 166 191 1 133 82 17 17 289 -1 unnamed_device 24.5 MiB 0.84 417 62.9 MiB 0.03 0.00 3.1857 -81.7769 -3.1857 3.1857 0.75 0.000103454 8.3196e-05 0.00726505 0.00608279 42 1223 42 6.79088e+06 107776 744469. 2576.02 3.29 0.0624513 0.0534964 26542 182613 -1 859 23 591 687 90067 46576 0 0 90067 46576 687 630 0 0 2513 2199 0 0 4921 3565 0 0 687 643 0 0 41151 19783 0 0 40108 19756 0 0 687 0 0 96 66 111 1152 0 0 3.1857 3.1857 -88.1672 -3.1857 0 0 949917. 3286.91 0.40 0.03 0.12 -1 -1 0.40 0.0078382 0.00702426 48 44 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml adder_028bits.v common 7.03 vpr 62.95 MiB -1 -1 0.09 20144 11 0.05 -1 -1 35176 -1 -1 8 57 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64464 57 29 198 227 1 158 94 17 17 289 -1 unnamed_device 24.3 MiB 1.13 739 63.0 MiB 0.04 0.00 3.77654 -110.336 -3.77654 3.77654 0.75 0.000255203 0.000231613 0.00933438 0.00797875 36 1787 26 6.79088e+06 107776 648988. 2245.63 3.24 0.0682585 0.0599672 25390 158009 -1 1554 13 630 871 61399 14860 0 0 61399 14860 871 705 0 0 3124 2676 0 0 5165 3653 0 0 871 734 0 0 24111 3763 0 0 27257 3329 0 0 871 0 0 241 215 206 2097 0 0 3.90184 3.90184 -126.336 -3.90184 0 0 828058. 2865.25 0.25 0.02 0.10 -1 -1 0.25 0.00669981 0.00613233 59 56 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml adder_032bits.v common 5.92 vpr 63.09 MiB -1 -1 0.08 20404 13 0.06 -1 -1 35196 -1 -1 9 65 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64600 65 33 224 257 1 176 107 17 17 289 -1 unnamed_device 24.6 MiB 1.38 978 63.1 MiB 0.06 0.00 4.44928 -138.947 -4.44928 4.44928 0.76 0.000147123 0.000121454 0.0121151 0.0101285 30 2113 19 6.79088e+06 121248 556674. 1926.21 2.04 0.0628112 0.054227 24526 138013 -1 1752 13 638 823 49472 12407 0 0 49472 12407 823 674 0 0 2898 2408 0 0 3942 3063 0 0 823 688 0 0 20657 2738 0 0 20329 2836 0 0 823 0 0 185 90 204 1680 0 0 4.44928 4.44928 -153.106 -4.44928 0 0 706193. 2443.58 0.24 0.02 0.08 -1 -1 0.24 0.00781818 0.00712236 66 62 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml adder_048bits.v common 7.31 vpr 64.07 MiB -1 -1 0.12 20652 19 0.09 -1 -1 35224 -1 -1 13 97 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65608 97 49 340 389 1 267 159 17 17 289 -1 unnamed_device 25.4 MiB 2.73 1350 64.1 MiB 0.07 0.00 6.71973 -260.111 -6.71973 6.71973 0.79 0.000258713 0.000219546 0.0142828 0.0123068 34 3400 44 6.79088e+06 175136 618332. 2139.56 1.67 0.0869368 0.0775065 25102 150614 -1 2874 14 1086 1469 111661 26701 0 0 111661 26701 1469 1253 0 0 5301 4488 0 0 8750 6399 0 0 1469 1279 0 0 47799 6473 0 0 46873 6809 0 0 1469 0 0 383 322 371 3389 0 0 6.80583 6.80583 -290.76 -6.80583 0 0 787024. 2723.27 0.24 0.04 0.09 -1 -1 0.24 0.0135979 0.0125698 100 98 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml adder_064bits.v common 7.97 vpr 64.83 MiB -1 -1 0.12 21008 26 0.09 -1 -1 35696 -1 -1 18 129 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 66384 129 65 453 518 1 350 212 17 17 289 -1 unnamed_device 26.1 MiB 3.61 1996 64.8 MiB 0.16 0.00 9.19737 -440.937 -9.19737 9.19737 0.76 0.000377527 0.000327523 0.0349416 0.0305215 36 4210 30 6.79088e+06 242496 648988. 2245.63 1.37 0.12314 0.110208 25390 158009 -1 3458 13 1274 1710 114779 27867 0 0 114779 27867 1710 1412 0 0 6056 5047 0 0 9571 7081 0 0 1710 1445 0 0 48317 6406 0 0 47415 6476 0 0 1710 0 0 436 312 382 3784 0 0 9.19737 9.19737 -464.618 -9.19737 0 0 828058. 2865.25 0.38 0.04 0.10 -1 -1 0.38 0.0182077 0.0169171 129 131 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml adder_003bits.v common 2.77 vpr 62.43 MiB -1 -1 0.07 19996 1 0.01 -1 -1 32976 -1 -1 1 7 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 63924 7 4 27 28 1 13 12 17 17 289 -1 unnamed_device 24.0 MiB 0.02 38 62.4 MiB 0.00 0.00 0.488083 -5.72471 -0.488083 0.488083 0.88 1.8175e-05 1.1892e-05 0.000330992 0.000252048 12 80 4 6.87369e+06 13973.8 243793. 843.575 0.32 0.000971923 0.000804442 21730 64085 -1 89 5 32 32 2061 627 0 0 2061 627 32 32 0 0 135 91 0 0 167 135 0 0 32 32 0 0 698 192 0 0 997 145 0 0 32 0 0 0 0 0 32 0 0 0.74674 0.74674 -7.98012 -0.74674 0 0 332735. 1151.33 0.13 0.00 0.05 -1 -1 0.13 0.000582792 0.000513938 8 -1 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml adder_004bits.v common 3.79 vpr 62.30 MiB -1 -1 0.07 19824 1 0.01 -1 -1 33020 -1 -1 2 9 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 63796 9 5 34 35 1 20 16 17 17 289 -1 unnamed_device 23.9 MiB 0.03 41 62.3 MiB 0.00 0.00 0.663773 -8.29102 -0.663773 0.663773 0.80 1.9208e-05 1.3724e-05 0.000543111 0.000423266 26 108 8 6.87369e+06 27947.7 503264. 1741.40 1.32 0.0062435 0.00489364 24322 120374 -1 121 11 55 55 3150 1018 0 0 3150 1018 55 55 0 0 218 172 0 0 284 233 0 0 55 55 0 0 1210 264 0 0 1328 239 0 0 55 0 0 0 0 0 55 0 0 0.789073 0.789073 -10.2958 -0.789073 0 0 618332. 2139.56 0.22 0.00 0.08 -1 -1 0.22 0.000885137 0.000758912 10 -1 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml adder_005bits.v common 3.09 vpr 62.52 MiB -1 -1 0.07 20068 1 0.00 -1 -1 33004 -1 -1 3 11 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64024 11 6 41 42 1 27 20 17 17 289 -1 unnamed_device 24.0 MiB 0.04 91 62.5 MiB 0.00 0.00 0.685773 -10.5905 -0.685773 0.685773 0.76 2.3069e-05 1.6448e-05 0.000466995 0.000369053 16 234 10 6.87369e+06 41921.5 332735. 1151.33 0.82 0.00213905 0.00176006 22306 75877 -1 215 10 133 133 7015 2206 0 0 7015 2206 133 133 0 0 480 382 0 0 587 492 0 0 133 133 0 0 2402 566 0 0 3280 500 0 0 133 0 0 0 0 0 133 0 0 1.02867 1.02867 -15.1686 -1.02867 0 0 414966. 1435.87 0.14 0.00 0.05 -1 -1 0.14 0.000957704 0.000820831 13 -1 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml adder_006bits.v common 5.29 vpr 62.68 MiB -1 -1 0.08 20112 1 0.00 -1 -1 32896 -1 -1 3 13 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64188 13 7 48 49 1 33 23 17 17 289 -1 unnamed_device 24.1 MiB 0.04 80 62.7 MiB 0.00 0.00 0.707773 -12.5849 -0.707773 0.707773 0.76 2.4111e-05 1.7871e-05 0.000933683 0.000723202 34 271 33 6.87369e+06 41921.5 618332. 2139.56 2.32 0.0135672 0.0105314 25762 151098 -1 218 20 301 301 17367 5523 0 0 17367 5523 301 301 0 0 1216 1041 0 0 1703 1403 0 0 301 301 0 0 6602 1132 0 0 7244 1345 0 0 301 0 0 0 0 0 301 0 0 0.958373 0.958373 -16.5945 -0.958373 0 0 787024. 2723.27 0.38 0.03 0.10 -1 -1 0.38 0.0125413 0.0122443 15 -1 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml adder_007bits.v common 3.18 vpr 62.59 MiB -1 -1 0.06 20084 1 0.01 -1 -1 33120 -1 -1 3 15 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64092 15 8 55 56 1 39 26 17 17 289 -1 unnamed_device 24.1 MiB 0.08 112 62.6 MiB 0.01 0.00 1.13846 -15.98 -1.13846 1.13846 0.88 2.8794e-05 2.1429e-05 0.00137984 0.00109913 26 304 17 6.87369e+06 41921.5 503264. 1741.40 0.53 0.00588592 0.00475905 24322 120374 -1 240 16 161 161 6837 2474 0 0 6837 2474 161 161 0 0 635 543 0 0 972 778 0 0 161 161 0 0 2371 437 0 0 2537 394 0 0 161 0 0 0 0 0 161 0 0 1.12264 1.12264 -18.7281 -1.12264 0 0 618332. 2139.56 0.21 0.01 0.08 -1 -1 0.21 0.0016185 0.00139953 17 -1 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml adder_008bits.v common 3.22 vpr 62.52 MiB -1 -1 0.06 20144 1 0.01 -1 -1 32924 -1 -1 3 17 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64016 17 9 62 63 1 42 29 17 17 289 -1 unnamed_device 23.9 MiB 0.05 123 62.5 MiB 0.01 0.00 0.964803 -17.8777 -0.964803 0.964803 0.76 3.6032e-05 2.7638e-05 0.00201013 0.00158931 26 319 15 6.87369e+06 41921.5 503264. 1741.40 0.80 0.00757369 0.00594565 24322 120374 -1 286 17 175 175 10718 3393 0 0 10718 3393 175 175 0 0 707 624 0 0 1203 1010 0 0 175 175 0 0 3866 770 0 0 4592 639 0 0 175 0 0 0 0 0 175 0 0 1.20697 1.20697 -23.626 -1.20697 0 0 618332. 2139.56 0.24 0.01 0.11 -1 -1 0.24 0.00214307 0.00187705 18 -1 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml adder_009bits.v common 4.43 vpr 62.43 MiB -1 -1 0.06 19956 1 0.01 -1 -1 33028 -1 -1 3 19 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 63932 19 10 69 70 1 45 32 17 17 289 -1 unnamed_device 23.8 MiB 0.05 132 62.4 MiB 0.01 0.00 0.975803 -19.7482 -0.975803 0.975803 0.76 3.987e-05 3.077e-05 0.00229654 0.00183054 28 386 18 6.87369e+06 41921.5 531479. 1839.03 1.90 0.0384589 0.0125133 24610 126494 -1 326 13 214 214 14496 4104 0 0 14496 4104 214 214 0 0 834 733 0 0 1180 973 0 0 214 214 0 0 5524 1084 0 0 6530 886 0 0 214 0 0 0 0 0 214 0 0 1.13667 1.13667 -26.1199 -1.13667 0 0 648988. 2245.63 0.24 0.01 0.08 -1 -1 0.24 0.00174029 0.00151337 20 -1 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml adder_010bits.v common 3.14 vpr 62.82 MiB -1 -1 0.07 19984 1 0.01 -1 -1 32892 -1 -1 3 21 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64324 21 11 76 77 1 48 35 17 17 289 -1 unnamed_device 24.4 MiB 0.05 153 62.8 MiB 0.01 0.00 0.986803 -22.4034 -0.986803 0.986803 0.82 3.8826e-05 2.9667e-05 0.00237388 0.00185956 28 442 24 6.87369e+06 41921.5 531479. 1839.03 0.60 0.00910422 0.00743675 24610 126494 -1 321 19 305 305 15557 4886 0 0 15557 4886 305 305 0 0 1140 991 0 0 1802 1412 0 0 305 305 0 0 5914 905 0 0 6091 968 0 0 305 0 0 0 0 0 305 0 0 1.14767 1.14767 -28.1842 -1.14767 0 0 648988. 2245.63 0.22 0.01 0.08 -1 -1 0.22 0.00232385 0.00199243 22 -1 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml adder_011bits.v common 5.15 vpr 62.88 MiB -1 -1 0.07 20016 1 0.00 -1 -1 32912 -1 -1 4 23 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64392 23 12 83 84 1 53 39 17 17 289 -1 unnamed_device 24.4 MiB 0.05 160 62.9 MiB 0.01 0.00 0.997803 -24.6718 -0.997803 0.997803 1.04 4.1025e-05 3.123e-05 0.00294112 0.00237866 32 451 12 6.87369e+06 55895.4 586450. 2029.24 2.22 0.0138935 0.0113748 25474 144626 -1 401 13 238 238 18203 4910 0 0 18203 4910 238 238 0 0 988 841 0 0 1458 1186 0 0 238 238 0 0 7501 1156 0 0 7780 1251 0 0 238 0 0 0 0 0 238 0 0 1.11467 1.11467 -31.1105 -1.11467 0 0 744469. 2576.02 0.28 0.01 0.09 -1 -1 0.28 0.00198468 0.00173206 24 -1 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml adder_012bits.v common 3.48 vpr 62.82 MiB -1 -1 0.07 19868 1 0.01 -1 -1 32904 -1 -1 4 25 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64328 25 13 90 91 1 60 42 17 17 289 -1 unnamed_device 24.4 MiB 0.05 197 62.8 MiB 0.01 0.00 1.0088 -27.5776 -1.0088 1.0088 0.77 4.5197e-05 3.4592e-05 0.0026224 0.00207088 32 666 20 6.87369e+06 55895.4 586450. 2029.24 0.71 0.0105093 0.00871659 25474 144626 -1 501 17 373 373 32112 8189 0 0 32112 8189 373 373 0 0 1443 1251 0 0 2280 1758 0 0 373 373 0 0 12748 2405 0 0 14895 2029 0 0 373 0 0 0 0 0 373 0 0 1.27297 1.27297 -35.8269 -1.27297 0 0 744469. 2576.02 0.38 0.01 0.10 -1 -1 0.38 0.00264124 0.00229599 26 -1 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml adder_013bits.v common 5.17 vpr 62.69 MiB -1 -1 0.07 20072 1 0.01 -1 -1 33016 -1 -1 4 27 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64196 27 14 97 98 1 67 45 17 17 289 -1 unnamed_device 24.2 MiB 0.05 211 62.7 MiB 0.02 0.00 1.0198 -28.9909 -1.0198 1.0198 0.78 4.9137e-05 3.7862e-05 0.00335875 0.00266566 34 760 33 6.87369e+06 55895.4 618332. 2139.56 2.57 0.0273812 0.0230697 25762 151098 -1 569 20 477 477 40000 10484 0 0 40000 10484 477 477 0 0 1850 1549 0 0 2758 2194 0 0 477 477 0 0 15365 3184 0 0 19073 2603 0 0 477 0 0 0 0 0 477 0 0 1.17597 1.17597 -38.285 -1.17597 0 0 787024. 2723.27 0.27 0.01 0.09 -1 -1 0.27 0.00316329 0.0027227 28 -1 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml adder_014bits.v common 3.81 vpr 62.78 MiB -1 -1 0.07 19784 1 0.00 -1 -1 32708 -1 -1 5 29 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64288 29 15 104 105 1 74 49 17 17 289 -1 unnamed_device 24.3 MiB 0.08 223 62.8 MiB 0.02 0.00 1.0308 -31.2922 -1.0308 1.0308 0.76 5.1352e-05 3.984e-05 0.0030693 0.00245236 34 797 32 6.87369e+06 69869.2 618332. 2139.56 1.08 0.0187325 0.0155147 25762 151098 -1 626 15 448 448 34542 10578 0 0 34542 10578 448 448 0 0 1742 1522 0 0 2542 2079 0 0 448 448 0 0 13676 3201 0 0 15686 2880 0 0 448 0 0 0 0 0 448 0 0 1.19167 1.19167 -41.2249 -1.19167 0 0 787024. 2723.27 0.27 0.01 0.10 -1 -1 0.27 0.00281145 0.00246102 31 -1 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml adder_015bits.v common 5.17 vpr 62.82 MiB -1 -1 0.08 20084 1 0.01 -1 -1 32988 -1 -1 5 31 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64324 31 16 111 112 1 80 52 17 17 289 -1 unnamed_device 24.3 MiB 0.10 290 62.8 MiB 0.02 0.00 1.27683 -33.8219 -1.27683 1.27683 0.76 6.4421e-05 5.1676e-05 0.00393255 0.00319237 36 641 13 6.87369e+06 69869.2 648988. 2245.63 2.46 0.0241641 0.0201201 26050 158493 -1 568 15 373 373 29444 7578 0 0 29444 7578 373 373 0 0 1458 1256 0 0 2033 1640 0 0 373 373 0 0 12916 1954 0 0 12291 1982 0 0 373 0 0 0 0 0 373 0 0 1.22267 1.22267 -43.074 -1.22267 0 0 828058. 2865.25 0.28 0.01 0.10 -1 -1 0.28 0.00275581 0.00241357 33 -1 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml adder_016bits.v common 3.20 vpr 62.84 MiB -1 -1 0.07 20024 1 0.01 -1 -1 33016 -1 -1 5 33 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64348 33 17 118 119 1 83 55 17 17 289 -1 unnamed_device 24.2 MiB 0.09 305 62.8 MiB 0.02 0.00 1.28783 -36.5233 -1.28783 1.28783 0.76 6.0864e-05 4.786e-05 0.00401562 0.00322596 32 807 20 6.87369e+06 69869.2 586450. 2029.24 0.64 0.0138472 0.0114974 25474 144626 -1 659 11 399 399 29624 8099 0 0 29624 8099 399 399 0 0 1658 1444 0 0 2427 2023 0 0 399 399 0 0 12330 1919 0 0 12411 1915 0 0 399 0 0 0 0 0 399 0 0 1.30397 1.30397 -48.266 -1.30397 0 0 744469. 2576.02 0.25 0.01 0.09 -1 -1 0.25 0.00284267 0.00256046 34 -1 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml adder_018bits.v common 3.24 vpr 63.00 MiB -1 -1 0.07 20112 1 0.01 -1 -1 33036 -1 -1 5 37 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64516 37 19 132 133 1 89 61 17 17 289 -1 unnamed_device 24.6 MiB 0.08 336 63.0 MiB 0.02 0.00 1.30983 -42.093 -1.30983 1.30983 0.85 6.8145e-05 5.3792e-05 0.0045456 0.00368288 32 1005 23 6.87369e+06 69869.2 586450. 2029.24 0.67 0.0161676 0.0135236 25474 144626 -1 813 18 527 527 53719 12759 0 0 53719 12759 527 527 0 0 2135 1882 0 0 3414 2642 0 0 527 527 0 0 22865 3761 0 0 24251 3420 0 0 527 0 0 0 0 0 527 0 0 1.35897 1.35897 -56.455 -1.35897 0 0 744469. 2576.02 0.28 0.02 0.09 -1 -1 0.28 0.00396399 0.0034818 38 -1 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml adder_020bits.v common 3.91 vpr 62.95 MiB -1 -1 0.08 20152 1 0.01 -1 -1 32904 -1 -1 6 41 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64460 41 21 146 147 1 101 68 17 17 289 -1 unnamed_device 24.4 MiB 0.08 390 62.9 MiB 0.03 0.00 1.33183 -48.3704 -1.33183 1.33183 0.79 7.4236e-05 5.925e-05 0.00490329 0.00399213 34 1186 33 6.87369e+06 83843 618332. 2139.56 1.26 0.0288413 0.0242224 25762 151098 -1 914 19 625 625 59108 14554 0 0 59108 14554 625 625 0 0 2402 2117 0 0 3546 2867 0 0 625 625 0 0 27307 3795 0 0 24603 4525 0 0 625 0 0 0 0 0 625 0 0 1.25567 1.25567 -60.7006 -1.25567 0 0 787024. 2723.27 0.26 0.02 0.10 -1 -1 0.26 0.00430959 0.00377666 42 -1 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml adder_022bits.v common 4.06 vpr 63.11 MiB -1 -1 0.08 20388 1 0.01 -1 -1 33196 -1 -1 7 45 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64624 45 23 160 161 1 115 75 17 17 289 -1 unnamed_device 24.5 MiB 0.11 461 63.1 MiB 0.03 0.00 1.35383 -52.9004 -1.35383 1.35383 0.78 8.5313e-05 6.7999e-05 0.00552054 0.00443607 36 1179 22 6.87369e+06 97816.9 648988. 2245.63 1.26 0.0299977 0.0252712 26050 158493 -1 989 18 693 693 59044 14540 0 0 59044 14540 693 693 0 0 2572 2238 0 0 3828 2987 0 0 693 693 0 0 26198 3844 0 0 25060 4085 0 0 693 0 0 0 0 0 693 0 0 1.26667 1.26667 -64.8803 -1.26667 0 0 828058. 2865.25 0.32 0.02 0.17 -1 -1 0.32 0.00451701 0.00399678 47 -1 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml adder_024bits.v common 4.02 vpr 63.19 MiB -1 -1 0.08 20212 1 0.01 -1 -1 32840 -1 -1 7 49 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64708 49 25 174 175 1 124 81 17 17 289 -1 unnamed_device 24.9 MiB 0.14 593 63.2 MiB 0.04 0.00 1.61086 -62.2859 -1.61086 1.61086 0.76 9.1151e-05 7.356e-05 0.00649089 0.00533009 34 1376 20 6.87369e+06 97816.9 618332. 2139.56 1.11 0.0315428 0.0268085 25762 151098 -1 1196 16 600 600 54974 12968 0 0 54974 12968 600 600 0 0 2404 2078 0 0 3412 2773 0 0 600 600 0 0 23435 3468 0 0 24523 3449 0 0 600 0 0 0 0 0 600 0 0 1.47327 1.47327 -77.646 -1.47327 0 0 787024. 2723.27 0.27 0.02 0.09 -1 -1 0.27 0.00492615 0.00438304 50 -1 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml adder_028bits.v common 3.82 vpr 63.11 MiB -1 -1 0.08 20292 1 0.01 -1 -1 32900 -1 -1 8 57 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64620 57 29 202 203 1 142 94 17 17 289 -1 unnamed_device 24.6 MiB 0.09 839 63.1 MiB 0.04 0.00 1.65486 -79.936 -1.65486 1.65486 0.75 0.000107903 8.8732e-05 0.00698204 0.00584868 34 1730 23 6.87369e+06 111791 618332. 2139.56 1.09 0.0389282 0.0346115 25762 151098 -1 1538 19 813 813 77020 17360 0 0 77020 17360 813 813 0 0 3138 2726 0 0 4882 3779 0 0 813 813 0 0 32765 4863 0 0 34609 4366 0 0 813 0 0 0 0 0 813 0 0 1.26037 1.26037 -90.0756 -1.26037 0 0 787024. 2723.27 0.27 0.03 0.10 -1 -1 0.27 0.00625639 0.00553823 58 -1 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml adder_032bits.v common 4.13 vpr 63.46 MiB -1 -1 0.08 20356 1 0.01 -1 -1 33184 -1 -1 9 65 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64984 65 33 230 231 1 165 107 17 17 289 -1 unnamed_device 25.1 MiB 0.09 932 63.5 MiB 0.05 0.00 1.93389 -92.6375 -1.93389 1.93389 0.77 0.000121927 0.000100721 0.00899717 0.00758259 34 1944 27 6.87369e+06 125765 618332. 2139.56 1.03 0.0443307 0.0380912 25762 151098 -1 1709 17 840 840 67579 16371 0 0 67579 16371 840 840 0 0 3324 2860 0 0 4909 3872 0 0 840 840 0 0 29442 3793 0 0 28224 4166 0 0 840 0 0 0 0 0 840 0 0 1.42297 1.42297 -105.235 -1.42297 0 0 787024. 2723.27 0.43 0.02 0.09 -1 -1 0.43 0.00629463 0.00559701 66 -1 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml adder_048bits.v common 4.21 vpr 64.35 MiB -1 -1 0.09 20440 1 0.02 -1 -1 33360 -1 -1 13 97 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65892 97 49 342 343 1 247 159 17 17 289 -1 unnamed_device 25.6 MiB 0.09 1457 64.3 MiB 0.11 0.00 2.57995 -155.956 -2.57995 2.57995 0.85 0.000210397 0.000179583 0.0171147 0.0146379 34 3232 21 6.87369e+06 181660 618332. 2139.56 1.37 0.0776454 0.0684068 25762 151098 -1 2758 19 1279 1279 149428 32476 0 0 149428 32476 1279 1279 0 0 5018 4361 0 0 7448 6006 0 0 1279 1279 0 0 66170 10042 0 0 68234 9509 0 0 1279 0 0 0 0 0 1279 0 0 1.55767 1.55767 -161.699 -1.55767 0 0 787024. 2723.27 0.28 0.04 0.10 -1 -1 0.28 0.0115317 0.0104301 98 -1 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml adder_064bits.v common 5.52 vpr 64.68 MiB -1 -1 0.09 20952 1 0.02 -1 -1 33464 -1 -1 17 129 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 66228 129 65 454 455 1 329 211 17 17 289 -1 unnamed_device 26.0 MiB 0.11 1996 64.7 MiB 0.18 0.00 3.22602 -227.983 -3.22602 3.22602 0.92 0.000334683 0.000292457 0.0294185 0.025802 34 4846 36 6.87369e+06 237555 618332. 2139.56 2.16 0.134703 0.1209 25762 151098 -1 3862 18 1663 1663 179620 41011 0 0 179620 41011 1663 1663 0 0 6479 5557 0 0 9924 7929 0 0 1663 1663 0 0 78998 11578 0 0 80893 12621 0 0 1663 0 0 0 0 0 1663 0 0 2.00227 2.00227 -237.661 -2.00227 0 0 787024. 2723.27 0.28 0.06 0.10 -1 -1 0.28 0.0161181 0.0147457 130 -1 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml adder_003bits.v common 2.51 vpr 62.36 MiB -1 -1 0.07 19900 1 0.00 -1 -1 33056 -1 -1 1 7 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 63852 7 4 27 28 1 13 12 17 17 289 -1 unnamed_device 23.9 MiB 0.02 38 62.4 MiB 0.00 0.00 0.488083 -5.72471 -0.488083 0.488083 0.77 1.87e-05 1.2284e-05 0.000350869 0.000270629 12 80 4 6.89349e+06 14093.8 243793. 843.575 0.29 0.00097457 0.000808007 21730 64085 -1 89 5 32 32 2061 627 0 0 2061 627 32 32 0 0 135 91 0 0 167 135 0 0 32 32 0 0 698 192 0 0 997 145 0 0 32 0 0 0 0 0 32 0 0 0.74674 0.74674 -7.98012 -0.74674 0 0 332735. 1151.33 0.13 0.00 0.04 -1 -1 0.13 0.000534735 0.000464911 8 -1 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml adder_004bits.v common 4.43 vpr 62.46 MiB -1 -1 0.07 19804 1 0.01 -1 -1 32708 -1 -1 2 9 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 63964 9 5 34 35 1 20 16 17 17 289 -1 unnamed_device 24.0 MiB 0.06 44 62.5 MiB 0.00 0.00 0.663773 -8.45852 -0.663773 0.663773 0.78 1.9243e-05 1.379e-05 0.000535061 0.000412772 22 152 9 6.89349e+06 28187.7 443629. 1535.05 1.90 0.00493574 0.00389231 23458 102101 -1 110 20 103 103 5696 2019 0 0 5696 2019 103 103 0 0 423 385 0 0 684 580 0 0 103 103 0 0 2073 408 0 0 2310 440 0 0 103 0 0 0 0 0 103 0 0 0.79102 0.79102 -10.0933 -0.79102 0 0 531479. 1839.03 0.18 0.01 0.06 -1 -1 0.18 0.00115647 0.000937789 10 -1 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml adder_005bits.v common 3.45 vpr 62.46 MiB -1 -1 0.08 20080 1 0.00 -1 -1 32984 -1 -1 3 11 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 63956 11 6 41 42 1 27 20 17 17 289 -1 unnamed_device 24.0 MiB 0.03 75 62.5 MiB 0.00 0.00 0.691973 -10.697 -0.691973 0.691973 0.78 2.3649e-05 1.7143e-05 0.000502505 0.000401322 16 276 30 6.89349e+06 42281.5 332735. 1151.33 0.84 0.00366967 0.00295557 22306 75877 -1 224 11 108 108 6460 2034 0 0 6460 2034 108 108 0 0 411 354 0 0 516 453 0 0 108 108 0 0 2162 518 0 0 3155 493 0 0 108 0 0 0 0 0 108 0 0 0.942573 0.942573 -15.3211 -0.942573 0 0 414966. 1435.87 0.15 0.00 0.14 -1 -1 0.15 0.000965131 0.000828931 13 -1 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml adder_006bits.v common 3.20 vpr 62.21 MiB -1 -1 0.06 19828 1 0.00 -1 -1 32956 -1 -1 3 13 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 63708 13 7 48 49 1 33 23 17 17 289 -1 unnamed_device 23.7 MiB 0.04 80 62.2 MiB 0.00 0.00 0.707773 -12.3375 -0.707773 0.707773 0.79 2.4329e-05 1.8167e-05 0.00110832 0.000646301 28 293 34 6.89349e+06 42281.5 531479. 1839.03 0.61 0.00606129 0.00464147 24610 126494 -1 261 20 254 254 16945 5294 0 0 16945 5294 254 254 0 0 962 845 0 0 1664 1300 0 0 254 254 0 0 6186 1421 0 0 7625 1220 0 0 254 0 0 0 0 0 254 0 0 1.08367 1.08367 -17.2242 -1.08367 0 0 648988. 2245.63 0.23 0.01 0.08 -1 -1 0.23 0.00154127 0.00127976 15 -1 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml adder_007bits.v common 2.90 vpr 62.45 MiB -1 -1 0.07 19992 1 0.00 -1 -1 32932 -1 -1 3 15 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 63948 15 8 55 56 1 39 26 17 17 289 -1 unnamed_device 23.9 MiB 0.06 110 62.4 MiB 0.01 0.00 1.13846 -15.98 -1.13846 1.13846 0.74 2.7601e-05 2.0159e-05 0.00122857 0.000952939 26 266 11 6.89349e+06 42281.5 503264. 1741.40 0.53 0.00542952 0.00437636 24322 120374 -1 251 12 144 144 6626 2203 0 0 6626 2203 144 144 0 0 563 459 0 0 783 639 0 0 144 144 0 0 2382 416 0 0 2610 401 0 0 144 0 0 0 0 0 144 0 0 0.96932 0.96932 -19.1597 -0.96932 0 0 618332. 2139.56 0.27 0.00 0.08 -1 -1 0.27 0.00125738 0.00109218 17 -1 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml adder_008bits.v common 2.96 vpr 62.34 MiB -1 -1 0.07 20108 1 0.00 -1 -1 33132 -1 -1 3 17 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 63832 17 9 62 63 1 42 29 17 17 289 -1 unnamed_device 23.8 MiB 0.04 125 62.3 MiB 0.01 0.00 0.964803 -18.1535 -0.964803 0.964803 0.77 3.3704e-05 2.4859e-05 0.00189875 0.00148351 26 324 18 6.89349e+06 42281.5 503264. 1741.40 0.55 0.00725969 0.00584262 24322 120374 -1 280 14 215 215 17058 4813 0 0 17058 4813 215 215 0 0 892 787 0 0 1464 1189 0 0 215 215 0 0 6556 1299 0 0 7716 1108 0 0 215 0 0 0 0 0 215 0 0 1.00232 1.00232 -22.1233 -1.00232 0 0 618332. 2139.56 0.21 0.01 0.07 -1 -1 0.21 0.00170731 0.00148174 18 -1 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml adder_009bits.v common 4.59 vpr 62.60 MiB -1 -1 0.07 19884 1 0.00 -1 -1 32960 -1 -1 3 19 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64104 19 10 69 70 1 46 32 17 17 289 -1 unnamed_device 24.0 MiB 0.04 134 62.6 MiB 0.01 0.00 0.975803 -20.1021 -0.975803 0.975803 0.76 3.5952e-05 2.715e-05 0.00181677 0.0014168 28 359 16 6.89349e+06 42281.5 531479. 1839.03 1.94 0.0115861 0.00936133 24610 126494 -1 296 10 180 180 12065 3431 0 0 12065 3431 180 180 0 0 722 598 0 0 1004 851 0 0 180 180 0 0 4561 920 0 0 5418 702 0 0 180 0 0 0 0 0 180 0 0 1.13667 1.13667 -25.4714 -1.13667 0 0 648988. 2245.63 0.23 0.01 0.09 -1 -1 0.23 0.00160534 0.00140887 20 -1 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml adder_010bits.v common 4.24 vpr 62.61 MiB -1 -1 0.07 20120 1 0.01 -1 -1 33068 -1 -1 3 21 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64112 21 11 76 77 1 48 35 17 17 289 -1 unnamed_device 24.2 MiB 0.04 153 62.6 MiB 0.01 0.00 0.986803 -22.4254 -0.986803 0.986803 0.77 3.8721e-05 2.9203e-05 0.00237349 0.00185262 28 446 19 6.89349e+06 42281.5 531479. 1839.03 1.55 0.0149397 0.0121196 24610 126494 -1 345 15 230 230 17182 4895 0 0 17182 4895 230 230 0 0 941 815 0 0 1330 1129 0 0 230 230 0 0 6612 1339 0 0 7839 1152 0 0 230 0 0 0 0 0 230 0 0 1.11467 1.11467 -28.5767 -1.11467 0 0 648988. 2245.63 0.30 0.01 0.11 -1 -1 0.30 0.00193384 0.00166799 22 -1 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml adder_011bits.v common 3.92 vpr 62.52 MiB -1 -1 0.08 20076 1 0.01 -1 -1 33068 -1 -1 4 23 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64020 23 12 83 84 1 53 39 17 17 289 -1 unnamed_device 24.1 MiB 0.04 160 62.5 MiB 0.01 0.00 0.997803 -24.8191 -0.997803 0.997803 0.76 4.6611e-05 3.6778e-05 0.00286671 0.00230389 30 470 19 6.89349e+06 56375.4 556674. 1926.21 1.41 0.0159916 0.0130708 25186 138497 -1 361 17 269 269 15701 4339 0 0 15701 4339 269 269 0 0 956 810 0 0 1266 1056 0 0 269 269 0 0 6727 906 0 0 6214 1029 0 0 269 0 0 0 0 0 269 0 0 1.01137 1.01137 -28.6692 -1.01137 0 0 706193. 2443.58 0.28 0.01 0.10 -1 -1 0.28 0.00230915 0.00200057 24 -1 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml adder_012bits.v common 4.97 vpr 62.63 MiB -1 -1 0.08 20028 1 0.01 -1 -1 32724 -1 -1 4 25 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64132 25 13 90 91 1 60 42 17 17 289 -1 unnamed_device 24.2 MiB 0.05 188 62.6 MiB 0.01 0.00 1.0088 -26.8478 -1.0088 1.0088 0.92 4.531e-05 3.47e-05 0.00283174 0.00212768 32 652 27 6.89349e+06 56375.4 586450. 2029.24 2.29 0.0177745 0.0144421 25474 144626 -1 483 14 292 292 27366 6990 0 0 27366 6990 292 292 0 0 1166 986 0 0 1925 1506 0 0 292 292 0 0 10992 2119 0 0 12699 1795 0 0 292 0 0 0 0 0 292 0 0 1.15867 1.15867 -34.0813 -1.15867 0 0 744469. 2576.02 0.25 0.01 0.09 -1 -1 0.25 0.00225507 0.00195704 26 -1 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml adder_013bits.v common 4.57 vpr 62.53 MiB -1 -1 0.07 20172 1 0.01 -1 -1 32892 -1 -1 4 27 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64032 27 14 97 98 1 67 45 17 17 289 -1 unnamed_device 24.0 MiB 0.05 211 62.5 MiB 0.02 0.00 1.0198 -29.2635 -1.0198 1.0198 0.79 4.6835e-05 3.5901e-05 0.00324734 0.002558 32 670 34 6.89349e+06 56375.4 586450. 2029.24 2.12 0.026086 0.0215309 25474 144626 -1 549 14 327 327 28499 7706 0 0 28499 7706 327 327 0 0 1367 1157 0 0 2221 1781 0 0 327 327 0 0 11847 2010 0 0 12410 2104 0 0 327 0 0 0 0 0 327 0 0 1.30597 1.30597 -40.0377 -1.30597 0 0 744469. 2576.02 0.27 0.01 0.09 -1 -1 0.27 0.00243228 0.00212975 28 -1 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml adder_014bits.v common 5.66 vpr 62.74 MiB -1 -1 0.06 19824 1 0.01 -1 -1 32904 -1 -1 5 29 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64248 29 15 104 105 1 74 49 17 17 289 -1 unnamed_device 24.2 MiB 0.07 228 62.7 MiB 0.02 0.00 1.0308 -31.4175 -1.0308 1.0308 0.89 5.1523e-05 4.0252e-05 0.00300805 0.00239951 44 629 17 6.89349e+06 70469.2 787024. 2723.27 2.74 0.024864 0.0205786 27778 195446 -1 488 17 396 396 26155 7053 0 0 26155 7053 396 396 0 0 1424 1204 0 0 2129 1737 0 0 396 396 0 0 10060 1738 0 0 11750 1582 0 0 396 0 0 0 0 0 396 0 0 0.947373 0.947373 -35.0232 -0.947373 0 0 997811. 3452.63 0.34 0.01 0.13 -1 -1 0.34 0.00295815 0.00256704 31 -1 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml adder_015bits.v common 3.51 vpr 62.60 MiB -1 -1 0.07 20492 1 0.01 -1 -1 32996 -1 -1 5 31 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64104 31 16 111 112 1 80 52 17 17 289 -1 unnamed_device 24.0 MiB 0.09 290 62.6 MiB 0.02 0.00 1.27683 -33.8219 -1.27683 1.27683 0.99 5.7246e-05 4.4986e-05 0.00371065 0.00298039 30 732 24 6.89349e+06 70469.2 556674. 1926.21 0.67 0.0137643 0.0113737 25186 138497 -1 570 13 374 374 21817 6118 0 0 21817 6118 374 374 0 0 1396 1168 0 0 1812 1539 0 0 374 374 0 0 9234 1294 0 0 8627 1369 0 0 374 0 0 0 0 0 374 0 0 1.06437 1.06437 -41.5171 -1.06437 0 0 706193. 2443.58 0.27 0.01 0.09 -1 -1 0.27 0.00282418 0.00251312 33 -1 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml adder_016bits.v common 3.28 vpr 62.55 MiB -1 -1 0.07 20256 1 0.01 -1 -1 33044 -1 -1 5 33 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64052 33 17 118 119 1 83 55 17 17 289 -1 unnamed_device 24.0 MiB 0.10 305 62.6 MiB 0.02 0.00 1.28783 -36.5265 -1.28783 1.28783 0.77 6.07e-05 4.7577e-05 0.00391733 0.00313487 30 763 24 6.89349e+06 70469.2 556674. 1926.21 0.66 0.0143956 0.0119021 25186 138497 -1 631 16 408 408 27345 7375 0 0 27345 7375 408 408 0 0 1570 1332 0 0 2226 1908 0 0 408 408 0 0 12010 1608 0 0 10723 1711 0 0 408 0 0 0 0 0 408 0 0 1.23367 1.23367 -47.4754 -1.23367 0 0 706193. 2443.58 0.32 0.01 0.08 -1 -1 0.32 0.00306399 0.00267569 34 -1 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml adder_018bits.v common 4.27 vpr 62.77 MiB -1 -1 0.07 20092 1 0.01 -1 -1 32900 -1 -1 5 37 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64280 37 19 132 133 1 90 61 17 17 289 -1 unnamed_device 24.4 MiB 0.07 340 62.8 MiB 0.02 0.00 1.30983 -42.5349 -1.30983 1.30983 0.76 6.9685e-05 5.5546e-05 0.00448678 0.00361604 30 924 21 6.89349e+06 70469.2 556674. 1926.21 1.86 0.0280123 0.0234128 25186 138497 -1 765 18 476 476 37469 9211 0 0 37469 9211 476 476 0 0 1723 1406 0 0 2182 1854 0 0 476 476 0 0 16018 2619 0 0 16594 2380 0 0 476 0 0 0 0 0 476 0 0 1.11467 1.11467 -51.366 -1.11467 0 0 706193. 2443.58 0.25 0.01 0.08 -1 -1 0.25 0.00378465 0.00331495 38 -1 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml adder_020bits.v common 3.77 vpr 62.91 MiB -1 -1 0.07 20280 1 0.01 -1 -1 32916 -1 -1 6 41 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64416 41 21 146 147 1 102 68 17 17 289 -1 unnamed_device 24.4 MiB 0.07 384 62.9 MiB 0.03 0.00 1.33183 -47.7879 -1.33183 1.33183 0.81 7.4998e-05 5.94e-05 0.00511893 0.00419008 34 1192 23 6.89349e+06 84563 618332. 2139.56 1.25 0.0294717 0.0250602 25762 151098 -1 876 22 578 578 75397 24455 0 0 75397 24455 578 578 0 0 2167 1763 0 0 3970 2949 0 0 578 578 0 0 34304 9418 0 0 33800 9169 0 0 578 0 0 0 0 0 578 0 0 1.53457 1.53457 -61.0012 -1.53457 0 0 787024. 2723.27 0.26 0.02 0.10 -1 -1 0.26 0.00489754 0.00424409 42 -1 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml adder_022bits.v common 6.08 vpr 63.27 MiB -1 -1 0.08 20228 1 0.00 -1 -1 33196 -1 -1 7 45 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64784 45 23 160 161 1 115 75 17 17 289 -1 unnamed_device 24.7 MiB 0.09 436 63.3 MiB 0.03 0.00 1.35383 -53.0257 -1.35383 1.35383 0.76 8.4718e-05 6.816e-05 0.00515711 0.00421732 38 1139 28 6.89349e+06 98656.9 678818. 2348.85 3.47 0.0492148 0.0420098 26626 170182 -1 930 15 636 636 48508 12290 0 0 48508 12290 636 636 0 0 2297 1915 0 0 3263 2651 0 0 636 636 0 0 21810 3071 0 0 19866 3381 0 0 636 0 0 0 0 0 636 0 0 1.20462 1.20462 -62.5171 -1.20462 0 0 902133. 3121.57 0.29 0.02 0.11 -1 -1 0.29 0.00421138 0.00372277 47 -1 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml adder_024bits.v common 3.77 vpr 63.09 MiB -1 -1 0.08 20104 1 0.00 -1 -1 33156 -1 -1 7 49 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64608 49 25 174 175 1 124 81 17 17 289 -1 unnamed_device 24.5 MiB 0.09 657 63.1 MiB 0.04 0.00 1.61086 -63.9148 -1.61086 1.61086 0.84 9.7114e-05 7.8951e-05 0.00603868 0.00499161 34 1354 18 6.89349e+06 98656.9 618332. 2139.56 1.07 0.023843 0.0202966 25762 151098 -1 1243 11 520 520 47607 11018 0 0 47607 11018 520 520 0 0 1998 1679 0 0 2786 2292 0 0 520 520 0 0 21104 2961 0 0 20679 3046 0 0 520 0 0 0 0 0 520 0 0 1.25087 1.25087 -75.1898 -1.25087 0 0 787024. 2723.27 0.27 0.02 0.09 -1 -1 0.27 0.00414377 0.00373523 50 -1 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml adder_028bits.v common 3.94 vpr 63.32 MiB -1 -1 0.06 20192 1 0.01 -1 -1 33112 -1 -1 8 57 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64840 57 29 202 203 1 143 94 17 17 289 -1 unnamed_device 24.9 MiB 0.07 894 63.3 MiB 0.04 0.00 1.65486 -81.8847 -1.65486 1.65486 0.78 0.00011697 9.7535e-05 0.00704155 0.00583436 34 1760 21 6.89349e+06 112751 618332. 2139.56 1.28 0.0315232 0.0270537 25762 151098 -1 1611 16 743 743 71332 15953 0 0 71332 15953 743 743 0 0 2892 2451 0 0 4544 3665 0 0 743 743 0 0 31305 4196 0 0 31105 4155 0 0 743 0 0 0 0 0 743 0 0 1.28867 1.28867 -90.9124 -1.28867 0 0 787024. 2723.27 0.29 0.03 0.10 -1 -1 0.29 0.00636389 0.00573336 58 -1 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml adder_032bits.v common 4.61 vpr 63.20 MiB -1 -1 0.08 20336 1 0.01 -1 -1 33100 -1 -1 9 65 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64716 65 33 230 231 1 165 107 17 17 289 -1 unnamed_device 24.9 MiB 0.12 937 63.2 MiB 0.08 0.00 1.93389 -92.387 -1.93389 1.93389 1.15 0.000160862 0.000136083 0.0167586 0.0136789 34 1976 19 6.89349e+06 126845 618332. 2139.56 1.17 0.0505661 0.0428915 25762 151098 -1 1763 16 798 798 75945 17453 0 0 75945 17453 798 798 0 0 3209 2677 0 0 4607 3767 0 0 798 798 0 0 34302 4455 0 0 32231 4958 0 0 798 0 0 0 0 0 798 0 0 1.43397 1.43397 -104.441 -1.43397 0 0 787024. 2723.27 0.31 0.03 0.10 -1 -1 0.31 0.00689383 0.00616947 66 -1 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml adder_048bits.v common 5.16 vpr 64.42 MiB -1 -1 0.08 20400 1 0.01 -1 -1 33176 -1 -1 13 97 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65964 97 49 342 343 1 247 159 17 17 289 -1 unnamed_device 25.7 MiB 0.10 1547 64.4 MiB 0.16 0.00 2.57995 -158.212 -2.57995 2.57995 0.99 0.000213606 0.000180883 0.0260243 0.0232267 34 3172 19 6.89349e+06 183220 618332. 2139.56 1.70 0.0991204 0.089339 25762 151098 -1 2822 14 1126 1126 112200 24280 0 0 112200 24280 1126 1126 0 0 4279 3532 0 0 6034 4847 0 0 1126 1126 0 0 49337 6970 0 0 50298 6679 0 0 1126 0 0 0 0 0 1126 0 0 1.61067 1.61067 -166.885 -1.61067 0 0 787024. 2723.27 0.33 0.04 0.17 -1 -1 0.33 0.00932628 0.00846771 98 -1 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml adder_064bits.v common 5.33 vpr 64.70 MiB -1 -1 0.09 20748 1 0.02 -1 -1 33360 -1 -1 17 129 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 66252 129 65 454 455 1 329 211 17 17 289 -1 unnamed_device 26.0 MiB 0.20 2069 64.7 MiB 0.20 0.00 3.22602 -231.867 -3.22602 3.22602 0.95 0.000322693 0.00028285 0.0287281 0.0255126 34 4582 22 6.89349e+06 239595 618332. 2139.56 1.71 0.141234 0.128328 25762 151098 -1 3943 19 1530 1530 175078 36774 0 0 175078 36774 1530 1530 0 0 5923 4921 0 0 8643 6911 0 0 1530 1530 0 0 77972 11242 0 0 79480 10640 0 0 1530 0 0 0 0 0 1530 0 0 1.75832 1.75832 -225.369 -1.75832 0 0 787024. 2723.27 0.33 0.06 0.10 -1 -1 0.33 0.017955 0.0158629 130 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/multless_consts/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/multless_consts/config/golden_results.txt index 7d97e1ff84e..b966512a864 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/multless_consts/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/multless_consts/config/golden_results.txt @@ -1,1025 +1,1025 @@ -arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops crit_path_total_internal_heap_pushes crit_path_total_internal_heap_pops crit_path_total_external_heap_pushes crit_path_total_external_heap_pops crit_path_total_external_SOURCE_pushes crit_path_total_external_SOURCE_pops crit_path_total_internal_SOURCE_pushes crit_path_total_internal_SOURCE_pops crit_path_total_external_SINK_pushes crit_path_total_external_SINK_pops crit_path_total_internal_SINK_pushes crit_path_total_internal_SINK_pops crit_path_total_external_IPIN_pushes crit_path_total_external_IPIN_pops crit_path_total_internal_IPIN_pushes crit_path_total_internal_IPIN_pops crit_path_total_external_OPIN_pushes crit_path_total_external_OPIN_pops crit_path_total_internal_OPIN_pushes crit_path_total_internal_OPIN_pops crit_path_total_external_CHANX_pushes crit_path_total_external_CHANX_pops crit_path_total_internal_CHANX_pushes crit_path_total_internal_CHANX_pops crit_path_total_external_CHANY_pushes crit_path_total_external_CHANY_pops crit_path_total_internal_CHANY_pushes crit_path_total_internal_CHANY_pops crit_path_rt_node_SOURCE_pushes crit_path_rt_node_SINK_pushes crit_path_rt_node_IPIN_pushes crit_path_rt_node_OPIN_pushes crit_path_rt_node_CHANX_pushes crit_path_rt_node_CHANY_pushes crit_path_adding_all_rt crit_path_adding_high_fanout_rt crit_path_total_number_of_adding_all_rt_from_calling_high_fanout_rt critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_001.v common 3.86 vpr 53.21 MiB -1 -1 0.14 17768 14 0.23 -1 -1 32240 -1 -1 27 32 0 0 success v8.0.0-7776-g6d5a301e6 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-05-04T19:10:09 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_2/vtr-verilog-to-routing/vtr_flow/tasks 54484 32 32 277 309 1 204 91 17 17 289 -1 unnamed_device 14.6 MiB 0.32 1389 53.2 MiB 0.04 0.00 6.52936 -137.096 -6.52936 6.52936 0.54 0.000168954 0.000135449 0.0100647 0.00828607 32 3881 45 6.55708e+06 325485 554710. 1919.41 1.08 0.049721 0.0424299 22174 131602 -1 3423 47 2390 8119 950380 367097 0 0 950380 367097 8119 4736 0 0 28053 23056 0 0 54064 35635 0 0 8119 5583 0 0 424782 149788 0 0 427243 148299 0 0 8119 0 0 5729 12476 12169 69851 0 0 7.25056 7.25056 -165.952 -7.25056 0 0 701300. 2426.64 0.19 0.17 0.06 -1 -1 0.19 0.0223128 0.0195252 183 182 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_002.v common 4.49 vpr 53.22 MiB -1 -1 0.15 17740 14 0.27 -1 -1 32344 -1 -1 31 30 0 0 success v8.0.0-7776-g6d5a301e6 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-05-04T19:10:09 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_2/vtr-verilog-to-routing/vtr_flow/tasks 54496 30 32 272 304 1 210 93 17 17 289 -1 unnamed_device 14.6 MiB 0.40 1212 53.2 MiB 0.04 0.00 6.76976 -130.82 -6.76976 6.76976 0.54 0.000167672 0.000136093 0.0100103 0.00828985 28 3699 44 6.55708e+06 373705 500653. 1732.36 1.73 0.050752 0.0432354 21310 115450 -1 3171 19 1590 4710 294141 67778 0 0 294141 67778 4710 2554 0 0 16187 13540 0 0 25500 19106 0 0 4710 2981 0 0 121366 14989 0 0 121668 14608 0 0 4710 0 0 3120 5855 6519 38198 0 0 7.17416 7.17416 -153.878 -7.17416 0 0 612192. 2118.31 0.17 0.05 0.06 -1 -1 0.17 0.0130436 0.0118022 184 181 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_003.v common 4.88 vpr 53.34 MiB -1 -1 0.11 17544 11 0.21 -1 -1 32240 -1 -1 26 32 0 0 success v8.0.0-7776-g6d5a301e6 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-05-04T19:10:09 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_2/vtr-verilog-to-routing/vtr_flow/tasks 54616 32 32 280 312 1 205 90 17 17 289 -1 unnamed_device 14.6 MiB 0.26 1329 53.3 MiB 0.05 0.00 5.87124 -120.512 -5.87124 5.87124 0.55 0.00017818 0.000138044 0.0109968 0.00898305 28 4037 43 6.55708e+06 313430 500653. 1732.36 2.24 0.0553601 0.0470893 21310 115450 -1 3260 27 1745 6552 571935 168183 0 0 571935 168183 6552 3069 0 0 21793 18165 0 0 35726 25169 0 0 6552 3673 0 0 247212 59673 0 0 254100 58434 0 0 6552 0 0 4807 11897 12099 72627 0 0 6.15344 6.15344 -139.362 -6.15344 0 0 612192. 2118.31 0.17 0.09 0.06 -1 -1 0.17 0.0155436 0.01394 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3.69 vpr 53.48 MiB -1 -1 0.14 17432 13 0.25 -1 -1 32288 -1 -1 31 32 0 0 success v8.0.0-7776-g6d5a301e6 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-05-04T19:10:09 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_2/vtr-verilog-to-routing/vtr_flow/tasks 54764 32 32 302 334 1 233 95 17 17 289 -1 unnamed_device 14.8 MiB 0.40 1517 53.5 MiB 0.05 0.00 6.50744 -139.044 -6.50744 6.50744 0.55 0.000184434 0.000150302 0.0107917 0.0090066 30 3842 30 6.55708e+06 373705 526063. 1820.29 0.87 0.0495335 0.0424427 21886 126133 -1 3207 17 1492 4352 203820 49148 0 0 203820 49148 4352 2229 0 0 14028 11506 0 0 19513 14926 0 0 4352 2744 0 0 80198 8986 0 0 81377 8757 0 0 4352 0 0 2860 4923 4295 32414 0 0 6.5981 6.5981 -156.158 -6.5981 0 0 666494. 2306.21 0.18 0.04 0.06 -1 -1 0.18 0.0137462 0.0125569 210 207 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_006.v common 4.47 vpr 53.26 MiB -1 -1 0.14 17352 13 0.24 -1 -1 32308 -1 -1 32 32 0 0 success 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betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_2/vtr-verilog-to-routing/vtr_flow/tasks 54264 31 32 229 261 1 184 85 17 17 289 -1 unnamed_device 14.4 MiB 0.18 1261 53.0 MiB 0.03 0.00 5.1068 -113.491 -5.1068 5.1068 0.54 0.000137014 0.000108839 0.00704557 0.00582543 36 3077 37 6.55708e+06 265210 612192. 2118.31 2.47 0.055022 0.047075 22750 144809 -1 2664 15 1037 3077 176903 40466 0 0 176903 40466 3077 1610 0 0 10518 8736 0 0 16229 12102 0 0 3077 1863 0 0 70854 8225 0 0 73148 7930 0 0 3077 0 0 2040 3962 4203 26262 0 0 5.68992 5.68992 -133.074 -5.68992 0 0 782063. 2706.10 0.21 0.03 0.07 -1 -1 0.21 0.00937175 0.00857697 140 136 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_009.v common 3.64 vpr 52.91 MiB -1 -1 0.13 17588 12 0.14 -1 -1 32164 -1 -1 26 31 0 0 success v8.0.0-7776-g6d5a301e6 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-05-04T19:10:09 betzgrp-wintermute.eecg.utoronto.ca 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2023-05-04T19:10:09 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_2/vtr-verilog-to-routing/vtr_flow/tasks 53812 25 32 183 215 1 140 79 17 17 289 -1 unnamed_device 14.1 MiB 0.13 812 52.6 MiB 0.02 0.00 4.28106 -80.808 -4.28106 4.28106 0.58 0.000108842 8.7425e-05 0.00505061 0.00421523 26 2476 34 6.55708e+06 265210 477104. 1650.88 1.01 0.0304714 0.026135 21022 109990 -1 1949 19 883 2478 146123 34173 0 0 146123 34173 2478 1347 0 0 8527 6904 0 0 13361 9767 0 0 2478 1545 0 0 59479 7280 0 0 59800 7330 0 0 2478 0 0 1595 2647 2787 18257 0 0 4.76186 4.76186 -97.0068 -4.76186 0 0 585099. 2024.56 0.16 0.03 0.05 -1 -1 0.16 0.00862248 0.00776264 111 102 -1 -1 -1 -1 -fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_127.v common 7.94 vpr 53.50 MiB -1 -1 0.13 17484 12 0.25 -1 -1 32272 -1 -1 33 32 0 0 success v8.0.0-7776-g6d5a301e6 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-05-04T19:10:09 betzgrp-wintermute.eecg.utoronto.ca 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v8.0.0-7776-g6d5a301e6 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-05-04T19:10:09 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_2/vtr-verilog-to-routing/vtr_flow/tasks 54328 30 32 303 262 1 139 79 17 17 289 -1 unnamed_device 14.5 MiB 0.08 802 53.1 MiB 0.04 0.00 3.22421 -92.1331 -3.22421 3.22421 0.55 0.000104464 8.3202e-05 0.00826081 0.00674849 30 1612 15 6.64007e+06 213486 526063. 1820.29 0.51 0.0261379 0.0220352 22546 126617 -1 1463 16 650 1002 56304 13497 0 0 56304 13497 1002 750 0 0 3378 2703 0 0 4379 3508 0 0 1002 827 0 0 22544 3096 0 0 23999 2613 0 0 1002 0 0 352 393 361 3052 0 0 2.89296 2.89296 -101.966 -2.89296 0 0 666494. 2306.21 0.18 0.02 0.06 -1 -1 0.18 0.00676814 0.006091 98 58 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_012.v common 2.73 vpr 52.88 MiB -1 -1 0.10 17640 1 0.01 -1 -1 29780 -1 -1 18 32 0 0 success v8.0.0-7776-g6d5a301e6 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on 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betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_2/vtr-verilog-to-routing/vtr_flow/tasks 54772 32 32 344 272 1 202 88 17 17 289 -1 unnamed_device 15.1 MiB 0.16 1104 53.5 MiB 0.07 0.00 3.65347 -120.082 -3.65347 3.65347 0.58 0.000127699 9.6974e-05 0.0104542 0.00836737 26 2966 28 6.64007e+06 301392 477104. 1650.88 0.72 0.0348396 0.0291795 21682 110474 -1 2352 20 1798 2742 213817 47912 0 0 213817 47912 2742 2148 0 0 10117 8544 0 0 15255 11926 0 0 2742 2217 0 0 93151 11469 0 0 89810 11608 0 0 2742 0 0 944 1100 878 7590 0 0 3.65363 3.65363 -134.874 -3.65363 0 0 585099. 2024.56 0.16 0.04 0.05 -1 -1 0.16 0.00921518 0.00824182 139 31 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_014.v common 2.93 vpr 53.43 MiB -1 -1 0.10 17440 1 0.01 -1 -1 29808 -1 -1 31 32 0 0 success v8.0.0-7776-g6d5a301e6 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-05-04T19:10:09 betzgrp-wintermute.eecg.utoronto.ca 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53.11 MiB -1 -1 0.10 17188 1 0.00 -1 -1 29692 -1 -1 21 32 0 0 success v8.0.0-7776-g6d5a301e6 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-05-04T19:10:09 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_2/vtr-verilog-to-routing/vtr_flow/tasks 54380 32 32 285 227 1 165 85 17 17 289 -1 unnamed_device 14.4 MiB 0.03 941 53.1 MiB 0.06 0.00 4.00635 -102.194 -4.00635 4.00635 0.54 0.000113414 9.1467e-05 0.00935687 0.00773265 32 2150 23 6.64007e+06 263718 554710. 1919.41 0.55 0.029679 0.0251802 22834 132086 -1 1974 19 1089 2067 148114 33840 0 0 148114 33840 2067 1576 0 0 7469 6075 0 0 11730 8752 0 0 2067 1814 0 0 63518 7633 0 0 61263 7990 0 0 2067 0 0 978 1181 1170 8116 0 0 4.04602 4.04602 -124.592 -4.04602 0 0 701300. 2426.64 0.19 0.04 0.07 -1 -1 0.19 0.00877104 0.00778808 118 -1 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_025.v common 2.65 vpr 52.37 MiB -1 -1 0.10 16812 1 0.01 -1 -1 29512 -1 -1 14 32 0 0 success v8.0.0-7776-g6d5a301e6 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-05-04T19:10:09 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_2/vtr-verilog-to-routing/vtr_flow/tasks 53624 32 32 173 169 1 116 78 17 17 289 -1 unnamed_device 13.8 MiB 0.07 409 52.4 MiB 0.02 0.00 2.08773 -59.2766 -2.08773 2.08773 0.55 7.5197e-05 5.9763e-05 0.00293715 0.00244466 28 1291 47 6.64007e+06 175812 500653. 1732.36 0.67 0.0201844 0.0171496 21970 115934 -1 872 15 508 596 42287 12656 0 0 42287 12656 596 561 0 0 2235 1797 0 0 3131 2603 0 0 596 567 0 0 18478 3729 0 0 17251 3399 0 0 596 0 0 88 90 100 1050 0 0 2.14231 2.14231 -71.1836 -2.14231 0 0 612192. 2118.31 0.17 0.02 0.06 -1 -1 0.17 0.00431249 0.00387366 79 -1 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_026.v common 2.58 vpr 53.01 MiB -1 -1 0.09 17480 1 0.01 -1 -1 29732 -1 -1 30 32 0 0 success v8.0.0-7776-g6d5a301e6 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-05-04T19:10:09 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_2/vtr-verilog-to-routing/vtr_flow/tasks 54280 32 32 300 245 1 165 94 17 17 289 -1 unnamed_device 14.6 MiB 0.04 1016 53.0 MiB 0.07 0.00 3.62727 -105.452 -3.62727 3.62727 0.55 0.000108732 8.6654e-05 0.0101566 0.00828806 28 2100 23 6.64007e+06 376740 500653. 1732.36 0.52 0.0309124 0.0261119 21970 115934 -1 1890 18 904 1451 93378 21459 0 0 93378 21459 1451 1054 0 0 5241 4084 0 0 7768 6156 0 0 1451 1123 0 0 38937 4510 0 0 38530 4532 0 0 1451 0 0 547 564 593 4757 0 0 3.41203 3.41203 -115.281 -3.41203 0 0 612192. 2118.31 0.17 0.03 0.06 -1 -1 0.17 0.00776637 0.0069737 123 21 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_027.v common 2.57 vpr 53.13 MiB -1 -1 0.08 17260 1 0.01 -1 -1 29720 -1 -1 31 32 0 0 success v8.0.0-7776-g6d5a301e6 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-05-04T19:10:09 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_2/vtr-verilog-to-routing/vtr_flow/tasks 54404 32 32 297 233 1 177 95 17 17 289 -1 unnamed_device 14.6 MiB 0.03 995 53.1 MiB 0.04 0.00 3.0905 -90.605 -3.0905 3.0905 0.55 0.000112147 9.0559e-05 0.00566943 0.00469947 26 2230 22 6.64007e+06 389298 477104. 1650.88 0.52 0.026424 0.0225102 21682 110474 -1 1988 18 1127 1955 122072 29452 0 0 122072 29452 1955 1346 0 0 7285 5808 0 0 10833 8487 0 0 1955 1485 0 0 50253 6062 0 0 49791 6264 0 0 1955 0 0 828 1074 1160 7879 0 0 2.84296 2.84296 -106.319 -2.84296 0 0 585099. 2024.56 0.16 0.03 0.06 -1 -1 0.16 0.00775532 0.0069472 128 -1 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_028.v common 2.73 vpr 53.38 MiB -1 -1 0.09 17464 1 0.01 -1 -1 29684 -1 -1 27 32 0 0 success v8.0.0-7776-g6d5a301e6 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-05-04T19:10:09 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_2/vtr-verilog-to-routing/vtr_flow/tasks 54664 32 32 338 277 1 179 91 17 17 289 -1 unnamed_device 14.8 MiB 0.10 1072 53.4 MiB 0.08 0.00 3.69347 -110.77 -3.69347 3.69347 0.59 0.00011778 9.3191e-05 0.0118006 0.00953767 28 2357 20 6.64007e+06 339066 500653. 1732.36 0.55 0.0338255 0.0284678 21970 115934 -1 2149 22 1255 2171 145664 32598 0 0 145664 32598 2171 1653 0 0 7475 6014 0 0 11411 8640 0 0 2171 1750 0 0 62208 7080 0 0 60228 7461 0 0 2171 0 0 916 1084 1048 7921 0 0 3.67063 3.67063 -128.321 -3.67063 0 0 612192. 2118.31 0.17 0.03 0.06 -1 -1 0.17 0.00940637 0.00836836 126 47 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_029.v common 2.64 vpr 53.02 MiB -1 -1 0.09 17376 1 0.01 -1 -1 29840 -1 -1 16 32 0 0 success v8.0.0-7776-g6d5a301e6 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-05-04T19:10:09 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_2/vtr-verilog-to-routing/vtr_flow/tasks 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31 0 0 success v8.0.0-7776-g6d5a301e6 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-05-04T19:10:09 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_2/vtr-verilog-to-routing/vtr_flow/tasks 54744 31 32 377 302 1 233 92 17 17 289 -1 unnamed_device 15.3 MiB 0.25 1272 53.5 MiB 0.07 0.00 4.67899 -142.805 -4.67899 4.67899 0.55 0.000131422 0.000106208 0.0111034 0.00913209 28 3457 26 6.64007e+06 364182 500653. 1732.36 0.84 0.0385203 0.032797 21970 115934 -1 2626 20 1939 2907 204299 47032 0 0 204299 47032 2907 2470 0 0 9951 7938 0 0 15030 11469 0 0 2907 2598 0 0 90747 10715 0 0 82757 11842 0 0 2907 0 0 968 1145 917 7873 0 0 5.26895 5.26895 -173.742 -5.26895 0 0 612192. 2118.31 0.17 0.04 0.06 -1 -1 0.17 0.0098952 0.0088714 172 60 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_040.v common 2.97 vpr 53.43 MiB -1 -1 0.12 17916 1 0.02 -1 -1 29896 -1 -1 27 31 0 0 success v8.0.0-7776-g6d5a301e6 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-05-04T19:10:09 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_2/vtr-verilog-to-routing/vtr_flow/tasks 54708 31 32 383 305 1 209 90 17 17 289 -1 unnamed_device 14.8 MiB 0.22 1024 53.4 MiB 0.05 0.00 4.12201 -121.45 -4.12201 4.12201 0.55 0.000129272 0.00010389 0.00762012 0.00633106 32 2849 25 6.64007e+06 339066 554710. 1919.41 0.60 0.0328935 0.0279727 22834 132086 -1 2274 23 1863 2919 206177 47249 0 0 206177 47249 2919 2193 0 0 10441 8717 0 0 17079 12483 0 0 2919 2362 0 0 87524 10825 0 0 85295 10669 0 0 2919 0 0 1056 1140 1111 8684 0 0 4.60548 4.60548 -147.371 -4.60548 0 0 701300. 2426.64 0.19 0.05 0.11 -1 -1 0.19 0.0116548 0.0102947 164 60 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_041.v common 2.77 vpr 53.25 MiB -1 -1 0.14 17340 1 0.01 -1 -1 29768 -1 -1 31 31 0 0 success v8.0.0-7776-g6d5a301e6 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-05-04T19:10:09 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_2/vtr-verilog-to-routing/vtr_flow/tasks 54528 31 32 352 285 1 184 94 17 17 289 -1 unnamed_device 14.9 MiB 0.08 1038 53.2 MiB 0.06 0.00 3.81567 -112.348 -3.81567 3.81567 0.55 0.000121605 9.8015e-05 0.00956961 0.00789474 28 2455 22 6.64007e+06 389298 500653. 1732.36 0.65 0.0328765 0.0278803 21970 115934 -1 2217 17 1183 2053 131966 30969 0 0 131966 30969 2053 1482 0 0 7257 5807 0 0 10676 8497 0 0 2053 1627 0 0 54514 6955 0 0 55413 6601 0 0 2053 0 0 870 1286 1237 7994 0 0 3.41203 3.41203 -125.003 -3.41203 0 0 612192. 2118.31 0.18 0.03 0.06 -1 -1 0.18 0.00864164 0.00777866 135 51 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_042.v common 2.72 vpr 53.22 MiB -1 -1 0.10 17340 1 0.01 -1 -1 29764 -1 -1 23 32 0 0 success v8.0.0-7776-g6d5a301e6 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-05-04T19:10:09 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_2/vtr-verilog-to-routing/vtr_flow/tasks 54496 32 32 291 242 1 179 87 17 17 289 -1 unnamed_device 14.8 MiB 0.17 972 53.2 MiB 0.06 0.00 3.46356 -95.4486 -3.46356 3.46356 0.55 0.000106201 8.4883e-05 0.0101008 0.00825305 30 2237 22 6.64007e+06 288834 526063. 1820.29 0.54 0.0303909 0.0256094 22546 126617 -1 1766 21 983 1453 83203 19713 0 0 83203 19713 1453 1184 0 0 4922 3918 0 0 6502 5218 0 0 1453 1261 0 0 35559 3946 0 0 33314 4186 0 0 1453 0 0 470 481 498 4130 0 0 3.46143 3.46143 -109.196 -3.46143 0 0 666494. 2306.21 0.19 0.03 0.06 -1 -1 0.19 0.00868598 0.00776337 119 24 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_043.v common 2.81 vpr 53.73 MiB -1 -1 0.13 17796 1 0.01 -1 -1 29944 -1 -1 40 32 0 0 success v8.0.0-7776-g6d5a301e6 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-05-04T19:10:09 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_2/vtr-verilog-to-routing/vtr_flow/tasks 55020 32 32 457 356 1 223 104 17 17 289 -1 unnamed_device 15.5 MiB 0.20 1263 53.7 MiB 0.07 0.00 4.04253 -135.234 -4.04253 4.04253 0.55 0.000152113 0.000120727 0.0116882 0.00946554 28 3135 22 6.64007e+06 502320 500653. 1732.36 0.56 0.0402085 0.0338512 21970 115934 -1 2560 18 1430 2291 144476 33254 0 0 144476 33254 2291 1687 0 0 7907 6342 0 0 11547 8951 0 0 2291 1837 0 0 60480 7402 0 0 59960 7035 0 0 2291 0 0 861 1223 1316 9041 0 0 4.23489 4.23489 -152.675 -4.23489 0 0 612192. 2118.31 0.17 0.04 0.06 -1 -1 0.17 0.0107481 0.00962456 174 84 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_044.v common 2.59 vpr 53.00 MiB -1 -1 0.11 17080 1 0.00 -1 -1 29668 -1 -1 21 31 0 0 success v8.0.0-7776-g6d5a301e6 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-05-04T19:10:09 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_2/vtr-verilog-to-routing/vtr_flow/tasks 54272 31 32 261 225 1 142 84 17 17 289 -1 unnamed_device 14.5 MiB 0.05 726 53.0 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VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-05-04T19:10:09 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_2/vtr-verilog-to-routing/vtr_flow/tasks 54732 32 32 387 315 1 189 86 17 17 289 -1 unnamed_device 15.0 MiB 0.10 1122 53.4 MiB 0.07 0.00 3.37636 -107.7 -3.37636 3.37636 0.55 0.000129062 0.000103138 0.0111218 0.00911346 32 2779 21 6.64007e+06 276276 554710. 1919.41 0.59 0.0352953 0.029796 22834 132086 -1 2429 17 1375 2440 189319 40413 0 0 189319 40413 2440 1844 0 0 8509 7009 0 0 13642 9792 0 0 2440 2122 0 0 80471 9997 0 0 81817 9649 0 0 2440 0 0 1065 1070 955 8024 0 0 3.53642 3.53642 -127.001 -3.53642 0 0 701300. 2426.64 0.19 0.04 0.09 -1 -1 0.19 0.00934774 0.0084165 136 74 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_055.v common 2.75 vpr 52.91 MiB -1 -1 0.10 17172 1 0.01 -1 -1 29704 -1 -1 24 32 0 0 success v8.0.0-7776-g6d5a301e6 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-05-04T19:10:09 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_2/vtr-verilog-to-routing/vtr_flow/tasks 54180 32 32 251 219 1 140 88 17 17 289 -1 unnamed_device 14.5 MiB 0.03 612 52.9 MiB 0.05 0.00 2.7119 -78.5001 -2.7119 2.7119 0.55 0.000104229 8.3761e-05 0.00757779 0.00619584 26 1952 44 6.64007e+06 301392 477104. 1650.88 0.74 0.0303334 0.0256265 21682 110474 -1 1461 18 873 1358 87504 21972 0 0 87504 21972 1358 1054 0 0 4870 3738 0 0 6892 5357 0 0 1358 1122 0 0 35908 5609 0 0 37118 5092 0 0 1358 0 0 485 633 613 4543 0 0 2.77597 2.77597 -96.3472 -2.77597 0 0 585099. 2024.56 0.16 0.02 0.06 -1 -1 0.16 0.00645755 0.00576333 97 20 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_056.v common 2.75 vpr 53.35 MiB -1 -1 0.09 17400 1 0.01 -1 -1 29692 -1 -1 22 32 0 0 success v8.0.0-7776-g6d5a301e6 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-05-04T19:10:09 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_2/vtr-verilog-to-routing/vtr_flow/tasks 54628 32 32 341 285 1 187 86 17 17 289 -1 unnamed_device 14.7 MiB 0.16 1015 53.3 MiB 0.04 0.00 3.21396 -113.796 -3.21396 3.21396 0.55 0.000114482 9.2227e-05 0.00538522 0.00448771 28 2498 16 6.64007e+06 276276 500653. 1732.36 0.55 0.0256474 0.0218268 21970 115934 -1 2182 23 1479 2112 147458 33641 0 0 147458 33641 2112 1792 0 0 7460 5894 0 0 11125 8706 0 0 2112 1979 0 0 63041 7500 0 0 61608 7770 0 0 2112 0 0 633 620 513 5144 0 0 3.21737 3.21737 -132.833 -3.21737 0 0 612192. 2118.31 0.17 0.04 0.06 -1 -1 0.17 0.00946116 0.00837988 127 62 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_057.v common 2.97 vpr 53.47 MiB -1 -1 0.09 17768 1 0.01 -1 -1 29812 -1 -1 29 32 0 0 success v8.0.0-7776-g6d5a301e6 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-05-04T19:10:09 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_2/vtr-verilog-to-routing/vtr_flow/tasks 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success v8.0.0-7776-g6d5a301e6 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-05-04T19:10:09 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_2/vtr-verilog-to-routing/vtr_flow/tasks 54720 32 32 358 289 1 175 88 17 17 289 -1 unnamed_device 14.8 MiB 0.08 925 53.4 MiB 0.04 0.00 3.64276 -112.993 -3.64276 3.64276 0.55 0.000123876 9.9123e-05 0.00546559 0.00455518 28 2144 24 6.64007e+06 301392 500653. 1732.36 0.57 0.029422 0.0251232 21970 115934 -1 1945 22 1459 2270 151414 35459 0 0 151414 35459 2270 1692 0 0 8269 6640 0 0 12231 9773 0 0 2270 1839 0 0 65249 7443 0 0 61125 8072 0 0 2270 0 0 811 764 955 6990 0 0 3.79303 3.79303 -130.827 -3.79303 0 0 612192. 2118.31 0.17 0.03 0.06 -1 -1 0.17 0.00981499 0.00873706 130 51 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_068.v common 2.79 vpr 53.29 MiB -1 -1 0.10 17580 1 0.01 -1 -1 29676 -1 -1 28 32 0 0 success v8.0.0-7776-g6d5a301e6 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-05-04T19:10:09 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_2/vtr-verilog-to-routing/vtr_flow/tasks 54572 32 32 353 285 1 181 92 17 17 289 -1 unnamed_device 14.7 MiB 0.13 1055 53.3 MiB 0.07 0.00 3.83895 -115.935 -3.83895 3.83895 0.56 0.000120369 9.6508e-05 0.0102625 0.00840317 32 2456 18 6.64007e+06 351624 554710. 1919.41 0.57 0.0321812 0.0272046 22834 132086 -1 2151 19 1242 2252 155825 35419 0 0 155825 35419 2252 1629 0 0 8173 6887 0 0 12566 9549 0 0 2252 1883 0 0 66925 7475 0 0 63657 7996 0 0 2252 0 0 1010 1222 1132 8562 0 0 3.51823 3.51823 -128.445 -3.51823 0 0 701300. 2426.64 0.19 0.03 0.07 -1 -1 0.19 0.00903614 0.00810556 133 48 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_069.v common 2.68 vpr 52.86 MiB -1 -1 0.09 17492 1 0.01 -1 -1 29744 -1 -1 17 32 0 0 success v8.0.0-7776-g6d5a301e6 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-05-04T19:10:09 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_2/vtr-verilog-to-routing/vtr_flow/tasks 54124 32 32 276 237 1 159 81 17 17 289 -1 unnamed_device 14.3 MiB 0.17 918 52.9 MiB 0.04 0.00 3.75438 -111.435 -3.75438 3.75438 0.56 9.9749e-05 8.0401e-05 0.00627655 0.00519491 26 2221 18 6.64007e+06 213486 477104. 1650.88 0.52 0.0243897 0.020808 21682 110474 -1 1889 18 941 1289 91196 21957 0 0 91196 21957 1289 1080 0 0 4826 3919 0 0 6998 5594 0 0 1289 1122 0 0 38356 4936 0 0 38438 5306 0 0 1289 0 0 348 397 372 3160 0 0 3.51843 3.51843 -124.499 -3.51843 0 0 585099. 2024.56 0.16 0.02 0.05 -1 -1 0.16 0.00711376 0.00639106 105 31 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_070.v common 2.75 vpr 53.19 MiB -1 -1 0.10 17564 1 0.01 -1 -1 29736 -1 -1 19 31 0 0 success v8.0.0-7776-g6d5a301e6 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-05-04T19:10:09 betzgrp-wintermute.eecg.utoronto.ca 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betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_2/vtr-verilog-to-routing/vtr_flow/tasks 54560 32 32 326 263 1 176 94 17 17 289 -1 unnamed_device 14.7 MiB 0.04 954 53.3 MiB 0.07 0.00 4.24618 -108.493 -4.24618 4.24618 0.55 0.000115431 9.2505e-05 0.0108024 0.00878598 30 2269 22 6.64007e+06 376740 526063. 1820.29 0.56 0.0322656 0.0271436 22546 126617 -1 1777 19 954 1564 93721 21530 0 0 93721 21530 1564 1130 0 0 5271 3990 0 0 6973 5640 0 0 1564 1241 0 0 40135 4690 0 0 38214 4839 0 0 1564 0 0 610 617 595 5026 0 0 3.61042 3.61042 -118.868 -3.61042 0 0 666494. 2306.21 0.18 0.03 0.06 -1 -1 0.18 0.00847769 0.0075879 126 31 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_100.v common 2.74 vpr 53.55 MiB -1 -1 0.11 17448 1 0.01 -1 -1 29744 -1 -1 34 31 0 0 success v8.0.0-7776-g6d5a301e6 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-05-04T19:10:09 betzgrp-wintermute.eecg.utoronto.ca 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v8.0.0-7776-g6d5a301e6 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-05-04T19:10:09 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_2/vtr-verilog-to-routing/vtr_flow/tasks 54976 31 32 396 325 1 183 95 17 17 289 -1 unnamed_device 15.0 MiB 0.21 888 53.7 MiB 0.05 0.00 3.50555 -107.078 -3.50555 3.50555 0.56 0.000132143 0.000105849 0.00811695 0.00666739 32 2180 19 6.64007e+06 401856 554710. 1919.41 0.55 0.0318381 0.0269095 22834 132086 -1 1817 19 1289 1875 117083 29016 0 0 117083 29016 1875 1426 0 0 6858 5689 0 0 10630 8146 0 0 1875 1597 0 0 48019 6238 0 0 47826 5920 0 0 1875 0 0 586 718 690 5533 0 0 3.33103 3.33103 -126.524 -3.33103 0 0 701300. 2426.64 0.20 0.03 0.07 -1 -1 0.20 0.0094928 0.00846339 138 87 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_113.v common 2.72 vpr 53.04 MiB -1 -1 0.14 17480 1 0.01 -1 -1 29712 -1 -1 17 32 0 0 success v8.0.0-7776-g6d5a301e6 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on 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betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_2/vtr-verilog-to-routing/vtr_flow/tasks 54496 32 32 290 244 1 175 85 17 17 289 -1 unnamed_device 14.8 MiB 0.15 977 53.2 MiB 0.06 0.00 3.43507 -111.507 -3.43507 3.43507 0.56 0.000103933 8.2933e-05 0.00910614 0.00741899 32 2185 21 6.64007e+06 263718 554710. 1919.41 0.56 0.0287436 0.0242364 22834 132086 -1 2000 20 1306 1951 145495 32684 0 0 145495 32684 1951 1636 0 0 7277 6071 0 0 10929 8380 0 0 1951 1777 0 0 61134 7636 0 0 62253 7184 0 0 1951 0 0 645 630 539 5055 0 0 3.19163 3.19163 -121.579 -3.19163 0 0 701300. 2426.64 0.19 0.03 0.07 -1 -1 0.19 0.0078704 0.0069811 117 31 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_115.v common 2.94 vpr 53.33 MiB -1 -1 0.15 17660 1 0.01 -1 -1 29748 -1 -1 23 32 0 0 success v8.0.0-7776-g6d5a301e6 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-05-04T19:10:09 betzgrp-wintermute.eecg.utoronto.ca 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success v8.0.0-7776-g6d5a301e6 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-05-04T19:10:09 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_2/vtr-verilog-to-routing/vtr_flow/tasks 54068 25 32 216 194 1 122 84 17 17 289 -1 unnamed_device 14.2 MiB 0.03 498 52.8 MiB 0.04 0.00 2.6929 -63.3531 -2.6929 2.6929 0.55 8.1268e-05 6.4933e-05 0.00605757 0.00488039 28 1465 34 6.64007e+06 339066 500653. 1732.36 0.62 0.0234143 0.0196586 21970 115934 -1 1223 21 732 1244 86849 21862 0 0 86849 21862 1244 982 0 0 4670 3869 0 0 6730 5357 0 0 1244 1063 0 0 35184 5446 0 0 37777 5145 0 0 1244 0 0 512 674 681 4905 0 0 2.76677 2.76677 -75.8206 -2.76677 0 0 612192. 2118.31 0.17 0.02 0.06 -1 -1 0.17 0.00616416 0.00547103 89 19 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_127.v common 3.02 vpr 53.45 MiB -1 -1 0.09 17584 1 0.01 -1 -1 29704 -1 -1 21 32 0 0 success v8.0.0-7776-g6d5a301e6 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-05-04T19:10:09 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_2/vtr-verilog-to-routing/vtr_flow/tasks 54736 32 32 376 307 1 185 85 17 17 289 -1 unnamed_device 15.0 MiB 0.10 977 53.5 MiB 0.07 0.00 3.73696 -113.519 -3.73696 3.73696 0.55 0.000132767 0.000106805 0.012326 0.0101276 28 2870 23 6.64007e+06 263718 500653. 1732.36 0.81 0.0409855 0.0349564 21970 115934 -1 2437 21 1399 2455 210044 53926 0 0 210044 53926 2455 1928 0 0 8568 7023 0 0 12569 9621 0 0 2455 2059 0 0 91865 16858 0 0 92132 16437 0 0 2455 0 0 1056 1354 1165 8480 0 0 3.93103 3.93103 -138.054 -3.93103 0 0 612192. 2118.31 0.18 0.04 0.06 -1 -1 0.18 0.0101824 0.00903346 136 69 -1 -1 -1 -1 -fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_128.v common 3.05 vpr 53.59 MiB -1 -1 0.11 17728 1 0.01 -1 -1 29856 -1 -1 35 31 0 0 success v8.0.0-7776-g6d5a301e6 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-05-04T19:10:09 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_2/vtr-verilog-to-routing/vtr_flow/tasks 54876 31 32 409 331 1 191 98 17 17 289 -1 unnamed_device 15.0 MiB 0.17 919 53.6 MiB 0.05 0.00 3.48461 -113.085 -3.48461 3.48461 0.55 0.000142359 0.00011412 0.00807117 0.00664184 30 2153 20 6.64007e+06 439530 526063. 1820.29 0.57 0.0338106 0.0286208 22546 126617 -1 1864 19 1229 1964 113173 26571 0 0 113173 26571 1964 1364 0 0 6612 5107 0 0 8457 6863 0 0 1964 1501 0 0 47269 5683 0 0 46907 6053 0 0 1964 0 0 735 823 822 6214 0 0 3.10897 3.10897 -122.024 -3.10897 0 0 666494. 2306.21 0.28 0.05 0.11 -1 -1 0.28 0.0166697 0.0148861 143 86 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_001.v common 3.20 vpr 53.48 MiB -1 -1 0.11 17512 1 0.01 -1 -1 29700 -1 -1 30 32 0 0 success v8.0.0-7776-g6d5a301e6 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-05-04T19:10:09 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_2/vtr-verilog-to-routing/vtr_flow/tasks 54764 32 32 354 285 1 202 94 17 17 289 -1 unnamed_device 14.8 MiB 0.32 1084 53.5 MiB 0.10 0.00 4.10361 -122.482 -4.10361 4.10361 0.55 0.000126684 0.000101239 0.0150988 0.0123431 32 2676 30 6.65987e+06 380340 554710. 1919.41 0.62 0.0418199 0.0352988 22834 132086 -1 2167 20 1561 2461 165899 40926 0 0 165899 40926 2461 1889 0 0 9655 8232 0 0 14990 11808 0 0 2461 2028 0 0 67416 8575 0 0 68916 8394 0 0 2461 0 0 900 1129 1047 8251 0 0 4.30897 4.30897 -143.206 -4.30897 0 0 701300. 2426.64 0.26 0.06 0.08 -1 -1 0.26 0.015609 0.0139376 152 47 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_002.v common 3.15 vpr 53.55 MiB -1 -1 0.17 17484 1 0.02 -1 -1 29764 -1 -1 23 30 0 0 success v8.0.0-7776-g6d5a301e6 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-05-04T19:10:09 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_2/vtr-verilog-to-routing/vtr_flow/tasks 54832 30 32 363 293 1 194 85 17 17 289 -1 unnamed_device 14.9 MiB 0.22 1130 53.5 MiB 0.07 0.00 3.90862 -119.942 -3.90862 3.90862 0.57 0.000124553 0.000100277 0.0120174 0.00991081 32 2644 22 6.65987e+06 291594 554710. 1919.41 0.59 0.0372481 0.0317317 22834 132086 -1 2352 18 1509 2257 198253 42601 0 0 198253 42601 2257 1909 0 0 8696 7420 0 0 13325 10490 0 0 2257 1998 0 0 83727 11044 0 0 87991 9740 0 0 2257 0 0 748 722 622 5845 0 0 4.22583 4.22583 -143.33 -4.22583 0 0 701300. 2426.64 0.27 0.06 0.06 -1 -1 0.27 0.0149134 0.01361 138 58 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_003.v common 2.63 vpr 53.15 MiB -1 -1 0.11 17360 1 0.01 -1 -1 29692 -1 -1 23 32 0 0 success v8.0.0-7776-g6d5a301e6 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-05-04T19:10:09 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_2/vtr-verilog-to-routing/vtr_flow/tasks 54424 32 32 299 247 1 188 87 17 17 289 -1 unnamed_device 14.5 MiB 0.07 1078 53.1 MiB 0.03 0.00 3.21404 -100.176 -3.21404 3.21404 0.55 0.000109114 8.8191e-05 0.00562153 0.00470795 30 2211 19 6.65987e+06 291594 526063. 1820.29 0.53 0.0260291 0.0223506 22546 126617 -1 1918 16 910 1280 67072 16737 0 0 67072 16737 1280 976 0 0 4451 3642 0 0 5699 4724 0 0 1280 1065 0 0 27317 3059 0 0 27045 3271 0 0 1280 0 0 370 321 371 3206 0 0 3.17971 3.17971 -114.132 -3.17971 0 0 666494. 2306.21 0.18 0.02 0.06 -1 -1 0.18 0.00796935 0.00726307 126 26 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_004.v common 2.72 vpr 52.96 MiB -1 -1 0.09 17532 1 0.01 -1 -1 29812 -1 -1 27 29 0 0 success v8.0.0-7776-g6d5a301e6 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-05-04T19:10:09 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_2/vtr-verilog-to-routing/vtr_flow/tasks 54232 29 32 308 248 1 169 88 17 17 289 -1 unnamed_device 14.5 MiB 0.06 920 53.0 MiB 0.04 0.00 3.39544 -91.96 -3.39544 3.39544 0.55 0.000110939 8.8651e-05 0.00693663 0.00575608 28 2050 20 6.65987e+06 342306 500653. 1732.36 0.63 0.0276388 0.0235468 21970 115934 -1 1915 21 1479 2745 169488 40952 0 0 169488 40952 2745 1856 0 0 9992 8347 0 0 15257 12008 0 0 2745 2115 0 0 68292 8382 0 0 70457 8244 0 0 2745 0 0 1266 1596 1640 11065 0 0 3.30391 3.30391 -111.304 -3.30391 0 0 612192. 2118.31 0.17 0.04 0.06 -1 -1 0.17 0.00900894 0.00805762 126 25 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_005.v common 2.79 vpr 53.01 MiB -1 -1 0.10 17476 1 0.01 -1 -1 29712 -1 -1 23 32 0 0 success v8.0.0-7776-g6d5a301e6 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-05-04T19:10:09 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_2/vtr-verilog-to-routing/vtr_flow/tasks 54280 32 32 336 268 1 174 87 17 17 289 -1 unnamed_device 14.4 MiB 0.07 879 53.0 MiB 0.06 0.00 3.48115 -101.76 -3.48115 3.48115 0.56 0.000118822 9.5794e-05 0.00882929 0.00727797 32 2720 23 6.65987e+06 291594 554710. 1919.41 0.60 0.0317856 0.0270158 22834 132086 -1 2094 23 1627 3030 207045 49022 0 0 207045 49022 3030 2382 0 0 11282 9650 0 0 17420 13401 0 0 3030 2551 0 0 85014 10678 0 0 87269 10360 0 0 3030 0 0 1403 1826 1708 11811 0 0 3.41891 3.41891 -121.07 -3.41891 0 0 701300. 2426.64 0.19 0.04 0.07 -1 -1 0.19 0.0100637 0.00896938 130 31 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_006.v common 2.70 vpr 53.44 MiB -1 -1 0.10 17508 1 0.01 -1 -1 29652 -1 -1 33 32 0 0 success v8.0.0-7776-g6d5a301e6 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-05-04T19:10:09 betzgrp-wintermute.eecg.utoronto.ca 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VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-05-04T19:10:09 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_2/vtr-verilog-to-routing/vtr_flow/tasks 54544 32 32 342 271 1 179 95 17 17 289 -1 unnamed_device 14.9 MiB 0.05 1053 53.3 MiB 0.06 0.00 3.36036 -109.189 -3.36036 3.36036 0.58 0.000122295 9.7987e-05 0.0100997 0.00825388 30 2104 31 6.65987e+06 393018 526063. 1820.29 0.60 0.0356164 0.0301141 22546 126617 -1 1879 19 1052 1686 102005 23529 0 0 102005 23529 1686 1155 0 0 5988 4830 0 0 7854 6553 0 0 1686 1265 0 0 41679 5141 0 0 43112 4585 0 0 1686 0 0 634 649 617 5606 0 0 3.39343 3.39343 -123.011 -3.39343 0 0 666494. 2306.21 0.18 0.03 0.06 -1 -1 0.18 0.00926859 0.00833096 135 31 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_022.v common 2.97 vpr 53.49 MiB -1 -1 0.09 17560 1 0.01 -1 -1 29712 -1 -1 23 32 0 0 success v8.0.0-7776-g6d5a301e6 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-05-04T19:10:09 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_2/vtr-verilog-to-routing/vtr_flow/tasks 54776 32 32 372 300 1 204 87 17 17 289 -1 unnamed_device 14.8 MiB 0.17 1125 53.5 MiB 0.07 0.00 3.36484 -108.843 -3.36484 3.36484 0.60 0.000126498 0.000101067 0.0116833 0.00955341 28 3137 27 6.65987e+06 291594 500653. 1732.36 0.69 0.0373853 0.0315642 21970 115934 -1 2513 20 1729 2617 214199 47773 0 0 214199 47773 2617 2128 0 0 9625 7995 0 0 14506 11743 0 0 2617 2398 0 0 93018 12058 0 0 91816 11451 0 0 2617 0 0 888 1042 1009 7870 0 0 3.68491 3.68491 -129.445 -3.68491 0 0 612192. 2118.31 0.17 0.04 0.06 -1 -1 0.17 0.00999005 0.00894979 142 59 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_023.v common 2.79 vpr 52.45 MiB -1 -1 0.10 17096 1 0.00 -1 -1 29676 -1 -1 18 26 0 0 success v8.0.0-7776-g6d5a301e6 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-05-04T19:10:09 betzgrp-wintermute.eecg.utoronto.ca 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/home/mahmo494/Desktop/RLplace_2/vtr-verilog-to-routing/vtr_flow/tasks 54892 31 32 383 305 1 210 88 17 17 289 -1 unnamed_device 15.1 MiB 0.97 1065 53.6 MiB 0.08 0.00 4.00075 -117.157 -4.00075 4.00075 0.55 0.000129655 0.000104568 0.0131954 0.0108312 32 2715 22 6.65987e+06 316950 554710. 1919.41 0.59 0.0385019 0.0325226 22834 132086 -1 2323 20 1705 2597 219213 47406 0 0 219213 47406 2597 2098 0 0 9954 8362 0 0 14876 11696 0 0 2597 2239 0 0 98187 11197 0 0 91002 11814 0 0 2597 0 0 892 1027 888 7414 0 0 4.41923 4.41923 -150.557 -4.41923 0 0 701300. 2426.64 0.19 0.04 0.07 -1 -1 0.19 0.010688 0.00959462 162 60 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_041.v common 3.07 vpr 53.37 MiB -1 -1 0.11 17664 1 0.00 -1 -1 29780 -1 -1 29 31 0 0 success v8.0.0-7776-g6d5a301e6 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-05-04T19:10:09 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_2/vtr-verilog-to-routing/vtr_flow/tasks 54648 31 32 352 285 1 184 92 17 17 289 -1 unnamed_device 14.9 MiB 0.16 856 53.4 MiB 0.05 0.00 3.37089 -97.7088 -3.37089 3.37089 0.60 0.000125232 9.9477e-05 0.00690657 0.0057315 28 2522 41 6.65987e+06 367662 500653. 1732.36 0.82 0.0369269 0.0315119 21970 115934 -1 2006 23 1465 2461 148158 38042 0 0 148158 38042 2461 1764 0 0 8829 7424 0 0 13413 10521 0 0 2461 1916 0 0 60997 8341 0 0 59997 8076 0 0 2461 0 0 996 1231 1222 8852 0 0 2.97525 2.97525 -110.998 -2.97525 0 0 612192. 2118.31 0.19 0.04 0.06 -1 -1 0.19 0.010369 0.00925375 133 51 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_042.v common 2.76 vpr 52.98 MiB -1 -1 0.10 17480 1 0.01 -1 -1 29728 -1 -1 22 32 0 0 success v8.0.0-7776-g6d5a301e6 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-05-04T19:10:09 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_2/vtr-verilog-to-routing/vtr_flow/tasks 54256 32 32 291 242 1 179 86 17 17 289 -1 unnamed_device 14.6 MiB 0.12 1064 53.0 MiB 0.05 0.00 3.22104 -93.8179 -3.22104 3.22104 0.55 0.000105882 8.5506e-05 0.00815528 0.00674993 32 2277 22 6.65987e+06 278916 554710. 1919.41 0.59 0.0320432 0.0273413 22834 132086 -1 2004 18 1224 1831 133000 30938 0 0 133000 30938 1831 1458 0 0 7263 6038 0 0 10588 8436 0 0 1831 1540 0 0 55261 6913 0 0 56226 6553 0 0 1831 0 0 607 693 810 5537 0 0 3.46799 3.46799 -112.746 -3.46799 0 0 701300. 2426.64 0.19 0.03 0.07 -1 -1 0.19 0.00793552 0.00716054 118 24 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_043.v common 3.07 vpr 53.42 MiB -1 -1 0.11 17776 1 0.01 -1 -1 29892 -1 -1 38 32 0 0 success v8.0.0-7776-g6d5a301e6 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-05-04T19:10:09 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_2/vtr-verilog-to-routing/vtr_flow/tasks 54704 32 32 457 356 1 223 102 17 17 289 -1 unnamed_device 15.2 MiB 0.20 1307 53.4 MiB 0.10 0.00 3.94735 -130.391 -3.94735 3.94735 0.54 0.000150845 0.000120935 0.0145551 0.0118836 30 2969 29 6.65987e+06 481764 526063. 1820.29 0.80 0.0540174 0.0458019 22546 126617 -1 2437 21 1601 2535 140228 33352 0 0 140228 33352 2535 1741 0 0 8662 7104 0 0 11267 9190 0 0 2535 1899 0 0 57064 6650 0 0 58165 6768 0 0 2535 0 0 934 1351 1272 9774 0 0 3.79291 3.79291 -145.665 -3.79291 0 0 666494. 2306.21 0.18 0.04 0.06 -1 -1 0.18 0.0122965 0.0110409 172 84 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_044.v common 2.67 vpr 52.64 MiB -1 -1 0.10 17248 1 0.01 -1 -1 29676 -1 -1 21 31 0 0 success v8.0.0-7776-g6d5a301e6 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-05-04T19:10:09 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_2/vtr-verilog-to-routing/vtr_flow/tasks 53900 31 32 261 225 1 142 84 17 17 289 -1 unnamed_device 14.1 MiB 0.08 741 52.6 MiB 0.03 0.00 2.74078 -78.476 -2.74078 2.74078 0.55 9.6783e-05 7.8003e-05 0.00468613 0.00388061 28 1909 21 6.65987e+06 266238 500653. 1732.36 0.59 0.0242614 0.0206319 21970 115934 -1 1650 21 996 1749 120673 28838 0 0 120673 28838 1749 1292 0 0 6495 5467 0 0 9987 7886 0 0 1749 1370 0 0 51363 6028 0 0 49330 6795 0 0 1749 0 0 753 798 864 6216 0 0 2.64539 2.64539 -98.0766 -2.64539 0 0 612192. 2118.31 0.17 0.03 0.06 -1 -1 0.17 0.00770501 0.00685783 101 24 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_045.v common 3.01 vpr 53.47 MiB -1 -1 0.10 17484 1 0.02 -1 -1 29860 -1 -1 23 31 0 0 success v8.0.0-7776-g6d5a301e6 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-05-04T19:10:09 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_2/vtr-verilog-to-routing/vtr_flow/tasks 54756 31 32 337 267 1 205 86 17 17 289 -1 unnamed_device 14.8 MiB 0.16 1226 53.5 MiB 0.07 0.00 3.8195 -115.518 -3.8195 3.8195 0.59 0.000119025 9.5949e-05 0.0112521 0.0093123 28 2816 27 6.65987e+06 291594 500653. 1732.36 0.72 0.0390807 0.0334501 21970 115934 -1 2405 22 1407 1965 145447 33847 0 0 145447 33847 1965 1670 0 0 7520 6267 0 0 11221 9171 0 0 1965 1761 0 0 60458 7743 0 0 62318 7235 0 0 1965 0 0 558 606 695 5302 0 0 3.99251 3.99251 -135.355 -3.99251 0 0 612192. 2118.31 0.17 0.03 0.06 -1 -1 0.17 0.0101803 0.00912986 142 30 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_046.v common 2.67 vpr 53.11 MiB -1 -1 0.08 17360 1 0.01 -1 -1 29756 -1 -1 33 32 0 0 success v8.0.0-7776-g6d5a301e6 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-05-04T19:10:09 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_2/vtr-verilog-to-routing/vtr_flow/tasks 54388 32 32 349 284 1 183 97 17 17 289 -1 unnamed_device 14.7 MiB 0.10 935 53.1 MiB 0.04 0.00 3.1757 -96.1015 -3.1757 3.1757 0.55 0.000123123 9.9439e-05 0.00604527 0.00504428 30 2419 20 6.65987e+06 418374 526063. 1820.29 0.58 0.0286008 0.0244199 22546 126617 -1 1852 23 1089 2079 116400 28087 0 0 116400 28087 2079 1501 0 0 6929 5510 0 0 9349 7315 0 0 2079 1586 0 0 46831 6106 0 0 49133 6069 0 0 2079 0 0 990 1165 1203 8585 0 0 2.74651 2.74651 -105.848 -2.74651 0 0 666494. 2306.21 0.18 0.03 0.06 -1 -1 0.18 0.0102482 0.0091396 131 50 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_047.v common 3.15 vpr 52.89 MiB -1 -1 0.09 16924 1 0.01 -1 -1 29660 -1 -1 24 32 0 0 success v8.0.0-7776-g6d5a301e6 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-05-04T19:10:09 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_2/vtr-verilog-to-routing/vtr_flow/tasks 54160 32 32 291 230 1 168 88 17 17 289 -1 unnamed_device 14.4 MiB 0.06 1001 52.9 MiB 0.06 0.00 3.15084 -101.746 -3.15084 3.15084 0.55 0.000115525 9.2156e-05 0.00949686 0.00782584 34 2254 21 6.65987e+06 304272 585099. 2024.56 1.01 0.043402 0.0367435 23122 138558 -1 1959 21 1292 2563 172276 38930 0 0 172276 38930 2563 1678 0 0 9262 7631 0 0 14281 11088 0 0 2563 1976 0 0 74763 7881 0 0 68844 8676 0 0 2563 0 0 1271 1621 1719 11026 0 0 3.35599 3.35599 -114.412 -3.35599 0 0 742403. 2568.87 0.20 0.04 0.07 -1 -1 0.20 0.00872323 0.00781576 123 -1 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_048.v common 3.11 vpr 53.33 MiB -1 -1 0.12 17368 1 0.02 -1 -1 29796 -1 -1 22 32 0 0 success v8.0.0-7776-g6d5a301e6 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-05-04T19:10:09 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_2/vtr-verilog-to-routing/vtr_flow/tasks 54612 32 32 353 287 1 198 86 17 17 289 -1 unnamed_device 14.8 MiB 0.25 1093 53.3 MiB 0.06 0.00 3.33475 -103.887 -3.33475 3.33475 0.55 0.000122518 9.7822e-05 0.0107816 0.00879815 28 2713 30 6.65987e+06 278916 500653. 1732.36 0.76 0.0369478 0.0311593 21970 115934 -1 2325 20 1165 1640 133636 30650 0 0 133636 30650 1640 1432 0 0 6186 5125 0 0 8804 7142 0 0 1640 1475 0 0 56919 8095 0 0 58447 7381 0 0 1640 0 0 475 609 638 4576 0 0 3.50731 3.50731 -122.711 -3.50731 0 0 612192. 2118.31 0.17 0.03 0.06 -1 -1 0.17 0.00980696 0.0088242 136 52 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_049.v common 3.04 vpr 53.47 MiB -1 -1 0.11 17516 1 0.02 -1 -1 29708 -1 -1 31 32 0 0 success v8.0.0-7776-g6d5a301e6 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-05-04T19:10:09 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_2/vtr-verilog-to-routing/vtr_flow/tasks 54756 32 32 361 291 1 185 95 17 17 289 -1 unnamed_device 14.8 MiB 0.34 941 53.5 MiB 0.07 0.00 2.9071 -94.6052 -2.9071 2.9071 0.55 0.000122411 9.799e-05 0.0109253 0.00887627 32 2577 25 6.65987e+06 393018 554710. 1919.41 0.59 0.0358038 0.0300231 22834 132086 -1 2025 18 1260 2164 151113 35373 0 0 151113 35373 2164 1528 0 0 8025 6647 0 0 12731 9592 0 0 2164 1706 0 0 61965 8148 0 0 64064 7752 0 0 2164 0 0 904 1536 1318 9596 0 0 3.12451 3.12451 -109.621 -3.12451 0 0 701300. 2426.64 0.21 0.03 0.09 -1 -1 0.21 0.0094268 0.00848374 132 52 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_050.v common 2.84 vpr 53.63 MiB -1 -1 0.09 17696 1 0.01 -1 -1 29784 -1 -1 36 32 0 0 success v8.0.0-7776-g6d5a301e6 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-05-04T19:10:09 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_2/vtr-verilog-to-routing/vtr_flow/tasks 54916 32 32 382 305 1 192 100 17 17 289 -1 unnamed_device 14.8 MiB 0.27 1111 53.6 MiB 0.07 0.00 3.47495 -108.938 -3.47495 3.47495 0.55 0.000143476 0.000113261 0.0112406 0.00901177 30 2401 21 6.65987e+06 456408 526063. 1820.29 0.54 0.0359828 0.0302689 22546 126617 -1 2051 20 1043 1578 94653 21637 0 0 94653 21637 1578 1203 0 0 5423 4254 0 0 6944 5745 0 0 1578 1281 0 0 40688 4470 0 0 38442 4684 0 0 1578 0 0 535 603 576 4744 0 0 3.19151 3.19151 -123.682 -3.19151 0 0 666494. 2306.21 0.19 0.03 0.06 -1 -1 0.19 0.010149 0.00909617 144 59 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_051.v common 2.74 vpr 53.15 MiB -1 -1 0.10 17364 1 0.03 -1 -1 29772 -1 -1 29 32 0 0 success v8.0.0-7776-g6d5a301e6 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-05-04T19:10:09 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_2/vtr-verilog-to-routing/vtr_flow/tasks 54424 32 32 306 248 1 166 93 17 17 289 -1 unnamed_device 14.6 MiB 0.07 854 53.1 MiB 0.06 0.00 3.20104 -95.0693 -3.20104 3.20104 0.55 0.000110966 8.9287e-05 0.00990864 0.00812862 32 2200 24 6.65987e+06 367662 554710. 1919.41 0.59 0.0322121 0.0273503 22834 132086 -1 1814 21 1349 2126 164406 38161 0 0 164406 38161 2126 1567 0 0 8401 6907 0 0 12864 10239 0 0 2126 1668 0 0 74061 8418 0 0 64828 9362 0 0 2126 0 0 777 914 946 7069 0 0 3.44705 3.44705 -111.984 -3.44705 0 0 701300. 2426.64 0.19 0.03 0.07 -1 -1 0.19 0.00892403 0.00796609 122 21 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_052.v common 2.73 vpr 53.30 MiB -1 -1 0.08 17576 1 0.00 -1 -1 29700 -1 -1 23 32 0 0 success v8.0.0-7776-g6d5a301e6 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-05-04T19:10:09 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_2/vtr-verilog-to-routing/vtr_flow/tasks 54576 32 32 319 257 1 198 87 17 17 289 -1 unnamed_device 14.9 MiB 0.11 1150 53.3 MiB 0.04 0.00 3.71955 -112.95 -3.71955 3.71955 0.58 0.000115602 9.2381e-05 0.00687657 0.00568442 28 2455 21 6.65987e+06 291594 500653. 1732.36 0.55 0.0285629 0.0243702 21970 115934 -1 2182 21 1417 2108 125001 31141 0 0 125001 31141 2108 1634 0 0 7783 6473 0 0 11460 9317 0 0 2108 1811 0 0 51532 5728 0 0 50010 6178 0 0 2108 0 0 691 710 712 5679 0 0 3.49637 3.49637 -127.553 -3.49637 0 0 612192. 2118.31 0.17 0.03 0.06 -1 -1 0.17 0.00923738 0.00827357 133 26 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_053.v common 3.19 vpr 53.48 MiB -1 -1 0.11 17628 1 0.01 -1 -1 29744 -1 -1 23 31 0 0 success v8.0.0-7776-g6d5a301e6 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-05-04T19:10:09 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_2/vtr-verilog-to-routing/vtr_flow/tasks 54768 31 32 373 299 1 202 86 17 17 289 -1 unnamed_device 14.8 MiB 0.21 1154 53.5 MiB 0.07 0.00 3.54855 -110.543 -3.54855 3.54855 0.57 0.000125842 0.000101191 0.0115024 0.00947748 28 3155 26 6.65987e+06 291594 500653. 1732.36 0.76 0.0384189 0.0326878 21970 115934 -1 2516 24 1908 3094 236058 52838 0 0 236058 52838 3094 2537 0 0 11176 9296 0 0 16463 12988 0 0 3094 2814 0 0 105574 12301 0 0 96657 12902 0 0 3094 0 0 1186 1426 1564 10296 0 0 3.95331 3.95331 -132.429 -3.95331 0 0 612192. 2118.31 0.17 0.05 0.06 -1 -1 0.17 0.0108223 0.00960111 146 58 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_054.v common 2.90 vpr 53.50 MiB -1 -1 0.11 17588 1 0.02 -1 -1 29772 -1 -1 21 32 0 0 success v8.0.0-7776-g6d5a301e6 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-05-04T19:10:09 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_2/vtr-verilog-to-routing/vtr_flow/tasks 54788 32 32 387 315 1 189 85 17 17 289 -1 unnamed_device 14.8 MiB 0.12 978 53.5 MiB 0.07 0.00 3.13344 -101.178 -3.13344 3.13344 0.61 0.000134743 0.000108329 0.0121374 0.00992037 32 2685 19 6.65987e+06 266238 554710. 1919.41 0.62 0.0369172 0.0312307 22834 132086 -1 2183 20 1508 2650 202713 46271 0 0 202713 46271 2650 1967 0 0 10199 8559 0 0 15379 12162 0 0 2650 2129 0 0 89103 10093 0 0 82732 11361 0 0 2650 0 0 1142 1136 1023 8613 0 0 3.43505 3.43505 -123.49 -3.43505 0 0 701300. 2426.64 0.19 0.04 0.07 -1 -1 0.19 0.0101744 0.00909686 135 74 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_055.v common 2.78 vpr 52.75 MiB -1 -1 0.09 17152 1 0.00 -1 -1 29664 -1 -1 24 32 0 0 success v8.0.0-7776-g6d5a301e6 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-05-04T19:10:09 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_2/vtr-verilog-to-routing/vtr_flow/tasks 54016 32 32 251 219 1 140 88 17 17 289 -1 unnamed_device 14.3 MiB 0.09 620 52.8 MiB 0.05 0.00 2.66984 -76.8361 -2.66984 2.66984 0.58 9.5029e-05 7.6408e-05 0.00814101 0.00665297 28 1892 32 6.65987e+06 304272 500653. 1732.36 0.67 0.0282784 0.0238844 21970 115934 -1 1525 19 853 1325 97437 25039 0 0 97437 25039 1325 1063 0 0 4941 4126 0 0 7311 6065 0 0 1325 1138 0 0 41312 6249 0 0 41223 6398 0 0 1325 0 0 472 512 630 4353 0 0 3.03625 3.03625 -90.2131 -3.03625 0 0 612192. 2118.31 0.17 0.02 0.06 -1 -1 0.17 0.00696508 0.00624407 97 20 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_056.v common 2.90 vpr 53.23 MiB -1 -1 0.09 17460 1 0.00 -1 -1 29732 -1 -1 20 32 0 0 success v8.0.0-7776-g6d5a301e6 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-05-04T19:10:09 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_2/vtr-verilog-to-routing/vtr_flow/tasks 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IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-05-04T19:10:09 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_2/vtr-verilog-to-routing/vtr_flow/tasks 54084 32 32 276 237 1 159 80 17 17 289 -1 unnamed_device 14.2 MiB 0.18 983 52.8 MiB 0.03 0.00 3.5308 -105.115 -3.5308 3.5308 0.59 0.000105748 8.5755e-05 0.0049445 0.00417312 30 1987 20 6.65987e+06 202848 526063. 1820.29 0.51 0.0238413 0.0204491 22546 126617 -1 1689 23 791 1065 57553 14375 0 0 57553 14375 1065 855 0 0 3727 3011 0 0 4700 3955 0 0 1065 923 0 0 24436 2749 0 0 22560 2882 0 0 1065 0 0 274 206 253 2362 0 0 3.15571 3.15571 -112.339 -3.15571 0 0 666494. 2306.21 0.18 0.02 0.06 -1 -1 0.18 0.00841753 0.00750679 103 31 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_070.v common 2.73 vpr 53.11 MiB -1 -1 0.10 17456 1 0.01 -1 -1 29716 -1 -1 19 31 0 0 success v8.0.0-7776-g6d5a301e6 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-05-04T19:10:09 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_2/vtr-verilog-to-routing/vtr_flow/tasks 54388 31 32 319 272 1 168 82 17 17 289 -1 unnamed_device 14.5 MiB 0.15 936 53.1 MiB 0.03 0.00 3.09498 -102.254 -3.09498 3.09498 0.58 0.000109335 8.6833e-05 0.00567522 0.00471563 32 2214 22 6.65987e+06 240882 554710. 1919.41 0.54 0.0269131 0.022888 22834 132086 -1 1912 22 1173 1725 120388 28827 0 0 120388 28827 1725 1432 0 0 6641 5611 0 0 9983 7881 0 0 1725 1483 0 0 49914 6303 0 0 50400 6117 0 0 1725 0 0 552 558 516 4455 0 0 3.04865 3.04865 -117.416 -3.04865 0 0 701300. 2426.64 0.19 0.03 0.07 -1 -1 0.19 0.00895595 0.00797513 111 60 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_071.v common 2.97 vpr 53.13 MiB -1 -1 0.15 17584 1 0.02 -1 -1 29684 -1 -1 33 30 0 0 success v8.0.0-7776-g6d5a301e6 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-05-04T19:10:09 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_2/vtr-verilog-to-routing/vtr_flow/tasks 54404 30 32 329 273 1 166 95 17 17 289 -1 unnamed_device 14.6 MiB 0.15 970 53.1 MiB 0.06 0.00 2.55652 -78.2693 -2.55652 2.55652 0.56 0.000115913 9.3574e-05 0.00939243 0.00769717 26 2308 20 6.65987e+06 418374 477104. 1650.88 0.76 0.0324719 0.0276012 21682 110474 -1 1972 21 1112 1927 134019 30314 0 0 134019 30314 1927 1311 0 0 7185 5905 0 0 10446 8250 0 0 1927 1459 0 0 58261 6499 0 0 54273 6890 0 0 1927 0 0 815 1138 1384 8658 0 0 2.66645 2.66645 -98.5902 -2.66645 0 0 585099. 2024.56 0.16 0.03 0.05 -1 -1 0.16 0.00888939 0.00790601 123 52 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_072.v common 2.76 vpr 52.86 MiB -1 -1 0.10 17532 1 0.01 -1 -1 29776 -1 -1 35 28 0 0 success v8.0.0-7776-g6d5a301e6 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-05-04T19:10:09 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_2/vtr-verilog-to-routing/vtr_flow/tasks 54124 28 32 277 229 1 155 95 17 17 289 -1 unnamed_device 14.4 MiB 0.08 773 52.9 MiB 0.05 0.00 3.16278 -78.7825 -3.16278 3.16278 0.55 0.000100583 8.0124e-05 0.00774974 0.00633673 28 2055 34 6.65987e+06 443730 500653. 1732.36 0.69 0.0293638 0.0247426 21970 115934 -1 1697 24 1154 2205 144685 34629 0 0 144685 34629 2205 1374 0 0 8109 6650 0 0 12503 9761 0 0 2205 1515 0 0 57820 8037 0 0 61843 7292 0 0 2205 0 0 1051 1811 1760 11395 0 0 3.24679 3.24679 -98.5965 -3.24679 0 0 612192. 2118.31 0.17 0.03 0.06 -1 -1 0.17 0.0083602 0.00739054 115 20 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_073.v common 2.76 vpr 53.00 MiB -1 -1 0.10 17516 1 0.02 -1 -1 29768 -1 -1 17 30 0 0 success v8.0.0-7776-g6d5a301e6 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-05-04T19:10:09 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_2/vtr-verilog-to-routing/vtr_flow/tasks 54268 30 32 317 269 1 152 79 17 17 289 -1 unnamed_device 14.6 MiB 0.16 827 53.0 MiB 0.05 0.00 3.29355 -97.6112 -3.29355 3.29355 0.55 0.000110406 8.8404e-05 0.00979213 0.00801222 28 2040 19 6.65987e+06 215526 500653. 1732.36 0.57 0.0308712 0.0261522 21970 115934 -1 1781 19 1004 1766 118717 27158 0 0 118717 27158 1766 1266 0 0 6298 5303 0 0 8973 7072 0 0 1766 1395 0 0 48167 6407 0 0 51747 5715 0 0 1766 0 0 762 875 707 6064 0 0 2.84971 2.84971 -107.399 -2.84971 0 0 612192. 2118.31 0.17 0.03 0.06 -1 -1 0.17 0.00979272 0.00882527 108 58 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_074.v common 2.80 vpr 53.12 MiB -1 -1 0.10 17288 1 0.01 -1 -1 29832 -1 -1 20 32 0 0 success v8.0.0-7776-g6d5a301e6 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-05-04T19:10:09 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_2/vtr-verilog-to-routing/vtr_flow/tasks 54396 32 32 335 282 1 184 84 17 17 289 -1 unnamed_device 14.5 MiB 0.13 993 53.1 MiB 0.06 0.00 2.94464 -103.892 -2.94464 2.94464 0.55 0.000114452 9.1485e-05 0.0105135 0.00854856 32 2440 18 6.65987e+06 253560 554710. 1919.41 0.61 0.031202 0.0262813 22834 132086 -1 2068 20 1407 2050 173152 38478 0 0 173152 38478 2050 1696 0 0 7825 6417 0 0 12008 9374 0 0 2050 1781 0 0 74496 9984 0 0 74723 9226 0 0 2050 0 0 643 602 620 5201 0 0 2.85111 2.85111 -119.684 -2.85111 0 0 701300. 2426.64 0.19 0.04 0.07 -1 -1 0.19 0.00873503 0.00781716 120 62 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_075.v common 2.75 vpr 52.88 MiB -1 -1 0.10 17268 1 0.01 -1 -1 29712 -1 -1 32 31 0 0 success v8.0.0-7776-g6d5a301e6 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-05-04T19:10:09 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_2/vtr-verilog-to-routing/vtr_flow/tasks 54144 31 32 293 230 1 175 95 17 17 289 -1 unnamed_device 14.4 MiB 0.06 1036 52.9 MiB 0.07 0.00 3.27404 -99.2302 -3.27404 3.27404 0.55 0.00011047 8.9192e-05 0.00964626 0.00793634 32 2377 25 6.65987e+06 405696 554710. 1919.41 0.57 0.0312986 0.0265869 22834 132086 -1 2100 25 1532 2794 207033 45982 0 0 207033 45982 2794 2079 0 0 10616 8516 0 0 16649 12592 0 0 2794 2298 0 0 87751 10084 0 0 86429 10413 0 0 2794 0 0 1262 1683 1615 11142 0 0 3.37911 3.37911 -116.825 -3.37911 0 0 701300. 2426.64 0.19 0.04 0.07 -1 -1 0.19 0.00955668 0.00849999 127 -1 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_076.v common 2.78 vpr 53.55 MiB -1 -1 0.10 17724 1 0.01 -1 -1 29780 -1 -1 22 32 0 0 success v8.0.0-7776-g6d5a301e6 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-05-04T19:10:09 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_2/vtr-verilog-to-routing/vtr_flow/tasks 54840 32 32 350 275 1 209 86 17 17 289 -1 unnamed_device 14.9 MiB 0.19 1119 53.6 MiB 0.06 0.00 3.98521 -126.961 -3.98521 3.98521 0.55 0.000120611 9.7159e-05 0.00846662 0.00700637 30 2528 20 6.65987e+06 278916 526063. 1820.29 0.55 0.0325043 0.0277978 22546 126617 -1 2056 20 1152 1741 101079 23848 0 0 101079 23848 1741 1386 0 0 6069 4809 0 0 7646 6374 0 0 1741 1438 0 0 46346 4270 0 0 37536 5571 0 0 1741 0 0 589 558 474 4594 0 0 3.74071 3.74071 -137.557 -3.74071 0 0 666494. 2306.21 0.18 0.03 0.06 -1 -1 0.18 0.00975263 0.00877561 144 31 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_077.v common 2.92 vpr 53.43 MiB -1 -1 0.09 17484 1 0.01 -1 -1 29768 -1 -1 32 32 0 0 success v8.0.0-7776-g6d5a301e6 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-05-04T19:10:09 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_2/vtr-verilog-to-routing/vtr_flow/tasks 54716 32 32 385 308 1 185 96 17 17 289 -1 unnamed_device 14.9 MiB 0.22 933 53.4 MiB 0.08 0.00 3.92821 -111.484 -3.92821 3.92821 0.58 0.000130285 0.000104925 0.0119382 0.00977741 30 2138 22 6.65987e+06 405696 526063. 1820.29 0.60 0.0365481 0.030856 22546 126617 -1 1632 21 1125 1967 89347 23507 0 0 89347 23507 1967 1221 0 0 6508 5244 0 0 8781 6960 0 0 1967 1309 0 0 33956 4564 0 0 36168 4209 0 0 1967 0 0 842 1078 915 7550 0 0 3.64083 3.64083 -121.487 -3.64083 0 0 666494. 2306.21 0.24 0.03 0.06 -1 -1 0.24 0.0104006 0.00930705 142 62 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_078.v common 2.93 vpr 53.38 MiB -1 -1 0.10 17368 1 0.01 -1 -1 29688 -1 -1 37 32 0 0 success v8.0.0-7776-g6d5a301e6 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-05-04T19:10:09 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_2/vtr-verilog-to-routing/vtr_flow/tasks 54660 32 32 387 309 1 190 101 17 17 289 -1 unnamed_device 14.7 MiB 0.19 1113 53.4 MiB 0.06 0.00 3.30775 -109.49 -3.30775 3.30775 0.55 0.000131929 0.000106367 0.0090934 0.00749046 28 2766 24 6.65987e+06 469086 500653. 1732.36 0.68 0.0352259 0.0297203 21970 115934 -1 2312 23 1461 2581 176251 41037 0 0 176251 41037 2581 1894 0 0 9450 7789 0 0 14019 10878 0 0 2581 2118 0 0 76541 8918 0 0 71079 9440 0 0 2581 0 0 1120 1472 1416 10065 0 0 3.44291 3.44291 -129.418 -3.44291 0 0 612192. 2118.31 0.17 0.04 0.07 -1 -1 0.17 0.0108997 0.00968284 140 62 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_079.v common 2.80 vpr 52.83 MiB -1 -1 0.09 17328 1 0.00 -1 -1 29700 -1 -1 19 30 0 0 success v8.0.0-7776-g6d5a301e6 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-05-04T19:10:09 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_2/vtr-verilog-to-routing/vtr_flow/tasks 54096 30 32 272 232 1 147 81 17 17 289 -1 unnamed_device 14.3 MiB 0.23 879 52.8 MiB 0.05 0.00 2.76049 -88.2512 -2.76049 2.76049 0.55 9.7679e-05 7.7657e-05 0.00850047 0.0069418 30 1821 22 6.65987e+06 240882 526063. 1820.29 0.53 0.0276139 0.0233198 22546 126617 -1 1562 18 788 1348 71287 16728 0 0 71287 16728 1348 947 0 0 4359 3455 0 0 5898 4577 0 0 1348 1152 0 0 29574 3293 0 0 28760 3304 0 0 1348 0 0 560 534 497 4317 0 0 2.46385 2.46385 -96.0168 -2.46385 0 0 666494. 2306.21 0.19 0.03 0.06 -1 -1 0.19 0.00920698 0.00826256 105 29 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_080.v common 3.03 vpr 53.25 MiB -1 -1 0.13 17416 1 0.00 -1 -1 29804 -1 -1 21 30 0 0 success v8.0.0-7776-g6d5a301e6 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-05-04T19:10:09 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_2/vtr-verilog-to-routing/vtr_flow/tasks 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21 6.65987e+06 393018 554710. 1919.41 0.55 0.0351639 0.0296335 22834 132086 -1 1988 21 1346 2251 157085 38008 0 0 157085 38008 2251 1640 0 0 8891 7578 0 0 14261 11223 0 0 2251 1931 0 0 64849 7937 0 0 64582 7699 0 0 2251 0 0 905 967 948 7569 0 0 2.99311 2.99311 -112.884 -2.99311 0 0 701300. 2426.64 0.19 0.06 0.07 -1 -1 0.19 0.0157101 0.014036 133 78 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_084.v common 2.90 vpr 53.12 MiB -1 -1 0.10 17512 1 0.01 -1 -1 29712 -1 -1 20 32 0 0 success v8.0.0-7776-g6d5a301e6 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-05-04T19:10:09 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_2/vtr-verilog-to-routing/vtr_flow/tasks 54396 32 32 365 294 1 185 84 17 17 289 -1 unnamed_device 14.7 MiB 0.14 1027 53.1 MiB 0.07 0.00 3.76955 -112.412 -3.76955 3.76955 0.55 0.000126352 0.000101115 0.0130915 0.0107011 32 2788 30 6.65987e+06 253560 554710. 1919.41 0.64 0.0394013 0.0333031 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-3.16871 0 0 585099. 2024.56 0.19 0.04 0.05 -1 -1 0.19 0.012847 0.0114601 110 25 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_108.v common 2.69 vpr 52.90 MiB -1 -1 0.09 17236 1 0.01 -1 -1 29700 -1 -1 16 32 0 0 success v8.0.0-7776-g6d5a301e6 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-05-04T19:10:09 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_2/vtr-verilog-to-routing/vtr_flow/tasks 54172 32 32 278 238 1 149 80 17 17 289 -1 unnamed_device 14.4 MiB 0.15 814 52.9 MiB 0.04 0.00 2.90269 -93.5111 -2.90269 2.90269 0.55 0.000101544 8.1618e-05 0.0075873 0.006245 30 1839 22 6.65987e+06 202848 526063. 1820.29 0.55 0.0269106 0.0228614 22546 126617 -1 1605 23 1118 1989 111092 25761 0 0 111092 25761 1989 1356 0 0 6547 5151 0 0 8612 6828 0 0 1989 1578 0 0 47006 5166 0 0 44949 5682 0 0 1989 0 0 871 1051 939 7012 0 0 2.61131 2.61131 -101.243 -2.61131 0 0 666494. 2306.21 0.18 0.03 0.07 -1 -1 0.18 0.00846322 0.00753081 109 31 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_109.v common 2.78 vpr 53.45 MiB -1 -1 0.12 17368 1 0.01 -1 -1 29808 -1 -1 35 31 0 0 success v8.0.0-7776-g6d5a301e6 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-05-04T19:10:09 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_2/vtr-verilog-to-routing/vtr_flow/tasks 54736 31 32 373 300 1 181 98 17 17 289 -1 unnamed_device 14.8 MiB 0.18 933 53.5 MiB 0.07 0.00 3.14515 -96.7165 -3.14515 3.14515 0.55 0.000128838 0.00010356 0.0118865 0.00970393 30 1942 22 6.65987e+06 443730 526063. 1820.29 0.54 0.0362526 0.0306137 22546 126617 -1 1802 17 995 1574 81363 19677 0 0 81363 19677 1574 1040 0 0 5268 4226 0 0 6713 5457 0 0 1574 1127 0 0 32394 4123 0 0 33840 3704 0 0 1574 0 0 579 679 740 5446 0 0 2.79096 2.79096 -107.779 -2.79096 0 0 666494. 2306.21 0.18 0.02 0.06 -1 -1 0.18 0.00914583 0.00826458 135 60 -1 -1 -1 -1 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mult_111.v common 3.47 vpr 53.31 MiB -1 -1 0.15 17360 1 0.01 -1 -1 29684 -1 -1 31 32 0 0 success v8.0.0-7776-g6d5a301e6 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-05-04T19:10:09 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_2/vtr-verilog-to-routing/vtr_flow/tasks 54588 32 32 349 286 1 171 95 17 17 289 -1 unnamed_device 14.9 MiB 0.19 1014 53.3 MiB 0.06 0.00 2.82075 -93.8051 -2.82075 2.82075 0.55 0.0001192 9.6007e-05 0.00939601 0.00765409 26 2495 26 6.65987e+06 393018 477104. 1650.88 1.13 0.0360343 0.0306366 21682 110474 -1 2163 23 1306 2279 193061 41448 0 0 193061 41448 2279 1598 0 0 8701 7197 0 0 13246 10485 0 0 2279 1758 0 0 84860 9874 0 0 81696 10536 0 0 2279 0 0 973 1411 1665 10344 0 0 2.67651 2.67651 -108.672 -2.67651 0 0 585099. 2024.56 0.18 0.06 0.06 -1 -1 0.18 0.0148391 0.0133507 126 54 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_112.v common 3.41 vpr 53.34 MiB -1 -1 0.10 17596 1 0.01 -1 -1 29792 -1 -1 32 31 0 0 success v8.0.0-7776-g6d5a301e6 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-05-04T19:10:09 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_2/vtr-verilog-to-routing/vtr_flow/tasks 54624 31 32 396 325 1 183 95 17 17 289 -1 unnamed_device 14.7 MiB 0.66 943 53.3 MiB 0.07 0.00 3.50555 -111.405 -3.50555 3.50555 0.55 0.000131308 0.000105244 0.0114753 0.00937574 32 2184 20 6.65987e+06 405696 554710. 1919.41 0.54 0.0355363 0.0299909 22834 132086 -1 1991 23 1464 1986 154136 36207 0 0 154136 36207 1986 1629 0 0 7656 6521 0 0 12753 9888 0 0 1986 1720 0 0 64833 8492 0 0 64922 7957 0 0 1986 0 0 522 551 561 5026 0 0 3.29183 3.29183 -129.054 -3.29183 0 0 701300. 2426.64 0.27 0.06 0.07 -1 -1 0.27 0.0163558 0.0143422 138 87 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_113.v common 2.77 vpr 52.88 MiB -1 -1 0.10 17660 1 0.02 -1 -1 29716 -1 -1 17 32 0 0 success v8.0.0-7776-g6d5a301e6 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-05-04T19:10:09 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_2/vtr-verilog-to-routing/vtr_flow/tasks 54144 32 32 303 262 1 150 81 17 17 289 -1 unnamed_device 14.2 MiB 0.20 759 52.9 MiB 0.04 0.00 2.54264 -82.2128 -2.54264 2.54264 0.55 0.000111811 8.455e-05 0.00626183 0.00505166 28 1974 22 6.65987e+06 215526 500653. 1732.36 0.61 0.0263123 0.0221684 21970 115934 -1 1684 20 817 1286 96576 22495 0 0 96576 22495 1286 1018 0 0 4606 3821 0 0 6786 5339 0 0 1286 1039 0 0 41854 5529 0 0 40758 5749 0 0 1286 0 0 469 414 409 3606 0 0 2.73671 2.73671 -105.81 -2.73671 0 0 612192. 2118.31 0.17 0.03 0.06 -1 -1 0.17 0.00793219 0.00707912 104 54 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_114.v common 2.76 vpr 53.05 MiB -1 -1 0.10 17368 1 0.01 -1 -1 29788 -1 -1 19 32 0 0 success v8.0.0-7776-g6d5a301e6 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-05-04T19:10:09 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_2/vtr-verilog-to-routing/vtr_flow/tasks 54328 32 32 290 244 1 175 83 17 17 289 -1 unnamed_device 14.6 MiB 0.13 965 53.1 MiB 0.06 0.00 3.35195 -108.382 -3.35195 3.35195 0.56 0.000102624 8.1903e-05 0.0102168 0.00833319 32 2288 22 6.65987e+06 240882 554710. 1919.41 0.55 0.0299512 0.025245 22834 132086 -1 1982 22 1303 1919 157599 35134 0 0 157599 35134 1919 1649 0 0 7478 6415 0 0 11778 9270 0 0 1919 1713 0 0 70779 7552 0 0 63726 8535 0 0 1919 0 0 616 573 477 4817 0 0 3.02531 3.02531 -117.799 -3.02531 0 0 701300. 2426.64 0.19 0.03 0.07 -1 -1 0.19 0.0084309 0.00750712 115 31 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_115.v common 3.05 vpr 53.38 MiB -1 -1 0.10 17484 1 0.01 -1 -1 29692 -1 -1 22 32 0 0 success v8.0.0-7776-g6d5a301e6 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-05-04T19:10:09 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_2/vtr-verilog-to-routing/vtr_flow/tasks 54660 32 32 318 257 1 194 86 17 17 289 -1 unnamed_device 14.8 MiB 0.09 897 53.4 MiB 0.03 0.00 3.7011 -110.351 -3.7011 3.7011 0.55 0.00011622 9.3431e-05 0.00559183 0.0046649 28 2758 48 6.65987e+06 278916 500653. 1732.36 0.96 0.0345049 0.0294074 21970 115934 -1 2148 24 1623 2320 170606 42155 0 0 170606 42155 2320 1889 0 0 8694 7172 0 0 12374 10136 0 0 2320 2009 0 0 72565 9710 0 0 72333 11239 0 0 2320 0 0 697 762 751 5996 0 0 4.16751 4.16751 -134.655 -4.16751 0 0 612192. 2118.31 0.17 0.04 0.06 -1 -1 0.17 0.0100364 0.00893612 130 27 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_116.v common 3.51 vpr 53.06 MiB -1 -1 0.10 17668 1 0.02 -1 -1 29704 -1 -1 28 29 0 0 success v8.0.0-7776-g6d5a301e6 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-05-04T19:10:09 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_2/vtr-verilog-to-routing/vtr_flow/tasks 54336 29 32 324 268 1 168 89 17 17 289 -1 unnamed_device 14.5 MiB 0.31 805 53.1 MiB 0.04 0.00 3.59335 -92.7366 -3.59335 3.59335 0.55 0.000113662 9.1182e-05 0.00680183 0.00561212 26 2741 44 6.65987e+06 354984 477104. 1650.88 1.09 0.0362901 0.030969 21682 110474 -1 1801 22 1037 1677 139387 34990 0 0 139387 34990 1677 1334 0 0 6307 5140 0 0 9429 7492 0 0 1677 1390 0 0 59370 9550 0 0 60927 10084 0 0 1677 0 0 640 911 847 6431 0 0 3.29871 3.29871 -109.577 -3.29871 0 0 585099. 2024.56 0.16 0.03 0.05 -1 -1 0.16 0.00915867 0.00818333 121 49 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_117.v common 2.85 vpr 53.37 MiB -1 -1 0.10 17676 1 0.01 -1 -1 29692 -1 -1 23 32 0 0 success v8.0.0-7776-g6d5a301e6 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-05-04T19:10:09 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_2/vtr-verilog-to-routing/vtr_flow/tasks 54648 32 32 393 312 1 213 87 17 17 289 -1 unnamed_device 15.1 MiB 0.18 1189 53.4 MiB 0.05 0.00 4.06506 -132.8 -4.06506 4.06506 0.55 0.000133325 0.000107217 0.0080496 0.0066776 32 2820 25 6.65987e+06 291594 554710. 1919.41 0.57 0.0341872 0.0290852 22834 132086 -1 2378 22 1988 2929 208830 48342 0 0 208830 48342 2929 2233 0 0 11158 9579 0 0 17614 13614 0 0 2929 2441 0 0 87116 10169 0 0 87084 10306 0 0 2929 0 0 941 1092 988 8494 0 0 4.15071 4.15071 -152.032 -4.15071 0 0 701300. 2426.64 0.19 0.04 0.07 -1 -1 0.19 0.0109968 0.00977349 153 62 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_118.v common 2.62 vpr 52.59 MiB -1 -1 0.10 17056 1 0.01 -1 -1 29540 -1 -1 18 31 0 0 success v8.0.0-7776-g6d5a301e6 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-05-04T19:10:09 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_2/vtr-verilog-to-routing/vtr_flow/tasks 53848 31 32 229 197 1 138 81 17 17 289 -1 unnamed_device 14.0 MiB 0.06 601 52.6 MiB 0.05 0.00 2.79204 -75.5102 -2.79204 2.79204 0.58 8.8932e-05 7.1475e-05 0.00813116 0.00665591 28 1769 25 6.65987e+06 228204 500653. 1732.36 0.54 0.0257643 0.021833 21970 115934 -1 1444 26 858 1400 151542 58713 0 0 151542 58713 1400 1149 0 0 5154 4201 0 0 8498 6495 0 0 1400 1200 0 0 66412 22679 0 0 68678 22989 0 0 1400 0 0 542 614 503 4329 0 0 2.70676 2.70676 -94.2005 -2.70676 0 0 612192. 2118.31 0.17 0.04 0.06 -1 -1 0.17 0.00791949 0.00703988 96 -1 -1 -1 -1 -1 -fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_119.v common 3.00 vpr 53.59 MiB -1 -1 0.10 17752 1 0.01 -1 -1 29796 -1 -1 33 32 0 0 success v8.0.0-7776-g6d5a301e6 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-05-04T19:10:09 betzgrp-wintermute.eecg.utoronto.ca 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/home/mahmo494/Desktop/RLplace_2/vtr-verilog-to-routing/vtr_flow/tasks 54152 32 32 303 262 1 200 82 17 17 289 -1 unnamed_device 14.2 MiB 1.94 1069 52.9 MiB 0.05 0.00 3.0513 -96.5592 -3.0513 3.0513 0.56 0.000104986 8.3987e-05 0.00837092 0.0067949 36 2612 19 6.89349e+06 253689 648988. 2245.63 1.27 0.0389632 0.0323811 26050 158493 -1 2158 19 1506 1995 168339 34689 0 0 168339 34689 1995 1655 0 0 7026 5495 0 0 9933 7812 0 0 1995 1822 0 0 70496 9701 0 0 76894 8204 0 0 1995 0 0 489 514 521 4519 0 0 2.94656 2.94656 -113.927 -2.94656 0 0 828058. 2865.25 0.22 0.03 0.13 -1 -1 0.22 0.00729069 0.006457 124 54 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml mult_114.v common 4.18 vpr 52.58 MiB -1 -1 0.16 17432 1 0.01 -1 -1 29736 -1 -1 18 32 0 0 success v8.0.0-7776-g6d5a301e6 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-05-04T19:10:09 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_2/vtr-verilog-to-routing/vtr_flow/tasks 53840 32 32 290 244 1 177 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0.01 -1 -1 29756 -1 -1 26 32 0 0 success v8.0.0-7776-g6d5a301e6 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-05-04T19:10:09 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_2/vtr-verilog-to-routing/vtr_flow/tasks 54648 32 32 396 299 1 241 90 17 17 289 -1 unnamed_device 14.7 MiB 1.96 1369 53.4 MiB 0.06 0.00 4.7624 -145.974 -4.7624 4.7624 0.56 0.000135639 0.000108954 0.00874284 0.00720346 36 3005 21 6.89349e+06 366440 648988. 2245.63 1.47 0.0482078 0.0405349 26050 158493 -1 2637 23 2042 3242 259853 55443 0 0 259853 55443 3242 2523 0 0 11672 9516 0 0 18160 14061 0 0 3242 2617 0 0 111295 13127 0 0 112242 13599 0 0 3242 0 0 1200 1717 1576 10815 0 0 4.71575 4.71575 -158.636 -4.71575 0 0 828058. 2865.25 0.31 0.08 0.14 -1 -1 0.31 0.0174796 0.0153529 172 31 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml mult_123.v common 3.55 vpr 52.21 MiB -1 -1 0.09 17248 1 0.00 -1 -1 29740 -1 -1 15 30 0 0 success v8.0.0-7776-g6d5a301e6 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-05-04T19:10:09 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_2/vtr-verilog-to-routing/vtr_flow/tasks 53464 30 32 224 207 1 137 77 17 17 289 -1 unnamed_device 13.6 MiB 0.66 686 52.2 MiB 0.04 0.00 2.38626 -77.3379 -2.38626 2.38626 0.56 8.139e-05 6.4223e-05 0.00674407 0.00543304 34 1636 20 6.89349e+06 211408 618332. 2139.56 0.86 0.0301105 0.0249825 25762 151098 -1 1446 21 847 1148 111221 24276 0 0 111221 24276 1148 966 0 0 4385 3629 0 0 7211 5547 0 0 1148 998 0 0 47329 6540 0 0 50000 6596 0 0 1148 0 0 301 321 351 2723 0 0 2.13627 2.13627 -88.7943 -2.13627 0 0 787024. 2723.27 0.20 0.03 0.08 -1 -1 0.20 0.00613738 0.005369 82 29 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml mult_124.v common 3.90 vpr 52.63 MiB -1 -1 0.09 17384 1 0.01 -1 -1 29684 -1 -1 20 30 0 0 success v8.0.0-7776-g6d5a301e6 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-05-04T19:10:09 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_2/vtr-verilog-to-routing/vtr_flow/tasks 53892 30 32 286 239 1 176 82 17 17 289 -1 unnamed_device 14.1 MiB 0.94 973 52.6 MiB 0.05 0.00 3.70827 -117.45 -3.70827 3.70827 0.56 0.000105047 8.3757e-05 0.00844543 0.0068637 34 2219 21 6.89349e+06 281877 618332. 2139.56 0.92 0.0382036 0.0319372 25762 151098 -1 1862 20 1248 1841 133058 30182 0 0 133058 30182 1841 1518 0 0 6960 5769 0 0 10439 8381 0 0 1841 1572 0 0 55314 6801 0 0 56663 6141 0 0 1841 0 0 593 696 425 5027 0 0 3.34945 3.34945 -126.918 -3.34945 0 0 787024. 2723.27 0.20 0.03 0.08 -1 -1 0.20 0.007071 0.00624771 119 29 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml mult_125.v common 4.64 vpr 52.74 MiB -1 -1 0.08 17552 1 0.01 -1 -1 29740 -1 -1 18 32 0 0 success v8.0.0-7776-g6d5a301e6 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-05-04T19:10:09 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_2/vtr-verilog-to-routing/vtr_flow/tasks 54004 32 32 296 247 1 187 82 17 17 289 -1 unnamed_device 14.2 MiB 1.48 1110 52.7 MiB 0.05 0.00 3.53059 -115.631 -3.53059 3.53059 0.57 0.000109293 8.7893e-05 0.00898085 0.00734193 34 2807 24 6.89349e+06 253689 618332. 2139.56 1.06 0.0419076 0.0352472 25762 151098 -1 2319 19 1457 2625 207423 46057 0 0 207423 46057 2625 2075 0 0 9707 8055 0 0 15706 12058 0 0 2625 2290 0 0 88055 11067 0 0 88705 10512 0 0 2625 0 0 1168 1478 1405 10052 0 0 3.5001 3.5001 -133.964 -3.5001 0 0 787024. 2723.27 0.20 0.04 0.08 -1 -1 0.20 0.00729147 0.00645473 120 31 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml mult_126.v common 3.84 vpr 52.22 MiB -1 -1 0.13 17120 1 0.01 -1 -1 29840 -1 -1 21 25 0 0 success v8.0.0-7776-g6d5a301e6 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-05-04T19:10:09 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_2/vtr-verilog-to-routing/vtr_flow/tasks 53476 25 32 216 194 1 138 78 17 17 289 -1 unnamed_device 13.7 MiB 0.93 569 52.2 MiB 0.04 0.00 3.0161 -71.862 -3.0161 3.0161 0.56 8.2712e-05 6.5964e-05 0.00690819 0.00564019 34 1615 26 6.89349e+06 295971 618332. 2139.56 0.85 0.0311374 0.0257816 25762 151098 -1 1192 21 801 1265 75547 19358 0 0 75547 19358 1265 1024 0 0 4596 3744 0 0 7351 5604 0 0 1265 1078 0 0 30592 3997 0 0 30478 3911 0 0 1265 0 0 464 598 561 4170 0 0 2.74511 2.74511 -77.3962 -2.74511 0 0 787024. 2723.27 0.20 0.02 0.08 -1 -1 0.20 0.00581386 0.00511094 92 19 -1 -1 -1 -1 -fixed_k6_frac_uripple_N8_22nm.xml mult_127.v common 5.51 vpr 53.14 MiB -1 -1 0.12 17432 1 0.01 -1 -1 29688 -1 -1 23 32 0 0 success v8.0.0-7776-g6d5a301e6 release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-05-04T19:10:09 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_2/vtr-verilog-to-routing/vtr_flow/tasks 54416 32 32 376 307 1 242 87 17 17 289 -1 unnamed_device 14.4 MiB 1.79 1406 53.1 MiB 0.05 0.00 3.72115 -114.833 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place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops crit_path_total_internal_heap_pushes crit_path_total_internal_heap_pops crit_path_total_external_heap_pushes crit_path_total_external_heap_pops crit_path_total_external_SOURCE_pushes crit_path_total_external_SOURCE_pops crit_path_total_internal_SOURCE_pushes crit_path_total_internal_SOURCE_pops crit_path_total_external_SINK_pushes crit_path_total_external_SINK_pops crit_path_total_internal_SINK_pushes crit_path_total_internal_SINK_pops crit_path_total_external_IPIN_pushes crit_path_total_external_IPIN_pops crit_path_total_internal_IPIN_pushes crit_path_total_internal_IPIN_pops crit_path_total_external_OPIN_pushes crit_path_total_external_OPIN_pops crit_path_total_internal_OPIN_pushes crit_path_total_internal_OPIN_pops crit_path_total_external_CHANX_pushes crit_path_total_external_CHANX_pops crit_path_total_internal_CHANX_pushes crit_path_total_internal_CHANX_pops crit_path_total_external_CHANY_pushes crit_path_total_external_CHANY_pops crit_path_total_internal_CHANY_pushes crit_path_total_internal_CHANY_pops crit_path_rt_node_SOURCE_pushes crit_path_rt_node_SINK_pushes crit_path_rt_node_IPIN_pushes crit_path_rt_node_OPIN_pushes crit_path_rt_node_CHANX_pushes crit_path_rt_node_CHANY_pushes crit_path_adding_all_rt crit_path_adding_high_fanout_rt crit_path_total_number_of_adding_all_rt_from_calling_high_fanout_rt critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length + fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_001.v common 6.55 vpr 63.55 MiB -1 -1 0.16 21120 14 0.25 -1 -1 36804 -1 -1 27 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65072 32 32 277 309 1 204 91 17 17 289 -1 unnamed_device 25.0 MiB 0.42 1378 63.5 MiB 0.04 0.00 6.64956 -137.729 -6.64956 6.64956 0.78 0.00023397 0.000195213 0.0115046 0.0098606 34 3695 34 6.55708e+06 325485 585099. 2024.56 3.26 0.110793 0.0963584 22462 138074 -1 3102 19 1318 4070 239449 54673 0 0 239449 54673 4070 2018 0 0 14049 11633 0 0 22585 16481 0 0 4070 2550 0 0 96411 11135 0 0 98264 10856 0 0 4070 0 0 2752 4450 5180 32160 0 0 7.30964 7.30964 -162.262 -7.30964 0 0 742403. 2568.87 0.24 0.05 0.08 -1 -1 0.24 0.0152609 0.0137943 183 182 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_002.v common 4.57 vpr 63.63 MiB -1 -1 0.17 21068 14 0.29 -1 -1 36072 -1 -1 31 30 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65160 30 32 272 304 1 210 93 17 17 289 -1 unnamed_device 25.2 MiB 0.52 1311 63.6 MiB 0.06 0.00 6.85276 -131.872 -6.85276 6.85276 0.75 0.000232163 0.000194378 0.0132119 0.0111154 28 3453 19 6.55708e+06 373705 500653. 1732.36 1.08 0.0601354 0.0524157 21310 115450 -1 3110 17 1475 4185 247016 57006 0 0 247016 57006 4185 2298 0 0 14300 11659 0 0 22131 16665 0 0 4185 2715 0 0 99679 12118 0 0 102536 11551 0 0 4185 0 0 2710 5104 4892 32299 0 0 6.97296 6.97296 -152.035 -6.97296 0 0 612192. 2118.31 0.22 0.06 0.07 -1 -1 0.22 0.0162763 0.0148285 184 181 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_003.v common 7.17 vpr 63.52 MiB -1 -1 0.15 20744 11 0.22 -1 -1 35948 -1 -1 26 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65040 32 32 280 312 1 205 90 17 17 289 -1 unnamed_device 24.9 MiB 0.35 1407 63.5 MiB 0.06 0.00 6.11164 -120.209 -6.11164 6.11164 0.76 0.000238955 0.000199992 0.0167906 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fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_007.v common 6.61 vpr 63.26 MiB -1 -1 0.14 20864 12 0.19 -1 -1 35944 -1 -1 27 27 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64780 27 32 229 261 1 176 86 17 17 289 -1 unnamed_device 24.7 MiB 0.26 1010 63.3 MiB 0.06 0.00 5.95024 -108.676 -5.95024 5.95024 0.87 0.000192247 0.000152637 0.014133 0.0115023 28 2669 45 6.55708e+06 325485 500653. 1732.36 3.37 0.0917088 0.0787583 21310 115450 -1 2296 18 1170 3102 171861 40357 0 0 171861 40357 3102 1710 0 0 10554 8455 0 0 16652 12260 0 0 3102 1977 0 0 68423 8148 0 0 70028 7807 0 0 3102 0 0 1932 2593 3175 20176 0 0 6.19064 6.19064 -125.711 -6.19064 0 0 612192. 2118.31 0.25 0.04 0.16 -1 -1 0.25 0.0125487 0.011395 152 144 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_008.v common 4.86 vpr 63.28 MiB -1 -1 0.14 20716 12 0.18 -1 -1 36020 -1 -1 22 31 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64796 31 32 229 261 1 184 85 17 17 289 -1 unnamed_device 24.8 MiB 0.22 1184 63.3 MiB 0.06 0.00 5.3864 -117.646 -5.3864 5.3864 0.78 0.00017634 0.000144911 0.0133295 0.0109964 34 3309 38 6.55708e+06 265210 585099. 2024.56 1.81 0.068353 0.0591361 22462 138074 -1 2619 17 1190 3678 220500 49832 0 0 220500 49832 3678 1811 0 0 12527 10348 0 0 20797 14997 0 0 3678 2170 0 0 88561 10493 0 0 91259 10013 0 0 3678 0 0 2488 5115 4968 32463 0 0 5.67826 5.67826 -134.483 -5.67826 0 0 742403. 2568.87 0.25 0.05 0.09 -1 -1 0.25 0.0125829 0.0113642 140 136 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_009.v common 4.80 vpr 63.39 MiB -1 -1 0.15 21068 12 0.16 -1 -1 35860 -1 -1 26 31 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64912 31 32 235 267 1 192 89 17 17 289 -1 unnamed_device 24.8 MiB 0.25 1185 63.4 MiB 0.05 0.00 5.54278 -115.705 -5.54278 5.54278 0.75 0.000181148 0.000148934 0.01052 0.00882348 36 2812 19 6.55708e+06 313430 612192. 2118.31 1.75 0.0807672 0.0714902 22750 144809 -1 2500 19 989 2479 138734 32102 0 0 138734 32102 2479 1337 0 0 8427 6769 0 0 12543 9501 0 0 2479 1600 0 0 55969 6620 0 0 56837 6275 0 0 2479 0 0 1490 2262 2166 15567 0 0 5.66298 5.66298 -130.577 -5.66298 0 0 782063. 2706.10 0.26 0.04 0.09 -1 -1 0.26 0.0134631 0.0122535 150 142 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_010.v common 11.31 vpr 63.32 MiB -1 -1 0.15 20744 13 0.19 -1 -1 36012 -1 -1 25 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64844 32 32 250 282 1 193 89 17 17 289 -1 unnamed_device 24.7 MiB 0.28 1122 63.3 MiB 0.05 0.00 6.10764 -131.404 -6.10764 6.10764 0.75 0.000207809 0.00017318 0.0123806 0.0103196 28 3805 49 6.55708e+06 301375 500653. 1732.36 8.22 0.107082 0.0929183 21310 115450 -1 2905 28 1305 3489 332701 113018 0 0 332701 113018 3489 2124 0 0 12455 10324 0 0 19672 15037 0 0 3489 2393 0 0 143528 42076 0 0 150068 41064 0 0 3489 0 0 2184 4164 3900 25181 0 0 6.37758 6.37758 -156.713 -6.37758 0 0 612192. 2118.31 0.22 0.08 0.07 -1 -1 0.22 0.0187667 0.0167838 157 155 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_011.v common 5.78 vpr 63.23 MiB -1 -1 0.14 21092 12 0.19 -1 -1 35872 -1 -1 24 30 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64752 30 32 216 248 1 168 86 17 17 289 -1 unnamed_device 24.9 MiB 0.32 1000 63.2 MiB 0.05 0.00 6.15344 -116.886 -6.15344 6.15344 0.74 0.000179765 0.000150006 0.0113664 0.00952438 34 2373 31 6.55708e+06 289320 585099. 2024.56 2.71 0.0916434 0.0793369 22462 138074 -1 2100 16 890 2426 132391 31263 0 0 132391 31263 2426 1178 0 0 8319 6744 0 0 13317 9661 0 0 2426 1488 0 0 52271 6325 0 0 53632 5867 0 0 2426 0 0 1536 2442 2444 16908 0 0 6.27364 6.27364 -130.709 -6.27364 0 0 742403. 2568.87 0.25 0.04 0.09 -1 -1 0.25 0.0115305 0.0105413 132 125 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_012.v common 4.70 vpr 63.18 MiB -1 -1 0.15 21068 12 0.14 -1 -1 36192 -1 -1 22 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64692 32 32 236 268 1 183 86 17 17 289 -1 unnamed_device 24.7 MiB 0.23 1183 63.2 MiB 0.05 0.00 5.71546 -130.205 -5.71546 5.71546 0.94 0.0001904 0.000159016 0.0125007 0.0107766 28 3148 27 6.55708e+06 265210 500653. 1732.36 1.51 0.0558721 0.0489226 21310 115450 -1 2728 15 1057 2891 174259 40386 0 0 174259 40386 2891 1619 0 0 9990 8119 0 0 15173 11462 0 0 2891 1859 0 0 72462 8609 0 0 70852 8718 0 0 2891 0 0 1834 2963 3265 20857 0 0 6.00932 6.00932 -152.843 -6.00932 0 0 612192. 2118.31 0.22 0.04 0.07 -1 -1 0.22 0.0122995 0.0112357 146 141 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_013.v common 6.50 vpr 63.66 MiB -1 -1 0.18 20928 13 0.25 -1 -1 36024 -1 -1 30 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65184 32 32 283 315 1 223 94 17 17 289 -1 unnamed_device 25.2 MiB 0.22 1389 63.7 MiB 0.05 0.00 6.72796 -141.789 -6.72796 6.72796 0.77 0.000224998 0.000185112 0.0127975 0.0109101 34 3291 23 6.55708e+06 361650 585099. 2024.56 3.17 0.13924 0.121977 22462 138074 -1 2865 14 1170 3367 184952 43579 0 0 184952 43579 3367 1663 0 0 11879 9496 0 0 18366 13888 0 0 3367 1971 0 0 73101 8579 0 0 74872 7982 0 0 3367 0 0 2197 4139 4384 29223 0 0 6.96836 6.96836 -158.438 -6.96836 0 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common 4.38 vpr 63.18 MiB -1 -1 0.14 21016 11 0.17 -1 -1 35776 -1 -1 27 29 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64700 29 32 225 257 1 174 88 17 17 289 -1 unnamed_device 24.7 MiB 0.23 960 63.2 MiB 0.05 0.00 5.53818 -107.159 -5.53818 5.53818 0.91 0.000189989 0.000149652 0.0125054 0.0103483 28 3059 34 6.55708e+06 325485 500653. 1732.36 1.24 0.0549045 0.0473058 21310 115450 -1 2443 15 1075 2913 191816 44712 0 0 191816 44712 2913 1652 0 0 10053 8116 0 0 15478 11606 0 0 2913 1920 0 0 79904 10919 0 0 80555 10499 0 0 2913 0 0 1838 3155 3118 20250 0 0 5.65838 5.65838 -123.364 -5.65838 0 0 612192. 2118.31 0.22 0.05 0.07 -1 -1 0.22 0.012185 0.0110656 147 136 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_016.v common 8.31 vpr 63.88 MiB -1 -1 0.16 20944 12 0.28 -1 -1 36120 -1 -1 33 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65408 32 32 301 333 1 230 97 17 17 289 -1 unnamed_device 25.4 MiB 0.37 1284 63.9 MiB 0.07 0.00 6.15144 -124.661 -6.15144 6.15144 0.74 0.00026993 0.000219403 0.015732 0.0131325 38 3421 31 6.55708e+06 397815 638502. 2209.35 4.86 0.173544 0.141987 23326 155178 -1 2818 15 1388 4502 218383 53481 0 0 218383 53481 4502 1902 0 0 14499 11821 0 0 21178 15691 0 0 4502 2432 0 0 83187 11409 0 0 90515 10226 0 0 4502 0 0 3114 6537 5820 41099 0 0 6.19064 6.19064 -140.04 -6.19064 0 0 851065. 2944.86 0.35 0.05 0.14 -1 -1 0.35 0.0166186 0.0151888 209 206 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_017.v common 6.94 vpr 63.70 MiB -1 -1 0.17 21080 14 0.24 -1 -1 35960 -1 -1 29 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65232 32 32 277 309 1 217 93 17 17 289 -1 unnamed_device 25.1 MiB 0.41 1504 63.7 MiB 0.05 0.00 6.10764 -131.576 -6.10764 6.10764 0.77 0.00026662 0.000219881 0.0129686 0.010873 38 3458 18 6.55708e+06 349595 638502. 2209.35 3.45 0.111752 0.0965215 23326 155178 -1 2850 16 1192 3414 168672 39209 0 0 168672 39209 3414 1566 0 0 11147 9146 0 0 15917 12042 0 0 3414 1908 0 0 67074 7404 0 0 67706 7143 0 0 3414 0 0 2222 3782 3806 26944 0 0 6.63024 6.63024 -152.004 -6.63024 0 0 851065. 2944.86 0.28 0.05 0.10 -1 -1 0.28 0.0150087 0.0136425 184 182 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_018.v common 4.48 vpr 63.34 MiB -1 -1 0.15 20780 12 0.15 -1 -1 35896 -1 -1 23 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64856 32 32 227 259 1 178 87 17 17 289 -1 unnamed_device 24.9 MiB 0.32 1142 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11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65104 32 32 287 319 1 210 89 17 17 289 -1 unnamed_device 25.2 MiB 0.30 1415 63.6 MiB 0.06 0.00 6.6419 -132.854 -6.6419 6.6419 0.74 0.000225838 0.000186446 0.0159964 0.0132464 30 3860 40 6.55708e+06 301375 526063. 1820.29 1.99 0.0782975 0.067682 21886 126133 -1 3033 18 1408 4246 209633 49596 0 0 209633 49596 4246 2037 0 0 13650 11393 0 0 19284 14524 0 0 4246 2458 0 0 83433 9731 0 0 84774 9453 0 0 4246 0 0 2838 4767 4862 32623 0 0 6.9633 6.9633 -152.102 -6.9633 0 0 666494. 2306.21 0.30 0.12 0.08 -1 -1 0.30 0.0294893 0.0278782 193 192 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_025.v common 5.07 vpr 62.43 MiB -1 -1 0.11 20356 8 0.08 -1 -1 35456 -1 -1 16 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 63932 32 32 154 186 1 120 80 17 17 289 -1 unnamed_device 23.9 MiB 0.13 766 62.4 MiB 0.03 0.00 3.37088 -79.3912 -3.37088 3.37088 0.86 0.000121051 9.9959e-05 0.00587401 0.00494641 26 1807 27 6.55708e+06 192880 477104. 1650.88 2.19 0.0547554 0.0473167 21022 109990 -1 1529 16 569 1220 68823 16787 0 0 68823 16787 1220 758 0 0 4145 3224 0 0 6556 4827 0 0 1220 835 0 0 28864 3458 0 0 26818 3685 0 0 1220 0 0 651 573 846 5668 0 0 3.73148 3.73148 -94.3796 -3.73148 0 0 585099. 2024.56 0.22 0.02 0.07 -1 -1 0.22 0.00721403 0.00655178 77 59 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_026.v common 6.52 vpr 63.45 MiB -1 -1 0.14 20796 15 0.23 -1 -1 35948 -1 -1 28 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64976 32 32 254 286 1 199 92 17 17 289 -1 unnamed_device 25.0 MiB 0.31 1345 63.5 MiB 0.03 0.00 6.9593 -136.429 -6.9593 6.9593 0.75 0.000217443 0.000182199 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success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64924 28 32 227 259 1 175 88 17 17 289 -1 unnamed_device 24.9 MiB 0.40 1033 63.4 MiB 0.05 0.00 5.50098 -107.86 -5.50098 5.50098 0.91 0.00017606 0.000144233 0.0130335 0.0108765 26 2936 47 6.55708e+06 337540 477104. 1650.88 4.78 0.129553 0.113996 21022 109990 -1 2552 26 1337 3683 302300 91662 0 0 302300 91662 3683 2059 0 0 13149 10423 0 0 21042 15823 0 0 3683 2367 0 0 130862 31225 0 0 129881 29765 0 0 3683 0 0 2346 3856 4294 26007 0 0 5.59926 5.59926 -127.764 -5.59926 0 0 585099. 2024.56 0.20 0.07 0.07 -1 -1 0.20 0.0156338 0.0139582 150 140 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_032.v common 5.06 vpr 63.52 MiB -1 -1 0.14 20772 12 0.19 -1 -1 35584 -1 -1 26 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65044 32 32 274 306 1 206 90 17 17 289 -1 unnamed_device 25.0 MiB 0.23 1294 63.5 MiB 0.03 0.00 5.8417 -130.983 -5.8417 5.8417 0.77 0.000233827 0.000194309 0.00845596 0.0072381 26 3449 34 6.55708e+06 313430 477104. 1650.88 1.91 0.0620065 0.0541617 21022 109990 -1 2989 22 1669 4717 353314 106564 0 0 353314 106564 4717 2802 0 0 16658 13543 0 0 27015 19839 0 0 4717 3320 0 0 149998 33467 0 0 150209 33593 0 0 4717 0 0 3048 4792 4855 30892 0 0 6.5629 6.5629 -157.112 -6.5629 0 0 585099. 2024.56 0.20 0.08 0.07 -1 -1 0.20 0.0169658 0.0152923 181 179 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_033.v common 10.67 vpr 63.31 MiB -1 -1 0.14 20792 12 0.15 -1 -1 35920 -1 -1 23 31 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64828 31 32 237 269 1 179 86 17 17 289 -1 unnamed_device 24.9 MiB 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success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65400 31 32 293 325 1 224 92 17 17 289 -1 unnamed_device 25.4 MiB 0.28 1561 63.9 MiB 0.04 0.00 6.65922 -133.175 -6.65922 6.65922 0.87 0.000246411 0.000206241 0.00971385 0.00829084 28 4049 49 6.55708e+06 349595 500653. 1732.36 9.17 0.138249 0.120318 21310 115450 -1 3635 24 2028 6361 437574 118387 0 0 437574 118387 6361 3489 0 0 21059 17344 0 0 34249 24457 0 0 6361 4105 0 0 180841 35532 0 0 188703 33460 0 0 6361 0 0 4333 8119 8499 52250 0 0 7.61376 7.61376 -164.945 -7.61376 0 0 612192. 2118.31 0.22 0.09 0.07 -1 -1 0.22 0.020444 0.0183268 202 200 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_040.v common 10.78 vpr 63.57 MiB -1 -1 0.18 21160 13 0.26 -1 -1 36044 -1 -1 28 31 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65100 31 32 276 308 1 223 91 17 17 289 -1 unnamed_device 25.2 MiB 0.33 1425 63.6 MiB 0.07 0.00 6.4805 -134.563 -6.4805 6.4805 0.73 0.000228948 0.000191421 0.0177044 0.0148255 30 3959 50 6.55708e+06 337540 526063. 1820.29 7.45 0.174372 0.147523 21886 126133 -1 3017 21 1621 4548 226829 52863 0 0 226829 52863 4548 2195 0 0 14578 11958 0 0 21207 15922 0 0 4548 2630 0 0 90930 10038 0 0 91018 10120 0 0 4548 0 0 2927 4107 4491 30407 0 0 6.7601 6.7601 -153.087 -6.7601 0 0 666494. 2306.21 0.25 0.06 0.08 -1 -1 0.25 0.0176777 0.0159849 185 183 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_041.v common 7.31 vpr 63.40 MiB -1 -1 0.17 21284 13 0.25 -1 -1 36016 -1 -1 26 31 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64924 31 32 269 301 1 203 89 17 17 289 -1 unnamed_device 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0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65336 32 32 272 304 1 203 93 17 17 289 -1 unnamed_device 25.4 MiB 0.24 1366 63.8 MiB 0.04 0.00 6.22784 -133.731 -6.22784 6.22784 0.82 0.000235135 0.000197119 0.0103582 0.00878472 28 3653 38 6.55708e+06 349595 500653. 1732.36 1.73 0.0728742 0.0638075 21310 115450 -1 3089 16 1362 4038 247105 57179 0 0 247105 57179 4038 2158 0 0 14017 11412 0 0 21471 16249 0 0 4038 2543 0 0 100704 12559 0 0 102837 12258 0 0 4038 0 0 2676 4457 4700 30481 0 0 6.79164 6.79164 -155.506 -6.79164 0 0 612192. 2118.31 0.21 0.06 0.13 -1 -1 0.21 0.0155444 0.0141636 183 177 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_048.v common 6.90 vpr 63.82 MiB -1 -1 0.17 21268 13 0.21 -1 -1 35944 -1 -1 26 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65356 32 32 271 303 1 212 90 17 17 289 -1 unnamed_device 25.3 MiB 0.28 1383 63.8 MiB 0.07 0.01 6.01698 -132.591 -6.01698 6.01698 0.79 0.000291145 0.00025043 0.0166288 0.0154808 36 3225 19 6.55708e+06 313430 612192. 2118.31 3.62 0.125736 0.112461 22750 144809 -1 2798 15 1144 3365 182862 42387 0 0 182862 42387 3365 1566 0 0 11452 9381 0 0 17550 13022 0 0 3365 1835 0 0 73902 8255 0 0 73228 8328 0 0 3365 0 0 2221 3684 4456 29802 0 0 6.25938 6.25938 -148.408 -6.25938 0 0 782063. 2706.10 0.27 0.05 0.09 -1 -1 0.27 0.0149024 0.0136664 178 176 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_049.v common 7.34 vpr 63.61 MiB -1 -1 0.18 21012 12 0.24 -1 -1 36088 -1 -1 30 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65140 32 32 288 320 1 223 94 17 17 289 -1 unnamed_device 25.2 MiB 0.42 1478 63.6 MiB 0.06 0.00 6.02864 -133.293 -6.02864 6.02864 0.72 0.000261721 0.000211504 0.0160662 0.0134241 36 3579 27 6.55708e+06 361650 612192. 2118.31 3.67 0.118413 0.102074 22750 144809 -1 3094 31 1258 4405 447488 185476 0 0 447488 185476 4405 2111 0 0 14786 12048 0 0 25894 18118 0 0 4405 2487 0 0 204048 78464 0 0 193950 72248 0 0 4405 0 0 3147 6944 7235 48281 0 0 6.67144 6.67144 -151.312 -6.67144 0 0 782063. 2706.10 0.27 0.12 0.09 -1 -1 0.27 0.0251434 0.0226228 197 193 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_050.v common 6.40 vpr 63.86 MiB -1 -1 0.17 21156 13 0.30 -1 -1 35940 -1 -1 31 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65396 32 32 306 338 1 233 95 17 17 289 -1 unnamed_device 25.2 MiB 0.38 1547 63.9 MiB 0.05 0.00 6.46824 -137.216 -6.46824 6.46824 0.88 0.000248968 0.000206816 0.0128138 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success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64516 32 32 216 248 1 160 82 17 17 289 -1 unnamed_device 24.5 MiB 0.23 1043 63.0 MiB 0.04 0.00 5.08892 -106.669 -5.08892 5.08892 0.81 0.000173477 0.000144209 0.00949871 0.00800276 28 2694 21 6.55708e+06 216990 500653. 1732.36 4.28 0.0784055 0.0679007 21310 115450 -1 2476 22 1010 2692 207454 52185 0 0 207454 52185 2692 1487 0 0 9773 8059 0 0 15483 11830 0 0 2692 1733 0 0 89412 14821 0 0 87402 14255 0 0 2692 0 0 1682 2603 3007 18056 0 0 5.16992 5.16992 -128.954 -5.16992 0 0 612192. 2118.31 0.22 0.05 0.08 -1 -1 0.22 0.0135144 0.0122149 125 121 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_056.v common 6.70 vpr 63.49 MiB -1 -1 0.16 20880 13 0.20 -1 -1 36184 -1 -1 24 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65012 32 32 254 286 1 194 88 17 17 289 -1 unnamed_device 25.1 MiB 0.32 1283 63.5 MiB 0.06 0.00 6.14684 -133.05 -6.14684 6.14684 0.73 0.000220299 0.000176405 0.0135617 0.0113333 34 3320 43 6.55708e+06 289320 585099. 2024.56 3.34 0.153821 0.136874 22462 138074 -1 2768 17 1142 3312 214170 49388 0 0 214170 49388 3312 1701 0 0 11423 9400 0 0 18515 13539 0 0 3312 2026 0 0 88708 11454 0 0 88900 11268 0 0 3312 0 0 2170 3582 4110 25242 0 0 6.51204 6.51204 -154.079 -6.51204 0 0 742403. 2568.87 0.26 0.05 0.09 -1 -1 0.26 0.0141679 0.0129111 161 159 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_057.v common 10.74 vpr 64.31 MiB -1 -1 0.17 21880 14 0.43 -1 -1 36368 -1 -1 33 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65852 32 32 338 370 1 252 97 17 17 289 -1 unnamed_device 25.9 MiB 0.30 1645 64.3 MiB 0.05 0.00 7.13802 -146.534 -7.13802 7.13802 0.92 0.00029633 0.000235363 0.0124958 0.0105459 30 4456 22 6.55708e+06 397815 526063. 1820.29 6.86 0.163083 0.142742 21886 126133 -1 3543 17 1746 5589 265895 62369 0 0 265895 62369 5589 2462 0 0 17891 14546 0 0 25147 19004 0 0 5589 3025 0 0 105512 11879 0 0 106167 11453 0 0 5589 0 0 3843 6602 7070 47314 0 0 7.25822 7.25822 -163.848 -7.25822 0 0 666494. 2306.21 0.23 0.13 0.08 -1 -1 0.23 0.0213305 0.0195304 245 243 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_058.v common 5.11 vpr 63.72 MiB -1 -1 0.16 21268 13 0.27 -1 -1 36032 -1 -1 27 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65252 32 32 271 303 1 212 91 17 17 289 -1 unnamed_device 25.1 MiB 0.38 1483 63.7 MiB 0.06 0.00 6.4779 -143.013 -6.4779 6.4779 0.81 0.000221848 0.000184059 0.0130791 0.0111021 34 3594 33 6.55708e+06 325485 585099. 2024.56 1.83 0.099066 0.0864877 22462 138074 -1 3073 19 1271 3623 219127 49872 0 0 219127 49872 3623 1746 0 0 12719 10336 0 0 19791 14784 0 0 3623 2230 0 0 88942 10455 0 0 90429 10321 0 0 3623 0 0 2352 4046 4435 27812 0 0 6.9587 6.9587 -164.728 -6.9587 0 0 742403. 2568.87 0.25 0.05 0.09 -1 -1 0.25 0.016859 0.0152849 178 176 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_059.v common 3.95 vpr 63.28 MiB -1 -1 0.14 20684 11 0.16 -1 -1 35908 -1 -1 23 30 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64796 30 32 224 256 1 165 85 17 17 289 -1 unnamed_device 24.8 MiB 0.16 1056 63.3 MiB 0.06 0.00 5.73878 -119.706 -5.73878 5.73878 0.75 0.000177552 0.000146196 0.0158512 0.0134092 28 2775 25 6.55708e+06 277265 500653. 1732.36 1.15 0.066184 0.0589958 21310 115450 -1 2468 32 1073 3198 355253 152529 0 0 355253 152529 3198 1590 0 0 11098 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-180.174 -8.33801 0 0 666494. 2306.21 0.24 0.09 0.08 -1 -1 0.24 0.0258611 0.0233145 257 256 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_061.v common 5.25 vpr 63.79 MiB -1 -1 0.16 21292 13 0.32 -1 -1 36512 -1 -1 28 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65324 32 32 297 329 1 215 92 17 17 289 -1 unnamed_device 25.3 MiB 0.36 1341 63.8 MiB 0.09 0.00 6.89196 -139.203 -6.89196 6.89196 0.75 0.0002566 0.000203925 0.0232741 0.0192601 28 4254 36 6.55708e+06 337540 500653. 1732.36 1.75 0.0933527 0.0818296 21310 115450 -1 3343 18 1520 4419 286833 65708 0 0 286833 65708 4419 2495 0 0 15575 12642 0 0 24094 18147 0 0 4419 2937 0 0 117453 15152 0 0 120873 14335 0 0 4419 0 0 2899 6279 5999 37216 0 0 7.25256 7.25256 -164.774 -7.25256 0 0 612192. 2118.31 0.22 0.06 0.07 -1 -1 0.22 0.0174336 0.0158886 203 202 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_062.v common 6.51 vpr 63.12 MiB -1 -1 0.13 20344 11 0.12 -1 -1 35776 -1 -1 22 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64636 32 32 231 263 1 176 86 17 17 289 -1 unnamed_device 24.7 MiB 0.31 1079 63.1 MiB 0.05 0.00 5.16732 -114.648 -5.16732 5.16732 0.73 0.000181439 0.000150339 0.0126694 0.0103961 44 2347 16 6.55708e+06 265210 742403. 2568.87 2.88 0.0932366 0.0809539 24478 177802 -1 2067 13 800 2411 120049 28314 0 0 120049 28314 2411 999 0 0 8107 6627 0 0 11918 9027 0 0 2411 1266 0 0 48486 5084 0 0 46716 5311 0 0 2411 0 0 1611 2341 2729 18920 0 0 5.28752 5.28752 -127.038 -5.28752 0 0 937218. 3242.97 0.31 0.03 0.11 -1 -1 0.31 0.00999787 0.00919023 141 136 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_063.v common 5.11 vpr 64.10 MiB -1 -1 0.16 20808 12 0.30 -1 -1 36124 -1 -1 30 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65640 32 32 305 337 1 231 94 17 17 289 -1 unnamed_device 25.4 MiB 0.41 1510 64.1 MiB 0.06 0.00 6.1611 -129.511 -6.1611 6.1611 0.75 0.000271653 0.000229043 0.0158967 0.0135026 30 3914 37 6.55708e+06 361650 526063. 1820.29 1.50 0.090692 0.0777788 21886 126133 -1 3206 21 1475 4612 238152 54354 0 0 238152 54354 4612 2169 0 0 14976 12245 0 0 21383 16113 0 0 4612 2524 0 0 93109 11305 0 0 99460 9998 0 0 4612 0 0 3137 7668 6745 46272 0 0 6.7621 6.7621 -151.217 -6.7621 0 0 666494. 2306.21 0.38 0.13 0.08 -1 -1 0.38 0.0422902 0.040381 213 210 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_064.v common 6.26 vpr 63.52 MiB -1 -1 0.14 20676 12 0.19 -1 -1 35844 -1 -1 26 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65048 32 32 243 275 1 186 90 17 17 289 -1 unnamed_device 24.9 MiB 0.38 1168 63.5 MiB 0.05 0.00 6.06844 -127.107 -6.06844 6.06844 0.75 0.000196799 0.000163619 0.0122352 0.0102854 30 2966 18 6.55708e+06 313430 526063. 1820.29 3.00 0.114001 0.0997836 21886 126133 -1 2344 17 1073 3081 139599 34392 0 0 139599 34392 3081 1442 0 0 10062 8175 0 0 13761 10572 0 0 3081 1769 0 0 54547 6246 0 0 55067 6188 0 0 3081 0 0 2008 2646 2835 20272 0 0 6.26964 6.26964 -143.68 -6.26964 0 0 666494. 2306.21 0.24 0.04 0.08 -1 -1 0.24 0.0132598 0.0120735 153 148 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_065.v common 5.48 vpr 63.09 MiB -1 -1 0.14 20736 12 0.16 -1 -1 36280 -1 -1 21 30 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64600 30 32 228 260 1 161 83 17 17 289 -1 unnamed_device 24.7 MiB 0.18 980 63.1 MiB 0.05 0.00 5.82944 -117.747 -5.82944 5.82944 0.79 0.000177138 0.000145501 0.0134036 0.0112014 28 2546 17 6.55708e+06 253155 500653. 1732.36 2.44 0.0817925 0.0707109 21310 115450 -1 2298 17 1003 2998 179486 41993 0 0 179486 41993 2998 1615 0 0 10535 8722 0 0 16308 12277 0 0 2998 1962 0 0 73388 8897 0 0 73259 8520 0 0 2998 0 0 1995 3593 3652 24082 0 0 6.31284 6.31284 -135.97 -6.31284 0 0 612192. 2118.31 0.32 0.04 0.07 -1 -1 0.32 0.0121531 0.0110037 140 137 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_066.v common 7.19 vpr 63.62 MiB -1 -1 0.17 21112 12 0.27 -1 -1 35968 -1 -1 31 29 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65152 29 32 275 307 1 206 92 17 17 289 -1 unnamed_device 25.2 MiB 0.22 1347 63.6 MiB 0.04 0.00 5.58198 -108.434 -5.58198 5.58198 1.09 0.000275234 0.000225718 0.00994539 0.00842896 34 3720 40 6.55708e+06 373705 585099. 2024.56 3.50 0.131841 0.114603 22462 138074 -1 3102 17 1349 4380 268326 60818 0 0 268326 60818 4380 1963 0 0 15231 12792 0 0 24539 18164 0 0 4380 2394 0 0 109732 13022 0 0 110064 12483 0 0 4380 0 0 3031 7161 6512 43640 0 0 6.06278 6.06278 -127.467 -6.06278 0 0 742403. 2568.87 0.27 0.07 0.11 -1 -1 0.27 0.0188533 0.017319 191 186 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_067.v common 5.96 vpr 64.16 MiB -1 -1 0.16 21044 13 0.31 -1 -1 35952 -1 -1 33 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65704 32 32 330 362 1 256 97 17 17 289 -1 unnamed_device 25.6 MiB 0.53 1596 64.2 MiB 0.04 0.00 7.25056 -149.828 -7.25056 7.25056 0.72 0.000267013 0.000222029 0.0101514 0.00860811 36 3911 26 6.55708e+06 397815 612192. 2118.31 2.40 0.100696 0.0879353 22750 144809 -1 3482 16 1693 4708 261342 61550 0 0 261342 61550 4708 2404 0 0 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-150.205 -6.6831 0 0 666494. 2306.21 0.24 0.07 0.08 -1 -1 0.24 0.0198966 0.0178928 200 195 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_069.v common 6.22 vpr 63.29 MiB -1 -1 0.13 20768 12 0.15 -1 -1 36236 -1 -1 20 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64808 32 32 214 246 1 164 84 17 17 289 -1 unnamed_device 24.7 MiB 0.50 1135 63.3 MiB 0.06 0.00 5.60752 -119.408 -5.60752 5.60752 0.96 0.000175937 0.00014009 0.0132069 0.0111485 38 2360 35 6.55708e+06 241100 638502. 2209.35 2.65 0.0984056 0.0849676 23326 155178 -1 2108 15 773 2249 112107 25925 0 0 112107 25925 2249 1013 0 0 7290 5935 0 0 10509 7935 0 0 2249 1233 0 0 45387 4919 0 0 44423 4890 0 0 2249 0 0 1476 2012 2356 16189 0 0 5.70018 5.70018 -129.905 -5.70018 0 0 851065. 2944.86 0.27 0.03 0.10 -1 -1 0.27 0.0103482 0.00944388 126 119 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_070.v common 10.96 vpr 63.49 MiB -1 -1 0.15 21152 12 0.20 -1 -1 35724 -1 -1 24 31 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65016 31 32 244 276 1 182 87 17 17 289 -1 unnamed_device 24.9 MiB 0.26 1177 63.5 MiB 0.12 0.00 5.89878 -117.754 -5.89878 5.89878 0.82 0.000201606 0.000167996 0.0315715 0.0249236 28 3413 20 6.55708e+06 289320 500653. 1732.36 7.70 0.126317 0.109461 21310 115450 -1 2965 17 1261 3870 248044 55702 0 0 248044 55702 3870 2095 0 0 13111 10970 0 0 20704 15173 0 0 3870 2472 0 0 102234 12750 0 0 104255 12242 0 0 3870 0 0 2609 5141 5130 31448 0 0 6.38218 6.38218 -142.189 -6.38218 0 0 612192. 2118.31 0.23 0.06 0.08 -1 -1 0.23 0.0134314 0.0122168 154 151 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_071.v common 6.59 vpr 63.58 MiB -1 -1 0.16 21068 11 0.19 -1 -1 36160 -1 -1 30 30 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65104 30 32 276 308 1 210 92 17 17 289 -1 unnamed_device 25.0 MiB 0.13 1415 63.6 MiB 0.06 0.00 5.55244 -111.164 -5.55244 5.55244 0.90 0.000221711 0.000182919 0.0148733 0.0122552 36 3551 38 6.55708e+06 361650 612192. 2118.31 3.37 0.1046 0.0903357 22750 144809 -1 3033 15 1185 3909 240327 52116 0 0 240327 52116 3909 1816 0 0 13142 10586 0 0 20295 14994 0 0 3909 2316 0 0 98369 11302 0 0 100703 11102 0 0 3909 0 0 2724 6035 6673 40205 0 0 6.03324 6.03324 -130.897 -6.03324 0 0 782063. 2706.10 0.27 0.05 0.09 -1 -1 0.27 0.0141838 0.0129649 190 185 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_072.v common 4.22 vpr 63.45 MiB -1 -1 0.15 21000 11 0.19 -1 -1 35948 -1 -1 27 28 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64976 28 32 253 285 1 181 87 17 17 289 -1 unnamed_device 25.1 MiB 0.14 1110 63.5 MiB 0.05 0.00 5.44692 -100.796 -5.44692 5.44692 0.92 0.000206351 0.0001665 0.0139467 0.0117626 30 2623 18 6.55708e+06 325485 526063. 1820.29 0.95 0.0566031 0.0493521 21886 126133 -1 2280 18 1020 3554 175410 40919 0 0 175410 40919 3554 1442 0 0 11539 9406 0 0 16768 12694 0 0 3554 1767 0 0 69997 7908 0 0 69998 7702 0 0 3554 0 0 2534 5205 5130 36941 0 0 5.56712 5.56712 -114.298 -5.56712 0 0 666494. 2306.21 0.24 0.05 0.08 -1 -1 0.24 0.0148287 0.0135345 172 166 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_073.v common 6.37 vpr 63.23 MiB -1 -1 0.14 21008 13 0.21 -1 -1 36012 -1 -1 25 30 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64744 30 32 235 267 1 174 87 17 17 289 -1 unnamed_device 24.8 MiB 0.27 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common 5.29 vpr 63.69 MiB -1 -1 0.17 21340 13 0.32 -1 -1 35956 -1 -1 29 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65216 32 32 296 328 1 221 93 17 17 289 -1 unnamed_device 25.2 MiB 0.27 1422 63.7 MiB 0.04 0.00 6.76916 -133.677 -6.76916 6.76916 0.73 0.000239851 0.000199199 0.00975546 0.00829298 34 3957 41 6.55708e+06 349595 585099. 2024.56 1.86 0.0843218 0.0733488 22462 138074 -1 3164 22 1449 4555 255784 59489 0 0 255784 59489 4555 2059 0 0 15750 12817 0 0 24951 18281 0 0 4555 2584 0 0 102962 11767 0 0 103011 11981 0 0 4555 0 0 3106 5369 5911 38393 0 0 7.21076 7.21076 -153.757 -7.21076 0 0 742403. 2568.87 0.32 0.07 0.09 -1 -1 0.32 0.0198045 0.0178974 205 201 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_079.v common 4.34 vpr 63.32 MiB -1 -1 0.15 20752 13 0.19 -1 -1 36260 -1 -1 24 30 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64840 30 32 234 266 1 186 86 17 17 289 -1 unnamed_device 24.8 MiB 0.45 1247 63.3 MiB 0.04 0.00 6.22784 -128.097 -6.22784 6.22784 0.79 0.000183092 0.000151224 0.0101336 0.00855248 28 3166 19 6.55708e+06 289320 500653. 1732.36 1.15 0.0515198 0.04499 21310 115450 -1 2734 18 1119 2939 175351 41044 0 0 175351 41044 2939 1643 0 0 10372 8433 0 0 16028 12208 0 0 2939 1914 0 0 72599 8292 0 0 70474 8554 0 0 2939 0 0 1820 2678 3251 19954 0 0 6.57618 6.57618 -147.311 -6.57618 0 0 612192. 2118.31 0.22 0.04 0.07 -1 -1 0.22 0.0128828 0.0116659 147 143 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_080.v common 7.28 vpr 63.96 MiB -1 -1 0.17 21656 13 0.42 -1 -1 35996 -1 -1 32 30 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65492 30 32 291 323 1 232 94 17 17 289 -1 unnamed_device 25.4 MiB 0.31 1415 64.0 MiB 0.04 0.00 6.73256 -132.364 -6.73256 6.73256 1.11 0.00025282 0.000212573 0.00984499 0.00837697 38 3313 26 6.55708e+06 385760 638502. 2209.35 3.42 0.121742 0.105825 23326 155178 -1 2841 17 1375 3895 181233 43375 0 0 181233 43375 3895 1728 0 0 12485 10275 0 0 17850 13418 0 0 3895 2164 0 0 72415 7785 0 0 70693 8005 0 0 3895 0 0 2520 3587 4145 27333 0 0 6.85276 6.85276 -150.315 -6.85276 0 0 851065. 2944.86 0.28 0.05 0.13 -1 -1 0.28 0.0167447 0.0152968 203 200 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_081.v common 11.58 vpr 63.57 MiB -1 -1 0.18 21048 14 0.30 -1 -1 36256 -1 -1 27 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65092 32 32 274 306 1 210 91 17 17 289 -1 unnamed_device 25.2 MiB 0.44 1358 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fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_086.v common 8.23 vpr 63.31 MiB -1 -1 0.12 21004 13 0.15 -1 -1 36092 -1 -1 24 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64828 32 32 222 254 1 180 88 17 17 289 -1 unnamed_device 24.9 MiB 0.29 1208 63.3 MiB 0.05 0.00 5.77918 -133.225 -5.77918 5.77918 0.80 0.000177806 0.000146954 0.011426 0.00953205 28 3240 40 6.55708e+06 289320 500653. 1732.36 5.22 0.102003 0.0885969 21310 115450 -1 2643 19 1112 2924 189467 43344 0 0 189467 43344 2924 1683 0 0 10402 8611 0 0 16063 12209 0 0 2924 1998 0 0 78124 9744 0 0 79030 9099 0 0 2924 0 0 1812 2680 2963 18715 0 0 6.45858 6.45858 -161.378 -6.45858 0 0 612192. 2118.31 0.22 0.06 0.07 -1 -1 0.22 0.0204318 0.0191479 138 127 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_087.v common 8.78 vpr 63.58 MiB -1 -1 0.16 21104 14 0.23 -1 -1 36116 -1 -1 28 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65108 32 32 267 299 1 205 92 17 17 289 -1 unnamed_device 25.0 MiB 0.59 1338 63.6 MiB 0.06 0.00 6.6771 -139.917 -6.6771 6.6771 0.75 0.000224775 0.000177446 0.0120468 0.0101831 36 3625 41 6.55708e+06 337540 612192. 2118.31 5.30 0.155435 0.130918 22750 144809 -1 2867 18 1384 4271 234622 54973 0 0 234622 54973 4271 2032 0 0 14233 11779 0 0 22848 16651 0 0 4271 2497 0 0 94891 11023 0 0 94108 10991 0 0 4271 0 0 2887 4738 5699 34975 0 0 6.9593 6.9593 -155.917 -6.9593 0 0 782063. 2706.10 0.27 0.06 0.09 -1 -1 0.27 0.0160575 0.0146482 179 172 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_088.v common 6.11 vpr 64.34 MiB -1 -1 0.16 21732 15 0.41 -1 -1 36000 -1 -1 33 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65888 32 32 334 366 1 263 97 17 17 289 -1 unnamed_device 25.8 MiB 0.26 1709 64.3 MiB 0.04 0.00 7.46001 -156.735 -7.46001 7.46001 0.85 0.000323365 0.000267116 0.0115729 0.00998745 30 4803 25 6.55708e+06 397815 526063. 1820.29 2.59 0.0742298 0.0652236 21886 126133 -1 3726 16 1727 5171 270315 61770 0 0 270315 61770 5171 2559 0 0 16539 13637 0 0 23394 17555 0 0 5171 3036 0 0 107830 12830 0 0 112210 12153 0 0 5171 0 0 3444 6249 6246 40440 0 0 7.70041 7.70041 -177.392 -7.70041 0 0 666494. 2306.21 0.23 0.06 0.08 -1 -1 0.23 0.018827 0.0172291 241 239 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_089.v common 5.53 vpr 63.10 MiB -1 -1 0.14 21128 11 0.15 -1 -1 35812 -1 -1 22 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64616 32 32 220 252 1 157 86 17 17 289 -1 unnamed_device 24.7 MiB 0.37 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6.55708e+06 313430 612192. 2118.31 2.06 0.0872514 0.0758278 22750 144809 -1 2474 13 1139 3168 177094 42481 0 0 177094 42481 3168 1647 0 0 10796 8886 0 0 16907 12535 0 0 3168 2006 0 0 71207 8915 0 0 71848 8492 0 0 3168 0 0 2029 3122 3484 22335 0 0 6.45798 6.45798 -142.396 -6.45798 0 0 782063. 2706.10 0.26 0.04 0.09 -1 -1 0.26 0.0117648 0.0108236 156 151 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_091.v common 6.21 vpr 63.84 MiB -1 -1 0.17 21024 12 0.30 -1 -1 35972 -1 -1 32 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65368 32 32 300 332 1 237 96 17 17 289 -1 unnamed_device 25.2 MiB 0.30 1469 63.8 MiB 0.06 0.00 5.9201 -131.593 -5.9201 5.9201 0.74 0.000252231 0.000210015 0.014511 0.0122786 36 3566 19 6.55708e+06 385760 612192. 2118.31 2.98 0.134754 0.117122 22750 144809 -1 3173 18 1479 4453 239924 55960 0 0 239924 55960 4453 2025 0 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-152.739 -6.6027 0 0 742403. 2568.87 0.26 0.06 0.09 -1 -1 0.26 0.0155901 0.0141789 181 176 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_093.v common 6.45 vpr 64.25 MiB -1 -1 0.16 21596 14 0.44 -1 -1 36256 -1 -1 31 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65788 32 32 327 359 1 242 95 17 17 289 -1 unnamed_device 25.6 MiB 0.48 1671 64.2 MiB 0.07 0.00 7.09622 -146.756 -7.09622 7.09622 0.80 0.000267549 0.000220796 0.0180785 0.0150903 38 4060 26 6.55708e+06 373705 638502. 2209.35 2.42 0.113826 0.0988633 23326 155178 -1 3585 18 1644 5404 291277 65478 0 0 291277 65478 5404 2274 0 0 17240 14424 0 0 25601 18737 0 0 5404 3015 0 0 119133 13364 0 0 118495 13664 0 0 5404 0 0 3760 5819 6553 43908 0 0 7.57702 7.57702 -168.842 -7.57702 0 0 851065. 2944.86 0.30 0.16 0.10 -1 -1 0.30 0.0264033 0.0243354 234 232 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_094.v common 6.08 vpr 63.41 MiB -1 -1 0.15 21156 12 0.22 -1 -1 36012 -1 -1 25 30 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64928 30 32 246 278 1 191 87 17 17 289 -1 unnamed_device 24.9 MiB 0.40 1284 63.4 MiB 0.07 0.00 6.01898 -117.232 -6.01898 6.01898 0.74 0.000205803 0.00017058 0.0178813 0.0149815 30 3219 44 6.55708e+06 301375 526063. 1820.29 2.92 0.119187 0.103384 21886 126133 -1 2613 19 1118 3517 170629 39829 0 0 170629 39829 3517 1584 0 0 11207 9146 0 0 16068 11986 0 0 3517 1971 0 0 69099 7437 0 0 67221 7705 0 0 3517 0 0 2399 3779 3838 29125 0 0 6.15344 6.15344 -130.759 -6.15344 0 0 666494. 2306.21 0.22 0.04 0.08 -1 -1 0.22 0.0144646 0.0130804 160 155 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_095.v common 9.12 vpr 63.11 MiB -1 -1 0.14 20600 11 0.18 -1 -1 35528 -1 -1 26 27 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64628 27 32 219 251 1 163 85 17 17 289 -1 unnamed_device 24.7 MiB 0.27 900 63.1 MiB 0.03 0.00 5.51064 -100.013 -5.51064 5.51064 0.75 0.000182391 0.000150255 0.00775877 0.00657195 26 3055 32 6.55708e+06 313430 477104. 1650.88 5.97 0.101395 0.0888747 21022 109990 -1 2444 18 1145 3511 221980 53075 0 0 221980 53075 3511 2013 0 0 12244 10143 0 0 19553 14123 0 0 3511 2386 0 0 90715 12508 0 0 92446 11902 0 0 3511 0 0 2366 4919 4806 28664 0 0 6.23384 6.23384 -126.881 -6.23384 0 0 585099. 2024.56 0.21 0.05 0.07 -1 -1 0.21 0.0129754 0.0117218 140 134 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_096.v common 12.58 vpr 64.32 MiB -1 -1 0.20 21488 13 0.43 -1 -1 36072 -1 -1 40 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65864 32 32 380 412 1 282 104 17 17 289 -1 unnamed_device 26.2 MiB 0.41 1950 64.3 MiB 0.16 0.00 6.8013 -139.508 -6.8013 6.8013 0.74 0.000315913 0.000254533 0.0282422 0.0235846 34 5513 40 6.55708e+06 482200 585099. 2024.56 8.69 0.20551 0.177312 22462 138074 -1 4309 21 2029 6332 380678 86989 0 0 380678 86989 6332 3046 0 0 21810 17723 0 0 33762 25215 0 0 6332 3653 0 0 154610 18968 0 0 157832 18384 0 0 6332 0 0 4303 9189 9010 58038 0 0 7.18944 7.18944 -163.758 -7.18944 0 0 742403. 2568.87 0.26 0.09 0.09 -1 -1 0.26 0.0261152 0.0237112 286 285 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_097.v common 8.63 vpr 63.54 MiB -1 -1 0.17 20804 14 0.24 -1 -1 35988 -1 -1 28 31 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65060 31 32 277 309 1 210 91 17 17 289 -1 unnamed_device 24.9 MiB 0.19 1332 63.5 MiB 0.05 0.00 6.88996 -136.389 -6.88996 6.88996 0.76 0.000255081 0.00021515 0.0118117 0.0100796 28 3813 40 6.55708e+06 337540 500653. 1732.36 5.28 0.11062 0.0960745 21310 115450 -1 3268 19 1406 3805 229560 53204 0 0 229560 53204 3805 2045 0 0 13218 10693 0 0 20071 15091 0 0 3805 2464 0 0 95748 11259 0 0 92913 11652 0 0 3805 0 0 2399 4226 4368 27300 0 0 7.2409 7.2409 -160.42 -7.2409 0 0 612192. 2118.31 0.25 0.06 0.07 -1 -1 0.25 0.0228965 0.0213826 188 184 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_098.v common 4.19 vpr 63.35 MiB -1 -1 0.14 20976 12 0.15 -1 -1 35932 -1 -1 27 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64868 32 32 229 261 1 178 91 17 17 289 -1 unnamed_device 24.8 MiB 0.30 1244 63.3 MiB 0.04 0.00 5.95024 -133.449 -5.95024 5.95024 0.77 0.000184759 0.000152237 0.00943684 0.00799662 28 3061 37 6.55708e+06 325485 500653. 1732.36 1.17 0.0600713 0.0524664 21310 115450 -1 2665 16 1017 2860 203513 48266 0 0 203513 48266 2860 1521 0 0 9824 7842 0 0 14939 11262 0 0 2860 1796 0 0 86748 13182 0 0 86282 12663 0 0 2860 0 0 1843 3329 3090 20928 0 0 6.07044 6.07044 -146.716 -6.07044 0 0 612192. 2118.31 0.22 0.05 0.07 -1 -1 0.22 0.0124664 0.0113842 145 134 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_099.v common 5.59 vpr 63.68 MiB -1 -1 0.16 21268 13 0.29 -1 -1 36036 -1 -1 26 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65208 32 32 263 295 1 201 90 17 17 289 -1 unnamed_device 25.2 MiB 0.58 1287 63.7 MiB 0.04 0.00 6.3623 -131.885 -6.3623 6.3623 0.74 0.000220528 0.000183516 0.0104958 0.00889471 28 3871 45 6.55708e+06 313430 500653. 1732.36 1.85 0.0736988 0.06374 21310 115450 -1 2953 20 1420 4197 247051 56664 0 0 247051 56664 4197 2231 0 0 14378 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fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_102.v common 5.21 vpr 64.03 MiB -1 -1 0.17 21332 15 0.32 -1 -1 35700 -1 -1 29 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65568 32 32 296 328 1 223 93 17 17 289 -1 unnamed_device 25.3 MiB 0.47 1573 64.0 MiB 0.05 0.00 7.25622 -151.279 -7.25622 7.25622 0.82 0.000251364 0.000202219 0.0120329 0.0101589 30 3820 25 6.55708e+06 349595 526063. 1820.29 1.39 0.0825737 0.0734867 21886 126133 -1 3141 18 1374 4261 210021 48715 0 0 210021 48715 4261 1868 0 0 13733 11230 0 0 19382 14699 0 0 4261 2236 0 0 85400 9212 0 0 82984 9470 0 0 4261 0 0 2887 5200 5523 36621 0 0 7.40596 7.40596 -169.898 -7.40596 0 0 666494. 2306.21 0.23 0.05 0.14 -1 -1 0.23 0.0179458 0.0163814 202 201 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_103.v common 6.18 vpr 63.76 MiB -1 -1 0.18 21520 13 0.32 -1 -1 36152 -1 -1 30 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65292 32 32 285 317 1 224 94 17 17 289 -1 unnamed_device 25.3 MiB 0.42 1476 63.8 MiB 0.05 0.00 6.6765 -142.241 -6.6765 6.6765 0.72 0.000231989 0.000191993 0.0134737 0.0112553 28 4515 46 6.55708e+06 361650 500653. 1732.36 2.51 0.079209 0.0689689 21310 115450 -1 3523 68 1680 5212 1126482 602435 0 0 1126482 602435 5212 2706 0 0 18110 14931 0 0 34479 23747 0 0 5212 3133 0 0 541142 297634 0 0 522327 260284 0 0 5212 0 0 3532 8213 8481 49156 0 0 7.3193 7.3193 -167.349 -7.3193 0 0 612192. 2118.31 0.24 0.33 0.07 -1 -1 0.24 0.0510493 0.0450852 194 190 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_104.v common 8.09 vpr 63.25 MiB -1 -1 0.15 20948 12 0.19 -1 -1 35780 -1 -1 29 29 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64768 29 32 239 271 1 189 90 17 17 289 -1 unnamed_device 24.7 MiB 0.44 1204 63.2 MiB 0.05 0.00 6.0801 -125.534 -6.0801 6.0801 0.85 0.00020199 0.000169429 0.0110521 0.0093602 28 3315 32 6.55708e+06 349595 500653. 1732.36 4.75 0.0918791 0.0792959 21310 115450 -1 2742 21 1411 3824 219340 52670 0 0 219340 52670 3824 2138 0 0 13405 11244 0 0 20853 15805 0 0 3824 2543 0 0 88428 10535 0 0 89006 10405 0 0 3824 0 0 2413 3284 3649 23710 0 0 6.3623 6.3623 -145.817 -6.3623 0 0 612192. 2118.31 0.22 0.05 0.08 -1 -1 0.22 0.0154317 0.0139175 157 150 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_105.v common 6.27 vpr 63.17 MiB -1 -1 0.15 21044 11 0.14 -1 -1 35864 -1 -1 21 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64684 32 32 235 267 1 176 85 17 17 289 -1 unnamed_device 24.8 MiB 0.20 952 63.2 MiB 0.07 0.00 5.54018 -111.263 -5.54018 5.54018 0.85 0.000195254 0.000156722 0.0158612 0.0131513 36 2759 36 6.55708e+06 253155 612192. 2118.31 3.15 0.101109 0.0872259 22750 144809 -1 2151 21 1100 2854 172028 44552 0 0 172028 44552 2854 1521 0 0 9921 7995 0 0 15001 11356 0 0 2854 1847 0 0 66891 11480 0 0 74507 10353 0 0 2854 0 0 1754 2776 2575 18109 0 0 6.10198 6.10198 -131.403 -6.10198 0 0 782063. 2706.10 0.27 0.05 0.09 -1 -1 0.27 0.0131285 0.0118065 145 140 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_106.v common 5.92 vpr 63.81 MiB -1 -1 0.15 20824 13 0.31 -1 -1 35964 -1 -1 29 31 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65340 31 32 294 326 1 226 92 17 17 289 -1 unnamed_device 25.3 MiB 0.46 1439 63.8 MiB 0.07 0.00 6.4387 -131.153 -6.4387 6.4387 0.86 0.000240842 0.000200154 0.018264 0.0153441 38 3664 21 6.55708e+06 349595 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VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65044 32 32 288 320 1 216 90 17 17 289 -1 unnamed_device 24.9 MiB 0.28 1459 63.5 MiB 0.06 0.00 5.87384 -126.375 -5.87384 5.87384 0.72 0.000229656 0.000191197 0.0148504 0.0124767 34 3625 50 6.55708e+06 313430 585099. 2024.56 2.58 0.122405 0.108294 22462 138074 -1 3145 25 1532 5098 618008 252593 0 0 618008 252593 5098 2418 0 0 17952 14870 0 0 31473 22048 0 0 5098 2904 0 0 281998 109313 0 0 276389 101040 0 0 5098 0 0 3566 8613 9326 55949 0 0 6.30518 6.30518 -148.763 -6.30518 0 0 742403. 2568.87 0.41 0.29 0.12 -1 -1 0.41 0.0213635 0.0193 195 193 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_112.v common 6.08 vpr 64.00 MiB -1 -1 0.18 21380 13 0.27 -1 -1 36352 -1 -1 29 31 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65540 31 32 282 314 1 222 92 17 17 289 -1 unnamed_device 25.5 MiB 0.77 1296 64.0 MiB 0.05 0.00 6.3205 -129.242 -6.3205 6.3205 0.75 0.000247167 0.000206412 0.0134871 0.0113935 36 3341 21 6.55708e+06 349595 612192. 2118.31 2.17 0.0905766 0.0785147 22750 144809 -1 2828 16 1340 4167 214246 51277 0 0 214246 51277 4167 1947 0 0 14181 11650 0 0 21355 16103 0 0 4167 2390 0 0 82435 9957 0 0 87941 9230 0 0 4167 0 0 2827 5452 5832 37708 0 0 6.94904 6.94904 -146.048 -6.94904 0 0 782063. 2706.10 0.26 0.05 0.09 -1 -1 0.26 0.0160684 0.0146233 193 189 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_113.v common 8.00 vpr 63.13 MiB -1 -1 0.16 20700 11 0.18 -1 -1 35820 -1 -1 25 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64648 32 32 233 265 1 183 89 17 17 289 -1 unnamed_device 24.7 MiB 0.35 1116 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0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65208 32 32 282 314 1 218 89 17 17 289 -1 unnamed_device 25.3 MiB 0.42 1324 63.7 MiB 0.08 0.00 6.6373 -131.168 -6.6373 6.6373 0.99 0.000230069 0.000190605 0.0221043 0.0188554 30 3872 41 6.55708e+06 301375 526063. 1820.29 2.00 0.103751 0.0912041 21886 126133 -1 2840 18 1353 4144 194474 46892 0 0 194474 46892 4144 1831 0 0 13368 11011 0 0 19007 14332 0 0 4144 2199 0 0 77679 8666 0 0 76132 8853 0 0 4144 0 0 2791 5628 5222 37333 0 0 6.7575 6.7575 -149.194 -6.7575 0 0 666494. 2306.21 0.26 0.06 0.08 -1 -1 0.26 0.0183729 0.0168197 189 187 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_120.v common 4.98 vpr 63.47 MiB -1 -1 0.16 21116 13 0.18 -1 -1 36128 -1 -1 26 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64992 32 32 238 270 1 186 90 17 17 289 -1 unnamed_device 24.9 MiB 0.31 1225 63.5 MiB 0.05 0.00 6.2003 -133.674 -6.2003 6.2003 0.95 0.000187185 0.000155247 0.0125624 0.0105499 28 3068 31 6.55708e+06 313430 500653. 1732.36 1.51 0.0843612 0.0763859 21310 115450 -1 2607 16 1084 2919 162448 38234 0 0 162448 38234 2919 1535 0 0 10065 7948 0 0 15267 11448 0 0 2919 1822 0 0 66042 7746 0 0 65236 7735 0 0 2919 0 0 1835 2561 2754 18941 0 0 6.5217 6.5217 -156.658 -6.5217 0 0 612192. 2118.31 0.26 0.05 0.08 -1 -1 0.26 0.0129529 0.0118681 151 143 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_121.v common 5.43 vpr 63.72 MiB -1 -1 0.17 21012 12 0.19 -1 -1 36488 -1 -1 26 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65252 32 32 269 301 1 199 90 17 17 289 -1 unnamed_device 25.2 MiB 0.24 1321 63.7 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fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_126.v common 5.35 vpr 62.88 MiB -1 -1 0.14 20528 9 0.12 -1 -1 35912 -1 -1 22 25 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64392 25 32 183 215 1 140 79 17 17 289 -1 unnamed_device 24.5 MiB 0.16 872 62.9 MiB 0.04 0.00 4.52146 -85.4086 -4.52146 4.52146 0.85 0.000150454 0.000124768 0.00863314 0.00715583 28 2278 24 6.55708e+06 265210 500653. 1732.36 2.40 0.0673454 0.057772 21310 115450 -1 1992 14 801 2286 129893 30962 0 0 129893 30962 2286 1198 0 0 7890 6440 0 0 12142 9143 0 0 2286 1393 0 0 53230 6148 0 0 52059 6640 0 0 2286 0 0 1485 2286 2771 17126 0 0 4.76186 4.76186 -98.4897 -4.76186 0 0 612192. 2118.31 0.22 0.03 0.07 -1 -1 0.22 0.00891635 0.00815052 111 102 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_127.v common 7.76 vpr 63.80 MiB -1 -1 0.18 21124 12 0.26 -1 -1 35984 -1 -1 33 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65332 32 32 300 332 1 233 97 17 17 289 -1 unnamed_device 25.3 MiB 0.37 1505 63.8 MiB 0.13 0.00 6.23184 -132.341 -6.23184 6.23184 0.80 0.000332577 0.000276309 0.0134052 0.0116491 36 3877 29 6.55708e+06 397815 612192. 2118.31 4.11 0.148021 0.130039 22750 144809 -1 3257 20 1461 4297 285453 70560 0 0 285453 70560 4297 2088 0 0 15042 12430 0 0 23156 17760 0 0 4297 2633 0 0 117926 18080 0 0 120735 17569 0 0 4297 0 0 2836 4810 5207 32472 0 0 6.6439 6.6439 -154.349 -6.6439 0 0 782063. 2706.10 0.31 0.12 0.09 -1 -1 0.31 0.023023 0.021359 212 205 -1 -1 -1 -1 + fixed_k6_N8_gate_boost_0.2V_22nm.xml mult_128.v common 5.05 vpr 63.71 MiB -1 -1 0.18 21376 13 0.31 -1 -1 36368 -1 -1 30 31 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65244 31 32 290 322 1 226 93 17 17 289 -1 unnamed_device 25.2 MiB 0.31 1471 63.7 MiB 0.04 0.00 6.6791 -139.471 -6.6791 6.6791 0.79 0.000262568 0.000211692 0.00857009 0.00741597 36 3822 30 6.55708e+06 361650 612192. 2118.31 1.58 0.0777982 0.067899 22750 144809 -1 3296 17 1370 4369 241767 55556 0 0 241767 55556 4369 2155 0 0 14596 11860 0 0 22682 16769 0 0 4369 2578 0 0 96270 11201 0 0 99481 10993 0 0 4369 0 0 2999 5579 6233 39726 0 0 7.3193 7.3193 -160.988 -7.3193 0 0 782063. 2706.10 0.26 0.06 0.09 -1 -1 0.26 0.0180247 0.0165009 200 197 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_001.v common 5.39 vpr 63.84 MiB -1 -1 0.12 20836 1 0.02 -1 -1 33180 -1 -1 32 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65368 32 32 354 285 1 202 96 17 17 289 -1 unnamed_device 25.4 MiB 0.21 1200 63.8 MiB 0.12 0.00 4.42712 -134.27 -4.42712 4.42712 0.87 0.000170194 0.000139481 0.0219427 0.0192088 30 2396 22 6.64007e+06 401856 526063. 1820.29 2.40 0.0997693 0.0861582 22546 126617 -1 2102 19 1157 1856 103576 23894 0 0 103576 23894 1856 1281 0 0 6186 4824 0 0 7998 6395 0 0 1856 1371 0 0 44200 4829 0 0 41480 5194 0 0 1856 0 0 699 765 863 6381 0 0 3.94328 3.94328 -142.514 -3.94328 0 0 666494. 2306.21 0.25 0.03 0.08 -1 -1 0.25 0.0118 0.0106535 154 47 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_002.v common 4.01 vpr 63.97 MiB -1 -1 0.13 20876 1 0.02 -1 -1 33192 -1 -1 24 30 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65504 30 32 363 293 1 194 86 17 17 289 -1 unnamed_device 25.4 MiB 0.29 990 64.0 MiB 0.11 0.00 3.79642 -119.207 -3.79642 3.79642 0.95 0.000218872 0.000184044 0.0230217 0.0191556 32 2334 19 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fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_006.v common 5.61 vpr 63.93 MiB -1 -1 0.12 20744 1 0.01 -1 -1 33164 -1 -1 34 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65464 32 32 366 295 1 189 98 17 17 289 -1 unnamed_device 25.3 MiB 0.09 1007 63.9 MiB 0.08 0.00 2.80439 -99.9308 -2.80439 2.80439 0.75 0.000169535 0.000139244 0.0127264 0.0106422 32 2272 20 6.64007e+06 426972 554710. 1919.41 2.75 0.0741595 0.0629809 22834 132086 -1 2006 19 1175 1868 120584 27842 0 0 120584 27842 1868 1310 0 0 6772 5352 0 0 10283 7829 0 0 1868 1455 0 0 49831 6114 0 0 49962 5782 0 0 1868 0 0 693 775 915 6433 0 0 3.09937 3.09937 -114.673 -3.09937 0 0 701300. 2426.64 0.25 0.04 0.09 -1 -1 0.25 0.0124156 0.0111163 142 55 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_007.v common 4.60 vpr 63.16 MiB -1 -1 0.11 20376 1 0.01 -1 -1 33432 -1 -1 19 27 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64676 27 32 259 221 1 130 78 17 17 289 -1 unnamed_device 24.8 MiB 0.08 662 63.2 MiB 0.05 0.00 3.15021 -83.3249 -3.15021 3.15021 0.90 0.000125911 0.00010353 0.00920751 0.00768633 28 1533 22 6.64007e+06 238602 500653. 1732.36 1.89 0.0611481 0.0520616 21970 115934 -1 1439 16 749 1304 83320 20620 0 0 83320 20620 1304 965 0 0 4825 4029 0 0 6897 5668 0 0 1304 1042 0 0 35376 4326 0 0 33614 4590 0 0 1304 0 0 555 606 528 4355 0 0 2.93397 2.93397 -97.0919 -2.93397 0 0 612192. 2118.31 0.22 0.03 0.07 -1 -1 0.22 0.00816092 0.00736188 93 26 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_008.v common 5.54 vpr 63.54 MiB -1 -1 0.11 20448 1 0.01 -1 -1 33276 -1 -1 31 31 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65064 31 32 271 219 1 162 94 17 17 289 -1 unnamed_device 25.0 MiB 0.07 926 63.5 MiB 0.05 0.00 2.7039 -83.4236 -2.7039 2.7039 0.94 0.000136888 0.000113678 0.00837499 0.00705307 30 1977 19 6.64007e+06 389298 526063. 1820.29 2.23 0.0650219 0.055532 22546 126617 -1 1788 18 837 1547 91510 20518 0 0 91510 20518 1547 1049 0 0 5120 3960 0 0 6839 5418 0 0 1547 1127 0 0 37009 4772 0 0 39448 4192 0 0 1547 0 0 710 922 1006 7081 0 0 2.67777 2.67777 -94.9341 -2.67777 0 0 666494. 2306.21 0.41 0.03 0.13 -1 -1 0.41 0.00869509 0.00776919 115 -1 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_009.v common 3.88 vpr 63.54 MiB -1 -1 0.12 20936 1 0.01 -1 -1 33280 -1 -1 20 31 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65068 31 32 317 271 1 167 83 17 17 289 -1 unnamed_device 25.1 MiB 0.17 829 63.5 MiB 0.07 0.00 2.88585 -95.7089 -2.88585 2.88585 0.82 0.000146601 0.000120881 0.0104897 0.0088817 32 1997 18 6.64007e+06 251160 554710. 1919.41 1.00 0.0358941 0.0308308 22834 132086 -1 1763 19 1129 1643 111455 26792 0 0 111455 26792 1643 1374 0 0 5991 4942 0 0 9150 6912 0 0 1643 1435 0 0 47543 6004 0 0 45485 6125 0 0 1643 0 0 514 446 349 3980 0 0 3.29303 3.29303 -122.439 -3.29303 0 0 701300. 2426.64 0.25 0.03 0.09 -1 -1 0.25 0.0097304 0.00868103 111 60 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_010.v common 5.51 vpr 63.43 MiB -1 -1 0.11 20760 1 0.01 -1 -1 33200 -1 -1 17 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64948 32 32 298 248 1 156 81 17 17 289 -1 unnamed_device 24.8 MiB 0.14 843 63.4 MiB 0.06 0.00 3.13721 -105.548 -3.13721 3.13721 0.76 0.000151518 0.00012531 0.0118816 0.00991405 32 2031 22 6.64007e+06 213486 554710. 1919.41 2.64 0.0773186 0.0658806 22834 132086 -1 1745 21 1221 2004 136660 31011 0 0 136660 31011 2004 1447 0 0 7218 6003 0 0 11282 8314 0 0 2004 1576 0 0 57749 6764 0 0 56403 6907 0 0 2004 0 0 783 758 934 6683 0 0 2.88177 2.88177 -115.347 -2.88177 0 0 701300. 2426.64 0.25 0.04 0.08 -1 -1 0.25 0.0104885 0.00934613 112 31 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_011.v common 5.41 vpr 63.55 MiB -1 -1 0.11 20748 1 0.01 -1 -1 33140 -1 -1 17 30 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65072 30 32 303 262 1 139 79 17 17 289 -1 unnamed_device 25.1 MiB 0.10 799 63.5 MiB 0.06 0.00 3.46461 -96.3089 -3.46461 3.46461 0.74 0.00013538 0.000109278 0.0112602 0.00925193 32 1667 19 6.64007e+06 213486 554710. 1919.41 2.42 0.0569982 0.0481524 22834 132086 -1 1507 17 825 1304 86602 20001 0 0 86602 20001 1304 922 0 0 4711 3889 0 0 7220 5456 0 0 1304 1089 0 0 36641 4300 0 0 35422 4345 0 0 1304 0 0 479 309 526 3904 0 0 2.77276 2.77276 -100.351 -2.77276 0 0 701300. 2426.64 0.42 0.04 0.08 -1 -1 0.42 0.00890812 0.0079827 98 58 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_012.v common 5.49 vpr 63.33 MiB -1 -1 0.10 20684 1 0.01 -1 -1 33160 -1 -1 18 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64848 32 32 276 237 1 166 82 17 17 289 -1 unnamed_device 24.8 MiB 0.22 822 63.3 MiB 0.06 0.00 3.02301 -96.2485 -3.02301 3.02301 0.74 0.000131243 0.000106977 0.011645 0.00964256 28 2274 30 6.64007e+06 226044 500653. 1732.36 2.60 0.0707342 0.0600155 21970 115934 -1 1834 19 1124 1520 104465 26455 0 0 104465 26455 1520 1255 0 0 5533 4578 0 0 8237 6545 0 0 1520 1355 0 0 43869 6333 0 0 43786 6389 0 0 1520 0 0 396 454 474 3680 0 0 3.75457 3.75457 -117.09 -3.75457 0 0 612192. 2118.31 0.23 0.03 0.07 -1 -1 0.23 0.00929706 0.00832994 109 31 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_013.v common 5.45 vpr 63.84 MiB -1 -1 0.11 20768 1 0.01 -1 -1 33160 -1 -1 24 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65372 32 32 344 272 1 202 88 17 17 289 -1 unnamed_device 25.5 MiB 0.19 976 63.8 MiB 0.08 0.00 3.57727 -114.954 -3.57727 3.57727 0.82 0.000164138 0.000135686 0.0106483 0.00890803 28 2689 28 6.64007e+06 301392 500653. 1732.36 2.46 0.0775268 0.0664362 21970 115934 -1 2300 19 1530 2247 153149 37069 0 0 153149 37069 2247 1793 0 0 8004 6574 0 0 11828 9236 0 0 2247 1886 0 0 63015 8744 0 0 65808 8836 0 0 2247 0 0 717 801 645 5864 0 0 3.65043 3.65043 -135.226 -3.65043 0 0 612192. 2118.31 0.43 0.04 0.07 -1 -1 0.43 0.0112693 0.0100827 139 31 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_014.v common 5.28 vpr 63.71 MiB -1 -1 0.12 20612 1 0.01 -1 -1 33096 -1 -1 31 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65236 32 32 363 295 1 181 95 17 17 289 -1 unnamed_device 25.3 MiB 0.11 967 63.7 MiB 0.11 0.01 4.12607 -118.057 -4.12607 4.12607 0.76 0.000236588 0.000200303 0.0203018 0.0182084 32 2121 19 6.64007e+06 389298 554710. 1919.41 2.34 0.0927967 0.080973 22834 132086 -1 1907 19 1222 2003 130341 29250 0 0 130341 29250 2003 1392 0 0 6971 5628 0 0 10825 8006 0 0 2003 1546 0 0 56626 5986 0 0 51913 6692 0 0 2003 0 0 781 922 875 6677 0 0 3.86262 3.86262 -130.052 -3.86262 0 0 701300. 2426.64 0.25 0.04 0.08 -1 -1 0.25 0.0109064 0.00973753 134 58 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_015.v common 4.54 vpr 63.25 MiB -1 -1 0.10 20896 1 0.01 -1 -1 33236 -1 -1 21 29 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64768 29 32 248 215 1 137 82 17 17 289 -1 unnamed_device 24.9 MiB 0.08 702 63.2 MiB 0.04 0.00 2.68419 -77.7395 -2.68419 2.68419 0.75 0.000134477 0.000112947 0.00727984 0.00608666 28 1696 18 6.64007e+06 263718 500653. 1732.36 1.86 0.0525806 0.0445803 21970 115934 -1 1546 18 871 1447 99877 23184 0 0 99877 23184 1447 1090 0 0 5090 4045 0 0 7364 5823 0 0 1447 1188 0 0 42820 5470 0 0 41709 5568 0 0 1447 0 0 576 418 504 4287 0 0 2.67757 2.67757 -91.4334 -2.67757 0 0 612192. 2118.31 0.23 0.03 0.07 -1 -1 0.23 0.00786526 0.00704227 98 21 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_016.v common 5.54 vpr 63.87 MiB -1 -1 0.11 21052 1 0.01 -1 -1 33264 -1 -1 22 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65404 32 32 370 297 1 183 86 17 17 289 -1 unnamed_device 25.4 MiB 0.12 1051 63.9 MiB 0.05 0.00 3.1755 -102.949 -3.1755 3.1755 0.75 0.000167955 0.000137773 0.00892163 0.0075367 26 2849 23 6.64007e+06 276276 477104. 1650.88 2.55 0.0734025 0.0631209 21682 110474 -1 2361 21 1334 2406 164212 38127 0 0 164212 38127 2406 1898 0 0 8531 6978 0 0 13048 9951 0 0 2406 2033 0 0 69810 8426 0 0 68011 8841 0 0 2406 0 0 1072 1325 1419 9308 0 0 3.41577 3.41577 -125.953 -3.41577 0 0 585099. 2024.56 0.44 0.04 0.07 -1 -1 0.44 0.0132786 0.0118388 133 55 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_017.v common 5.70 vpr 63.75 MiB -1 -1 0.10 21224 1 0.01 -1 -1 33148 -1 -1 23 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65280 32 32 338 269 1 196 87 17 17 289 -1 unnamed_device 25.3 MiB 0.19 1191 63.8 MiB 0.08 0.00 3.51127 -116.95 -3.51127 3.51127 0.75 0.000169205 0.00014049 0.0135441 0.0113339 36 2360 22 6.64007e+06 288834 612192. 2118.31 2.82 0.0981254 0.084146 23410 145293 -1 2070 18 1177 1680 108056 24347 0 0 108056 24347 1680 1362 0 0 5913 4631 0 0 8200 6588 0 0 1680 1512 0 0 46612 5142 0 0 43971 5112 0 0 1680 0 0 503 417 544 4202 0 0 3.41523 3.41523 -128.89 -3.41523 0 0 782063. 2706.10 0.27 0.03 0.09 -1 -1 0.27 0.0106675 0.00956984 138 31 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_018.v common 3.65 vpr 63.57 MiB -1 -1 0.11 20504 1 0.02 -1 -1 33268 -1 -1 29 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65100 32 32 323 276 1 153 93 17 17 289 -1 unnamed_device 25.2 MiB 0.20 862 63.6 MiB 0.07 0.00 2.30864 -87.9994 -2.30864 2.30864 0.77 0.000156673 0.000128215 0.0116682 0.00962795 28 1950 21 6.64007e+06 364182 500653. 1732.36 0.64 0.0378669 0.0322119 21970 115934 -1 1758 15 891 1389 87384 20373 0 0 87384 20373 1389 943 0 0 4829 3755 0 0 6937 5397 0 0 1389 1065 0 0 36822 4612 0 0 36018 4601 0 0 1389 0 0 498 646 619 4866 0 0 2.15051 2.15051 -100.385 -2.15051 0 0 612192. 2118.31 0.47 0.03 0.07 -1 -1 0.47 0.00818274 0.00731908 110 62 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_019.v common 3.50 vpr 62.93 MiB -1 -1 0.09 20524 1 0.00 -1 -1 33060 -1 -1 15 30 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64444 30 32 222 206 1 117 77 17 17 289 -1 unnamed_device 24.5 MiB 0.04 696 62.9 MiB 0.05 0.00 1.89953 -66.1252 -1.89953 1.89953 0.78 0.000108978 8.9036e-05 0.00897651 0.00739005 32 1407 19 6.64007e+06 188370 554710. 1919.41 0.65 0.0267897 0.0226977 22834 132086 -1 1330 19 728 1051 82194 19349 0 0 82194 19349 1051 837 0 0 4083 3446 0 0 7104 5487 0 0 1051 906 0 0 34618 4447 0 0 34287 4226 0 0 1051 0 0 323 343 391 2890 0 0 2.19451 2.19451 -87.9297 -2.19451 0 0 701300. 2426.64 0.25 0.02 0.09 -1 -1 0.25 0.00695031 0.00618584 81 29 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_020.v common 7.09 vpr 63.69 MiB -1 -1 0.12 20796 1 0.01 -1 -1 33284 -1 -1 20 31 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65220 31 32 291 243 1 171 83 17 17 289 -1 unnamed_device 25.3 MiB 0.21 732 63.7 MiB 0.06 0.00 3.93687 -115.005 -3.93687 3.93687 0.78 0.000135915 0.000111083 0.0125358 0.0104179 28 2207 33 6.64007e+06 251160 500653. 1732.36 3.98 0.108026 0.093974 21970 115934 -1 1642 20 1209 1760 144738 45055 0 0 144738 45055 1760 1514 0 0 6393 5280 0 0 9388 7452 0 0 1760 1644 0 0 65671 14930 0 0 59766 14235 0 0 1760 0 0 551 614 516 4679 0 0 3.65663 3.65663 -130.26 -3.65663 0 0 612192. 2118.31 0.25 0.05 0.07 -1 -1 0.25 0.0110894 0.00926468 128 30 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_021.v common 3.68 vpr 63.56 MiB -1 -1 0.11 20580 1 0.01 -1 -1 33552 -1 -1 31 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65084 32 32 342 271 1 179 95 17 17 289 -1 unnamed_device 25.0 MiB 0.06 1026 63.6 MiB 0.06 0.00 3.49156 -112.285 -3.49156 3.49156 0.80 0.000174074 0.000143084 0.00966819 0.00813849 32 2289 21 6.64007e+06 389298 554710. 1919.41 0.74 0.0477456 0.0421492 22834 132086 -1 2086 22 1452 2293 177443 39048 0 0 177443 39048 2293 1792 0 0 8721 7032 0 0 13728 10390 0 0 2293 1958 0 0 74205 9218 0 0 76203 8658 0 0 2293 0 0 841 1190 1097 8137 0 0 3.57743 3.57743 -129.162 -3.57743 0 0 701300. 2426.64 0.29 0.05 0.09 -1 -1 0.29 0.0125982 0.0112274 135 31 -1 -1 -1 -1 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-1 -1 18 26 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64628 26 32 190 182 1 110 76 17 17 289 -1 unnamed_device 24.6 MiB 0.27 382 63.1 MiB 0.04 0.00 1.89953 -51.9576 -1.89953 1.89953 0.77 9.9819e-05 8.2115e-05 0.00764393 0.00631019 28 1234 31 6.64007e+06 226044 500653. 1732.36 0.73 0.0278034 0.0235916 21970 115934 -1 1012 21 680 966 77132 20457 0 0 77132 20457 966 778 0 0 3468 2801 0 0 5253 4107 0 0 966 842 0 0 33569 5834 0 0 32910 6095 0 0 966 0 0 286 323 329 2644 0 0 1.86811 1.86811 -67.5242 -1.86811 0 0 612192. 2118.31 0.22 0.02 0.07 -1 -1 0.22 0.00649699 0.0057391 77 21 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_024.v common 5.68 vpr 63.39 MiB -1 -1 0.10 20452 1 0.01 -1 -1 33140 -1 -1 21 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64908 32 32 285 227 1 165 85 17 17 289 -1 unnamed_device 24.7 MiB 0.04 891 63.4 MiB 0.04 0.00 4.09606 -104.083 -4.09606 4.09606 0.95 0.000162421 0.000135653 0.00620124 0.00533943 28 2244 37 6.64007e+06 263718 500653. 1732.36 2.61 0.129531 0.118672 21970 115934 -1 1916 21 1136 2087 143571 33860 0 0 143571 33860 2087 1601 0 0 7590 6179 0 0 11075 8845 0 0 2087 1698 0 0 58934 7784 0 0 61798 7753 0 0 2087 0 0 951 1112 1002 7876 0 0 3.79362 3.79362 -123.019 -3.79362 0 0 612192. 2118.31 0.25 0.07 0.09 -1 -1 0.25 0.0269925 0.00949506 118 -1 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_025.v common 4.35 vpr 62.89 MiB -1 -1 0.09 20224 1 0.01 -1 -1 33096 -1 -1 14 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64396 32 32 173 169 1 116 78 17 17 289 -1 unnamed_device 24.3 MiB 0.05 445 62.9 MiB 0.06 0.00 2.08773 -60.0534 -2.08773 2.08773 0.96 9.3388e-05 7.5257e-05 0.0254953 0.0221871 28 1274 35 6.64007e+06 175812 500653. 1732.36 0.70 0.0500956 0.0392999 21970 115934 -1 985 16 510 566 48315 14627 0 0 48315 14627 566 513 0 0 2264 1879 0 0 3069 2567 0 0 566 520 0 0 20718 4678 0 0 21132 4470 0 0 566 0 0 56 44 55 833 0 0 2.17251 2.17251 -72.6657 -2.17251 0 0 612192. 2118.31 0.36 0.02 0.13 -1 -1 0.36 0.00550222 0.00493942 79 -1 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_026.v common 3.97 vpr 63.70 MiB -1 -1 0.11 20512 1 0.01 -1 -1 33112 -1 -1 30 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65224 32 32 300 245 1 165 94 17 17 289 -1 unnamed_device 25.3 MiB 0.08 945 63.7 MiB 0.09 0.00 3.53527 -103.097 -3.53527 3.53527 0.99 0.000150738 0.000124104 0.0137625 0.0114466 28 2110 21 6.64007e+06 376740 500653. 1732.36 0.83 0.0426815 0.0364072 21970 115934 -1 1948 20 1127 1874 130467 29771 0 0 130467 29771 1874 1365 0 0 6767 5321 0 0 9574 7735 0 0 1874 1485 0 0 55314 7097 0 0 55064 6768 0 0 1874 0 0 747 965 906 6728 0 0 3.61323 3.61323 -119.568 -3.61323 0 0 612192. 2118.31 0.22 0.04 0.07 -1 -1 0.22 0.0106747 0.00955661 123 21 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_027.v common 5.48 vpr 63.66 MiB -1 -1 0.11 20444 1 0.01 -1 -1 33180 -1 -1 31 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65188 32 32 297 233 1 177 95 17 17 289 -1 unnamed_device 25.3 MiB 0.04 919 63.7 MiB 0.05 0.00 3.0905 -86.6383 -3.0905 3.0905 1.09 0.000158743 0.00013219 0.00672203 0.00570327 28 2057 19 6.64007e+06 389298 500653. 1732.36 2.43 0.0700509 0.0609599 21970 115934 -1 1814 22 1036 1891 109477 27911 0 0 109477 27911 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2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65104 32 32 253 210 1 154 83 17 17 289 -1 unnamed_device 25.1 MiB 0.04 895 63.6 MiB 0.04 0.00 3.19341 -98.0221 -3.19341 3.19341 0.79 0.000140595 0.0001167 0.00528102 0.00447542 30 1917 22 6.64007e+06 238602 526063. 1820.29 0.73 0.0295841 0.0255013 22546 126617 -1 1693 19 953 1607 93362 21666 0 0 93362 21666 1607 1128 0 0 5505 4381 0 0 7163 5840 0 0 1607 1278 0 0 40598 4333 0 0 36882 4706 0 0 1607 0 0 654 658 698 5325 0 0 2.72977 2.72977 -108.822 -2.72977 0 0 666494. 2306.21 0.24 0.03 0.08 -1 -1 0.24 0.00867247 0.00764017 110 -1 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_033.v common 3.60 vpr 63.48 MiB -1 -1 0.09 20472 1 0.02 -1 -1 33144 -1 -1 27 31 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65008 31 32 271 231 1 148 90 17 17 289 -1 unnamed_device 25.0 MiB 0.04 706 63.5 MiB 0.08 0.00 2.8301 -84.4669 -2.8301 2.8301 0.92 0.000141477 0.00011638 0.00778582 0.00659833 30 1740 23 6.64007e+06 339066 526063. 1820.29 0.73 0.0325732 0.0280339 22546 126617 -1 1435 19 721 1249 63004 15127 0 0 63004 15127 1249 799 0 0 3953 3111 0 0 5394 4110 0 0 1249 915 0 0 23602 3388 0 0 27557 2804 0 0 1249 0 0 528 715 546 4876 0 0 2.67557 2.67557 -94.839 -2.67557 0 0 666494. 2306.21 0.36 0.04 0.08 -1 -1 0.36 0.0159202 0.0149313 103 26 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_034.v common 3.88 vpr 63.41 MiB -1 -1 0.10 20552 1 0.01 -1 -1 33376 -1 -1 26 29 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64936 29 32 291 250 1 153 87 17 17 289 -1 unnamed_device 24.8 MiB 0.11 731 63.4 MiB 0.07 0.00 2.6377 -83.2904 -2.6377 2.6377 0.96 0.000136501 0.000111168 0.0127293 0.0105244 32 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-1 33304 -1 -1 29 31 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65404 31 32 377 302 1 233 92 17 17 289 -1 unnamed_device 25.7 MiB 0.31 1394 63.9 MiB 0.08 0.00 4.79918 -144.463 -4.79918 4.79918 0.75 0.000196128 0.00016424 0.012396 0.0104951 28 3385 25 6.64007e+06 364182 500653. 1732.36 0.82 0.0502141 0.0435378 21970 115934 -1 2786 20 1950 2815 201491 44478 0 0 201491 44478 2815 2442 0 0 9825 7580 0 0 14395 10941 0 0 2815 2604 0 0 87035 10443 0 0 84606 10468 0 0 2815 0 0 865 733 833 6976 0 0 4.84769 4.84769 -170.619 -4.84769 0 0 612192. 2118.31 0.21 0.05 0.07 -1 -1 0.21 0.0125189 0.0112422 172 60 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_040.v common 4.07 vpr 63.89 MiB -1 -1 0.12 20876 1 0.01 -1 -1 33316 -1 -1 27 31 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65428 31 32 383 305 1 209 90 17 17 289 -1 unnamed_device 25.3 MiB 0.37 975 63.9 MiB 0.10 0.00 4.11401 -119.791 -4.11401 4.11401 0.77 0.000190835 0.000160091 0.0168916 0.0141912 32 2772 25 6.64007e+06 339066 554710. 1919.41 0.77 0.0535262 0.0461307 22834 132086 -1 2228 19 1669 2486 173905 41325 0 0 173905 41325 2486 2017 0 0 9060 7338 0 0 13974 10477 0 0 2486 2137 0 0 71158 10397 0 0 74741 8959 0 0 2486 0 0 817 839 683 6667 0 0 4.67268 4.67268 -150.464 -4.67268 0 0 701300. 2426.64 0.25 0.04 0.09 -1 -1 0.25 0.0123637 0.0111066 164 60 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_041.v common 5.74 vpr 63.86 MiB -1 -1 0.11 21084 1 0.01 -1 -1 33204 -1 -1 31 31 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65388 31 32 352 285 1 184 94 17 17 289 -1 unnamed_device 25.5 MiB 0.10 988 63.9 MiB 0.06 0.00 3.70647 -107.491 -3.70647 3.70647 0.83 0.000172048 0.000142421 0.0102499 0.00866224 26 2742 24 6.64007e+06 389298 477104. 1650.88 2.63 0.0762582 0.0652998 21682 110474 -1 2299 20 1367 2385 152112 35771 0 0 152112 35771 2385 1799 0 0 8560 6863 0 0 12698 9577 0 0 2385 2081 0 0 63718 7709 0 0 62366 7742 0 0 2385 0 0 1018 1394 1373 9176 0 0 3.21617 3.21617 -121.096 -3.21617 0 0 585099. 2024.56 0.21 0.04 0.08 -1 -1 0.21 0.0121137 0.0107879 135 51 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_042.v common 5.83 vpr 63.64 MiB -1 -1 0.11 20592 1 0.01 -1 -1 33216 -1 -1 23 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65168 32 32 291 242 1 179 87 17 17 289 -1 unnamed_device 25.3 MiB 0.17 993 63.6 MiB 0.08 0.00 3.46356 -96.491 -3.46356 3.46356 0.76 0.000138505 0.000113489 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0.00 -1 -1 33124 -1 -1 24 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65108 32 32 291 230 1 168 88 17 17 289 -1 unnamed_device 25.2 MiB 0.04 868 63.6 MiB 0.07 0.00 3.36216 -101.805 -3.36216 3.36216 0.94 0.000150144 0.000123695 0.0116505 0.00981518 30 2127 21 6.64007e+06 301392 526063. 1820.29 2.02 0.0681637 0.0587193 22546 126617 -1 1715 20 1130 2198 107283 26167 0 0 107283 26167 2198 1412 0 0 7102 5635 0 0 9577 7457 0 0 2198 1673 0 0 41524 5327 0 0 44684 4663 0 0 2198 0 0 1068 1415 1337 9224 0 0 3.57243 3.57243 -117.151 -3.57243 0 0 666494. 2306.21 0.25 0.04 0.08 -1 -1 0.25 0.0103495 0.00929154 123 -1 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_048.v common 5.38 vpr 64.13 MiB -1 -1 0.11 20952 1 0.01 -1 -1 32968 -1 -1 24 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65672 32 32 353 287 1 198 88 17 17 289 -1 unnamed_device 25.7 MiB 0.23 1104 64.1 MiB 0.13 0.00 3.67818 -114.268 -3.67818 3.67818 0.87 0.000171659 0.000142073 0.039313 0.0252398 26 2902 23 6.64007e+06 301392 477104. 1650.88 2.20 0.0976903 0.0753975 21682 110474 -1 2375 18 1149 1665 156068 33847 0 0 156068 33847 1665 1366 0 0 6306 5243 0 0 9410 7568 0 0 1665 1414 0 0 70558 8946 0 0 66464 9310 0 0 1665 0 0 516 650 582 4691 0 0 3.26903 3.26903 -123.031 -3.26903 0 0 585099. 2024.56 0.21 0.04 0.07 -1 -1 0.21 0.0108652 0.00974501 138 52 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_049.v common 6.32 vpr 63.70 MiB -1 -1 0.11 20956 1 0.01 -1 -1 33188 -1 -1 32 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65232 32 32 361 291 1 185 96 17 17 289 -1 unnamed_device 25.3 MiB 0.11 1015 63.7 MiB 0.10 0.00 2.9151 -98.0492 -2.9151 2.9151 0.79 0.000174147 0.000142868 0.0168641 0.0141047 28 2697 24 6.64007e+06 401856 500653. 1732.36 3.32 0.102936 0.0891959 21970 115934 -1 2163 19 1160 2092 150412 34047 0 0 150412 34047 2092 1468 0 0 7339 5966 0 0 10850 8496 0 0 2092 1574 0 0 63045 8586 0 0 64994 7957 0 0 2092 0 0 932 1313 1576 9721 0 0 2.85277 2.85277 -113.571 -2.85277 0 0 612192. 2118.31 0.25 0.04 0.07 -1 -1 0.25 0.0117952 0.0106008 133 52 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_050.v common 3.80 vpr 63.92 MiB -1 -1 0.12 20880 1 0.01 -1 -1 33160 -1 -1 37 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65456 32 32 382 305 1 192 101 17 17 289 -1 unnamed_device 25.4 MiB 0.11 1097 63.9 MiB 0.20 0.00 3.82667 -120.249 -3.82667 3.82667 0.93 0.000197482 0.000163862 0.0348299 0.0321679 32 2360 19 6.64007e+06 464646 554710. 1919.41 0.71 0.0667581 0.0595789 22834 132086 -1 2113 15 1096 1611 108924 24951 0 0 108924 24951 1611 1196 0 0 5841 4727 0 0 8693 6655 0 0 1611 1295 0 0 44610 5936 0 0 46558 5142 0 0 1611 0 0 515 575 522 4583 0 0 3.35083 3.35083 -127.273 -3.35083 0 0 701300. 2426.64 0.26 0.03 0.08 -1 -1 0.26 0.0108352 0.00975982 145 59 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_051.v common 3.31 vpr 63.51 MiB -1 -1 0.12 20808 1 0.02 -1 -1 33424 -1 -1 29 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65032 32 32 306 248 1 166 93 17 17 289 -1 unnamed_device 25.1 MiB 0.04 850 63.5 MiB 0.08 0.00 3.38416 -99.6745 -3.38416 3.38416 0.78 0.000150964 0.000124044 0.0119303 0.00992742 32 2008 20 6.64007e+06 364182 554710. 1919.41 0.68 0.0376758 0.0321601 22834 132086 -1 1704 20 1156 1883 118677 28260 0 0 118677 28260 1883 1287 0 0 6840 5495 0 0 10084 7819 0 0 1883 1449 0 0 53818 5486 0 0 44169 6724 0 0 1883 0 0 727 924 930 6806 0 0 3.57043 3.57043 -117.016 -3.57043 0 0 701300. 2426.64 0.25 0.03 0.09 -1 -1 0.25 0.0103548 0.0092516 122 21 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_052.v common 5.20 vpr 63.71 MiB -1 -1 0.11 20876 1 0.01 -1 -1 33316 -1 -1 24 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65236 32 32 319 257 1 198 88 17 17 289 -1 unnamed_device 25.0 MiB 0.20 1165 63.7 MiB 0.08 0.00 4.07126 -117.916 -4.07126 4.07126 0.73 0.000155652 0.000127879 0.0140943 0.0116774 32 2606 21 6.64007e+06 301392 554710. 1919.41 2.33 0.0883204 0.0757454 22834 132086 -1 2233 21 1486 2142 161787 35789 0 0 161787 35789 2142 1764 0 0 7902 6564 0 0 11870 9154 0 0 2142 1875 0 0 69047 8410 0 0 68684 8022 0 0 2142 0 0 656 627 771 5574 0 0 4.03702 4.03702 -135.19 -4.03702 0 0 701300. 2426.64 0.28 0.04 0.09 -1 -1 0.28 0.0113389 0.0101402 133 26 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_053.v common 9.21 vpr 63.93 MiB -1 -1 0.12 21092 1 0.02 -1 -1 33180 -1 -1 25 31 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65468 31 32 373 299 1 202 88 17 17 289 -1 unnamed_device 25.3 MiB 0.29 1048 63.9 MiB 0.09 0.00 4.03253 -118.529 -4.03253 4.03253 0.75 0.000169611 0.000139387 0.0157399 0.0129287 28 3494 43 6.64007e+06 313950 500653. 1732.36 6.05 0.128155 0.0991972 21970 115934 -1 2523 26 1936 3188 281584 70472 0 0 281584 70472 3188 2622 0 0 10976 8708 0 0 16474 12568 0 0 3188 2953 0 0 128141 21648 0 0 119617 21973 0 0 3188 0 0 1252 1929 1731 11362 0 0 4.49029 4.49029 -147.718 -4.49029 0 0 612192. 2118.31 0.22 0.06 0.09 -1 -1 0.22 0.0146977 0.0129804 148 58 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_054.v common 8.32 vpr 64.06 MiB -1 -1 0.12 20812 1 0.01 -1 -1 33116 -1 -1 22 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65596 32 32 387 315 1 189 86 17 17 289 -1 unnamed_device 25.5 MiB 0.12 984 64.1 MiB 0.08 0.00 3.49656 -107.233 -3.49656 3.49656 0.77 0.000178919 0.000147917 0.0148274 0.0123953 28 3294 37 6.64007e+06 276276 500653. 1732.36 5.12 0.123506 0.107247 21970 115934 -1 2535 21 1575 2818 289847 75954 0 0 289847 75954 2818 2244 0 0 9920 8051 0 0 14966 11445 0 0 2818 2427 0 0 128900 26385 0 0 130425 25402 0 0 2818 0 0 1243 1530 1238 9699 0 0 4.13742 4.13742 -136.849 -4.13742 0 0 612192. 2118.31 0.34 0.07 0.16 -1 -1 0.34 0.0139881 0.0123981 136 74 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_055.v common 4.78 vpr 63.43 MiB -1 -1 0.10 20696 1 0.01 -1 -1 33140 -1 -1 24 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64948 32 32 251 219 1 140 88 17 17 289 -1 unnamed_device 25.0 MiB 0.04 729 63.4 MiB 0.07 0.00 2.7119 -83.0677 -2.7119 2.7119 0.77 0.000124121 0.000100587 0.0110486 0.00909527 30 1587 18 6.64007e+06 301392 526063. 1820.29 1.98 0.0577056 0.0488797 22546 126617 -1 1372 15 534 820 43292 10551 0 0 43292 10551 820 568 0 0 2727 2084 0 0 3527 2835 0 0 820 617 0 0 17099 2347 0 0 18299 2100 0 0 820 0 0 286 316 299 2611 0 0 2.52837 2.52837 -90.2066 -2.52837 0 0 666494. 2306.21 0.28 0.02 0.10 -1 -1 0.28 0.00697799 0.00631067 97 20 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_056.v common 5.70 vpr 64.05 MiB -1 -1 0.10 20672 1 0.01 -1 -1 32988 -1 -1 22 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65588 32 32 341 285 1 187 86 17 17 289 -1 unnamed_device 25.4 MiB 0.19 985 64.1 MiB 0.06 0.00 3.21396 -114.637 -3.21396 3.21396 1.23 0.000161702 0.000133356 0.0104596 0.00890027 26 2777 21 6.64007e+06 276276 477104. 1650.88 2.30 0.0733014 0.06301 21682 110474 -1 2335 20 1627 2300 190178 41966 0 0 190178 41966 2300 2069 0 0 8256 6890 0 0 12427 9397 0 0 2300 2108 0 0 81626 11106 0 0 83269 10396 0 0 2300 0 0 673 729 666 5714 0 0 3.48997 3.48997 -136.201 -3.48997 0 0 585099. 2024.56 0.21 0.05 0.07 -1 -1 0.21 0.0113885 0.0100919 127 62 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_057.v common 4.05 vpr 63.66 MiB -1 -1 0.12 20984 1 0.01 -1 -1 33456 -1 -1 29 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65192 32 32 387 293 1 234 93 17 17 289 -1 unnamed_device 25.5 MiB 0.20 1448 63.7 MiB 0.11 0.00 4.36321 -135.43 -4.36321 4.36321 0.87 0.000190394 0.00015794 0.0167498 0.0140981 32 3238 27 6.64007e+06 364182 554710. 1919.41 0.80 0.0572291 0.049571 22834 132086 -1 2929 25 2232 3517 314604 67550 0 0 314604 67550 3517 2937 0 0 13107 10844 0 0 20949 15895 0 0 3517 3179 0 0 138522 17152 0 0 134992 17543 0 0 3517 0 0 1285 1385 1357 10494 0 0 5.13028 5.13028 -160.67 -5.13028 0 0 701300. 2426.64 0.40 0.07 0.09 -1 -1 0.40 0.0155973 0.0138648 169 28 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_058.v common 5.42 vpr 63.62 MiB -1 -1 0.11 20780 1 0.01 -1 -1 33316 -1 -1 32 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65144 32 32 340 270 1 181 96 17 17 289 -1 unnamed_device 25.1 MiB 0.09 1034 63.6 MiB 0.07 0.00 3.67472 -113.027 -3.67472 3.67472 0.85 0.000170925 0.000140208 0.017162 0.01547 32 2068 20 6.64007e+06 401856 554710. 1919.41 2.33 0.0847339 0.0731562 22834 132086 -1 1881 20 1123 1733 109303 25050 0 0 109303 25050 1733 1259 0 0 6143 4883 0 0 9794 7109 0 0 1733 1372 0 0 47774 4780 0 0 42126 5647 0 0 1733 0 0 610 616 730 5655 0 0 3.07237 3.07237 -117.271 -3.07237 0 0 701300. 2426.64 0.45 0.03 0.08 -1 -1 0.45 0.0113191 0.0101382 133 31 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_059.v common 5.08 vpr 63.42 MiB -1 -1 0.11 20380 1 0.01 -1 -1 33232 -1 -1 26 30 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64940 30 32 278 235 1 148 88 17 17 289 -1 unnamed_device 24.9 MiB 0.06 767 63.4 MiB 0.07 0.00 2.7859 -86.9546 -2.7859 2.7859 0.79 0.000135264 0.00011088 0.0108047 0.00904046 26 1903 22 6.64007e+06 326508 477104. 1650.88 2.43 0.0668931 0.0570606 21682 110474 -1 1733 21 1051 1615 112764 26326 0 0 112764 26326 1615 1213 0 0 5799 4731 0 0 8773 6618 0 0 1615 1336 0 0 47793 6392 0 0 47169 6036 0 0 1615 0 0 564 688 746 5595 0 0 2.79297 2.79297 -104.793 -2.79297 0 0 585099. 2024.56 0.21 0.03 0.07 -1 -1 0.21 0.0095659 0.00848409 104 29 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_060.v common 4.21 vpr 64.06 MiB -1 -1 0.12 21272 1 0.01 -1 -1 33532 -1 -1 27 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65596 32 32 431 332 1 235 91 17 17 289 -1 unnamed_device 25.9 MiB 0.45 1385 64.1 MiB 0.13 0.00 5.03129 -150.861 -5.03129 5.03129 0.84 0.000208067 0.000172323 0.0514313 0.0420747 32 2896 23 6.64007e+06 339066 554710. 1919.41 0.84 0.0903314 0.0759719 22834 132086 -1 2436 22 1733 2476 147846 36628 0 0 147846 36628 2476 2029 0 0 9082 7391 0 0 13324 10224 0 0 2476 2147 0 0 60166 7523 0 0 60322 7314 0 0 2476 0 0 743 888 849 7022 0 0 5.12054 5.12054 -172.926 -5.12054 0 0 701300. 2426.64 0.24 0.04 0.09 -1 -1 0.24 0.0145568 0.0130251 170 62 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_061.v common 3.76 vpr 63.74 MiB -1 -1 0.11 21032 1 0.01 -1 -1 32936 -1 -1 33 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65272 32 32 336 268 1 174 97 17 17 289 -1 unnamed_device 25.2 MiB 0.11 938 63.7 MiB 0.05 0.00 3.69147 -114.707 -3.69147 3.69147 0.91 0.000159164 0.000131551 0.0078608 0.00665455 32 2244 21 6.64007e+06 414414 554710. 1919.41 0.71 0.0360731 0.0309749 22834 132086 -1 2027 19 1304 2009 146415 33551 0 0 146415 33551 2009 1471 0 0 7484 6252 0 0 12066 9192 0 0 2009 1606 0 0 59324 7952 0 0 63523 7078 0 0 2009 0 0 705 895 900 6985 0 0 3.79663 3.79663 -131.52 -3.79663 0 0 701300. 2426.64 0.26 0.04 0.09 -1 -1 0.26 0.0110271 0.00984279 130 31 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_062.v common 5.03 vpr 63.12 MiB -1 -1 0.10 20748 1 0.01 -1 -1 33268 -1 -1 23 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64640 32 32 231 199 1 140 87 17 17 289 -1 unnamed_device 24.5 MiB 0.05 756 63.1 MiB 0.06 0.00 2.8441 -82.1212 -2.8441 2.8441 0.80 0.000133228 0.000110021 0.00904084 0.00754728 28 1872 20 6.64007e+06 288834 500653. 1732.36 2.28 0.0510057 0.0435312 21970 115934 -1 1598 19 811 1376 100363 23586 0 0 100363 23586 1376 1035 0 0 5003 4119 0 0 7462 5943 0 0 1376 1125 0 0 43840 5530 0 0 41306 5834 0 0 1376 0 0 565 781 934 5600 0 0 2.81777 2.81777 -98.8746 -2.81777 0 0 612192. 2118.31 0.25 0.05 0.09 -1 -1 0.25 0.00887011 0.007944 100 -1 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_063.v common 5.25 vpr 63.74 MiB -1 -1 0.12 20824 1 0.01 -1 -1 33408 -1 -1 34 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65272 32 32 349 273 1 191 98 17 17 289 -1 unnamed_device 25.4 MiB 0.08 993 63.7 MiB 0.08 0.00 4.67452 -111.4 -4.67452 4.67452 0.84 0.000176462 0.000147591 0.0134709 0.0115441 32 2480 23 6.64007e+06 426972 554710. 1919.41 2.36 0.0932284 0.0808031 22834 132086 -1 2024 20 1291 2328 141067 33531 0 0 141067 33531 2328 1502 0 0 8277 6633 0 0 12633 9491 0 0 2328 1642 0 0 58775 7119 0 0 56726 7144 0 0 2328 0 0 1037 1782 1704 11989 0 0 4.73968 4.73968 -132.674 -4.73968 0 0 701300. 2426.64 0.28 0.04 0.10 -1 -1 0.28 0.0111148 0.00991094 139 26 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_064.v common 5.57 vpr 63.44 MiB -1 -1 0.11 20612 1 0.01 -1 -1 33108 -1 -1 20 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64964 32 32 247 207 1 147 84 17 17 289 -1 unnamed_device 25.0 MiB 0.04 834 63.4 MiB 0.08 0.00 2.8171 -91.1457 -2.8171 2.8171 0.77 0.000130473 0.000105959 0.0118211 0.00979663 32 1896 22 6.64007e+06 251160 554710. 1919.41 2.50 0.0591827 0.0503677 22834 132086 -1 1717 20 1152 1984 142463 32073 0 0 142463 32073 1984 1394 0 0 7312 6119 0 0 11495 8550 0 0 1984 1597 0 0 59766 7452 0 0 59922 6961 0 0 1984 0 0 832 854 1030 6984 0 0 2.87197 2.87197 -107.171 -2.87197 0 0 701300. 2426.64 0.24 0.04 0.08 -1 -1 0.24 0.00855837 0.00762341 104 -1 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_065.v common 4.69 vpr 63.34 MiB -1 -1 0.11 20504 1 0.01 -1 -1 33280 -1 -1 33 30 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64860 30 32 278 235 1 147 95 17 17 289 -1 unnamed_device 24.8 MiB 0.09 858 63.3 MiB 0.07 0.00 3.22421 -90.1146 -3.22421 3.22421 0.95 0.000136754 0.00011174 0.010873 0.00901868 28 1805 21 6.64007e+06 414414 500653. 1732.36 1.69 0.0580748 0.0492357 21970 115934 -1 1627 15 694 1219 74940 17383 0 0 74940 17383 1219 789 0 0 4345 3537 0 0 6184 4895 0 0 1219 873 0 0 31584 3540 0 0 30389 3749 0 0 1219 0 0 525 514 659 4903 0 0 2.62817 2.62817 -101.037 -2.62817 0 0 612192. 2118.31 0.22 0.02 0.07 -1 -1 0.22 0.00736312 0.00661288 105 29 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_066.v common 5.39 vpr 64.00 MiB -1 -1 0.12 21032 1 0.01 -1 -1 33200 -1 -1 26 29 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65532 29 32 355 287 1 198 87 17 17 289 -1 unnamed_device 25.4 MiB 0.23 1098 64.0 MiB 0.07 0.00 3.67395 -109.891 -3.67395 3.67395 0.77 0.000183803 0.000154142 0.012403 0.0104557 26 2990 45 6.64007e+06 326508 477104. 1650.88 2.38 0.109116 0.0970941 21682 110474 -1 2294 17 1422 2149 151485 34776 0 0 151485 34776 2149 1741 0 0 7700 6391 0 0 11355 8722 0 0 2149 1971 0 0 64826 8065 0 0 63306 7886 0 0 2149 0 0 727 740 715 5861 0 0 3.76782 3.76782 -130.04 -3.76782 0 0 585099. 2024.56 0.38 0.06 0.07 -1 -1 0.38 0.0119386 0.0107399 139 56 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_067.v common 5.55 vpr 63.77 MiB -1 -1 0.12 21044 1 0.01 -1 -1 33196 -1 -1 24 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65304 32 32 358 289 1 175 88 17 17 289 -1 unnamed_device 25.2 MiB 0.25 917 63.8 MiB 0.05 0.00 3.64276 -112.872 -3.64276 3.64276 0.84 0.000171133 0.000140628 0.00941566 0.00806725 32 2098 20 6.64007e+06 301392 554710. 1919.41 2.47 0.0915157 0.0792519 22834 132086 -1 1882 22 1563 2377 159900 37817 0 0 159900 37817 2377 1848 0 0 8856 7502 0 0 14565 10992 0 0 2377 1987 0 0 64383 7849 0 0 67342 7639 0 0 2377 0 0 814 860 887 7126 0 0 3.56742 3.56742 -127.655 -3.56742 0 0 701300. 2426.64 0.25 0.04 0.08 -1 -1 0.25 0.0129555 0.0115321 130 51 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_068.v common 5.16 vpr 63.71 MiB -1 -1 0.11 20600 1 0.01 -1 -1 33232 -1 -1 28 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65240 32 32 353 285 1 181 92 17 17 289 -1 unnamed_device 25.1 MiB 0.20 1015 63.7 MiB 0.09 0.00 3.99107 -121.69 -3.99107 3.99107 0.76 0.000205046 0.000172831 0.0136784 0.0114622 26 2740 35 6.64007e+06 351624 477104. 1650.88 2.32 0.0838742 0.0723485 21682 110474 -1 2327 21 1422 2476 203220 46097 0 0 203220 46097 2476 1774 0 0 8746 7095 0 0 13367 9912 0 0 2476 1949 0 0 89381 12272 0 0 86774 13095 0 0 2476 0 0 1054 1340 1294 9378 0 0 3.97303 3.97303 -139.345 -3.97303 0 0 585099. 2024.56 0.22 0.06 0.07 -1 -1 0.22 0.0239442 0.0226251 133 48 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_069.v common 5.36 vpr 63.45 MiB -1 -1 0.11 20460 1 0.01 -1 -1 33364 -1 -1 17 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64968 32 32 276 237 1 159 81 17 17 289 -1 unnamed_device 24.9 MiB 0.35 1003 63.4 MiB 0.06 0.00 3.67818 -110.331 -3.67818 3.67818 0.77 0.000127414 0.000103653 0.0116049 0.00969544 32 2110 17 6.64007e+06 213486 554710. 1919.41 2.18 0.0656536 0.0560697 22834 132086 -1 1853 16 794 1043 69959 16351 0 0 69959 16351 1043 917 0 0 3851 3169 0 0 5436 4302 0 0 1043 976 0 0 29113 3679 0 0 29473 3308 0 0 1043 0 0 249 240 226 2288 0 0 3.35823 3.35823 -119.997 -3.35823 0 0 701300. 2426.64 0.25 0.02 0.08 -1 -1 0.25 0.00838741 0.00757241 105 31 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_070.v common 3.82 vpr 63.72 MiB -1 -1 0.12 20920 1 0.01 -1 -1 33420 -1 -1 19 31 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65252 31 32 319 272 1 168 82 17 17 289 -1 unnamed_device 25.3 MiB 0.19 739 63.7 MiB 0.04 0.00 3.12596 -96.872 -3.12596 3.12596 0.77 0.000157319 0.000131577 0.00905538 0.0076608 32 2096 22 6.64007e+06 238602 554710. 1919.41 0.71 0.0373742 0.0322669 22834 132086 -1 1637 19 1124 1664 107120 26285 0 0 107120 26285 1664 1368 0 0 5977 5012 0 0 9130 6968 0 0 1664 1404 0 0 43295 5498 0 0 45390 6035 0 0 1664 0 0 540 547 315 4146 0 0 3.13883 3.13883 -112.295 -3.13883 0 0 701300. 2426.64 0.40 0.04 0.08 -1 -1 0.40 0.0109871 0.00977777 113 60 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_071.v common 3.53 vpr 63.69 MiB -1 -1 0.12 20884 1 0.01 -1 -1 33276 -1 -1 33 30 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65216 30 32 329 273 1 166 95 17 17 289 -1 unnamed_device 25.2 MiB 0.13 911 63.7 MiB 0.05 0.00 2.8221 -83.2193 -2.8221 2.8221 0.77 0.000160529 0.000131316 0.00823031 0.00690792 26 2232 20 6.64007e+06 414414 477104. 1650.88 0.78 0.0375042 0.0321738 21682 110474 -1 1930 18 1049 1818 117188 27804 0 0 117188 27804 1818 1138 0 0 6673 5323 0 0 9773 7607 0 0 1818 1273 0 0 49685 5955 0 0 47421 6508 0 0 1818 0 0 769 1129 1322 8232 0 0 2.90897 2.90897 -100.774 -2.90897 0 0 585099. 2024.56 0.21 0.03 0.07 -1 -1 0.21 0.0100189 0.0089157 123 52 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_072.v common 5.41 vpr 63.55 MiB -1 -1 0.12 20604 1 0.02 -1 -1 33168 -1 -1 35 28 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65080 28 32 277 229 1 155 95 17 17 289 -1 unnamed_device 25.0 MiB 0.08 929 63.6 MiB 0.05 0.00 3.51555 -88.3652 -3.51555 3.51555 0.83 0.00015164 0.000125986 0.00854944 0.00692478 24 2363 21 6.64007e+06 439530 448715. 1552.65 2.23 0.0737255 0.0632466 21394 104001 -1 1935 20 990 1957 148689 31701 0 0 148689 31701 1957 1338 0 0 7082 5391 0 0 10721 7689 0 0 1957 1476 0 0 63368 8010 0 0 63604 7797 0 0 1957 0 0 967 1409 1532 9993 0 0 3.43322 3.43322 -105.429 -3.43322 0 0 554710. 1919.41 0.28 0.04 0.11 -1 -1 0.28 0.0101109 0.00904181 115 20 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_073.v common 5.84 vpr 63.62 MiB -1 -1 0.11 20644 1 0.02 -1 -1 33204 -1 -1 18 30 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65152 30 32 317 269 1 152 80 17 17 289 -1 unnamed_device 25.0 MiB 0.11 630 63.6 MiB 0.07 0.00 3.29461 -91.6276 -3.29461 3.29461 0.88 0.000144187 0.000114641 0.0126346 0.0102362 32 1968 34 6.64007e+06 226044 554710. 1919.41 2.51 0.0796069 0.0679834 22834 132086 -1 1607 19 1254 2126 150283 36386 0 0 150283 36386 2126 1615 0 0 7457 6193 0 0 11780 8600 0 0 2126 1771 0 0 61858 9078 0 0 64936 9129 0 0 2126 0 0 872 1109 1035 7346 0 0 3.26157 3.26157 -110.717 -3.26157 0 0 701300. 2426.64 0.34 0.11 0.15 -1 -1 0.34 0.0242219 0.0228758 108 58 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_074.v common 4.72 vpr 63.59 MiB -1 -1 0.11 20784 1 0.01 -1 -1 33280 -1 -1 21 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65120 32 32 335 282 1 184 85 17 17 289 -1 unnamed_device 25.1 MiB 0.19 1023 63.6 MiB 0.06 0.00 3.14796 -106.886 -3.14796 3.14796 0.77 0.000262444 0.000150697 0.00999469 0.00814931 30 2189 18 6.64007e+06 263718 526063. 1820.29 1.86 0.0634009 0.053806 22546 126617 -1 1934 17 1004 1460 81398 19348 0 0 81398 19348 1460 1117 0 0 4968 3939 0 0 6319 5205 0 0 1460 1156 0 0 32435 4258 0 0 34756 3673 0 0 1460 0 0 456 397 274 3499 0 0 3.19283 3.19283 -121.958 -3.19283 0 0 666494. 2306.21 0.34 0.04 0.08 -1 -1 0.34 0.00926933 0.00831191 121 62 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_075.v common 5.31 vpr 63.57 MiB -1 -1 0.11 20436 1 0.01 -1 -1 32924 -1 -1 32 31 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65100 31 32 293 230 1 175 95 17 17 289 -1 unnamed_device 25.1 MiB 0.04 1045 63.6 MiB 0.07 0.00 3.68447 -107.387 -3.68447 3.68447 0.77 0.000155367 0.000128066 0.00997242 0.00831994 32 2303 19 6.64007e+06 401856 554710. 1919.41 2.30 0.0585035 0.0498745 22834 132086 -1 2053 19 1136 1973 126592 29489 0 0 126592 29489 1973 1404 0 0 7278 5859 0 0 11121 8545 0 0 1973 1577 0 0 53012 5957 0 0 51235 6147 0 0 1973 0 0 837 996 868 7118 0 0 3.71963 3.71963 -124.079 -3.71963 0 0 701300. 2426.64 0.26 0.04 0.09 -1 -1 0.26 0.0102961 0.00924124 127 -1 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_076.v common 5.92 vpr 64.02 MiB -1 -1 0.11 20844 1 0.02 -1 -1 33188 -1 -1 24 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65556 32 32 350 275 1 209 88 17 17 289 -1 unnamed_device 25.4 MiB 0.22 1051 64.0 MiB 0.06 0.00 4.34793 -133.107 -4.34793 4.34793 0.76 0.000166553 0.000138019 0.0085657 0.00725657 32 2980 25 6.64007e+06 301392 554710. 1919.41 2.54 0.0829548 0.0710503 22834 132086 -1 2432 21 1511 2260 156720 36584 0 0 156720 36584 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-1 -1 23 30 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65336 30 32 375 299 1 187 85 17 17 289 -1 unnamed_device 25.4 MiB 0.17 1022 63.8 MiB 0.07 0.00 3.92987 -116.279 -3.92987 3.92987 0.81 0.000162805 0.000132998 0.013444 0.0111753 28 2357 21 6.64007e+06 288834 500653. 1732.36 2.25 0.0804094 0.0686311 21970 115934 -1 2115 23 1599 2611 183101 40681 0 0 183101 40681 2611 1970 0 0 9126 7316 0 0 13876 10486 0 0 2611 2121 0 0 81021 8848 0 0 73856 9940 0 0 2611 0 0 1012 999 1201 8439 0 0 3.85963 3.85963 -135.626 -3.85963 0 0 612192. 2118.31 0.22 0.05 0.07 -1 -1 0.22 0.0152587 0.0137721 138 58 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_081.v common 5.69 vpr 63.93 MiB -1 -1 0.12 20684 1 0.01 -1 -1 33312 -1 -1 26 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65460 32 32 340 270 1 200 90 17 17 289 -1 unnamed_device 25.6 MiB 0.19 1214 63.9 MiB 0.13 0.00 4.18044 -127.637 -4.18044 4.18044 0.82 0.000157477 0.000129 0.0167176 0.0141988 28 2762 25 6.64007e+06 326508 500653. 1732.36 2.68 0.0827248 0.0706997 21970 115934 -1 2365 21 1743 2832 221968 51511 0 0 221968 51511 2832 2227 0 0 10018 8300 0 0 14677 11269 0 0 2832 2360 0 0 94572 14071 0 0 97037 13284 0 0 2832 0 0 1089 1779 1927 11893 0 0 4.15669 4.15669 -145.723 -4.15669 0 0 612192. 2118.31 0.21 0.05 0.07 -1 -1 0.21 0.0114871 0.010197 140 31 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_082.v common 4.28 vpr 63.82 MiB -1 -1 0.13 20776 1 0.01 -1 -1 33020 -1 -1 30 31 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65356 31 32 340 275 1 195 93 17 17 289 -1 unnamed_device 25.5 MiB 0.23 1101 63.8 MiB 0.10 0.00 4.22421 -124.896 -4.22421 4.22421 0.74 0.000164938 0.000135176 0.015729 0.0131102 32 2541 23 6.64007e+06 376740 554710. 1919.41 0.74 0.0515443 0.0436115 22834 132086 -1 2263 21 1442 2106 156545 34439 0 0 156545 34439 2106 1777 0 0 7522 6236 0 0 11541 8719 0 0 2106 1867 0 0 69123 7473 0 0 64147 8367 0 0 2106 0 0 664 683 706 6049 0 0 4.28708 4.28708 -141.4 -4.28708 0 0 701300. 2426.64 0.26 0.04 0.19 -1 -1 0.26 0.011357 0.0101406 148 43 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_083.v common 3.84 vpr 64.09 MiB -1 -1 0.12 21016 1 0.01 -1 -1 33376 -1 -1 33 30 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65632 30 32 377 310 1 177 95 17 17 289 -1 unnamed_device 25.7 MiB 0.27 1021 64.1 MiB 0.09 0.00 3.53327 -109.699 -3.53327 3.53327 0.91 0.000167763 0.000137867 0.0149039 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40734 0 0 176849 40734 2634 2103 0 0 9440 7739 0 0 14380 10706 0 0 2634 2269 0 0 74382 8945 0 0 73379 8972 0 0 2634 0 0 1173 1293 1312 9230 0 0 3.60922 3.60922 -130.121 -3.60922 0 0 701300. 2426.64 0.25 0.04 0.09 -1 -1 0.25 0.0124534 0.0110694 134 54 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_085.v common 3.61 vpr 63.64 MiB -1 -1 0.11 20712 1 0.01 -1 -1 33300 -1 -1 31 29 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65172 29 32 378 310 1 177 92 17 17 289 -1 unnamed_device 25.3 MiB 0.13 986 63.6 MiB 0.10 0.00 4.15226 -117.476 -4.15226 4.15226 0.76 0.000220661 0.000186259 0.0265165 0.0244364 30 2270 20 6.64007e+06 389298 526063. 1820.29 0.97 0.0624861 0.0563145 22546 126617 -1 1923 16 884 1494 90761 20327 0 0 90761 20327 1494 1048 0 0 4976 3887 0 0 6660 5284 0 0 1494 1337 0 0 39125 4300 0 0 37012 4471 0 0 1494 0 0 610 678 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-1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_087.v common 4.80 vpr 63.78 MiB -1 -1 0.11 20864 1 0.01 -1 -1 33400 -1 -1 32 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65312 32 32 373 302 1 176 96 17 17 289 -1 unnamed_device 25.4 MiB 0.18 927 63.8 MiB 0.09 0.00 3.69947 -113.313 -3.69947 3.69947 0.75 0.000170165 0.000139774 0.0144493 0.0120679 30 1985 23 6.64007e+06 401856 526063. 1820.29 2.01 0.0763806 0.0653146 22546 126617 -1 1688 20 1089 1832 82300 21357 0 0 82300 21357 1832 1195 0 0 6089 4879 0 0 8137 6488 0 0 1832 1244 0 0 29900 4224 0 0 34510 3327 0 0 1832 0 0 743 909 538 6114 0 0 3.51143 3.51143 -124.844 -3.51143 0 0 666494. 2306.21 0.24 0.03 0.08 -1 -1 0.24 0.011461 0.0102424 132 62 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_088.v common 5.62 vpr 63.95 MiB -1 -1 0.11 20824 1 0.02 -1 -1 33208 -1 -1 22 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65480 32 32 397 314 1 196 86 17 17 289 -1 unnamed_device 25.5 MiB 0.12 1038 63.9 MiB 0.05 0.00 3.95187 -123.513 -3.95187 3.95187 1.02 0.000188526 0.000154076 0.00909848 0.00765419 26 2830 37 6.64007e+06 276276 477104. 1650.88 2.43 0.0832662 0.0712804 21682 110474 -1 2310 25 2144 3573 243949 56172 0 0 243949 56172 3573 2738 0 0 12662 10025 0 0 19533 14671 0 0 3573 2920 0 0 102740 12661 0 0 101868 13157 0 0 3573 0 0 1429 1703 1756 12073 0 0 3.95002 3.95002 -145.775 -3.95002 0 0 585099. 2024.56 0.22 0.07 0.07 -1 -1 0.22 0.0153634 0.0136358 148 62 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_089.v common 4.05 vpr 63.53 MiB -1 -1 0.11 20340 1 0.01 -1 -1 33132 -1 -1 20 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65052 32 32 269 231 1 170 84 17 17 289 -1 unnamed_device 24.9 MiB 0.20 832 63.5 MiB 0.10 0.01 3.43261 -99.0262 -3.43261 3.43261 0.83 0.00014199 0.000116115 0.00870029 0.00740279 26 2296 39 6.64007e+06 251160 477104. 1650.88 0.99 0.0429844 0.0372214 21682 110474 -1 1798 19 1023 1365 92354 21808 0 0 92354 21808 1365 1221 0 0 4936 3887 0 0 7086 5453 0 0 1365 1269 0 0 38870 5043 0 0 38732 4935 0 0 1365 0 0 342 339 307 3053 0 0 3.20383 3.20383 -114.428 -3.20383 0 0 585099. 2024.56 0.22 0.03 0.07 -1 -1 0.22 0.00915816 0.00814907 109 26 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_090.v common 3.54 vpr 63.27 MiB -1 -1 0.11 20644 1 0.01 -1 -1 33188 -1 -1 21 31 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64788 31 32 245 205 1 150 84 17 17 289 -1 unnamed_device 24.9 MiB 0.04 708 63.3 MiB 0.04 0.00 3.02901 -87.4156 -3.02901 3.02901 0.77 0.000135121 0.000112203 0.00632263 0.0051535 30 1743 27 6.64007e+06 263718 526063. 1820.29 0.88 0.0434148 0.0388277 22546 126617 -1 1425 19 980 1653 91270 21779 0 0 91270 21779 1653 1197 0 0 5509 4249 0 0 7177 5742 0 0 1653 1335 0 0 36685 4818 0 0 38593 4438 0 0 1653 0 0 673 636 683 5403 0 0 2.92497 2.92497 -102.757 -2.92497 0 0 666494. 2306.21 0.25 0.03 0.08 -1 -1 0.25 0.00799158 0.00713282 106 -1 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_091.v common 4.00 vpr 63.87 MiB -1 -1 0.11 20804 1 0.01 -1 -1 33344 -1 -1 26 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65404 32 32 348 274 1 211 90 17 17 289 -1 unnamed_device 25.5 MiB 0.18 939 63.9 MiB 0.06 0.00 4.06553 -126.825 -4.06553 4.06553 0.76 0.000181947 0.000149821 0.00915875 0.00776282 28 2914 25 6.64007e+06 326508 500653. 1732.36 0.91 0.0464285 0.0401205 21970 115934 -1 2264 22 1806 2402 195976 46308 0 0 195976 46308 2402 2147 0 0 8533 6825 0 0 12279 9604 0 0 2402 2261 0 0 88851 12075 0 0 81509 13396 0 0 2402 0 0 596 514 618 5346 0 0 4.06168 4.06168 -143.788 -4.06168 0 0 612192. 2118.31 0.38 0.05 0.13 -1 -1 0.38 0.0125487 0.0112116 144 31 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_092.v common 6.08 vpr 63.76 MiB -1 -1 0.10 20932 1 0.01 -1 -1 33116 -1 -1 29 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65292 32 32 356 289 1 202 93 17 17 289 -1 unnamed_device 25.3 MiB 0.24 1068 63.8 MiB 0.08 0.00 4.05281 -122.297 -4.05281 4.05281 0.76 0.000176477 0.000147648 0.0157637 0.0134772 32 2629 25 6.64007e+06 364182 554710. 1919.41 2.88 0.0962011 0.0831492 22834 132086 -1 2234 19 1542 2351 157195 36928 0 0 157195 36928 2351 1899 0 0 8593 7073 0 0 13334 10082 0 0 2351 1988 0 0 65760 7927 0 0 64806 7959 0 0 2351 0 0 809 877 947 7310 0 0 4.35909 4.35909 -146.097 -4.35909 0 0 701300. 2426.64 0.25 0.04 0.08 -1 -1 0.25 0.0116884 0.010417 155 53 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_093.v common 5.48 vpr 64.36 MiB -1 -1 0.11 20588 1 0.01 -1 -1 33168 -1 -1 36 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65904 32 32 349 260 1 204 100 17 17 289 -1 unnamed_device 25.7 MiB 0.07 1187 64.4 MiB 0.24 0.00 4.49732 -123.909 -4.49732 4.49732 0.99 0.000193431 0.000162553 0.0481407 0.045248 26 3213 22 6.64007e+06 452088 477104. 1650.88 2.54 0.125279 0.112223 21682 110474 -1 2556 19 1455 2672 194320 42948 0 0 194320 42948 2672 2023 0 0 9545 7494 0 0 13957 10751 0 0 2672 2228 0 0 84483 9982 0 0 80991 10470 0 0 2672 0 0 1217 1624 1701 11236 0 0 4.59548 4.59548 -146.99 -4.59548 0 0 585099. 2024.56 0.21 0.05 0.07 -1 -1 0.21 0.0129262 0.0116225 153 -1 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_094.v common 3.65 vpr 63.59 MiB -1 -1 0.11 21008 1 0.01 -1 -1 33304 -1 -1 32 30 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65120 30 32 316 264 1 162 94 17 17 289 -1 unnamed_device 25.2 MiB 0.10 794 63.6 MiB 0.05 0.00 2.8471 -85.0982 -2.8471 2.8471 0.96 0.000187797 0.00015814 0.00862164 0.00727723 32 1976 21 6.64007e+06 401856 554710. 1919.41 0.69 0.0355795 0.0305536 22834 132086 -1 1736 19 1207 2040 144032 34156 0 0 144032 34156 2040 1468 0 0 7538 6323 0 0 12032 9014 0 0 2040 1561 0 0 59500 7911 0 0 60882 7879 0 0 2040 0 0 833 952 828 6949 0 0 2.85197 2.85197 -101.671 -2.85197 0 0 701300. 2426.64 0.25 0.04 0.09 -1 -1 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MiB -1 -1 0.13 20916 1 0.01 -1 -1 33436 -1 -1 26 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65480 32 32 421 327 1 232 90 17 17 289 -1 unnamed_device 25.7 MiB 0.23 1359 63.9 MiB 0.11 0.00 3.53756 -116.72 -3.53756 3.53756 0.76 0.000190814 0.000156694 0.0197856 0.0167703 32 3499 23 6.64007e+06 326508 554710. 1919.41 2.95 0.113767 0.0971977 22834 132086 -1 2983 23 2213 3675 287943 61749 0 0 287943 61749 3675 3001 0 0 13088 10701 0 0 20169 14907 0 0 3675 3188 0 0 123235 15642 0 0 124101 14310 0 0 3675 0 0 1462 1831 1608 12158 0 0 3.72363 3.72363 -138.102 -3.72363 0 0 701300. 2426.64 0.24 0.07 0.08 -1 -1 0.24 0.01679 0.0149771 170 62 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_097.v common 4.12 vpr 63.88 MiB -1 -1 0.12 20836 1 0.01 -1 -1 33184 -1 -1 23 31 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65416 31 32 365 296 1 193 86 17 17 289 -1 unnamed_device 25.3 MiB 0.25 951 63.9 MiB 0.08 0.00 4.33341 -126.789 -4.33341 4.33341 1.27 0.000168715 0.000138392 0.0152753 0.0126673 32 2470 18 6.64007e+06 288834 554710. 1919.41 0.73 0.0471967 0.040478 22834 132086 -1 1971 20 1308 2228 143495 35713 0 0 143495 35713 2228 1767 0 0 8181 6777 0 0 12615 9525 0 0 2228 1819 0 0 58353 8131 0 0 59890 7694 0 0 2228 0 0 920 1203 1066 8045 0 0 4.33409 4.33409 -145.311 -4.33409 0 0 701300. 2426.64 0.25 0.04 0.09 -1 -1 0.25 0.0117486 0.010502 152 60 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_098.v common 3.70 vpr 63.45 MiB -1 -1 0.12 20848 1 0.01 -1 -1 33280 -1 -1 19 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64976 32 32 331 280 1 174 83 17 17 289 -1 unnamed_device 25.1 MiB 0.24 926 63.5 MiB 0.07 0.00 3.74495 -109.736 -3.74495 3.74495 0.77 0.000148562 0.000121462 0.014421 0.0118621 32 2155 18 6.64007e+06 238602 554710. 1919.41 0.76 0.0401949 0.0341455 22834 132086 -1 1797 20 1234 1795 136958 31070 0 0 136958 31070 1795 1448 0 0 6641 5466 0 0 10247 7874 0 0 1795 1497 0 0 57721 7782 0 0 58759 7003 0 0 1795 0 0 561 588 459 4635 0 0 3.58762 3.58762 -128.074 -3.58762 0 0 701300. 2426.64 0.28 0.04 0.08 -1 -1 0.28 0.0111378 0.00998034 128 62 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_099.v common 5.57 vpr 63.50 MiB -1 -1 0.11 21192 1 0.01 -1 -1 33204 -1 -1 30 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65020 32 32 326 263 1 176 94 17 17 289 -1 unnamed_device 25.0 MiB 0.05 1036 63.5 MiB 0.08 0.00 4.23518 -110.63 -4.23518 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0.0634645 22834 132086 -1 2137 20 1493 2520 166886 38754 0 0 166886 38754 2520 1754 0 0 9479 7603 0 0 14391 11097 0 0 2520 1936 0 0 70350 7841 0 0 67626 8523 0 0 2520 0 0 1027 1583 1611 10483 0 0 3.70662 3.70662 -130.298 -3.70662 0 0 701300. 2426.64 0.59 0.05 0.10 -1 -1 0.59 0.0130355 0.0116418 145 46 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_101.v common 3.95 vpr 63.66 MiB -1 -1 0.12 21076 1 0.02 -1 -1 33144 -1 -1 31 30 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65188 30 32 325 268 1 171 93 17 17 289 -1 unnamed_device 25.2 MiB 0.10 1009 63.7 MiB 0.05 0.00 2.8933 -91.5477 -2.8933 2.8933 0.75 0.000190895 0.000160563 0.00831616 0.00706047 32 2194 24 6.64007e+06 389298 554710. 1919.41 0.74 0.0382277 0.0329178 22834 132086 -1 1872 19 1047 1837 118933 27267 0 0 118933 27267 1837 1215 0 0 6682 5480 0 0 10314 7891 0 0 1837 1363 0 0 49770 5512 0 0 48493 5806 0 0 1837 0 0 790 836 841 6618 0 0 2.97917 2.97917 -110.304 -2.97917 0 0 701300. 2426.64 0.24 0.03 0.08 -1 -1 0.24 0.0102607 0.00916542 124 46 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_102.v common 4.07 vpr 64.20 MiB -1 -1 0.12 20816 1 0.00 -1 -1 33132 -1 -1 25 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65740 32 32 350 275 1 214 89 17 17 289 -1 unnamed_device 25.5 MiB 0.22 1119 64.2 MiB 0.07 0.00 4.13153 -129.919 -4.13153 4.13153 0.74 0.000272352 0.000232502 0.0117342 0.00990065 32 2721 47 6.64007e+06 313950 554710. 1919.41 1.07 0.0634085 0.0558121 22834 132086 -1 2336 18 1778 2667 161287 39087 0 0 161287 39087 2667 2008 0 0 9521 8068 0 0 14453 10754 0 0 2667 2219 0 0 64531 8322 0 0 67448 7716 0 0 2667 0 0 889 756 731 6821 0 0 4.10068 4.10068 -144.695 -4.10068 0 0 701300. 2426.64 0.33 0.04 0.09 -1 -1 0.33 0.0121103 0.0108927 148 31 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_103.v common 5.16 vpr 64.04 MiB -1 -1 0.11 20940 1 0.01 -1 -1 33188 -1 -1 36 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65580 32 32 386 307 1 195 100 17 17 289 -1 unnamed_device 25.5 MiB 0.12 1104 64.0 MiB 0.08 0.00 3.87621 -121.227 -3.87621 3.87621 0.95 0.000188494 0.000156375 0.0118604 0.0100959 28 2513 15 6.64007e+06 452088 500653. 1732.36 2.13 0.0822276 0.0713593 21970 115934 -1 2152 21 1068 1763 111230 26072 0 0 111230 26072 1763 1224 0 0 6405 4983 0 0 8976 7229 0 0 1763 1364 0 0 47441 5482 0 0 44882 5790 0 0 1763 0 0 695 674 883 5917 0 0 3.32537 3.32537 -127.212 -3.32537 0 0 612192. 2118.31 0.24 0.04 0.09 -1 -1 0.24 0.0143989 0.0130203 144 59 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_104.v common 5.20 vpr 63.46 MiB -1 -1 0.12 20420 1 0.01 -1 -1 33296 -1 -1 17 29 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64988 29 32 269 229 1 129 78 17 17 289 -1 unnamed_device 25.1 MiB 0.06 649 63.5 MiB 0.06 0.00 2.88681 -85.3419 -2.88681 2.88681 0.77 0.000128761 0.000105419 0.00824084 0.00695122 32 1322 21 6.64007e+06 213486 554710. 1919.41 2.24 0.0596346 0.0505976 22834 132086 -1 1210 19 807 1196 74454 19572 0 0 74454 19572 1196 937 0 0 4549 3769 0 0 7262 5728 0 0 1196 1009 0 0 30018 4083 0 0 30233 4046 0 0 1196 0 0 389 429 460 3328 0 0 2.78317 2.78317 -94.5989 -2.78317 0 0 701300. 2426.64 0.29 0.03 0.10 -1 -1 0.29 0.00868486 0.00772932 91 28 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_105.v common 5.18 vpr 63.61 MiB -1 -1 0.11 20868 1 0.01 -1 -1 33096 -1 -1 21 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65140 32 32 310 266 1 175 85 17 17 289 -1 unnamed_device 25.2 MiB 0.16 906 63.6 MiB 0.07 0.00 3.19816 -104.679 -3.19816 3.19816 0.78 0.000140912 0.000114734 0.0127085 0.0105604 32 1966 21 6.64007e+06 263718 554710. 1919.41 2.24 0.0792221 0.0677435 22834 132086 -1 1820 21 1426 1891 143117 32592 0 0 143117 32592 1891 1567 0 0 7157 5969 0 0 11409 8718 0 0 1891 1639 0 0 60096 7619 0 0 60673 7080 0 0 1891 0 0 465 389 428 4103 0 0 3.49343 3.49343 -124.722 -3.49343 0 0 701300. 2426.64 0.26 0.04 0.08 -1 -1 0.26 0.0111686 0.0098455 117 55 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_106.v common 3.83 vpr 63.59 MiB -1 -1 0.12 20808 1 0.01 -1 -1 33332 -1 -1 37 31 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65112 31 32 326 261 1 177 100 17 17 289 -1 unnamed_device 25.1 MiB 0.06 1074 63.6 MiB 0.10 0.01 3.82167 -106.687 -3.82167 3.82167 0.89 0.000152286 0.000125082 0.0229065 0.0214537 26 2490 23 6.64007e+06 464646 477104. 1650.88 0.94 0.0589734 0.0528376 21682 110474 -1 2198 19 1376 2403 166115 37639 0 0 166115 37639 2403 1765 0 0 8659 6907 0 0 12999 9889 0 0 2403 1908 0 0 68930 8891 0 0 70721 8279 0 0 2403 0 0 1027 1353 1416 9845 0 0 3.95803 3.95803 -130.145 -3.95803 0 0 585099. 2024.56 0.21 0.04 0.07 -1 -1 0.21 0.0107484 0.00961414 129 29 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_107.v common 3.73 vpr 63.45 MiB -1 -1 0.10 20612 1 0.01 -1 -1 33288 -1 -1 22 29 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64976 29 32 262 224 1 168 83 17 17 289 -1 unnamed_device 24.9 MiB 0.20 863 63.5 MiB 0.05 0.00 3.36661 -94.4008 -3.36661 3.36661 0.93 0.000155022 0.000129944 0.00837675 0.00708462 26 2158 21 6.64007e+06 276276 477104. 1650.88 0.68 0.0342302 0.029735 21682 110474 -1 1838 20 1190 1543 106003 25178 0 0 106003 25178 1543 1355 0 0 5621 4573 0 0 8294 6459 0 0 1543 1396 0 0 44190 5803 0 0 44812 5592 0 0 1543 0 0 353 360 289 3301 0 0 3.32403 3.32403 -112.052 -3.32403 0 0 585099. 2024.56 0.21 0.03 0.08 -1 -1 0.21 0.00912943 0.00814125 109 25 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_108.v common 4.78 vpr 63.35 MiB -1 -1 0.10 20620 1 0.00 -1 -1 33160 -1 -1 17 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64872 32 32 278 238 1 149 81 17 17 289 -1 unnamed_device 24.8 MiB 0.11 780 63.4 MiB 0.06 0.00 3.14521 -97.6445 -3.14521 3.14521 0.88 0.00013186 0.000105716 0.0106796 0.00880012 30 1889 21 6.64007e+06 213486 526063. 1820.29 1.75 0.0619314 0.0530657 22546 126617 -1 1566 21 1045 1718 99000 23120 0 0 99000 23120 1718 1240 0 0 5653 4569 0 0 7512 5952 0 0 1718 1354 0 0 41969 4945 0 0 40430 5060 0 0 1718 0 0 673 656 705 5326 0 0 2.68457 2.68457 -102.146 -2.68457 0 0 666494. 2306.21 0.31 0.03 0.08 -1 -1 0.31 0.00925445 0.00824255 108 31 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_109.v common 5.45 vpr 63.95 MiB -1 -1 0.11 20668 1 0.01 -1 -1 33340 -1 -1 36 31 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65488 31 32 373 300 1 181 99 17 17 289 -1 unnamed_device 25.6 MiB 0.12 996 64.0 MiB 0.08 0.00 3.26641 -99.9164 -3.26641 3.26641 0.78 0.000167972 0.000136954 0.013319 0.0110919 30 1973 21 6.64007e+06 452088 526063. 1820.29 2.53 0.0941529 0.0807957 22546 126617 -1 1766 19 1072 1750 101901 22845 0 0 101901 22845 1750 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-114.128 -3.07163 0 0 585099. 2024.56 0.21 0.03 0.07 -1 -1 0.21 0.00779079 0.0070058 107 30 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_111.v common 5.52 vpr 63.89 MiB -1 -1 0.11 20936 1 0.02 -1 -1 33312 -1 -1 32 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65424 32 32 349 286 1 171 96 17 17 289 -1 unnamed_device 25.3 MiB 0.20 1075 63.9 MiB 0.12 0.00 3.01201 -100.358 -3.01201 3.01201 1.03 0.000159803 0.000130337 0.0149799 0.0124947 28 2435 21 6.64007e+06 401856 500653. 1732.36 2.30 0.0888711 0.0774468 21970 115934 -1 2031 18 1105 1868 112572 26215 0 0 112572 26215 1868 1323 0 0 6485 5122 0 0 9378 7302 0 0 1868 1445 0 0 47150 5488 0 0 45823 5535 0 0 1868 0 0 763 1043 1213 7951 0 0 2.77577 2.77577 -110.145 -2.77577 0 0 612192. 2118.31 0.22 0.03 0.07 -1 -1 0.22 0.0109013 0.00980382 127 54 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_112.v common 4.00 vpr 63.98 MiB -1 -1 0.12 20804 1 0.01 -1 -1 33288 -1 -1 32 31 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65516 31 32 396 325 1 183 95 17 17 289 -1 unnamed_device 25.6 MiB 0.24 913 64.0 MiB 0.09 0.00 3.50555 -110.684 -3.50555 3.50555 0.97 0.000188349 0.000157409 0.0167847 0.0141268 32 2147 21 6.64007e+06 401856 554710. 1919.41 0.74 0.0504998 0.0432837 22834 132086 -1 1803 21 1223 1814 116092 27503 0 0 116092 27503 1814 1343 0 0 6823 5595 0 0 10121 7956 0 0 1814 1449 0 0 48725 5469 0 0 46795 5691 0 0 1814 0 0 591 751 680 5522 0 0 3.17963 3.17963 -124.569 -3.17963 0 0 701300. 2426.64 0.27 0.04 0.10 -1 -1 0.27 0.0127126 0.0113175 138 87 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_113.v common 4.88 vpr 63.31 MiB -1 -1 0.11 20760 1 0.01 -1 -1 33188 -1 -1 17 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64832 32 32 303 262 1 150 81 17 17 289 -1 unnamed_device 24.8 MiB 0.13 888 63.3 MiB 0.07 0.00 2.6639 -87.2845 -2.6639 2.6639 0.82 0.000143043 0.00011707 0.0123866 0.0100718 28 1974 23 6.64007e+06 213486 500653. 1732.36 2.09 0.0699984 0.0593759 21970 115934 -1 1772 23 944 1532 117212 26507 0 0 117212 26507 1532 1228 0 0 5525 4582 0 0 8161 6467 0 0 1532 1258 0 0 51211 6556 0 0 49251 6416 0 0 1532 0 0 588 523 583 4552 0 0 2.73897 2.73897 -102.86 -2.73897 0 0 612192. 2118.31 0.22 0.03 0.07 -1 -1 0.22 0.0106543 0.00941711 104 54 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_114.v common 3.92 vpr 63.57 MiB -1 -1 0.11 20516 1 0.01 -1 -1 33204 -1 -1 21 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65096 32 32 290 244 1 175 85 17 17 289 -1 unnamed_device 25.1 MiB 0.19 846 63.6 MiB 0.07 0.00 3.55527 -109.103 -3.55527 3.55527 1.00 0.000154958 0.000130278 0.0111176 0.0092298 32 2245 19 6.64007e+06 263718 554710. 1919.41 0.71 0.0382847 0.0328554 22834 132086 -1 1876 19 1337 1984 141984 33307 0 0 141984 33307 1984 1652 0 0 7378 6213 0 0 10950 8426 0 0 1984 1733 0 0 60004 7806 0 0 59684 7477 0 0 1984 0 0 647 610 510 5045 0 0 3.14763 3.14763 -118.7 -3.14763 0 0 701300. 2426.64 0.25 0.10 0.08 -1 -1 0.25 0.0102061 0.00918928 117 31 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_115.v common 5.38 vpr 63.74 MiB -1 -1 0.10 20780 1 0.01 -1 -1 33336 -1 -1 23 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65272 32 32 318 257 1 194 87 17 17 289 -1 unnamed_device 25.3 MiB 0.17 1051 63.7 MiB 0.07 0.00 3.86215 -116.454 -3.86215 3.86215 1.07 0.000146712 0.000119873 0.0123782 0.0102992 28 2514 19 6.64007e+06 288834 500653. 1732.36 2.35 0.0781905 0.0667039 21970 115934 -1 2238 21 1554 2153 142673 34101 0 0 142673 34101 2153 1793 0 0 7833 6440 0 0 11693 9322 0 0 2153 1923 0 0 59946 7456 0 0 58895 7167 0 0 2153 0 0 599 535 629 5148 0 0 3.79382 3.79382 -133.679 -3.79382 0 0 612192. 2118.31 0.22 0.04 0.07 -1 -1 0.22 0.0125223 0.0113126 130 27 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_116.v common 4.92 vpr 63.57 MiB -1 -1 0.12 20596 1 0.01 -1 -1 33328 -1 -1 29 29 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65096 29 32 324 268 1 168 90 17 17 289 -1 unnamed_device 25.1 MiB 0.14 859 63.6 MiB 0.08 0.00 3.68447 -96.6025 -3.68447 3.68447 0.85 0.000171315 0.000143972 0.0142524 0.0120208 26 2312 26 6.64007e+06 364182 477104. 1650.88 2.12 0.0823373 0.0708805 21682 110474 -1 1818 20 903 1484 94168 22476 0 0 94168 22476 1484 1163 0 0 5483 4325 0 0 7869 6209 0 0 1484 1256 0 0 38616 4942 0 0 39232 4581 0 0 1484 0 0 581 859 894 5982 0 0 3.53023 3.53023 -109.786 -3.53023 0 0 585099. 2024.56 0.22 0.03 0.07 -1 -1 0.22 0.0106364 0.00949875 122 49 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_117.v common 4.10 vpr 64.22 MiB -1 -1 0.11 21076 1 0.01 -1 -1 33216 -1 -1 24 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65764 32 32 393 312 1 213 88 17 17 289 -1 unnamed_device 25.4 MiB 0.23 1157 64.2 MiB 0.14 0.00 4.33064 -141.129 -4.33064 4.33064 0.77 0.000191653 0.00015724 0.0122531 0.0101762 32 2573 21 6.64007e+06 301392 554710. 1919.41 0.84 0.046456 0.0397159 22834 132086 -1 2288 22 1770 2556 175991 41897 0 0 175991 41897 2556 1937 0 0 9711 8342 0 0 15778 12119 0 0 2556 2127 0 0 73666 8417 0 0 71724 8955 0 0 2556 0 0 786 808 804 7030 0 0 4.05449 4.05449 -148.491 -4.05449 0 0 701300. 2426.64 0.26 0.05 0.09 -1 -1 0.26 0.0141077 0.0126009 154 62 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_118.v common 3.51 vpr 63.16 MiB -1 -1 0.11 20336 1 0.01 -1 -1 32836 -1 -1 18 31 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64676 31 32 229 197 1 138 81 17 17 289 -1 unnamed_device 24.6 MiB 0.03 706 63.2 MiB 0.03 0.00 2.9133 -81.7891 -2.9133 2.9133 0.82 0.000117659 9.6621e-05 0.00585339 0.00487872 28 1685 19 6.64007e+06 226044 500653. 1732.36 0.81 0.05515 0.0513964 21970 115934 -1 1523 17 679 1086 68418 16423 0 0 68418 16423 1086 868 0 0 3827 2911 0 0 5428 4305 0 0 1086 909 0 0 29779 3555 0 0 27212 3875 0 0 1086 0 0 407 314 326 3047 0 0 2.71576 2.71576 -94.8353 -2.71576 0 0 612192. 2118.31 0.23 0.02 0.07 -1 -1 0.23 0.00758478 0.0068388 96 -1 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_119.v common 5.87 vpr 64.04 MiB -1 -1 0.12 20932 1 0.00 -1 -1 33364 -1 -1 34 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65576 32 32 412 334 1 190 98 17 17 289 -1 unnamed_device 25.5 MiB 0.12 1105 64.0 MiB 0.10 0.00 3.56376 -119.795 -3.56376 3.56376 0.87 0.000189971 0.000157112 0.0157434 0.0131677 32 2591 21 6.64007e+06 426972 554710. 1919.41 2.71 0.139811 0.123872 22834 132086 -1 2193 21 1638 2412 186753 41577 0 0 186753 41577 2412 1857 0 0 9061 7377 0 0 14392 11032 0 0 2412 2023 0 0 79725 9794 0 0 78751 9494 0 0 2412 0 0 774 928 921 7135 0 0 3.71063 3.71063 -139.204 -3.71063 0 0 701300. 2426.64 0.32 0.08 0.08 -1 -1 0.32 0.0146815 0.0130231 145 87 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_120.v common 4.01 vpr 63.65 MiB -1 -1 0.11 20940 1 0.01 -1 -1 33368 -1 -1 17 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65180 32 32 376 318 1 155 81 17 17 289 -1 unnamed_device 25.2 MiB 0.20 824 63.7 MiB 0.05 0.00 2.8021 -101.477 -2.8021 2.8021 1.01 0.000161101 0.000131232 0.0110999 0.00936936 32 1791 19 6.64007e+06 213486 554710. 1919.41 0.89 0.0486877 0.0428065 22834 132086 -1 1642 21 1362 2045 136290 30418 0 0 136290 30418 2045 1522 0 0 6901 5469 0 0 11240 8065 0 0 2045 1660 0 0 56057 6759 0 0 58002 6943 0 0 2045 0 0 683 780 789 5813 0 0 3.08917 3.08917 -124.292 -3.08917 0 0 701300. 2426.64 0.25 0.04 0.09 -1 -1 0.25 0.0113419 0.0100491 114 93 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_121.v common 3.62 vpr 63.71 MiB -1 -1 0.12 20936 1 0.01 -1 -1 33268 -1 -1 32 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65244 32 32 360 293 1 179 96 17 17 289 -1 unnamed_device 25.1 MiB 0.10 1004 63.7 MiB 0.08 0.00 3.45707 -108.459 -3.45707 3.45707 0.77 0.000194879 0.000164166 0.0135533 0.0113921 32 2221 21 6.64007e+06 401856 554710. 1919.41 0.88 0.0454124 0.0390752 22834 132086 -1 1813 15 842 1265 77135 18183 0 0 77135 18183 1265 923 0 0 4560 3542 0 0 6565 5048 0 0 1265 996 0 0 31424 3879 0 0 32056 3795 0 0 1265 0 0 423 562 526 4348 0 0 3.09343 3.09343 -110.74 -3.09343 0 0 701300. 2426.64 0.25 0.03 0.08 -1 -1 0.25 0.010323 0.0093462 131 57 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_122.v common 6.02 vpr 63.82 MiB -1 -1 0.13 20756 1 0.01 -1 -1 33360 -1 -1 27 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65348 32 32 396 299 1 236 91 17 17 289 -1 unnamed_device 25.5 MiB 0.26 1295 63.8 MiB 0.12 0.00 5.15449 -155.274 -5.15449 5.15449 0.77 0.000198533 0.000164934 0.0205823 0.0175277 32 3284 23 6.64007e+06 339066 554710. 1919.41 2.82 0.124389 0.103937 22834 132086 -1 2699 21 1987 2911 231502 51063 0 0 231502 51063 2911 2435 0 0 11122 9047 0 0 16366 12749 0 0 2911 2634 0 0 100405 12187 0 0 97787 12011 0 0 2911 0 0 924 1420 1279 9014 0 0 5.43934 5.43934 -173 -5.43934 0 0 701300. 2426.64 0.25 0.06 0.09 -1 -1 0.25 0.0148993 0.0133787 170 31 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_123.v common 5.03 vpr 63.21 MiB -1 -1 0.10 20684 1 0.01 -1 -1 33104 -1 -1 18 30 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64732 30 32 224 207 1 137 80 17 17 289 -1 unnamed_device 24.7 MiB 0.14 602 63.2 MiB 0.04 0.00 2.5747 -78.1428 -2.5747 2.5747 0.80 0.000109697 8.8545e-05 0.0071388 0.00594391 28 1575 28 6.64007e+06 226044 500653. 1732.36 2.21 0.0462839 0.0392488 21970 115934 -1 1282 17 751 943 69573 17047 0 0 69573 17047 943 825 0 0 3359 2748 0 0 4950 3899 0 0 943 868 0 0 27593 4567 0 0 31785 4140 0 0 943 0 0 192 182 218 1919 0 0 2.40817 2.40817 -89.7622 -2.40817 0 0 612192. 2118.31 0.31 0.06 0.07 -1 -1 0.31 0.02935 0.00695272 87 29 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_124.v common 4.79 vpr 63.57 MiB -1 -1 0.11 20400 1 0.01 -1 -1 33300 -1 -1 16 30 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65100 30 32 286 239 1 134 78 17 17 289 -1 unnamed_device 25.0 MiB 0.08 610 63.6 MiB 0.04 0.00 3.52781 -96.4169 -3.52781 3.52781 1.05 0.000140145 0.000114275 0.00767875 0.00644186 28 1624 21 6.64007e+06 200928 500653. 1732.36 1.94 0.0635629 0.0542744 21970 115934 -1 1378 20 701 1099 70942 18097 0 0 70942 18097 1099 863 0 0 4157 3274 0 0 5747 4724 0 0 1099 943 0 0 28209 4640 0 0 30631 3653 0 0 1099 0 0 398 659 327 3495 0 0 3.05197 3.05197 -107.875 -3.05197 0 0 612192. 2118.31 0.22 0.03 0.07 -1 -1 0.22 0.00940984 0.00842527 92 29 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_125.v common 3.63 vpr 63.60 MiB -1 -1 0.10 20484 1 0.01 -1 -1 33196 -1 -1 21 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65128 32 32 296 247 1 157 85 17 17 289 -1 unnamed_device 25.1 MiB 0.07 741 63.6 MiB 0.05 0.00 2.8981 -91.503 -2.8981 2.8981 0.78 0.000141486 0.000115342 0.00975084 0.00814136 32 2046 23 6.64007e+06 263718 554710. 1919.41 0.87 0.037419 0.0321726 22834 132086 -1 1735 21 1361 2439 158493 37808 0 0 158493 37808 2439 1797 0 0 8523 7234 0 0 13670 9768 0 0 2439 2073 0 0 62571 8585 0 0 68851 8351 0 0 2439 0 0 1078 1465 1127 8975 0 0 3.22337 3.22337 -115.338 -3.22337 0 0 701300. 2426.64 0.24 0.04 0.09 -1 -1 0.24 0.0102578 0.00910509 115 31 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_126.v common 4.51 vpr 63.18 MiB -1 -1 0.11 20760 1 0.01 -1 -1 33464 -1 -1 27 25 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64692 25 32 216 194 1 122 84 17 17 289 -1 unnamed_device 24.6 MiB 0.04 556 63.2 MiB 0.04 0.00 2.7119 -63.6186 -2.7119 2.7119 0.77 0.000105408 8.6005e-05 0.00761988 0.00633028 26 1466 25 6.64007e+06 339066 477104. 1650.88 1.79 0.0528836 0.0453996 21682 110474 -1 1215 20 730 1232 89677 21038 0 0 89677 21038 1232 938 0 0 4614 3770 0 0 7094 5545 0 0 1232 1042 0 0 37472 4971 0 0 38033 4772 0 0 1232 0 0 502 709 669 4828 0 0 2.96517 2.96517 -78.848 -2.96517 0 0 585099. 2024.56 0.22 0.03 0.07 -1 -1 0.22 0.00747 0.00664361 89 19 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_127.v common 6.01 vpr 63.85 MiB -1 -1 0.12 20820 1 0.01 -1 -1 33188 -1 -1 21 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65384 32 32 376 307 1 185 85 17 17 289 -1 unnamed_device 25.4 MiB 0.13 1072 63.9 MiB 0.10 0.00 3.61676 -114.072 -3.61676 3.61676 0.75 0.000178272 0.000140464 0.0174619 0.0143898 30 2392 19 6.64007e+06 263718 526063. 1820.29 2.69 0.118669 0.106124 22546 126617 -1 2074 18 1050 1899 105255 24501 0 0 105255 24501 1899 1292 0 0 6263 5070 0 0 8493 6712 0 0 1899 1362 0 0 46019 4604 0 0 40682 5461 0 0 1899 0 0 849 724 677 6145 0 0 3.47022 3.47022 -128.025 -3.47022 0 0 666494. 2306.21 0.24 0.03 0.08 -1 -1 0.24 0.011353 0.0101657 136 69 -1 -1 -1 -1 + fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml mult_128.v common 5.93 vpr 63.85 MiB -1 -1 0.12 20852 1 0.02 -1 -1 33492 -1 -1 35 31 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65384 31 32 409 331 1 191 98 17 17 289 -1 unnamed_device 25.3 MiB 0.20 995 63.9 MiB 0.10 0.00 3.48461 -115.73 -3.48461 3.48461 0.77 0.00017735 0.000144148 0.0165299 0.0138209 32 2313 21 6.64007e+06 439530 554710. 1919.41 2.95 0.0902523 0.0778468 22834 132086 -1 2071 20 1413 2172 149048 34054 0 0 149048 34054 2172 1621 0 0 7812 6443 0 0 11938 9072 0 0 2172 1791 0 0 61516 7954 0 0 63438 7173 0 0 2172 0 0 759 915 969 6709 0 0 3.34603 3.34603 -128.235 -3.34603 0 0 701300. 2426.64 0.26 0.04 0.09 -1 -1 0.26 0.0131055 0.0116494 143 86 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_001.v common 4.04 vpr 63.78 MiB -1 -1 0.11 20796 1 0.02 -1 -1 33376 -1 -1 30 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65308 32 32 354 285 1 202 94 17 17 289 -1 unnamed_device 25.2 MiB 0.44 1082 63.8 MiB 0.10 0.00 4.10361 -121.4 -4.10361 4.10361 0.76 0.000186264 0.000153491 0.0161931 0.013493 32 2478 22 6.65987e+06 380340 554710. 1919.41 0.90 0.0705262 0.0633429 22834 132086 -1 2093 21 1633 2519 157956 39625 0 0 157956 39625 2519 1881 0 0 9725 8230 0 0 14839 11729 0 0 2519 2034 0 0 64733 7835 0 0 63621 7916 0 0 2519 0 0 886 1139 1009 8279 0 0 4.42917 4.42917 -147.327 -4.42917 0 0 701300. 2426.64 0.26 0.04 0.12 -1 -1 0.26 0.0128722 0.0115231 152 47 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_002.v common 3.83 vpr 63.83 MiB -1 -1 0.12 20876 1 0.01 -1 -1 33428 -1 -1 23 30 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65364 30 32 363 293 1 194 85 17 17 289 -1 unnamed_device 25.2 MiB 0.24 991 63.8 MiB 0.09 0.00 3.67516 -115.945 -3.67516 3.67516 0.95 0.000165644 0.000136056 0.0159115 0.0133283 32 2373 25 6.65987e+06 291594 554710. 1919.41 0.77 0.0520299 0.0448945 22834 132086 -1 2070 22 1729 2573 202728 45273 0 0 202728 45273 2573 2170 0 0 9713 8235 0 0 15370 11847 0 0 2573 2239 0 0 92249 9315 0 0 80250 11467 0 0 2573 0 0 844 859 825 6789 0 0 4.18983 4.18983 -140.491 -4.18983 0 0 701300. 2426.64 0.24 0.05 0.08 -1 -1 0.24 0.0131022 0.0116906 138 58 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_003.v common 5.96 vpr 63.30 MiB -1 -1 0.11 21156 1 0.01 -1 -1 33376 -1 -1 23 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64820 32 32 299 247 1 188 87 17 17 289 -1 unnamed_device 24.8 MiB 0.09 1069 63.3 MiB 0.05 0.00 3.25104 -98.8467 -3.25104 3.25104 0.91 0.000166903 0.000140393 0.00910519 0.00771273 26 2559 23 6.65987e+06 291594 477104. 1650.88 2.79 0.077263 0.0663174 21682 110474 -1 2226 27 1536 2083 266134 109226 0 0 266134 109226 2083 1737 0 0 8016 6662 0 0 13459 10609 0 0 2083 1870 0 0 122642 45600 0 0 117851 42748 0 0 2083 0 0 547 650 584 5126 0 0 3.65251 3.65251 -124.299 -3.65251 0 0 585099. 2024.56 0.41 0.11 0.07 -1 -1 0.41 0.025725 0.0241294 126 26 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_004.v common 3.89 vpr 63.36 MiB -1 -1 0.12 20612 1 0.01 -1 -1 33148 -1 -1 27 29 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64884 29 32 308 248 1 169 88 17 17 289 -1 unnamed_device 24.9 MiB 0.07 893 63.4 MiB 0.05 0.00 3.3873 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1 0.02 -1 -1 33168 -1 -1 17 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64824 32 32 298 248 1 156 81 17 17 289 -1 unnamed_device 24.7 MiB 0.22 930 63.3 MiB 0.07 0.00 2.86455 -99.7586 -2.86455 2.86455 0.98 0.000144236 0.000119401 0.0131591 0.0109657 32 1984 21 6.65987e+06 215526 554710. 1919.41 0.70 0.0394887 0.0337163 22834 132086 -1 1778 21 1089 1730 125103 28968 0 0 125103 28968 1730 1354 0 0 6592 5670 0 0 10209 8218 0 0 1730 1428 0 0 51692 6393 0 0 53150 5905 0 0 1730 0 0 641 675 675 5517 0 0 2.76451 2.76451 -109.57 -2.76451 0 0 701300. 2426.64 0.25 0.04 0.08 -1 -1 0.25 0.0106658 0.0095571 113 31 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_011.v common 3.85 vpr 63.29 MiB -1 -1 0.11 20676 1 0.01 -1 -1 33160 -1 -1 17 30 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64804 30 32 303 262 1 139 79 17 17 289 -1 unnamed_device 24.8 MiB 0.22 715 63.3 MiB 0.08 0.00 3.13415 -87.8029 -3.13415 3.13415 1.08 0.000154466 0.000128805 0.0113532 0.010541 28 1650 17 6.65987e+06 215526 500653. 1732.36 0.71 0.0368202 0.0325684 21970 115934 -1 1431 17 665 1047 70473 17082 0 0 70473 17082 1047 799 0 0 3955 3241 0 0 5482 4514 0 0 1047 880 0 0 28933 3835 0 0 30009 3813 0 0 1047 0 0 382 477 458 3408 0 0 2.80291 2.80291 -99.3078 -2.80291 0 0 612192. 2118.31 0.25 0.03 0.07 -1 -1 0.25 0.0095444 0.00862359 98 58 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_012.v common 5.35 vpr 63.27 MiB -1 -1 0.10 20892 1 0.01 -1 -1 33140 -1 -1 17 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64788 32 32 276 237 1 166 81 17 17 289 -1 unnamed_device 24.9 MiB 0.23 1005 63.3 MiB 0.04 0.00 2.91589 -97.8016 -2.91589 2.91589 0.89 0.000135059 0.000110668 0.00756473 0.00633749 32 2039 21 6.65987e+06 215526 554710. 1919.41 2.39 0.0650244 0.0554358 22834 132086 -1 1849 19 1035 1394 101853 23397 0 0 101853 23397 1394 1152 0 0 5381 4666 0 0 7850 6322 0 0 1394 1211 0 0 43331 4952 0 0 42503 5094 0 0 1394 0 0 359 324 315 3140 0 0 2.67265 2.67265 -107.841 -2.67265 0 0 701300. 2426.64 0.29 0.03 0.08 -1 -1 0.29 0.0210666 0.0201211 106 31 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_013.v common 3.75 vpr 63.79 MiB -1 -1 0.10 20704 1 0.01 -1 -1 33268 -1 -1 24 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65320 32 32 344 272 1 202 88 17 17 289 -1 unnamed_device 25.3 MiB 0.19 1087 63.8 MiB 0.22 0.01 3.37501 -113.673 -3.37501 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Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64900 31 32 291 243 1 171 82 17 17 289 -1 unnamed_device 24.9 MiB 0.30 832 63.4 MiB 0.05 0.00 3.73355 -112.498 -3.73355 3.73355 0.76 0.000157066 0.000127055 0.00832315 0.00706848 32 2134 22 6.65987e+06 240882 554710. 1919.41 2.46 0.0704757 0.059396 22834 132086 -1 1767 21 1037 1493 114820 27520 0 0 114820 27520 1493 1214 0 0 5802 5007 0 0 9925 7737 0 0 1493 1353 0 0 50369 5776 0 0 45738 6433 0 0 1493 0 0 456 515 418 3884 0 0 3.37791 3.37791 -124.492 -3.37791 0 0 701300. 2426.64 0.28 0.04 0.13 -1 -1 0.28 0.0109487 0.00979177 127 30 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_021.v common 5.29 vpr 63.88 MiB -1 -1 0.11 21096 1 0.02 -1 -1 33372 -1 -1 31 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65416 32 32 342 271 1 179 95 17 17 289 -1 unnamed_device 25.5 MiB 0.04 1026 63.9 MiB 0.07 0.00 3.38856 -108.872 -3.38856 3.38856 0.76 0.00017291 0.000144833 0.0129319 0.0109244 32 2344 21 6.65987e+06 393018 554710. 1919.41 2.49 0.0899494 0.0632606 22834 132086 -1 2099 19 1321 1984 145840 34235 0 0 145840 34235 1984 1537 0 0 7598 6515 0 0 12197 9532 0 0 1984 1688 0 0 60534 7688 0 0 61543 7275 0 0 1984 0 0 663 840 833 6422 0 0 3.47443 3.47443 -125.958 -3.47443 0 0 701300. 2426.64 0.25 0.05 0.08 -1 -1 0.25 0.0122654 0.0109972 135 31 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_022.v common 5.47 vpr 64.05 MiB -1 -1 0.11 20880 1 0.01 -1 -1 33120 -1 -1 23 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65588 32 32 372 300 1 204 87 17 17 289 -1 unnamed_device 25.3 MiB 0.29 1213 64.1 MiB 0.06 0.00 3.36484 -110.526 -3.36484 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0.07 -1 -1 0.22 0.00511333 0.0046466 79 -1 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_026.v common 5.04 vpr 63.55 MiB -1 -1 0.10 20520 1 0.01 -1 -1 33276 -1 -1 30 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65076 32 32 300 245 1 165 94 17 17 289 -1 unnamed_device 25.1 MiB 0.15 952 63.6 MiB 0.08 0.00 3.42395 -99.6489 -3.42395 3.42395 0.76 0.000170818 0.000141545 0.0124132 0.0103692 32 2076 22 6.65987e+06 380340 554710. 1919.41 2.21 0.0728392 0.0620935 22834 132086 -1 1918 21 1165 1816 137759 31884 0 0 137759 31884 1816 1424 0 0 7235 5907 0 0 11384 9149 0 0 1816 1515 0 0 57952 7048 0 0 57556 6841 0 0 1816 0 0 651 823 696 5906 0 0 3.52905 3.52905 -114.611 -3.52905 0 0 701300. 2426.64 0.24 0.04 0.09 -1 -1 0.24 0.0112726 0.0101108 123 21 -1 -1 -1 -1 + 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20596 1 0.01 -1 -1 33384 -1 -1 26 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64968 32 32 338 277 1 179 90 17 17 289 -1 unnamed_device 25.1 MiB 0.10 1088 63.4 MiB 0.09 0.00 3.32969 -104.657 -3.32969 3.32969 0.73 0.000160381 0.000131292 0.0152144 0.0126902 30 2232 21 6.65987e+06 329628 526063. 1820.29 2.52 0.0822586 0.0709234 22546 126617 -1 1957 22 1237 2176 126679 29178 0 0 126679 29178 2176 1500 0 0 7334 5899 0 0 10180 8093 0 0 2176 1651 0 0 53309 5820 0 0 51504 6215 0 0 2176 0 0 939 1137 1093 8107 0 0 3.41085 3.41085 -119.268 -3.41085 0 0 666494. 2306.21 0.25 0.04 0.08 -1 -1 0.25 0.0125135 0.011249 125 47 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_029.v common 4.70 vpr 63.28 MiB -1 -1 0.11 20724 1 0.01 -1 -1 32944 -1 -1 16 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64800 32 32 284 241 1 145 80 17 17 289 -1 unnamed_device 24.8 MiB 0.04 780 63.3 MiB 0.04 0.00 2.29953 -80.5951 -2.29953 2.29953 0.85 0.000135513 0.000111334 0.00750404 0.00637047 28 1885 22 6.65987e+06 202848 500653. 1732.36 1.82 0.0635898 0.0542517 21970 115934 -1 1725 22 1014 1554 126826 28714 0 0 126826 28714 1554 1197 0 0 5867 4978 0 0 8325 6746 0 0 1554 1283 0 0 53693 7734 0 0 55833 6776 0 0 1554 0 0 540 490 590 4414 0 0 2.68565 2.68565 -103.502 -2.68565 0 0 612192. 2118.31 0.27 0.03 0.08 -1 -1 0.27 0.0101816 0.00910348 101 31 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_030.v common 4.64 vpr 63.19 MiB -1 -1 0.12 20852 1 0.01 -1 -1 33248 -1 -1 23 30 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64708 30 32 262 227 1 135 85 17 17 289 -1 unnamed_device 24.7 MiB 0.07 677 63.2 MiB 0.03 0.00 2.39767 -75.3822 -2.39767 2.39767 0.88 0.000134607 0.000111627 0.00587607 0.00494368 26 1770 23 6.65987e+06 291594 477104. 1650.88 1.68 0.0475856 0.0405786 21682 110474 -1 1489 21 1016 1643 108633 26416 0 0 108633 26416 1643 1164 0 0 6123 4953 0 0 9232 7320 0 0 1643 1278 0 0 44913 6042 0 0 45079 5659 0 0 1643 0 0 627 671 715 5438 0 0 2.77991 2.77991 -93.6778 -2.77991 0 0 585099. 2024.56 0.23 0.04 0.07 -1 -1 0.23 0.00986644 0.00879147 97 29 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_031.v common 5.53 vpr 63.12 MiB -1 -1 0.11 20584 1 0.02 -1 -1 33072 -1 -1 23 28 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64640 28 32 260 223 1 140 83 17 17 289 -1 unnamed_device 24.7 MiB 0.03 610 63.1 MiB 0.07 0.00 2.58899 -72.1138 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0.11 20508 1 0.01 -1 -1 33024 -1 -1 17 31 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64616 31 32 279 237 1 161 80 17 17 289 -1 unnamed_device 24.5 MiB 0.25 839 63.1 MiB 0.05 0.00 3.11855 -95.6325 -3.11855 3.11855 0.75 0.000134996 0.000111339 0.010246 0.0086716 26 2145 33 6.65987e+06 215526 477104. 1650.88 2.25 0.0812658 0.0715766 21682 110474 -1 1845 22 1296 1829 125050 31018 0 0 125050 31018 1829 1587 0 0 7059 5718 0 0 10652 8477 0 0 1829 1641 0 0 50366 7167 0 0 53315 6428 0 0 1829 0 0 533 628 781 5295 0 0 3.34497 3.34497 -118.191 -3.34497 0 0 585099. 2024.56 0.21 0.04 0.07 -1 -1 0.21 0.0102582 0.00917342 109 30 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_038.v common 5.27 vpr 64.07 MiB -1 -1 0.11 21052 1 0.01 -1 -1 33200 -1 -1 24 31 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65612 31 32 370 297 1 186 87 17 17 289 -1 unnamed_device 25.4 MiB 0.21 944 64.1 MiB 0.14 0.00 3.29135 -102.08 -3.29135 3.29135 0.91 0.000178269 0.000149188 0.0185296 0.0163189 28 2239 19 6.65987e+06 304272 500653. 1732.36 2.13 0.0898072 0.077273 21970 115934 -1 1982 18 1234 2154 132536 33838 0 0 132536 33838 2154 1534 0 0 7913 6556 0 0 11655 9345 0 0 2154 1679 0 0 57015 7564 0 0 51645 7160 0 0 2154 0 0 920 950 1118 7748 0 0 2.99297 2.99297 -116.779 -2.99297 0 0 612192. 2118.31 0.26 0.08 0.07 -1 -1 0.26 0.0258931 0.0234002 137 57 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_039.v common 4.11 vpr 63.60 MiB -1 -1 0.12 20760 1 0.01 -1 -1 33396 -1 -1 27 31 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65128 31 32 377 302 1 233 90 17 17 289 -1 unnamed_device 25.4 MiB 0.30 1278 63.6 MiB 0.14 0.00 4.69513 -143.575 -4.69513 4.69513 0.80 0.000176803 0.00014576 0.0169476 0.0142902 32 3229 30 6.65987e+06 342306 554710. 1919.41 0.86 0.0639073 0.0554647 22834 132086 -1 2587 22 2259 3351 236181 55721 0 0 236181 55721 3351 2773 0 0 12648 10823 0 0 20083 15092 0 0 3351 2903 0 0 100674 11724 0 0 96074 12406 0 0 3351 0 0 1092 1213 1019 8859 0 0 5.16489 5.16489 -175.542 -5.16489 0 0 701300. 2426.64 0.27 0.06 0.09 -1 -1 0.27 0.0143558 0.0129173 170 60 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_040.v common 7.42 vpr 63.89 MiB -1 -1 0.12 20772 1 0.01 -1 -1 33160 -1 -1 25 31 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65424 31 32 383 305 1 210 88 17 17 289 -1 unnamed_device 25.4 MiB 1.26 979 63.9 MiB 0.06 0.00 3.8685 -115.087 -3.8685 3.8685 0.98 0.000183056 0.000151898 0.0111269 0.00938564 30 2188 26 6.65987e+06 316950 526063. 1820.29 3.40 0.0834993 0.071985 22546 126617 -1 1837 19 1151 1786 94918 22679 0 0 94918 22679 1786 1399 0 0 5938 4608 0 0 7793 6207 0 0 1786 1454 0 0 41796 4080 0 0 35819 4931 0 0 1786 0 0 635 584 500 4949 0 0 3.59377 3.59377 -127.715 -3.59377 0 0 666494. 2306.21 0.24 0.03 0.08 -1 -1 0.24 0.0122972 0.0111157 162 60 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_041.v common 5.84 vpr 63.51 MiB -1 -1 0.11 20852 1 0.00 -1 -1 33232 -1 -1 29 31 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65032 31 32 352 285 1 184 92 17 17 289 -1 unnamed_device 25.1 MiB 0.22 840 63.5 MiB 0.06 0.00 3.49215 -102.722 -3.49215 3.49215 0.72 0.000203404 0.000171428 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1381 2035 184653 41724 0 0 184653 41724 2035 1832 0 0 7837 6505 0 0 12206 9714 0 0 2035 1913 0 0 81513 10877 0 0 79027 10883 0 0 2035 0 0 654 879 952 6240 0 0 3.60251 3.60251 -118.529 -3.60251 0 0 585099. 2024.56 0.21 0.04 0.07 -1 -1 0.21 0.0117694 0.0104151 118 24 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_043.v common 3.94 vpr 63.90 MiB -1 -1 0.13 21064 1 0.02 -1 -1 33316 -1 -1 38 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65432 32 32 457 356 1 223 102 17 17 289 -1 unnamed_device 25.7 MiB 0.23 1158 63.9 MiB 0.10 0.00 4.06967 -130.913 -4.06967 4.06967 0.75 0.000258094 0.000219343 0.0156637 0.0129691 30 2706 20 6.65987e+06 481764 526063. 1820.29 0.99 0.0653114 0.0572024 22546 126617 -1 2251 20 1234 2006 112805 26668 0 0 112805 26668 2006 1471 0 0 6923 5539 0 0 9118 7484 0 0 2006 1575 0 0 47985 5137 0 0 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0.08 -1 -1 0.26 0.0165139 0.0155109 101 24 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_045.v common 6.01 vpr 63.73 MiB -1 -1 0.12 20960 1 0.00 -1 -1 33288 -1 -1 23 31 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65260 31 32 337 267 1 205 86 17 17 289 -1 unnamed_device 25.1 MiB 0.20 1194 63.7 MiB 0.05 0.00 4.03882 -126.169 -4.03882 4.03882 0.75 0.00015976 0.000131213 0.00850881 0.00717825 34 2654 45 6.65987e+06 291594 585099. 2024.56 2.96 0.112787 0.0992309 23122 138558 -1 2372 21 1393 1994 151814 34646 0 0 151814 34646 1994 1605 0 0 7475 6310 0 0 11291 8983 0 0 1994 1698 0 0 64073 8171 0 0 64987 7879 0 0 1994 0 0 601 631 733 5527 0 0 4.11669 4.11669 -142.1 -4.11669 0 0 742403. 2568.87 0.27 0.04 0.10 -1 -1 0.27 0.0124444 0.0112147 142 30 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_046.v common 5.65 vpr 63.54 MiB -1 -1 0.11 20852 1 0.01 -1 -1 33368 -1 -1 33 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65064 32 32 349 284 1 183 97 17 17 289 -1 unnamed_device 25.1 MiB 0.14 1105 63.5 MiB 0.07 0.00 3.1757 -99.4614 -3.1757 3.1757 0.80 0.000177954 0.000145881 0.0102399 0.00855842 28 2494 20 6.65987e+06 418374 500653. 1732.36 3.01 0.0784432 0.0678258 21970 115934 -1 2142 21 1125 2040 140676 31825 0 0 140676 31825 2040 1396 0 0 7480 6188 0 0 11033 8703 0 0 2040 1524 0 0 60799 6736 0 0 57284 7278 0 0 2040 0 0 915 1035 1207 8063 0 0 2.74651 2.74651 -111.21 -2.74651 0 0 612192. 2118.31 0.22 0.04 0.07 -1 -1 0.22 0.0125074 0.0111472 131 50 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_047.v common 5.27 vpr 63.34 MiB -1 -1 0.10 20604 1 0.01 -1 -1 33180 -1 -1 24 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64856 32 32 291 230 1 168 88 17 17 289 -1 unnamed_device 24.9 MiB 0.07 935 63.3 MiB 0.16 0.00 3.27104 -101.948 -3.27104 3.27104 0.80 0.000148054 0.000120857 0.0251542 0.0227502 28 2380 22 6.65987e+06 304272 500653. 1732.36 2.58 0.105204 0.0931754 21970 115934 -1 2056 21 1459 2731 190331 43908 0 0 190331 43908 2731 1794 0 0 9843 8194 0 0 14713 11562 0 0 2731 1905 0 0 80140 10044 0 0 80173 10409 0 0 2731 0 0 1272 1915 1723 11469 0 0 3.57745 3.57745 -120.152 -3.57745 0 0 612192. 2118.31 0.22 0.05 0.07 -1 -1 0.22 0.0116219 0.0104398 123 -1 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_048.v common 5.76 vpr 63.67 MiB -1 -1 0.11 21080 1 0.01 -1 -1 32972 -1 -1 22 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65200 32 32 353 287 1 198 86 17 17 289 -1 unnamed_device 25.2 MiB 0.52 1116 63.7 MiB 0.05 0.00 3.4346 -106.79 -3.4346 3.4346 0.94 0.000161924 0.000133177 0.00829465 0.00704835 26 2797 45 6.65987e+06 278916 477104. 1650.88 2.44 0.104496 0.0868627 21682 110474 -1 2382 30 1543 2161 289120 97592 0 0 289120 97592 2161 1975 0 0 8368 7149 0 0 14004 10863 0 0 2161 2021 0 0 128377 37328 0 0 134049 38256 0 0 2161 0 0 618 881 885 6093 0 0 3.26691 3.26691 -121.153 -3.26691 0 0 585099. 2024.56 0.21 0.07 0.07 -1 -1 0.21 0.0163315 0.0144843 136 52 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_049.v common 5.75 vpr 63.79 MiB -1 -1 0.11 21028 1 0.01 -1 -1 33280 -1 -1 31 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65320 32 32 361 291 1 185 95 17 17 289 -1 unnamed_device 25.3 MiB 0.33 979 63.8 MiB 0.10 0.00 2.9071 -96.889 -2.9071 2.9071 0.74 0.000190296 0.000158823 0.0166464 0.0138795 30 2212 33 6.65987e+06 393018 526063. 1820.29 2.46 0.0905634 0.0776447 22546 126617 -1 1900 14 880 1505 88258 20524 0 0 88258 20524 1505 1054 0 0 5023 3985 0 0 6812 5376 0 0 1505 1127 0 0 35473 4811 0 0 37940 4171 0 0 1505 0 0 625 689 846 6199 0 0 3.01911 3.01911 -112.951 -3.01911 0 0 666494. 2306.21 0.24 0.03 0.08 -1 -1 0.24 0.00967387 0.00875849 132 52 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_050.v common 5.89 vpr 63.72 MiB -1 -1 0.11 20620 1 0.01 -1 -1 33372 -1 -1 36 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65252 32 32 382 305 1 192 100 17 17 289 -1 unnamed_device 25.2 MiB 0.31 1074 63.7 MiB 0.11 0.00 3.47495 -108.457 -3.47495 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fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_055.v common 4.74 vpr 63.31 MiB -1 -1 0.10 20568 1 0.00 -1 -1 33124 -1 -1 24 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64832 32 32 251 219 1 140 88 17 17 289 -1 unnamed_device 24.9 MiB 0.07 768 63.3 MiB 0.09 0.00 2.59064 -80.8644 -2.59064 2.59064 0.87 0.000123791 0.000101051 0.014022 0.0120228 26 1927 20 6.65987e+06 304272 477104. 1650.88 1.70 0.064915 0.0559748 21682 110474 -1 1655 18 821 1291 100377 25223 0 0 100377 25223 1291 1012 0 0 5030 4112 0 0 7437 6075 0 0 1291 1073 0 0 42372 6729 0 0 42956 6222 0 0 1291 0 0 470 610 560 4343 0 0 2.73971 2.73971 -96.1759 -2.73971 0 0 585099. 2024.56 0.23 0.03 0.18 -1 -1 0.23 0.00831121 0.00746166 97 20 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_056.v common 5.69 vpr 63.49 MiB -1 -1 0.10 21016 1 0.01 -1 -1 33168 -1 -1 20 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65012 32 32 341 285 1 187 84 17 17 289 -1 unnamed_device 25.1 MiB 0.14 893 63.5 MiB 0.06 0.00 3.1319 -108.409 -3.1319 3.1319 0.91 0.000157868 0.000130215 0.0108074 0.00903458 32 2445 25 6.65987e+06 253560 554710. 1919.41 2.55 0.0873086 0.0727067 22834 132086 -1 2098 22 1582 2242 183923 42429 0 0 183923 42429 2242 1943 0 0 8759 7628 0 0 13978 10728 0 0 2242 1996 0 0 77041 10513 0 0 79661 9621 0 0 2242 0 0 660 610 546 5378 0 0 3.29077 3.29077 -128.088 -3.29077 0 0 701300. 2426.64 0.25 0.05 0.08 -1 -1 0.25 0.013096 0.0117326 125 62 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_057.v common 4.26 vpr 63.91 MiB -1 -1 0.13 21220 1 0.02 -1 -1 33396 -1 -1 28 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65440 32 32 387 293 1 234 92 17 17 289 -1 unnamed_device 25.6 MiB 0.14 1365 63.9 MiB 0.12 0.00 4.23387 -130.947 -4.23387 4.23387 0.93 0.000214638 0.00018149 0.0195064 0.0165456 30 2803 26 6.65987e+06 354984 526063. 1820.29 0.79 0.0604969 0.0524821 22546 126617 -1 2245 19 1330 2119 111342 27307 0 0 111342 27307 2119 1520 0 0 7221 5737 0 0 9381 7656 0 0 2119 1673 0 0 43958 5740 0 0 46544 4981 0 0 2119 0 0 789 697 757 6280 0 0 4.19488 4.19488 -145.288 -4.19488 0 0 666494. 2306.21 0.24 0.08 0.08 -1 -1 0.24 0.0165201 0.0141134 168 28 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_058.v common 4.17 vpr 63.58 MiB -1 -1 0.11 20616 1 0.01 -1 -1 33216 -1 -1 31 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65108 32 32 340 270 1 181 95 17 17 289 -1 unnamed_device 25.2 MiB 0.20 950 63.6 MiB 0.12 0.00 3.56446 -108.073 -3.56446 3.56446 0.89 0.000248614 0.000207731 0.00979522 0.008278 32 2199 22 6.65987e+06 393018 554710. 1919.41 1.02 0.0407455 0.0349852 22834 132086 -1 1904 22 1188 1902 138987 33371 0 0 138987 33371 1902 1353 0 0 7443 6324 0 0 11792 9282 0 0 1902 1504 0 0 57797 7382 0 0 58151 7526 0 0 1902 0 0 714 755 819 6440 0 0 3.12451 3.12451 -120.082 -3.12451 0 0 701300. 2426.64 0.25 0.08 0.09 -1 -1 0.25 0.0128449 0.0114788 133 31 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_059.v common 3.74 vpr 63.45 MiB -1 -1 0.11 20632 1 0.01 -1 -1 33192 -1 -1 26 30 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64976 30 32 278 235 1 148 88 17 17 289 -1 unnamed_device 24.8 MiB 0.05 797 63.5 MiB 0.08 0.00 2.54444 -82.4839 -2.54444 2.54444 0.79 0.00013574 0.000111595 0.0131764 0.011006 28 1876 43 6.65987e+06 329628 500653. 1732.36 0.92 0.0493344 0.0422501 21970 115934 -1 1731 22 1182 2002 158026 36347 0 0 158026 36347 2002 1370 0 0 7358 6146 0 0 11368 9080 0 0 2002 1550 0 0 66604 9377 0 0 68692 8824 0 0 2002 0 0 820 1009 1140 7855 0 0 2.72371 2.72371 -98.6145 -2.72371 0 0 612192. 2118.31 0.24 0.04 0.10 -1 -1 0.24 0.0100244 0.0089249 104 29 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_060.v common 8.03 vpr 63.89 MiB -1 -1 0.13 21112 1 0.01 -1 -1 33412 -1 -1 25 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65424 32 32 431 332 1 235 89 17 17 289 -1 unnamed_device 25.7 MiB 0.31 1389 63.9 MiB 0.09 0.00 5.14349 -155.118 -5.14349 5.14349 0.97 0.000221378 0.000184897 0.0158124 0.0132605 28 3281 23 6.65987e+06 316950 500653. 1732.36 4.74 0.118779 0.105247 21970 115934 -1 2806 21 1863 2627 191929 43383 0 0 191929 43383 2627 2205 0 0 9697 7827 0 0 13859 11085 0 0 2627 2339 0 0 80887 10064 0 0 82232 9863 0 0 2627 0 0 764 873 1026 7412 0 0 5.36894 5.36894 -180.141 -5.36894 0 0 612192. 2118.31 0.22 0.06 0.07 -1 -1 0.22 0.015517 0.0139764 168 62 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_061.v common 4.18 vpr 63.61 MiB -1 -1 0.11 20644 1 0.01 -1 -1 33152 -1 -1 32 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65140 32 32 336 268 1 174 96 17 17 289 -1 unnamed_device 25.0 MiB 0.28 868 63.6 MiB 0.07 0.00 3.54535 -106.254 -3.54535 3.54535 0.94 0.000161522 0.000133263 0.0110503 0.00920876 32 2135 22 6.65987e+06 405696 554710. 1919.41 0.69 0.0402257 0.0344624 22834 132086 -1 1857 19 1275 1870 120488 29530 0 0 120488 29530 1870 1386 0 0 7058 5865 0 0 11016 8619 0 0 1870 1513 0 0 48854 6177 0 0 49820 5970 0 0 1870 0 0 595 706 721 5924 0 0 3.56231 3.56231 -122.353 -3.56231 0 0 701300. 2426.64 0.25 0.03 0.08 -1 -1 0.25 0.0112014 0.010039 130 31 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_062.v common 3.31 vpr 62.96 MiB -1 -1 0.10 20468 1 0.01 -1 -1 33052 -1 -1 23 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64472 32 32 231 199 1 140 87 17 17 289 -1 unnamed_device 24.5 MiB 0.03 758 63.0 MiB 0.06 0.00 2.48032 -74.2415 -2.48032 2.48032 0.74 0.000122558 0.000100216 0.0094439 0.00791991 28 1977 22 6.65987e+06 291594 500653. 1732.36 0.81 0.0350588 0.0303522 21970 115934 -1 1711 19 952 1603 127882 29775 0 0 127882 29775 1603 1246 0 0 6023 4987 0 0 8760 6989 0 0 1603 1327 0 0 55316 7679 0 0 54577 7547 0 0 1603 0 0 651 850 1054 6396 0 0 2.93479 2.93479 -97.5474 -2.93479 0 0 612192. 2118.31 0.28 0.04 0.07 -1 -1 0.28 0.00889808 0.00804875 100 -1 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_063.v common 5.93 vpr 63.80 MiB -1 -1 0.10 20832 1 0.02 -1 -1 33220 -1 -1 34 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65332 32 32 349 273 1 191 98 17 17 289 -1 unnamed_device 25.4 MiB 0.11 991 63.8 MiB 0.07 0.00 4.55326 -107.965 -4.55326 4.55326 0.81 0.000187701 0.000157305 0.0118579 0.010016 32 2630 24 6.65987e+06 431052 554710. 1919.41 2.99 0.128094 0.114465 22834 132086 -1 2084 20 1361 2489 160827 38734 0 0 160827 38734 2489 1588 0 0 9313 7666 0 0 14682 11218 0 0 2489 1757 0 0 67093 8184 0 0 64761 8321 0 0 2489 0 0 1128 1907 1912 12956 0 0 4.55822 4.55822 -129.593 -4.55822 0 0 701300. 2426.64 0.25 0.04 0.08 -1 -1 0.25 0.0127453 0.011327 139 26 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_064.v common 5.30 vpr 63.02 MiB -1 -1 0.09 20296 1 0.01 -1 -1 33248 -1 -1 20 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64528 32 32 247 207 1 147 84 17 17 289 -1 unnamed_device 24.6 MiB 0.08 849 63.0 MiB 0.07 0.00 2.57564 -85.1096 -2.57564 2.57564 0.75 0.000124148 0.000101743 0.0108133 0.00897469 30 1878 22 6.65987e+06 253560 526063. 1820.29 2.30 0.0581855 0.0499433 22546 126617 -1 1627 19 935 1588 97255 22793 0 0 97255 22793 1588 1153 0 0 5571 4600 0 0 7375 6062 0 0 1588 1259 0 0 41440 4873 0 0 39693 4846 0 0 1588 0 0 653 635 716 5374 0 0 2.63051 2.63051 -102.219 -2.63051 0 0 666494. 2306.21 0.24 0.03 0.08 -1 -1 0.24 0.00888959 0.00799914 104 -1 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_065.v common 5.43 vpr 63.36 MiB -1 -1 0.10 20448 1 0.01 -1 -1 33248 -1 -1 33 30 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64880 30 32 278 235 1 147 95 17 17 289 -1 unnamed_device 24.8 MiB 0.12 870 63.4 MiB 0.09 0.00 2.98169 -84.6118 -2.98169 2.98169 1.31 0.000132778 0.000109351 0.0119379 0.00985641 28 1853 21 6.65987e+06 418374 500653. 1732.36 2.09 0.0601775 0.0509674 21970 115934 -1 1685 23 899 1605 119563 26476 0 0 119563 26476 1605 1067 0 0 6029 5002 0 0 9194 7209 0 0 1605 1215 0 0 51706 5841 0 0 49424 6142 0 0 1605 0 0 706 951 934 6906 0 0 2.74625 2.74625 -99.0265 -2.74625 0 0 612192. 2118.31 0.23 0.03 0.09 -1 -1 0.23 0.0100214 0.00890921 105 29 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_066.v common 4.10 vpr 63.91 MiB -1 -1 0.12 20948 1 0.01 -1 -1 33200 -1 -1 24 29 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65448 29 32 355 287 1 198 85 17 17 289 -1 unnamed_device 25.2 MiB 0.22 905 63.9 MiB 0.10 0.00 3.37101 -98.2294 -3.37101 3.37101 0.85 0.000162538 0.000133459 0.0189311 0.0159117 30 2579 27 6.65987e+06 304272 526063. 1820.29 0.94 0.0544701 0.0467008 22546 126617 -1 1895 22 1282 1965 120427 29362 0 0 120427 29362 1965 1618 0 0 6758 5465 0 0 9136 7389 0 0 1965 1657 0 0 50769 6563 0 0 49834 6670 0 0 1965 0 0 683 690 624 5368 0 0 3.16191 3.16191 -108.615 -3.16191 0 0 666494. 2306.21 0.33 0.11 0.08 -1 -1 0.33 0.0343253 0.0327108 138 56 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_067.v common 5.78 vpr 63.73 MiB -1 -1 0.12 20812 1 0.01 -1 -1 33032 -1 -1 24 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65260 32 32 358 289 1 175 88 17 17 289 -1 unnamed_device 25.3 MiB 0.17 1007 63.7 MiB 0.04 0.00 3.5135 -109.739 -3.5135 3.5135 0.75 0.000172925 0.000143116 0.00739235 0.00637193 32 2142 21 6.65987e+06 304272 554710. 1919.41 2.61 0.0729352 0.062717 22834 132086 -1 1955 24 1416 2198 155256 36237 0 0 155256 36237 2198 1754 0 0 8290 6887 0 0 12979 10150 0 0 2198 1849 0 0 64741 7648 0 0 64850 7949 0 0 2198 0 0 782 839 1028 6967 0 0 3.69551 3.69551 -133.157 -3.69551 0 0 701300. 2426.64 0.26 0.04 0.14 -1 -1 0.26 0.0140325 0.0124823 130 51 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_068.v common 3.73 vpr 63.58 MiB -1 -1 0.11 20632 1 0.01 -1 -1 33164 -1 -1 27 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65108 32 32 353 285 1 181 91 17 17 289 -1 unnamed_device 25.2 MiB 0.19 1113 63.6 MiB 0.08 0.00 3.63564 -112.148 -3.63564 3.63564 0.89 0.000167518 0.000137982 0.0128567 0.0108059 28 2615 21 6.65987e+06 342306 500653. 1732.36 0.76 0.0484158 0.0419502 21970 115934 -1 2297 21 1366 2484 169015 38132 0 0 169015 38132 2484 1732 0 0 8799 7300 0 0 13224 10186 0 0 2484 2032 0 0 73848 8052 0 0 68176 8830 0 0 2484 0 0 1118 1393 1476 9815 0 0 3.64431 3.64431 -129.676 -3.64431 0 0 612192. 2118.31 0.23 0.04 0.07 -1 -1 0.23 0.0131334 0.0118035 132 48 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_069.v common 5.49 vpr 63.26 MiB -1 -1 0.11 20672 1 0.00 -1 -1 33236 -1 -1 16 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64780 32 32 276 237 1 159 80 17 17 289 -1 unnamed_device 24.7 MiB 0.34 822 63.3 MiB 0.06 0.00 3.5308 -102.471 -3.5308 3.5308 0.86 0.000130672 0.000106467 0.0111503 0.00927958 32 2073 22 6.65987e+06 202848 554710. 1919.41 2.43 0.067855 0.0587503 22834 132086 -1 1684 20 930 1235 96448 22570 0 0 96448 22570 1235 1101 0 0 4730 3890 0 0 6871 5460 0 0 1235 1133 0 0 40473 5677 0 0 41904 5309 0 0 1235 0 0 305 316 293 2773 0 0 3.38517 3.38517 -113.447 -3.38517 0 0 701300. 2426.64 0.26 0.03 0.08 -1 -1 0.26 0.00960311 0.00860672 103 31 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_070.v common 3.65 vpr 63.46 MiB -1 -1 0.12 20856 1 0.02 -1 -1 33172 -1 -1 19 31 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64980 31 32 319 272 1 168 82 17 17 289 -1 unnamed_device 24.9 MiB 0.17 910 63.5 MiB 0.07 0.00 2.85458 -96.8905 -2.85458 2.85458 0.74 0.000144791 0.000118224 0.0121771 0.0102595 32 2268 24 6.65987e+06 240882 554710. 1919.41 0.73 0.0413062 0.0354483 22834 132086 -1 1915 19 1293 1936 150620 34905 0 0 150620 34905 1936 1619 0 0 7424 6416 0 0 11992 9370 0 0 1936 1689 0 0 63231 8236 0 0 64101 7575 0 0 1936 0 0 643 709 503 5077 0 0 2.92845 2.92845 -111.949 -2.92845 0 0 701300. 2426.64 0.42 0.04 0.08 -1 -1 0.42 0.0104971 0.00935643 111 60 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_071.v common 5.62 vpr 63.41 MiB -1 -1 0.12 21112 1 0.01 -1 -1 33208 -1 -1 33 30 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64932 30 32 329 273 1 166 95 17 17 289 -1 unnamed_device 24.9 MiB 0.25 917 63.4 MiB 0.07 0.00 2.72184 -81.6865 -2.72184 2.72184 0.74 0.000153081 0.00012519 0.0121403 0.0100365 32 2137 21 6.65987e+06 418374 554710. 1919.41 2.81 0.084252 0.0724801 22834 132086 -1 1833 21 1025 1895 126216 29465 0 0 126216 29465 1895 1203 0 0 7159 5991 0 0 10979 8520 0 0 1895 1390 0 0 52141 6270 0 0 52147 6091 0 0 1895 0 0 870 1332 1390 9143 0 0 2.52119 2.52119 -91.8377 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20836 1 0.00 -1 -1 33128 -1 -1 20 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64876 32 32 335 282 1 184 84 17 17 289 -1 unnamed_device 24.9 MiB 0.16 1076 63.4 MiB 0.07 0.00 2.94464 -104.132 -2.94464 2.94464 0.71 0.000165287 0.000138124 0.0120318 0.0100476 28 2496 20 6.65987e+06 253560 500653. 1732.36 2.44 0.0836653 0.07176 21970 115934 -1 2217 20 1237 1803 138305 30442 0 0 138305 30442 1803 1482 0 0 6326 5117 0 0 9325 7305 0 0 1803 1545 0 0 60062 7660 0 0 58986 7333 0 0 1803 0 0 566 580 547 4628 0 0 3.21171 3.21171 -129.814 -3.21171 0 0 612192. 2118.31 0.33 0.08 0.07 -1 -1 0.33 0.0152182 0.0140175 120 62 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_075.v common 4.95 vpr 63.45 MiB -1 -1 0.12 20716 1 0.01 -1 -1 33144 -1 -1 32 31 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64972 31 32 293 230 1 175 95 17 17 289 -1 unnamed_device 25.0 MiB 0.07 1043 63.4 MiB 0.06 0.00 3.57527 -104.665 -3.57527 3.57527 0.74 0.000149522 0.000123742 0.00938743 0.00788315 26 2598 24 6.65987e+06 405696 477104. 1650.88 1.91 0.062294 0.0533361 21682 110474 -1 2316 22 1495 2633 214788 48493 0 0 214788 48493 2633 2042 0 0 10190 8636 0 0 16045 12757 0 0 2633 2277 0 0 90969 11285 0 0 92318 11496 0 0 2633 0 0 1138 1506 1606 10301 0 0 3.81383 3.81383 -126.3 -3.81383 0 0 585099. 2024.56 0.32 0.05 0.07 -1 -1 0.32 0.0105699 0.00943302 127 -1 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_076.v common 7.68 vpr 63.74 MiB -1 -1 0.12 21136 1 0.02 -1 -1 33216 -1 -1 22 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65272 32 32 350 275 1 209 86 17 17 289 -1 unnamed_device 25.1 MiB 0.27 1218 63.7 MiB 0.07 0.00 4.10541 -132.01 -4.10541 4.10541 0.87 0.000170733 0.000141001 0.0109112 0.00923146 28 3207 22 6.65987e+06 278916 500653. 1732.36 4.60 0.0994934 0.0805002 21970 115934 -1 2657 22 1592 2348 207047 52439 0 0 207047 52439 2348 2026 0 0 8652 7180 0 0 12667 10162 0 0 2348 2088 0 0 93904 14941 0 0 87128 16042 0 0 2348 0 0 756 732 650 6028 0 0 3.97311 3.97311 -150.318 -3.97311 0 0 612192. 2118.31 0.24 0.05 0.08 -1 -1 0.24 0.0135992 0.0121559 144 31 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_077.v common 6.76 vpr 63.84 MiB -1 -1 0.11 20644 1 0.01 -1 -1 33140 -1 -1 32 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65376 32 32 385 308 1 185 96 17 17 289 -1 unnamed_device 25.4 MiB 0.35 881 63.8 MiB 0.08 0.00 3.92821 -107.518 -3.92821 3.92821 0.93 0.000198054 0.000164093 0.0122832 0.0100551 28 2671 25 6.65987e+06 405696 500653. 1732.36 3.51 0.091397 0.0790564 21970 115934 -1 2143 21 1221 2249 150899 36628 0 0 150899 36628 2249 1681 0 0 8119 6671 0 0 11732 9331 0 0 2249 1813 0 0 62863 9036 0 0 63687 8096 0 0 2249 0 0 1028 1235 1216 9044 0 0 3.98771 3.98771 -134.802 -3.98771 0 0 612192. 2118.31 0.22 0.04 0.07 -1 -1 0.22 0.0126874 0.0113068 142 62 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_078.v common 5.62 vpr 63.85 MiB -1 -1 0.13 20828 1 0.01 -1 -1 33352 -1 -1 37 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65384 32 32 387 309 1 190 101 17 17 289 -1 unnamed_device 25.3 MiB 0.22 1143 63.9 MiB 0.10 0.00 3.25355 -109.31 -3.25355 3.25355 0.84 0.000229583 0.000193312 0.0130209 0.0109065 30 2410 22 6.65987e+06 469086 526063. 1820.29 2.55 0.0936077 0.0817697 22546 126617 -1 2120 17 1057 1960 98865 24162 0 0 98865 24162 1960 1313 0 0 6830 5372 0 0 8559 7175 0 0 1960 1480 0 0 41173 4289 0 0 38383 4533 0 0 1960 0 0 903 930 835 7534 0 0 3.28671 3.28671 -125.203 -3.28671 0 0 666494. 2306.21 0.24 0.03 0.08 -1 -1 0.24 0.011558 0.0103498 140 62 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_079.v common 5.44 vpr 63.10 MiB -1 -1 0.11 20584 1 0.01 -1 -1 33104 -1 -1 19 30 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64612 30 32 272 232 1 147 81 17 17 289 -1 unnamed_device 24.6 MiB 0.17 835 63.1 MiB 0.07 0.00 2.90104 -91.6576 -2.90104 2.90104 0.74 0.000134268 0.000110199 0.0120024 0.0100111 32 2009 17 6.65987e+06 240882 554710. 1919.41 2.43 0.0698058 0.0610842 22834 132086 -1 1713 20 1019 1744 138072 30983 0 0 138072 30983 1744 1404 0 0 6737 5597 0 0 10349 8056 0 0 1744 1511 0 0 57834 7563 0 0 59664 6852 0 0 1744 0 0 725 892 722 5915 0 0 2.51705 2.51705 -97.4052 -2.51705 0 0 701300. 2426.64 0.25 0.04 0.09 -1 -1 0.25 0.00999224 0.00891921 105 29 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_080.v common 5.85 vpr 63.68 MiB -1 -1 0.12 20780 1 0.01 -1 -1 33028 -1 -1 21 30 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65208 30 32 375 299 1 187 83 17 17 289 -1 unnamed_device 25.1 MiB 0.21 882 63.7 MiB 0.07 0.00 3.77847 -108.414 -3.77847 3.77847 0.88 0.00018308 0.000151702 0.0143258 0.0120851 30 2279 26 6.65987e+06 266238 526063. 1820.29 2.53 0.10054 0.0856792 22546 126617 -1 1710 23 1351 2168 114854 29366 0 0 114854 29366 2168 1639 0 0 7466 5936 0 0 9705 8013 0 0 2168 1781 0 0 47286 5659 0 0 46061 6338 0 0 2168 0 0 817 689 903 6673 0 0 3.62231 3.62231 -126.616 -3.62231 0 0 666494. 2306.21 0.35 0.08 0.08 -1 -1 0.35 0.0215394 0.0201283 137 58 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_081.v common 5.41 vpr 63.82 MiB -1 -1 0.12 21048 1 0.01 -1 -1 33148 -1 -1 24 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65348 32 32 340 270 1 200 88 17 17 289 -1 unnamed_device 25.3 MiB 0.31 1286 63.8 MiB 0.06 0.00 3.8156 -118.226 -3.8156 3.8156 0.82 0.000182963 0.000152257 0.0100058 0.00838275 26 3005 41 6.65987e+06 304272 477104. 1650.88 2.44 0.0866363 0.0745771 21682 110474 -1 2509 22 1750 2757 234845 49792 0 0 234845 49792 2757 2096 0 0 10337 8441 0 0 15429 11960 0 0 2757 2216 0 0 102995 11989 0 0 100570 13090 0 0 2757 0 0 1007 1761 1588 11095 0 0 3.67751 3.67751 -134.16 -3.67751 0 0 585099. 2024.56 0.21 0.05 0.07 -1 -1 0.21 0.0124818 0.0111432 138 31 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_082.v common 4.22 vpr 63.67 MiB -1 -1 0.12 20888 1 0.02 -1 -1 33208 -1 -1 28 31 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65196 31 32 340 275 1 195 91 17 17 289 -1 unnamed_device 25.3 MiB 0.30 1100 63.7 MiB 0.09 0.00 4.10296 -123.19 -4.10296 4.10296 1.19 0.000163892 0.000134796 0.00961907 0.00811201 28 2581 23 6.65987e+06 354984 500653. 1732.36 0.80 0.0467855 0.0408019 21970 115934 -1 2317 20 1295 1959 142404 32685 0 0 142404 32685 1959 1529 0 0 7252 6022 0 0 10701 8699 0 0 1959 1597 0 0 58368 7795 0 0 62165 7043 0 0 1959 0 0 664 794 754 6147 0 0 4.28603 4.28603 -145.842 -4.28603 0 0 612192. 2118.31 0.23 0.04 0.07 -1 -1 0.23 0.0127789 0.011529 146 43 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_083.v common 6.53 vpr 63.55 MiB -1 -1 0.13 21132 1 0.01 -1 -1 33200 -1 -1 31 30 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65076 30 32 377 310 1 177 93 17 17 289 -1 unnamed_device 25.1 MiB 0.97 924 63.6 MiB 0.09 0.00 3.34201 -101.96 -3.34201 3.34201 0.76 0.000168995 0.000137939 0.0152695 0.012792 28 2378 24 6.65987e+06 393018 500653. 1732.36 2.82 0.100342 0.0859253 21970 115934 -1 2001 19 1441 2378 166633 38461 0 0 166633 38461 2378 1807 0 0 8689 7081 0 0 12633 10064 0 0 2378 1909 0 0 68841 9480 0 0 71714 8120 0 0 2378 0 0 937 1090 1169 8262 0 0 3.03517 3.03517 -113.273 -3.03517 0 0 612192. 2118.31 0.22 0.04 0.07 -1 -1 0.22 0.0124838 0.0111908 133 78 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_084.v common 3.99 vpr 63.60 MiB -1 -1 0.11 20868 1 0.01 -1 -1 33152 -1 -1 20 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65128 32 32 365 294 1 185 84 17 17 289 -1 unnamed_device 25.2 MiB 0.24 983 63.6 MiB 0.09 0.00 3.76955 -109.292 -3.76955 3.76955 0.91 0.000165179 0.000135427 0.0167156 0.0139215 32 2696 24 6.65987e+06 253560 554710. 1919.41 0.75 0.0511111 0.0438195 22834 132086 -1 2265 22 1714 3031 225865 52534 0 0 225865 52534 3031 2503 0 0 11427 9709 0 0 18035 13903 0 0 3031 2651 0 0 96162 11849 0 0 94179 11919 0 0 3031 0 0 1317 1454 1588 10576 0 0 3.71631 3.71631 -128.955 -3.71631 0 0 701300. 2426.64 0.25 0.09 0.09 -1 -1 0.25 0.0221072 0.0205227 133 54 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_085.v common 5.22 vpr 63.80 MiB -1 -1 0.12 21012 1 0.02 -1 -1 33248 -1 -1 29 29 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65336 29 32 378 310 1 177 90 17 17 289 -1 unnamed_device 25.4 MiB 0.30 871 63.8 MiB 0.06 0.00 3.57869 -99.9377 -3.57869 3.57869 0.84 0.000172148 0.000141488 0.0113178 0.00960154 26 2335 21 6.65987e+06 367662 477104. 1650.88 2.00 0.0765345 0.0655594 21682 110474 -1 1971 23 1467 2269 165407 39747 0 0 165407 39747 2269 1796 0 0 8574 7316 0 0 12914 10206 0 0 2269 1881 0 0 69282 9498 0 0 70099 9050 0 0 2269 0 0 802 943 854 6856 0 0 3.26471 3.26471 -116.297 -3.26471 0 0 585099. 2024.56 0.22 0.05 0.10 -1 -1 0.22 0.0150724 0.0131218 131 79 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_086.v common 3.34 vpr 63.13 MiB -1 -1 0.11 20532 1 0.01 -1 -1 33064 -1 -1 15 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64644 32 32 243 205 1 139 79 17 17 289 -1 unnamed_device 24.8 MiB 0.07 756 63.1 MiB 0.07 0.00 2.87075 -89.3775 -2.87075 2.87075 0.74 0.000119798 9.7849e-05 0.0121872 0.0102719 28 1723 20 6.65987e+06 190170 500653. 1732.36 0.67 0.0349906 0.0301221 21970 115934 -1 1487 19 793 1183 87564 20785 0 0 87564 20785 1183 951 0 0 4509 3712 0 0 6313 5242 0 0 1183 1001 0 0 38137 4871 0 0 36239 5008 0 0 1183 0 0 390 493 384 3338 0 0 2.56325 2.56325 -99.3836 -2.56325 0 0 612192. 2118.31 0.23 0.03 0.08 -1 -1 0.23 0.00875472 0.00789613 96 -1 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_087.v common 5.46 vpr 63.74 MiB -1 -1 0.11 20864 1 0.02 -1 -1 33416 -1 -1 30 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65272 32 32 373 302 1 176 94 17 17 289 -1 unnamed_device 25.4 MiB 0.30 1050 63.7 MiB 0.06 0.00 3.45695 -110.861 -3.45695 3.45695 0.73 0.000177893 0.000145634 0.0093499 0.00787063 28 2397 40 6.65987e+06 380340 500653. 1732.36 2.71 0.15761 0.142351 21970 115934 -1 2131 18 1196 1982 135514 31370 0 0 135514 31370 1982 1508 0 0 7418 5990 0 0 10532 8558 0 0 1982 1586 0 0 57574 6522 0 0 56026 7206 0 0 1982 0 0 786 933 953 6936 0 0 3.73871 3.73871 -131.664 -3.73871 0 0 612192. 2118.31 0.21 0.04 0.07 -1 -1 0.21 0.0112715 0.010128 130 62 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_088.v common 6.11 vpr 63.94 MiB -1 -1 0.12 21084 1 0.01 -1 -1 33000 -1 -1 20 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65472 32 32 397 314 1 196 84 17 17 289 -1 unnamed_device 25.4 MiB 0.22 1074 63.9 MiB 0.07 0.00 3.74961 -118.449 -3.74961 3.74961 1.15 0.000177433 0.000146521 0.0131792 0.0110118 32 2569 23 6.65987e+06 253560 554710. 1919.41 2.53 0.085573 0.0729226 22834 132086 -1 2236 21 1860 3011 208914 48764 0 0 208914 48764 3011 2244 0 0 11319 9811 0 0 17688 13693 0 0 3011 2413 0 0 86767 10438 0 0 87118 10165 0 0 3011 0 0 1151 1051 1213 9364 0 0 3.64877 3.64877 -140.027 -3.64877 0 0 701300. 2426.64 0.49 0.07 0.09 -1 -1 0.49 0.0152494 0.0136103 147 62 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_089.v common 5.80 vpr 63.61 MiB -1 -1 0.10 20600 1 0.01 -1 -1 33132 -1 -1 19 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65136 32 32 269 231 1 170 83 17 17 289 -1 unnamed_device 25.0 MiB 0.19 1013 63.6 MiB 0.06 0.00 3.19629 -98.5902 -3.19629 3.19629 0.86 0.000128017 0.000104724 0.0103517 0.00866701 26 2312 28 6.65987e+06 240882 477104. 1650.88 3.04 0.0824809 0.0727072 21682 110474 -1 2095 22 1221 1619 151361 33323 0 0 151361 33323 1619 1431 0 0 6371 5258 0 0 9685 7879 0 0 1619 1471 0 0 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0.13 20804 1 0.01 -1 -1 33404 -1 -1 36 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65576 32 32 349 260 1 204 100 17 17 289 -1 unnamed_device 25.3 MiB 0.11 1199 64.0 MiB 0.10 0.00 4.29287 -118.291 -4.29287 4.29287 0.76 0.000184432 0.000146472 0.016435 0.0136162 32 2930 24 6.65987e+06 456408 554710. 1919.41 3.59 0.1203 0.105178 22834 132086 -1 2478 17 1575 2763 220341 49470 0 0 220341 49470 2763 2003 0 0 10521 8996 0 0 16588 12961 0 0 2763 2200 0 0 92955 12137 0 0 94751 11173 0 0 2763 0 0 1188 1526 1416 10835 0 0 4.45522 4.45522 -141.128 -4.45522 0 0 701300. 2426.64 0.24 0.05 0.08 -1 -1 0.24 0.0116702 0.0105482 153 -1 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_094.v common 4.07 vpr 63.30 MiB -1 -1 0.12 21036 1 0.01 -1 -1 33176 -1 -1 31 30 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64824 30 32 316 264 1 162 93 17 17 289 -1 unnamed_device 24.9 MiB 0.18 737 63.3 MiB 0.05 0.00 2.60458 -77.596 -2.60458 2.60458 0.78 0.000182466 0.000151287 0.00763564 0.00638614 26 2301 22 6.65987e+06 393018 477104. 1650.88 0.98 0.0395154 0.0340981 21682 110474 -1 1884 22 1380 2312 164911 41104 0 0 164911 41104 2312 1777 0 0 8727 7393 0 0 13136 10368 0 0 2312 1878 0 0 69356 10043 0 0 69068 9645 0 0 2312 0 0 932 1070 1232 8122 0 0 2.87265 2.87265 -102.753 -2.87265 0 0 585099. 2024.56 0.21 0.04 0.07 -1 -1 0.21 0.0111037 0.0098766 120 47 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_095.v common 5.11 vpr 63.07 MiB -1 -1 0.10 20536 1 0.01 -1 -1 33216 -1 -1 21 27 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64584 27 32 255 219 1 132 80 17 17 289 -1 unnamed_device 24.7 MiB 0.04 641 63.1 MiB 0.07 0.00 2.7331 -77.2835 -2.7331 2.7331 0.82 0.000122497 9.9169e-05 0.0169303 0.0151822 28 1583 23 6.65987e+06 266238 500653. 1732.36 2.25 0.0699121 0.0603202 21970 115934 -1 1362 20 1038 1508 116390 27242 0 0 116390 27242 1508 1294 0 0 5690 4853 0 0 8445 6911 0 0 1508 1336 0 0 50991 6248 0 0 48248 6600 0 0 1508 0 0 470 508 491 4135 0 0 2.73097 2.73097 -90.2119 -2.73097 0 0 612192. 2118.31 0.22 0.09 0.08 -1 -1 0.22 0.00957732 0.0085766 97 26 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_096.v common 3.79 vpr 63.98 MiB -1 -1 0.11 21080 1 0.01 -1 -1 33220 -1 -1 26 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65512 32 32 421 327 1 232 90 17 17 289 -1 unnamed_device 25.8 MiB 0.13 1442 64.0 MiB 0.10 0.00 3.4163 -115.859 -3.4163 3.4163 0.76 0.000203567 0.000168292 0.0188256 0.015747 32 3755 30 6.65987e+06 329628 554710. 1919.41 0.84 0.0601215 0.0515938 22834 132086 -1 3107 22 2228 3640 288609 63937 0 0 288609 63937 3640 2815 0 0 13539 11687 0 0 21833 16262 0 0 3640 3199 0 0 129315 14220 0 0 116642 15754 0 0 3640 0 0 1412 1747 1689 11880 0 0 3.85977 3.85977 -136.908 -3.85977 0 0 701300. 2426.64 0.26 0.06 0.09 -1 -1 0.26 0.0152473 0.0136006 170 62 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_097.v common 6.25 vpr 63.73 MiB -1 -1 0.12 20752 1 0.01 -1 -1 33164 -1 -1 21 31 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65260 31 32 365 296 1 194 84 17 17 289 -1 unnamed_device 25.1 MiB 1.00 995 63.7 MiB 0.07 0.00 4.27986 -124.137 -4.27986 4.27986 0.76 0.00016522 0.000136092 0.0129775 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common 5.67 vpr 63.93 MiB -1 -1 0.11 20860 1 0.01 -1 -1 33216 -1 -1 24 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65460 32 32 350 275 1 214 88 17 17 289 -1 unnamed_device 25.2 MiB 0.13 1406 63.9 MiB 0.18 0.00 3.8505 -125.328 -3.8505 3.8505 0.99 0.000202459 0.000170729 0.0361419 0.0337562 30 2920 23 6.65987e+06 304272 526063. 1820.29 2.32 0.106279 0.0942613 22546 126617 -1 2563 20 1589 2419 168681 36028 0 0 168681 36028 2419 1796 0 0 8202 6637 0 0 11205 8895 0 0 2419 2000 0 0 71192 8767 0 0 73244 7933 0 0 2419 0 0 830 869 824 6602 0 0 3.85257 3.85257 -140.414 -3.85257 0 0 666494. 2306.21 0.39 0.06 0.08 -1 -1 0.39 0.0233129 0.022049 147 31 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_103.v common 5.95 vpr 63.75 MiB -1 -1 0.13 20876 1 0.01 -1 -1 33104 -1 -1 34 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65276 32 32 386 307 1 195 98 17 17 289 -1 unnamed_device 25.2 MiB 0.38 1103 63.7 MiB 0.11 0.00 3.71641 -117.038 -3.71641 3.71641 1.05 0.000232347 0.000196737 0.0146347 0.0122777 26 2916 28 6.65987e+06 431052 477104. 1650.88 2.15 0.0959055 0.0821114 21682 110474 -1 2309 23 1509 2334 222913 54186 0 0 222913 54186 2334 1844 0 0 8893 7317 0 0 13674 10870 0 0 2334 1930 0 0 101780 15971 0 0 93898 16254 0 0 2334 0 0 825 986 1127 7428 0 0 3.61237 3.61237 -134.789 -3.61237 0 0 585099. 2024.56 0.21 0.16 0.07 -1 -1 0.21 0.0251279 0.0229562 143 59 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_104.v common 3.72 vpr 63.14 MiB -1 -1 0.11 20496 1 0.01 -1 -1 33440 -1 -1 17 29 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64660 29 32 269 229 1 129 78 17 17 289 -1 unnamed_device 24.7 MiB 0.11 631 63.1 MiB 0.07 0.00 2.88681 -85.1602 -2.88681 2.88681 0.92 0.000144431 0.000119737 0.0114919 0.00961426 32 1365 20 6.65987e+06 215526 554710. 1919.41 0.84 0.0339766 0.0291104 22834 132086 -1 1260 20 886 1247 92539 22318 0 0 92539 22318 1247 988 0 0 4847 4281 0 0 8499 6718 0 0 1247 1063 0 0 37466 4731 0 0 39233 4537 0 0 1247 0 0 361 387 351 3122 0 0 2.68177 2.68177 -92.9771 -2.68177 0 0 701300. 2426.64 0.25 0.03 0.09 -1 -1 0.25 0.00926302 0.00803227 92 28 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_105.v common 4.10 vpr 63.50 MiB -1 -1 0.11 20840 1 0.01 -1 -1 32916 -1 -1 20 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65028 32 32 310 266 1 175 84 17 17 289 -1 unnamed_device 25.0 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0.00750949 30 2211 21 6.65987e+06 469086 526063. 1820.29 2.58 0.0817017 0.0697064 22546 126617 -1 1916 20 1124 1966 115507 26347 0 0 115507 26347 1966 1366 0 0 6549 5002 0 0 8533 6860 0 0 1966 1522 0 0 47624 5936 0 0 48869 5661 0 0 1966 0 0 842 1020 1123 7893 0 0 3.37811 3.37811 -115.41 -3.37811 0 0 666494. 2306.21 0.23 0.03 0.08 -1 -1 0.23 0.0109172 0.00979095 129 29 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_107.v common 5.18 vpr 63.16 MiB -1 -1 0.11 20824 1 0.01 -1 -1 33260 -1 -1 21 29 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64672 29 32 262 224 1 168 82 17 17 289 -1 unnamed_device 24.5 MiB 0.19 859 63.2 MiB 0.04 0.00 3.18595 -87.8969 -3.18595 3.18595 0.79 0.000131952 0.000109082 0.00679071 0.00572664 32 1955 21 6.65987e+06 266238 554710. 1919.41 2.38 0.0819939 0.059227 22834 132086 -1 1733 20 1151 1495 108004 26371 0 0 108004 26371 1495 1280 0 0 5838 4946 0 0 10042 7700 0 0 1495 1343 0 0 44441 5659 0 0 44693 5443 0 0 1495 0 0 344 330 284 3153 0 0 2.85531 2.85531 -99.5951 -2.85531 0 0 701300. 2426.64 0.26 0.03 0.09 -1 -1 0.26 0.00958391 0.00862679 110 25 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_108.v common 3.63 vpr 63.20 MiB -1 -1 0.11 20484 1 0.01 -1 -1 33176 -1 -1 16 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64720 32 32 278 238 1 149 80 17 17 289 -1 unnamed_device 24.7 MiB 0.17 904 63.2 MiB 0.05 0.00 2.78249 -92.7899 -2.78249 2.78249 0.90 0.000188369 0.000162324 0.0122884 0.0109725 30 1818 23 6.65987e+06 202848 526063. 1820.29 0.76 0.0436941 0.0384207 22546 126617 -1 1607 21 991 1677 90935 21919 0 0 90935 21919 1677 1123 0 0 5718 4628 0 0 7539 6121 0 0 1677 1258 0 0 38267 4214 0 0 36057 4575 0 0 1677 0 0 686 674 729 5406 0 0 2.56625 2.56625 -100.614 -2.56625 0 0 666494. 2306.21 0.25 0.03 0.08 -1 -1 0.25 0.010089 0.00902285 109 31 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_109.v common 6.47 vpr 63.64 MiB -1 -1 0.12 20992 1 0.01 -1 -1 33216 -1 -1 35 31 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65164 31 32 373 300 1 181 98 17 17 289 -1 unnamed_device 25.3 MiB 0.21 913 63.6 MiB 0.07 0.00 3.33161 -98.3149 -3.33161 3.33161 1.17 0.000174072 0.000143144 0.0132546 0.0113687 32 2053 22 6.65987e+06 443730 554710. 1919.41 2.97 0.116148 0.0962762 22834 132086 -1 1732 23 1525 2258 142391 34490 0 0 142391 34490 2258 1632 0 0 8451 6970 0 0 12728 9811 0 0 2258 1828 0 0 60069 6909 0 0 56627 7340 0 0 2258 0 0 733 818 958 6985 0 0 3.00816 3.00816 -108.43 -3.00816 0 0 701300. 2426.64 0.26 0.04 0.09 -1 -1 0.26 0.0134044 0.0119626 135 60 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_110.v common 6.39 vpr 63.23 MiB -1 -1 0.12 20820 1 0.01 -1 -1 33332 -1 -1 19 31 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64744 31 32 265 230 1 162 82 17 17 289 -1 unnamed_device 24.7 MiB 0.14 909 63.2 MiB 0.06 0.00 3.0359 -98.1422 -3.0359 3.0359 1.11 0.000153729 0.000127099 0.0105031 0.00806861 32 2155 21 6.65987e+06 240882 554710. 1919.41 3.11 0.117399 0.103168 22834 132086 -1 1840 22 1263 1837 141559 32742 0 0 141559 32742 1837 1486 0 0 7309 6270 0 0 11274 9015 0 0 1837 1569 0 0 57658 7628 0 0 61644 6774 0 0 1837 0 0 574 527 563 4649 0 0 3.22997 3.22997 -117.572 -3.22997 0 0 701300. 2426.64 0.28 0.04 0.09 -1 -1 0.28 0.0118652 0.0106688 108 30 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_111.v common 6.37 vpr 63.59 MiB -1 -1 0.11 20788 1 0.01 -1 -1 33116 -1 -1 31 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65120 32 32 349 286 1 171 95 17 17 289 -1 unnamed_device 25.0 MiB 0.26 864 63.6 MiB 0.14 0.00 2.92995 -93.2427 -2.92995 2.92995 0.92 0.000274643 0.000237458 0.0224863 0.0195626 30 2128 19 6.65987e+06 393018 526063. 1820.29 2.89 0.10301 0.0889879 22546 126617 -1 1722 16 995 1758 108595 25057 0 0 108595 25057 1758 1163 0 0 5999 4760 0 0 7898 6377 0 0 1758 1291 0 0 46205 5626 0 0 44977 5840 0 0 1758 0 0 763 1047 1233 7915 0 0 2.51631 2.51631 -100.858 -2.51631 0 0 666494. 2306.21 0.35 0.04 0.11 -1 -1 0.35 0.0106392 0.00924737 126 54 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_112.v common 4.48 vpr 63.61 MiB -1 -1 0.12 20876 1 0.02 -1 -1 33372 -1 -1 32 31 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65132 31 32 396 325 1 183 95 17 17 289 -1 unnamed_device 25.2 MiB 0.89 890 63.6 MiB 0.08 0.00 3.3843 -107.194 -3.3843 3.3843 0.87 0.000192536 0.000160627 0.0144661 0.0122346 32 2136 22 6.65987e+06 405696 554710. 1919.41 0.71 0.0483422 0.0416087 22834 132086 -1 1911 21 1571 2180 144508 35244 0 0 144508 35244 2180 1752 0 0 8302 7140 0 0 13195 10070 0 0 2180 1908 0 0 62221 6850 0 0 56430 7524 0 0 2180 0 0 609 796 706 5981 0 0 3.29983 3.29983 -127.331 -3.29983 0 0 701300. 2426.64 0.28 0.04 0.09 -1 -1 0.28 0.0147574 0.0132364 138 87 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_113.v common 5.54 vpr 63.40 MiB -1 -1 0.10 20764 1 0.01 -1 -1 33292 -1 -1 17 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64924 32 32 303 262 1 150 81 17 17 289 -1 unnamed_device 24.8 MiB 0.21 861 63.4 MiB 0.06 0.00 2.54264 -84.4966 -2.54264 2.54264 0.87 0.000254573 0.00022402 0.0108222 0.00908885 32 2003 35 6.65987e+06 215526 554710. 1919.41 2.57 0.0933733 0.0794513 22834 132086 -1 1789 18 931 1448 111970 25860 0 0 111970 25860 1448 1153 0 0 5604 4844 0 0 8731 6856 0 0 1448 1344 0 0 49895 5574 0 0 44844 6089 0 0 1448 0 0 517 417 423 3919 0 0 2.63651 2.63651 -101.106 -2.63651 0 0 701300. 2426.64 0.27 0.03 0.09 -1 -1 0.27 0.0112545 0.010251 104 54 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_114.v common 3.60 vpr 63.37 MiB -1 -1 0.10 20744 1 0.01 -1 -1 33108 -1 -1 19 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64892 32 32 290 244 1 175 83 17 17 289 -1 unnamed_device 25.0 MiB 0.12 890 63.4 MiB 0.06 0.00 3.26875 -101.502 -3.26875 3.26875 0.79 0.000150237 0.000123066 0.00936259 0.00789646 32 2147 21 6.65987e+06 240882 554710. 1919.41 0.75 0.0389492 0.0339123 22834 132086 -1 1804 17 1111 1705 116118 29035 0 0 116118 29035 1705 1482 0 0 6419 5402 0 0 9393 7414 0 0 1705 1554 0 0 49227 6453 0 0 47669 6730 0 0 1705 0 0 594 495 578 4560 0 0 3.14551 3.14551 -117.139 -3.14551 0 0 701300. 2426.64 0.30 0.03 0.10 -1 -1 0.30 0.00936359 0.00842777 115 31 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_115.v common 6.26 vpr 63.57 MiB -1 -1 0.11 20848 1 0.01 -1 -1 33152 -1 -1 22 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65096 32 32 318 257 1 194 86 17 17 289 -1 unnamed_device 25.2 MiB 0.11 1061 63.6 MiB 0.06 0.00 3.8213 -118.261 -3.8213 3.8213 1.31 0.000173506 0.000143909 0.0103624 0.00871629 32 2518 20 6.65987e+06 278916 554710. 1919.41 2.66 0.0811372 0.0700226 22834 132086 -1 2167 23 1500 2119 148606 35862 0 0 148606 35862 2119 1756 0 0 8302 6827 0 0 12810 10159 0 0 2119 1884 0 0 61948 7674 0 0 61308 7562 0 0 2119 0 0 619 635 614 5275 0 0 3.69471 3.69471 -127.674 -3.69471 0 0 701300. 2426.64 0.29 0.05 0.09 -1 -1 0.29 0.0153489 0.0139064 130 27 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_116.v common 5.78 vpr 63.50 MiB -1 -1 0.12 20764 1 0.02 -1 -1 33360 -1 -1 28 29 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65020 29 32 324 268 1 168 89 17 17 289 -1 unnamed_device 25.0 MiB 0.46 981 63.5 MiB 0.37 0.00 3.80467 -100.309 -3.80467 3.80467 1.40 0.000226787 0.000194352 0.0658978 0.0386767 26 2236 20 6.65987e+06 354984 477104. 1650.88 1.23 0.101636 0.0700073 21682 110474 -1 1981 19 956 1578 112034 26429 0 0 112034 26429 1578 1154 0 0 5995 4957 0 0 8879 7133 0 0 1578 1227 0 0 47292 6016 0 0 46712 5942 0 0 1578 0 0 622 759 879 6266 0 0 3.44903 3.44903 -117.5 -3.44903 0 0 585099. 2024.56 0.24 0.04 0.08 -1 -1 0.24 0.0117573 0.0105772 121 49 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_117.v common 7.84 vpr 63.49 MiB -1 -1 0.12 20768 1 0.01 -1 -1 33204 -1 -1 23 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65016 32 32 393 312 1 213 87 17 17 289 -1 unnamed_device 25.3 MiB 0.40 1044 63.5 MiB 0.10 0.00 3.94486 -124.626 -3.94486 3.94486 1.22 0.00020927 0.000174466 0.0196056 0.0175014 28 2680 29 6.65987e+06 291594 500653. 1732.36 3.97 0.131878 0.114583 21970 115934 -1 2241 21 1664 2450 161962 40104 0 0 161962 40104 2450 1962 0 0 8815 7093 0 0 12801 10145 0 0 2450 2080 0 0 69546 9279 0 0 65900 9545 0 0 2450 0 0 786 778 976 7074 0 0 4.09325 4.09325 -149.406 -4.09325 0 0 612192. 2118.31 0.23 0.05 0.07 -1 -1 0.23 0.0146584 0.0131269 153 62 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_118.v common 5.51 vpr 62.95 MiB -1 -1 0.11 20496 1 0.01 -1 -1 33032 -1 -1 18 31 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64464 31 32 229 197 1 138 81 17 17 289 -1 unnamed_device 24.3 MiB 0.08 786 63.0 MiB 0.05 0.00 2.91224 -81.8808 -2.91224 2.91224 0.88 0.000122551 0.000100779 0.00940594 0.00780856 32 1659 19 6.65987e+06 228204 554710. 1919.41 2.36 0.0624401 0.0533525 22834 132086 -1 1560 22 821 1349 99282 23871 0 0 99282 23871 1349 1035 0 0 5448 4659 0 0 8684 7067 0 0 1349 1183 0 0 41577 5011 0 0 40875 4916 0 0 1349 0 0 528 559 424 4096 0 0 2.72871 2.72871 -98.0314 -2.72871 0 0 701300. 2426.64 0.34 0.04 0.10 -1 -1 0.34 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VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65372 32 32 360 293 1 179 95 17 17 289 -1 unnamed_device 25.4 MiB 0.39 1063 63.8 MiB 0.09 0.00 3.33475 -107.709 -3.33475 3.33475 0.81 0.000169339 0.000139384 0.0157389 0.013212 32 2252 23 6.65987e+06 393018 554710. 1919.41 2.17 0.0865309 0.073809 22834 132086 -1 2022 18 1000 1433 100926 23667 0 0 100926 23667 1433 1118 0 0 5559 4649 0 0 8368 6512 0 0 1433 1164 0 0 42796 5068 0 0 41337 5156 0 0 1433 0 0 433 530 556 4538 0 0 3.19951 3.19951 -118.578 -3.19951 0 0 701300. 2426.64 0.37 0.04 0.09 -1 -1 0.37 0.0124233 0.0112971 130 57 -1 -1 -1 -1 + fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml mult_122.v common 7.45 vpr 63.77 MiB -1 -1 0.12 21016 1 0.02 -1 -1 33336 -1 -1 25 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev 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-1 0.13 20856 1 0.01 -1 -1 33292 -1 -1 13 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65948 32 32 354 285 1 193 77 17 17 289 -1 unnamed_device 25.8 MiB 2.44 794 64.4 MiB 0.09 0.00 4.4212 -127.216 -4.4212 4.4212 1.44 0.000192711 0.000161367 0.0189075 0.0153382 54 2354 27 6.95648e+06 188184 949917. 3286.91 5.70 0.154627 0.132995 29506 232905 -1 1793 22 1575 2348 171538 39455 0 0 171538 39455 2348 1887 0 0 7617 6852 0 0 13929 9029 0 0 2348 2051 0 0 74458 9405 0 0 70838 10231 0 0 2348 0 0 773 823 827 6835 0 0 4.62216 4.62216 -149.51 -4.62216 0 0 1.17392e+06 4061.99 0.45 0.05 0.16 -1 -1 0.45 0.0144696 0.0129666 81 47 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_002.v common 20.43 vpr 64.26 MiB -1 -1 0.13 21156 1 0.01 -1 -1 33196 -1 -1 15 30 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65804 30 32 363 293 1 187 77 17 17 289 -1 unnamed_device 25.7 MiB 2.27 838 64.3 MiB 0.14 0.00 3.66177 -114.959 -3.66177 3.66177 1.18 0.000329905 0.000283678 0.0441664 0.0352828 38 2667 39 6.95648e+06 217135 678818. 2348.85 14.52 0.202726 0.172607 26626 170182 -1 2126 24 2022 2865 234393 50183 0 0 234393 50183 2865 2576 0 0 8842 7856 0 0 14561 9731 0 0 2865 2712 0 0 106223 12952 0 0 99037 14356 0 0 2865 0 0 843 887 817 7098 0 0 4.36702 4.36702 -147.434 -4.36702 0 0 902133. 3121.57 0.41 0.07 0.11 -1 -1 0.41 0.0166622 0.0151344 80 58 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_003.v common 8.82 vpr 64.24 MiB -1 -1 0.11 20492 1 0.01 -1 -1 33212 -1 -1 15 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65784 32 32 299 247 1 182 79 17 17 289 -1 unnamed_device 25.8 MiB 1.45 993 64.2 MiB 0.09 0.00 3.10314 -103.161 -3.10314 3.10314 0.96 0.000147771 0.000121781 0.0225342 0.0199892 38 2600 42 6.95648e+06 217135 678818. 2348.85 3.71 0.129058 0.102086 26626 170182 -1 2071 20 1280 1705 132414 27935 0 0 132414 27935 1705 1399 0 0 5589 4826 0 0 8722 6136 0 0 1705 1456 0 0 58784 7129 0 0 55909 6989 0 0 1705 0 0 425 387 490 4075 0 0 3.51522 3.51522 -126.514 -3.51522 0 0 902133. 3121.57 0.55 0.05 0.28 -1 -1 0.55 0.0153008 0.0139982 76 26 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_004.v common 7.37 vpr 64.27 MiB -1 -1 0.11 20424 1 0.01 -1 -1 33256 -1 -1 19 29 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65808 29 32 308 248 1 162 80 17 17 289 -1 unnamed_device 25.7 MiB 0.31 698 64.3 MiB 0.05 0.00 3.50318 -98.6968 -3.50318 3.50318 0.78 0.000143684 0.000117109 0.0106341 0.00889546 40 2365 27 6.95648e+06 275038 706193. 2443.58 4.00 0.0914902 0.0780933 26914 176310 -1 1939 21 1634 2645 340242 99620 0 0 340242 99620 2645 2090 0 0 8853 7608 0 0 16609 10650 0 0 2645 2245 0 0 156985 38798 0 0 152505 38229 0 0 2645 0 0 1011 1246 1285 8939 0 0 3.78576 3.78576 -122.36 -3.78576 0 0 926341. 3205.33 0.59 0.09 0.16 -1 -1 0.59 0.0138794 0.0124891 71 25 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_005.v common 6.33 vpr 64.17 MiB -1 -1 0.11 20952 1 0.01 -1 -1 33224 -1 -1 16 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65708 32 32 336 268 1 172 80 17 17 289 -1 unnamed_device 25.6 MiB 0.73 764 64.2 MiB 0.06 0.00 3.67069 -107.059 -3.67069 3.67069 0.77 0.00015809 0.000129032 0.0133289 0.0111584 46 2390 32 6.95648e+06 231611 828058. 2865.25 2.79 0.0720027 0.0621116 28066 200906 -1 1871 24 1370 2330 193175 42384 0 0 193175 42384 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common 8.23 vpr 64.20 MiB -1 -1 0.12 20452 1 0.01 -1 -1 33384 -1 -1 25 31 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65744 31 32 271 219 1 157 88 17 17 289 -1 unnamed_device 25.7 MiB 0.39 679 64.2 MiB 0.06 0.00 2.5154 -76.9069 -2.5154 2.5154 0.91 0.000167346 0.000133558 0.0117618 0.00980848 44 1890 28 6.95648e+06 361892 787024. 2723.27 4.90 0.144871 0.131385 27778 195446 -1 1494 21 962 1653 109412 25706 0 0 109412 25706 1653 1170 0 0 5552 4751 0 0 9042 6576 0 0 1653 1300 0 0 45607 5741 0 0 45905 6168 0 0 1653 0 0 691 977 1105 6952 0 0 2.88052 2.88052 -97.888 -2.88052 0 0 997811. 3452.63 0.32 0.03 0.12 -1 -1 0.32 0.0100921 0.00905145 69 -1 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_009.v common 9.74 vpr 64.31 MiB -1 -1 0.12 20892 1 0.01 -1 -1 33012 -1 -1 11 31 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65856 31 32 317 271 1 163 74 17 17 289 -1 unnamed_device 25.7 MiB 2.75 653 64.3 MiB 0.05 0.00 2.76819 -94.7229 -2.76819 2.76819 2.23 0.000157297 0.000131064 0.0124481 0.0104945 38 2241 30 6.95648e+06 159232 678818. 2348.85 2.39 0.0641545 0.0550356 26626 170182 -1 1634 20 1319 1850 153266 34753 0 0 153266 34753 1850 1553 0 0 5882 5230 0 0 9647 6559 0 0 1850 1570 0 0 63614 10522 0 0 70423 9319 0 0 1850 0 0 531 533 376 4352 0 0 3.53556 3.53556 -122.843 -3.53556 0 0 902133. 3121.57 0.29 0.04 0.11 -1 -1 0.29 0.0105812 0.0094877 66 60 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_010.v common 12.63 vpr 64.23 MiB -1 -1 0.11 20852 1 0.01 -1 -1 33116 -1 -1 10 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65776 32 32 298 248 1 150 74 17 17 289 -1 unnamed_device 25.7 MiB 1.40 628 64.2 MiB 0.06 0.00 2.66488 -91.5447 -2.66488 2.66488 1.64 0.000193026 0.000163333 0.0111048 0.00949575 38 1893 46 6.95648e+06 144757 678818. 2348.85 6.50 0.120812 0.107525 26626 170182 -1 1504 23 1265 1808 141711 31809 0 0 141711 31809 1808 1501 0 0 5671 4950 0 0 9179 6239 0 0 1808 1569 0 0 63482 8310 0 0 59763 9240 0 0 1808 0 0 543 527 636 4974 0 0 3.24832 3.24832 -122.525 -3.24832 0 0 902133. 3121.57 0.46 0.04 0.19 -1 -1 0.46 0.0128848 0.0115347 59 31 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_011.v common 8.46 vpr 63.95 MiB -1 -1 0.11 20724 1 0.01 -1 -1 33148 -1 -1 12 30 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65480 30 32 303 262 1 137 74 17 17 289 -1 unnamed_device 25.4 MiB 1.62 505 63.9 MiB 0.05 0.00 2.79013 -84.2419 -2.79013 2.79013 1.00 0.000137999 0.000111813 0.0111816 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3.73437 -138.942 -3.73437 0 0 926341. 3205.33 0.72 0.13 0.19 -1 -1 0.72 0.0393571 0.0345091 83 31 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_014.v common 11.24 vpr 64.41 MiB -1 -1 0.11 20868 1 0.02 -1 -1 33164 -1 -1 22 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65952 32 32 363 295 1 174 86 17 17 289 -1 unnamed_device 25.9 MiB 0.73 788 64.4 MiB 0.04 0.00 3.72883 -113.103 -3.72883 3.72883 0.76 0.000293007 0.000261621 0.00987948 0.00829327 36 3338 48 6.95648e+06 318465 648988. 2245.63 7.57 0.0870925 0.0750967 26050 158493 -1 2230 28 2308 3355 439415 139560 0 0 439415 139560 3355 2865 0 0 9995 8477 0 0 18665 11497 0 0 3355 3041 0 0 206066 57631 0 0 197979 56049 0 0 3355 0 0 1047 1378 1498 9906 0 0 4.13172 4.13172 -142.816 -4.13172 0 0 828058. 2865.25 0.40 0.14 0.13 -1 -1 0.40 0.0254857 0.0235369 75 58 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_015.v common 5.70 vpr 63.76 MiB -1 -1 0.10 20564 1 0.01 -1 -1 33152 -1 -1 13 29 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65292 29 32 248 215 1 136 74 17 17 289 -1 unnamed_device 25.2 MiB 1.12 641 63.8 MiB 0.03 0.00 2.60155 -73.105 -2.60155 2.60155 0.75 0.000121442 9.8881e-05 0.00782061 0.00651969 36 2412 45 6.95648e+06 188184 648988. 2245.63 1.87 0.0508412 0.043681 26050 158493 -1 1603 21 1201 1804 183297 41490 0 0 183297 41490 1804 1625 0 0 5516 4710 0 0 9881 6229 0 0 1804 1701 0 0 81432 13612 0 0 82860 13613 0 0 1804 0 0 603 679 699 5051 0 0 3.21527 3.21527 -105.42 -3.21527 0 0 828058. 2865.25 0.34 0.05 0.16 -1 -1 0.34 0.0113704 0.00929802 55 21 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_016.v common 9.81 vpr 64.40 MiB -1 -1 0.10 20776 1 0.01 -1 -1 33396 -1 -1 17 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65948 32 32 370 297 1 180 81 17 17 289 -1 unnamed_device 25.9 MiB 0.94 766 64.4 MiB 0.05 0.00 2.6254 -93.1189 -2.6254 2.6254 0.75 0.000169795 0.000138463 0.012568 0.0104629 48 2451 38 6.95648e+06 246087 865456. 2994.66 6.20 0.131147 0.113143 28354 207349 -1 1813 25 1675 2662 296784 68934 0 0 296784 68934 2662 2054 0 0 8972 7830 0 0 16693 10974 0 0 2662 2193 0 0 132423 22543 0 0 133372 23340 0 0 2662 0 0 987 1178 1194 8681 0 0 3.38757 3.38757 -120.673 -3.38757 0 0 1.05005e+06 3633.38 0.34 0.08 0.13 -1 -1 0.34 0.0340166 0.0324054 76 55 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_017.v common 6.11 vpr 64.30 MiB -1 -1 0.11 20844 1 0.01 -1 -1 33144 -1 -1 14 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65848 32 32 338 269 1 190 78 17 17 289 -1 unnamed_device 25.8 MiB 1.67 824 64.3 MiB 0.07 0.00 3.53151 -112.935 -3.53151 3.53151 0.77 0.000155388 0.000127209 0.0150928 0.0116656 38 3074 41 6.95648e+06 202660 678818. 2348.85 1.86 0.0775139 0.0662367 26626 170182 -1 2083 20 1556 2118 179966 38975 0 0 179966 38975 2118 1907 0 0 6711 5791 0 0 10748 7403 0 0 2118 1946 0 0 77350 11093 0 0 80921 10835 0 0 2118 0 0 562 613 542 4959 0 0 3.85502 3.85502 -139.123 -3.85502 0 0 902133. 3121.57 0.29 0.05 0.11 -1 -1 0.29 0.012427 0.0111815 79 31 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_018.v common 4.52 vpr 64.22 MiB -1 -1 0.11 20512 1 0.01 -1 -1 33156 -1 -1 9 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65764 32 32 323 276 1 148 73 17 17 289 -1 unnamed_device 25.6 MiB 0.65 926 64.2 MiB 0.05 0.00 1.91376 -83.6912 -1.91376 1.91376 0.83 0.000148896 0.000121377 0.0113942 0.00939914 38 2160 23 6.95648e+06 130281 678818. 2348.85 1.27 0.0475907 0.0404808 26626 170182 -1 1946 20 1211 1759 166433 32412 0 0 166433 32412 1759 1523 0 0 5436 4812 0 0 9106 5905 0 0 1759 1605 0 0 75192 9082 0 0 73181 9485 0 0 1759 0 0 548 852 884 5587 0 0 2.36013 2.36013 -108.678 -2.36013 0 0 902133. 3121.57 0.28 0.04 0.11 -1 -1 0.28 0.0106338 0.00949456 57 62 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_019.v common 4.38 vpr 63.50 MiB -1 -1 0.10 20804 1 0.01 -1 -1 33304 -1 -1 9 30 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65028 30 32 222 206 1 116 71 17 17 289 -1 unnamed_device 25.2 MiB 0.31 463 63.5 MiB 0.03 0.00 1.85256 -62.2361 -1.85256 1.85256 0.74 0.000109726 8.8254e-05 0.0069722 0.00577116 40 1303 33 6.95648e+06 130281 706193. 2443.58 1.61 0.0444899 0.0377373 26914 176310 -1 1041 18 738 948 95793 21178 0 0 95793 21178 948 906 0 0 3238 2779 0 0 5609 3837 0 0 948 909 0 0 41961 6364 0 0 43089 6383 0 0 948 0 0 210 273 256 2107 0 0 2.39128 2.39128 -83.548 -2.39128 0 0 926341. 3205.33 0.31 0.03 0.11 -1 -1 0.31 0.00729975 0.00653932 43 29 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_020.v common 8.19 vpr 63.96 MiB -1 -1 0.10 20448 1 0.02 -1 -1 33296 -1 -1 12 31 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65492 31 32 291 243 1 169 75 17 17 289 -1 unnamed_device 25.4 MiB 2.06 903 64.0 MiB 0.04 0.00 3.36378 -112.731 -3.36378 3.36378 0.74 0.000150549 0.000125549 0.0104579 0.00888115 44 2178 28 6.95648e+06 173708 787024. 2723.27 3.57 0.0819379 0.0703889 27778 195446 -1 1879 19 1428 1883 169692 34539 0 0 169692 34539 1883 1756 0 0 6107 5385 0 0 10679 7088 0 0 1883 1770 0 0 77828 8351 0 0 71312 10189 0 0 1883 0 0 455 241 464 3991 0 0 3.88817 3.88817 -139.758 -3.88817 0 0 997811. 3452.63 0.32 0.04 0.12 -1 -1 0.32 0.0100877 0.0090699 69 30 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_021.v common 11.05 vpr 64.22 MiB -1 -1 0.11 21184 1 0.01 -1 -1 33468 -1 -1 20 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65760 32 32 342 271 1 173 84 17 17 289 -1 unnamed_device 25.7 MiB 0.64 702 64.2 MiB 0.06 0.00 3.07689 -100.888 -3.07689 3.07689 0.86 0.000170724 0.000142075 0.0139238 0.0116109 38 2433 28 6.95648e+06 289514 678818. 2348.85 7.70 0.122443 0.105302 26626 170182 -1 1811 23 1528 2188 174581 37954 0 0 174581 37954 2188 1821 0 0 6715 5789 0 0 10867 7322 0 0 2188 1891 0 0 79899 9724 0 0 72724 11407 0 0 2188 0 0 660 846 708 6382 0 0 3.97236 3.97236 -136.064 -3.97236 0 0 902133. 3121.57 0.29 0.04 0.10 -1 -1 0.29 0.0121425 0.0108138 75 31 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_022.v common 6.89 vpr 64.51 MiB -1 -1 0.11 20700 1 0.01 -1 -1 33216 -1 -1 14 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 66056 32 32 372 300 1 197 78 17 17 289 -1 unnamed_device 26.1 MiB 1.24 847 64.5 MiB 0.07 0.00 3.8447 -111.917 -3.8447 3.8447 0.87 0.000164757 0.000134763 0.0181508 0.0152152 54 2427 47 6.95648e+06 202660 949917. 3286.91 2.76 0.0927142 0.0793263 29506 232905 -1 1734 22 1437 2269 206287 44374 0 0 206287 44374 2269 1762 0 0 7175 6356 0 0 13230 8344 0 0 2269 1895 0 0 92961 12687 0 0 88383 13330 0 0 2269 0 0 832 909 796 6908 0 0 4.16372 4.16372 -133.012 -4.16372 0 0 1.17392e+06 4061.99 0.39 0.05 0.16 -1 -1 0.39 0.013248 0.0118523 82 59 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_023.v common 6.39 vpr 63.64 MiB -1 -1 0.09 20620 1 0.01 -1 -1 33320 -1 -1 13 26 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65168 26 32 190 182 1 104 71 17 17 289 -1 unnamed_device 25.1 MiB 0.79 313 63.6 MiB 0.03 0.00 1.86056 -53.5017 -1.86056 1.86056 0.76 9.4581e-05 7.6265e-05 0.00759014 0.00628647 38 1009 24 6.95648e+06 188184 678818. 2348.85 3.17 0.0459376 0.0386786 26626 170182 -1 747 20 549 650 46367 12158 0 0 46367 12158 650 591 0 0 2103 1860 0 0 3297 2317 0 0 650 591 0 0 19258 3492 0 0 20409 3307 0 0 650 0 0 101 58 55 1090 0 0 1.97423 1.97423 -65.1302 -1.97423 0 0 902133. 3121.57 0.28 0.02 0.10 -1 -1 0.28 0.00650547 0.0057983 44 21 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_024.v common 5.61 vpr 64.27 MiB -1 -1 0.10 20776 1 0.01 -1 -1 33124 -1 -1 15 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65816 32 32 285 227 1 161 79 17 17 289 -1 unnamed_device 25.8 MiB 0.73 660 64.3 MiB 0.04 0.00 3.81446 -97.2097 -3.81446 3.81446 0.75 0.000150374 0.000124817 0.00944547 0.00805946 46 1733 28 6.95648e+06 217135 828058. 2865.25 2.31 0.0586858 0.0504788 28066 200906 -1 1265 24 1177 1929 123864 32253 0 0 123864 32253 1929 1505 0 0 6324 5481 0 0 11020 7473 0 0 1929 1623 0 0 49573 8491 0 0 53089 7680 0 0 1929 0 0 752 1014 751 6576 0 0 3.72272 3.72272 -115.79 -3.72272 0 0 1.01997e+06 3529.29 0.35 0.04 0.13 -1 -1 0.35 0.0118185 0.0105747 66 -1 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_025.v common 5.91 vpr 63.68 MiB -1 -1 0.10 20224 1 0.01 -1 -1 33020 -1 -1 8 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65204 32 32 173 169 1 112 72 17 17 289 -1 unnamed_device 25.2 MiB 0.26 371 63.7 MiB 0.03 0.00 1.77736 -57.0815 -1.77736 1.77736 0.80 9.7217e-05 7.8476e-05 0.00748534 0.00626965 36 1204 41 6.95648e+06 115805 648988. 2245.63 3.07 0.0505986 0.0430516 26050 158493 -1 943 21 681 796 72255 17792 0 0 72255 17792 796 762 0 0 2825 2505 0 0 4482 3245 0 0 796 771 0 0 30778 5184 0 0 32578 5325 0 0 796 0 0 115 69 127 1337 0 0 1.93388 1.93388 -74.6492 -1.93388 0 0 828058. 2865.25 0.26 0.02 0.10 -1 -1 0.26 0.00670408 0.00594475 42 -1 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_026.v common 8.43 vpr 64.27 MiB -1 -1 0.13 20596 1 0.01 -1 -1 32948 -1 -1 15 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65812 32 32 300 245 1 165 79 17 17 289 -1 unnamed_device 25.7 MiB 1.30 957 64.3 MiB 0.06 0.00 3.51735 -103.645 -3.51735 3.51735 0.79 0.000139679 0.000114349 0.0153011 0.0128007 36 2609 38 6.95648e+06 217135 648988. 2245.63 4.05 0.0739621 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success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65484 30 32 262 227 1 134 80 17 17 289 -1 unnamed_device 25.4 MiB 0.19 509 63.9 MiB 0.04 0.00 2.86043 -79.3085 -2.86043 2.86043 0.83 0.000127007 0.000103053 0.00965087 0.00796987 46 1182 27 6.95648e+06 260562 828058. 2865.25 3.82 0.0799212 0.0681963 28066 200906 -1 940 18 662 954 58099 16182 0 0 58099 16182 954 723 0 0 3217 2759 0 0 5071 3538 0 0 954 799 0 0 22589 4375 0 0 25314 3988 0 0 954 0 0 292 350 236 2610 0 0 2.61412 2.61412 -89.1578 -2.61412 0 0 1.01997e+06 3529.29 0.38 0.03 0.13 -1 -1 0.38 0.00941525 0.00847552 57 29 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_031.v common 13.11 vpr 63.88 MiB -1 -1 0.11 20608 1 0.01 -1 -1 32900 -1 -1 16 28 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65408 28 32 260 223 1 135 76 17 17 289 -1 unnamed_device 25.3 MiB 0.53 454 63.9 MiB 0.06 0.00 2.5594 -74.4713 -2.5594 2.5594 1.08 0.000126408 0.000103015 0.0137126 0.0119085 40 2146 48 6.95648e+06 231611 706193. 2443.58 8.66 0.137527 0.119019 26914 176310 -1 1584 23 1225 1845 170110 43917 0 0 170110 43917 1845 1617 0 0 6245 5527 0 0 11859 7924 0 0 1845 1656 0 0 72604 13513 0 0 75712 13680 0 0 1845 0 0 620 629 709 5231 0 0 3.53622 3.53622 -110.508 -3.53622 0 0 926341. 3205.33 0.61 0.15 0.23 -1 -1 0.61 0.045146 0.0338922 57 27 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_032.v common 9.45 vpr 63.87 MiB -1 -1 0.11 20692 1 0.01 -1 -1 33112 -1 -1 10 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65400 32 32 253 210 1 149 74 17 17 289 -1 unnamed_device 25.3 MiB 0.40 547 63.9 MiB 0.04 0.00 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0.0142729 84 26 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_036.v common 8.70 vpr 64.35 MiB -1 -1 0.11 20736 1 0.01 -1 -1 33012 -1 -1 24 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65892 32 32 391 311 1 184 88 17 17 289 -1 unnamed_device 26.0 MiB 1.35 750 64.3 MiB 0.08 0.00 2.75098 -96.7793 -2.75098 2.75098 0.99 0.000239543 0.000198825 0.0265279 0.0234207 44 2357 40 6.95648e+06 347416 787024. 2723.27 2.75 0.0966998 0.0836411 27778 195446 -1 1795 23 1787 2487 215742 46747 0 0 215742 46747 2487 1951 0 0 7608 6672 0 0 13847 8872 0 0 2487 2147 0 0 90111 13983 0 0 99202 13122 0 0 2487 0 0 700 819 849 6707 0 0 3.39997 3.39997 -121.005 -3.39997 0 0 997811. 3452.63 0.48 0.06 0.16 -1 -1 0.48 0.0168762 0.0150733 82 62 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_037.v common 13.45 vpr 64.09 MiB -1 -1 0.11 20840 1 0.01 -1 -1 33408 -1 -1 11 31 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65624 31 32 279 237 1 153 74 17 17 289 -1 unnamed_device 25.6 MiB 1.78 804 64.1 MiB 0.09 0.00 3.28867 -109.886 -3.28867 3.28867 1.18 0.000193989 0.000160548 0.0193677 0.0175731 36 2296 24 6.95648e+06 159232 648988. 2245.63 8.12 0.144798 0.109405 26050 158493 -1 1997 20 1268 1760 168219 33846 0 0 168219 33846 1760 1580 0 0 5518 4749 0 0 9658 6216 0 0 1760 1602 0 0 72891 10209 0 0 76632 9490 0 0 1760 0 0 492 535 599 4784 0 0 3.69652 3.69652 -137.059 -3.69652 0 0 828058. 2865.25 0.34 0.05 0.12 -1 -1 0.34 0.0114381 0.0103328 63 30 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_038.v common 14.09 vpr 64.32 MiB -1 -1 0.12 20800 1 0.02 -1 -1 33280 -1 -1 16 31 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65868 31 32 370 297 1 179 79 17 17 289 -1 unnamed_device 25.7 MiB 1.26 782 64.3 MiB 0.08 0.00 3.10309 -100.182 -3.10309 3.10309 1.15 0.000212894 0.000180819 0.0224734 0.0195166 56 2116 45 6.95648e+06 231611 973134. 3367.25 8.39 0.170048 0.149046 29794 239141 -1 1625 21 1454 2185 177367 40502 0 0 177367 40502 2185 1711 0 0 7255 6081 0 0 12655 8585 0 0 2185 2012 0 0 70228 11558 0 0 82859 10555 0 0 2185 0 0 731 724 748 6116 0 0 3.02467 3.02467 -114.707 -3.02467 0 0 1.19926e+06 4149.71 0.42 0.05 0.15 -1 -1 0.42 0.0143121 0.0128617 76 57 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_039.v common 14.46 vpr 64.34 MiB -1 -1 0.12 20848 1 0.02 -1 -1 33264 -1 -1 16 31 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65880 31 32 377 302 1 225 79 17 17 289 -1 unnamed_device 25.9 MiB 1.91 1038 64.3 MiB 0.07 0.00 4.49406 -141.673 -4.49406 4.49406 0.94 0.000222915 0.000188333 0.0169237 0.0143039 46 3055 26 6.95648e+06 231611 828058. 2865.25 8.00 0.226285 0.206065 28066 200906 -1 2366 23 2128 3078 283733 58027 0 0 283733 58027 3078 2789 0 0 9928 8989 0 0 18196 11815 0 0 3078 2872 0 0 121558 16027 0 0 127895 15535 0 0 3078 0 0 950 850 789 7567 0 0 5.0959 5.0959 -172.092 -5.0959 0 0 1.01997e+06 3529.29 1.07 0.11 0.47 -1 -1 1.07 0.0285514 0.0266177 97 60 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_040.v common 11.90 vpr 64.36 MiB -1 -1 0.12 20924 1 0.01 -1 -1 33096 -1 -1 16 31 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65904 31 32 383 305 1 204 79 17 17 289 -1 unnamed_device 25.9 MiB 2.33 864 64.4 MiB 0.07 0.00 3.71649 -118.457 -3.71649 3.71649 0.78 0.000202347 0.00016909 0.0183056 0.0153709 46 2754 25 6.95648e+06 231611 828058. 2865.25 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0.0159276 0.0143619 71 24 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_043.v common 7.18 vpr 65.04 MiB -1 -1 0.13 21200 1 0.01 -1 -1 33384 -1 -1 22 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 66596 32 32 457 356 1 214 86 17 17 289 -1 unnamed_device 26.4 MiB 1.51 906 65.0 MiB 0.09 0.00 3.98456 -128.516 -3.98456 3.98456 0.89 0.000221386 0.000183941 0.0215231 0.0177509 44 3159 49 6.95648e+06 318465 787024. 2723.27 2.64 0.113981 0.096907 27778 195446 -1 2170 23 1935 2789 209447 47044 0 0 209447 47044 2789 2260 0 0 8720 7662 0 0 15168 10298 0 0 2789 2389 0 0 95077 10873 0 0 84904 13562 0 0 2789 0 0 854 1124 944 8323 0 0 4.59581 4.59581 -158.047 -4.59581 0 0 997811. 3452.63 0.44 0.05 0.14 -1 -1 0.44 0.0164583 0.014655 93 84 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_044.v common 6.95 vpr 63.96 MiB -1 -1 0.09 20820 1 0.01 -1 -1 33348 -1 -1 15 31 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65492 31 32 261 225 1 137 78 17 17 289 -1 unnamed_device 25.3 MiB 0.77 472 64.0 MiB 0.04 0.00 2.86325 -81.3593 -2.86325 2.86325 0.76 0.000137772 0.000114769 0.0100372 0.00832414 42 1558 26 6.95648e+06 217135 744469. 2576.02 3.40 0.0837844 0.0703899 27202 183097 -1 1249 17 1002 1377 98573 25685 0 0 98573 25685 1377 1190 0 0 4810 4158 0 0 8269 5947 0 0 1377 1244 0 0 38438 6743 0 0 44302 6403 0 0 1377 0 0 375 381 331 3320 0 0 3.34677 3.34677 -103.288 -3.34677 0 0 949917. 3286.91 0.30 0.03 0.11 -1 -1 0.30 0.00837094 0.00752595 56 24 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_045.v common 12.05 vpr 64.54 MiB -1 -1 0.12 21032 1 0.02 -1 -1 33216 -1 -1 15 31 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 66088 31 32 337 267 1 199 78 17 17 289 -1 unnamed_device 26.0 MiB 1.18 931 64.5 MiB 0.07 0.00 3.94062 -123.085 -3.94062 3.94062 0.75 0.000155772 0.000127415 0.0153434 0.0128757 48 2558 27 6.95648e+06 217135 865456. 2994.66 8.14 0.138416 0.118948 28354 207349 -1 2079 25 1817 2586 253359 51768 0 0 253359 51768 2586 2300 0 0 8399 7409 0 0 16763 10177 0 0 2586 2388 0 0 113185 14509 0 0 109840 14985 0 0 2586 0 0 769 888 836 7021 0 0 4.51986 4.51986 -149.743 -4.51986 0 0 1.05005e+06 3633.38 0.36 0.06 0.13 -1 -1 0.36 0.0154175 0.0137848 84 30 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_046.v common 6.00 vpr 64.34 MiB -1 -1 0.11 20924 1 0.01 -1 -1 33132 -1 -1 17 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65884 32 32 349 284 1 175 81 17 17 289 -1 unnamed_device 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6.95648e+06 231611 828058. 2865.25 1.71 0.0529791 0.0460723 28066 200906 -1 1593 23 1125 1949 172385 40630 0 0 172385 40630 1949 1490 0 0 6188 5463 0 0 11850 7353 0 0 1949 1629 0 0 76020 11902 0 0 74429 12793 0 0 1949 0 0 824 1178 1002 7495 0 0 3.96632 3.96632 -124.931 -3.96632 0 0 1.01997e+06 3529.29 0.53 0.08 0.13 -1 -1 0.53 0.0255516 0.0236151 68 -1 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_048.v common 10.38 vpr 64.42 MiB -1 -1 0.12 20836 1 0.01 -1 -1 33264 -1 -1 14 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65964 32 32 353 287 1 185 78 17 17 289 -1 unnamed_device 25.8 MiB 2.76 810 64.4 MiB 0.06 0.00 3.53145 -110.258 -3.53145 3.53145 1.16 0.000185522 0.000151786 0.0138731 0.0116156 46 2354 24 6.95648e+06 202660 828058. 2865.25 4.25 0.0950124 0.0814485 28066 200906 -1 1809 20 1314 1785 120180 27921 0 0 120180 27921 1785 1527 0 0 5840 5147 0 0 9903 6682 0 0 1785 1585 0 0 50025 6398 0 0 50842 6582 0 0 1785 0 0 471 473 423 4310 0 0 3.78266 3.78266 -129.657 -3.78266 0 0 1.01997e+06 3529.29 0.36 0.04 0.13 -1 -1 0.36 0.0132179 0.011867 78 52 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_049.v common 7.55 vpr 64.30 MiB -1 -1 0.12 20728 1 0.01 -1 -1 33108 -1 -1 17 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65840 32 32 361 291 1 179 81 17 17 289 -1 unnamed_device 25.8 MiB 1.84 761 64.3 MiB 0.05 0.00 2.6818 -92.9296 -2.6818 2.6818 0.91 0.000168816 0.000135799 0.0134665 0.010991 38 2744 39 6.95648e+06 246087 678818. 2348.85 2.21 0.07293 0.0621546 26626 170182 -1 2082 22 1565 2353 215930 48112 0 0 215930 48112 2353 1947 0 0 7389 6440 0 0 12471 8272 0 0 2353 2059 0 0 98075 14176 0 0 93289 15218 0 0 2353 0 0 788 1123 1104 7900 0 0 3.30467 3.30467 -122.831 -3.30467 0 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vpr 64.24 MiB -1 -1 0.11 20544 1 0.01 -1 -1 33204 -1 -1 22 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65784 32 32 306 248 1 164 86 17 17 289 -1 unnamed_device 25.6 MiB 1.03 688 64.2 MiB 0.09 0.00 3.63883 -96.8071 -3.63883 3.63883 1.19 0.000144018 0.000117513 0.0124019 0.0103826 46 2277 34 6.95648e+06 318465 828058. 2865.25 3.97 0.122542 0.107252 28066 200906 -1 1681 21 1278 2023 138529 33372 0 0 138529 33372 2023 1589 0 0 6305 5434 0 0 10516 6981 0 0 2023 1730 0 0 56158 8905 0 0 61504 8733 0 0 2023 0 0 745 903 833 6666 0 0 3.80966 3.80966 -125.783 -3.80966 0 0 1.01997e+06 3529.29 0.52 0.13 0.13 -1 -1 0.52 0.0124336 0.0111488 69 21 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_052.v common 11.18 vpr 64.11 MiB -1 -1 0.11 20944 1 0.02 -1 -1 32984 -1 -1 13 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65652 32 32 319 257 1 191 77 17 17 289 -1 unnamed_device 25.7 MiB 2.66 788 64.1 MiB 0.06 0.00 3.53127 -106.029 -3.53127 3.53127 1.42 0.000150895 0.000123056 0.014658 0.0127479 40 2745 41 6.95648e+06 188184 706193. 2443.58 3.83 0.0858996 0.0753663 26914 176310 -1 2133 20 1728 2302 201080 47324 0 0 201080 47324 2302 2050 0 0 7990 6950 0 0 13767 9601 0 0 2302 2102 0 0 88378 13192 0 0 86341 13429 0 0 2302 0 0 574 673 596 5311 0 0 4.60486 4.60486 -142.641 -4.60486 0 0 926341. 3205.33 0.72 0.14 0.15 -1 -1 0.72 0.0373893 0.0357242 79 26 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_053.v common 22.98 vpr 64.71 MiB -1 -1 0.11 20872 1 0.01 -1 -1 33172 -1 -1 15 31 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 66260 31 32 373 299 1 194 78 17 17 289 -1 unnamed_device 26.2 MiB 1.29 861 64.7 MiB 0.06 0.00 3.78527 -117.676 -3.78527 3.78527 0.81 0.000184751 0.000152101 0.01439 0.0122194 40 3186 48 6.95648e+06 217135 706193. 2443.58 18.74 0.178597 0.155885 26914 176310 -1 2635 24 2007 3175 366874 81134 0 0 366874 81134 3175 2880 0 0 10132 8970 0 0 20337 12202 0 0 3175 3016 0 0 166141 26935 0 0 163914 27131 0 0 3175 0 0 1168 1394 1619 10314 0 0 4.56272 4.56272 -151.701 -4.56272 0 0 926341. 3205.33 0.39 0.10 0.12 -1 -1 0.39 0.019899 0.0178283 85 58 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_054.v common 10.11 vpr 64.52 MiB -1 -1 0.11 20848 1 0.01 -1 -1 33220 -1 -1 13 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 66072 32 32 387 315 1 182 77 17 17 289 -1 unnamed_device 26.2 MiB 2.12 833 64.5 MiB 0.06 0.00 3.495 -109.002 -3.495 3.495 0.76 0.000169028 0.00013747 0.0149936 0.0125507 46 2855 31 6.95648e+06 188184 828058. 2865.25 5.19 0.138777 0.120195 28066 200906 -1 2192 20 1464 2432 185008 43114 0 0 185008 43114 2432 2040 0 0 7632 6805 0 0 12854 8598 0 0 2432 2216 0 0 78349 11496 0 0 81309 11959 0 0 2432 0 0 968 858 760 7028 0 0 4.43452 4.43452 -143.608 -4.43452 0 0 1.01997e+06 3529.29 0.41 0.05 0.18 -1 -1 0.41 0.0138341 0.012363 76 74 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_055.v common 4.35 vpr 63.84 MiB -1 -1 0.10 20724 1 0.01 -1 -1 33216 -1 -1 18 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65372 32 32 251 219 1 136 82 17 17 289 -1 unnamed_device 25.3 MiB 0.22 615 63.8 MiB 0.05 0.00 2.50468 -77.473 -2.50468 2.50468 0.78 0.000123839 9.9955e-05 0.0104075 0.0085918 40 1793 23 6.95648e+06 260562 706193. 2443.58 1.55 0.0514253 0.0440671 26914 176310 -1 1591 21 1094 1668 157420 35511 0 0 157420 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fixed_k6_frac_2ripple_N8_22nm.xml mult_058.v common 6.27 vpr 64.16 MiB -1 -1 0.11 20812 1 0.01 -1 -1 33212 -1 -1 17 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65704 32 32 340 270 1 175 81 17 17 289 -1 unnamed_device 25.7 MiB 0.80 697 64.2 MiB 0.07 0.00 3.78211 -117.569 -3.78211 3.78211 0.79 0.000162768 0.000133775 0.0187268 0.0160195 40 2312 46 6.95648e+06 246087 706193. 2443.58 2.74 0.0846341 0.0731236 26914 176310 -1 1918 26 1761 2344 328880 107100 0 0 328880 107100 2344 2052 0 0 8047 6940 0 0 15423 10132 0 0 2344 2111 0 0 149336 43383 0 0 151386 42482 0 0 2344 0 0 583 618 822 6005 0 0 3.60616 3.60616 -138.533 -3.60616 0 0 926341. 3205.33 0.30 0.08 0.11 -1 -1 0.30 0.015414 0.0137648 74 31 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_059.v common 6.72 vpr 64.30 MiB -1 -1 0.10 20884 1 0.01 -1 -1 33112 -1 -1 20 30 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65840 30 32 278 235 1 143 82 17 17 289 -1 unnamed_device 25.8 MiB 0.47 641 64.3 MiB 0.05 0.00 2.44995 -80.8493 -2.44995 2.44995 0.81 0.00089417 0.000865007 0.0122408 0.0103081 46 1663 29 6.95648e+06 289514 828058. 2865.25 3.53 0.0822304 0.0704031 28066 200906 -1 1351 23 1165 1726 122168 27967 0 0 122168 27967 1726 1340 0 0 5577 4842 0 0 9319 6469 0 0 1726 1494 0 0 50343 6853 0 0 53477 6969 0 0 1726 0 0 561 701 581 5179 0 0 2.84232 2.84232 -99.9216 -2.84232 0 0 1.01997e+06 3529.29 0.32 0.03 0.13 -1 -1 0.32 0.00990663 0.00877004 62 29 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_060.v common 8.22 vpr 64.79 MiB -1 -1 0.13 21112 1 0.01 -1 -1 33208 -1 -1 15 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 66348 32 32 431 332 1 224 79 17 17 289 -1 unnamed_device 26.3 MiB 2.13 1093 64.8 MiB 0.08 0.00 4.99359 -148.63 -4.99359 4.99359 1.12 0.000199889 0.000165354 0.0207476 0.0175439 46 2866 27 6.95648e+06 217135 828058. 2865.25 2.70 0.106121 0.0865357 28066 200906 -1 2376 22 1980 2932 229342 47140 0 0 229342 47140 2932 2272 0 0 9025 7905 0 0 16408 10294 0 0 2932 2403 0 0 99398 12107 0 0 98647 12159 0 0 2932 0 0 952 1133 1077 8532 0 0 5.05225 5.05225 -167.912 -5.05225 0 0 1.01997e+06 3529.29 0.34 0.06 0.14 -1 -1 0.34 0.0174423 0.0157578 95 62 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_061.v common 8.90 vpr 64.20 MiB -1 -1 0.10 20992 1 0.01 -1 -1 33188 -1 -1 23 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65740 32 32 336 268 1 169 87 17 17 289 -1 unnamed_device 25.7 MiB 1.09 728 64.2 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-1 -1 33224 -1 -1 16 29 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 66232 29 32 355 287 1 186 77 17 17 289 -1 unnamed_device 26.1 MiB 1.36 837 64.7 MiB 0.06 0.00 3.16908 -99.2771 -3.16908 3.16908 0.75 0.000179186 0.000150972 0.0155466 0.0130437 40 2676 34 6.95648e+06 231611 706193. 2443.58 15.96 0.168222 0.147943 26914 176310 -1 2443 24 2092 3090 333908 69993 0 0 333908 69993 3090 2627 0 0 10246 9003 0 0 19802 12410 0 0 3090 2828 0 0 147304 22164 0 0 150376 20961 0 0 3090 0 0 998 1083 1044 8211 0 0 3.79376 3.79376 -133.678 -3.79376 0 0 926341. 3205.33 0.31 0.07 0.11 -1 -1 0.31 0.0144102 0.0128452 80 56 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_067.v common 8.49 vpr 64.24 MiB -1 -1 0.11 20700 1 0.01 -1 -1 33092 -1 -1 16 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65780 32 32 358 289 1 173 80 17 17 289 -1 unnamed_device 25.8 MiB 1.20 606 64.2 MiB 0.07 0.00 3.91028 -109.378 -3.91028 3.91028 0.95 0.000182232 0.000149933 0.024368 0.0216 46 2142 38 6.95648e+06 231611 828058. 2865.25 4.33 0.16049 0.138621 28066 200906 -1 1576 37 2113 3041 187535 48170 0 0 187535 48170 3041 2594 0 0 8864 7819 0 0 16239 10017 0 0 3041 2762 0 0 73770 12656 0 0 82580 12322 0 0 3041 0 0 928 1131 984 8272 0 0 4.23706 4.23706 -137.95 -4.23706 0 0 1.01997e+06 3529.29 0.33 0.06 0.14 -1 -1 0.33 0.0187481 0.0164544 72 51 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_068.v common 13.54 vpr 64.30 MiB -1 -1 0.11 20864 1 0.00 -1 -1 33144 -1 -1 14 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65844 32 32 353 285 1 178 78 17 17 289 -1 unnamed_device 25.8 MiB 1.74 726 64.3 MiB 0.12 0.01 3.66779 -114.583 -3.66779 3.66779 0.92 0.00193737 0.00189111 0.0225007 0.0194888 46 2389 23 6.95648e+06 202660 828058. 2865.25 8.82 0.17235 0.131538 28066 200906 -1 1847 22 1283 1946 135919 31383 0 0 135919 31383 1946 1653 0 0 6210 5430 0 0 10409 6975 0 0 1946 1731 0 0 53894 8268 0 0 61514 7326 0 0 1946 0 0 663 704 773 5756 0 0 4.32986 4.32986 -137.188 -4.32986 0 0 1.01997e+06 3529.29 0.33 0.04 0.15 -1 -1 0.33 0.0144937 0.0130881 73 48 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_069.v common 9.13 vpr 63.91 MiB -1 -1 0.09 20608 1 0.00 -1 -1 33152 -1 -1 10 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65448 32 32 276 237 1 155 74 17 17 289 -1 unnamed_device 25.5 MiB 2.71 691 63.9 MiB 0.05 0.00 3.30448 -104.445 -3.30448 3.30448 0.76 0.000141902 0.000117721 0.0105041 0.00877777 46 1866 27 6.95648e+06 144757 828058. 2865.25 3.81 0.08725 0.0752011 28066 200906 -1 1436 21 1130 1469 105546 24266 0 0 105546 24266 1469 1332 0 0 4829 4247 0 0 7710 5434 0 0 1469 1380 0 0 40508 6551 0 0 49561 5322 0 0 1469 0 0 339 282 340 3142 0 0 3.73151 3.73151 -124.46 -3.73151 0 0 1.01997e+06 3529.29 0.41 0.03 0.13 -1 -1 0.41 0.00958649 0.00859111 61 31 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_070.v common 13.15 vpr 64.07 MiB -1 -1 0.11 20872 1 0.01 -1 -1 33364 -1 -1 12 31 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65604 31 32 319 272 1 165 75 17 17 289 -1 unnamed_device 25.5 MiB 1.79 628 64.1 MiB 0.05 0.00 3.15532 -100.374 -3.15532 3.15532 0.75 0.000146511 0.000119377 0.0129832 0.010831 42 2381 41 6.95648e+06 173708 744469. 2576.02 8.83 0.113941 0.0957083 27202 183097 -1 1645 22 1347 1965 164385 36817 0 0 164385 36817 1965 1665 0 0 6482 5729 0 0 11409 7576 0 0 1965 1684 0 0 67430 10668 0 0 75134 9495 0 0 1965 0 0 618 635 559 5013 0 0 3.32487 3.32487 -123.573 -3.32487 0 0 949917. 3286.91 0.30 0.05 0.11 -1 -1 0.30 0.01162 0.0102194 68 60 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_071.v common 6.58 vpr 64.19 MiB -1 -1 0.11 20600 1 0.02 -1 -1 33372 -1 -1 22 30 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65728 30 32 329 273 1 160 84 17 17 289 -1 unnamed_device 25.7 MiB 0.70 618 64.2 MiB 0.05 0.00 2.4971 -76.2077 -2.4971 2.4971 0.76 0.000162147 0.000134814 0.0114685 0.00936078 46 1762 22 6.95648e+06 318465 828058. 2865.25 3.10 0.0837286 0.0718042 28066 200906 -1 1381 20 1038 1595 104720 25430 0 0 104720 25430 1595 1279 0 0 5184 4334 0 0 8416 5828 0 0 1595 1373 0 0 42612 5962 0 0 45318 6654 0 0 1595 0 0 557 763 747 5496 0 0 3.07917 3.07917 -97.767 -3.07917 0 0 1.01997e+06 3529.29 0.32 0.03 0.13 -1 -1 0.32 0.0112178 0.0100102 71 52 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_072.v common 6.19 vpr 64.13 MiB -1 -1 0.11 20752 1 0.01 -1 -1 33360 -1 -1 28 28 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65672 28 32 277 229 1 155 88 17 17 289 -1 unnamed_device 25.6 MiB 0.51 783 64.1 MiB 0.05 0.00 3.09514 -86.8271 -3.09514 3.09514 0.88 0.000187602 0.000156098 0.0107147 0.00906456 36 2233 40 6.95648e+06 405319 648988. 2245.63 3.01 0.0653894 0.0561525 26050 158493 -1 1832 22 1267 1989 181228 37189 0 0 181228 37189 1989 1471 0 0 6505 5589 0 0 11263 7567 0 0 1989 1592 0 0 81455 10322 0 0 78027 10648 0 0 1989 0 0 722 922 1021 7282 0 0 3.92206 3.92206 -113.225 -3.92206 0 0 828058. 2865.25 0.26 0.04 0.10 -1 -1 0.26 0.0102655 0.00913911 72 20 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_073.v common 8.69 vpr 64.25 MiB -1 -1 0.11 20944 1 0.01 -1 -1 33176 -1 -1 12 30 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65796 30 32 317 269 1 149 74 17 17 289 -1 unnamed_device 25.7 MiB 0.91 579 64.3 MiB 0.06 0.00 2.79633 -89.7531 -2.79633 2.79633 1.02 0.00015216 0.000124903 0.0159159 0.0132976 38 1890 39 6.95648e+06 173708 678818. 2348.85 4.93 0.13114 0.112355 26626 170182 -1 1402 21 1307 1828 128284 30001 0 0 128284 30001 1828 1574 0 0 5710 5032 0 0 9746 6458 0 0 1828 1610 0 0 58366 6981 0 0 50806 8346 0 0 1828 0 0 521 349 543 4511 0 0 3.16502 3.16502 -114.561 -3.16502 0 0 902133. 3121.57 0.28 0.03 0.10 -1 -1 0.28 0.0104586 0.00927468 60 58 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_074.v common 8.76 vpr 64.27 MiB -1 -1 0.12 20856 1 0.01 -1 -1 33168 -1 -1 11 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65812 32 32 335 282 1 178 75 17 17 289 -1 unnamed_device 25.9 MiB 1.72 654 64.3 MiB 0.05 0.00 2.80395 -97.9853 -2.80395 2.80395 1.25 0.000148238 0.000120537 0.0147132 0.0122567 50 1900 25 6.95648e+06 159232 902133. 3121.57 3.33 0.0857563 0.0751085 28642 213929 -1 1591 21 1391 2030 142589 35097 0 0 142589 35097 2030 1621 0 0 6490 5812 0 0 11621 7564 0 0 2030 1636 0 0 61377 8139 0 0 59041 10325 0 0 2030 0 0 639 656 394 4997 0 0 3.51016 3.51016 -129.728 -3.51016 0 0 1.08113e+06 3740.92 0.49 0.04 0.18 -1 -1 0.49 0.0135181 0.0122304 72 62 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_075.v common 6.78 vpr 64.41 MiB -1 -1 0.11 20484 1 0.01 -1 -1 33208 -1 -1 24 31 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65960 31 32 293 230 1 168 87 17 17 289 -1 unnamed_device 25.8 MiB 0.60 714 64.4 MiB 0.05 0.00 3.89128 -102.001 -3.89128 3.89128 1.21 0.000156809 0.000129917 0.0117844 0.00984287 46 2151 34 6.95648e+06 347416 828058. 2865.25 1.98 0.0598804 0.0518623 28066 200906 -1 1615 21 1158 1893 165155 45241 0 0 165155 45241 1893 1398 0 0 5941 5228 0 0 10139 6665 0 0 1893 1553 0 0 74385 14959 0 0 70904 15438 0 0 1893 0 0 735 648 792 6132 0 0 3.78902 3.78902 -120.509 -3.78902 0 0 1.01997e+06 3529.29 0.45 0.05 0.29 -1 -1 0.45 0.0135171 0.0122965 74 -1 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_076.v common 9.66 vpr 64.30 MiB -1 -1 0.11 20848 1 0.01 -1 -1 33004 -1 -1 13 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65848 32 32 350 275 1 196 77 17 17 289 -1 unnamed_device 25.7 MiB 1.61 858 64.3 MiB 0.06 0.00 3.94537 -126.254 -3.94537 3.94537 0.90 0.000166062 0.000136688 0.016111 0.0136108 50 2943 45 6.95648e+06 188184 902133. 3121.57 5.03 0.136429 0.117394 28642 213929 -1 2239 21 1752 2558 236554 51736 0 0 236554 51736 2558 2217 0 0 8337 7270 0 0 14974 9836 0 0 2558 2298 0 0 102819 14837 0 0 105308 15278 0 0 2558 0 0 806 643 799 6418 0 0 4.34566 4.34566 -151.325 -4.34566 0 0 1.08113e+06 3740.92 0.41 0.06 0.14 -1 -1 0.41 0.0147114 0.0132902 82 31 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_077.v common 22.01 vpr 64.73 MiB -1 -1 0.13 20844 1 0.01 -1 -1 33128 -1 -1 24 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 66284 32 32 385 308 1 179 88 17 17 289 -1 unnamed_device 26.4 MiB 2.24 969 64.7 MiB 0.11 0.00 3.62123 -113.1 -3.62123 3.62123 1.53 0.000180644 0.000149592 0.0183834 0.0152859 40 2683 34 6.95648e+06 347416 706193. 2443.58 14.44 0.173674 0.150293 26914 176310 -1 2313 28 1713 2999 505336 158471 0 0 505336 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fixed_k6_frac_2ripple_N8_22nm.xml mult_080.v common 7.87 vpr 64.45 MiB -1 -1 0.13 20840 1 0.02 -1 -1 33452 -1 -1 14 30 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65992 30 32 375 299 1 179 76 17 17 289 -1 unnamed_device 25.8 MiB 1.03 630 64.4 MiB 0.06 0.00 3.71763 -111.147 -3.71763 3.71763 0.83 0.000233112 0.000194733 0.0194264 0.0169254 48 2057 25 6.95648e+06 202660 865456. 2994.66 3.10 0.111305 0.0975219 28354 207349 -1 1661 22 1790 2506 187621 45523 0 0 187621 45523 2506 2208 0 0 8105 7017 0 0 14347 9364 0 0 2506 2310 0 0 74325 12388 0 0 85832 12236 0 0 2506 0 0 716 832 775 6533 0 0 3.99132 3.99132 -134.723 -3.99132 0 0 1.05005e+06 3633.38 0.60 0.05 0.24 -1 -1 0.60 0.0142511 0.01273 76 58 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_081.v common 10.92 vpr 64.30 MiB -1 -1 0.12 20936 1 0.01 -1 -1 33252 -1 -1 14 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65840 32 32 340 270 1 193 78 17 17 289 -1 unnamed_device 25.7 MiB 2.21 825 64.3 MiB 0.06 0.00 4.0079 -119.402 -4.0079 4.0079 0.87 0.000183831 0.000153534 0.0166413 0.0141862 54 2190 21 6.95648e+06 202660 949917. 3286.91 4.69 0.138595 0.123274 29506 232905 -1 1800 20 1574 2469 195900 44140 0 0 195900 44140 2469 2022 0 0 7813 6844 0 0 13962 9006 0 0 2469 2129 0 0 77490 12766 0 0 91697 11373 0 0 2469 0 0 895 1094 1155 9013 0 0 4.15082 4.15082 -137.276 -4.15082 0 0 1.17392e+06 4061.99 0.61 0.05 0.17 -1 -1 0.61 0.0130974 0.0118341 80 31 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_082.v common 10.00 vpr 64.37 MiB -1 -1 0.11 20876 1 0.01 -1 -1 33252 -1 -1 14 31 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65912 31 32 340 275 1 187 77 17 17 289 -1 unnamed_device 25.9 MiB 3.09 876 64.4 MiB 0.11 0.00 4.77836 -130.82 -4.77836 4.77836 0.99 0.000195754 0.000162624 0.0200611 0.0179475 44 2541 31 6.95648e+06 202660 787024. 2723.27 3.11 0.0852722 0.0758062 27778 195446 -1 2006 20 1224 1812 155979 32911 0 0 155979 32911 1812 1414 0 0 5892 5170 0 0 10396 6868 0 0 1812 1520 0 0 66938 9204 0 0 69129 8735 0 0 1812 0 0 588 509 564 4967 0 0 4.38386 4.38386 -143.204 -4.38386 0 0 997811. 3452.63 0.34 0.04 0.13 -1 -1 0.34 0.0133583 0.0121365 79 43 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_083.v common 11.53 vpr 64.54 MiB -1 -1 0.11 20900 1 0.01 -1 -1 33308 -1 -1 21 30 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 66084 30 32 377 310 1 170 83 17 17 289 -1 unnamed_device 26.0 MiB 1.80 833 64.5 MiB 0.18 0.00 3.74802 -117.262 -3.74802 3.74802 1.44 0.000189691 0.000158035 0.0164517 0.013741 38 2732 34 6.95648e+06 303989 678818. 2348.85 5.38 0.0907645 0.0779398 26626 170182 -1 2019 18 1203 1853 158995 34049 0 0 158995 34049 1853 1513 0 0 6071 5299 0 0 9661 6784 0 0 1853 1676 0 0 68660 9436 0 0 70897 9341 0 0 1853 0 0 650 776 759 5846 0 0 4.31231 4.31231 -148.608 -4.31231 0 0 902133. 3121.57 0.79 0.08 0.15 -1 -1 0.79 0.0289577 0.0277208 74 78 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_084.v common 14.18 vpr 64.59 MiB -1 -1 0.11 20952 1 0.01 -1 -1 33328 -1 -1 13 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 66140 32 32 365 294 1 177 77 17 17 289 -1 unnamed_device 26.0 MiB 1.19 725 64.6 MiB 0.20 0.00 3.77393 -114.341 -3.77393 3.77393 1.29 0.000208264 0.00017622 0.0375146 0.034217 48 2612 50 6.95648e+06 188184 865456. 2994.66 9.05 0.218186 0.193063 28354 207349 -1 2029 20 1551 2516 265963 60109 0 0 265963 60109 2516 2075 0 0 8407 7373 0 0 14885 9926 0 0 2516 2153 0 0 119034 18370 0 0 118605 20212 0 0 2516 0 0 965 1070 881 7582 0 0 3.91407 3.91407 -143.126 -3.91407 0 0 1.05005e+06 3633.38 0.37 0.06 0.16 -1 -1 0.37 0.0143573 0.0129723 72 54 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_085.v common 7.77 vpr 64.38 MiB -1 -1 0.12 21032 1 0.01 -1 -1 33272 -1 -1 16 29 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65928 29 32 378 310 1 170 77 17 17 289 -1 unnamed_device 25.8 MiB 1.05 685 64.4 MiB 0.05 0.00 3.26967 -101.645 -3.26967 3.26967 0.83 0.00016631 0.000134906 0.0129384 0.0109467 44 2142 22 6.95648e+06 231611 787024. 2723.27 3.71 0.102021 0.0873379 27778 195446 -1 1595 21 1277 1892 153197 33610 0 0 153197 33610 1892 1497 0 0 5964 5181 0 0 10093 6968 0 0 1892 1541 0 0 63652 9867 0 0 69704 8556 0 0 1892 0 0 615 664 509 5070 0 0 3.69672 3.69672 -126.21 -3.69672 0 0 997811. 3452.63 0.42 0.05 0.16 -1 -1 0.42 0.0136247 0.0121834 73 79 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_086.v common 6.09 vpr 63.91 MiB -1 -1 0.10 20736 1 0.01 -1 -1 33128 -1 -1 10 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65440 32 32 243 205 1 139 74 17 17 289 -1 unnamed_device 25.4 MiB 1.06 655 63.9 MiB 0.04 0.00 2.91658 -88.9369 -2.91658 2.91658 0.93 0.000132738 0.000111388 0.00904815 0.00763705 38 1824 20 6.95648e+06 144757 678818. 2348.85 1.60 0.0464988 0.0395683 26626 170182 -1 1611 21 1114 1651 132469 27877 0 0 132469 27877 1651 1413 0 0 5025 4421 0 0 8501 5559 0 0 1651 1446 0 0 57576 7723 0 0 58065 7315 0 0 1651 0 0 537 559 598 4495 0 0 3.10387 3.10387 -110.49 -3.10387 0 0 902133. 3121.57 0.57 0.12 0.18 -1 -1 0.57 0.0116819 0.0105735 53 -1 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_087.v common 8.74 vpr 64.61 MiB -1 -1 0.13 20744 1 0.01 -1 -1 33352 -1 -1 23 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 66156 32 32 373 302 1 174 87 17 17 289 -1 unnamed_device 26.1 MiB 3.15 821 64.6 MiB 0.07 0.00 3.91556 -109.001 -3.91556 3.91556 0.79 0.00017542 0.000144036 0.0163196 0.0135365 44 2491 35 6.95648e+06 332941 787024. 2723.27 2.45 0.0827384 0.065133 27778 195446 -1 1853 21 1131 1786 148503 32728 0 0 148503 32728 1786 1455 0 0 6015 5260 0 0 10681 7199 0 0 1786 1564 0 0 64287 8672 0 0 63948 8578 0 0 1786 0 0 655 647 620 5580 0 0 3.8554 3.8554 -133.464 -3.8554 0 0 997811. 3452.63 0.40 0.10 0.13 -1 -1 0.40 0.0127346 0.011381 76 62 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_088.v common 8.81 vpr 64.64 MiB -1 -1 0.12 21012 1 0.02 -1 -1 33252 -1 -1 13 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 66192 32 32 397 314 1 188 77 17 17 289 -1 unnamed_device 26.2 MiB 0.60 756 64.6 MiB 0.05 0.00 3.49708 -113.705 -3.49708 3.49708 1.14 0.000180208 0.00014805 0.01543 0.0135544 48 2480 46 6.95648e+06 188184 865456. 2994.66 4.33 0.128687 0.111052 28354 207349 -1 1918 24 1925 2877 245386 61829 0 0 245386 61829 2877 2471 0 0 9274 8047 0 0 17728 11230 0 0 2877 2625 0 0 101876 20233 0 0 110754 17223 0 0 2877 0 0 952 1193 1122 8470 0 0 4.14461 4.14461 -151.019 -4.14461 0 0 1.05005e+06 3633.38 0.58 0.06 0.13 -1 -1 0.58 0.0155164 0.0138485 78 62 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_089.v common 8.70 vpr 64.21 MiB -1 -1 0.11 20552 1 0.01 -1 -1 33280 -1 -1 11 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65756 32 32 269 231 1 166 75 17 17 289 -1 unnamed_device 25.7 MiB 1.62 764 64.2 MiB 0.06 0.00 3.28067 -100.55 -3.28067 3.28067 1.03 0.000130749 0.000106559 0.0134721 0.0113845 44 2152 34 6.95648e+06 159232 787024. 2723.27 3.55 0.0837819 0.0712677 27778 195446 -1 1681 21 1185 1481 117406 26772 0 0 117406 26772 1481 1364 0 0 4949 4441 0 0 8096 5711 0 0 1481 1392 0 0 50650 6915 0 0 50749 6949 0 0 1481 0 0 296 189 289 2911 0 0 3.71571 3.71571 -122.326 -3.71571 0 0 997811. 3452.63 0.36 0.04 0.12 -1 -1 0.36 0.0111873 0.010111 68 26 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_090.v common 11.71 vpr 63.82 MiB -1 -1 0.13 20452 1 0.01 -1 -1 33068 -1 -1 13 31 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65352 31 32 245 205 1 144 76 17 17 289 -1 unnamed_device 25.3 MiB 1.15 516 63.8 MiB 0.05 0.00 2.78823 -84.0827 -2.78823 2.78823 0.83 0.000127398 0.000103679 0.0117964 0.00972803 40 1802 36 6.95648e+06 188184 706193. 2443.58 7.51 0.111964 0.0961237 26914 176310 -1 1407 25 1360 1872 160303 38414 0 0 160303 38414 1872 1573 0 0 6335 5542 0 0 11991 8044 0 0 1872 1663 0 0 68951 10090 0 0 69282 11502 0 0 1872 0 0 512 563 512 4617 0 0 3.17332 3.17332 -113.52 -3.17332 0 0 926341. 3205.33 0.29 0.04 0.11 -1 -1 0.29 0.010113 0.00898684 57 -1 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_091.v common 8.84 vpr 64.34 MiB -1 -1 0.12 20784 1 0.01 -1 -1 33104 -1 -1 15 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65884 32 32 348 274 1 202 79 17 17 289 -1 unnamed_device 25.7 MiB 1.55 789 64.3 MiB 0.09 0.00 3.75407 -122.757 -3.75407 3.75407 1.66 0.000211649 0.000172428 0.020069 0.0171999 46 2988 36 6.95648e+06 217135 828058. 2865.25 2.89 0.109317 0.0957758 28066 200906 -1 2090 20 1755 2358 180226 40253 0 0 180226 40253 2358 2126 0 0 7402 6491 0 0 12446 8296 0 0 2358 2160 0 0 73080 10944 0 0 82582 10236 0 0 2358 0 0 603 420 662 5283 0 0 4.4037 4.4037 -152.061 -4.4037 0 0 1.01997e+06 3529.29 0.46 0.05 0.13 -1 -1 0.46 0.0141167 0.0126613 85 31 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_092.v common 8.36 vpr 64.38 MiB -1 -1 0.12 21060 1 0.01 -1 -1 33084 -1 -1 14 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65924 32 32 356 289 1 196 78 17 17 289 -1 unnamed_device 25.9 MiB 1.02 781 64.4 MiB 0.06 0.00 4.05782 -121.625 -4.05782 4.05782 0.87 0.000178496 0.000147994 0.0153314 0.0129821 48 2388 47 6.95648e+06 202660 865456. 2994.66 4.19 0.13862 0.120235 28354 207349 -1 1896 23 1689 2410 200204 44784 0 0 200204 44784 2410 2076 0 0 8328 7288 0 0 15070 10351 0 0 2410 2141 0 0 82959 12018 0 0 89027 10910 0 0 2410 0 0 721 721 764 6568 0 0 4.46096 4.46096 -146.347 -4.46096 0 0 1.05005e+06 3633.38 0.46 0.07 0.15 -1 -1 0.46 0.0175887 0.0159687 82 53 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_093.v common 11.26 vpr 64.25 MiB -1 -1 0.12 20864 1 0.00 -1 -1 33376 -1 -1 17 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65792 32 32 349 260 1 195 81 17 17 289 -1 unnamed_device 25.7 MiB 0.61 862 64.2 MiB 0.10 0.00 4.06272 -117.727 -4.06272 4.06272 1.16 0.000178853 0.000148238 0.0220004 0.0186174 50 2370 25 6.95648e+06 246087 902133. 3121.57 6.70 0.163893 0.140864 28642 213929 -1 1979 22 1793 2956 227789 52442 0 0 227789 52442 2956 2356 0 0 9600 8254 0 0 17204 11168 0 0 2956 2580 0 0 97656 13758 0 0 97417 14326 0 0 2956 0 0 1163 1189 1611 10513 0 0 4.477 4.477 -142.85 -4.477 0 0 1.08113e+06 3740.92 0.42 0.07 0.14 -1 -1 0.42 0.0189355 0.0142039 83 -1 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_094.v common 8.08 vpr 64.28 MiB -1 -1 0.13 20760 1 0.01 -1 -1 32948 -1 -1 21 30 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65824 30 32 316 264 1 159 83 17 17 289 -1 unnamed_device 25.6 MiB 1.07 632 64.3 MiB 0.08 0.00 2.83043 -79.56 -2.83043 2.83043 1.07 0.000188854 0.000160067 0.0241513 0.0219106 38 2218 29 6.95648e+06 303989 678818. 2348.85 3.77 0.140568 0.125289 26626 170182 -1 1432 20 1272 1972 132688 30078 0 0 132688 30078 1972 1490 0 0 6018 5250 0 0 9836 6588 0 0 1972 1618 0 0 59370 6967 0 0 53520 8165 0 0 1972 0 0 700 651 611 5720 0 0 3.19827 3.19827 -101.641 -3.19827 0 0 902133. 3121.57 0.33 0.04 0.11 -1 -1 0.33 0.0128846 0.0116036 69 47 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_095.v common 8.03 vpr 63.80 MiB -1 -1 0.11 20516 1 0.01 -1 -1 33280 -1 -1 14 27 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65336 27 32 255 219 1 130 73 17 17 289 -1 unnamed_device 25.2 MiB 0.47 469 63.8 MiB 0.04 0.00 2.4231 -73.3364 -2.4231 2.4231 1.29 0.000118697 9.6246e-05 0.00989678 0.00847095 36 1601 31 6.95648e+06 202660 648988. 2245.63 3.45 0.0930207 0.0790552 26050 158493 -1 1227 22 990 1205 103484 23381 0 0 103484 23381 1205 1100 0 0 4229 3504 0 0 6444 4796 0 0 1205 1125 0 0 48339 5830 0 0 42062 7026 0 0 1205 0 0 215 177 220 2275 0 0 3.19822 3.19822 -97.5944 -3.19822 0 0 828058. 2865.25 0.64 0.03 0.16 -1 -1 0.64 0.0106208 0.00949212 54 26 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_096.v common 9.36 vpr 64.83 MiB -1 -1 0.12 20956 1 0.01 -1 -1 33232 -1 -1 16 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 66384 32 32 421 327 1 224 80 17 17 289 -1 unnamed_device 26.4 MiB 1.11 958 64.8 MiB 0.09 0.00 3.20225 -108.346 -3.20225 3.20225 0.82 0.00023241 0.000198643 0.0232353 0.0197038 54 3066 50 6.95648e+06 231611 949917. 3286.91 4.54 0.162651 0.14163 29506 232905 -1 2159 24 1986 3124 235827 54600 0 0 235827 54600 3124 2383 0 0 9614 8467 0 0 18031 10953 0 0 3124 2693 0 0 99028 16393 0 0 102906 13711 0 0 3124 0 0 1138 1399 1116 9669 0 0 4.02271 4.02271 -137.102 -4.02271 0 0 1.17392e+06 4061.99 0.51 0.08 0.25 -1 -1 0.51 0.0248787 0.0216021 95 62 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_097.v common 13.50 vpr 64.27 MiB -1 -1 0.13 20864 1 0.02 -1 -1 33176 -1 -1 15 31 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65816 31 32 365 296 1 190 78 17 17 289 -1 unnamed_device 25.7 MiB 4.74 1028 64.3 MiB 0.06 0.00 4.5044 -130.841 -4.5044 4.5044 0.88 0.000160274 0.000130554 0.0138325 0.0115956 38 2834 30 6.95648e+06 217135 678818. 2348.85 5.66 0.107514 0.0958193 26626 170182 -1 2362 24 1921 2908 285337 54639 0 0 285337 54639 2908 2250 0 0 8857 7893 0 0 15670 9920 0 0 2908 2455 0 0 125160 16814 0 0 129834 15307 0 0 2908 0 0 987 1343 1354 9336 0 0 4.59111 4.59111 -157.994 -4.59111 0 0 902133. 3121.57 0.33 0.16 0.11 -1 -1 0.33 0.0254748 0.0235029 82 60 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_098.v common 14.71 vpr 64.08 MiB -1 -1 0.11 21120 1 0.01 -1 -1 33192 -1 -1 11 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65620 32 32 331 280 1 171 75 17 17 289 -1 unnamed_device 25.8 MiB 3.36 823 64.1 MiB 0.05 0.00 3.30244 -111.934 -3.30244 3.30244 0.88 0.000144109 0.000116511 0.0128918 0.0107211 38 2344 23 6.95648e+06 159232 678818. 2348.85 8.23 0.129553 0.110378 26626 170182 -1 2047 18 1285 1866 160461 32688 0 0 160461 32688 1866 1527 0 0 6051 5272 0 0 9459 6700 0 0 1866 1560 0 0 74326 8072 0 0 66893 9557 0 0 1866 0 0 581 430 559 4864 0 0 3.68266 3.68266 -139.132 -3.68266 0 0 902133. 3121.57 0.43 0.05 0.12 -1 -1 0.43 0.0144228 0.0132207 70 62 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_099.v common 5.08 vpr 64.17 MiB -1 -1 0.12 20728 1 0.01 -1 -1 33188 -1 -1 22 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65712 32 32 326 263 1 169 86 17 17 289 -1 unnamed_device 25.8 MiB 0.34 813 64.2 MiB 0.07 0.00 3.46513 -100.524 -3.46513 3.46513 0.85 0.000172866 0.000142139 0.0152942 0.0124387 46 2252 22 6.95648e+06 318465 828058. 2865.25 1.69 0.0647358 0.0551641 28066 200906 -1 1865 21 1214 1936 148233 32372 0 0 148233 32372 1936 1606 0 0 6030 5281 0 0 9924 6632 0 0 1936 1704 0 0 59615 9199 0 0 68792 7950 0 0 1936 0 0 722 550 800 5914 0 0 3.80451 3.80451 -120.946 -3.80451 0 0 1.01997e+06 3529.29 0.33 0.04 0.13 -1 -1 0.33 0.0116906 0.0104938 74 31 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_100.v common 8.85 vpr 64.34 MiB -1 -1 0.13 20936 1 0.00 -1 -1 33192 -1 -1 25 31 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65884 31 32 373 294 1 188 88 17 17 289 -1 unnamed_device 25.9 MiB 0.78 763 64.3 MiB 0.06 0.00 3.58273 -103.837 -3.58273 3.58273 1.05 0.000167294 0.000136941 0.0149704 0.0124687 48 2088 23 6.95648e+06 361892 865456. 2994.66 4.41 0.105066 0.0896101 28354 207349 -1 1669 21 1405 2061 148950 36413 0 0 148950 36413 2061 1602 0 0 7217 6038 0 0 12080 8631 0 0 2061 1762 0 0 55941 9829 0 0 69590 8551 0 0 2061 0 0 656 847 859 6485 0 0 4.00977 4.00977 -126.774 -4.00977 0 0 1.05005e+06 3633.38 0.37 0.04 0.13 -1 -1 0.37 0.0140551 0.0125844 83 46 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_101.v common 9.58 vpr 64.24 MiB -1 -1 0.10 20736 1 0.01 -1 -1 33268 -1 -1 16 30 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65784 30 32 325 268 1 166 78 17 17 289 -1 unnamed_device 25.9 MiB 0.93 754 64.2 MiB 0.05 0.00 2.87605 -84.5862 -2.87605 2.87605 0.78 0.000151094 0.000123144 0.0124495 0.0103639 52 2088 39 6.95648e+06 231611 926341. 3205.33 5.67 0.127629 0.110187 29218 227130 -1 1567 23 1270 2067 151136 33746 0 0 151136 33746 2067 1651 0 0 6635 5755 0 0 12446 8057 0 0 2067 1819 0 0 59958 8759 0 0 67963 7705 0 0 2067 0 0 797 783 938 6675 0 0 2.98482 2.98482 -102.595 -2.98482 0 0 1.14541e+06 3963.36 0.53 0.04 0.16 -1 -1 0.53 0.0117035 0.0103951 68 46 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_102.v common 8.87 vpr 64.72 MiB -1 -1 0.11 21172 1 0.01 -1 -1 33308 -1 -1 14 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 66276 32 32 350 275 1 208 78 17 17 289 -1 unnamed_device 26.1 MiB 1.55 897 64.7 MiB 0.13 0.00 3.74967 -121.549 -3.74967 3.74967 0.89 0.000861319 0.000805432 0.0431684 0.04048 48 3452 42 6.95648e+06 202660 865456. 2994.66 3.98 0.128673 0.115539 28354 207349 -1 2299 35 2699 3928 466380 137270 0 0 466380 137270 3928 3494 0 0 12025 10699 0 0 25983 15135 0 0 3928 3645 0 0 219231 51961 0 0 201285 52336 0 0 3928 0 0 1229 1355 1620 10676 0 0 4.29401 4.29401 -152.048 -4.29401 0 0 1.05005e+06 3633.38 0.42 0.11 0.22 -1 -1 0.42 0.0204323 0.0181905 88 31 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_103.v common 9.98 vpr 64.36 MiB -1 -1 0.11 20848 1 0.02 -1 -1 33268 -1 -1 18 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65904 32 32 386 307 1 187 82 17 17 289 -1 unnamed_device 25.9 MiB 0.92 781 64.4 MiB 0.05 0.00 3.70063 -117.46 -3.70063 3.70063 0.83 0.000171496 0.000139687 0.013854 0.0115889 52 2210 29 6.95648e+06 260562 926341. 3205.33 5.91 0.152135 0.130764 29218 227130 -1 1606 21 1382 1859 146132 34360 0 0 146132 34360 1859 1584 0 0 6071 5246 0 0 10006 6938 0 0 1859 1702 0 0 62192 8752 0 0 64145 10138 0 0 1859 0 0 477 530 504 4484 0 0 3.79092 3.79092 -137.547 -3.79092 0 0 1.14541e+06 3963.36 0.49 0.05 0.15 -1 -1 0.49 0.015309 0.0136545 80 59 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_104.v common 11.40 vpr 63.88 MiB -1 -1 0.13 20520 1 0.01 -1 -1 33256 -1 -1 12 29 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65416 29 32 269 229 1 132 73 17 17 289 -1 unnamed_device 25.3 MiB 4.72 489 63.9 MiB 0.03 0.00 3.26592 -84.8562 -3.26592 3.26592 0.79 0.000124381 0.000100537 0.00861429 0.00719451 36 1479 29 6.95648e+06 173708 648988. 2245.63 3.28 0.0675145 0.0571182 26050 158493 -1 1177 16 773 1048 80897 18477 0 0 80897 18477 1048 872 0 0 3653 3110 0 0 5384 4140 0 0 1048 942 0 0 35612 4554 0 0 34152 4859 0 0 1048 0 0 275 348 340 2669 0 0 2.95672 2.95672 -97.8748 -2.95672 0 0 828058. 2865.25 0.39 0.03 0.11 -1 -1 0.39 0.0125034 0.0114515 53 28 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_105.v common 6.08 vpr 64.05 MiB -1 -1 0.11 21036 1 0.01 -1 -1 33328 -1 -1 11 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65584 32 32 310 266 1 163 75 17 17 289 -1 unnamed_device 25.5 MiB 1.06 700 64.0 MiB 0.04 0.00 3.06285 -104.202 -3.06285 3.06285 0.74 0.00013564 0.000109895 0.00903594 0.00754778 44 1840 24 6.95648e+06 159232 787024. 2723.27 1.54 0.048305 0.0415521 27778 195446 -1 1421 19 1117 1420 99913 22569 0 0 99913 22569 1420 1275 0 0 4618 4022 0 0 7606 5321 0 0 1420 1317 0 0 38714 5833 0 0 46135 4801 0 0 1420 0 0 303 225 204 2758 0 0 3.28982 3.28982 -119.422 -3.28982 0 0 997811. 3452.63 0.50 0.03 0.12 -1 -1 0.50 0.0092318 0.00826809 64 55 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_106.v common 6.43 vpr 64.21 MiB -1 -1 0.12 21164 1 0.01 -1 -1 33156 -1 -1 23 31 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65748 31 32 326 261 1 172 86 17 17 289 -1 unnamed_device 25.8 MiB 1.09 749 64.2 MiB 0.06 0.00 3.43718 -100.911 -3.43718 3.43718 1.29 0.000157286 0.000122366 0.0130909 0.0107912 46 2170 27 6.95648e+06 332941 828058. 2865.25 1.73 0.0650666 0.055534 28066 200906 -1 1743 23 1470 2332 167751 38184 0 0 167751 38184 2332 1797 0 0 7330 6511 0 0 12423 8315 0 0 2332 1974 0 0 68167 10044 0 0 75167 9543 0 0 2332 0 0 862 1210 1100 8216 0 0 3.66956 3.66956 -126.568 -3.66956 0 0 1.01997e+06 3529.29 0.45 0.04 0.14 -1 -1 0.45 0.0117956 0.0105294 77 29 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_107.v common 8.04 vpr 64.07 MiB -1 -1 0.13 20672 1 0.02 -1 -1 33196 -1 -1 13 29 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65612 29 32 262 224 1 161 74 17 17 289 -1 unnamed_device 25.6 MiB 1.51 616 64.1 MiB 0.05 0.00 3.40298 -96.0998 -3.40298 3.40298 1.12 0.00012628 0.000102984 0.00990656 0.00830281 38 2239 31 6.95648e+06 188184 678818. 2348.85 3.12 0.0623933 0.0538005 26626 170182 -1 1593 21 1276 1604 133117 30584 0 0 133117 30584 1604 1434 0 0 5039 4403 0 0 8286 5564 0 0 1604 1462 0 0 57045 8981 0 0 59539 8740 0 0 1604 0 0 328 217 315 3140 0 0 3.41492 3.41492 -114.825 -3.41492 0 0 902133. 3121.57 0.29 0.04 0.13 -1 -1 0.29 0.0096077 0.00860201 67 25 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_108.v common 6.62 vpr 63.82 MiB -1 -1 0.10 20548 1 0.01 -1 -1 33364 -1 -1 9 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65352 32 32 278 238 1 144 73 17 17 289 -1 unnamed_device 25.4 MiB 1.30 694 63.8 MiB 0.05 0.00 3.31656 -97.2168 -3.31656 3.31656 0.95 0.000134566 0.000105716 0.0117988 0.00951404 36 2138 44 6.95648e+06 130281 648988. 2245.63 2.02 0.0626026 0.0532974 26050 158493 -1 1645 21 1288 1853 165825 35634 0 0 165825 35634 1853 1532 0 0 5919 5185 0 0 10143 6784 0 0 1853 1623 0 0 73013 10550 0 0 73044 9960 0 0 1853 0 0 565 478 566 4714 0 0 3.38757 3.38757 -120.35 -3.38757 0 0 828058. 2865.25 0.33 0.05 0.11 -1 -1 0.33 0.0149094 0.0137064 56 31 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_109.v common 6.16 vpr 64.32 MiB -1 -1 0.12 20884 1 0.02 -1 -1 33192 -1 -1 24 31 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65860 31 32 373 300 1 174 87 17 17 289 -1 unnamed_device 25.8 MiB 0.98 659 64.3 MiB 0.08 0.00 2.96863 -94.5196 -2.96863 2.96863 0.87 0.000197263 0.00016346 0.0150393 0.0125923 44 2116 43 6.95648e+06 347416 787024. 2723.27 2.04 0.0805263 0.0691929 27778 195446 -1 1479 26 1818 2444 165368 41873 0 0 165368 41873 2444 1882 0 0 7926 6915 0 0 13226 9217 0 0 2444 2036 0 0 68978 10071 0 0 70350 11752 0 0 2444 0 0 626 690 676 6154 0 0 3.02267 3.02267 -115.168 -3.02267 0 0 997811. 3452.63 0.34 0.08 0.23 -1 -1 0.34 0.0349178 0.0301224 79 60 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_110.v common 7.55 vpr 64.17 MiB -1 -1 0.13 20468 1 0.01 -1 -1 33152 -1 -1 12 31 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65708 31 32 265 230 1 159 75 17 17 289 -1 unnamed_device 25.7 MiB 2.53 786 64.2 MiB 0.03 0.00 3.35097 -102.439 -3.35097 3.35097 0.81 0.000123643 0.000100561 0.00751203 0.00629213 38 2042 23 6.95648e+06 173708 678818. 2348.85 2.03 0.0574395 0.049799 26626 170182 -1 1735 20 1065 1523 121759 25462 0 0 121759 25462 1523 1330 0 0 4768 4148 0 0 7501 5180 0 0 1523 1396 0 0 55904 6648 0 0 50540 6760 0 0 1523 0 0 458 486 272 3655 0 0 3.27682 3.27682 -119.763 -3.27682 0 0 902133. 3121.57 0.29 0.03 0.11 -1 -1 0.29 0.0102443 0.00923834 64 30 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_111.v common 6.72 vpr 64.25 MiB -1 -1 0.13 20776 1 0.01 -1 -1 33340 -1 -1 22 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65796 32 32 349 286 1 165 86 17 17 289 -1 unnamed_device 25.8 MiB 1.54 853 64.3 MiB 0.07 0.00 2.5815 -91.5934 -2.5815 2.5815 0.84 0.000156049 0.000127618 0.0131001 0.0109404 40 2052 25 6.95648e+06 318465 706193. 2443.58 1.88 0.0712634 0.0574101 26914 176310 -1 1889 21 1365 2068 167785 36544 0 0 167785 36544 2068 1553 0 0 7112 6123 0 0 12910 8584 0 0 2068 1670 0 0 71839 9291 0 0 71788 9323 0 0 2068 0 0 703 986 1022 7301 0 0 3.20437 3.20437 -119.373 -3.20437 0 0 926341. 3205.33 0.31 0.04 0.11 -1 -1 0.31 0.0131464 0.011821 71 54 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_112.v common 7.38 vpr 64.39 MiB -1 -1 0.12 20820 1 0.02 -1 -1 33404 -1 -1 15 31 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65932 31 32 396 325 1 176 78 17 17 289 -1 unnamed_device 25.8 MiB 1.59 675 64.4 MiB 0.14 0.00 3.3685 -110.466 -3.3685 3.3685 1.03 0.000176953 0.000144311 0.021231 0.0180866 40 2193 40 6.95648e+06 217135 706193. 2443.58 2.36 0.0866352 0.0741712 26914 176310 -1 1859 23 1728 2308 219518 50912 0 0 219518 50912 2308 1996 0 0 7758 6738 0 0 14025 9269 0 0 2308 2077 0 0 90304 15885 0 0 102815 14947 0 0 2308 0 0 580 684 807 5897 0 0 3.96011 3.96011 -139.49 -3.96011 0 0 926341. 3205.33 0.29 0.05 0.11 -1 -1 0.29 0.0142376 0.0126905 73 87 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_113.v common 7.70 vpr 64.03 MiB -1 -1 0.12 20528 1 0.01 -1 -1 33284 -1 -1 10 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65564 32 32 303 262 1 145 74 17 17 289 -1 unnamed_device 25.5 MiB 1.23 545 64.0 MiB 0.05 0.00 2.4011 -79.9159 -2.4011 2.4011 0.81 0.000138793 0.00011268 0.0108507 0.00901542 46 1451 25 6.95648e+06 144757 828058. 2865.25 3.76 0.0951409 0.0737288 28066 200906 -1 1111 21 938 1461 89314 21976 0 0 89314 21976 1461 1112 0 0 4499 4005 0 0 7783 5043 0 0 1461 1152 0 0 39540 4937 0 0 34570 5727 0 0 1461 0 0 523 367 298 3807 0 0 2.66912 2.66912 -95.8011 -2.66912 0 0 1.01997e+06 3529.29 0.33 0.03 0.13 -1 -1 0.33 0.0101135 0.00898701 57 54 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_114.v common 6.38 vpr 64.16 MiB -1 -1 0.11 20440 1 0.01 -1 -1 33124 -1 -1 11 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65700 32 32 290 244 1 170 75 17 17 289 -1 unnamed_device 25.6 MiB 1.27 702 64.2 MiB 0.11 0.00 3.29168 -104.399 -3.29168 3.29168 0.85 0.000159829 0.000133974 0.0154469 0.0135247 48 1900 50 6.95648e+06 159232 865456. 2994.66 1.75 0.0634118 0.0549009 28354 207349 -1 1577 22 1369 1985 162836 45267 0 0 162836 45267 1985 1654 0 0 6719 5924 0 0 12824 8312 0 0 1985 1815 0 0 67563 15057 0 0 71760 12505 0 0 1985 0 0 616 616 607 5056 0 0 3.95012 3.95012 -128.525 -3.95012 0 0 1.05005e+06 3633.38 0.40 0.04 0.18 -1 -1 0.40 0.0107983 0.00965938 70 31 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_115.v common 10.22 vpr 64.16 MiB -1 -1 0.11 20876 1 0.01 -1 -1 33080 -1 -1 14 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65696 32 32 318 257 1 188 78 17 17 289 -1 unnamed_device 25.7 MiB 2.09 714 64.2 MiB 0.05 0.00 3.45418 -103.596 -3.45418 3.45418 0.75 0.000148688 0.000121299 0.0118079 0.00982615 46 2524 45 6.95648e+06 202660 828058. 2865.25 5.15 0.128988 0.0978097 28066 200906 -1 1807 23 1708 2393 175991 42411 0 0 175991 42411 2393 1994 0 0 7701 6876 0 0 13184 8900 0 0 2393 2115 0 0 68699 11601 0 0 81621 10925 0 0 2393 0 0 685 742 677 5947 0 0 4.07382 4.07382 -132.794 -4.07382 0 0 1.01997e+06 3529.29 0.37 0.05 0.13 -1 -1 0.37 0.0141015 0.0126684 79 27 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_116.v common 6.20 vpr 64.20 MiB -1 -1 0.12 21152 1 0.01 -1 -1 33324 -1 -1 21 29 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65736 29 32 324 268 1 162 82 17 17 289 -1 unnamed_device 25.8 MiB 0.95 683 64.2 MiB 0.05 0.00 3.53128 -97.3988 -3.53128 3.53128 0.72 0.000146578 0.000119351 0.0112197 0.00942674 40 2194 47 6.95648e+06 303989 706193. 2443.58 2.57 0.07428 0.0638085 26914 176310 -1 1777 32 1370 1979 283795 103574 0 0 283795 103574 1979 1650 0 0 6611 5654 0 0 12539 8135 0 0 1979 1732 0 0 130020 44346 0 0 130667 42057 0 0 1979 0 0 609 887 804 6295 0 0 3.55116 3.55116 -118.787 -3.55116 0 0 926341. 3205.33 0.32 0.07 0.11 -1 -1 0.32 0.0162768 0.0144691 71 49 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_117.v common 7.64 vpr 64.38 MiB -1 -1 0.12 20720 1 0.01 -1 -1 33328 -1 -1 14 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65920 32 32 393 312 1 206 78 17 17 289 -1 unnamed_device 25.9 MiB 1.29 818 64.4 MiB 0.06 0.00 4.0452 -128.08 -4.0452 4.0452 0.77 0.000177494 0.000145536 0.0167642 0.0136204 46 2729 37 6.95648e+06 202660 828058. 2865.25 3.51 0.0975561 0.0846118 28066 200906 -1 2028 23 2086 2971 250832 57266 0 0 250832 57266 2971 2577 0 0 9329 8318 0 0 16954 10890 0 0 2971 2665 0 0 104719 16457 0 0 113888 16359 0 0 2971 0 0 885 990 1028 8310 0 0 4.47261 4.47261 -153.652 -4.47261 0 0 1.01997e+06 3529.29 0.31 0.06 0.13 -1 -1 0.31 0.0143728 0.0128531 89 62 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_118.v common 6.16 vpr 63.87 MiB -1 -1 0.10 20460 1 0.01 -1 -1 32944 -1 -1 13 31 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65404 31 32 229 197 1 137 76 17 17 289 -1 unnamed_device 25.3 MiB 1.32 843 63.9 MiB 0.05 0.00 3.10444 -86.1242 -3.10444 3.10444 0.80 0.000116257 9.5547e-05 0.0107741 0.00902148 36 1978 24 6.95648e+06 188184 648988. 2245.63 2.23 0.0518691 0.0444245 26050 158493 -1 1774 22 925 1487 137396 27348 0 0 137396 27348 1487 1201 0 0 4529 3839 0 0 8612 5224 0 0 1487 1301 0 0 61640 7891 0 0 59641 7892 0 0 1487 0 0 562 511 585 4439 0 0 2.99092 2.99092 -105.083 -2.99092 0 0 828058. 2865.25 0.26 0.03 0.10 -1 -1 0.26 0.00868803 0.00774845 54 -1 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_119.v common 12.81 vpr 64.67 MiB -1 -1 0.12 21040 1 0.01 -1 -1 33116 -1 -1 25 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 66224 32 32 412 334 1 182 89 17 17 289 -1 unnamed_device 26.1 MiB 1.02 1057 64.7 MiB 0.06 0.00 3.08489 -115.661 -3.08489 3.08489 0.75 0.000176856 0.000144384 0.0135327 0.0111599 36 2860 33 6.95648e+06 361892 648988. 2245.63 8.86 0.133238 0.113425 26050 158493 -1 2292 21 1704 2285 228957 52512 0 0 228957 52512 2285 1965 0 0 7415 6392 0 0 12385 8423 0 0 2285 2102 0 0 104857 16616 0 0 99730 17014 0 0 2285 0 0 581 546 723 5655 0 0 3.92226 3.92226 -151.05 -3.92226 0 0 828058. 2865.25 0.27 0.05 0.10 -1 -1 0.27 0.0138994 0.0124322 81 87 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_120.v common 11.52 vpr 64.18 MiB -1 -1 0.12 21140 1 0.01 -1 -1 33124 -1 -1 10 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65724 32 32 376 318 1 154 74 17 17 289 -1 unnamed_device 25.7 MiB 3.70 613 64.2 MiB 0.05 0.00 2.45985 -91.5837 -2.45985 2.45985 0.80 0.000158245 0.000128443 0.0142791 0.0118753 50 1638 25 6.95648e+06 144757 902133. 3121.57 4.59 0.10629 0.0904918 28642 213929 -1 1380 22 1538 2170 172872 38895 0 0 172872 38895 2170 1826 0 0 7041 6265 0 0 11895 7947 0 0 2170 1919 0 0 79517 9297 0 0 70079 11641 0 0 2170 0 0 632 365 749 5498 0 0 3.48182 3.48182 -126.918 -3.48182 0 0 1.08113e+06 3740.92 0.36 0.04 0.14 -1 -1 0.36 0.012442 0.0110397 61 93 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_121.v common 8.98 vpr 64.42 MiB -1 -1 0.13 20836 1 0.01 -1 -1 33328 -1 -1 22 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65968 32 32 360 293 1 172 86 17 17 289 -1 unnamed_device 25.9 MiB 1.24 713 64.4 MiB 0.06 0.00 3.41878 -102.821 -3.41878 3.41878 0.99 0.00017451 0.000144797 0.0130956 0.0110971 40 2722 44 6.95648e+06 318465 706193. 2443.58 3.90 0.132537 0.117594 26914 176310 -1 1913 18 1202 1842 144734 35148 0 0 144734 35148 1842 1472 0 0 6540 5669 0 0 10944 7801 0 0 1842 1560 0 0 59476 9747 0 0 64090 8899 0 0 1842 0 0 640 897 897 6490 0 0 3.71246 3.71246 -128.461 -3.71246 0 0 926341. 3205.33 0.31 0.04 0.13 -1 -1 0.31 0.0133718 0.0122306 75 57 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_122.v common 10.75 vpr 64.68 MiB -1 -1 0.14 20844 1 0.01 -1 -1 33256 -1 -1 15 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 66232 32 32 396 299 1 224 79 17 17 289 -1 unnamed_device 26.1 MiB 1.97 932 64.7 MiB 0.07 0.00 4.78047 -141.161 -4.78047 4.78047 0.90 0.000187013 0.000153829 0.0187457 0.0157428 54 2444 33 6.95648e+06 217135 949917. 3286.91 5.40 0.142831 0.123503 29506 232905 -1 1906 21 1750 2502 191775 42931 0 0 191775 42931 2502 2120 0 0 8098 7206 0 0 15189 9731 0 0 2502 2185 0 0 81877 10496 0 0 81607 11193 0 0 2502 0 0 752 798 859 6881 0 0 4.85675 4.85675 -159.034 -4.85675 0 0 1.17392e+06 4061.99 0.35 0.05 0.14 -1 -1 0.35 0.0139632 0.0125784 95 31 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_123.v common 12.08 vpr 63.59 MiB -1 -1 0.11 20744 1 0.01 -1 -1 33108 -1 -1 11 30 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65120 30 32 224 207 1 132 73 17 17 289 -1 unnamed_device 25.2 MiB 2.92 546 63.6 MiB 0.07 0.00 2.26495 -77.3411 -2.26495 2.26495 0.90 0.000133176 0.000110512 0.0136142 0.00924568 48 1352 18 6.95648e+06 159232 865456. 2994.66 5.96 0.0848664 0.0712494 28354 207349 -1 1110 23 880 1128 103582 22037 0 0 103582 22037 1128 1029 0 0 3813 3352 0 0 7075 4671 0 0 1128 1040 0 0 43455 6250 0 0 46983 5695 0 0 1128 0 0 248 207 230 2309 0 0 2.28052 2.28052 -86.197 -2.28052 0 0 1.05005e+06 3633.38 0.56 0.03 0.13 -1 -1 0.56 0.00867205 0.00766401 52 29 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_124.v common 10.50 vpr 64.27 MiB -1 -1 0.13 20592 1 0.01 -1 -1 33128 -1 -1 11 30 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65816 30 32 286 239 1 135 73 17 17 289 -1 unnamed_device 25.8 MiB 1.60 452 64.3 MiB 0.05 0.00 3.12499 -90.986 -3.12499 3.12499 1.09 0.000146927 0.000120878 0.0125582 0.010248 50 1167 49 6.95648e+06 159232 902133. 3121.57 5.14 0.120229 0.103595 28642 213929 -1 941 20 905 1346 100660 26905 0 0 100660 26905 1346 1134 0 0 4686 4104 0 0 8283 5728 0 0 1346 1159 0 0 44393 6565 0 0 40606 8215 0 0 1346 0 0 441 535 408 3894 0 0 3.51897 3.51897 -111.605 -3.51897 0 0 1.08113e+06 3740.92 0.50 0.04 0.17 -1 -1 0.50 0.011568 0.0103666 54 29 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_125.v common 12.04 vpr 64.08 MiB -1 -1 0.12 20804 1 0.01 -1 -1 33060 -1 -1 10 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65620 32 32 296 247 1 152 74 17 17 289 -1 unnamed_device 25.6 MiB 0.45 548 64.1 MiB 0.04 0.00 2.6818 -88.2907 -2.6818 2.6818 1.08 0.000149351 0.000122808 0.0109052 0.00902377 58 1268 32 6.95648e+06 144757 997811. 3452.63 7.54 0.122941 0.106136 30370 251734 -1 1215 21 1143 1837 173908 42405 0 0 173908 42405 1837 1493 0 0 6070 5405 0 0 12737 7962 0 0 1837 1557 0 0 78210 11574 0 0 73217 14414 0 0 1837 0 0 694 696 504 5335 0 0 2.90077 2.90077 -103.681 -2.90077 0 0 1.25153e+06 4330.55 0.60 0.06 0.20 -1 -1 0.60 0.0189355 0.0165865 59 31 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_126.v common 5.39 vpr 63.68 MiB -1 -1 0.12 20500 1 0.01 -1 -1 33252 -1 -1 18 25 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65204 25 32 216 194 1 121 75 17 17 289 -1 unnamed_device 25.2 MiB 0.74 493 63.7 MiB 0.03 0.00 2.59693 -61.9274 -2.59693 2.59693 0.87 0.000107867 8.7583e-05 0.00795905 0.00668533 38 1281 21 6.95648e+06 260562 678818. 2348.85 1.51 0.0436079 0.0376276 26626 170182 -1 1005 20 849 1335 78656 19493 0 0 78656 19493 1335 1035 0 0 4256 3796 0 0 7328 4937 0 0 1335 1078 0 0 33665 3999 0 0 30737 4648 0 0 1335 0 0 486 273 903 4455 0 0 2.89587 2.89587 -78.4616 -2.89587 0 0 902133. 3121.57 0.33 0.03 0.11 -1 -1 0.33 0.00821431 0.00733609 53 19 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_127.v common 13.67 vpr 64.46 MiB -1 -1 0.13 20780 1 0.01 -1 -1 33072 -1 -1 12 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 66012 32 32 376 307 1 178 76 17 17 289 -1 unnamed_device 25.9 MiB 2.38 724 64.5 MiB 0.06 0.00 3.43255 -106.707 -3.43255 3.43255 0.98 0.000216592 0.00018194 0.016036 0.0136946 52 2577 41 6.95648e+06 173708 926341. 3205.33 7.66 0.208773 0.184085 29218 227130 -1 1945 23 1562 2628 214378 49981 0 0 214378 49981 2628 2096 0 0 8335 7365 0 0 15642 9965 0 0 2628 2167 0 0 83628 14959 0 0 101517 13429 0 0 2628 0 0 1066 1162 1037 8255 0 0 4.08982 4.08982 -133.987 -4.08982 0 0 1.14541e+06 3963.36 0.57 0.10 0.19 -1 -1 0.57 0.034096 0.0320567 73 69 -1 -1 -1 -1 + fixed_k6_frac_2ripple_N8_22nm.xml mult_128.v common 7.40 vpr 64.67 MiB -1 -1 0.13 20744 1 0.01 -1 -1 33304 -1 -1 17 31 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 66220 31 32 409 331 1 183 80 17 17 289 -1 unnamed_device 26.3 MiB 1.22 871 64.7 MiB 0.06 0.00 3.32468 -114.951 -3.32468 3.32468 0.93 0.000187081 0.000154278 0.0166606 0.0141458 38 2809 37 6.95648e+06 246087 678818. 2348.85 2.70 0.116906 0.0965088 26626 170182 -1 2045 23 1662 2205 185689 39156 0 0 185689 39156 2205 1940 0 0 6884 5917 0 0 10641 7511 0 0 2205 2055 0 0 80915 11031 0 0 82839 10702 0 0 2205 0 0 543 816 733 5571 0 0 3.84582 3.84582 -142.69 -3.84582 0 0 902133. 3121.57 0.34 0.05 0.12 -1 -1 0.34 0.0175588 0.0155516 80 86 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_001.v common 18.49 vpr 64.33 MiB -1 -1 0.12 20948 1 0.01 -1 -1 33132 -1 -1 15 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65872 32 32 354 285 1 206 79 17 17 289 -1 unnamed_device 25.8 MiB 1.49 927 64.3 MiB 0.07 0.00 4.0552 -122.848 -4.0552 4.0552 0.86 0.000224884 0.000191906 0.0181067 0.0153321 40 2847 26 6.99608e+06 220735 706193. 2443.58 13.85 0.165861 0.142135 26914 176310 -1 2413 23 2068 3008 319527 66944 0 0 319527 66944 3008 2591 0 0 9513 8277 0 0 18069 11295 0 0 3008 2705 0 0 144670 20748 0 0 141259 21328 0 0 3008 0 0 940 1399 1334 9045 0 0 4.73541 4.73541 -157.502 -4.73541 0 0 926341. 3205.33 0.35 0.08 0.12 -1 -1 0.35 0.0175688 0.015701 88 47 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_002.v common 7.88 vpr 64.19 MiB -1 -1 0.14 20840 1 0.01 -1 -1 33208 -1 -1 17 30 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65732 30 32 363 293 1 224 79 17 17 289 -1 unnamed_device 25.8 MiB 1.59 1020 64.2 MiB 0.08 0.00 3.9687 -120.128 -3.9687 3.9687 1.14 0.000166888 0.000136621 0.020897 0.0184175 46 2634 48 6.99608e+06 250167 828058. 2865.25 2.38 0.0924791 0.080459 28066 200906 -1 2037 22 1937 2914 206191 49214 0 0 206191 49214 2914 2249 0 0 9457 8609 0 0 16316 11126 0 0 2914 2363 0 0 88732 12382 0 0 85858 12485 0 0 2914 0 0 977 1011 594 7450 0 0 4.38774 4.38774 -147.141 -4.38774 0 0 1.01997e+06 3529.29 0.62 0.06 0.16 -1 -1 0.62 0.0148875 0.0133174 99 58 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_003.v common 14.43 vpr 63.98 MiB -1 -1 0.11 20768 1 0.01 -1 -1 33376 -1 -1 14 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65520 32 32 299 247 1 183 78 17 17 289 -1 unnamed_device 25.4 MiB 0.68 801 64.0 MiB 0.11 0.00 2.87639 -92.2213 -2.87639 2.87639 0.93 0.000153928 0.000126915 0.0152605 0.0129662 40 2333 28 6.99608e+06 206020 706193. 2443.58 10.57 0.172578 0.148542 26914 176310 -1 2056 23 1516 2058 194760 42785 0 0 194760 42785 2058 1671 0 0 6927 6000 0 0 12636 8208 0 0 2058 1722 0 0 83796 12842 0 0 87285 12342 0 0 2058 0 0 542 611 505 4980 0 0 3.81291 3.81291 -123.954 -3.81291 0 0 926341. 3205.33 0.41 0.07 0.13 -1 -1 0.41 0.0162014 0.0142864 76 26 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_004.v common 9.34 vpr 64.25 MiB -1 -1 0.11 20828 1 0.01 -1 -1 33188 -1 -1 16 29 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65796 29 32 308 248 1 179 77 17 17 289 -1 unnamed_device 25.6 MiB 1.16 778 64.3 MiB 0.05 0.00 3.42478 -96.0081 -3.42478 3.42478 0.84 0.000155516 0.000129694 0.0128304 0.0107867 46 2047 30 6.99608e+06 235451 828058. 2865.25 4.85 0.145746 0.130257 28066 200906 -1 1415 20 1159 1804 97361 26527 0 0 97361 26527 1804 1334 0 0 5685 4925 0 0 8946 6351 0 0 1804 1493 0 0 38580 6589 0 0 40542 5835 0 0 1804 0 0 645 536 654 5389 0 0 3.71852 3.71852 -117.978 -3.71852 0 0 1.01997e+06 3529.29 0.46 0.03 0.15 -1 -1 0.46 0.0110726 0.00997666 78 25 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_005.v common 9.72 vpr 64.15 MiB -1 -1 0.11 20768 1 0.01 -1 -1 33196 -1 -1 14 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65688 32 32 336 268 1 194 78 17 17 289 -1 unnamed_device 25.6 MiB 2.42 836 64.1 MiB 0.06 0.00 3.89209 -118.75 -3.89209 3.89209 0.79 0.000154768 0.000126224 0.014534 0.012118 46 2609 24 6.99608e+06 206020 828058. 2865.25 4.23 0.115078 0.099465 28066 200906 -1 2001 21 1397 2314 167103 36482 0 0 167103 36482 2314 1805 0 0 7208 6288 0 0 11502 7771 0 0 2314 1887 0 0 72309 9169 0 0 71456 9562 0 0 2314 0 0 917 974 866 7595 0 0 4.41681 4.41681 -144.161 -4.41681 0 0 1.01997e+06 3529.29 0.52 0.05 0.15 -1 -1 0.52 0.0143301 0.0126545 81 31 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_006.v common 13.45 vpr 64.37 MiB -1 -1 0.12 20980 1 0.02 -1 -1 33264 -1 -1 17 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65912 32 32 366 295 1 221 81 17 17 289 -1 unnamed_device 26.0 MiB 2.67 908 64.4 MiB 0.08 0.00 2.79566 -97.2249 -2.79566 2.79566 0.77 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fixed_k6_frac_2uripple_N8_22nm.xml mult_010.v common 12.42 vpr 63.94 MiB -1 -1 0.10 20724 1 0.01 -1 -1 33220 -1 -1 13 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65472 32 32 298 248 1 181 77 17 17 289 -1 unnamed_device 25.3 MiB 0.84 873 63.9 MiB 0.05 0.00 3.18112 -113.032 -3.18112 3.18112 0.90 0.000143436 0.000117796 0.0129185 0.0108174 38 2497 41 6.99608e+06 191304 678818. 2348.85 8.15 0.115266 0.0980574 26626 170182 -1 1900 18 1318 1659 116797 25833 0 0 116797 25833 1659 1463 0 0 5325 4670 0 0 8019 5730 0 0 1659 1482 0 0 51068 6204 0 0 49067 6284 0 0 1659 0 0 341 265 301 3248 0 0 3.37756 3.37756 -132.713 -3.37756 0 0 902133. 3121.57 0.51 0.03 0.11 -1 -1 0.51 0.00915813 0.00824414 75 31 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_011.v common 6.58 vpr 64.12 MiB -1 -1 0.11 20512 1 0.01 -1 -1 33180 -1 -1 14 30 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65664 30 32 303 262 1 188 76 17 17 289 -1 unnamed_device 25.5 MiB 0.82 821 64.1 MiB 0.05 0.00 3.18013 -104.101 -3.18013 3.18013 0.90 0.00013672 0.000111363 0.0116586 0.00969392 38 2600 33 6.99608e+06 206020 678818. 2348.85 2.81 0.0763409 0.0664831 26626 170182 -1 1885 22 1718 2348 177776 37662 0 0 177776 37662 2348 1996 0 0 7183 6249 0 0 11262 7576 0 0 2348 2037 0 0 75471 10029 0 0 79164 9775 0 0 2348 0 0 630 742 660 5704 0 0 3.803 3.803 -129.399 -3.803 0 0 902133. 3121.57 0.31 0.05 0.11 -1 -1 0.31 0.0117773 0.010494 83 58 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_012.v common 5.54 vpr 64.05 MiB -1 -1 0.11 20572 1 0.01 -1 -1 33232 -1 -1 11 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65584 32 32 276 237 1 165 75 17 17 289 -1 unnamed_device 25.6 MiB 0.59 831 64.0 MiB 0.04 0.00 2.61058 -94.9371 -2.61058 2.61058 0.72 0.00013054 0.000106485 0.00913867 0.00763409 38 2234 25 6.99608e+06 161872 678818. 2348.85 2.37 0.0523977 0.0448606 26626 170182 -1 1882 21 1197 1553 143438 29205 0 0 143438 29205 1553 1350 0 0 4925 4347 0 0 8032 5455 0 0 1553 1398 0 0 63029 8263 0 0 64346 8392 0 0 1553 0 0 356 354 268 3243 0 0 3.06517 3.06517 -116.225 -3.06517 0 0 902133. 3121.57 0.28 0.04 0.11 -1 -1 0.28 0.00994869 0.00887844 66 31 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_013.v common 8.69 vpr 64.10 MiB -1 -1 0.10 21048 1 0.01 -1 -1 33128 -1 -1 15 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65640 32 32 344 272 1 201 79 17 17 289 -1 unnamed_device 25.6 MiB 0.71 979 64.1 MiB 0.07 0.00 3.18112 -109.79 -3.18112 3.18112 0.76 0.000161497 0.000131769 0.0156817 0.0130555 46 2867 31 6.99608e+06 220735 828058. 2865.25 5.15 0.109045 0.0931086 28066 200906 -1 2137 21 1731 2467 225829 48110 0 0 225829 48110 2467 2077 0 0 7690 6710 0 0 12303 8294 0 0 2467 2192 0 0 100619 14277 0 0 100283 14560 0 0 2467 0 0 736 768 815 6292 0 0 3.43901 3.43901 -132.224 -3.43901 0 0 1.01997e+06 3529.29 0.33 0.06 0.12 -1 -1 0.33 0.0144671 0.0129878 87 31 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_014.v common 13.54 vpr 64.20 MiB -1 -1 0.11 21004 1 0.01 -1 -1 33032 -1 -1 17 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65736 32 32 363 295 1 228 81 17 17 289 -1 unnamed_device 25.8 MiB 1.36 987 64.2 MiB 0.07 0.00 3.86116 -115.099 -3.86116 3.86116 0.78 0.000179863 0.000149682 0.0140346 0.0117552 46 2755 35 6.99608e+06 250167 828058. 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20728 1 0.01 -1 -1 33292 -1 -1 15 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65828 32 32 323 276 1 210 79 17 17 289 -1 unnamed_device 25.8 MiB 0.83 819 64.3 MiB 0.06 0.00 2.59239 -95.5898 -2.59239 2.59239 0.75 0.000162642 0.00013512 0.013645 0.0114219 44 2784 32 6.99608e+06 220735 787024. 2723.27 1.96 0.0585226 0.0502891 27778 195446 -1 1854 18 1533 1925 128339 30541 0 0 128339 30541 1925 1673 0 0 6200 5487 0 0 10037 7122 0 0 1925 1744 0 0 54124 7022 0 0 54128 7493 0 0 1925 0 0 392 445 473 4315 0 0 3.38202 3.38202 -120.775 -3.38202 0 0 997811. 3452.63 0.33 0.04 0.12 -1 -1 0.33 0.0105787 0.00956793 89 62 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_019.v common 6.17 vpr 63.68 MiB -1 -1 0.10 20724 1 0.02 -1 -1 33128 -1 -1 10 30 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65208 30 32 222 206 1 131 72 17 17 289 -1 unnamed_device 25.2 MiB 1.57 483 63.7 MiB 0.04 0.00 1.95956 -69.6963 -1.95956 1.95956 0.89 0.000116196 9.6431e-05 0.00820239 0.00687394 36 1484 33 6.99608e+06 147157 648988. 2245.63 1.72 0.0510031 0.0435952 26050 158493 -1 1016 17 653 732 56805 15008 0 0 56805 15008 732 674 0 0 2629 2306 0 0 3962 3086 0 0 732 690 0 0 24215 4408 0 0 24535 3844 0 0 732 0 0 79 77 73 1135 0 0 2.26878 2.26878 -83.5035 -2.26878 0 0 828058. 2865.25 0.27 0.02 0.10 -1 -1 0.27 0.00679011 0.00609683 52 29 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_020.v common 7.09 vpr 63.83 MiB -1 -1 0.11 20504 1 0.01 -1 -1 33352 -1 -1 13 31 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65360 31 32 291 243 1 171 76 17 17 289 -1 unnamed_device 25.3 MiB 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0.01 -1 -1 32984 -1 -1 8 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64900 32 32 173 169 1 112 72 17 17 289 -1 unnamed_device 25.0 MiB 0.17 367 63.4 MiB 0.03 0.00 1.68521 -55.2113 -1.68521 1.68521 0.87 9.5409e-05 7.6825e-05 0.0065803 0.00541323 38 1074 36 6.99608e+06 117725 678818. 2348.85 3.02 0.0454971 0.0383158 26626 170182 -1 837 15 568 636 42202 11370 0 0 42202 11370 636 612 0 0 2283 1974 0 0 3178 2518 0 0 636 618 0 0 18114 2664 0 0 17355 2984 0 0 636 0 0 68 10 72 962 0 0 1.84172 1.84172 -69.6098 -1.84172 0 0 902133. 3121.57 0.27 0.02 0.11 -1 -1 0.27 0.00533522 0.0046541 42 -1 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_026.v common 7.64 vpr 63.96 MiB -1 -1 0.10 20608 1 0.01 -1 -1 33056 -1 -1 14 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65496 32 32 300 245 1 178 78 17 17 289 -1 unnamed_device 25.4 MiB 1.05 894 64.0 MiB 0.06 0.00 3.68643 -101.798 -3.68643 3.68643 1.04 0.000150439 0.000123093 0.0142652 0.0118754 44 2236 22 6.99608e+06 206020 787024. 2723.27 3.41 0.0897009 0.076743 27778 195446 -1 1877 23 1124 1716 124445 27065 0 0 124445 27065 1716 1376 0 0 5406 4803 0 0 9043 6170 0 0 1716 1478 0 0 52478 6790 0 0 54086 6448 0 0 1716 0 0 592 578 580 4894 0 0 3.88287 3.88287 -123.468 -3.88287 0 0 997811. 3452.63 0.33 0.04 0.12 -1 -1 0.33 0.0117184 0.0104253 73 21 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_027.v common 7.23 vpr 64.01 MiB -1 -1 0.10 20760 1 0.01 -1 -1 33348 -1 -1 21 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65544 32 32 297 233 1 170 85 17 17 289 -1 unnamed_device 25.4 MiB 0.46 699 64.0 MiB 0.05 0.00 2.46605 -78.7522 -2.46605 2.46605 0.77 0.000144595 0.000116008 0.0118352 0.00978792 54 1848 22 6.99608e+06 309029 949917. 3286.91 3.94 0.0953252 0.0814643 29506 232905 -1 1477 18 1168 1903 121476 30484 0 0 121476 30484 1903 1351 0 0 6040 5176 0 0 10143 6897 0 0 1903 1500 0 0 48321 7865 0 0 53166 7695 0 0 1903 0 0 735 871 753 6560 0 0 2.82232 2.82232 -97.9525 -2.82232 0 0 1.17392e+06 4061.99 0.39 0.03 0.15 -1 -1 0.39 0.0104035 0.00932158 74 -1 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_028.v common 11.05 vpr 64.09 MiB -1 -1 0.12 20700 1 0.01 -1 -1 33288 -1 -1 15 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65632 32 32 338 277 1 205 79 17 17 289 -1 unnamed_device 25.6 MiB 1.37 837 64.1 MiB 0.06 0.00 3.44978 -102.261 -3.44978 3.44978 0.80 0.000157089 0.000128862 0.014589 0.0121359 50 2945 34 6.99608e+06 220735 902133. 3121.57 6.83 0.125727 0.108101 28642 213929 -1 2219 21 1791 2764 224374 54813 0 0 224374 54813 2764 2271 0 0 8960 7842 0 0 15903 10301 0 0 2764 2389 0 0 88543 16358 0 0 105440 15652 0 0 2764 0 0 973 1151 937 8435 0 0 4.08836 4.08836 -133.311 -4.08836 0 0 1.08113e+06 3740.92 0.36 0.05 0.14 -1 -1 0.36 0.0131596 0.0117103 87 47 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_029.v common 8.44 vpr 64.03 MiB -1 -1 0.11 20996 1 0.01 -1 -1 33124 -1 -1 12 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65568 32 32 284 241 1 168 76 17 17 289 -1 unnamed_device 25.6 MiB 2.16 700 64.0 MiB 0.05 0.00 2.6695 -91.049 -2.6695 2.6695 0.77 0.000132818 0.00010789 0.0113052 0.00946939 38 2330 39 6.99608e+06 176588 678818. 2348.85 3.65 0.0839941 0.0712375 26626 170182 -1 1710 20 1236 1745 137136 31052 0 0 137136 31052 1745 1536 0 0 5549 4876 0 0 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63.70 MiB -1 -1 0.09 20360 1 0.01 -1 -1 33356 -1 -1 10 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65228 32 32 253 210 1 149 74 17 17 289 -1 unnamed_device 25.1 MiB 0.41 581 63.7 MiB 0.05 0.00 2.81485 -90.4049 -2.81485 2.81485 0.78 0.00012811 0.000104323 0.0118549 0.00999269 42 1937 26 6.99608e+06 147157 744469. 2576.02 3.45 0.0682051 0.0583161 27202 183097 -1 1415 24 1131 1606 132682 30177 0 0 132682 30177 1606 1322 0 0 5315 4731 0 0 9904 6557 0 0 1606 1366 0 0 58657 7571 0 0 55594 8630 0 0 1606 0 0 475 334 485 3992 0 0 3.28557 3.28557 -109.75 -3.28557 0 0 949917. 3286.91 0.29 0.03 0.11 -1 -1 0.29 0.00967159 0.00860627 58 -1 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_033.v common 5.69 vpr 63.86 MiB -1 -1 0.11 20828 1 0.01 -1 -1 33160 -1 -1 13 31 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65388 31 32 271 231 1 165 76 17 17 289 -1 unnamed_device 25.4 MiB 0.75 801 63.9 MiB 0.04 0.00 2.75428 -90.3488 -2.75428 2.75428 0.75 0.000130915 0.000107309 0.00913587 0.00769077 38 2377 21 6.99608e+06 191304 678818. 2348.85 2.29 0.0554736 0.0477614 26626 170182 -1 1887 18 1155 1595 133535 28816 0 0 133535 28816 1595 1358 0 0 5060 4434 0 0 8303 5621 0 0 1595 1423 0 0 59735 8019 0 0 57247 7961 0 0 1595 0 0 440 432 461 4182 0 0 2.93552 2.93552 -111.913 -2.93552 0 0 902133. 3121.57 0.27 0.03 0.12 -1 -1 0.27 0.0086147 0.00774659 69 26 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_034.v common 6.80 vpr 64.27 MiB -1 -1 0.11 20580 1 0.01 -1 -1 33280 -1 -1 15 29 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65812 29 32 291 250 1 180 76 17 17 289 -1 unnamed_device 25.7 MiB 2.47 970 64.3 MiB 0.04 0.00 2.45385 -89.9013 -2.45385 2.45385 0.76 0.000134894 0.000110003 0.00809236 0.00680337 38 2245 23 6.99608e+06 220735 678818. 2348.85 1.38 0.0432789 0.0372158 26626 170182 -1 1852 21 1325 1738 128213 27143 0 0 128213 27143 1738 1427 0 0 5279 4544 0 0 8693 5740 0 0 1738 1480 0 0 55755 6735 0 0 55010 7217 0 0 1738 0 0 413 388 459 4060 0 0 2.59242 2.59242 -103.381 -2.59242 0 0 902133. 3121.57 0.45 0.05 0.10 -1 -1 0.45 0.0143129 0.0131721 77 48 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_035.v common 7.97 vpr 64.20 MiB -1 -1 0.12 20756 1 0.01 -1 -1 33196 -1 -1 16 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65736 32 32 367 282 1 217 80 17 17 289 -1 unnamed_device 25.6 MiB 1.02 945 64.2 MiB 0.07 0.00 3.66263 -104.012 -3.66263 3.66263 0.75 0.000185228 0.00015519 0.0172284 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fixed_k6_frac_2uripple_N8_22nm.xml mult_039.v common 7.95 vpr 64.26 MiB -1 -1 0.13 20808 1 0.01 -1 -1 33412 -1 -1 17 31 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65804 31 32 377 302 1 235 80 17 17 289 -1 unnamed_device 25.8 MiB 1.33 1040 64.3 MiB 0.07 0.00 4.27366 -133.02 -4.27366 4.27366 0.76 0.000170776 0.000139672 0.0155559 0.01298 48 3043 28 6.99608e+06 250167 865456. 2994.66 3.82 0.112929 0.0958855 28354 207349 -1 2504 24 2516 3620 344486 69713 0 0 344486 69713 3620 3303 0 0 11517 10242 0 0 22127 13812 0 0 3620 3505 0 0 152468 18958 0 0 151134 19893 0 0 3620 0 0 1104 1062 881 8875 0 0 4.8761 4.8761 -163.906 -4.8761 0 0 1.05005e+06 3633.38 0.34 0.07 0.13 -1 -1 0.34 0.0141547 0.0126109 104 60 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_040.v common 16.36 vpr 64.36 MiB -1 -1 0.13 20780 1 0.02 -1 -1 33292 -1 -1 18 31 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65908 31 32 383 305 1 233 81 17 17 289 -1 unnamed_device 25.9 MiB 2.82 978 64.4 MiB 0.07 0.00 4.14878 -130.965 -4.14878 4.14878 0.85 0.000168209 0.000136765 0.0164983 0.0137838 38 3709 44 6.99608e+06 264882 678818. 2348.85 10.61 0.135437 0.116474 26626 170182 -1 2667 21 2189 2958 259822 55404 0 0 259822 55404 2958 2615 0 0 9366 8095 0 0 15039 10348 0 0 2958 2634 0 0 114348 16195 0 0 115153 15517 0 0 2958 0 0 769 630 639 6688 0 0 5.06434 5.06434 -172.679 -5.06434 0 0 902133. 3121.57 0.27 0.06 0.10 -1 -1 0.27 0.0130635 0.0117218 103 60 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_041.v common 17.16 vpr 64.49 MiB -1 -1 0.11 20876 1 0.01 -1 -1 33092 -1 -1 16 31 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 66040 31 32 352 285 1 215 79 17 17 289 -1 unnamed_device 26.0 MiB 1.86 1037 64.5 MiB 0.07 0.00 3.12612 -104.757 -3.12612 3.12612 0.76 0.000175179 0.00014674 0.0161697 0.0136989 40 2918 23 6.99608e+06 235451 706193. 2443.58 12.63 0.145457 0.127245 26914 176310 -1 2446 20 1800 2434 229138 46350 0 0 229138 46350 2434 2075 0 0 8179 7176 0 0 14533 9693 0 0 2434 2180 0 0 104029 12285 0 0 97529 12941 0 0 2434 0 0 634 692 732 6114 0 0 3.67846 3.67846 -133.323 -3.67846 0 0 926341. 3205.33 0.29 0.05 0.11 -1 -1 0.29 0.0121301 0.0108954 93 51 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_042.v common 6.25 vpr 64.06 MiB -1 -1 0.11 20460 1 0.01 -1 -1 33376 -1 -1 14 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65600 32 32 291 242 1 178 78 17 17 289 -1 unnamed_device 25.5 MiB 1.00 843 64.1 MiB 0.05 0.00 3.22248 -91.914 -3.22248 3.22248 0.72 0.000136042 0.000110371 0.0120337 0.0100381 40 2690 40 6.99608e+06 206020 706193. 2443.58 2.48 0.0699078 0.0595277 26914 176310 -1 2025 33 1838 2507 387391 166211 0 0 387391 166211 2507 2159 0 0 7910 6904 0 0 15226 9392 0 0 2507 2282 0 0 182782 72712 0 0 176459 72762 0 0 2507 0 0 669 813 868 6575 0 0 3.90012 3.90012 -123.018 -3.90012 0 0 926341. 3205.33 0.32 0.10 0.11 -1 -1 0.32 0.0169286 0.0151371 72 24 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_043.v common 8.10 vpr 64.67 MiB -1 -1 0.12 21348 1 0.01 -1 -1 33440 -1 -1 21 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 66220 32 32 457 356 1 282 85 17 17 289 -1 unnamed_device 26.2 MiB 1.23 1486 64.7 MiB 0.13 0.00 4.125 -141.675 -4.125 4.125 0.79 0.000194051 0.00015899 0.0213702 0.018469 40 4073 27 6.99608e+06 309029 706193. 2443.58 3.52 0.0999347 0.0868917 26914 176310 -1 3584 73 6103 8633 2110833 940810 0 0 2110833 940810 8633 7908 0 0 24252 21698 0 0 69667 32218 0 0 8633 8041 0 0 1026409 434351 0 0 973239 436594 0 0 8633 0 0 2530 4231 4977 27429 0 0 4.98381 4.98381 -177.227 -4.98381 0 0 926341. 3205.33 0.30 0.50 0.11 -1 -1 0.30 0.0467943 0.0408203 129 84 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_044.v common 7.28 vpr 63.75 MiB -1 -1 0.11 20604 1 0.01 -1 -1 33288 -1 -1 11 31 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65284 31 32 261 225 1 158 74 17 17 289 -1 unnamed_device 25.4 MiB 2.82 620 63.8 MiB 0.04 0.00 2.4909 -81.579 -2.4909 2.4909 1.03 0.000126041 0.000102245 0.00866586 0.00723908 44 1714 22 6.99608e+06 161872 787024. 2723.27 1.40 0.0404383 0.0347018 27778 195446 -1 1301 20 1136 1479 87139 22140 0 0 87139 22140 1479 1214 0 0 4983 4396 0 0 7917 5803 0 0 1479 1261 0 0 37002 4278 0 0 34279 5188 0 0 1479 0 0 343 302 196 3028 0 0 2.76302 2.76302 -98.3628 -2.76302 0 0 997811. 3452.63 0.32 0.03 0.20 -1 -1 0.32 0.00880057 0.00787252 65 24 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_045.v common 7.99 vpr 64.20 MiB -1 -1 0.11 20896 1 0.01 -1 -1 33396 -1 -1 15 31 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65736 31 32 337 267 1 200 78 17 17 289 -1 unnamed_device 25.7 MiB 0.56 970 64.2 MiB 0.06 0.00 3.70767 -116.074 -3.70767 3.70767 0.74 0.000169004 0.000140703 0.0151532 0.0125991 52 2740 42 6.99608e+06 220735 926341. 3205.33 4.56 0.115877 0.0985003 29218 227130 -1 2113 21 1619 2254 233780 47359 0 0 233780 47359 2254 1939 0 0 7117 6232 0 0 13156 8310 0 0 2254 2025 0 0 107071 14118 0 0 101928 14735 0 0 2254 0 0 635 628 691 5864 0 0 4.51461 4.51461 -141.6 -4.51461 0 0 1.14541e+06 3963.36 0.37 0.05 0.14 -1 -1 0.37 0.0119345 0.0106449 85 30 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_046.v common 19.86 vpr 64.34 MiB -1 -1 0.11 20776 1 0.01 -1 -1 33180 -1 -1 15 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65884 32 32 349 284 1 213 79 17 17 289 -1 unnamed_device 25.8 MiB 1.34 1125 64.3 MiB 0.06 0.00 3.12594 -108.005 -3.12594 3.12594 0.90 0.000158972 0.000129792 0.0153997 0.0133551 38 3065 37 6.99608e+06 220735 678818. 2348.85 15.71 0.137942 0.111067 26626 170182 -1 2592 23 1620 2575 239369 47554 0 0 239369 47554 2575 2119 0 0 8178 7191 0 0 13905 9140 0 0 2575 2259 0 0 107337 13207 0 0 104799 13638 0 0 2575 0 0 955 1184 1054 8222 0 0 3.50772 3.50772 -134.404 -3.50772 0 0 902133. 3121.57 0.29 0.06 0.11 -1 -1 0.29 0.0139208 0.0124198 91 50 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_047.v common 6.10 vpr 63.87 MiB -1 -1 0.12 20296 1 0.01 -1 -1 33108 -1 -1 16 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65400 32 32 291 230 1 166 80 17 17 289 -1 unnamed_device 25.3 MiB 0.79 669 63.9 MiB 0.05 0.00 3.61243 -98.5885 -3.61243 3.61243 0.78 0.000145333 0.000119271 0.0113158 0.00952585 48 2009 49 6.99608e+06 235451 865456. 2994.66 2.56 0.0811036 0.0631505 28354 207349 -1 1576 26 1281 2350 178599 42896 0 0 178599 42896 2350 1814 0 0 7513 6499 0 0 15273 9266 0 0 2350 1990 0 0 75824 11197 0 0 75289 12130 0 0 2350 0 0 1069 1375 1416 9602 0 0 3.96112 3.96112 -124.622 -3.96112 0 0 1.05005e+06 3633.38 0.33 0.04 0.14 -1 -1 0.33 0.0117286 0.0104124 68 -1 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_048.v common 7.60 vpr 64.31 MiB -1 -1 0.12 20900 1 0.00 -1 -1 33348 -1 -1 15 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65856 32 32 353 287 1 204 79 17 17 289 -1 unnamed_device 25.8 MiB 1.16 953 64.3 MiB 0.06 0.00 3.52245 -109.707 -3.52245 3.52245 0.74 0.000197284 0.000145516 0.0118521 0.0100027 44 2636 23 6.99608e+06 220735 787024. 2723.27 3.68 0.0926274 0.0791097 27778 195446 -1 2174 22 1460 1947 168777 35575 0 0 168777 35575 1947 1663 0 0 6233 5514 0 0 10144 7025 0 0 1947 1734 0 0 74421 10028 0 0 74085 9611 0 0 1947 0 0 487 609 488 4709 0 0 3.58916 3.58916 -127.339 -3.58916 0 0 997811. 3452.63 0.33 0.05 0.12 -1 -1 0.33 0.0129367 0.0115356 90 52 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_049.v common 8.14 vpr 64.36 MiB -1 -1 0.12 20872 1 0.02 -1 -1 33168 -1 -1 15 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65900 32 32 361 291 1 216 79 17 17 289 -1 unnamed_device 25.8 MiB 1.41 1076 64.4 MiB 0.10 0.00 2.90529 -102.96 -2.90529 2.90529 0.86 0.000164811 0.000135169 0.0211588 0.0185498 42 3146 34 6.99608e+06 220735 744469. 2576.02 3.77 0.118261 0.10231 27202 183097 -1 2492 21 1681 2464 197593 41716 0 0 197593 41716 2464 2056 0 0 8314 7224 0 0 14122 9892 0 0 2464 2166 0 0 83525 10658 0 0 86704 9720 0 0 2464 0 0 783 1108 1184 8395 0 0 3.76811 3.76811 -136.07 -3.76811 0 0 949917. 3286.91 0.32 0.05 0.12 -1 -1 0.32 0.0127046 0.0112978 92 52 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_050.v common 17.14 vpr 64.47 MiB -1 -1 0.12 20808 1 0.01 -1 -1 33208 -1 -1 16 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 66016 32 32 382 305 1 237 80 17 17 289 -1 unnamed_device 25.9 MiB 2.26 1123 64.5 MiB 0.08 0.00 3.04477 -106.857 -3.04477 3.04477 0.78 0.000174544 0.000143625 0.0174951 0.0146569 46 2974 23 6.99608e+06 235451 828058. 2865.25 12.05 0.144931 0.123829 28066 200906 -1 2363 21 1835 2428 175614 37452 0 0 175614 37452 2428 2016 0 0 7718 6782 0 0 11795 8295 0 0 2428 2173 0 0 78262 9005 0 0 72983 9181 0 0 2428 0 0 593 619 632 5778 0 0 3.45281 3.45281 -131.246 -3.45281 0 0 1.01997e+06 3529.29 0.33 0.05 0.13 -1 -1 0.33 0.0140725 0.0126481 101 59 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_051.v common 5.84 vpr 63.96 MiB -1 -1 0.11 20696 1 0.01 -1 -1 33232 -1 -1 14 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65492 32 32 306 248 1 178 78 17 17 289 -1 unnamed_device 25.4 MiB 0.95 764 64.0 MiB 0.04 0.00 3.71143 -99.7777 -3.71143 3.71143 0.90 0.000156983 0.000131193 0.0110446 0.0092984 46 2296 45 6.99608e+06 206020 828058. 2865.25 1.97 0.0672893 0.0576991 28066 200906 -1 1543 23 1134 1703 104699 27214 0 0 104699 27214 1703 1368 0 0 5390 4775 0 0 8250 5836 0 0 1703 1458 0 0 41291 7194 0 0 46362 6583 0 0 1703 0 0 569 638 432 4840 0 0 3.75451 3.75451 -120.393 -3.75451 0 0 1.01997e+06 3529.29 0.35 0.04 0.13 -1 -1 0.35 0.0122971 0.0109955 74 21 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_052.v common 7.69 vpr 64.16 MiB -1 -1 0.11 21160 1 0.01 -1 -1 33276 -1 -1 13 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65696 32 32 319 257 1 192 77 17 17 289 -1 unnamed_device 25.7 MiB 1.84 706 64.2 MiB 0.05 0.00 3.44198 -102.523 -3.44198 3.44198 0.74 0.000146643 0.000119467 0.0115209 0.00960911 46 2679 49 6.99608e+06 191304 828058. 2865.25 2.85 0.0759911 0.0649413 28066 200906 -1 1810 28 1811 2485 204321 46603 0 0 204321 46603 2485 2167 0 0 7688 6742 0 0 13614 8667 0 0 2485 2269 0 0 81699 14167 0 0 96350 12591 0 0 2485 0 0 674 702 661 5912 0 0 4.24601 4.24601 -128.755 -4.24601 0 0 1.01997e+06 3529.29 0.35 0.05 0.13 -1 -1 0.35 0.014796 0.0131093 81 26 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_053.v common 6.08 vpr 64.38 MiB -1 -1 0.12 20732 1 0.01 -1 -1 33232 -1 -1 16 31 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65924 31 32 373 299 1 224 79 17 17 289 -1 unnamed_device 26.0 MiB 0.81 1122 64.4 MiB 0.07 0.00 3.56031 -113.625 -3.56031 3.56031 0.78 0.000184257 0.000154339 0.0147286 0.0124811 44 3411 28 6.99608e+06 235451 787024. 2723.27 2.35 0.0753508 0.065558 27778 195446 -1 2662 24 2046 3167 281574 56275 0 0 281574 56275 3167 2666 0 0 10004 8802 0 0 16820 11344 0 0 3167 2763 0 0 121958 16114 0 0 126458 14586 0 0 3167 0 0 1121 1389 1524 10081 0 0 4.20995 4.20995 -146.527 -4.20995 0 0 997811. 3452.63 0.32 0.06 0.12 -1 -1 0.32 0.0139655 0.0124154 99 58 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_054.v common 6.14 vpr 64.58 MiB -1 -1 0.12 20764 1 0.01 -1 -1 32932 -1 -1 16 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 66132 32 32 387 315 1 241 80 17 17 289 -1 unnamed_device 26.0 MiB 0.88 1112 64.6 MiB 0.08 0.00 3.36392 -112.351 -3.36392 3.36392 0.72 0.000194149 0.0001626 0.0180091 0.0152435 48 3244 28 6.99608e+06 235451 865456. 2994.66 2.21 0.0819099 0.0704621 28354 207349 -1 2732 24 2349 3444 311833 64596 0 0 311833 64596 3444 2724 0 0 11193 9897 0 0 20371 13515 0 0 3444 2997 0 0 132761 18635 0 0 140620 16828 0 0 3444 0 0 1095 1016 1083 9078 0 0 3.89412 3.89412 -138.998 -3.89412 0 0 1.05005e+06 3633.38 0.42 0.07 0.18 -1 -1 0.42 0.0162268 0.0145458 104 74 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_055.v common 10.72 vpr 63.64 MiB -1 -1 0.10 20524 1 0.01 -1 -1 33300 -1 -1 10 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65164 32 32 251 219 1 152 74 17 17 289 -1 unnamed_device 25.1 MiB 0.50 652 63.6 MiB 0.04 0.00 2.58978 -78.8686 -2.58978 2.58978 0.75 0.00012458 0.000101121 0.00909318 0.00755958 42 1935 29 6.99608e+06 147157 744469. 2576.02 7.51 0.0812337 0.0688003 27202 183097 -1 1466 20 1085 1507 107073 26761 0 0 107073 26761 1507 1249 0 0 5207 4530 0 0 8804 6182 0 0 1507 1326 0 0 41230 6936 0 0 48818 6538 0 0 1507 0 0 422 349 467 3833 0 0 3.23357 3.23357 -100.069 -3.23357 0 0 949917. 3286.91 0.31 0.03 0.12 -1 -1 0.31 0.00871086 0.00779835 60 20 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_056.v common 6.35 vpr 64.16 MiB -1 -1 0.11 20948 1 0.01 -1 -1 33224 -1 -1 15 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65704 32 32 341 285 1 214 79 17 17 289 -1 unnamed_device 25.7 MiB 0.83 970 64.2 MiB 0.06 0.00 3.31348 -119.997 -3.31348 3.31348 0.78 0.00017027 0.000142356 0.0132759 0.0112497 38 3566 34 6.99608e+06 220735 678818. 2348.85 2.70 0.0624396 0.0533437 26626 170182 -1 2791 20 2260 3077 341425 67678 0 0 341425 67678 3077 2845 0 0 9331 8301 0 0 15088 9920 0 0 3077 2897 0 0 153138 22641 0 0 157714 21074 0 0 3077 0 0 817 967 872 7367 0 0 4.42155 4.42155 -162.962 -4.42155 0 0 902133. 3121.57 0.28 0.06 0.10 -1 -1 0.28 0.0119545 0.0107512 93 62 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_057.v common 8.85 vpr 64.34 MiB -1 -1 0.12 20756 1 0.02 -1 -1 33272 -1 -1 16 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65888 32 32 387 293 1 226 80 17 17 289 -1 unnamed_device 25.9 MiB 1.09 1157 64.3 MiB 0.08 0.00 3.99514 -125.321 -3.99514 3.99514 0.76 0.000178693 0.000146518 0.0182918 0.0152609 50 2856 29 6.99608e+06 235451 902133. 3121.57 4.78 0.150539 0.131085 28642 213929 -1 2326 21 2027 3106 320330 69780 0 0 320330 69780 3106 2453 0 0 10141 8873 0 0 20062 11973 0 0 3106 2701 0 0 141148 21981 0 0 142767 21799 0 0 3106 0 0 1079 952 1131 8892 0 0 4.51586 4.51586 -150.83 -4.51586 0 0 1.08113e+06 3740.92 0.40 0.07 0.13 -1 -1 0.40 0.0145594 0.0130788 98 28 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_058.v common 13.39 vpr 64.00 MiB -1 -1 0.11 20776 1 0.01 -1 -1 33164 -1 -1 15 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65536 32 32 340 270 1 203 79 17 17 289 -1 unnamed_device 25.6 MiB 0.56 1018 64.0 MiB 0.06 0.00 3.52245 -120.884 -3.52245 3.52245 0.75 0.000174851 0.000145246 0.0115386 0.00968754 36 3140 41 6.99608e+06 220735 648988. 2245.63 10.13 0.119188 0.102727 26050 158493 -1 2507 20 1767 2409 225636 45235 0 0 225636 45235 2409 2074 0 0 7560 6620 0 0 12726 8535 0 0 2409 2154 0 0 99139 13232 0 0 101393 12620 0 0 2409 0 0 642 750 767 6212 0 0 3.83976 3.83976 -147.854 -3.83976 0 0 828058. 2865.25 0.28 0.05 0.10 -1 -1 0.28 0.0117256 0.0105002 85 31 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_059.v common 8.42 vpr 63.84 MiB -1 -1 0.10 20952 1 0.01 -1 -1 33192 -1 -1 20 30 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65376 30 32 278 235 1 166 82 17 17 289 -1 unnamed_device 25.4 MiB 1.13 659 63.8 MiB 0.05 0.00 3.02694 -91.1422 -3.02694 3.02694 0.75 0.000133937 0.000109188 0.00988551 0.00820782 40 2078 33 6.99608e+06 294314 706193. 2443.58 4.66 0.109063 0.0954468 26914 176310 -1 1695 18 1206 1796 158240 37125 0 0 158240 37125 1796 1427 0 0 6146 5369 0 0 10691 7270 0 0 1796 1543 0 0 69131 10440 0 0 68680 11076 0 0 1796 0 0 590 724 745 5865 0 0 3.66766 3.66766 -121.477 -3.66766 0 0 926341. 3205.33 0.29 0.04 0.11 -1 -1 0.29 0.00862928 0.00773401 72 29 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_060.v common 7.86 vpr 64.72 MiB -1 -1 0.12 21336 1 0.02 -1 -1 33284 -1 -1 18 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 66276 32 32 431 332 1 261 82 17 17 289 -1 unnamed_device 26.1 MiB 1.52 1458 64.7 MiB 0.09 0.00 4.69828 -148.633 -4.69828 4.69828 0.74 0.000189621 0.00015595 0.0198068 0.0165205 44 4094 42 6.99608e+06 264882 787024. 2723.27 3.30 0.100003 0.0863149 27778 195446 -1 3214 21 2468 3773 362365 69797 0 0 362365 69797 3773 3103 0 0 11537 10298 0 0 21844 13421 0 0 3773 3372 0 0 162805 19457 0 0 158633 20146 0 0 3773 0 0 1305 1472 1628 11540 0 0 5.28929 5.28929 -180.23 -5.28929 0 0 997811. 3452.63 0.52 0.07 0.12 -1 -1 0.52 0.015401 0.0138476 116 62 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_061.v common 7.21 vpr 64.34 MiB -1 -1 0.11 20892 1 0.01 -1 -1 33136 -1 -1 14 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65880 32 32 336 268 1 199 78 17 17 289 -1 unnamed_device 25.8 MiB 0.55 867 64.3 MiB 0.08 0.00 3.85334 -116.528 -3.85334 3.85334 0.75 0.000163116 0.000133344 0.02004 0.017541 42 2760 36 6.99608e+06 206020 744469. 2576.02 3.84 0.105683 0.0907944 27202 183097 -1 1980 21 1651 2264 199913 42337 0 0 199913 42337 2264 1872 0 0 7412 6432 0 0 12823 8657 0 0 2264 1954 0 0 85469 12287 0 0 89681 11135 0 0 2264 0 0 613 843 788 6164 0 0 4.05242 4.05242 -138.272 -4.05242 0 0 949917. 3286.91 0.31 0.05 0.12 -1 -1 0.31 0.0123024 0.0110484 83 31 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_062.v common 4.34 vpr 63.53 MiB -1 -1 0.10 20384 1 0.01 -1 -1 32992 -1 -1 13 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65056 32 32 231 199 1 136 77 17 17 289 -1 unnamed_device 25.1 MiB 0.20 652 63.5 MiB 0.04 0.00 2.4029 -78.4802 -2.4029 2.4029 0.77 0.000115814 9.4603e-05 0.00827789 0.00693677 38 1845 21 6.99608e+06 191304 678818. 2348.85 1.40 0.037735 0.0323466 26626 170182 -1 1622 18 945 1497 125662 26597 0 0 125662 26597 1497 1101 0 0 4705 4064 0 0 7770 5163 0 0 1497 1213 0 0 55492 7574 0 0 54701 7482 0 0 1497 0 0 552 732 740 5137 0 0 3.05697 3.05697 -104.423 -3.05697 0 0 902133. 3121.57 0.28 0.03 0.10 -1 -1 0.28 0.0075976 0.00679926 51 -1 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_063.v common 14.64 vpr 64.33 MiB -1 -1 0.11 20868 1 0.02 -1 -1 33288 -1 -1 16 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65876 32 32 349 273 1 207 80 17 17 289 -1 unnamed_device 25.8 MiB 1.19 948 64.3 MiB 0.07 0.00 4.00152 -109.55 -4.00152 4.00152 0.92 0.000162034 0.000132889 0.0177867 0.0149721 44 3107 50 6.99608e+06 235451 787024. 2723.27 10.60 0.130155 0.111801 27778 195446 -1 2134 23 1607 2717 208533 46608 0 0 208533 46608 2717 2068 0 0 8282 7290 0 0 15459 9818 0 0 2717 2237 0 0 88142 12408 0 0 91216 12787 0 0 2717 0 0 1110 1898 2002 12677 0 0 4.50986 4.50986 -136.938 -4.50986 0 0 997811. 3452.63 0.34 0.05 0.12 -1 -1 0.34 0.0132466 0.0118235 85 26 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_064.v common 5.53 vpr 63.80 MiB -1 -1 0.10 20316 1 0.01 -1 -1 33152 -1 -1 14 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65332 32 32 247 207 1 142 78 17 17 289 -1 unnamed_device 25.2 MiB 0.97 483 63.8 MiB 0.04 0.00 2.5722 -81.3565 -2.5722 2.5722 0.75 0.000136203 0.000113616 0.00929907 0.00788318 40 1647 31 6.99608e+06 206020 706193. 2443.58 1.82 0.0554799 0.0479124 26914 176310 -1 1399 24 1326 1924 172945 42073 0 0 172945 42073 1924 1600 0 0 6286 5436 0 0 11244 7426 0 0 1924 1665 0 0 77437 12089 0 0 74130 13857 0 0 1924 0 0 598 763 652 5405 0 0 3.21227 3.21227 -114.591 -3.21227 0 0 926341. 3205.33 0.29 0.04 0.11 -1 -1 0.29 0.00952735 0.00844536 57 -1 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_065.v common 10.65 vpr 63.84 MiB -1 -1 0.11 20604 1 0.00 -1 -1 33228 -1 -1 13 30 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65376 30 32 278 235 1 170 75 17 17 289 -1 unnamed_device 25.4 MiB 0.54 687 63.8 MiB 0.10 0.00 3.03377 -95.0567 -3.03377 3.03377 0.90 0.000168532 0.000140512 0.0172088 0.0146097 38 2272 40 6.99608e+06 191304 678818. 2348.85 7.04 0.108321 0.0876448 26626 170182 -1 1692 19 1255 1668 125047 28625 0 0 125047 28625 1668 1426 0 0 5192 4580 0 0 8143 5589 0 0 1668 1474 0 0 52201 8043 0 0 56175 7513 0 0 1668 0 0 413 413 451 4093 0 0 3.34751 3.34751 -116.374 -3.34751 0 0 902133. 3121.57 0.35 0.05 0.18 -1 -1 0.35 0.0183222 0.0173694 69 29 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_066.v common 8.66 vpr 64.15 MiB -1 -1 0.13 20988 1 0.01 -1 -1 33212 -1 -1 18 29 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65692 29 32 355 287 1 213 79 17 17 289 -1 unnamed_device 25.6 MiB 1.53 1017 64.2 MiB 0.04 0.00 3.40046 -105.096 -3.40046 3.40046 0.93 0.0001713 0.000136885 0.00918444 0.00752036 40 3065 26 6.99608e+06 264882 706193. 2443.58 4.05 0.117606 0.103632 26914 176310 -1 2655 30 2446 3577 515848 159171 0 0 515848 159171 3577 2994 0 0 11519 9853 0 0 24364 14340 0 0 3577 3132 0 0 233527 66901 0 0 239284 61951 0 0 3577 0 0 1131 1301 1250 9633 0 0 4.1569 4.1569 -141.868 -4.1569 0 0 926341. 3205.33 0.35 0.11 0.11 -1 -1 0.35 0.0159218 0.014057 97 56 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_067.v common 7.83 vpr 64.37 MiB -1 -1 0.11 20728 1 0.01 -1 -1 33208 -1 -1 15 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65916 32 32 358 289 1 217 79 17 17 289 -1 unnamed_device 25.8 MiB 1.29 1094 64.4 MiB 0.05 0.00 3.50518 -117.692 -3.50518 3.50518 0.73 0.000177927 0.000148494 0.0119145 0.0100135 46 2656 21 6.99608e+06 220735 828058. 2865.25 3.61 0.0906701 0.0776194 28066 200906 -1 2226 18 1527 2094 141280 30536 0 0 141280 30536 2094 1709 0 0 6407 5619 0 0 9778 6744 0 0 2094 1815 0 0 59942 7455 0 0 60965 7194 0 0 2094 0 0 567 508 555 4974 0 0 4.12191 4.12191 -148.239 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mult_069.v common 9.18 vpr 64.05 MiB -1 -1 0.12 20488 1 0.01 -1 -1 33368 -1 -1 11 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65588 32 32 276 237 1 163 75 17 17 289 -1 unnamed_device 25.6 MiB 1.81 846 64.1 MiB 0.07 0.00 3.18112 -104.147 -3.18112 3.18112 0.84 0.00014469 0.000119451 0.012921 0.0109767 48 2063 22 6.99608e+06 161872 865456. 2994.66 4.16 0.0784998 0.0672998 28354 207349 -1 1731 20 1134 1473 123440 25664 0 0 123440 25664 1473 1332 0 0 4848 4207 0 0 8224 5521 0 0 1473 1396 0 0 52817 6766 0 0 54605 6442 0 0 1473 0 0 339 187 336 3047 0 0 3.23226 3.23226 -117.346 -3.23226 0 0 1.05005e+06 3633.38 0.36 0.03 0.13 -1 -1 0.36 0.00984303 0.00888541 67 31 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_070.v common 7.47 vpr 64.11 MiB -1 -1 0.12 20636 1 0.01 -1 -1 33004 -1 -1 14 31 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65652 31 32 319 272 1 200 77 17 17 289 -1 unnamed_device 25.6 MiB 0.83 790 64.1 MiB 0.05 0.00 3.00077 -96.7127 -3.00077 3.00077 0.74 0.000151209 0.000125303 0.0102058 0.00864955 48 2042 26 6.99608e+06 206020 865456. 2994.66 3.73 0.0894451 0.0778493 28354 207349 -1 1629 22 1606 2245 158572 37768 0 0 158572 37768 2245 1793 0 0 7575 6558 0 0 13607 9056 0 0 2245 1867 0 0 66070 9153 0 0 66830 9341 0 0 2245 0 0 639 608 448 5218 0 0 3.11221 3.11221 -118.338 -3.11221 0 0 1.05005e+06 3633.38 0.35 0.04 0.13 -1 -1 0.35 0.0118903 0.0106258 86 60 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_071.v common 7.44 vpr 64.27 MiB -1 -1 0.11 21020 1 0.01 -1 -1 33368 -1 -1 19 30 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65808 30 32 329 273 1 202 81 17 17 289 -1 unnamed_device 25.8 MiB 1.10 841 64.3 MiB 0.05 0.00 2.70194 -87.7568 -2.70194 2.70194 0.77 0.000152833 0.000123121 0.0104871 0.00871706 46 2378 26 6.99608e+06 279598 828058. 2865.25 3.48 0.0815124 0.069603 28066 200906 -1 1876 21 1360 1972 146878 32414 0 0 146878 32414 1972 1542 0 0 6500 5702 0 0 10490 7346 0 0 1972 1632 0 0 63092 8214 0 0 62852 7978 0 0 1972 0 0 612 949 793 6750 0 0 3.19951 3.19951 -115.274 -3.19951 0 0 1.01997e+06 3529.29 0.32 0.04 0.12 -1 -1 0.32 0.0113939 0.0101888 91 52 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_072.v common 6.01 vpr 63.90 MiB -1 -1 0.11 20500 1 0.02 -1 -1 33156 -1 -1 17 28 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65432 28 32 277 229 1 170 77 17 17 289 -1 unnamed_device 25.4 MiB 0.43 857 63.9 MiB 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0.01 -1 -1 33164 -1 -1 17 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65884 32 32 385 308 1 237 81 17 17 289 -1 unnamed_device 25.8 MiB 0.66 1069 64.3 MiB 0.06 0.00 4.0077 -127.842 -4.0077 4.0077 0.75 0.000178567 0.000146334 0.0136556 0.0115502 48 3126 34 6.99608e+06 250167 865456. 2994.66 4.49 0.121939 0.10387 28354 207349 -1 2566 24 2423 3438 355314 76380 0 0 355314 76380 3438 3140 0 0 11390 10029 0 0 21197 13601 0 0 3438 3245 0 0 157963 22803 0 0 157888 23562 0 0 3438 0 0 1015 1267 1313 9589 0 0 5.11734 5.11734 -173.586 -5.11734 0 0 1.05005e+06 3633.38 0.36 0.08 0.13 -1 -1 0.36 0.0157999 0.0140614 102 62 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_078.v common 20.12 vpr 64.29 MiB -1 -1 0.12 20956 1 0.02 -1 -1 33388 -1 -1 17 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65836 32 32 387 309 1 244 81 17 17 289 -1 unnamed_device 25.8 MiB 0.75 1098 64.3 MiB 0.07 0.00 3.47616 -116.907 -3.47616 3.47616 0.80 0.000173441 0.000141612 0.0156652 0.0131243 46 3921 29 6.99608e+06 250167 828058. 2865.25 16.53 0.147753 0.127312 28066 200906 -1 2737 22 2162 3183 282249 57690 0 0 282249 57690 3183 2762 0 0 9655 8569 0 0 16398 10615 0 0 3183 2963 0 0 121726 16725 0 0 128104 16056 0 0 3183 0 0 1021 1284 1104 9138 0 0 3.7919 3.7919 -143.724 -3.7919 0 0 1.01997e+06 3529.29 0.34 0.06 0.12 -1 -1 0.34 0.0141874 0.0126768 104 62 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_079.v common 9.00 vpr 64.07 MiB -1 -1 0.11 20652 1 0.02 -1 -1 33268 -1 -1 13 30 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65608 30 32 272 232 1 171 75 17 17 289 -1 unnamed_device 25.6 MiB 0.95 592 64.1 MiB 0.04 0.00 3.63675 -103.141 -3.63675 3.63675 0.80 0.000131779 0.000107291 0.00980549 0.00832751 48 1886 27 6.99608e+06 191304 865456. 2994.66 5.40 0.087836 0.0755018 28354 207349 -1 1516 25 1265 1832 161315 40431 0 0 161315 40431 1832 1541 0 0 6155 5380 0 0 11149 7262 0 0 1832 1612 0 0 71424 11774 0 0 68923 12862 0 0 1832 0 0 567 607 499 4683 0 0 3.49286 3.49286 -118.503 -3.49286 0 0 1.05005e+06 3633.38 0.34 0.04 0.13 -1 -1 0.34 0.0101222 0.0089758 71 29 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_080.v common 8.58 vpr 64.59 MiB -1 -1 0.12 20788 1 0.02 -1 -1 33376 -1 -1 18 30 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 66144 30 32 375 299 1 233 80 17 17 289 -1 unnamed_device 25.9 MiB 0.85 898 64.6 MiB 0.05 0.00 4.22166 -128.126 -4.22166 4.22166 0.83 0.000182255 0.000152348 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fixed_k6_frac_2uripple_N8_22nm.xml mult_084.v common 14.45 vpr 64.34 MiB -1 -1 0.12 21136 1 0.01 -1 -1 33172 -1 -1 17 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65880 32 32 365 294 1 223 81 17 17 289 -1 unnamed_device 26.0 MiB 1.67 1271 64.3 MiB 0.08 0.00 3.75306 -124.358 -3.75306 3.75306 0.74 0.000163436 0.00013386 0.0183306 0.0153517 44 3123 28 6.99608e+06 250167 787024. 2723.27 9.77 0.128283 0.109843 27778 195446 -1 2509 20 1906 2810 242995 47758 0 0 242995 47758 2810 2397 0 0 8762 7717 0 0 15992 10129 0 0 2810 2525 0 0 106191 12468 0 0 106430 12522 0 0 2810 0 0 904 965 767 7578 0 0 4.2911 4.2911 -152.981 -4.2911 0 0 997811. 3452.63 0.54 0.05 0.12 -1 -1 0.54 0.0123502 0.0110888 95 54 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_085.v common 14.03 vpr 64.53 MiB -1 -1 0.12 21084 1 0.01 -1 -1 33152 -1 -1 20 29 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 66076 29 32 378 310 1 237 81 17 17 289 -1 unnamed_device 26.0 MiB 2.42 1165 64.5 MiB 0.05 0.00 3.11675 -104.42 -3.11675 3.11675 0.77 0.000163724 0.000134071 0.0109098 0.00916576 38 3394 50 6.99608e+06 294314 678818. 2348.85 8.79 0.123568 0.104761 26626 170182 -1 2604 24 2183 2840 247688 50633 0 0 247688 50633 2840 2463 0 0 8999 7885 0 0 14006 9911 0 0 2840 2524 0 0 108628 14695 0 0 110375 13155 0 0 2840 0 0 657 690 691 6328 0 0 3.86321 3.86321 -133.57 -3.86321 0 0 902133. 3121.57 0.30 0.06 0.10 -1 -1 0.30 0.0151752 0.0135028 109 79 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_086.v common 7.31 vpr 63.78 MiB -1 -1 0.11 20688 1 0.01 -1 -1 33140 -1 -1 10 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65312 32 32 243 205 1 140 74 17 17 289 -1 unnamed_device 25.3 MiB 1.10 624 63.8 MiB 0.04 0.00 2.91658 -85.962 -2.91658 2.91658 0.81 0.000122859 9.9949e-05 0.00956497 0.00791397 42 1906 25 6.99608e+06 147157 744469. 2576.02 3.64 0.0620288 0.0525282 27202 183097 -1 1479 19 1076 1649 130689 27340 0 0 130689 27340 1649 1372 0 0 5001 4318 0 0 8616 5514 0 0 1649 1428 0 0 56555 7504 0 0 57219 7204 0 0 1649 0 0 573 601 638 4747 0 0 2.80307 2.80307 -102.418 -2.80307 0 0 949917. 3286.91 0.30 0.03 0.12 -1 -1 0.30 0.00824825 0.00742181 54 -1 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_087.v common 8.05 vpr 64.61 MiB -1 -1 0.12 20604 1 0.01 -1 -1 33252 -1 -1 17 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 66156 32 32 373 302 1 234 81 17 17 289 -1 unnamed_device 26.0 MiB 0.58 1079 64.6 MiB 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20768 1 0.01 -1 -1 33104 -1 -1 15 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65856 32 32 356 289 1 218 79 17 17 289 -1 unnamed_device 25.7 MiB 1.56 1011 64.3 MiB 0.06 0.00 3.63687 -114.181 -3.63687 3.63687 0.75 0.000177595 0.000147984 0.0148935 0.012546 38 3385 47 6.99608e+06 220735 678818. 2348.85 13.88 0.150609 0.127158 26626 170182 -1 2370 24 1901 2606 192627 41430 0 0 192627 41430 2606 2167 0 0 8134 7149 0 0 13558 9018 0 0 2606 2291 0 0 86734 10056 0 0 78989 10749 0 0 2606 0 0 705 602 697 6476 0 0 4.54021 4.54021 -145.164 -4.54021 0 0 902133. 3121.57 0.28 0.05 0.11 -1 -1 0.28 0.0129179 0.0114627 95 53 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_093.v common 8.92 vpr 64.25 MiB -1 -1 0.12 20856 1 0.00 -1 -1 33264 -1 -1 17 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65796 32 32 349 260 1 195 81 17 17 289 -1 unnamed_device 25.7 MiB 0.37 834 64.3 MiB 0.12 0.00 3.77681 -111.474 -3.77681 3.77681 0.88 0.000165107 0.000135444 0.0374241 0.0345317 58 2092 21 6.99608e+06 250167 997811. 3452.63 5.36 0.146762 0.12965 30370 251734 -1 1704 23 1735 2961 207433 47091 0 0 207433 47091 2961 2125 0 0 9457 8171 0 0 17789 11381 0 0 2961 2406 0 0 84539 11421 0 0 89726 11587 0 0 2961 0 0 1226 1093 1399 10599 0 0 4.22195 4.22195 -131.467 -4.22195 0 0 1.25153e+06 4330.55 0.41 0.05 0.16 -1 -1 0.41 0.0136827 0.0122616 83 -1 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_094.v common 8.32 vpr 64.09 MiB -1 -1 0.11 20876 1 0.01 -1 -1 33168 -1 -1 16 30 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65632 30 32 316 264 1 197 78 17 17 289 -1 unnamed_device 25.6 MiB 0.98 788 64.1 MiB 0.05 0.00 3.02754 -88.8726 -3.02754 3.02754 0.78 0.000153221 0.000126599 0.0119349 0.00888368 46 2423 48 6.99608e+06 235451 828058. 2865.25 4.50 0.10232 0.0865148 28066 200906 -1 1887 21 1621 2406 185858 43906 0 0 185858 43906 2406 1990 0 0 7625 6777 0 0 12693 8657 0 0 2406 2167 0 0 79197 12183 0 0 81531 12132 0 0 2406 0 0 785 983 819 6881 0 0 3.80037 3.80037 -120.973 -3.80037 0 0 1.01997e+06 3529.29 0.36 0.05 0.12 -1 -1 0.36 0.0122271 0.0109125 86 47 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_095.v common 5.40 vpr 63.73 MiB -1 -1 0.11 20800 1 0.01 -1 -1 33152 -1 -1 15 27 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65264 27 32 255 219 1 145 74 17 17 289 -1 unnamed_device 25.1 MiB 0.86 487 63.7 MiB 0.05 0.00 2.96122 -84.2305 -2.96122 2.96122 0.77 0.000131368 0.000108014 0.00972053 0.00807223 38 1681 28 6.99608e+06 220735 678818. 2348.85 1.69 0.0507516 0.0430267 26626 170182 -1 1272 22 1034 1575 102328 25793 0 0 102328 25793 1575 1270 0 0 5009 4350 0 0 7844 5492 0 0 1575 1311 0 0 46193 5804 0 0 40132 7566 0 0 1575 0 0 541 558 512 4486 0 0 3.47636 3.47636 -110.452 -3.47636 0 0 902133. 3121.57 0.29 0.03 0.10 -1 -1 0.29 0.00922092 0.00819623 66 26 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_096.v common 9.07 vpr 64.56 MiB -1 -1 0.13 20856 1 0.01 -1 -1 33228 -1 -1 18 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 66112 32 32 421 327 1 257 82 17 17 289 -1 unnamed_device 26.1 MiB 0.95 1215 64.6 MiB 0.09 0.00 3.41284 -117.869 -3.41284 3.41284 0.87 0.00018804 0.000154474 0.0194287 0.0161428 48 3897 35 6.99608e+06 264882 865456. 2994.66 5.08 0.129592 0.110999 28354 207349 -1 3189 22 2467 3850 447060 99359 0 0 447060 99359 3850 3271 0 0 12435 10783 0 0 23535 14956 0 0 3850 3529 0 0 191079 35352 0 0 212311 31468 0 0 3850 0 0 1383 1874 1550 12149 0 0 4.30361 4.30361 -155.713 -4.30361 0 0 1.05005e+06 3633.38 0.35 0.09 0.13 -1 -1 0.35 0.017424 0.0155587 111 62 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_097.v common 7.80 vpr 64.15 MiB -1 -1 0.13 20620 1 0.01 -1 -1 33104 -1 -1 17 31 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65692 31 32 365 296 1 229 80 17 17 289 -1 unnamed_device 25.8 MiB 1.61 1215 64.2 MiB 0.07 0.00 4.34903 -133.1 -4.34903 4.34903 0.73 0.000188468 0.000157079 0.0170779 0.0145066 40 3074 25 6.99608e+06 250167 706193. 2443.58 3.47 0.102247 0.0915685 26914 176310 -1 2739 22 2360 3274 340504 65363 0 0 340504 65363 3274 2717 0 0 10572 9250 0 0 19592 12423 0 0 3274 2883 0 0 153710 19359 0 0 150082 18731 0 0 3274 0 0 914 1307 1289 9240 0 0 5.12834 5.12834 -174.894 -5.12834 0 0 926341. 3205.33 0.30 0.07 0.11 -1 -1 0.30 0.0157964 0.0141853 100 60 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_098.v common 12.77 vpr 64.11 MiB -1 -1 0.11 20840 1 0.01 -1 -1 33340 -1 -1 14 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65648 32 32 331 280 1 215 78 17 17 289 -1 unnamed_device 25.7 MiB 0.79 1014 64.1 MiB 0.05 0.00 3.46994 -124.611 -3.46994 3.46994 0.72 0.000176881 0.000148851 0.0105594 0.00884909 38 3080 34 6.99608e+06 206020 678818. 2348.85 9.32 0.112761 0.0971569 26626 170182 -1 2244 17 1489 1846 141889 30956 0 0 141889 30956 1846 1656 0 0 5909 5108 0 0 8529 6220 0 0 1846 1698 0 0 63832 8185 0 0 59927 8089 0 0 1846 0 0 357 397 210 3524 0 0 3.87341 3.87341 -149.054 -3.87341 0 0 902133. 3121.57 0.28 0.04 0.10 -1 -1 0.28 0.0102628 0.00925497 91 62 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_099.v common 6.91 vpr 64.02 MiB -1 -1 0.12 21116 1 0.01 -1 -1 33228 -1 -1 15 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65560 32 32 326 263 1 197 79 17 17 289 -1 unnamed_device 25.7 MiB 0.61 907 64.0 MiB 0.06 0.00 3.34348 -104.597 -3.34348 3.34348 0.82 0.000152567 0.000124933 0.0153334 0.0131481 44 2764 24 6.99608e+06 220735 787024. 2723.27 3.47 0.0905423 0.0775233 27778 195446 -1 2105 23 1381 1880 145306 32057 0 0 145306 32057 1880 1637 0 0 5974 5151 0 0 9628 6793 0 0 1880 1723 0 0 57416 9322 0 0 68528 7431 0 0 1880 0 0 499 489 549 4677 0 0 3.59921 3.59921 -128.312 -3.59921 0 0 997811. 3452.63 0.33 0.04 0.12 -1 -1 0.33 0.0121754 0.010878 81 31 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_100.v common 13.70 vpr 64.39 MiB -1 -1 0.12 20596 1 0.01 -1 -1 33212 -1 -1 17 31 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65932 31 32 373 294 1 221 80 17 17 289 -1 unnamed_device 25.9 MiB 1.27 977 64.4 MiB 0.07 0.00 3.45118 -103.39 -3.45118 3.45118 0.84 0.000168624 0.000138563 0.0158775 0.0132696 40 3041 42 6.99608e+06 250167 706193. 2443.58 9.15 0.141915 0.121257 26914 176310 -1 2422 22 2068 2952 237165 55296 0 0 237165 55296 2952 2367 0 0 9869 8600 0 0 16782 11524 0 0 2952 2527 0 0 102407 14661 0 0 102203 15617 0 0 2952 0 0 884 1225 1348 9213 0 0 4.45762 4.45762 -138.816 -4.45762 0 0 926341. 3205.33 0.31 0.05 0.11 -1 -1 0.31 0.0130212 0.0116237 97 46 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_101.v common 15.50 vpr 64.23 MiB -1 -1 0.11 20704 1 0.01 -1 -1 33420 -1 -1 17 30 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65772 30 32 325 268 1 198 79 17 17 289 -1 unnamed_device 25.7 MiB 1.34 904 64.2 MiB 0.05 0.00 2.85029 -90.0497 -2.85029 2.85029 0.92 0.000160584 0.00013391 0.0124637 0.0103457 44 2693 37 6.99608e+06 250167 787024. 2723.27 11.17 0.120211 0.102404 27778 195446 -1 1937 20 1448 2081 158210 36178 0 0 158210 36178 2081 1681 0 0 6858 6049 0 0 11349 8007 0 0 2081 1849 0 0 65061 9625 0 0 70780 8967 0 0 2081 0 0 633 722 512 5662 0 0 3.22576 3.22576 -113.509 -3.22576 0 0 997811. 3452.63 0.32 0.04 0.12 -1 -1 0.32 0.0111155 0.00990539 88 46 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_102.v common 8.48 vpr 64.31 MiB -1 -1 0.10 20752 1 0.01 -1 -1 33160 -1 -1 14 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65856 32 32 350 275 1 209 78 17 17 289 -1 unnamed_device 25.7 MiB 0.71 919 64.3 MiB 0.06 0.00 3.51478 -114.727 -3.51478 3.51478 0.90 0.000162362 0.000133156 0.014241 0.012 50 2816 43 6.99608e+06 206020 902133. 3121.57 4.83 0.133787 0.110112 28642 213929 -1 2115 22 1745 2623 194333 45096 0 0 194333 45096 2623 2140 0 0 8301 7293 0 0 14809 9561 0 0 2623 2308 0 0 80754 12203 0 0 85223 11591 0 0 2623 0 0 878 762 808 6863 0 0 4.13101 4.13101 -142.689 -4.13101 0 0 1.08113e+06 3740.92 0.36 0.05 0.14 -1 -1 0.36 0.013528 0.0121438 88 31 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_103.v common 7.26 vpr 64.50 MiB -1 -1 0.12 20948 1 0.01 -1 -1 33320 -1 -1 16 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 66048 32 32 386 307 1 240 80 17 17 289 -1 unnamed_device 26.0 MiB 2.35 1027 64.5 MiB 0.07 0.00 2.94423 -103.749 -2.94423 2.94423 1.01 0.000175977 0.000144945 0.0158388 0.0133918 44 2914 28 6.99608e+06 235451 787024. 2723.27 1.73 0.0707458 0.0607888 27778 195446 -1 2072 22 1898 2540 163518 37575 0 0 163518 37575 2540 2040 0 0 7753 6832 0 0 13095 8691 0 0 2540 2153 0 0 69566 9080 0 0 68024 8779 0 0 2540 0 0 642 614 618 5858 0 0 3.60011 3.60011 -135.455 -3.60011 0 0 997811. 3452.63 0.35 0.08 0.13 -1 -1 0.35 0.0194786 0.0178965 103 59 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_104.v common 5.89 vpr 63.79 MiB -1 -1 0.11 20596 1 0.01 -1 -1 33296 -1 -1 14 29 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65316 29 32 269 229 1 168 75 17 17 289 -1 unnamed_device 25.3 MiB 1.22 667 63.8 MiB 0.04 0.00 3.37515 -99.403 -3.37515 3.37515 0.75 0.000126542 0.000102759 0.0102202 0.00849711 38 1802 35 6.99608e+06 206020 678818. 2348.85 1.80 0.0561926 0.0480122 26626 170182 -1 1447 21 1351 1796 124241 27656 0 0 124241 27656 1796 1530 0 0 5658 4926 0 0 8624 6076 0 0 1796 1563 0 0 53895 6846 0 0 52472 6715 0 0 1796 0 0 445 498 491 4246 0 0 3.44186 3.44186 -117.802 -3.44186 0 0 902133. 3121.57 0.31 0.04 0.10 -1 -1 0.31 0.0102564 0.00913099 70 28 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_105.v common 9.21 vpr 64.02 MiB -1 -1 0.11 20880 1 0.01 -1 -1 33152 -1 -1 14 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65556 32 32 310 266 1 182 78 17 17 289 -1 unnamed_device 25.4 MiB 2.21 818 64.0 MiB 0.05 0.00 3.25048 -108.694 -3.25048 3.25048 0.74 0.000156521 0.000130282 0.0125376 0.010503 40 2473 50 6.99608e+06 206020 706193. 2443.58 4.22 0.119081 0.104146 26914 176310 -1 2014 34 2208 3045 548254 196007 0 0 548254 196007 3045 2822 0 0 9765 8662 0 0 21242 12555 0 0 3045 2849 0 0 256839 86098 0 0 254318 83021 0 0 3045 0 0 837 1012 903 7471 0 0 4.29411 4.29411 -145.003 -4.29411 0 0 926341. 3205.33 0.30 0.12 0.11 -1 -1 0.30 0.0157166 0.0138093 79 55 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_106.v common 8.02 vpr 64.24 MiB -1 -1 0.11 21088 1 0.02 -1 -1 33172 -1 -1 15 31 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65784 31 32 326 261 1 193 78 17 17 289 -1 unnamed_device 25.8 MiB 0.72 757 64.2 MiB 0.05 0.00 3.35878 -99.9459 -3.35878 3.35878 0.78 0.000161611 0.000132612 0.0130137 0.0107435 50 1985 29 6.99608e+06 220735 902133. 3121.57 4.45 0.130631 0.114945 28642 213929 -1 1629 23 1625 2370 162457 38990 0 0 162457 38990 2370 1871 0 0 7846 6907 0 0 13771 9259 0 0 2370 2013 0 0 69428 9056 0 0 66672 9884 0 0 2370 0 0 745 920 891 7102 0 0 3.65252 3.65252 -122.941 -3.65252 0 0 1.08113e+06 3740.92 0.34 0.04 0.14 -1 -1 0.34 0.0120496 0.0107736 80 29 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_107.v common 7.66 vpr 63.65 MiB -1 -1 0.11 20580 1 0.01 -1 -1 33120 -1 -1 13 29 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65180 29 32 262 224 1 162 74 17 17 289 -1 unnamed_device 25.3 MiB 0.85 606 63.7 MiB 0.04 0.00 3.02297 -87.5909 -3.02297 3.02297 0.77 0.000123508 0.000100354 0.00919996 0.00767242 44 1950 42 6.99608e+06 191304 787024. 2723.27 4.01 0.0708768 0.0600947 27778 195446 -1 1178 20 1004 1302 78060 21777 0 0 78060 21777 1302 1168 0 0 4328 3835 0 0 7119 5105 0 0 1302 1201 0 0 29861 5678 0 0 34148 4790 0 0 1302 0 0 298 255 220 2685 0 0 3.09411 3.09411 -101.553 -3.09411 0 0 997811. 3452.63 0.32 0.03 0.12 -1 -1 0.32 0.00888234 0.00797488 68 25 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_108.v common 7.33 vpr 63.95 MiB -1 -1 0.10 20756 1 0.01 -1 -1 33132 -1 -1 12 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65484 32 32 278 238 1 178 76 17 17 289 -1 unnamed_device 25.5 MiB 0.70 938 63.9 MiB 0.06 0.00 3.40815 -110.366 -3.40815 3.40815 0.74 0.000131909 0.000107161 0.0118748 0.00999142 44 2327 32 6.99608e+06 176588 787024. 2723.27 3.50 0.0885847 0.0759961 27778 195446 -1 1954 21 1305 1790 161236 31970 0 0 161236 31970 1790 1451 0 0 5712 4957 0 0 9600 6486 0 0 1790 1607 0 0 71595 8611 0 0 70749 8858 0 0 1790 0 0 485 488 510 4285 0 0 3.25226 3.25226 -125.779 -3.25226 0 0 997811. 3452.63 0.52 0.04 0.13 -1 -1 0.52 0.0100593 0.00901634 73 31 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_109.v common 8.15 vpr 64.41 MiB -1 -1 0.12 20732 1 0.01 -1 -1 33196 -1 -1 17 31 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65960 31 32 373 300 1 231 80 17 17 289 -1 unnamed_device 26.0 MiB 0.79 998 64.4 MiB 0.06 0.00 3.61381 -116.286 -3.61381 3.61381 0.95 0.00018807 0.000157507 0.0131423 0.0111517 46 2766 23 6.99608e+06 250167 828058. 2865.25 4.23 0.103835 0.0890413 28066 200906 -1 2277 19 1862 2546 196469 43815 0 0 196469 43815 2546 2189 0 0 8156 7163 0 0 13090 9152 0 0 2546 2256 0 0 86172 11079 0 0 83959 11976 0 0 2546 0 0 684 803 747 6486 0 0 4.36555 4.36555 -151.793 -4.36555 0 0 1.01997e+06 3529.29 0.35 0.05 0.13 -1 -1 0.35 0.0140181 0.0126498 101 60 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_110.v common 4.98 vpr 63.84 MiB -1 -1 0.11 20748 1 0.01 -1 -1 33332 -1 -1 13 31 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65372 31 32 265 230 1 171 76 17 17 289 -1 unnamed_device 25.4 MiB 0.69 668 63.8 MiB 0.05 0.00 3.10427 -93.1977 -3.10427 3.10427 0.76 0.000126834 0.000103646 0.0107099 0.00887343 44 2119 29 6.99608e+06 191304 787024. 2723.27 1.52 0.044752 0.0382654 27778 195446 -1 1578 20 1070 1489 120199 26225 0 0 120199 26225 1489 1232 0 0 4844 4158 0 0 7964 5555 0 0 1489 1283 0 0 53562 6663 0 0 50851 7334 0 0 1489 0 0 419 348 314 3408 0 0 2.99891 2.99891 -107.343 -2.99891 0 0 997811. 3452.63 0.35 0.03 0.14 -1 -1 0.35 0.00951652 0.00851543 71 30 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_111.v common 6.36 vpr 64.18 MiB -1 -1 0.12 20936 1 0.01 -1 -1 33136 -1 -1 15 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65716 32 32 349 286 1 207 79 17 17 289 -1 unnamed_device 25.7 MiB 0.95 1039 64.2 MiB 0.06 0.00 2.87229 -99.4775 -2.87229 2.87229 0.77 0.000170867 0.000142251 0.0128131 0.0107325 38 2900 49 6.99608e+06 220735 678818. 2348.85 2.70 0.0814544 0.0698928 26626 170182 -1 2294 18 1436 1935 165359 33856 0 0 165359 33856 1935 1657 0 0 6008 5168 0 0 9104 6405 0 0 1935 1693 0 0 74048 9306 0 0 72329 9627 0 0 1935 0 0 499 461 476 4975 0 0 3.48716 3.48716 -127.312 -3.48716 0 0 902133. 3121.57 0.29 0.04 0.11 -1 -1 0.29 0.0112748 0.0101494 91 54 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_112.v common 10.43 vpr 64.39 MiB -1 -1 0.13 20844 1 0.01 -1 -1 33304 -1 -1 20 31 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65932 31 32 396 325 1 255 83 17 17 289 -1 unnamed_device 25.8 MiB 2.48 1134 64.4 MiB 0.06 0.00 3.80112 -129.442 -3.80112 3.80112 0.75 0.000188556 0.000156466 0.0133442 0.011201 54 2955 23 6.99608e+06 294314 949917. 3286.91 5.05 0.100474 0.0854758 29506 232905 -1 2545 22 2265 3219 285293 57488 0 0 285293 57488 3219 2638 0 0 10285 9077 0 0 18292 11906 0 0 3219 2712 0 0 120853 16335 0 0 129425 14820 0 0 3219 0 0 954 953 987 8493 0 0 4.42399 4.42399 -158.877 -4.42399 0 0 1.17392e+06 4061.99 0.39 0.07 0.15 -1 -1 0.39 0.017162 0.0156324 113 87 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_113.v common 9.67 vpr 64.04 MiB -1 -1 0.12 20948 1 0.01 -1 -1 33276 -1 -1 12 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65580 32 32 303 262 1 192 76 17 17 289 -1 unnamed_device 25.4 MiB 2.05 722 64.0 MiB 0.04 0.00 2.79904 -93.1152 -2.79904 2.79904 0.75 0.000140857 0.000114539 0.00990216 0.00823687 52 2255 37 6.99608e+06 176588 926341. 3205.33 4.87 0.101698 0.0863294 29218 227130 -1 1728 21 1581 2094 153106 37179 0 0 153106 37179 2094 1814 0 0 6871 6088 0 0 11737 8037 0 0 2094 1949 0 0 59558 10317 0 0 70752 8974 0 0 2094 0 0 513 534 433 4696 0 0 3.25251 3.25251 -117.974 -3.25251 0 0 1.14541e+06 3963.36 0.38 0.04 0.14 -1 -1 0.38 0.0107434 0.00960995 80 54 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_114.v common 7.72 vpr 63.96 MiB -1 -1 0.10 20612 1 0.01 -1 -1 33324 -1 -1 11 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65500 32 32 290 244 1 172 75 17 17 289 -1 unnamed_device 25.5 MiB 0.60 722 64.0 MiB 0.05 0.00 3.13712 -100.64 -3.13712 3.13712 0.79 0.000134735 0.000109657 0.0117259 0.00973057 44 2147 36 6.99608e+06 161872 787024. 2723.27 4.23 0.0901841 0.0767775 27778 195446 -1 1497 19 1125 1631 94727 25494 0 0 94727 25494 1631 1353 0 0 5429 4865 0 0 9286 6536 0 0 1631 1415 0 0 37048 6355 0 0 39702 4970 0 0 1631 0 0 506 463 328 3940 0 0 3.58416 3.58416 -119.429 -3.58416 0 0 997811. 3452.63 0.32 0.03 0.21 -1 -1 0.32 0.00954044 0.00857486 72 31 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_115.v common 8.45 vpr 63.97 MiB -1 -1 0.10 20952 1 0.01 -1 -1 33132 -1 -1 14 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65504 32 32 318 257 1 191 78 17 17 289 -1 unnamed_device 25.6 MiB 1.42 834 64.0 MiB 0.05 0.00 3.36978 -103.576 -3.36978 3.36978 0.80 0.000162118 0.000135557 0.0129459 0.0110543 46 2368 49 6.99608e+06 206020 828058. 2865.25 4.09 0.112852 0.0968041 28066 200906 -1 1669 21 1318 1902 115917 27210 0 0 115917 27210 1902 1445 0 0 5892 5189 0 0 9896 6520 0 0 1902 1582 0 0 44839 6761 0 0 51486 5713 0 0 1902 0 0 584 609 428 4795 0 0 3.56842 3.56842 -121.512 -3.56842 0 0 1.01997e+06 3529.29 0.32 0.03 0.26 -1 -1 0.32 0.0113085 0.0101616 79 27 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_116.v common 7.73 vpr 64.14 MiB -1 -1 0.12 20856 1 0.01 -1 -1 33168 -1 -1 18 29 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65680 29 32 324 268 1 195 79 17 17 289 -1 unnamed_device 25.6 MiB 1.38 862 64.1 MiB 0.05 0.00 2.89747 -87.1647 -2.89747 2.89747 0.78 0.000147374 0.0001207 0.0105653 0.00878976 40 2730 42 6.99608e+06 264882 706193. 2443.58 3.56 0.07816 0.066786 26914 176310 -1 2095 31 1958 2789 382662 139932 0 0 382662 139932 2789 2436 0 0 9252 8163 0 0 18852 11601 0 0 2789 2522 0 0 176428 56998 0 0 172552 58212 0 0 2789 0 0 831 1099 1122 8601 0 0 3.43081 3.43081 -110.481 -3.43081 0 0 926341. 3205.33 0.29 0.09 0.11 -1 -1 0.29 0.0157654 0.0139965 88 49 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_117.v common 6.83 vpr 64.39 MiB -1 -1 0.12 21028 1 0.02 -1 -1 33216 -1 -1 17 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65932 32 32 393 312 1 235 81 17 17 289 -1 unnamed_device 25.9 MiB 1.50 1292 64.4 MiB 0.06 0.00 4.35209 -146.514 -4.35209 4.35209 0.78 0.000178536 0.000147088 0.0149059 0.0125638 38 3809 25 6.99608e+06 250167 678818. 2348.85 2.08 0.0710866 0.0614937 26626 170182 -1 3140 19 2333 3502 301873 60728 0 0 301873 60728 3502 2787 0 0 10525 9429 0 0 17895 11426 0 0 3502 2950 0 0 135443 16857 0 0 131006 17279 0 0 3502 0 0 1169 1179 1281 10191 0 0 4.83824 4.83824 -176.815 -4.83824 0 0 902133. 3121.57 0.71 0.10 0.11 -1 -1 0.71 0.024888 0.0235096 105 62 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_118.v common 6.35 vpr 63.68 MiB -1 -1 0.10 20444 1 0.00 -1 -1 33136 -1 -1 13 31 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65212 31 32 229 197 1 137 76 17 17 289 -1 unnamed_device 25.3 MiB 0.74 841 63.7 MiB 0.05 0.00 2.70223 -81.2143 -2.70223 2.70223 0.77 0.000116907 9.5653e-05 0.0106093 0.0088213 38 1850 19 6.99608e+06 191304 678818. 2348.85 3.00 0.0600983 0.0510484 26626 170182 -1 1654 22 932 1498 109639 22918 0 0 109639 22918 1498 1181 0 0 4628 4025 0 0 7514 4975 0 0 1498 1254 0 0 46619 6014 0 0 47882 5469 0 0 1498 0 0 566 551 508 4411 0 0 2.81932 2.81932 -102.898 -2.81932 0 0 902133. 3121.57 0.28 0.03 0.10 -1 -1 0.28 0.00895903 0.00800248 54 -1 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_119.v common 7.89 vpr 64.76 MiB -1 -1 0.11 20856 1 0.01 -1 -1 33124 -1 -1 20 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 66312 32 32 412 334 1 258 84 17 17 289 -1 unnamed_device 26.3 MiB 2.65 1180 64.8 MiB 0.08 0.00 3.87123 -131.912 -3.87123 3.87123 0.77 0.000181207 0.00014883 0.0180362 0.0150728 40 3623 26 6.99608e+06 294314 706193. 2443.58 2.32 0.082474 0.0710299 26914 176310 -1 3003 23 2639 3326 322623 65875 0 0 322623 65875 3326 3111 0 0 11012 9747 0 0 19743 12862 0 0 3326 3167 0 0 142417 19001 0 0 142799 17987 0 0 3326 0 0 687 679 726 7062 0 0 5.3332 5.3332 -183.382 -5.3332 0 0 926341. 3205.33 0.30 0.15 0.11 -1 -1 0.30 0.0403153 0.0383357 116 87 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_120.v common 9.89 vpr 64.75 MiB -1 -1 0.12 20760 1 0.02 -1 -1 33128 -1 -1 16 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 66308 32 32 376 318 1 253 80 17 17 289 -1 unnamed_device 26.1 MiB 0.74 945 64.8 MiB 0.06 0.00 3.63182 -126.713 -3.63182 3.63182 0.83 0.000178109 0.000147734 0.0137535 0.0115988 46 3262 32 6.99608e+06 235451 828058. 2865.25 5.94 0.113313 0.0974334 28066 200906 -1 2230 20 2341 2972 273274 59673 0 0 273274 59673 2972 2616 0 0 9220 8216 0 0 15205 10072 0 0 2972 2656 0 0 121718 17497 0 0 121187 18616 0 0 2972 0 0 631 607 420 5978 0 0 4.6754 4.6754 -166.93 -4.6754 0 0 1.01997e+06 3529.29 0.31 0.05 0.28 -1 -1 0.31 0.011136 0.00996457 110 93 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_121.v common 9.42 vpr 64.27 MiB -1 -1 0.12 21088 1 0.02 -1 -1 33180 -1 -1 15 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65808 32 32 360 293 1 219 79 17 17 289 -1 unnamed_device 25.7 MiB 1.42 998 64.3 MiB 0.05 0.00 3.03377 -100.173 -3.03377 3.03377 0.74 0.00016013 0.000130093 0.0107534 0.00904911 38 3297 37 6.99608e+06 220735 678818. 2348.85 5.01 0.0781067 0.0673034 26626 170182 -1 2386 21 1835 2480 253968 64223 0 0 253968 64223 2480 2137 0 0 7922 6930 0 0 12799 8716 0 0 2480 2278 0 0 111791 22463 0 0 116496 21699 0 0 2480 0 0 645 1078 970 7229 0 0 3.35751 3.35751 -123.612 -3.35751 0 0 902133. 3121.57 0.32 0.06 0.11 -1 -1 0.32 0.0196238 0.0182077 94 57 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_122.v common 5.51 vpr 64.39 MiB -1 -1 0.11 20940 1 0.01 -1 -1 33460 -1 -1 15 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65932 32 32 396 299 1 228 79 17 17 289 -1 unnamed_device 25.9 MiB 0.81 1132 64.4 MiB 0.08 0.00 4.65368 -140.023 -4.65368 4.65368 0.73 0.00018689 0.00015217 0.0185991 0.0155642 46 2943 21 6.99608e+06 220735 828058. 2865.25 1.97 0.0699408 0.0602469 28066 200906 -1 2517 22 2128 3215 290455 58935 0 0 290455 58935 3215 2582 0 0 9923 8800 0 0 18162 11322 0 0 3215 2669 0 0 128207 16755 0 0 127733 16807 0 0 3215 0 0 1087 1173 1187 9440 0 0 4.8755 4.8755 -164.608 -4.8755 0 0 1.01997e+06 3529.29 0.31 0.06 0.13 -1 -1 0.31 0.0156912 0.0141085 98 31 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_123.v common 6.60 vpr 63.47 MiB -1 -1 0.10 20748 1 0.01 -1 -1 33292 -1 -1 12 30 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64996 30 32 224 207 1 132 74 17 17 289 -1 unnamed_device 25.1 MiB 0.61 479 63.5 MiB 0.04 0.00 2.28455 -79.4386 -2.28455 2.28455 0.95 0.000107679 8.6976e-05 0.00760787 0.00628341 44 1393 22 6.99608e+06 176588 787024. 2723.27 3.13 0.0563625 0.04744 27778 195446 -1 994 21 751 972 74443 17941 0 0 74443 17941 972 841 0 0 3205 2839 0 0 5154 3693 0 0 972 877 0 0 33801 4708 0 0 30339 4983 0 0 972 0 0 221 186 166 1987 0 0 2.44542 2.44542 -91.4642 -2.44542 0 0 997811. 3452.63 0.36 0.03 0.14 -1 -1 0.36 0.00863265 0.00774784 53 29 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_124.v common 8.23 vpr 63.83 MiB -1 -1 0.10 20384 1 0.01 -1 -1 33256 -1 -1 14 30 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65364 30 32 286 239 1 157 76 17 17 289 -1 unnamed_device 25.4 MiB 3.27 622 63.8 MiB 0.05 0.00 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0.102734 0.0893851 29506 232905 -1 1583 19 1232 1859 149037 32790 0 0 149037 32790 1859 1510 0 0 5873 5098 0 0 9781 6470 0 0 1859 1618 0 0 60565 9085 0 0 69100 9009 0 0 1859 0 0 627 634 505 5191 0 0 3.15341 3.15341 -116.091 -3.15341 0 0 1.17392e+06 4061.99 0.38 0.04 0.14 -1 -1 0.38 0.010135 0.00907787 78 31 -1 -1 -1 -1 + fixed_k6_frac_2uripple_N8_22nm.xml mult_126.v common 7.52 vpr 63.44 MiB -1 -1 0.10 20616 1 0.02 -1 -1 33324 -1 -1 16 25 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64964 25 32 216 194 1 136 73 17 17 289 -1 unnamed_device 25.0 MiB 0.96 490 63.4 MiB 0.03 0.00 2.77723 -63.3331 -2.77723 2.77723 0.78 0.000104111 8.4649e-05 0.00663185 0.00554901 38 1486 24 6.99608e+06 235451 678818. 2348.85 4.04 0.0746781 0.0645075 26626 170182 -1 1037 20 796 1065 63215 16059 0 0 63215 16059 1065 880 0 0 3485 2959 0 0 5122 3788 0 0 1065 902 0 0 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2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65428 30 32 272 304 1 194 81 17 17 289 -1 unnamed_device 25.5 MiB 2.23 1040 63.9 MiB 0.06 0.00 6.24419 -126.365 -6.24419 6.24419 0.89 0.000215791 0.000178489 0.0188295 0.0163268 34 3412 42 6.79088e+06 255968 618332. 2139.56 3.27 0.114199 0.0985224 25102 150614 -1 2718 20 1499 4160 281353 62585 0 0 281353 62585 4160 2543 0 0 13786 11703 0 0 23938 16339 0 0 4160 2881 0 0 116816 14725 0 0 118493 14394 0 0 4160 0 0 2661 4776 4967 30928 0 0 6.9064 6.9064 -151.265 -6.9064 0 0 787024. 2723.27 0.25 0.06 0.09 -1 -1 0.25 0.017448 0.0158787 125 181 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml mult_003.v common 8.66 vpr 63.76 MiB -1 -1 0.15 21056 11 0.22 -1 -1 35956 -1 -1 19 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65288 32 32 280 312 1 193 83 17 17 289 -1 unnamed_device 25.3 MiB 3.34 1253 63.8 MiB 0.10 0.00 5.55944 -125.582 -5.55944 5.55944 0.92 0.000291188 0.000245643 0.015646 0.0133164 30 3633 39 6.79088e+06 255968 556674. 1926.21 2.23 0.0781968 0.0684073 24526 138013 -1 2786 21 1290 3869 280690 84643 0 0 280690 84643 3869 1975 0 0 11928 10178 0 0 18635 13070 0 0 3869 2254 0 0 119920 29096 0 0 122469 28070 0 0 3869 0 0 2579 4508 4512 31266 0 0 6.0572 6.0572 -147.138 -6.0572 0 0 706193. 2443.58 0.26 0.08 0.08 -1 -1 0.26 0.0202304 0.0184047 130 185 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml mult_004.v common 8.42 vpr 64.04 MiB -1 -1 0.16 21224 12 0.31 -1 -1 35956 -1 -1 24 29 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65580 29 32 275 307 1 202 85 17 17 289 -1 unnamed_device 25.6 MiB 1.02 1191 64.0 MiB 0.04 0.00 6.16917 -123.049 -6.16917 6.16917 0.94 0.000238177 0.000199142 0.00971441 0.00835718 38 2811 20 6.79088e+06 323328 678818. 2348.85 4.14 0.141987 0.124254 25966 169698 -1 2476 20 1316 3665 178908 41302 0 0 178908 41302 3665 1777 0 0 11206 9436 0 0 17303 12081 0 0 3665 2160 0 0 71291 7944 0 0 71778 7904 0 0 3665 0 0 2349 3021 3525 24982 0 0 6.36938 6.36938 -138.019 -6.36938 0 0 902133. 3121.57 0.29 0.05 0.11 -1 -1 0.29 0.0185103 0.016834 136 186 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml mult_005.v common 8.78 vpr 63.94 MiB -1 -1 0.16 21280 13 0.28 -1 -1 35992 -1 -1 22 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65472 32 32 302 334 1 234 86 17 17 289 -1 unnamed_device 25.6 MiB 1.59 1366 63.9 MiB 0.07 0.00 6.88531 -147.057 -6.88531 6.88531 0.89 0.000239713 0.000198345 0.0181604 0.0152129 38 3872 36 6.79088e+06 296384 678818. 2348.85 3.91 0.162026 0.141601 25966 169698 -1 2990 18 1576 4069 216043 49137 0 0 216043 49137 4069 2264 0 0 12826 10870 0 0 19341 13963 0 0 4069 2640 0 0 87457 9836 0 0 88281 9564 0 0 4069 0 0 2493 3406 3511 25159 0 0 7.13591 7.13591 -167.126 -7.13591 0 0 902133. 3121.57 0.28 0.05 0.10 -1 -1 0.28 0.0188001 0.0171419 152 207 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml mult_006.v common 8.51 vpr 64.04 MiB -1 -1 0.17 21120 13 0.23 -1 -1 35996 -1 -1 19 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65580 32 32 292 324 1 210 83 17 17 289 -1 unnamed_device 25.5 MiB 1.50 1303 64.0 MiB 0.07 0.00 6.45897 -132.965 -6.45897 6.45897 0.76 0.000237315 0.000196823 0.0183292 0.0152988 44 3241 33 6.79088e+06 255968 787024. 2723.27 3.72 0.138613 0.119888 27118 194962 -1 2663 18 1204 3576 195345 43321 0 0 195345 43321 3576 1675 0 0 11269 9595 0 0 18512 12794 0 0 3576 2003 0 0 80113 8634 0 0 78299 8620 0 0 3576 0 0 2372 3920 3772 29158 0 0 6.83487 6.83487 -153.874 -6.83487 0 0 997811. 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0.15 20668 12 0.18 -1 -1 36128 -1 -1 17 31 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65000 31 32 229 261 1 188 80 17 17 289 -1 unnamed_device 25.1 MiB 2.66 1145 63.5 MiB 0.06 0.00 5.2739 -114.048 -5.2739 5.2739 0.76 0.000187391 0.000156365 0.0156933 0.0132571 44 2907 17 6.79088e+06 229024 787024. 2723.27 3.75 0.109593 0.0956702 27118 194962 -1 2337 21 1023 2601 145666 32159 0 0 145666 32159 2601 1436 0 0 8101 6954 0 0 12940 9048 0 0 2601 1670 0 0 59408 6569 0 0 60015 6482 0 0 2601 0 0 1578 2298 2675 17600 0 0 5.61055 5.61055 -131.352 -5.61055 0 0 997811. 3452.63 0.34 0.04 0.13 -1 -1 0.34 0.0159664 0.0145924 106 136 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml mult_009.v common 7.74 vpr 63.45 MiB -1 -1 0.15 21276 12 0.17 -1 -1 35960 -1 -1 20 31 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64968 31 32 235 267 1 194 83 17 17 289 -1 unnamed_device 25.0 MiB 2.92 1133 63.4 MiB 0.03 0.00 5.70019 -124.604 -5.70019 5.70019 0.73 0.000195933 0.00016348 0.00808745 0.00696729 38 2920 25 6.79088e+06 269440 678818. 2348.85 2.09 0.0740126 0.0646989 25966 169698 -1 2442 17 1194 3132 182074 40493 0 0 182074 40493 3132 1736 0 0 9743 8344 0 0 15424 10708 0 0 3132 2106 0 0 75247 8752 0 0 75396 8847 0 0 3132 0 0 1938 2759 2766 19613 0 0 6.07609 6.07609 -141.942 -6.07609 0 0 902133. 3121.57 0.27 0.04 0.10 -1 -1 0.27 0.0127731 0.011627 113 142 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml mult_010.v common 8.42 vpr 63.65 MiB -1 -1 0.15 20980 13 0.18 -1 -1 36132 -1 -1 15 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65180 32 32 250 282 1 182 79 17 17 289 -1 unnamed_device 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229024 618332. 2139.56 2.79 0.101848 0.0883207 25102 150614 -1 2224 16 879 2103 128972 29328 0 0 128972 29328 2103 1378 0 0 7058 5801 0 0 11216 8119 0 0 2103 1522 0 0 52228 6463 0 0 54264 6045 0 0 2103 0 0 1224 1815 2090 13862 0 0 6.02149 6.02149 -140.43 -6.02149 0 0 787024. 2723.27 0.26 0.04 0.09 -1 -1 0.26 0.0120554 0.0110595 96 125 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml mult_012.v common 7.48 vpr 63.63 MiB -1 -1 0.14 20792 12 0.13 -1 -1 35876 -1 -1 17 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65160 32 32 236 268 1 171 81 17 17 289 -1 unnamed_device 25.0 MiB 2.24 1051 63.6 MiB 0.04 0.00 5.05901 -126.733 -5.05901 5.05901 0.91 0.00018613 0.000154546 0.0112252 0.00938261 36 3074 21 6.79088e+06 229024 648988. 2245.63 2.24 0.0590744 0.0513659 25390 158009 -1 2479 16 1070 2884 175736 39419 0 0 175736 39419 2884 1639 0 0 9445 8153 0 0 15879 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-1 -1 0.14 21052 11 0.17 -1 -1 36060 -1 -1 21 29 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65136 29 32 225 257 1 176 82 17 17 289 -1 unnamed_device 25.1 MiB 2.31 923 63.6 MiB 0.07 0.01 5.52794 -112.023 -5.52794 5.52794 0.75 0.000179933 0.000148367 0.01432 0.0121203 38 2527 32 6.79088e+06 282912 678818. 2348.85 4.72 0.120892 0.104469 25966 169698 -1 2151 16 1111 2639 141315 33042 0 0 141315 33042 2639 1515 0 0 8424 7107 0 0 12305 8976 0 0 2639 1767 0 0 55898 7166 0 0 59410 6511 0 0 2639 0 0 1528 1586 1828 13845 0 0 5.65324 5.65324 -128.433 -5.65324 0 0 902133. 3121.57 0.29 0.04 0.11 -1 -1 0.29 0.0122105 0.0111885 106 136 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml mult_016.v common 8.15 vpr 64.23 MiB -1 -1 0.16 21000 12 0.26 -1 -1 36060 -1 -1 24 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65776 32 32 301 333 1 221 88 17 17 289 -1 unnamed_device 25.8 MiB 1.32 1140 64.2 MiB 0.08 0.00 6.12997 -130.612 -6.12997 6.12997 0.76 0.000244278 0.000201359 0.0201751 0.0169863 46 3223 34 6.79088e+06 323328 828058. 2865.25 3.62 0.13697 0.109225 27406 200422 -1 2620 19 1434 4511 256945 67310 0 0 256945 67310 4511 2092 0 0 14133 12255 0 0 23012 15650 0 0 4511 2631 0 0 101788 17953 0 0 108990 16729 0 0 4511 0 0 3077 5081 5207 37026 0 0 6.54158 6.54158 -149.863 -6.54158 0 0 1.01997e+06 3529.29 0.31 0.07 0.12 -1 -1 0.31 0.0201903 0.0184495 145 206 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml mult_017.v common 7.95 vpr 63.97 MiB -1 -1 0.16 21032 14 0.25 -1 -1 35652 -1 -1 19 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65508 32 32 277 309 1 210 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mult_022.v common 10.74 vpr 63.88 MiB -1 -1 0.17 20932 13 0.27 -1 -1 35720 -1 -1 21 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65412 32 32 288 320 1 216 85 17 17 289 -1 unnamed_device 25.3 MiB 2.28 1414 63.9 MiB 0.06 0.00 6.21612 -140.759 -6.21612 6.21612 0.82 0.000232347 0.000185751 0.0167994 0.0141472 38 3991 45 6.79088e+06 282912 678818. 2348.85 5.23 0.13251 0.116659 25966 169698 -1 3206 18 1440 4261 252755 53927 0 0 252755 53927 4261 2195 0 0 13148 11323 0 0 20495 14245 0 0 4261 2622 0 0 104261 12012 0 0 106329 11530 0 0 4261 0 0 2821 5496 5095 34087 0 0 6.71732 6.71732 -161.735 -6.71732 0 0 902133. 3121.57 0.29 0.06 0.12 -1 -1 0.29 0.0176548 0.016124 141 193 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml mult_023.v common 6.31 vpr 63.25 MiB -1 -1 0.11 20412 9 0.09 -1 -1 35488 -1 -1 18 26 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64772 26 32 152 184 1 122 76 17 17 289 -1 unnamed_device 24.7 MiB 1.09 674 63.3 MiB 0.04 0.00 3.8527 -78.6612 -3.8527 3.8527 0.77 0.000120304 9.9505e-05 0.00958496 0.00798748 30 1657 19 6.79088e+06 242496 556674. 1926.21 2.42 0.0511562 0.0437466 24526 138013 -1 1355 15 631 1421 69387 16771 0 0 69387 16771 1421 793 0 0 4431 3786 0 0 6710 4762 0 0 1421 854 0 0 27573 3307 0 0 27831 3269 0 0 1421 0 0 790 440 962 7287 0 0 3.8527 3.8527 -88.3248 -3.8527 0 0 706193. 2443.58 0.23 0.02 0.08 -1 -1 0.23 0.00705089 0.00637014 67 69 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml mult_024.v common 8.55 vpr 63.90 MiB -1 -1 0.14 20772 13 0.27 -1 -1 36220 -1 -1 23 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65436 32 32 287 319 1 214 87 17 17 289 -1 unnamed_device 25.4 MiB 1.90 1311 63.9 MiB 0.05 0.00 6.87423 -142.05 -6.87423 6.87423 0.91 0.000236777 0.000187678 0.0138264 0.0115876 38 3622 26 6.79088e+06 309856 678818. 2348.85 3.42 0.0956924 0.0830523 25966 169698 -1 2790 16 1324 3715 194990 44294 0 0 194990 44294 3715 1885 0 0 11609 9931 0 0 17639 12451 0 0 3715 2266 0 0 77247 9139 0 0 81065 8622 0 0 3715 0 0 2391 3594 3585 24733 0 0 7.12483 7.12483 -159.274 -7.12483 0 0 902133. 3121.57 0.28 0.05 0.10 -1 -1 0.28 0.0163373 0.0149677 136 192 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml mult_025.v common 7.76 vpr 63.21 MiB -1 -1 0.11 20236 8 0.06 -1 -1 35468 -1 -1 11 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64724 32 32 154 186 1 126 75 17 17 289 -1 unnamed_device 24.7 MiB 1.88 594 63.2 MiB 0.02 0.00 3.54052 -79.1271 -3.54052 3.54052 0.83 0.000114905 9.4229e-05 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v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64876 30 32 213 245 1 164 80 17 17 289 -1 unnamed_device 24.9 MiB 2.01 1022 63.4 MiB 0.04 0.00 5.07364 -114.347 -5.07364 5.07364 0.68 0.000165637 0.000136293 0.0105564 0.00882432 36 2615 24 6.79088e+06 242496 648988. 2245.63 9.89 0.111021 0.0953955 25390 158009 -1 2272 15 978 2361 154150 34252 0 0 154150 34252 2361 1570 0 0 7879 6703 0 0 12652 9089 0 0 2361 1737 0 0 60894 8210 0 0 68003 6943 0 0 2361 0 0 1383 1866 1808 13046 0 0 5.32424 5.32424 -134.352 -5.32424 0 0 828058. 2865.25 0.26 0.04 0.10 -1 -1 0.26 0.0105216 0.00964434 95 122 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml mult_031.v common 6.45 vpr 63.38 MiB -1 -1 0.15 20904 11 0.16 -1 -1 35860 -1 -1 21 28 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64904 28 32 227 259 1 171 81 17 17 289 -1 unnamed_device 24.9 MiB 1.45 997 63.4 MiB 0.04 0.00 5.49223 -108.467 -5.49223 5.49223 0.76 0.000179275 0.00014827 0.0103649 0.00877269 34 2718 35 6.79088e+06 282912 618332. 2139.56 1.98 0.0667511 0.0581167 25102 150614 -1 2246 15 963 2598 166353 36984 0 0 166353 36984 2598 1475 0 0 8591 7260 0 0 14876 10294 0 0 2598 1700 0 0 68009 8180 0 0 69681 8075 0 0 2598 0 0 1635 2681 2450 17854 0 0 5.99343 5.99343 -127.534 -5.99343 0 0 787024. 2723.27 0.27 0.04 0.10 -1 -1 0.27 0.0119885 0.0110214 109 140 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml mult_032.v common 15.32 vpr 63.65 MiB -1 -1 0.13 20676 12 0.21 -1 -1 35292 -1 -1 17 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65180 32 32 274 306 1 209 81 17 17 289 -1 unnamed_device 25.1 MiB 2.56 1143 63.7 MiB 0.07 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dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65592 31 32 307 339 1 226 87 17 17 289 -1 unnamed_device 25.7 MiB 2.50 1378 64.1 MiB 0.06 0.00 6.09421 -131.718 -6.09421 6.09421 0.77 0.000254501 0.000213523 0.0148855 0.0127081 38 3915 48 6.79088e+06 323328 678818. 2348.85 3.31 0.125512 0.109215 25966 169698 -1 3123 19 1583 4700 260296 57264 0 0 260296 57264 4700 2236 0 0 14067 12176 0 0 22513 15133 0 0 4700 2703 0 0 106080 12717 0 0 108236 12299 0 0 4700 0 0 3117 4380 4742 33257 0 0 6.42321 6.42321 -148.255 -6.42321 0 0 902133. 3121.57 0.29 0.07 0.11 -1 -1 0.29 0.0209395 0.0190436 146 214 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml mult_039.v common 6.90 vpr 63.98 MiB -1 -1 0.18 21276 14 0.34 -1 -1 36092 -1 -1 22 31 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65516 31 32 293 325 1 209 85 17 17 289 -1 unnamed_device 25.5 MiB 1.29 1297 64.0 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0.19 -1 -1 35932 -1 -1 16 31 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65092 31 32 249 281 1 186 79 17 17 289 -1 unnamed_device 25.1 MiB 2.28 1170 63.6 MiB 0.04 0.00 5.48104 -120.034 -5.48104 5.48104 0.74 0.000226927 0.000191725 0.00989325 0.00841032 38 3180 32 6.79088e+06 215552 678818. 2348.85 2.62 0.0963892 0.0821146 25966 169698 -1 2562 18 1263 3688 199284 44094 0 0 199284 44094 3688 1782 0 0 11154 9796 0 0 17727 12076 0 0 3688 2130 0 0 80946 9227 0 0 82081 9083 0 0 3688 0 0 2425 3402 3429 24674 0 0 5.61747 5.61747 -134.753 -5.61747 0 0 902133. 3121.57 0.27 0.05 0.10 -1 -1 0.27 0.0142081 0.0129587 112 156 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml mult_045.v common 6.86 vpr 63.86 MiB -1 -1 0.16 21344 13 0.27 -1 -1 35964 -1 -1 20 31 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65388 31 32 284 316 1 193 83 17 17 289 -1 unnamed_device 25.3 MiB 1.67 1191 63.9 MiB 0.08 0.02 6.38411 -136.826 -6.38411 6.38411 0.76 0.000225904 0.00018696 0.0175614 0.0148561 36 3382 39 6.79088e+06 269440 648988. 2245.63 2.16 0.0942403 0.0820247 25390 158009 -1 2793 18 1275 3958 262785 58474 0 0 262785 58474 3958 1950 0 0 12936 11144 0 0 21603 15061 0 0 3958 2243 0 0 108527 14534 0 0 111803 13542 0 0 3958 0 0 2683 4881 5199 35149 0 0 6.92102 6.92102 -158.525 -6.92102 0 0 828058. 2865.25 0.32 0.07 0.10 -1 -1 0.32 0.0180159 0.0163458 137 191 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml mult_046.v common 9.95 vpr 64.12 MiB -1 -1 0.16 21044 12 0.26 -1 -1 36092 -1 -1 21 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65660 32 32 303 335 1 212 85 17 17 289 -1 unnamed_device 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Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65524 32 32 291 323 1 214 85 17 17 289 -1 unnamed_device 25.5 MiB 2.24 1289 64.0 MiB 0.08 0.00 6.51285 -133.328 -6.51285 6.51285 0.78 0.000236367 0.000195638 0.0218557 0.0184672 36 3598 30 6.79088e+06 282912 648988. 2245.63 2.53 0.0961287 0.0833882 25390 158009 -1 3150 18 1499 4133 253139 56552 0 0 253139 56552 4133 2336 0 0 13380 11269 0 0 22388 15552 0 0 4133 2706 0 0 104804 12484 0 0 104301 12205 0 0 4133 0 0 2634 3719 4277 28725 0 0 6.84955 6.84955 -155.659 -6.84955 0 0 828058. 2865.25 0.30 0.06 0.12 -1 -1 0.30 0.0173227 0.0158159 136 196 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml mult_053.v common 6.80 vpr 63.99 MiB -1 -1 0.19 21248 13 0.28 -1 -1 36052 -1 -1 21 31 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65524 31 32 302 334 1 224 84 17 17 289 -1 unnamed_device 25.4 MiB 1.83 1358 64.0 MiB 0.04 0.00 6.45902 -141.579 -6.45902 6.45902 0.72 0.000258621 0.000208126 0.0110902 0.00941917 38 3856 47 6.79088e+06 282912 678818. 2348.85 1.97 0.0945883 0.0823556 25966 169698 -1 3015 19 1644 4634 257332 56401 0 0 257332 56401 4634 2439 0 0 14162 12164 0 0 22414 15365 0 0 4634 2878 0 0 104647 11916 0 0 106841 11639 0 0 4634 0 0 2990 5428 4962 34784 0 0 6.87412 6.87412 -161.98 -6.87412 0 0 902133. 3121.57 0.29 0.06 0.10 -1 -1 0.29 0.0192762 0.0175373 144 209 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml mult_054.v common 8.84 vpr 64.39 MiB -1 -1 0.17 21052 12 0.29 -1 -1 36252 -1 -1 21 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65936 32 32 308 340 1 225 85 17 17 289 -1 unnamed_device 25.7 MiB 1.72 1293 64.4 MiB 0.07 0.00 6.36178 -135.889 -6.36178 6.36178 0.71 0.000236792 0.000195278 0.0205837 0.0172214 44 3519 21 6.79088e+06 282912 787024. 2723.27 3.97 0.138955 0.120008 27118 194962 -1 2727 19 1417 3995 212419 49124 0 0 212419 49124 3995 2008 0 0 12558 10967 0 0 20986 14613 0 0 3995 2396 0 0 85040 9575 0 0 85845 9565 0 0 3995 0 0 2578 3458 3892 26505 0 0 6.70613 6.70613 -152.493 -6.70613 0 0 997811. 3452.63 0.31 0.05 0.12 -1 -1 0.31 0.0184373 0.0168403 147 213 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml mult_055.v common 6.36 vpr 63.55 MiB -1 -1 0.12 21012 11 0.13 -1 -1 35840 -1 -1 14 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65080 32 32 216 248 1 160 78 17 17 289 -1 unnamed_device 25.1 MiB 1.20 794 63.6 MiB 0.04 0.00 5.10508 -108.421 -5.10508 5.10508 0.77 0.000181764 0.000152153 0.00936407 0.00816804 36 2535 27 6.79088e+06 188608 648988. 2245.63 2.27 0.098053 0.0891661 25390 158009 -1 1909 16 859 2142 120134 29045 0 0 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fixed_k6_frac_N8_22nm.xml mult_058.v common 8.82 vpr 64.05 MiB -1 -1 0.17 21316 13 0.26 -1 -1 36204 -1 -1 21 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65592 32 32 271 303 1 215 85 17 17 289 -1 unnamed_device 25.6 MiB 1.50 1376 64.1 MiB 0.05 0.00 6.76001 -145.356 -6.76001 6.76001 1.00 0.00021665 0.000179164 0.0134376 0.0113907 44 3288 30 6.79088e+06 282912 787024. 2723.27 3.98 0.124725 0.10814 27118 194962 -1 2771 15 1175 3162 178831 39965 0 0 178831 39965 3162 1625 0 0 10172 8763 0 0 16679 11637 0 0 3162 1930 0 0 72694 7899 0 0 72962 8111 0 0 3162 0 0 1987 2989 3471 22971 0 0 7.13591 7.13591 -167.393 -7.13591 0 0 997811. 3452.63 0.35 0.07 0.12 -1 -1 0.35 0.0281015 0.0267545 134 176 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml mult_059.v common 5.18 vpr 63.60 MiB -1 -1 0.15 20880 11 0.16 -1 -1 35908 -1 -1 17 30 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65124 30 32 224 256 1 163 79 17 17 289 -1 unnamed_device 25.1 MiB 0.86 1031 63.6 MiB 0.03 0.00 5.69249 -122.087 -5.69249 5.69249 0.73 0.00017787 0.000145884 0.00717456 0.00610064 30 3073 40 6.79088e+06 229024 556674. 1926.21 1.56 0.0562474 0.048767 24526 138013 -1 2346 19 1081 3063 181983 40071 0 0 181983 40071 3063 1680 0 0 9470 8233 0 0 15314 10317 0 0 3063 1926 0 0 75231 8929 0 0 75842 8986 0 0 3063 0 0 1982 3192 3343 22052 0 0 6.15444 6.15444 -143.566 -6.15444 0 0 706193. 2443.58 0.23 0.04 0.09 -1 -1 0.23 0.0132275 0.0119927 101 133 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml mult_060.v common 7.33 vpr 64.41 MiB -1 -1 0.18 21604 15 0.51 -1 -1 36228 -1 -1 25 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65952 32 32 351 383 1 259 89 17 17 289 -1 unnamed_device 25.9 MiB 1.06 1508 64.4 MiB 0.12 0.00 7.85565 -160.53 -7.85565 7.85565 1.07 0.000314542 0.000256659 0.0319188 0.0288541 46 3663 20 6.79088e+06 336800 828058. 2865.25 2.38 0.183224 0.167638 27406 200422 -1 3103 17 1631 4799 231484 53930 0 0 231484 53930 4799 2080 0 0 15074 12867 0 0 23290 16492 0 0 4799 2548 0 0 92947 10009 0 0 90575 9934 0 0 4799 0 0 3168 5380 4993 38516 0 0 8.35685 8.35685 -180.562 -8.35685 0 0 1.01997e+06 3529.29 0.35 0.07 0.13 -1 -1 0.35 0.0242742 0.0218444 179 256 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml mult_061.v common 7.37 vpr 64.12 MiB -1 -1 0.16 21100 13 0.31 -1 -1 36372 -1 -1 20 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65660 32 32 297 329 1 217 84 17 17 289 -1 unnamed_device 25.5 MiB 1.06 1287 64.1 MiB 0.08 0.00 6.76001 -145.768 -6.76001 6.76001 0.77 0.000325647 0.000280116 0.0209019 0.0175271 36 3383 42 6.79088e+06 269440 648988. 2245.63 3.17 0.116077 0.10088 25390 158009 -1 2867 19 1274 3509 197103 44628 0 0 197103 44628 3509 1907 0 0 11327 9593 0 0 18708 12930 0 0 3509 2201 0 0 80404 9050 0 0 79646 8947 0 0 3509 0 0 2235 3472 4127 25943 0 0 7.01061 7.01061 -163.515 -7.01061 0 0 828058. 2865.25 0.31 0.05 0.10 -1 -1 0.31 0.0190472 0.0174242 139 202 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml mult_062.v common 7.39 vpr 63.34 MiB -1 -1 0.13 20512 11 0.12 -1 -1 35824 -1 -1 13 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64860 32 32 231 263 1 165 77 17 17 289 -1 unnamed_device 24.8 MiB 1.33 1049 63.3 MiB 0.06 0.00 5.40613 -119.346 -5.40613 5.40613 0.77 0.000177706 0.000146683 0.0141032 0.0118303 38 2501 18 6.79088e+06 175136 678818. 2348.85 3.27 0.105789 0.0885374 25966 169698 -1 2078 17 839 2186 126988 28238 0 0 126988 28238 2186 1129 0 0 7007 5970 0 0 10962 7712 0 0 2186 1309 0 0 51543 6314 0 0 53104 5804 0 0 2186 0 0 1347 1941 1895 14229 0 0 5.65673 5.65673 -135.986 -5.65673 0 0 902133. 3121.57 0.29 0.04 0.10 -1 -1 0.29 0.0124962 0.0114177 94 136 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml mult_063.v common 11.34 vpr 64.15 MiB -1 -1 0.15 21200 12 0.31 -1 -1 35696 -1 -1 20 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65692 32 32 305 337 1 217 84 17 17 289 -1 unnamed_device 25.8 MiB 1.08 1356 64.2 MiB 0.06 0.00 6.42326 -135.664 -6.42326 6.42326 1.05 0.000251504 0.000207131 0.0162334 0.0137163 36 3830 50 6.79088e+06 269440 648988. 2245.63 6.80 0.122722 0.106905 25390 158009 -1 3091 17 1441 4415 280502 60401 0 0 280502 60401 4415 2273 0 0 14144 12138 0 0 23784 16345 0 0 4415 2596 0 0 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36064 -1 -1 26 29 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65380 29 32 275 307 1 201 87 17 17 289 -1 unnamed_device 25.3 MiB 2.12 1225 63.8 MiB 0.03 0.00 6.25527 -120.607 -6.25527 6.25527 0.76 0.000243406 0.000205314 0.00846641 0.00728542 38 3120 32 6.79088e+06 350272 678818. 2348.85 2.35 0.0952202 0.0835898 25966 169698 -1 2713 19 1201 3592 194871 42943 0 0 194871 42943 3592 1701 0 0 11085 9504 0 0 17111 11905 0 0 3592 2081 0 0 81361 8731 0 0 78130 9021 0 0 3592 0 0 2391 4824 4309 30766 0 0 6.38057 6.38057 -135.001 -6.38057 0 0 902133. 3121.57 0.30 0.05 0.11 -1 -1 0.30 0.0184426 0.0168651 140 186 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml mult_067.v common 9.53 vpr 64.25 MiB -1 -1 0.16 20992 13 0.33 -1 -1 35948 -1 -1 23 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65796 32 32 330 362 1 257 87 17 17 289 -1 unnamed_device 25.7 MiB 0.97 1481 64.3 MiB 0.07 0.00 6.67386 -141.288 -6.67386 6.67386 0.84 0.000264989 0.000219047 0.0171216 0.014509 36 4215 42 6.79088e+06 309856 648988. 2245.63 5.37 0.125206 0.108829 25390 158009 -1 3406 19 2106 5143 310073 68109 0 0 310073 68109 5143 3052 0 0 16056 13641 0 0 27416 18637 0 0 5143 3504 0 0 129173 14467 0 0 127142 14808 0 0 5143 0 0 3037 4449 4966 30917 0 0 7.21077 7.21077 -168.857 -7.21077 0 0 828058. 2865.25 0.27 0.07 0.10 -1 -1 0.27 0.0202385 0.0184154 160 235 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml mult_068.v common 8.41 vpr 64.02 MiB -1 -1 0.16 21064 12 0.22 -1 -1 36256 -1 -1 20 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65560 32 32 290 322 1 218 84 17 17 289 -1 unnamed_device 25.5 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-1 -1 0.15 21328 13 0.19 -1 -1 35892 -1 -1 18 30 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65024 30 32 235 267 1 172 80 17 17 289 -1 unnamed_device 25.1 MiB 1.72 1061 63.5 MiB 0.06 0.00 5.9509 -124.204 -5.9509 5.9509 0.76 0.00020179 0.000169562 0.01783 0.0152826 36 3047 41 6.79088e+06 242496 648988. 2245.63 4.26 0.0971798 0.0843146 25390 158009 -1 2333 17 998 2787 160649 36602 0 0 160649 36602 2787 1444 0 0 9084 7800 0 0 14818 10464 0 0 2787 1769 0 0 66366 7589 0 0 64807 7536 0 0 2787 0 0 1789 2651 2720 19045 0 0 6.11529 6.11529 -139.373 -6.11529 0 0 828058. 2865.25 0.37 0.08 0.10 -1 -1 0.37 0.0214285 0.0200647 108 144 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml mult_074.v common 6.95 vpr 63.61 MiB -1 -1 0.15 21280 12 0.19 -1 -1 35828 -1 -1 18 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65132 32 32 264 296 1 200 82 17 17 289 -1 unnamed_device 25.0 MiB 2.23 1225 63.6 MiB 0.04 0.00 5.66792 -136.48 -5.66792 5.66792 0.77 0.00020403 0.000168046 0.010139 0.00857277 38 3074 27 6.79088e+06 242496 678818. 2348.85 1.81 0.0708404 0.0617416 25966 169698 -1 2595 15 1142 3015 165664 37565 0 0 165664 37565 3015 1653 0 0 9531 8186 0 0 14911 10483 0 0 3015 1889 0 0 67073 7853 0 0 68119 7501 0 0 3015 0 0 1873 2739 2468 19209 0 0 6.12992 6.12992 -156.414 -6.12992 0 0 902133. 3121.57 0.29 0.04 0.11 -1 -1 0.29 0.0144377 0.0132649 120 169 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml mult_075.v common 6.54 vpr 63.81 MiB -1 -1 0.15 20824 13 0.29 -1 -1 36056 -1 -1 21 31 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65344 31 32 278 310 1 200 84 17 17 289 -1 unnamed_device 25.3 MiB 1.59 1261 63.8 MiB 0.05 0.00 6.92806 -142.643 -6.92806 6.92806 0.75 0.000226045 0.000187654 0.0141074 0.0119664 36 3374 35 6.79088e+06 282912 648988. 2245.63 2.00 0.105288 0.0915479 25390 158009 -1 2604 17 1213 3219 169237 39678 0 0 169237 39678 3219 1711 0 0 10606 8863 0 0 16699 12008 0 0 3219 1976 0 0 67770 7625 0 0 67724 7495 0 0 3219 0 0 2006 2749 3093 21359 0 0 7.26127 7.26127 -158.56 -7.26127 0 0 828058. 2865.25 0.27 0.05 0.10 -1 -1 0.27 0.0166318 0.0152403 137 185 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml mult_076.v common 8.44 vpr 63.80 MiB -1 -1 0.18 21092 14 0.25 -1 -1 36668 -1 -1 20 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65336 32 32 290 322 1 212 84 17 17 289 -1 unnamed_device 25.3 MiB 1.23 1354 63.8 MiB 0.08 0.00 7.26476 -155.727 -7.26476 7.26476 0.75 0.00025769 0.000217009 0.020999 0.0175838 44 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11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65216 32 32 274 306 1 205 82 17 17 289 -1 unnamed_device 25.2 MiB 1.57 1283 63.7 MiB 0.05 0.00 7.05762 -149.408 -7.05762 7.05762 0.77 0.00023098 0.000193253 0.0196425 0.0181279 44 3170 28 6.79088e+06 242496 787024. 2723.27 1.99 0.0956887 0.0841016 27118 194962 -1 2578 16 1204 3465 207944 44927 0 0 207944 44927 3465 1796 0 0 11013 9484 0 0 19118 12939 0 0 3465 2095 0 0 82894 9921 0 0 87989 8692 0 0 3465 0 0 2261 4315 3901 27654 0 0 7.43352 7.43352 -166.778 -7.43352 0 0 997811. 3452.63 0.32 0.05 0.12 -1 -1 0.32 0.0160954 0.0147727 128 179 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml mult_082.v common 7.86 vpr 63.63 MiB -1 -1 0.17 21260 13 0.21 -1 -1 36236 -1 -1 19 31 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65160 31 32 266 298 1 196 82 17 17 289 -1 unnamed_device 25.0 MiB 1.74 1171 63.6 MiB 0.06 0.00 6.28333 -136.535 -6.28333 6.28333 0.74 0.000214575 0.000177892 0.0164741 0.0138911 36 3329 48 6.79088e+06 255968 648988. 2245.63 3.16 0.11199 0.0972467 25390 158009 -1 2765 21 1494 4164 269381 58623 0 0 269381 58623 4164 2248 0 0 13128 11198 0 0 23358 15149 0 0 4164 2628 0 0 111207 13896 0 0 113360 13504 0 0 4164 0 0 2670 4227 4428 29701 0 0 6.76985 6.76985 -157.172 -6.76985 0 0 828058. 2865.25 0.25 0.06 0.10 -1 -1 0.25 0.0160286 0.0144632 124 173 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml mult_083.v common 8.83 vpr 63.81 MiB -1 -1 0.17 21240 13 0.20 -1 -1 36632 -1 -1 19 30 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65340 30 32 266 298 1 199 81 17 17 289 -1 unnamed_device 25.4 MiB 1.59 1189 63.8 MiB 0.05 0.00 6.13113 -122.629 -6.13113 6.13113 1.01 0.000205943 0.000169743 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fixed_k6_frac_N8_22nm.xml mult_087.v common 8.72 vpr 63.62 MiB -1 -1 0.17 21276 14 0.22 -1 -1 36112 -1 -1 17 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65144 32 32 267 299 1 200 81 17 17 289 -1 unnamed_device 25.0 MiB 1.77 1036 63.6 MiB 0.04 0.00 7.17517 -141.92 -7.17517 7.17517 0.81 0.000766277 0.000726577 0.0110579 0.00944981 38 3274 23 6.79088e+06 229024 678818. 2348.85 3.75 0.124796 0.108113 25966 169698 -1 2451 16 1193 3138 167604 38496 0 0 167604 38496 3138 1660 0 0 9749 8175 0 0 14838 10460 0 0 3138 1978 0 0 66234 8468 0 0 70507 7755 0 0 3138 0 0 1945 3535 2988 22540 0 0 7.17517 7.17517 -156.944 -7.17517 0 0 902133. 3121.57 0.33 0.04 0.12 -1 -1 0.33 0.0151994 0.0138782 122 172 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml mult_088.v common 9.10 vpr 64.17 MiB -1 -1 0.18 21244 15 0.40 -1 -1 35708 -1 -1 23 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65712 32 32 334 366 1 254 87 17 17 289 -1 unnamed_device 25.6 MiB 1.71 1439 64.2 MiB 0.06 0.00 7.43275 -158.86 -7.43275 7.43275 0.77 0.000273698 0.000228021 0.0154313 0.0131322 46 3719 38 6.79088e+06 309856 828058. 2865.25 4.19 0.162245 0.140762 27406 200422 -1 3134 18 1657 4342 233356 51707 0 0 233356 51707 4342 2191 0 0 13469 11726 0 0 21255 14725 0 0 4342 2648 0 0 92863 10572 0 0 97085 9845 0 0 4342 0 0 2685 3407 3631 27085 0 0 7.89474 7.89474 -178.519 -7.89474 0 0 1.01997e+06 3529.29 0.33 0.07 0.13 -1 -1 0.33 0.0242239 0.0223638 163 239 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml mult_089.v common 6.49 vpr 63.57 MiB -1 -1 0.15 20680 11 0.15 -1 -1 35816 -1 -1 15 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65096 32 32 220 252 1 168 79 17 17 289 -1 unnamed_device 25.1 MiB 1.57 972 63.6 MiB 0.05 0.00 5.50342 -119.473 -5.50342 5.50342 0.89 0.000169651 0.000139625 0.0127336 0.0107112 30 2696 50 6.79088e+06 202080 556674. 1926.21 1.77 0.0658236 0.0575083 24526 138013 -1 2220 16 946 2522 147242 33404 0 0 147242 33404 2522 1498 0 0 8053 6920 0 0 12142 8764 0 0 2522 1651 0 0 60658 7459 0 0 61345 7112 0 0 2522 0 0 1576 2784 2607 19179 0 0 5.82887 5.82887 -141.368 -5.82887 0 0 706193. 2443.58 0.24 0.04 0.08 -1 -1 0.24 0.0115323 0.0105092 97 125 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml mult_090.v common 6.55 vpr 63.60 MiB -1 -1 0.14 20792 12 0.18 -1 -1 36064 -1 -1 17 31 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65124 31 32 244 276 1 193 80 17 17 289 -1 unnamed_device 25.2 MiB 1.57 1184 63.6 MiB 0.04 0.00 5.44959 -123.238 -5.44959 5.44959 0.77 0.000203561 0.000159552 0.00975904 0.00818999 36 3582 31 6.79088e+06 229024 648988. 2245.63 1.95 0.0731345 0.0634515 25390 158009 -1 2755 18 1392 3916 241313 53688 0 0 241313 53688 3916 2362 0 0 12412 10830 0 0 21265 14385 0 0 3916 2717 0 0 98548 12001 0 0 101256 11393 0 0 3916 0 0 2524 4127 4270 27195 0 0 5.822 5.822 -145.271 -5.822 0 0 828058. 2865.25 0.28 0.05 0.11 -1 -1 0.28 0.0138571 0.0126162 112 151 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml mult_091.v common 8.57 vpr 64.04 MiB -1 -1 0.17 21328 12 0.29 -1 -1 36376 -1 -1 19 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65580 32 32 300 332 1 219 83 17 17 289 -1 unnamed_device 25.6 MiB 1.15 1382 64.0 MiB 0.04 0.00 6.21181 -135.633 -6.21181 6.21181 0.84 0.000241788 0.000200302 0.0101718 0.00881031 44 3306 21 6.79088e+06 255968 787024. 2723.27 4.17 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36064 -1 -1 19 27 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64960 27 32 219 251 1 163 78 17 17 289 -1 unnamed_device 24.8 MiB 1.95 900 63.4 MiB 0.05 0.00 5.66792 -104.013 -5.66792 5.66792 0.73 0.000172559 0.000142821 0.0137303 0.0115536 28 2759 46 6.79088e+06 255968 531479. 1839.03 1.14 0.0608044 0.0525071 23950 126010 -1 2168 17 1061 2691 167754 38601 0 0 167754 38601 2691 1682 0 0 8981 7544 0 0 14571 10455 0 0 2691 1848 0 0 70761 8375 0 0 68059 8697 0 0 2691 0 0 1630 2208 2753 16602 0 0 5.70363 5.70363 -121.758 -5.70363 0 0 648988. 2245.63 0.22 0.04 0.08 -1 -1 0.22 0.012587 0.0114428 104 134 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml mult_096.v common 10.66 vpr 64.57 MiB -1 -1 0.19 21864 13 0.43 -1 -1 36484 -1 -1 26 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 66116 32 32 380 412 1 276 90 17 17 289 -1 unnamed_device 25.9 MiB 1.51 1693 64.6 MiB 0.07 0.00 6.75763 -141.164 -6.75763 6.75763 0.80 0.000319098 0.000263358 0.0207416 0.0174847 44 4792 33 6.79088e+06 350272 787024. 2723.27 5.56 0.210951 0.183696 27118 194962 -1 3711 20 1876 5904 320171 70261 0 0 320171 70261 5904 2649 0 0 18133 15718 0 0 30383 20725 0 0 5904 3455 0 0 130905 13541 0 0 128942 14173 0 0 5904 0 0 4028 6932 6886 48996 0 0 7.05513 7.05513 -157.496 -7.05513 0 0 997811. 3452.63 0.33 0.08 0.12 -1 -1 0.33 0.0258132 0.0234824 188 285 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml mult_097.v common 8.91 vpr 64.09 MiB -1 -1 0.18 21204 14 0.24 -1 -1 36304 -1 -1 22 31 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65632 31 32 277 309 1 197 85 17 17 289 -1 unnamed_device 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242496 618332. 2139.56 6.14 0.128729 0.111553 25102 150614 -1 2528 17 1086 2740 167858 37955 0 0 167858 37955 2740 1653 0 0 9061 7689 0 0 15247 10499 0 0 2740 1837 0 0 68772 8155 0 0 69298 8122 0 0 2740 0 0 1654 2093 2379 16140 0 0 6.52587 6.52587 -155.05 -6.52587 0 0 787024. 2723.27 0.26 0.05 0.09 -1 -1 0.26 0.0147555 0.0135377 109 134 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml mult_099.v common 7.82 vpr 63.81 MiB -1 -1 0.16 21248 13 0.28 -1 -1 36036 -1 -1 18 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65340 32 32 263 295 1 199 82 17 17 289 -1 unnamed_device 25.4 MiB 1.33 1285 63.8 MiB 0.05 0.00 6.71317 -144.222 -6.71317 6.71317 0.74 0.000221835 0.000183233 0.0123791 0.0104804 44 3017 17 6.79088e+06 242496 787024. 2723.27 3.23 0.109027 0.0948404 27118 194962 -1 2513 16 1044 2925 155885 35184 0 0 155885 35184 2925 1384 0 0 9333 7928 0 0 14782 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0.17 20964 15 0.35 -1 -1 35520 -1 -1 22 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65592 32 32 296 328 1 220 86 17 17 289 -1 unnamed_device 25.6 MiB 1.43 1350 64.1 MiB 0.06 0.00 7.21442 -154.203 -7.21442 7.21442 0.80 0.000251444 0.000209358 0.0160003 0.0136124 38 3568 28 6.79088e+06 296384 678818. 2348.85 2.09 0.0887445 0.0776075 25966 169698 -1 2823 16 1292 4110 210792 47621 0 0 210792 47621 4110 1919 0 0 12633 10784 0 0 19987 13704 0 0 4110 2348 0 0 84176 9644 0 0 85776 9222 0 0 4110 0 0 2818 4603 4730 34469 0 0 7.67991 7.67991 -172.743 -7.67991 0 0 902133. 3121.57 0.28 0.05 0.10 -1 -1 0.28 0.0172665 0.0158513 147 201 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml mult_103.v common 9.18 vpr 64.01 MiB -1 -1 0.16 21628 13 0.32 -1 -1 36240 -1 -1 21 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65548 32 32 285 317 1 217 85 17 17 289 -1 unnamed_device 25.4 MiB 2.01 1369 64.0 MiB 0.10 0.00 6.57668 -145.772 -6.57668 6.57668 0.84 0.000258261 0.000217459 0.0232133 0.0213225 38 3571 41 6.79088e+06 282912 678818. 2348.85 3.78 0.164871 0.144671 25966 169698 -1 2812 17 1353 4018 200343 45591 0 0 200343 45591 4018 1939 0 0 12400 10433 0 0 18991 13422 0 0 4018 2296 0 0 78230 9052 0 0 82686 8449 0 0 4018 0 0 2665 4512 4340 31495 0 0 7.03867 7.03867 -166.923 -7.03867 0 0 902133. 3121.57 0.42 0.09 0.10 -1 -1 0.42 0.0202614 0.0188087 143 190 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml mult_104.v common 7.76 vpr 63.85 MiB -1 -1 0.15 20736 12 0.20 -1 -1 35868 -1 -1 18 29 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65380 29 32 239 271 1 185 79 17 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0.00810214 34 3187 33 6.79088e+06 188608 618332. 2139.56 3.71 0.0955414 0.0824813 25102 150614 -1 2423 15 1109 2695 175547 39921 0 0 175547 39921 2695 1702 0 0 9142 7897 0 0 14971 10519 0 0 2695 1961 0 0 72877 8975 0 0 73167 8867 0 0 2695 0 0 1586 1923 2192 15122 0 0 5.86813 5.86813 -142.187 -5.86813 0 0 787024. 2723.27 0.26 0.04 0.09 -1 -1 0.26 0.0121657 0.0111347 98 140 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml mult_106.v common 6.89 vpr 64.03 MiB -1 -1 0.15 20984 13 0.32 -1 -1 35952 -1 -1 21 31 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65568 31 32 294 326 1 212 84 17 17 289 -1 unnamed_device 25.5 MiB 1.21 1312 64.0 MiB 0.05 0.00 6.9357 -137.041 -6.9357 6.9357 0.76 0.000254098 0.000213779 0.0147278 0.0125925 38 3289 23 6.79088e+06 282912 678818. 2348.85 2.62 0.105847 0.0920669 25966 169698 -1 2757 20 1686 5025 264884 58128 0 0 264884 58128 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-122.984 -5.41372 0 0 787024. 2723.27 0.29 0.04 0.18 -1 -1 0.29 0.0128152 0.0115544 101 130 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml mult_108.v common 9.82 vpr 63.55 MiB -1 -1 0.15 20916 14 0.17 -1 -1 35988 -1 -1 18 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65076 32 32 239 271 1 184 82 17 17 289 -1 unnamed_device 25.1 MiB 2.74 1042 63.6 MiB 0.07 0.00 6.62358 -137.051 -6.62358 6.62358 0.76 0.000213964 0.000170246 0.0173136 0.0143906 34 3062 46 6.79088e+06 242496 618332. 2139.56 4.17 0.188839 0.171893 25102 150614 -1 2646 18 1364 3641 252537 55382 0 0 252537 55382 3641 2207 0 0 12247 10397 0 0 20627 14268 0 0 3641 2462 0 0 103804 13591 0 0 108577 12457 0 0 3641 0 0 2277 3948 4045 26123 0 0 6.90989 6.90989 -158.652 -6.90989 0 0 787024. 2723.27 0.27 0.06 0.09 -1 -1 0.27 0.0160436 0.0146414 110 144 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml mult_109.v common 9.54 vpr 63.78 MiB -1 -1 0.17 21116 13 0.28 -1 -1 36076 -1 -1 20 31 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65308 31 32 266 298 1 209 83 17 17 289 -1 unnamed_device 25.4 MiB 2.37 1245 63.8 MiB 0.05 0.00 6.34835 -135.308 -6.34835 6.34835 0.79 0.000210484 0.000174463 0.0132912 0.0112778 44 3030 38 6.79088e+06 269440 787024. 2723.27 3.96 0.127005 0.110636 27118 194962 -1 2486 15 1221 3155 169521 38422 0 0 169521 38422 3155 1606 0 0 9877 8609 0 0 16336 11382 0 0 3155 1902 0 0 69147 7476 0 0 67851 7447 0 0 3155 0 0 1934 2632 2718 20471 0 0 6.63815 6.63815 -152.531 -6.63815 0 0 997811. 3452.63 0.35 0.05 0.15 -1 -1 0.35 0.0157394 0.0144604 125 173 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml mult_110.v common 9.87 vpr 63.36 MiB -1 -1 0.14 20980 12 0.15 -1 -1 35856 -1 -1 17 31 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64884 31 32 225 257 1 172 80 17 17 289 -1 unnamed_device 24.9 MiB 3.28 889 63.4 MiB 0.04 0.00 5.57833 -115.945 -5.57833 5.57833 0.82 0.000184208 0.000153814 0.0103511 0.00882768 44 2551 25 6.79088e+06 229024 787024. 2723.27 3.54 0.0937751 0.0810233 27118 194962 -1 1940 16 940 2410 140575 33585 0 0 140575 33585 2410 1307 0 0 7850 6775 0 0 13485 9215 0 0 2410 1536 0 0 55397 7555 0 0 59023 7197 0 0 2410 0 0 1470 2062 2356 15914 0 0 5.78203 5.78203 -131.686 -5.78203 0 0 997811. 3452.63 0.34 0.04 0.12 -1 -1 0.34 0.0119143 0.0109212 99 132 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml mult_111.v common 8.26 vpr 63.94 MiB -1 -1 0.17 21340 12 0.19 -1 -1 36356 -1 -1 18 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65476 32 32 288 320 1 203 82 17 17 289 -1 unnamed_device 25.5 MiB 2.07 1075 63.9 MiB 0.05 0.00 5.91508 -127.079 -5.91508 5.91508 0.70 0.000225101 0.000186203 0.013204 0.011172 44 2604 18 6.79088e+06 242496 787024. 2723.27 3.24 0.122956 0.107904 27118 194962 -1 2148 16 1027 3109 161248 36550 0 0 161248 36550 3109 1388 0 0 9767 8206 0 0 15685 10934 0 0 3109 1684 0 0 62227 7342 0 0 67351 6996 0 0 3109 0 0 2082 3619 4226 27502 0 0 6.29098 6.29098 -140.486 -6.29098 0 0 997811. 3452.63 0.31 0.04 0.12 -1 -1 0.31 0.0160795 0.0146793 130 193 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml mult_112.v common 8.48 vpr 64.07 MiB -1 -1 0.18 21028 13 0.29 -1 -1 35960 -1 -1 20 31 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65608 31 32 282 314 1 212 83 17 17 289 -1 unnamed_device 25.5 MiB 1.09 1245 64.1 MiB 0.07 0.00 6.69391 -144.564 -6.69391 6.69391 0.78 0.000228184 0.000188415 0.0206337 0.0174338 44 3263 16 6.79088e+06 269440 787024. 2723.27 4.13 0.112716 0.0976771 27118 194962 -1 2662 17 1221 3507 184131 41655 0 0 184131 41655 3507 1731 0 0 11171 9503 0 0 17529 12561 0 0 3507 2072 0 0 76763 7523 0 0 71654 8265 0 0 3507 0 0 2286 3210 3445 25160 0 0 6.78001 6.78001 -157.619 -6.78001 0 0 997811. 3452.63 0.34 0.05 0.12 -1 -1 0.34 0.017895 0.0164336 143 189 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml mult_113.v common 6.53 vpr 63.67 MiB -1 -1 0.14 20992 11 0.16 -1 -1 35816 -1 -1 16 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65200 32 32 233 265 1 183 80 17 17 289 -1 unnamed_device 25.0 MiB 1.98 1038 63.7 MiB 0.06 0.00 5.0702 -121.482 -5.0702 5.0702 0.73 0.000182525 0.000150937 0.0155394 0.0130332 36 3335 29 6.79088e+06 215552 648988. 2245.63 1.69 0.0830331 0.070595 25390 158009 -1 2690 16 1261 3261 227468 53601 0 0 227468 53601 3261 1962 0 0 10277 8748 0 0 17208 11797 0 0 3261 2271 0 0 93742 15024 0 0 99719 13799 0 0 3261 0 0 2000 3071 3085 20227 0 0 5.52445 5.52445 -144.169 -5.52445 0 0 828058. 2865.25 0.26 0.05 0.10 -1 -1 0.26 0.0130777 0.0119787 106 138 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml mult_114.v common 9.61 vpr 64.05 MiB -1 -1 0.14 20732 13 0.21 -1 -1 35944 -1 -1 15 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65584 32 32 254 286 1 188 79 17 17 289 -1 unnamed_device 25.4 MiB 2.60 1103 64.0 MiB 0.05 0.00 6.29458 -136.168 -6.29458 6.29458 0.88 0.000202781 0.000167256 0.0143707 0.0121014 38 3050 33 6.79088e+06 202080 678818. 2348.85 3.93 0.115421 0.099935 25966 169698 -1 2469 17 1177 3139 178035 40112 0 0 178035 40112 3139 1746 0 0 9872 8477 0 0 15357 10637 0 0 3139 2011 0 0 71965 8881 0 0 74563 8360 0 0 3139 0 0 1962 3351 2870 21866 0 0 6.54518 6.54518 -153.384 -6.54518 0 0 902133. 3121.57 0.27 0.05 0.10 -1 -1 0.27 0.0146354 0.0133305 113 159 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml mult_115.v common 10.31 vpr 63.88 MiB -1 -1 0.14 21060 13 0.25 -1 -1 36404 -1 -1 19 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65408 32 32 285 317 1 214 83 17 17 289 -1 unnamed_device 25.4 MiB 1.13 1307 63.9 MiB 0.06 0.00 6.49473 -143.781 -6.49473 6.49473 0.77 0.000262116 0.000222436 0.0163756 0.0139208 36 4061 35 6.79088e+06 255968 648988. 2245.63 6.17 0.105581 0.0917675 25390 158009 -1 3243 16 1457 4028 273866 59372 0 0 273866 59372 4028 2460 0 0 13238 11178 0 0 22455 15689 0 0 4028 2820 0 0 113368 14022 0 0 116749 13203 0 0 4028 0 0 2571 4468 4570 28629 0 0 6.94909 6.94909 -166.5 -6.94909 0 0 828058. 2865.25 0.27 0.06 0.10 -1 -1 0.27 0.0166043 0.0151508 136 190 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml mult_116.v common 8.67 vpr 63.93 MiB -1 -1 0.15 21296 11 0.20 -1 -1 35984 -1 -1 19 29 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65468 29 32 243 275 1 184 80 17 17 289 -1 unnamed_device 25.4 MiB 2.14 973 63.9 MiB 0.06 0.00 5.38344 -106.741 -5.38344 5.38344 0.75 0.000204593 0.000170251 0.0162237 0.0135287 44 2679 23 6.79088e+06 255968 787024. 2723.27 3.60 0.110231 0.0947722 27118 194962 -1 2004 14 878 2626 131317 30463 0 0 131317 30463 2626 1215 0 0 8160 6964 0 0 13311 9217 0 0 2626 1460 0 0 51381 6006 0 0 53213 5601 0 0 2626 0 0 1748 3079 3129 22536 0 0 5.63404 5.63404 -121.384 -5.63404 0 0 997811. 3452.63 0.33 0.04 0.13 -1 -1 0.33 0.0131573 0.0120982 116 154 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml mult_117.v common 8.32 vpr 64.25 MiB -1 -1 0.18 21404 14 0.33 -1 -1 36428 -1 -1 23 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65788 32 32 318 350 1 238 87 17 17 289 -1 unnamed_device 25.8 MiB 1.63 1358 64.2 MiB 0.07 0.00 7.68761 -161.022 -7.68761 7.68761 0.74 0.000266275 0.000222699 0.0196236 0.0164239 44 3241 18 6.79088e+06 309856 787024. 2723.27 3.42 0.137085 0.118538 27118 194962 -1 2680 18 1330 3529 181202 41270 0 0 181202 41270 3529 1763 0 0 11222 9418 0 0 17401 12652 0 0 3529 2114 0 0 72375 7827 0 0 73146 7496 0 0 3529 0 0 2199 3249 3293 23678 0 0 7.72675 7.72675 -177.297 -7.72675 0 0 997811. 3452.63 0.31 0.05 0.12 -1 -1 0.31 0.0193146 0.0176874 159 223 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml mult_118.v common 6.93 vpr 63.41 MiB -1 -1 0.13 20432 12 0.14 -1 -1 36368 -1 -1 19 31 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64928 31 32 222 254 1 188 82 17 17 289 -1 unnamed_device 24.9 MiB 2.53 1087 63.4 MiB 0.06 0.00 5.36349 -125.306 -5.36349 5.36349 0.72 0.000188037 0.000157209 0.0152241 0.0127257 38 2705 25 6.79088e+06 255968 678818. 2348.85 1.47 0.0619627 0.0538047 25966 169698 -1 2326 17 1087 2540 147294 32505 0 0 147294 32505 2540 1519 0 0 7917 6631 0 0 11979 8481 0 0 2540 1720 0 0 60519 7243 0 0 61799 6911 0 0 2540 0 0 1453 1825 2187 14265 0 0 5.82549 5.82549 -143.04 -5.82549 0 0 902133. 3121.57 0.29 0.04 0.10 -1 -1 0.29 0.0119081 0.0108833 106 129 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml mult_119.v common 7.64 vpr 63.90 MiB -1 -1 0.18 21444 13 0.29 -1 -1 36640 -1 -1 20 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65436 32 32 282 314 1 211 84 17 17 289 -1 unnamed_device 25.4 MiB 1.36 1333 63.9 MiB 0.04 0.00 6.66283 -141.183 -6.66283 6.66283 0.78 0.000253612 0.000199404 0.00991489 0.00841895 38 3556 22 6.79088e+06 269440 678818. 2348.85 3.17 0.100593 0.0824524 25966 169698 -1 3015 18 1376 4005 206847 46644 0 0 206847 46644 4005 1986 0 0 12291 10549 0 0 18788 13051 0 0 4005 2366 0 0 80690 10074 0 0 87068 8618 0 0 4005 0 0 2629 4880 4139 30833 0 0 7.17511 7.17511 -161.281 -7.17511 0 0 902133. 3121.57 0.28 0.05 0.10 -1 -1 0.28 0.0167667 0.0153174 136 187 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml mult_120.v common 7.87 vpr 63.55 MiB -1 -1 0.16 21412 13 0.17 -1 -1 36204 -1 -1 20 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65072 32 32 238 270 1 180 84 17 17 289 -1 unnamed_device 25.1 MiB 1.26 1076 63.5 MiB 0.06 0.00 6.33716 -140.535 -6.33716 6.33716 0.75 0.000191326 0.000159399 0.0150768 0.0126576 36 3088 33 6.79088e+06 269440 648988. 2245.63 3.63 0.104904 0.0906388 25390 158009 -1 2496 17 1127 2945 193875 43508 0 0 193875 43508 2945 1687 0 0 9722 8276 0 0 16380 11531 0 0 2945 1946 0 0 83049 9856 0 0 78834 10212 0 0 2945 0 0 1818 2433 2778 18038 0 0 6.67386 6.67386 -161.639 -6.67386 0 0 828058. 2865.25 0.25 0.04 0.10 -1 -1 0.25 0.012618 0.0115202 107 143 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml mult_121.v common 7.35 vpr 63.79 MiB -1 -1 0.16 21240 12 0.22 -1 -1 36324 -1 -1 19 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65324 32 32 269 301 1 190 83 17 17 289 -1 unnamed_device 25.4 MiB 1.53 1198 63.8 MiB 0.04 0.00 5.87167 -132.399 -5.87167 5.87167 0.73 0.000237284 0.000188331 0.0124231 0.0105142 36 3180 21 6.79088e+06 255968 648988. 2245.63 2.69 0.0893747 0.0776957 25390 158009 -1 2518 17 1085 3212 179823 40993 0 0 179823 40993 3212 1657 0 0 10508 8905 0 0 16897 11932 0 0 3212 1906 0 0 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-1 0.34 0.0267273 0.0243427 183 255 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml mult_123.v common 5.86 vpr 62.91 MiB -1 -1 0.13 20528 10 0.07 -1 -1 35520 -1 -1 12 30 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64424 30 32 172 204 1 133 74 17 17 289 -1 unnamed_device 24.5 MiB 1.49 777 62.9 MiB 0.03 0.00 4.08102 -100.592 -4.08102 4.08102 0.92 0.000137164 0.000113106 0.00768182 0.00642949 38 1821 19 6.79088e+06 161664 678818. 2348.85 1.52 0.0682804 0.0533221 25966 169698 -1 1528 15 667 1610 79756 18836 0 0 79756 18836 1610 907 0 0 4994 4311 0 0 7837 5442 0 0 1610 1041 0 0 33019 3526 0 0 30686 3609 0 0 1610 0 0 943 785 1241 8487 0 0 4.08102 4.08102 -109.614 -4.08102 0 0 902133. 3121.57 0.29 0.03 0.11 -1 -1 0.29 0.00842671 0.00769295 66 81 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml mult_124.v common 6.92 vpr 63.61 MiB -1 -1 0.14 20928 13 0.17 -1 -1 35664 -1 -1 17 30 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65140 30 32 228 260 1 176 79 17 17 289 -1 unnamed_device 25.2 MiB 1.50 921 63.6 MiB 0.04 0.00 6.47021 -131.827 -6.47021 6.47021 0.90 0.000178086 0.000147484 0.00901181 0.00767643 30 3176 33 6.79088e+06 229024 556674. 1926.21 2.37 0.0558305 0.0485678 24526 138013 -1 2353 15 1110 2797 150848 35247 0 0 150848 35247 2797 1740 0 0 8643 7350 0 0 12886 9142 0 0 2797 1989 0 0 60527 7698 0 0 63198 7328 0 0 2797 0 0 1687 2036 2061 15671 0 0 6.72081 6.72081 -151.395 -6.72081 0 0 706193. 2443.58 0.26 0.04 0.09 -1 -1 0.26 0.0127854 0.0117342 103 137 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml mult_125.v common 6.97 vpr 63.69 MiB -1 -1 0.14 21080 12 0.20 -1 -1 35804 -1 -1 18 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65220 32 32 264 296 1 200 82 17 17 289 -1 unnamed_device 25.1 MiB 2.08 1186 63.7 MiB 0.07 0.00 5.90733 -133.846 -5.90733 5.90733 0.93 0.000204422 0.000167266 0.0187323 0.0155964 36 2874 19 6.79088e+06 242496 648988. 2245.63 1.75 0.0721132 0.0624647 25390 158009 -1 2722 15 1203 2948 179704 40203 0 0 179704 40203 2948 1752 0 0 9670 8300 0 0 15993 11089 0 0 2948 1975 0 0 73548 8715 0 0 74597 8372 0 0 2948 0 0 1745 2370 2712 18531 0 0 6.36938 6.36938 -160.172 -6.36938 0 0 828058. 2865.25 0.26 0.05 0.10 -1 -1 0.26 0.0138301 0.012641 117 169 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml mult_126.v common 6.65 vpr 63.16 MiB -1 -1 0.14 20448 9 0.12 -1 -1 35668 -1 -1 18 25 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64676 25 32 183 215 1 134 75 17 17 289 -1 unnamed_device 24.7 MiB 0.84 672 63.2 MiB 0.05 0.00 4.27129 -82.6904 -4.27129 4.27129 0.74 0.000151456 0.000126359 0.0132593 0.0110655 34 2057 21 6.79088e+06 242496 618332. 2139.56 2.86 0.079658 0.0681381 25102 150614 -1 1783 22 840 2420 242161 87077 0 0 242161 87077 2420 1376 0 0 7876 6682 0 0 14987 9698 0 0 2420 1589 0 0 105513 33252 0 0 108945 34480 0 0 2420 0 0 1580 2397 2343 17388 0 0 4.73329 4.73329 -100.948 -4.73329 0 0 787024. 2723.27 0.25 0.05 0.09 -1 -1 0.25 0.011459 0.0103467 86 102 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml mult_127.v common 8.58 vpr 63.96 MiB -1 -1 0.16 20888 12 0.26 -1 -1 35700 -1 -1 21 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65492 32 32 300 332 1 226 85 17 17 289 -1 unnamed_device 25.4 MiB 1.45 1452 64.0 MiB 0.08 0.00 6.04387 -138.13 -6.04387 6.04387 0.91 0.000245179 0.000204282 0.0221724 0.0185135 40 3622 42 6.79088e+06 282912 706193. 2443.58 3.75 0.113168 0.097563 26254 175826 -1 3259 20 1671 4751 355690 79020 0 0 355690 79020 4751 2628 0 0 15341 13204 0 0 27738 18063 0 0 4751 3097 0 0 152912 21104 0 0 150197 20924 0 0 4751 0 0 3080 5451 5433 34399 0 0 6.66688 6.66688 -162.485 -6.66688 0 0 926341. 3205.33 0.30 0.09 0.11 -1 -1 0.30 0.0192856 0.017559 143 205 -1 -1 -1 -1 + fixed_k6_frac_N8_22nm.xml mult_128.v common 7.32 vpr 64.16 MiB -1 -1 0.17 21716 13 0.30 -1 -1 35960 -1 -1 22 31 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65704 31 32 290 322 1 215 85 17 17 289 -1 unnamed_device 25.8 MiB 1.97 1318 64.2 MiB 0.06 0.00 6.928 -146.391 -6.928 6.928 0.95 0.000256613 0.000210336 0.0155816 0.0133518 38 3565 21 6.79088e+06 296384 678818. 2348.85 2.01 0.100315 0.0874284 25966 169698 -1 2879 18 1389 4026 211878 48031 0 0 211878 48031 4026 2080 0 0 12717 10857 0 0 19408 13718 0 0 4026 2437 0 0 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0.27 0.0111099 0.00990866 142 47 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_002.v common 7.25 vpr 64.03 MiB -1 -1 0.12 20632 1 0.02 -1 -1 33256 -1 -1 24 30 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65564 30 32 363 293 1 199 86 17 17 289 -1 unnamed_device 25.5 MiB 2.51 1023 64.0 MiB 0.06 0.00 3.65445 -111.378 -3.65445 3.65445 0.77 0.000161944 0.000132731 0.00996966 0.00840631 30 2165 22 6.87369e+06 335372 556674. 1926.21 2.01 0.0714007 0.0607095 25186 138497 -1 1828 21 1461 2266 106800 28654 0 0 106800 28654 2266 1595 0 0 7883 6632 0 0 10285 8477 0 0 2266 1703 0 0 40904 5431 0 0 43196 4816 0 0 2266 0 0 805 1029 674 6384 0 0 3.82346 3.82346 -132.348 -3.82346 0 0 706193. 2443.58 0.24 0.04 0.09 -1 -1 0.24 0.0115256 0.0101946 138 58 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_003.v common 6.59 vpr 63.76 MiB -1 -1 0.11 20600 1 0.01 -1 -1 33340 -1 -1 21 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65292 32 32 299 247 1 190 85 17 17 289 -1 unnamed_device 25.1 MiB 2.45 1042 63.8 MiB 0.05 0.00 3.45035 -102.032 -3.45035 3.45035 0.93 0.000152425 0.000126974 0.0071143 0.00600103 34 2514 22 6.87369e+06 293451 618332. 2139.56 1.28 0.0514694 0.044075 25762 151098 -1 2079 20 1254 1740 124840 29614 0 0 124840 29614 1740 1475 0 0 6787 5987 0 0 9995 8155 0 0 1740 1541 0 0 52613 6153 0 0 51965 6303 0 0 1740 0 0 486 397 570 4323 0 0 3.65436 3.65436 -121.595 -3.65436 0 0 787024. 2723.27 0.27 0.03 0.10 -1 -1 0.27 0.00971663 0.00863199 124 26 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_004.v common 6.23 vpr 63.77 MiB -1 -1 0.11 20572 1 0.01 -1 -1 33180 -1 -1 29 29 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65304 29 32 308 248 1 172 90 17 17 289 -1 unnamed_device 25.2 MiB 1.01 978 63.8 MiB 0.08 0.00 3.69012 -105.3 -3.69012 3.69012 0.79 0.000145477 0.000118074 0.0114038 0.00893341 34 2326 24 6.87369e+06 405241 618332. 2139.56 2.61 0.0778658 0.0654346 25762 151098 -1 2007 22 1517 2770 206471 47736 0 0 206471 47736 2770 2026 0 0 10543 9114 0 0 16831 13106 0 0 2770 2200 0 0 85716 10941 0 0 87841 10349 0 0 2770 0 0 1253 1636 1623 11086 0 0 3.8134 3.8134 -122.26 -3.8134 0 0 787024. 2723.27 0.25 0.05 0.09 -1 -1 0.25 0.010455 0.00921777 124 25 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_005.v common 7.08 vpr 64.30 MiB -1 -1 0.11 20884 1 0.01 -1 -1 33212 -1 -1 27 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65844 32 32 336 268 1 181 91 17 17 289 -1 unnamed_device 25.8 MiB 1.18 1069 64.3 MiB 0.07 0.00 3.56782 -109.183 -3.56782 3.56782 1.04 0.000346392 0.000127005 0.0113507 0.00927817 34 2765 30 6.87369e+06 377294 618332. 2139.56 2.99 0.0907978 0.0775291 25762 151098 -1 2246 22 1698 3319 233457 55698 0 0 233457 55698 3319 2300 0 0 12793 11517 0 0 19823 15695 0 0 3319 2582 0 0 97510 11505 0 0 96693 12099 0 0 3319 0 0 1621 1914 1883 13417 0 0 3.7854 3.7854 -134.332 -3.7854 0 0 787024. 2723.27 0.25 0.05 0.09 -1 -1 0.25 0.0108863 0.00957812 131 31 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_006.v common 6.70 vpr 64.18 MiB -1 -1 0.11 20872 1 0.01 -1 -1 32984 -1 -1 30 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65720 32 32 366 295 1 189 94 17 17 289 -1 unnamed_device 25.7 MiB 1.44 1066 64.2 MiB 0.07 0.00 2.67957 -99.0661 -2.67957 2.67957 0.76 0.000188099 0.000156683 0.0114655 0.0097022 32 2694 24 6.87369e+06 419215 586450. 2029.24 2.69 0.0748339 0.0637534 25474 144626 -1 2184 21 1429 2255 177295 41458 0 0 177295 41458 2255 1783 0 0 8754 7782 0 0 15216 11799 0 0 2255 1897 0 0 75458 9019 0 0 73357 9178 0 0 2255 0 0 826 963 1016 7598 0 0 2.98531 2.98531 -122.433 -2.98531 0 0 744469. 2576.02 0.24 0.04 0.09 -1 -1 0.24 0.0114335 0.0100908 136 55 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_007.v common 6.85 vpr 63.81 MiB -1 -1 0.11 20516 1 0.01 -1 -1 33344 -1 -1 19 27 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65340 27 32 259 221 1 141 78 17 17 289 -1 unnamed_device 25.2 MiB 2.13 623 63.8 MiB 0.05 0.00 2.94598 -84.4417 -2.94598 2.94598 0.78 0.000122466 0.000100482 0.0104863 0.00873061 28 1724 21 6.87369e+06 265503 531479. 1839.03 1.81 0.059799 0.0504894 24610 126494 -1 1506 19 1105 1811 128352 30527 0 0 128352 30527 1811 1474 0 0 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0 0 618332. 2139.56 0.21 0.05 0.08 -1 -1 0.21 0.0105434 0.00942279 119 -1 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_009.v common 6.33 vpr 64.09 MiB -1 -1 0.12 20916 1 0.01 -1 -1 33192 -1 -1 17 31 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65624 31 32 317 271 1 175 80 17 17 289 -1 unnamed_device 25.4 MiB 2.40 740 64.1 MiB 0.04 0.00 2.65757 -87.8608 -2.65757 2.65757 0.77 0.000150925 0.000123965 0.00798533 0.00666097 34 2329 24 6.87369e+06 237555 618332. 2139.56 1.37 0.0520149 0.0440377 25762 151098 -1 1734 20 1348 1931 145988 35137 0 0 145988 35137 1931 1678 0 0 7497 6516 0 0 11030 8887 0 0 1931 1721 0 0 60317 8319 0 0 63282 8016 0 0 1931 0 0 583 591 518 4789 0 0 3.19191 3.19191 -114.086 -3.19191 0 0 787024. 2723.27 0.24 0.04 0.09 -1 -1 0.24 0.0102839 0.0092098 113 60 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_010.v common 7.66 vpr 63.68 MiB -1 -1 0.10 20876 1 0.01 -1 -1 33184 -1 -1 16 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65204 32 32 298 248 1 162 80 17 17 289 -1 unnamed_device 25.3 MiB 3.69 788 63.7 MiB 0.05 0.00 3.21683 -107.397 -3.21683 3.21683 0.95 0.000142324 0.000116414 0.00724605 0.00603392 34 2094 21 6.87369e+06 223581 618332. 2139.56 1.18 0.0521067 0.0423486 25762 151098 -1 1688 20 1211 2028 140639 35012 0 0 140639 35012 2028 1607 0 0 7651 6709 0 0 11756 9387 0 0 2028 1663 0 0 57961 7696 0 0 59215 7950 0 0 2028 0 0 817 969 1081 7241 0 0 2.90196 2.90196 -116.848 -2.90196 0 0 787024. 2723.27 0.25 0.03 0.09 -1 -1 0.25 0.00879433 0.00773785 107 31 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_011.v common 6.97 vpr 63.99 MiB -1 -1 0.11 20492 1 0.02 -1 -1 33132 -1 -1 16 30 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65524 30 32 303 262 1 148 78 17 17 289 -1 unnamed_device 25.5 MiB 3.05 738 64.0 MiB 0.04 0.00 3.28893 -97.5252 -3.28893 3.28893 0.95 0.000140208 0.000115511 0.00720133 0.0060615 34 1857 20 6.87369e+06 223581 618332. 2139.56 1.21 0.0445488 0.0377192 25762 151098 -1 1562 18 849 1397 90909 21806 0 0 90909 21806 1397 996 0 0 5212 4438 0 0 7749 6062 0 0 1397 1082 0 0 38504 4530 0 0 36650 4698 0 0 1397 0 0 548 492 617 4590 0 0 2.95696 2.95696 -108.436 -2.95696 0 0 787024. 2723.27 0.24 0.03 0.09 -1 -1 0.24 0.00833059 0.00740638 98 58 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_012.v common 6.15 vpr 63.68 MiB -1 -1 0.11 20520 1 0.01 -1 -1 33220 -1 -1 17 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65212 32 32 276 237 1 171 81 17 17 289 -1 unnamed_device 25.3 MiB 2.20 1005 63.7 MiB 0.06 0.00 3.0081 -102.337 -3.0081 3.0081 0.79 0.000141046 0.000116585 0.0107969 0.00895211 34 2346 26 6.87369e+06 237555 618332. 2139.56 1.16 0.0501372 0.0424484 25762 151098 -1 1987 20 1074 1457 105690 25624 0 0 105690 25624 1457 1265 0 0 5812 5184 0 0 8653 7170 0 0 1457 1319 0 0 44780 5258 0 0 43531 5428 0 0 1457 0 0 383 354 331 3309 0 0 3.04261 3.04261 -117.084 -3.04261 0 0 787024. 2723.27 0.24 0.03 0.09 -1 -1 0.24 0.00854075 0.00751312 107 31 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_013.v common 7.59 vpr 63.98 MiB -1 -1 0.10 20768 1 0.01 -1 -1 33032 -1 -1 23 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65520 32 32 344 272 1 209 87 17 17 289 -1 unnamed_device 25.5 MiB 3.56 1017 64.0 MiB 0.10 0.00 3.36593 -110.453 -3.36593 3.36593 0.84 0.00017817 0.000141632 0.0169738 0.0140127 34 2756 22 6.87369e+06 321398 618332. 2139.56 1.29 0.0696636 0.0592661 25762 151098 -1 2349 21 1890 2857 230928 53309 0 0 230928 53309 2857 2366 0 0 11311 10234 0 0 17536 14256 0 0 2857 2398 0 0 99602 11948 0 0 96765 12107 0 0 2857 0 0 967 1102 976 7836 0 0 3.25291 3.25291 -125.762 -3.25291 0 0 787024. 2723.27 0.25 0.05 0.10 -1 -1 0.25 0.0114914 0.0102286 142 31 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_014.v common 6.33 vpr 64.19 MiB -1 -1 0.11 21160 1 0.01 -1 -1 33116 -1 -1 31 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65728 32 32 363 295 1 181 95 17 17 289 -1 unnamed_device 25.6 MiB 2.35 1021 64.2 MiB 0.15 0.00 3.88148 -120.44 -3.88148 3.88148 0.88 0.000177208 0.000146704 0.0156515 0.0130467 26 2784 36 6.87369e+06 433189 503264. 1741.40 1.13 0.0510175 0.0435241 24322 120374 -1 2451 25 1940 3135 271074 61701 0 0 271074 61701 3135 2485 0 0 12547 11208 0 0 19913 15572 0 0 3135 2642 0 0 119178 14510 0 0 113166 15284 0 0 3135 0 0 1195 1553 1607 10816 0 0 4.50896 4.50896 -153.465 -4.50896 0 0 618332. 2139.56 0.20 0.06 0.07 -1 -1 0.20 0.0120359 0.0105486 133 58 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_015.v common 6.98 vpr 63.51 MiB -1 -1 0.11 20424 1 0.01 -1 -1 33216 -1 -1 19 29 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65036 29 32 248 215 1 142 80 17 17 289 -1 unnamed_device 25.0 MiB 1.52 596 63.5 MiB 0.04 0.00 2.63557 -78.8285 -2.63557 2.63557 0.74 0.000132489 0.000109893 0.0077436 0.00641493 28 1964 34 6.87369e+06 265503 531479. 1839.03 2.51 0.0685836 0.0584292 24610 126494 -1 1631 20 1025 1617 119178 29427 0 0 119178 29427 1617 1254 0 0 6077 5243 0 0 8706 7066 0 0 1617 1277 0 0 48523 7342 0 0 52638 7245 0 0 1617 0 0 592 798 617 5004 0 0 3.04661 3.04661 -103.047 -3.04661 0 0 648988. 2245.63 0.31 0.12 0.08 -1 -1 0.31 0.00848247 0.0074983 94 21 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_016.v common 7.50 vpr 64.03 MiB -1 -1 0.10 20872 1 0.02 -1 -1 33112 -1 -1 24 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65568 32 32 370 297 1 191 88 17 17 289 -1 unnamed_device 25.5 MiB 2.01 865 64.0 MiB 0.06 0.00 2.9366 -95.9942 -2.9366 2.9366 0.81 0.000168058 0.000138789 0.0114847 0.00960227 34 2745 26 6.87369e+06 335372 618332. 2139.56 2.82 0.09278 0.0790752 25762 151098 -1 1943 23 1600 2805 214244 50958 0 0 214244 50958 2805 2058 0 0 10861 9679 0 0 16660 13337 0 0 2805 2212 0 0 91693 11265 0 0 89420 12407 0 0 2805 0 0 1205 1463 1590 10539 0 0 3.22491 3.22491 -119.221 -3.22491 0 0 787024. 2723.27 0.26 0.05 0.09 -1 -1 0.26 0.0123356 0.0108692 135 55 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_017.v common 7.77 vpr 63.93 MiB -1 -1 0.10 20904 1 0.01 -1 -1 33124 -1 -1 21 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65468 32 32 338 269 1 204 85 17 17 289 -1 unnamed_device 25.4 MiB 3.99 1050 63.9 MiB 0.05 0.00 3.24063 -108.847 -3.24063 3.24063 0.75 0.000194788 0.00016374 0.00947769 0.00798008 34 2630 21 6.87369e+06 293451 618332. 2139.56 1.25 0.0582768 0.049691 25762 151098 -1 2151 22 1718 2539 191980 43292 0 0 191980 43292 2539 2075 0 0 9419 8066 0 0 14314 11265 0 0 2539 2192 0 0 81062 9622 0 0 82107 10072 0 0 2539 0 0 821 812 877 6691 0 0 3.03621 3.03621 -120.891 -3.03621 0 0 787024. 2723.27 0.25 0.04 0.09 -1 -1 0.25 0.0108982 0.009649 140 31 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_018.v common 7.42 vpr 63.93 MiB -1 -1 0.11 20936 1 0.01 -1 -1 33180 -1 -1 28 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65468 32 32 323 276 1 156 92 17 17 289 -1 unnamed_device 25.3 MiB 2.33 895 63.9 MiB 0.12 0.00 2.46506 -93.2432 -2.46506 2.46506 0.76 0.000151158 0.000123491 0.0131247 0.0109246 34 2070 21 6.87369e+06 391268 618332. 2139.56 2.42 0.0731118 0.0618992 25762 151098 -1 1772 20 1061 1548 113303 27055 0 0 113303 27055 1548 1128 0 0 6106 5305 0 0 9437 7588 0 0 1548 1258 0 0 46029 6234 0 0 48635 5542 0 0 1548 0 0 487 698 640 5027 0 0 2.31317 2.31317 -105.825 -2.31317 0 0 787024. 2723.27 0.27 0.03 0.10 -1 -1 0.27 0.00975686 0.00834301 109 62 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_019.v common 5.69 vpr 63.33 MiB -1 -1 0.10 20536 1 0.00 -1 -1 33248 -1 -1 14 30 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64852 30 32 222 206 1 117 76 17 17 289 -1 unnamed_device 24.7 MiB 0.65 678 63.3 MiB 0.05 0.00 2.10903 -75.4981 -2.10903 2.10903 0.73 0.000108738 8.8448e-05 0.0088305 0.00727034 32 1581 19 6.87369e+06 195634 586450. 2029.24 2.21 0.0772302 0.0690032 25474 144626 -1 1358 16 660 918 75493 17520 0 0 75493 17520 918 833 0 0 3617 3165 0 0 5653 4512 0 0 918 856 0 0 31737 4346 0 0 32650 3808 0 0 918 0 0 258 210 291 2281 0 0 2.19412 2.19412 -92.1058 -2.19412 0 0 744469. 2576.02 0.24 0.04 0.09 -1 -1 0.24 0.00605423 0.00536348 71 29 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_020.v common 6.90 vpr 63.74 MiB -1 -1 0.12 20360 1 0.01 -1 -1 33468 -1 -1 19 31 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65268 31 32 291 243 1 178 82 17 17 289 -1 unnamed_device 25.2 MiB 3.02 998 63.7 MiB 0.05 0.00 3.93483 -123.477 -3.93483 3.93483 0.73 0.000135666 0.00011154 0.00904524 0.00753046 34 2148 24 6.87369e+06 265503 618332. 2139.56 1.09 0.0498367 0.0424304 25762 151098 -1 1871 24 1177 1775 132459 30131 0 0 132459 30131 1775 1570 0 0 6502 5627 0 0 9835 7723 0 0 1775 1621 0 0 57168 6321 0 0 55404 7269 0 0 1775 0 0 598 625 656 4972 0 0 3.55586 3.55586 -133.974 -3.55586 0 0 787024. 2723.27 0.26 0.04 0.09 -1 -1 0.26 0.0106303 0.00941058 116 30 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_021.v common 5.98 vpr 64.05 MiB -1 -1 0.11 20936 1 0.01 -1 -1 33424 -1 -1 35 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65588 32 32 342 271 1 181 99 17 17 289 -1 unnamed_device 25.5 MiB 0.81 1192 64.1 MiB 0.09 0.00 3.33899 -111.682 -3.33899 3.33899 0.76 0.000169298 0.000140851 0.0149334 0.0124442 32 2596 22 6.87369e+06 489084 586450. 2029.24 2.40 0.0867463 0.0736349 25474 144626 -1 2153 19 1462 2184 160277 37110 0 0 160277 37110 2184 1655 0 0 8581 7284 0 0 13453 10728 0 0 2184 1803 0 0 66748 8069 0 0 67127 7571 0 0 2184 0 0 722 823 896 6949 0 0 3.7734 3.7734 -137.428 -3.7734 0 0 744469. 2576.02 0.30 0.04 0.09 -1 -1 0.30 0.00969385 0.00857744 137 31 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_022.v common 8.38 vpr 64.08 MiB -1 -1 0.12 20816 1 0.01 -1 -1 33352 -1 -1 22 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65620 32 32 372 300 1 206 86 17 17 289 -1 unnamed_device 25.5 MiB 2.17 1104 64.1 MiB 0.05 0.00 3.42215 -106.583 -3.42215 3.42215 0.76 0.000173188 0.000142529 0.0088749 0.00743618 38 2390 20 6.87369e+06 307425 678818. 2348.85 3.37 0.112027 0.0895182 26626 170182 -1 2147 20 1388 2314 165710 36591 0 0 165710 36591 2314 1587 0 0 8287 7351 0 0 11588 9508 0 0 2314 1911 0 0 70341 8295 0 0 70866 7939 0 0 2314 0 0 926 1120 1067 7883 0 0 3.84876 3.84876 -126.255 -3.84876 0 0 902133. 3121.57 0.31 0.04 0.11 -1 -1 0.31 0.011599 0.0103002 142 59 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_023.v common 6.66 vpr 63.36 MiB -1 -1 0.09 20716 1 0.01 -1 -1 33364 -1 -1 17 26 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64876 26 32 190 182 1 108 75 17 17 289 -1 unnamed_device 24.9 MiB 1.66 344 63.4 MiB 0.03 0.00 2.06503 -56.4036 -2.06503 2.06503 0.79 9.3474e-05 7.5902e-05 0.00693024 0.00577894 34 1278 29 6.87369e+06 237555 618332. 2139.56 2.37 0.0491035 0.0411128 25762 151098 -1 799 17 583 771 49854 14782 0 0 49854 14782 771 640 0 0 3090 2741 0 0 4661 3895 0 0 771 662 0 0 21340 3204 0 0 19221 3640 0 0 771 0 0 188 240 168 1851 0 0 2.37877 2.37877 -75.7147 -2.37877 0 0 787024. 2723.27 0.26 0.02 0.09 -1 -1 0.26 0.00527655 0.00466849 67 21 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_024.v common 5.22 vpr 63.93 MiB -1 -1 0.11 20672 1 0.01 -1 -1 33352 -1 -1 23 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65468 32 32 285 227 1 169 87 17 17 289 -1 unnamed_device 25.4 MiB 1.18 998 63.9 MiB 0.03 0.00 3.71512 -108.094 -3.71512 3.71512 0.78 0.000141971 0.000116823 0.0050822 0.00430156 34 2324 21 6.87369e+06 321398 618332. 2139.56 1.22 0.0500573 0.0430338 25762 151098 -1 2076 21 1369 2500 190743 42423 0 0 190743 42423 2500 2075 0 0 9513 8324 0 0 14309 11154 0 0 2500 2219 0 0 83833 8810 0 0 78088 9841 0 0 2500 0 0 1131 1433 1654 9984 0 0 3.7041 3.7041 -126.435 -3.7041 0 0 787024. 2723.27 0.27 0.04 0.10 -1 -1 0.27 0.00980103 0.00870136 119 -1 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_025.v common 4.65 vpr 63.24 MiB -1 -1 0.09 20188 1 0.01 -1 -1 32972 -1 -1 12 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64760 32 32 173 169 1 114 76 17 17 289 -1 unnamed_device 24.9 MiB 0.39 533 63.2 MiB 0.04 0.00 2.08703 -66.0984 -2.08703 2.08703 0.78 9.6377e-05 7.811e-05 0.00719773 0.00589046 28 1388 27 6.87369e+06 167686 531479. 1839.03 1.72 0.0421919 0.0356924 24610 126494 -1 1231 20 676 820 66783 16500 0 0 66783 16500 820 733 0 0 3211 2646 0 0 4567 3768 0 0 820 754 0 0 28984 4298 0 0 28381 4301 0 0 820 0 0 144 86 152 1490 0 0 2.40077 2.40077 -85.6913 -2.40077 0 0 648988. 2245.63 0.24 0.04 0.09 -1 -1 0.24 0.0120104 0.00510895 65 -1 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_026.v common 6.35 vpr 63.81 MiB -1 -1 0.10 20504 1 0.01 -1 -1 33180 -1 -1 30 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65340 32 32 300 245 1 169 94 17 17 289 -1 unnamed_device 25.3 MiB 0.94 827 63.8 MiB 0.06 0.00 3.63082 -102.435 -3.63082 3.63082 0.75 0.000156623 0.000127366 0.00908177 0.00747376 26 2525 42 6.87369e+06 419215 503264. 1741.40 2.92 0.0811503 0.0598619 24322 120374 -1 2041 30 1628 2619 202583 48889 0 0 202583 48889 2619 2110 0 0 9815 8345 0 0 15190 11850 0 0 2619 2247 0 0 84082 12133 0 0 88258 12204 0 0 2619 0 0 991 1539 1328 9471 0 0 3.8784 3.8784 -128.473 -3.8784 0 0 618332. 2139.56 0.21 0.05 0.08 -1 -1 0.21 0.0123283 0.0107783 120 21 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_027.v common 5.87 vpr 63.93 MiB -1 -1 0.10 20480 1 0.01 -1 -1 33144 -1 -1 31 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65464 32 32 297 233 1 177 95 17 17 289 -1 unnamed_device 25.3 MiB 1.05 1035 63.9 MiB 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0.01 -1 -1 33360 -1 -1 17 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65080 32 32 253 210 1 156 81 17 17 289 -1 unnamed_device 25.0 MiB 0.85 819 63.6 MiB 0.05 0.00 3.20393 -100.286 -3.20393 3.20393 0.75 0.000129804 0.00010703 0.00782502 0.00650003 32 2255 23 6.87369e+06 237555 586450. 2029.24 2.39 0.0579217 0.0492681 25474 144626 -1 1808 21 1269 2106 164988 37624 0 0 164988 37624 2106 1635 0 0 7900 6998 0 0 12981 9923 0 0 2106 1778 0 0 69358 8733 0 0 70537 8557 0 0 2106 0 0 837 980 1063 7140 0 0 2.88426 2.88426 -114.521 -2.88426 0 0 744469. 2576.02 0.26 0.04 0.09 -1 -1 0.26 0.00870951 0.00772283 101 -1 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_033.v common 5.67 vpr 63.44 MiB -1 -1 0.11 20468 1 0.01 -1 -1 33216 -1 -1 26 31 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64960 31 32 271 231 1 149 89 17 17 289 -1 unnamed_device 25.1 MiB 0.81 778 63.4 MiB 0.05 0.00 2.8296 -88.0864 -2.8296 2.8296 0.78 0.000136394 0.000111595 0.00877013 0.00750736 30 1983 23 6.87369e+06 363320 556674. 1926.21 2.08 0.0586083 0.0499323 25186 138497 -1 1560 22 829 1544 100736 23830 0 0 100736 23830 1544 1051 0 0 5428 4701 0 0 7630 6157 0 0 1544 1163 0 0 41556 5454 0 0 43034 5304 0 0 1544 0 0 715 784 919 6412 0 0 2.83496 2.83496 -104.177 -2.83496 0 0 706193. 2443.58 0.23 0.03 0.13 -1 -1 0.23 0.00872603 0.00767359 102 26 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_034.v common 6.97 vpr 63.82 MiB -1 -1 0.12 20840 1 0.01 -1 -1 33356 -1 -1 25 29 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65356 29 32 291 250 1 154 86 17 17 289 -1 unnamed_device 25.4 MiB 2.91 860 63.8 MiB 0.07 0.00 2.42106 -82.6823 -2.42106 2.42106 0.78 0.000130931 0.000106514 0.0113553 0.00942894 34 1912 20 6.87369e+06 349346 618332. 2139.56 1.29 0.0785886 0.0708414 25762 151098 -1 1687 20 1148 1708 118687 28776 0 0 118687 28776 1708 1305 0 0 6628 5896 0 0 9918 7998 0 0 1708 1412 0 0 50554 6096 0 0 48171 6069 0 0 1708 0 0 560 633 766 5305 0 0 2.57007 2.57007 -100.677 -2.57007 0 0 787024. 2723.27 0.29 0.03 0.09 -1 -1 0.29 0.00875451 0.00774052 106 48 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_035.v common 7.04 vpr 64.15 MiB -1 -1 0.12 21028 1 0.01 -1 -1 33296 -1 -1 40 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65692 32 32 367 282 1 201 104 17 17 289 -1 unnamed_device 25.7 MiB 3.48 1171 64.2 MiB 0.09 0.00 3.28579 -102.179 -3.28579 3.28579 0.76 0.000201176 0.000168617 0.0136562 0.0113985 28 2728 23 6.87369e+06 558954 531479. 1839.03 1.03 0.0494817 0.042541 24610 126494 -1 2434 21 1622 3164 256367 55212 0 0 256367 55212 3164 1906 0 0 11825 10071 0 0 18405 14362 0 0 3164 2122 0 0 113512 12716 0 0 106297 14035 0 0 3164 0 0 1542 2986 3275 18655 0 0 3.8527 3.8527 -125.257 -3.8527 0 0 648988. 2245.63 0.22 0.06 0.08 -1 -1 0.22 0.0126603 0.0112795 156 26 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_036.v common 8.45 vpr 64.10 MiB -1 -1 0.13 20760 1 0.01 -1 -1 33188 -1 -1 38 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65636 32 32 391 311 1 194 102 17 17 289 -1 unnamed_device 25.7 MiB 3.37 1097 64.1 MiB 0.09 0.00 3.09148 -109.588 -3.09148 3.09148 0.76 0.000183328 0.000151218 0.0144359 0.011952 34 2315 21 6.87369e+06 531006 618332. 2139.56 2.45 0.0941462 0.0800563 25762 151098 -1 2022 22 1734 2924 178611 41610 0 0 178611 41610 2924 1885 0 0 10753 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vpr 64.16 MiB -1 -1 0.12 20676 1 0.02 -1 -1 33464 -1 -1 25 31 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65700 31 32 377 302 1 237 88 17 17 289 -1 unnamed_device 25.8 MiB 3.75 1235 64.2 MiB 0.10 0.00 4.36902 -137.043 -4.36902 4.36902 0.79 0.000181548 0.000150823 0.0177525 0.014935 34 3425 37 6.87369e+06 349346 618332. 2139.56 1.91 0.0827939 0.0712809 25762 151098 -1 2740 21 2217 3306 285405 64333 0 0 285405 64333 3306 2856 0 0 12968 11443 0 0 20224 16028 0 0 3306 2998 0 0 122227 15827 0 0 123374 15181 0 0 3306 0 0 1089 1073 1212 8858 0 0 4.9525 4.9525 -167.429 -4.9525 0 0 787024. 2723.27 0.26 0.07 0.09 -1 -1 0.26 0.0130411 0.0116089 159 60 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_040.v common 9.43 vpr 64.46 MiB -1 -1 0.12 20740 1 0.01 -1 -1 33424 -1 -1 27 31 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 66008 31 32 383 305 1 212 90 17 17 289 -1 unnamed_device 26.0 MiB 3.24 1074 64.5 MiB 0.12 0.00 4.33584 -133.913 -4.33584 4.33584 0.77 0.000185337 0.000153576 0.0171178 0.0143302 30 2743 27 6.87369e+06 377294 556674. 1926.21 3.29 0.0907514 0.0775356 25186 138497 -1 2088 23 1550 2443 158862 36330 0 0 158862 36330 2443 1861 0 0 8564 7172 0 0 11459 9413 0 0 2443 1914 0 0 67931 7995 0 0 66022 7975 0 0 2443 0 0 893 971 876 7189 0 0 4.5118 4.5118 -156.016 -4.5118 0 0 706193. 2443.58 0.23 0.04 0.09 -1 -1 0.23 0.0126252 0.0110777 152 60 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_041.v common 7.80 vpr 63.95 MiB -1 -1 0.11 20940 1 0.02 -1 -1 33264 -1 -1 25 31 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65484 31 32 352 285 1 186 88 17 17 289 -1 unnamed_device 25.5 MiB 2.77 972 63.9 MiB 0.06 0.00 3.22963 -104.153 -3.22963 3.22963 0.72 0.000162194 0.000132847 0.00996443 0.00829293 32 3145 37 6.87369e+06 349346 586450. 2029.24 2.44 0.0903232 0.0765667 25474 144626 -1 2348 26 1768 2993 242060 56934 0 0 242060 56934 2993 2527 0 0 11870 10548 0 0 20639 15810 0 0 2993 2718 0 0 101918 12678 0 0 101647 12653 0 0 2993 0 0 1225 1705 1637 10994 0 0 3.43321 3.43321 -124.88 -3.43321 0 0 744469. 2576.02 0.24 0.05 0.09 -1 -1 0.24 0.0129113 0.0113407 131 51 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_042.v common 6.48 vpr 63.79 MiB -1 -1 0.11 20760 1 0.01 -1 -1 33216 -1 -1 20 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65324 32 32 291 242 1 183 84 17 17 289 -1 unnamed_device 25.2 MiB 2.69 1056 63.8 MiB 0.09 0.00 3.52545 -100.891 -3.52545 3.52545 0.72 0.00013764 0.000112639 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fixed_k6_frac_ripple_N8_22nm.xml mult_046.v common 7.63 vpr 63.88 MiB -1 -1 0.12 20864 1 0.01 -1 -1 33132 -1 -1 32 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65416 32 32 349 284 1 183 96 17 17 289 -1 unnamed_device 25.5 MiB 2.28 960 63.9 MiB 0.09 0.00 2.9146 -93.1402 -2.9146 2.9146 0.70 0.000173615 0.000144842 0.0148675 0.0124848 30 2406 21 6.87369e+06 447163 556674. 1926.21 2.63 0.104231 0.0807839 25186 138497 -1 1876 22 1169 2097 122901 28930 0 0 122901 28930 2097 1418 0 0 7246 5941 0 0 9877 8008 0 0 2097 1555 0 0 51163 5991 0 0 50421 6017 0 0 2097 0 0 928 1095 1170 8182 0 0 2.88001 2.88001 -106.901 -2.88001 0 0 706193. 2443.58 0.35 0.04 0.15 -1 -1 0.35 0.0109356 0.00963039 132 50 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_047.v common 5.68 vpr 63.76 MiB -1 -1 0.11 20472 1 0.01 -1 -1 33116 -1 -1 26 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65288 32 32 291 230 1 175 90 17 17 289 -1 unnamed_device 25.2 MiB 0.63 1057 63.8 MiB 0.08 0.00 3.35979 -108.146 -3.35979 3.35979 0.72 0.000156613 0.000130584 0.0117455 0.00973304 28 2542 22 6.87369e+06 363320 531479. 1839.03 2.55 0.073559 0.0626654 24610 126494 -1 2265 23 1558 2994 235200 52837 0 0 235200 52837 2994 2310 0 0 11214 9836 0 0 17319 13828 0 0 2994 2480 0 0 104004 11743 0 0 96675 12640 0 0 2994 0 0 1436 1798 2183 12841 0 0 3.7964 3.7964 -130.566 -3.7964 0 0 648988. 2245.63 0.23 0.05 0.08 -1 -1 0.23 0.0101652 0.00894593 123 -1 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_048.v common 8.16 vpr 64.29 MiB -1 -1 0.11 21088 1 0.01 -1 -1 33244 -1 -1 22 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65832 32 32 353 287 1 203 86 17 17 289 -1 unnamed_device 25.8 MiB 2.87 1082 64.3 MiB 0.06 0.00 3.93315 -121.002 -3.93315 3.93315 0.76 0.000158643 0.00012982 0.00980572 0.00819849 30 2602 31 6.87369e+06 307425 556674. 1926.21 2.68 0.0758548 0.0643299 25186 138497 -1 2064 18 1114 1573 93849 23606 0 0 93849 23606 1573 1343 0 0 5563 4525 0 0 7176 6011 0 0 1573 1366 0 0 38664 5313 0 0 39300 5048 0 0 1573 0 0 459 551 532 4251 0 0 3.4645 3.4645 -128.185 -3.4645 0 0 706193. 2443.58 0.32 0.03 0.10 -1 -1 0.32 0.0103407 0.0092443 136 52 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_049.v common 8.84 vpr 63.99 MiB -1 -1 0.12 20880 1 0.01 -1 -1 33300 -1 -1 32 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65528 32 32 361 291 1 189 96 17 17 289 -1 unnamed_device 25.5 MiB 3.00 1027 64.0 MiB 0.09 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0.120179 0.102488 26050 158493 -1 2100 19 1603 2597 188272 44530 0 0 188272 44530 2597 1925 0 0 9507 7966 0 0 14119 11070 0 0 2597 2214 0 0 80195 10312 0 0 79257 11043 0 0 2597 0 0 994 1451 1189 9041 0 0 3.12961 3.12961 -118.612 -3.12961 0 0 828058. 2865.25 0.27 0.05 0.10 -1 -1 0.27 0.0116333 0.0103368 144 59 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_051.v common 6.21 vpr 64.18 MiB -1 -1 0.11 20608 1 0.01 -1 -1 33292 -1 -1 33 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65716 32 32 306 248 1 170 97 17 17 289 -1 unnamed_device 25.5 MiB 0.86 900 64.2 MiB 0.06 0.00 3.39279 -101.124 -3.39279 3.39279 0.76 0.00015206 0.000124127 0.00874229 0.00725634 26 2577 29 6.87369e+06 461137 503264. 1741.40 2.54 0.0638886 0.054402 24322 120374 -1 2201 23 1497 2638 236440 53047 0 0 236440 53047 2638 1999 0 0 10138 8516 0 0 15494 12170 0 0 2638 2145 0 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0.26 0.0105788 0.00932124 135 26 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_053.v common 6.48 vpr 64.14 MiB -1 -1 0.12 20768 1 0.02 -1 -1 33216 -1 -1 22 31 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65680 31 32 373 299 1 204 85 17 17 289 -1 unnamed_device 25.5 MiB 2.13 1153 64.1 MiB 0.09 0.00 3.72318 -119.527 -3.72318 3.72318 0.77 0.000179428 0.000149742 0.0164017 0.0136688 34 3014 23 6.87369e+06 307425 618332. 2139.56 1.63 0.0683788 0.0583047 25762 151098 -1 2516 21 1596 2554 225666 49521 0 0 225666 49521 2554 2220 0 0 10120 9070 0 0 15776 12773 0 0 2554 2326 0 0 99103 11185 0 0 95559 11947 0 0 2554 0 0 958 1219 1168 8451 0 0 3.98276 3.98276 -142.852 -3.98276 0 0 787024. 2723.27 0.27 0.08 0.09 -1 -1 0.27 0.0118801 0.0105191 141 58 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_054.v common 6.79 vpr 64.20 MiB -1 -1 0.11 20840 1 0.01 -1 -1 33224 -1 -1 21 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65740 32 32 387 315 1 194 85 17 17 289 -1 unnamed_device 25.6 MiB 2.74 1055 64.2 MiB 0.07 0.00 3.65075 -115.066 -3.65075 3.65075 0.73 0.000169931 0.000139757 0.0123549 0.0103083 34 3064 47 6.87369e+06 293451 618332. 2139.56 1.32 0.0775545 0.0663936 25762 151098 -1 2510 18 1545 2731 208018 49176 0 0 208018 49176 2731 2286 0 0 10739 9550 0 0 16199 13153 0 0 2731 2363 0 0 87710 11054 0 0 87908 10770 0 0 2731 0 0 1186 1223 1188 9102 0 0 3.67446 3.67446 -133.244 -3.67446 0 0 787024. 2723.27 0.26 0.05 0.09 -1 -1 0.26 0.0115081 0.0102516 135 74 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_055.v common 5.54 vpr 63.63 MiB -1 -1 0.09 20676 1 0.01 -1 -1 33168 -1 -1 22 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65156 32 32 251 219 1 141 86 17 17 289 -1 unnamed_device 25.1 MiB 0.66 730 63.6 MiB 0.04 0.00 2.7886 -85.3614 -2.7886 2.7886 0.90 0.000132636 0.000108713 0.00682241 0.00564718 30 1765 40 6.87369e+06 307425 556674. 1926.21 1.95 0.0541741 0.0460298 25186 138497 -1 1537 19 785 1335 83892 20437 0 0 83892 20437 1335 936 0 0 4746 3971 0 0 6277 5184 0 0 1335 1058 0 0 33567 4796 0 0 36632 4492 0 0 1335 0 0 550 545 666 4876 0 0 2.67666 2.67666 -99.0084 -2.67666 0 0 706193. 2443.58 0.24 0.03 0.13 -1 -1 0.24 0.00789098 0.00699231 93 20 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_056.v common 5.83 vpr 63.87 MiB -1 -1 0.11 21036 1 0.01 -1 -1 33344 -1 -1 18 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65400 32 32 341 285 1 188 82 17 17 289 -1 unnamed_device 25.4 MiB 1.76 981 63.9 MiB 0.08 0.00 3.03076 -110.051 -3.03076 3.03076 0.84 0.000158234 0.000130385 0.0151715 0.0126251 34 2651 24 6.87369e+06 251529 618332. 2139.56 1.24 0.0629365 0.0536163 25762 151098 -1 2199 22 1716 2488 223086 50062 0 0 223086 50062 2488 2228 0 0 9908 8898 0 0 15678 12481 0 0 2488 2269 0 0 97254 12277 0 0 95270 11909 0 0 2488 0 0 772 834 730 6368 0 0 3.58351 3.58351 -137.547 -3.58351 0 0 787024. 2723.27 0.25 0.05 0.09 -1 -1 0.25 0.0114058 0.0101223 124 62 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_057.v common 8.16 vpr 64.51 MiB -1 -1 0.12 20756 1 0.01 -1 -1 33292 -1 -1 24 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 66060 32 32 387 293 1 236 88 17 17 289 -1 unnamed_device 26.0 MiB 2.93 1259 64.5 MiB 0.10 0.00 4.25892 -128.132 -4.25892 4.25892 0.82 0.000182638 0.000151298 0.0173257 0.0145584 34 3856 48 6.87369e+06 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Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65212 32 32 231 199 1 142 88 17 17 289 -1 unnamed_device 25.1 MiB 0.91 774 63.7 MiB 0.06 0.00 2.8436 -83.7272 -2.8436 2.8436 0.74 0.000127336 0.000105881 0.010269 0.00855908 26 2048 44 6.87369e+06 335372 503264. 1741.40 2.95 0.070716 0.0602649 24322 120374 -1 1678 20 1107 1845 140926 34293 0 0 140926 34293 1845 1357 0 0 7176 6276 0 0 10751 8545 0 0 1845 1438 0 0 61080 8197 0 0 58229 8480 0 0 1845 0 0 738 1088 999 7202 0 0 2.93831 2.93831 -104.342 -2.93831 0 0 618332. 2139.56 0.20 0.03 0.07 -1 -1 0.20 0.00756911 0.00668534 94 -1 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_063.v common 8.90 vpr 64.17 MiB -1 -1 0.11 20828 1 0.02 -1 -1 33276 -1 -1 37 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65712 32 32 349 273 1 191 101 17 17 289 -1 unnamed_device 25.6 MiB 2.01 1148 64.2 MiB 0.10 0.00 4.06437 -112.431 -4.06437 4.06437 0.75 0.000170177 0.000133578 0.0151701 0.0123678 26 3175 50 6.87369e+06 517032 503264. 1741.40 4.26 0.102783 0.0871178 24322 120374 -1 2614 20 1673 3029 243968 55546 0 0 243968 55546 3029 2063 0 0 11808 10012 0 0 18016 14337 0 0 3029 2254 0 0 102210 13913 0 0 105876 12967 0 0 3029 0 0 1356 3012 2539 16902 0 0 5.14705 5.14705 -150.622 -5.14705 0 0 618332. 2139.56 0.20 0.05 0.07 -1 -1 0.20 0.0101949 0.0089919 145 26 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_064.v common 5.79 vpr 63.64 MiB -1 -1 0.10 20456 1 0.01 -1 -1 33048 -1 -1 19 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65164 32 32 247 207 1 153 83 17 17 289 -1 unnamed_device 25.1 MiB 0.72 671 63.6 MiB 0.04 0.00 2.8626 -89.6716 -2.8626 2.8626 0.84 0.000125033 0.000102253 0.00656684 0.00546167 30 1876 25 6.87369e+06 265503 556674. 1926.21 2.14 0.0765815 0.0674899 25186 138497 -1 1529 18 792 1373 80662 20344 0 0 80662 20344 1373 949 0 0 4786 3983 0 0 6291 5134 0 0 1373 1036 0 0 33409 4360 0 0 33430 4882 0 0 1373 0 0 581 510 641 4749 0 0 2.82401 2.82401 -107.721 -2.82401 0 0 706193. 2443.58 0.46 0.05 0.09 -1 -1 0.46 0.0188051 0.0147674 98 -1 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_065.v common 6.77 vpr 63.66 MiB -1 -1 0.11 20540 1 0.01 -1 -1 33196 -1 -1 34 30 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65184 30 32 278 235 1 151 96 17 17 289 -1 unnamed_device 25.2 MiB 2.42 876 63.7 MiB 0.08 0.00 2.97898 -93.3988 -2.97898 2.97898 0.76 0.000133549 0.000108831 0.0116419 0.00963311 26 2094 20 6.87369e+06 475111 503264. 1741.40 1.28 0.0410048 0.0351948 24322 120374 -1 1869 19 1184 2125 169251 39181 0 0 169251 39181 2125 1411 0 0 8072 6864 0 0 12434 9810 0 0 2125 1603 0 0 70878 10073 0 0 73617 9420 0 0 2125 0 0 941 1260 1262 9226 0 0 3.14786 3.14786 -112.704 -3.14786 0 0 618332. 2139.56 0.46 0.04 0.18 -1 -1 0.46 0.0103809 0.00941823 109 29 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_066.v common 7.80 vpr 64.08 MiB -1 -1 0.13 21032 1 0.01 -1 -1 33172 -1 -1 24 29 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65620 29 32 355 287 1 200 85 17 17 289 -1 unnamed_device 25.5 MiB 3.69 939 64.1 MiB 0.06 0.00 3.21063 -97.8768 -3.21063 3.21063 0.79 0.000165265 0.000135834 0.0111158 0.00925948 34 2953 30 6.87369e+06 335372 618332. 2139.56 1.39 0.0677019 0.0574806 25762 151098 -1 2206 20 1730 2591 195497 47720 0 0 195497 47720 2591 2249 0 0 9968 8803 0 0 15085 11974 0 0 2591 2305 0 0 79228 11298 0 0 86034 11091 0 0 2591 0 0 861 752 839 6765 0 0 3.40321 3.40321 -120.276 -3.40321 0 0 787024. 2723.27 0.27 0.05 0.10 -1 -1 0.27 0.0111364 0.00987283 138 56 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_067.v common 6.26 vpr 63.90 MiB -1 -1 0.11 20836 1 0.01 -1 -1 33088 -1 -1 26 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65432 32 32 358 289 1 183 90 17 17 289 -1 unnamed_device 25.4 MiB 2.10 1098 63.9 MiB 0.08 0.00 3.48515 -116.696 -3.48515 3.48515 0.74 0.000174259 0.000143772 0.0147798 0.0125068 34 2470 21 6.87369e+06 363320 618332. 2139.56 1.15 0.0627857 0.0537659 25762 151098 -1 2074 22 1677 2598 181665 42033 0 0 181665 42033 2598 1970 0 0 9470 8096 0 0 15231 11670 0 0 2598 2147 0 0 77168 8826 0 0 74600 9324 0 0 2598 0 0 921 1045 1181 8305 0 0 3.7404 3.7404 -136.431 -3.7404 0 0 787024. 2723.27 0.33 0.04 0.16 -1 -1 0.33 0.0116975 0.0103713 132 51 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_068.v common 7.41 vpr 63.96 MiB -1 -1 0.11 20852 1 0.00 -1 -1 33228 -1 -1 27 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65496 32 32 353 285 1 188 91 17 17 289 -1 unnamed_device 25.5 MiB 2.21 1149 64.0 MiB 0.07 0.00 3.69318 -116.202 -3.69318 3.69318 0.74 0.000205134 0.000172 0.0126305 0.0105969 32 2896 25 6.87369e+06 377294 586450. 2029.24 2.56 0.0881969 0.0753237 25474 144626 -1 2412 24 1629 2745 226915 53087 0 0 226915 53087 2745 2292 0 0 11076 9914 0 0 18843 14725 0 0 2745 2409 0 0 97229 12078 0 0 94277 11669 0 0 2745 0 0 1116 1481 1489 9983 0 0 4.04706 4.04706 -141.92 -4.04706 0 0 744469. 2576.02 0.25 0.06 0.09 -1 -1 0.25 0.0148708 0.0132672 133 48 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_069.v common 8.31 vpr 63.75 MiB -1 -1 0.11 20504 1 0.01 -1 -1 33232 -1 -1 15 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65276 32 32 276 237 1 165 79 17 17 289 -1 unnamed_device 25.4 MiB 3.14 1003 63.7 MiB 0.06 0.00 3.74452 -113.984 -3.74452 3.74452 0.77 0.000128647 0.00010451 0.0111655 0.00926146 34 2254 23 6.87369e+06 209608 618332. 2139.56 2.43 0.0731256 0.0627667 25762 151098 -1 2018 19 1077 1491 122057 27370 0 0 122057 27370 1491 1294 0 0 5733 4856 0 0 8489 6819 0 0 1491 1342 0 0 52973 6431 0 0 51880 6628 0 0 1491 0 0 414 363 501 3613 0 0 3.28061 3.28061 -122.258 -3.28061 0 0 787024. 2723.27 0.44 0.03 0.09 -1 -1 0.44 0.00837446 0.00746543 103 31 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_070.v common 6.37 vpr 63.86 MiB -1 -1 0.11 21056 1 0.01 -1 -1 33220 -1 -1 17 31 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65388 31 32 319 272 1 176 80 17 17 289 -1 unnamed_device 25.3 MiB 2.66 998 63.9 MiB 0.06 0.00 2.99776 -103.303 -2.99776 2.99776 0.69 0.000143856 0.000116851 0.0132016 0.0110615 34 2474 24 6.87369e+06 237555 618332. 2139.56 1.17 0.0583353 0.0494434 25762 151098 -1 2056 23 1378 2022 159777 38010 0 0 159777 38010 2022 1786 0 0 8146 7284 0 0 12415 10096 0 0 2022 1822 0 0 66885 8635 0 0 68287 8387 0 0 2022 0 0 644 699 680 5333 0 0 3.27491 3.27491 -125.712 -3.27491 0 0 787024. 2723.27 0.26 0.04 0.10 -1 -1 0.26 0.010631 0.00938333 114 60 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_071.v common 7.77 vpr 64.01 MiB -1 -1 0.11 20944 1 0.01 -1 -1 33160 -1 -1 34 30 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65544 30 32 329 273 1 167 96 17 17 289 -1 unnamed_device 25.6 MiB 2.39 1003 64.0 MiB 0.09 0.00 2.84355 -85.591 -2.84355 2.84355 0.76 0.000155769 0.000128626 0.0147225 0.0122916 32 2480 24 6.87369e+06 475111 586450. 2029.24 2.69 0.0937591 0.0815358 25474 144626 -1 1965 21 1194 2240 156835 36163 0 0 156835 36163 2240 1455 0 0 8521 7303 0 0 13917 10746 0 0 2240 1612 0 0 64145 7789 0 0 65772 7258 0 0 2240 0 0 1046 1766 1825 11477 0 0 2.62666 2.62666 -98.7145 -2.62666 0 0 744469. 2576.02 0.24 0.04 0.09 -1 -1 0.24 0.0100558 0.00888469 124 52 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_072.v common 7.68 vpr 63.89 MiB -1 -1 0.12 20808 1 0.01 -1 -1 33256 -1 -1 35 28 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65420 28 32 277 229 1 156 95 17 17 289 -1 unnamed_device 25.3 MiB 2.37 904 63.9 MiB 0.05 0.00 3.27479 -88.419 -3.27479 3.27479 0.75 0.00013105 0.000107486 0.00772435 0.00643938 26 2179 22 6.87369e+06 489084 503264. 1741.40 2.56 0.0634243 0.054069 24322 120374 -1 2118 21 1387 2508 232381 51603 0 0 232381 51603 2508 1740 0 0 9489 8015 0 0 15517 11874 0 0 2508 1843 0 0 100042 14466 0 0 102317 13665 0 0 2508 0 0 1121 1637 1745 11897 0 0 4.1023 4.1023 -121.458 -4.1023 0 0 618332. 2139.56 0.22 0.05 0.07 -1 -1 0.22 0.00917126 0.0080652 117 20 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_073.v common 8.96 vpr 63.78 MiB -1 -1 0.12 21124 1 0.01 -1 -1 33172 -1 -1 17 30 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65308 30 32 317 269 1 155 79 17 17 289 -1 unnamed_device 25.3 MiB 2.66 728 63.8 MiB 0.06 0.00 3.16363 -95.7832 -3.16363 3.16363 0.81 0.000143351 0.000117326 0.0117449 0.00989437 36 2153 23 6.87369e+06 237555 648988. 2245.63 3.27 0.0801192 0.0667221 26050 158493 -1 1620 22 1315 2212 167299 41665 0 0 167299 41665 2212 1661 0 0 8165 7158 0 0 11750 9431 0 0 2212 1837 0 0 71729 10870 0 0 71231 10708 0 0 2212 0 0 897 951 1085 7405 0 0 3.14956 3.14956 -115.837 -3.14956 0 0 828058. 2865.25 0.51 0.04 0.11 -1 -1 0.51 0.00982229 0.00861061 105 58 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_074.v common 7.62 vpr 64.02 MiB -1 -1 0.11 20736 1 0.01 -1 -1 33004 -1 -1 17 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65552 32 32 335 282 1 189 81 17 17 289 -1 unnamed_device 25.7 MiB 3.50 1013 64.0 MiB 0.07 0.00 2.9238 -103.215 -2.9238 2.9238 0.74 0.000159568 0.000132811 0.0138571 0.0115836 34 2613 24 6.87369e+06 237555 618332. 2139.56 1.23 0.0610558 0.0518958 25762 151098 -1 2236 21 1481 2234 195407 43963 0 0 195407 43963 2234 1857 0 0 8702 7742 0 0 13928 10948 0 0 2234 1899 0 0 83021 11380 0 0 85288 10137 0 0 2234 0 0 753 819 688 6000 0 0 3.41151 3.41151 -130.93 -3.41151 0 0 787024. 2723.27 0.28 0.05 0.10 -1 -1 0.28 0.0117679 0.0105045 122 62 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_075.v common 6.42 vpr 63.98 MiB -1 -1 0.12 20296 1 0.01 -1 -1 33176 -1 -1 31 31 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65516 31 32 293 230 1 175 94 17 17 289 -1 unnamed_device 25.4 MiB 0.81 946 64.0 MiB 0.06 0.00 3.58982 -105.213 -3.58982 3.58982 0.80 0.000154457 0.000128596 0.00860199 0.00720917 34 2297 22 6.87369e+06 433189 618332. 2139.56 2.60 0.0843601 0.0722824 25762 151098 -1 1987 21 1299 2250 148293 35460 0 0 148293 35460 2250 1619 0 0 8555 7305 0 0 12818 10032 0 0 2250 1854 0 0 61683 7154 0 0 60737 7496 0 0 2250 0 0 951 932 1223 8170 0 0 3.4925 3.4925 -120.213 -3.4925 0 0 787024. 2723.27 0.30 0.09 0.11 -1 -1 0.30 0.0233348 0.0122368 129 -1 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_076.v common 10.44 vpr 64.02 MiB -1 -1 0.14 20856 1 0.01 -1 -1 33416 -1 -1 23 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65556 32 32 350 275 1 214 87 17 17 289 -1 unnamed_device 25.4 MiB 3.91 1027 64.0 MiB 0.09 0.00 3.78918 -118.751 -3.78918 3.78918 0.97 0.000211725 0.000177864 0.0152327 0.012843 34 3226 26 6.87369e+06 321398 618332. 2139.56 2.53 0.108486 0.097222 25762 151098 -1 2480 22 2004 2993 236508 56899 0 0 236508 56899 2993 2700 0 0 11788 10555 0 0 18216 14697 0 0 2993 2759 0 0 97713 13603 0 0 102805 12585 0 0 2993 0 0 989 1140 1064 8164 0 0 4.23836 4.23836 -146.051 -4.23836 0 0 787024. 2723.27 0.47 0.07 0.22 -1 -1 0.47 0.0155417 0.0139848 147 31 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_077.v common 11.69 vpr 64.20 MiB -1 -1 0.14 21012 1 0.00 -1 -1 33180 -1 -1 36 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65744 32 32 385 308 1 196 100 17 17 289 -1 unnamed_device 25.9 MiB 5.11 985 64.2 MiB 0.08 0.00 4.24987 -125.238 -4.24987 4.24987 1.03 0.000202584 0.000167378 0.0140628 0.0117579 34 2970 24 6.87369e+06 503058 618332. 2139.56 2.34 0.084812 0.0735416 25762 151098 -1 2313 23 1710 2942 233766 56426 0 0 233766 56426 2942 2251 0 0 11664 10362 0 0 18183 14664 0 0 2942 2399 0 0 95294 13151 0 0 102741 13599 0 0 2942 0 0 1232 1612 1640 11564 0 0 4.43945 4.43945 -145.951 -4.43945 0 0 787024. 2723.27 0.32 0.08 0.19 -1 -1 0.32 0.0135474 0.0119969 147 62 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_078.v common 11.75 vpr 64.11 MiB -1 -1 0.14 20724 1 0.02 -1 -1 33232 -1 -1 41 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65652 32 32 387 309 1 192 105 17 17 289 -1 unnamed_device 25.7 MiB 3.68 1135 64.1 MiB 0.11 0.00 3.61982 -117.192 -3.61982 3.61982 0.91 0.000175106 0.000142521 0.0191734 0.0158315 34 2785 23 6.87369e+06 572927 618332. 2139.56 4.52 0.134479 0.105027 25762 151098 -1 2215 24 1788 3285 288286 63977 0 0 288286 63977 3285 2161 0 0 12926 11620 0 0 20958 16600 0 0 3285 2479 0 0 129969 14760 0 0 117863 16357 0 0 3285 0 0 1497 1771 1724 13177 0 0 3.6078 3.6078 -131.543 -3.6078 0 0 787024. 2723.27 0.30 0.07 0.10 -1 -1 0.30 0.0142139 0.0123986 148 62 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_079.v common 8.09 vpr 63.63 MiB -1 -1 0.12 20600 1 0.01 -1 -1 33148 -1 -1 17 30 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65160 30 32 272 232 1 151 79 17 17 289 -1 unnamed_device 25.1 MiB 2.90 875 63.6 MiB 0.07 0.00 3.28893 -103.003 -3.28893 3.28893 0.83 0.000129002 0.000105006 0.0128793 0.0106428 28 2155 28 6.87369e+06 237555 531479. 1839.03 2.06 0.0717029 0.0607485 24610 126494 -1 1968 20 1181 1976 137718 32372 0 0 137718 32372 1976 1670 0 0 7207 6256 0 0 10740 8485 0 0 1976 1754 0 0 59123 6963 0 0 56696 7244 0 0 1976 0 0 795 829 844 6442 0 0 3.44716 3.44716 -120.813 -3.44716 0 0 648988. 2245.63 0.33 0.04 0.08 -1 -1 0.33 0.0101866 0.00914827 99 29 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_080.v common 10.31 vpr 64.20 MiB -1 -1 0.12 20992 1 0.01 -1 -1 33308 -1 -1 22 30 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65740 30 32 375 299 1 188 84 17 17 289 -1 unnamed_device 25.6 MiB 3.77 1020 64.2 MiB 0.11 0.00 3.68402 -118.486 -3.68402 3.68402 1.15 0.000168643 0.000138608 0.0236535 0.0107157 30 2245 23 6.87369e+06 307425 556674. 1926.21 2.73 0.115771 0.0875434 25186 138497 -1 1894 22 1481 2475 158589 35944 0 0 158589 35944 2475 1857 0 0 8588 7150 0 0 11356 9316 0 0 2475 1956 0 0 69733 7382 0 0 63962 8283 0 0 2475 0 0 994 900 1088 8069 0 0 3.6873 3.6873 -135.329 -3.6873 0 0 706193. 2443.58 0.35 0.06 0.12 -1 -1 0.35 0.0175188 0.0160338 136 58 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_081.v common 7.31 vpr 64.30 MiB -1 -1 0.12 20852 1 0.01 -1 -1 32980 -1 -1 23 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65840 32 32 340 270 1 204 87 17 17 289 -1 unnamed_device 25.8 MiB 2.59 1128 64.3 MiB 0.07 0.00 4.00821 -123.654 -4.00821 4.00821 0.83 0.000193735 0.000161966 0.0121997 0.0103067 34 2742 21 6.87369e+06 321398 618332. 2139.56 1.69 0.072864 0.0624951 25762 151098 -1 2289 23 1757 2948 228828 53338 0 0 228828 53338 2948 2217 0 0 11553 10021 0 0 19070 14738 0 0 2948 2346 0 0 99643 11629 0 0 92666 12387 0 0 2948 0 0 1191 2063 2059 12935 0 0 3.99366 3.99366 -139.036 -3.99366 0 0 787024. 2723.27 0.33 0.06 0.17 -1 -1 0.33 0.0140821 0.0125002 140 31 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_082.v common 9.53 vpr 64.03 MiB -1 -1 0.13 20808 1 0.01 -1 -1 33252 -1 -1 28 31 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65564 31 32 340 275 1 201 91 17 17 289 -1 unnamed_device 25.5 MiB 3.04 1112 64.0 MiB 0.12 0.00 4.43294 -126.224 -4.43294 4.43294 1.00 0.00017462 0.000145113 0.0204887 0.0168595 34 2902 25 6.87369e+06 391268 618332. 2139.56 2.93 0.125685 0.108523 25762 151098 -1 2359 21 1644 2654 204473 47619 0 0 204473 47619 2654 1996 0 0 10351 9153 0 0 15276 12416 0 0 2654 2109 0 0 92078 10450 0 0 81460 11495 0 0 2654 0 0 1010 999 1446 9077 0 0 4.61485 4.61485 -150.449 -4.61485 0 0 787024. 2723.27 0.35 0.05 0.11 -1 -1 0.35 0.0128257 0.0113773 141 43 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_083.v common 9.22 vpr 64.35 MiB -1 -1 0.13 20836 1 0.01 -1 -1 33336 -1 -1 32 30 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65892 30 32 377 310 1 183 94 17 17 289 -1 unnamed_device 25.8 MiB 2.70 997 64.3 MiB 0.09 0.00 3.69518 -115.863 -3.69518 3.69518 0.92 0.000175213 0.000143369 0.016013 0.0132514 34 2476 24 6.87369e+06 447163 618332. 2139.56 3.04 0.100822 0.0870813 25762 151098 -1 2081 20 1313 2172 177617 40045 0 0 177617 40045 2172 1694 0 0 8430 7363 0 0 13469 10503 0 0 2172 1785 0 0 76056 9652 0 0 75318 9048 0 0 2172 0 0 859 969 988 7476 0 0 3.21096 3.21096 -120.89 -3.21096 0 0 787024. 2723.27 0.30 0.05 0.10 -1 -1 0.30 0.0120872 0.0106588 135 78 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_084.v common 7.70 vpr 63.98 MiB -1 -1 0.14 20724 1 0.01 -1 -1 33100 -1 -1 21 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65512 32 32 365 294 1 187 85 17 17 289 -1 unnamed_device 25.5 MiB 2.67 1057 64.0 MiB 0.14 0.00 3.73418 -120.089 -3.73418 3.73418 0.89 0.000162581 0.000133262 0.0298741 0.026961 34 2737 24 6.87369e+06 293451 618332. 2139.56 1.51 0.0911689 0.0797716 25762 151098 -1 2353 21 1696 3027 255559 56104 0 0 255559 56104 3027 2445 0 0 11777 10494 0 0 18101 14495 0 0 3027 2527 0 0 115579 12128 0 0 104048 14015 0 0 3027 0 0 1331 1535 1329 10490 0 0 3.93276 3.93276 -142.539 -3.93276 0 0 787024. 2723.27 0.32 0.07 0.12 -1 -1 0.32 0.0123922 0.0110233 132 54 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_085.v common 8.83 vpr 64.11 MiB -1 -1 0.15 21212 1 0.02 -1 -1 33312 -1 -1 29 29 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65644 29 32 378 310 1 179 90 17 17 289 -1 unnamed_device 25.5 MiB 2.57 982 64.1 MiB 0.07 0.00 3.18563 -100.418 -3.18563 3.18563 0.85 0.000191493 0.000158446 0.0130171 0.010898 34 2223 23 6.87369e+06 405241 618332. 2139.56 2.64 0.102506 0.0875483 25762 151098 -1 1852 23 1503 2562 177594 41833 0 0 177594 41833 2562 1828 0 0 9818 8595 0 0 15485 12154 0 0 2562 1991 0 0 75353 8237 0 0 71814 9028 0 0 2562 0 0 1059 1253 1148 8808 0 0 3.02731 3.02731 -110.743 -3.02731 0 0 787024. 2723.27 0.34 0.05 0.10 -1 -1 0.34 0.0142977 0.0125885 132 79 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_086.v common 5.53 vpr 63.62 MiB -1 -1 0.11 20680 1 0.01 -1 -1 33064 -1 -1 17 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65144 32 32 243 205 1 149 81 17 17 289 -1 unnamed_device 25.1 MiB 0.72 835 63.6 MiB 0.05 0.00 3.18563 -100.403 -3.18563 3.18563 0.89 0.000219404 0.000187112 0.0106632 0.00933336 28 1855 26 6.87369e+06 237555 531479. 1839.03 1.11 0.0542529 0.0482812 24610 126494 -1 1790 17 982 1436 109096 26084 0 0 109096 26084 1436 1270 0 0 5554 4723 0 0 7775 6506 0 0 1436 1296 0 0 46355 6099 0 0 46540 6190 0 0 1436 0 0 454 492 434 3802 0 0 3.19461 3.19461 -114.173 -3.19461 0 0 648988. 2245.63 0.44 0.08 0.10 -1 -1 0.44 0.00989945 0.00896951 96 -1 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_087.v common 11.61 vpr 64.24 MiB -1 -1 0.12 21236 1 0.01 -1 -1 33128 -1 -1 34 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65784 32 32 373 302 1 184 98 17 17 289 -1 unnamed_device 25.6 MiB 5.82 1060 64.2 MiB 0.11 0.00 3.66382 -116.633 -3.66382 3.66382 1.18 0.000217601 0.000181142 0.017 0.0144316 34 2557 24 6.87369e+06 475111 618332. 2139.56 1.83 0.0972647 0.0841664 25762 151098 -1 2076 21 1396 2318 158987 38367 0 0 158987 38367 2318 1824 0 0 9039 7877 0 0 13937 11192 0 0 2318 2012 0 0 67710 7288 0 0 63665 8174 0 0 2318 0 0 922 1001 889 7560 0 0 3.6838 3.6838 -131.998 -3.6838 0 0 787024. 2723.27 0.32 0.05 0.10 -1 -1 0.32 0.0119785 0.0106021 137 62 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_088.v common 11.02 vpr 64.20 MiB -1 -1 0.12 20840 1 0.01 -1 -1 33184 -1 -1 21 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65744 32 32 397 314 1 197 85 17 17 289 -1 unnamed_device 25.8 MiB 5.07 1162 64.2 MiB 0.08 0.00 3.54952 -124.484 -3.54952 3.54952 1.50 0.000204652 0.000163959 0.015161 0.0126478 34 2644 23 6.87369e+06 293451 618332. 2139.56 2.12 0.145635 0.122366 25762 151098 -1 2223 22 1899 3183 231637 51930 0 0 231637 51930 3183 2442 0 0 11913 10411 0 0 18162 14235 0 0 3183 2641 0 0 98049 10999 0 0 97147 11202 0 0 3183 0 0 1284 1421 1365 10611 0 0 3.7917 3.7917 -148.092 -3.7917 0 0 787024. 2723.27 0.37 0.07 0.10 -1 -1 0.37 0.0193237 0.017185 142 62 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_089.v common 7.95 vpr 63.68 MiB -1 -1 0.13 20848 1 0.00 -1 -1 33216 -1 -1 16 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65204 32 32 269 231 1 170 80 17 17 289 -1 unnamed_device 25.3 MiB 3.14 1057 63.7 MiB 0.07 0.00 3.34852 -102.009 -3.34852 3.34852 0.84 0.000129751 0.000106249 0.0128562 0.0107381 34 2353 23 6.87369e+06 223581 618332. 2139.56 1.22 0.0602705 0.051019 25762 151098 -1 1956 22 1221 1666 130352 30355 0 0 130352 30355 1666 1460 0 0 6701 5964 0 0 10212 8448 0 0 1666 1480 0 0 54725 6620 0 0 55382 6383 0 0 1666 0 0 445 388 453 3930 0 0 3.3655 3.3655 -119.008 -3.3655 0 0 787024. 2723.27 0.33 0.04 0.12 -1 -1 0.33 0.0111683 0.0100251 106 26 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_090.v common 6.52 vpr 63.71 MiB -1 -1 0.12 20496 1 0.01 -1 -1 33260 -1 -1 20 31 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65244 31 32 245 205 1 153 83 17 17 289 -1 unnamed_device 25.1 MiB 0.71 688 63.7 MiB 0.04 0.00 3.17463 -94.6151 -3.17463 3.17463 1.09 0.000132135 0.000108169 0.00713422 0.00599834 32 1995 23 6.87369e+06 279477 586450. 2029.24 2.60 0.0676631 0.0563728 25474 144626 -1 1607 22 1199 1935 130536 32179 0 0 130536 32179 1935 1624 0 0 7203 6138 0 0 11520 8806 0 0 1935 1715 0 0 53328 7106 0 0 54615 6790 0 0 1935 0 0 736 913 936 6402 0 0 3.16361 3.16361 -111.569 -3.16361 0 0 744469. 2576.02 0.27 0.04 0.09 -1 -1 0.27 0.00897584 0.00791536 99 -1 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_091.v common 9.42 vpr 64.42 MiB -1 -1 0.12 21080 1 0.02 -1 -1 33096 -1 -1 23 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65964 32 32 348 274 1 215 87 17 17 289 -1 unnamed_device 25.9 MiB 4.14 1048 64.4 MiB 0.09 0.00 3.74338 -121.833 -3.74338 3.74338 1.01 0.000164809 0.000136155 0.0164915 0.0142784 34 2860 24 6.87369e+06 321398 618332. 2139.56 1.85 0.0834802 0.0731603 25762 151098 -1 2195 20 1924 2595 184726 44565 0 0 184726 44565 2595 2303 0 0 9865 8584 0 0 15007 11951 0 0 2595 2390 0 0 76938 10303 0 0 77726 9034 0 0 2595 0 0 671 693 655 5956 0 0 4.25556 4.25556 -152.276 -4.25556 0 0 787024. 2723.27 0.33 0.06 0.10 -1 -1 0.33 0.01268 0.0113204 145 31 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_092.v common 8.30 vpr 64.27 MiB -1 -1 0.12 21216 1 0.00 -1 -1 33356 -1 -1 27 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65808 32 32 356 289 1 202 91 17 17 289 -1 unnamed_device 25.7 MiB 2.52 1147 64.3 MiB 0.08 0.00 4.30764 -129.95 -4.30764 4.30764 0.90 0.000822138 0.000787037 0.0112058 0.00966249 34 3042 38 6.87369e+06 377294 618332. 2139.56 2.64 0.171421 0.135513 25762 151098 -1 2461 19 1590 2519 194336 44696 0 0 194336 44696 2519 2066 0 0 9549 8340 0 0 14644 11683 0 0 2519 2179 0 0 83136 10118 0 0 81969 10310 0 0 2519 0 0 929 986 1086 8144 0 0 4.98285 4.98285 -157.621 -4.98285 0 0 787024. 2723.27 0.33 0.06 0.13 -1 -1 0.33 0.0153246 0.0136452 142 53 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_093.v common 7.28 vpr 64.12 MiB -1 -1 0.11 20896 1 0.01 -1 -1 33264 -1 -1 36 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65664 32 32 349 260 1 204 100 17 17 289 -1 unnamed_device 25.6 MiB 0.76 1313 64.1 MiB 0.13 0.00 4.13357 -123.907 -4.13357 4.13357 0.85 0.000235339 0.00019868 0.0229325 0.0193007 34 3015 23 6.87369e+06 503058 618332. 2139.56 3.37 0.143107 0.126084 25762 151098 -1 2492 19 1558 2881 199955 45748 0 0 199955 45748 2881 2001 0 0 10833 9214 0 0 16589 13030 0 0 2881 2283 0 0 83294 9879 0 0 83477 9341 0 0 2881 0 0 1323 1567 1793 12164 0 0 4.58185 4.58185 -143.632 -4.58185 0 0 787024. 2723.27 0.36 0.09 0.11 -1 -1 0.36 0.016482 0.0150198 157 -1 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_094.v common 9.64 vpr 63.91 MiB -1 -1 0.13 20796 1 0.01 -1 -1 33160 -1 -1 34 30 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65440 30 32 316 264 1 165 96 17 17 289 -1 unnamed_device 25.3 MiB 2.51 824 63.9 MiB 0.09 0.00 2.83325 -86.0399 -2.83325 2.83325 1.04 0.000148421 0.000120667 0.0132019 0.0107939 28 2250 46 6.87369e+06 475111 531479. 1839.03 3.49 0.127338 0.104294 24610 126494 -1 1923 20 1335 2294 183527 43548 0 0 183527 43548 2294 1735 0 0 8959 7709 0 0 13284 10846 0 0 2294 1898 0 0 81994 10322 0 0 74702 11038 0 0 2294 0 0 959 1231 1318 8530 0 0 3.15456 3.15456 -106.968 -3.15456 0 0 648988. 2245.63 0.37 0.05 0.12 -1 -1 0.37 0.0117002 0.0103388 119 47 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_095.v common 7.25 vpr 63.77 MiB -1 -1 0.12 20828 1 0.01 -1 -1 33260 -1 -1 21 27 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65300 27 32 255 219 1 139 80 17 17 289 -1 unnamed_device 25.2 MiB 0.89 599 63.8 MiB 0.06 0.00 2.8908 -78.0905 -2.8908 2.8908 0.85 0.000123974 0.000102229 0.0142035 0.0122685 34 1510 17 6.87369e+06 293451 618332. 2139.56 3.69 0.08775 0.076786 25762 151098 -1 1213 19 877 1287 75671 18990 0 0 75671 18990 1287 973 0 0 4635 3817 0 0 6827 5399 0 0 1287 1076 0 0 30191 4130 0 0 31444 3595 0 0 1287 0 0 410 630 444 3895 0 0 2.83301 2.83301 -91.1114 -2.83301 0 0 787024. 2723.27 0.31 0.03 0.10 -1 -1 0.31 0.00896439 0.00796039 96 26 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_096.v common 12.59 vpr 64.46 MiB -1 -1 0.12 20852 1 0.01 -1 -1 33440 -1 -1 24 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 66004 32 32 421 327 1 233 88 17 17 289 -1 unnamed_device 25.8 MiB 4.45 1381 64.5 MiB 0.21 0.00 3.58845 -117.662 -3.58845 3.58845 1.11 0.000238939 0.000200129 0.0531738 0.0459623 34 4092 32 6.87369e+06 335372 618332. 2139.56 3.90 0.159156 0.139665 25762 151098 -1 3016 22 2127 3463 290012 63591 0 0 290012 63591 3463 2700 0 0 13452 11937 0 0 20718 16450 0 0 3463 2898 0 0 125046 14764 0 0 123870 14842 0 0 3463 0 0 1336 1636 1638 11307 0 0 4.01406 4.01406 -142.634 -4.01406 0 0 787024. 2723.27 0.40 0.08 0.13 -1 -1 0.40 0.0212934 0.0195441 165 62 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_097.v common 11.26 vpr 63.96 MiB -1 -1 0.13 20888 1 0.02 -1 -1 33216 -1 -1 22 31 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65492 31 32 365 296 1 203 85 17 17 289 -1 unnamed_device 25.3 MiB 5.45 916 64.0 MiB 0.13 0.01 4.46437 -133.819 -4.46437 4.46437 1.06 0.000198279 0.000165071 0.0309486 0.0285078 36 2508 26 6.87369e+06 307425 648988. 2245.63 1.99 0.131339 0.118732 26050 158493 -1 2016 22 1598 2486 186465 43642 0 0 186465 43642 2486 2197 0 0 9404 8142 0 0 14135 11394 0 0 2486 2248 0 0 86314 8915 0 0 71640 10746 0 0 2486 0 0 888 1060 1062 7986 0 0 4.344 4.344 -144.336 -4.344 0 0 828058. 2865.25 0.33 0.06 0.11 -1 -1 0.33 0.0156914 0.0140346 139 60 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_098.v common 10.21 vpr 63.91 MiB -1 -1 0.12 20872 1 0.01 -1 -1 33276 -1 -1 18 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65440 32 32 331 280 1 185 82 17 17 289 -1 unnamed_device 25.5 MiB 5.51 995 63.9 MiB 0.06 0.00 3.45235 -118.525 -3.45235 3.45235 0.89 0.000173952 0.000143385 0.0103994 0.008591 34 2469 29 6.87369e+06 251529 618332. 2139.56 1.52 0.107524 0.0881222 25762 151098 -1 2178 21 1369 2042 150216 34772 0 0 150216 34772 2042 1755 0 0 7671 6533 0 0 11406 9127 0 0 2042 1885 0 0 65155 7301 0 0 61900 8171 0 0 2042 0 0 673 617 669 5459 0 0 3.4368 3.4368 -138.786 -3.4368 0 0 787024. 2723.27 0.30 0.05 0.10 -1 -1 0.30 0.0134241 0.0119347 118 62 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_099.v common 5.06 vpr 63.88 MiB -1 -1 0.11 21100 1 0.02 -1 -1 33228 -1 -1 33 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65408 32 32 326 263 1 176 97 17 17 289 -1 unnamed_device 25.4 MiB 1.11 1092 63.9 MiB 0.10 0.00 4.22895 -118.87 -4.22895 4.22895 0.86 0.000182021 0.000149804 0.0171186 0.014338 32 2765 46 6.87369e+06 461137 586450. 2029.24 1.05 0.0659694 0.0570616 25474 144626 -1 2245 21 1164 1929 179787 39475 0 0 179787 39475 1929 1419 0 0 7698 6632 0 0 12560 9817 0 0 1929 1612 0 0 80608 9304 0 0 75063 10691 0 0 1929 0 0 765 817 844 6469 0 0 3.607 3.607 -126.43 -3.607 0 0 744469. 2576.02 0.29 0.05 0.09 -1 -1 0.29 0.0119708 0.0105666 129 31 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_100.v common 8.13 vpr 64.13 MiB -1 -1 0.12 20844 1 0.01 -1 -1 33288 -1 -1 34 31 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65668 31 32 373 294 1 197 97 17 17 289 -1 unnamed_device 25.6 MiB 1.82 1073 64.1 MiB 0.10 0.00 3.46135 -105.573 -3.46135 3.46135 0.97 0.000190315 0.000159071 0.0178989 0.0151069 32 2586 24 6.87369e+06 475111 586450. 2029.24 2.92 0.111567 0.0953977 25474 144626 -1 2098 21 1304 2311 158720 37355 0 0 158720 37355 2311 1633 0 0 8875 7593 0 0 14018 10904 0 0 2311 1831 0 0 67645 7412 0 0 63560 7982 0 0 2311 0 0 1007 1442 1571 9923 0 0 3.47886 3.47886 -121.958 -3.47886 0 0 744469. 2576.02 0.42 0.07 0.13 -1 -1 0.42 0.0145015 0.0129175 149 46 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_101.v common 5.60 vpr 63.94 MiB -1 -1 0.12 21032 1 0.02 -1 -1 33328 -1 -1 31 30 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65476 30 32 325 268 1 172 93 17 17 289 -1 unnamed_device 25.6 MiB 2.00 912 63.9 MiB 0.07 0.00 2.8846 -86.2435 -2.8846 2.8846 0.76 0.000154379 0.000126783 0.0104726 0.00874929 28 2607 37 6.87369e+06 433189 531479. 1839.03 1.02 0.0487846 0.0421577 24610 126494 -1 2047 20 1316 2229 159693 37864 0 0 159693 37864 2229 1607 0 0 8558 7535 0 0 12609 10314 0 0 2229 1791 0 0 66733 8213 0 0 67335 8404 0 0 2229 0 0 913 1106 1143 8179 0 0 3.15791 3.15791 -106.559 -3.15791 0 0 648988. 2245.63 0.26 0.04 0.08 -1 -1 0.26 0.0134363 0.0122011 124 46 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_102.v common 9.07 vpr 64.27 MiB -1 -1 0.11 20804 1 0.01 -1 -1 33220 -1 -1 22 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65808 32 32 350 275 1 216 86 17 17 289 -1 unnamed_device 25.6 MiB 3.33 1107 64.3 MiB 0.10 0.00 3.95364 -125.973 -3.95364 3.95364 0.74 0.000219859 0.00019015 0.0168171 0.0140718 34 3361 35 6.87369e+06 307425 618332. 2139.56 2.63 0.0986765 0.0872514 25762 151098 -1 2699 24 2370 3651 331702 73113 0 0 331702 73113 3651 3213 0 0 14081 12475 0 0 23073 17798 0 0 3651 3321 0 0 141706 18687 0 0 145540 17619 0 0 3651 0 0 1281 1600 1475 10609 0 0 4.40025 4.40025 -156.62 -4.40025 0 0 787024. 2723.27 0.38 0.08 0.12 -1 -1 0.38 0.0161257 0.0142668 148 31 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_103.v common 11.13 vpr 64.14 MiB -1 -1 0.12 20772 1 0.01 -1 -1 33300 -1 -1 36 32 0 0 exited with return code 2 v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65676 32 32 386 307 1 196 100 17 17 289 -1 unnamed_device 25.8 MiB 3.19 1031 64.1 MiB 0.07 0.00 3.24063 -108.952 -3.24063 3.24063 0.75 0.00018231 0.000149504 0.0119096 0.0100051 24 3287 49 6.87369e+06 503058 470940. 1629.55 4.55 0.123929 0.106975 24034 113901 -1 -1 -1 5655 11235 2205128 575650 0 0 2205128 575650 11235 9093 0 0 41867 34035 0 0 72990 49861 0 0 11235 9973 0 0 1107783 237894 0 0 960018 234794 0 0 11235 0 0 5580 11624 10575 55338 0 0 -1 -1 -1 -1 -1 -1 -1 -1 0.30 0.60 0.08 -1 -1 0.30 -1 -1 147 59 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_104.v common 5.39 vpr 63.65 MiB -1 -1 0.10 20600 1 0.01 -1 -1 33188 -1 -1 19 29 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65176 29 32 269 229 1 150 80 17 17 289 -1 unnamed_device 25.1 MiB 2.06 680 63.6 MiB 0.04 0.00 3.00718 -91.0226 -3.00718 3.00718 0.73 0.00012789 0.000103975 0.00761323 0.00629551 32 1643 31 6.87369e+06 265503 586450. 2029.24 0.69 0.0313699 0.0265855 25474 144626 -1 1402 19 1148 1682 111488 26313 0 0 111488 26313 1682 1384 0 0 6169 5197 0 0 9318 7100 0 0 1682 1519 0 0 45976 5759 0 0 46661 5354 0 0 1682 0 0 534 642 619 4669 0 0 2.89086 2.89086 -106.082 -2.89086 0 0 744469. 2576.02 0.24 0.03 0.09 -1 -1 0.24 0.00906455 0.00809665 101 28 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_105.v common 5.81 vpr 63.88 MiB -1 -1 0.11 20776 1 0.00 -1 -1 33088 -1 -1 17 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65416 32 32 310 266 1 176 81 17 17 289 -1 unnamed_device 25.3 MiB 1.56 930 63.9 MiB 0.08 0.00 3.5666 -103.336 -3.5666 3.5666 0.92 0.000149941 0.000122547 0.0140018 0.0116011 34 2306 18 6.87369e+06 237555 618332. 2139.56 1.45 0.0540394 0.0457958 25762 151098 -1 1974 21 1038 1424 115372 25830 0 0 115372 25830 1424 1138 0 0 5447 4687 0 0 7923 6465 0 0 1424 1191 0 0 48691 6313 0 0 50463 6036 0 0 1424 0 0 386 364 403 3349 0 0 3.24725 3.24725 -124.863 -3.24725 0 0 787024. 2723.27 0.24 0.03 0.09 -1 -1 0.24 0.00931128 0.00817353 112 55 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_106.v common 7.27 vpr 64.01 MiB -1 -1 0.11 21032 1 0.01 -1 -1 33200 -1 -1 39 31 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65544 31 32 326 261 1 178 102 17 17 289 -1 unnamed_device 25.5 MiB 1.66 888 64.0 MiB 0.09 0.00 3.70112 -104.79 -3.70112 3.70112 0.83 0.000157029 0.000128221 0.0125292 0.0104273 32 2599 26 6.87369e+06 544980 586450. 2029.24 2.63 0.0870123 0.0738922 25474 144626 -1 1993 20 1499 2615 193544 45412 0 0 193544 45412 2615 1763 0 0 10296 8906 0 0 16169 12769 0 0 2615 2004 0 0 80052 10241 0 0 81797 9729 0 0 2615 0 0 1116 1589 1724 11218 0 0 3.7934 3.7934 -125.361 -3.7934 0 0 744469. 2576.02 0.37 0.05 0.09 -1 -1 0.37 0.0110967 0.00992729 135 29 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_107.v common 7.33 vpr 63.73 MiB -1 -1 0.12 20660 1 0.01 -1 -1 33136 -1 -1 19 29 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65260 29 32 262 224 1 168 80 17 17 289 -1 unnamed_device 25.4 MiB 3.49 807 63.7 MiB 0.04 0.00 3.70248 -100.07 -3.70248 3.70248 0.78 0.000144218 0.000120512 0.00731161 0.00611168 34 2095 28 6.87369e+06 265503 618332. 2139.56 1.18 0.0454957 0.0387044 25762 151098 -1 1748 18 1064 1428 111419 26853 0 0 111419 26853 1428 1200 0 0 5706 5122 0 0 8733 7159 0 0 1428 1236 0 0 48686 5902 0 0 45438 6234 0 0 1428 0 0 364 326 394 3308 0 0 3.46886 3.46886 -110.713 -3.46886 0 0 787024. 2723.27 0.25 0.03 0.09 -1 -1 0.25 0.00761837 0.00674765 107 25 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_108.v common 7.00 vpr 63.71 MiB -1 -1 0.10 20596 1 0.02 -1 -1 33188 -1 -1 15 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65244 32 32 278 238 1 158 79 17 17 289 -1 unnamed_device 25.3 MiB 3.21 870 63.7 MiB 0.04 0.00 3.31093 -107.104 -3.31093 3.31093 0.83 0.000135407 0.000110998 0.00738863 0.00619223 34 2152 23 6.87369e+06 209608 618332. 2139.56 1.14 0.0488453 0.041654 25762 151098 -1 1794 22 1451 2460 170850 40163 0 0 170850 40163 2460 1833 0 0 9170 8205 0 0 14728 11461 0 0 2460 1945 0 0 69885 8356 0 0 72147 8363 0 0 2460 0 0 1009 1143 1180 8298 0 0 3.19656 3.19656 -121.319 -3.19656 0 0 787024. 2723.27 0.26 0.04 0.10 -1 -1 0.26 0.00937298 0.00825534 101 31 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_109.v common 6.63 vpr 64.09 MiB -1 -1 0.12 20848 1 0.01 -1 -1 33140 -1 -1 37 31 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65624 31 32 373 300 1 185 100 17 17 289 -1 unnamed_device 25.6 MiB 3.08 989 64.1 MiB 0.07 0.00 3.11528 -104.533 -3.11528 3.11528 0.75 0.000166529 0.000136618 0.0108059 0.00898715 30 2190 19 6.87369e+06 517032 556674. 1926.21 0.72 0.0405863 0.0346486 25186 138497 -1 1775 18 1157 1834 102800 24549 0 0 102800 24549 1834 1204 0 0 6436 5282 0 0 8247 6908 0 0 1834 1337 0 0 43547 4664 0 0 40902 5154 0 0 1834 0 0 677 799 836 6372 0 0 2.74266 2.74266 -111.9 -2.74266 0 0 706193. 2443.58 0.24 0.03 0.08 -1 -1 0.24 0.0101483 0.00898448 141 60 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_110.v common 9.05 vpr 63.52 MiB -1 -1 0.10 20840 1 0.01 -1 -1 33404 -1 -1 17 31 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65048 31 32 265 230 1 169 80 17 17 289 -1 unnamed_device 25.2 MiB 2.79 844 63.5 MiB 0.03 0.00 3.0319 -94.5954 -3.0319 3.0319 0.78 0.000129982 0.000106231 0.00589192 0.00496631 28 2744 41 6.87369e+06 237555 531479. 1839.03 3.53 0.099402 0.0885372 24610 126494 -1 1970 18 1182 1655 126238 31780 0 0 126238 31780 1655 1490 0 0 6402 5559 0 0 9082 7560 0 0 1655 1536 0 0 51798 7596 0 0 55646 8039 0 0 1655 0 0 473 507 503 4084 0 0 3.10861 3.10861 -118.873 -3.10861 0 0 648988. 2245.63 0.41 0.03 0.08 -1 -1 0.41 0.00788667 0.00701615 105 30 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_111.v common 8.87 vpr 64.16 MiB -1 -1 0.11 20892 1 0.00 -1 -1 33048 -1 -1 31 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65696 32 32 349 286 1 177 95 17 17 289 -1 unnamed_device 25.6 MiB 2.84 981 64.2 MiB 0.06 0.00 2.9036 -92.5407 -2.9036 2.9036 0.79 0.000180328 0.000151168 0.00932593 0.00782801 34 2413 21 6.87369e+06 433189 618332. 2139.56 3.16 0.0984762 0.084646 25762 151098 -1 1933 23 1244 2141 140810 34154 0 0 140810 34154 2141 1451 0 0 8153 6925 0 0 12158 9595 0 0 2141 1636 0 0 56523 7400 0 0 59694 7147 0 0 2141 0 0 897 1209 1226 9161 0 0 2.95431 2.95431 -108.632 -2.95431 0 0 787024. 2723.27 0.27 0.05 0.09 -1 -1 0.27 0.0139078 0.0124802 129 54 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_112.v common 8.71 vpr 64.07 MiB -1 -1 0.12 20700 1 0.01 -1 -1 33504 -1 -1 32 31 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65612 31 32 396 325 1 185 95 17 17 289 -1 unnamed_device 25.8 MiB 3.40 955 64.1 MiB 0.09 0.00 2.9696 -103.404 -2.9696 2.9696 0.77 0.00017993 0.000148484 0.0151266 0.0125898 32 2641 37 6.87369e+06 447163 586450. 2029.24 2.52 0.11164 0.0951073 25474 144626 -1 2147 23 1903 2791 239165 54067 0 0 239165 54067 2791 2211 0 0 10868 9354 0 0 19599 14781 0 0 2791 2425 0 0 103721 12716 0 0 99395 12580 0 0 2791 0 0 888 1211 1150 8598 0 0 3.25351 3.25351 -124.186 -3.25351 0 0 744469. 2576.02 0.28 0.05 0.10 -1 -1 0.28 0.0122159 0.0107277 137 87 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_113.v common 7.40 vpr 63.95 MiB -1 -1 0.11 20348 1 0.01 -1 -1 33180 -1 -1 16 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65480 32 32 303 262 1 154 80 17 17 289 -1 unnamed_device 25.5 MiB 2.46 708 63.9 MiB 0.04 0.00 2.8516 -87.9482 -2.8516 2.8516 0.69 0.000137294 0.000111546 0.00785894 0.00652996 34 2086 29 6.87369e+06 223581 618332. 2139.56 2.45 0.0803627 0.069492 25762 151098 -1 1536 22 1171 1949 139943 35369 0 0 139943 35369 1949 1510 0 0 7867 6924 0 0 12178 9728 0 0 1949 1696 0 0 52987 8061 0 0 63013 7450 0 0 1949 0 0 778 940 971 6400 0 0 2.88831 2.88831 -106.176 -2.88831 0 0 787024. 2723.27 0.27 0.04 0.09 -1 -1 0.27 0.0106849 0.00944228 99 54 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_114.v common 5.48 vpr 63.97 MiB -1 -1 0.10 20620 1 0.01 -1 -1 33100 -1 -1 18 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65504 32 32 290 244 1 177 82 17 17 289 -1 unnamed_device 25.4 MiB 1.49 989 64.0 MiB 0.07 0.00 3.36109 -108.361 -3.36109 3.36109 0.76 0.000134845 0.00011015 0.0124535 0.0103275 34 2403 22 6.87369e+06 251529 618332. 2139.56 1.42 0.0556322 0.0471491 25762 151098 -1 2039 19 1363 2028 173011 38343 0 0 173011 38343 2028 1712 0 0 7977 7126 0 0 12322 9959 0 0 2028 1783 0 0 74971 8874 0 0 73685 8889 0 0 2028 0 0 665 564 566 5153 0 0 3.37021 3.37021 -124.149 -3.37021 0 0 787024. 2723.27 0.27 0.04 0.09 -1 -1 0.27 0.0087943 0.00780111 114 31 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_115.v common 6.66 vpr 63.95 MiB -1 -1 0.12 20776 1 0.02 -1 -1 33128 -1 -1 22 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65488 32 32 318 257 1 197 86 17 17 289 -1 unnamed_device 25.5 MiB 2.46 941 64.0 MiB 0.05 0.00 4.03908 -110.471 -4.03908 4.03908 0.82 0.00014836 0.000122126 0.0077071 0.00661754 34 2461 19 6.87369e+06 307425 618332. 2139.56 1.28 0.0538871 0.0465412 25762 151098 -1 2099 21 1530 2121 147253 35403 0 0 147253 35403 2121 1785 0 0 8077 6961 0 0 12207 9798 0 0 2121 1876 0 0 61061 7512 0 0 61666 7471 0 0 2121 0 0 591 572 709 5183 0 0 3.98006 3.98006 -131.826 -3.98006 0 0 787024. 2723.27 0.32 0.06 0.09 -1 -1 0.32 0.0129864 0.0115587 132 27 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_116.v common 7.88 vpr 63.87 MiB -1 -1 0.12 20640 1 0.01 -1 -1 33324 -1 -1 29 29 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65400 29 32 324 268 1 169 90 17 17 289 -1 unnamed_device 25.5 MiB 2.77 910 63.9 MiB 0.08 0.00 3.20763 -92.8782 -3.20763 3.20763 0.74 0.000146934 0.000120002 0.0126869 0.0105201 34 2254 21 6.87369e+06 405241 618332. 2139.56 2.53 0.0770181 0.0651978 25762 151098 -1 1777 19 1018 1731 111964 27848 0 0 111964 27848 1731 1242 0 0 6732 5831 0 0 10104 8174 0 0 1731 1337 0 0 45837 5733 0 0 45829 5531 0 0 1731 0 0 713 893 967 6990 0 0 2.96031 2.96031 -102.377 -2.96031 0 0 787024. 2723.27 0.25 0.03 0.11 -1 -1 0.25 0.00934477 0.00828149 123 49 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_117.v common 7.06 vpr 64.23 MiB -1 -1 0.12 20880 1 0.01 -1 -1 33204 -1 -1 22 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65768 32 32 393 312 1 215 86 17 17 289 -1 unnamed_device 25.8 MiB 2.98 1112 64.2 MiB 0.09 0.00 4.14151 -131.605 -4.14151 4.14151 0.75 0.000172966 0.000141933 0.0172264 0.0143863 34 3014 26 6.87369e+06 307425 618332. 2139.56 1.46 0.0788225 0.0675647 25762 151098 -1 2472 23 1929 2984 269192 58377 0 0 269192 58377 2984 2506 0 0 11218 9913 0 0 17449 13780 0 0 2984 2636 0 0 116436 14673 0 0 118121 14869 0 0 2984 0 0 1055 1747 1702 10416 0 0 4.28856 4.28856 -151.495 -4.28856 0 0 787024. 2723.27 0.29 0.06 0.10 -1 -1 0.29 0.0135275 0.0119843 151 62 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_118.v common 4.56 vpr 63.48 MiB -1 -1 0.11 20632 1 0.01 -1 -1 32944 -1 -1 17 31 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65000 31 32 229 197 1 143 80 17 17 289 -1 unnamed_device 25.0 MiB 0.62 840 63.5 MiB 0.05 0.00 2.9769 -91.9689 -2.9769 2.9769 0.94 0.000115578 9.4121e-05 0.00821289 0.00681981 34 1849 21 6.87369e+06 237555 618332. 2139.56 1.30 0.0437519 0.0374504 25762 151098 -1 1680 21 969 1549 121030 27471 0 0 121030 27471 1549 1281 0 0 5747 4951 0 0 8955 6953 0 0 1549 1317 0 0 51772 6652 0 0 51458 6317 0 0 1549 0 0 580 527 557 4547 0 0 2.79301 2.79301 -103.138 -2.79301 0 0 787024. 2723.27 0.24 0.03 0.09 -1 -1 0.24 0.00798641 0.00709614 92 -1 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_119.v common 5.60 vpr 64.59 MiB -1 -1 0.12 20868 1 0.01 -1 -1 33436 -1 -1 35 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 66144 32 32 412 334 1 194 99 17 17 289 -1 unnamed_device 26.1 MiB 1.85 1078 64.6 MiB 0.10 0.00 3.50715 -119.693 -3.50715 3.50715 0.76 0.000186643 0.000154199 0.0182798 0.0152419 30 2578 21 6.87369e+06 489084 556674. 1926.21 0.90 0.0531269 0.0451446 25186 138497 -1 2072 23 1357 1945 118680 28070 0 0 118680 28070 1945 1547 0 0 6804 5610 0 0 8667 7213 0 0 1945 1675 0 0 47685 6473 0 0 51634 5552 0 0 1945 0 0 588 692 688 5437 0 0 3.84846 3.84846 -138.34 -3.84846 0 0 706193. 2443.58 0.23 0.04 0.09 -1 -1 0.23 0.0129466 0.0113901 145 87 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_120.v common 8.53 vpr 63.88 MiB -1 -1 0.12 20816 1 0.01 -1 -1 33356 -1 -1 16 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65408 32 32 376 318 1 168 80 17 17 289 -1 unnamed_device 25.4 MiB 4.44 961 63.9 MiB 0.05 0.00 2.9898 -111.33 -2.9898 2.9898 0.94 0.000158265 0.00012845 0.0115588 0.00962008 34 2256 24 6.87369e+06 223581 618332. 2139.56 1.33 0.0704661 0.0611722 25762 151098 -1 1925 23 1609 2345 182558 41524 0 0 182558 41524 2345 1871 0 0 8862 7775 0 0 14282 11329 0 0 2345 2002 0 0 76101 9610 0 0 78623 8937 0 0 2345 0 0 736 797 852 6384 0 0 3.05731 3.05731 -130.678 -3.05731 0 0 787024. 2723.27 0.24 0.06 0.09 -1 -1 0.24 0.0198411 0.0181174 114 93 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_121.v common 8.54 vpr 63.96 MiB -1 -1 0.12 20848 1 0.01 -1 -1 32928 -1 -1 32 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65492 32 32 360 293 1 182 96 17 17 289 -1 unnamed_device 25.5 MiB 2.89 1117 64.0 MiB 0.10 0.00 3.24063 -105.014 -3.24063 3.24063 0.89 0.000185973 0.000154232 0.0140945 0.0117374 34 2414 22 6.87369e+06 447163 618332. 2139.56 2.58 0.0875286 0.0743595 25762 151098 -1 2072 23 1258 1924 136181 31583 0 0 136181 31583 1924 1458 0 0 7286 6198 0 0 10589 8515 0 0 1924 1544 0 0 58124 6801 0 0 56334 7067 0 0 1924 0 0 666 790 937 6833 0 0 2.97901 2.97901 -113.008 -2.97901 0 0 787024. 2723.27 0.26 0.04 0.10 -1 -1 0.26 0.0117087 0.0103085 134 57 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_122.v common 8.25 vpr 64.27 MiB -1 -1 0.12 21024 1 0.01 -1 -1 33192 -1 -1 25 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65812 32 32 396 299 1 240 89 17 17 289 -1 unnamed_device 25.8 MiB 3.86 1274 64.3 MiB 0.09 0.00 4.69005 -144.336 -4.69005 4.69005 0.77 0.000188811 0.00015553 0.0192889 0.0167163 34 3323 25 6.87369e+06 349346 618332. 2139.56 1.70 0.0819929 0.0710267 25762 151098 -1 2671 24 2443 3732 315267 72131 0 0 315267 72131 3732 3017 0 0 14491 12962 0 0 23592 18557 0 0 3732 3135 0 0 138524 16624 0 0 131196 17836 0 0 3732 0 0 1289 1718 1953 12156 0 0 4.9322 4.9322 -164.516 -4.9322 0 0 787024. 2723.27 0.25 0.07 0.10 -1 -1 0.25 0.0143581 0.0127161 171 31 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_123.v common 6.50 vpr 63.52 MiB -1 -1 0.10 20600 1 0.01 -1 -1 33096 -1 -1 15 30 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65048 30 32 224 207 1 137 77 17 17 289 -1 unnamed_device 25.1 MiB 1.36 809 63.5 MiB 0.04 0.00 2.40522 -81.1084 -2.40522 2.40522 0.94 0.000117758 9.7652e-05 0.00804282 0.00682743 34 1666 21 6.87369e+06 209608 618332. 2139.56 2.46 0.0493312 0.0418336 25762 151098 -1 1551 17 665 899 81260 17554 0 0 81260 17554 899 799 0 0 3565 3034 0 0 5126 4218 0 0 899 807 0 0 35860 4363 0 0 34911 4333 0 0 899 0 0 234 227 219 2047 0 0 2.34306 2.34306 -97.2686 -2.34306 0 0 787024. 2723.27 0.25 0.02 0.09 -1 -1 0.25 0.00620052 0.0054917 81 29 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_124.v common 6.28 vpr 63.79 MiB -1 -1 0.10 20520 1 0.01 -1 -1 33160 -1 -1 19 30 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65320 30 32 286 239 1 151 81 17 17 289 -1 unnamed_device 25.4 MiB 1.07 830 63.8 MiB 0.07 0.00 3.14163 -100.812 -3.14163 3.14163 0.79 0.000140524 0.000115627 0.011396 0.00929721 34 1907 19 6.87369e+06 265503 618332. 2139.56 2.46 0.0849661 0.0745526 25762 151098 -1 1546 20 1095 1596 117179 27126 0 0 117179 27126 1596 1351 0 0 6012 5098 0 0 8982 7133 0 0 1596 1431 0 0 47432 6629 0 0 51561 5484 0 0 1596 0 0 501 633 589 4629 0 0 3.01331 3.01331 -114.206 -3.01331 0 0 787024. 2723.27 0.25 0.03 0.09 -1 -1 0.25 0.0089693 0.00793625 105 29 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_125.v common 4.77 vpr 63.80 MiB -1 -1 0.11 20504 1 0.01 -1 -1 33112 -1 -1 23 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65332 32 32 296 247 1 158 87 17 17 289 -1 unnamed_device 25.4 MiB 0.99 898 63.8 MiB 0.10 0.00 2.9879 -101.502 -2.9879 2.9879 0.83 0.000160666 0.000130327 0.0136618 0.0113143 30 2276 21 6.87369e+06 321398 556674. 1926.21 1.00 0.0826755 0.0665826 25186 138497 -1 1900 16 970 1776 116490 26827 0 0 116490 26827 1776 1249 0 0 6290 5266 0 0 8237 6799 0 0 1776 1323 0 0 50045 6102 0 0 48366 6088 0 0 1776 0 0 806 823 828 6445 0 0 3.00256 3.00256 -117.284 -3.00256 0 0 706193. 2443.58 0.24 0.03 0.09 -1 -1 0.24 0.00797011 0.00709475 109 31 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_126.v common 5.77 vpr 63.43 MiB -1 -1 0.11 20544 1 0.01 -1 -1 33480 -1 -1 29 25 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64956 25 32 216 194 1 123 86 17 17 289 -1 unnamed_device 25.1 MiB 0.69 504 63.4 MiB 0.05 0.00 2.9029 -68.0577 -2.9029 2.9029 0.78 0.000105295 8.5691e-05 0.0086309 0.00716258 32 1659 31 6.87369e+06 405241 586450. 2029.24 2.35 0.057602 0.0488818 25474 144626 -1 1156 24 962 1776 121459 30103 0 0 121459 30103 1776 1177 0 0 6781 5806 0 0 11744 8760 0 0 1776 1346 0 0 48468 6730 0 0 50914 6284 0 0 1776 0 0 814 1015 1103 7504 0 0 2.86326 2.86326 -78.3429 -2.86326 0 0 744469. 2576.02 0.26 0.03 0.09 -1 -1 0.26 0.00779858 0.00684646 87 19 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_127.v common 9.16 vpr 64.16 MiB -1 -1 0.13 20816 1 0.01 -1 -1 33132 -1 -1 20 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65700 32 32 376 307 1 193 84 17 17 289 -1 unnamed_device 25.6 MiB 2.75 1061 64.2 MiB 0.08 0.00 3.64275 -112.262 -3.64275 3.64275 0.80 0.00017496 0.000142723 0.0161115 0.0132565 36 2700 20 6.87369e+06 279477 648988. 2245.63 3.50 0.119297 0.104769 26050 158493 -1 2404 23 1448 2576 191468 44075 0 0 191468 44075 2576 2087 0 0 9541 8430 0 0 13977 11282 0 0 2576 2173 0 0 79247 10537 0 0 83551 9566 0 0 2576 0 0 1128 1331 1137 8756 0 0 3.60416 3.60416 -127.864 -3.60416 0 0 828058. 2865.25 0.32 0.05 0.10 -1 -1 0.32 0.012429 0.010914 133 69 -1 -1 -1 -1 + fixed_k6_frac_ripple_N8_22nm.xml mult_128.v common 8.24 vpr 64.21 MiB -1 -1 0.13 20612 1 0.01 -1 -1 33192 -1 -1 31 31 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65752 31 32 409 331 1 193 94 17 17 289 -1 unnamed_device 25.8 MiB 3.01 1032 64.2 MiB 0.08 0.00 3.48023 -114.653 -3.48023 3.48023 0.77 0.000184113 0.000151865 0.0135267 0.0112782 28 2565 23 6.87369e+06 433189 531479. 1839.03 2.53 0.098636 0.0840183 24610 126494 -1 2275 22 1813 2824 194391 47200 0 0 194391 47200 2824 2200 0 0 10894 9440 0 0 16091 13011 0 0 2824 2295 0 0 80676 9909 0 0 81082 10345 0 0 2824 0 0 1011 1343 1357 9221 0 0 3.43621 3.43621 -131.453 -3.43621 0 0 648988. 2245.63 0.23 0.05 0.08 -1 -1 0.23 0.0136097 0.0120457 143 86 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_001.v common 6.62 vpr 63.84 MiB -1 -1 0.12 21068 1 0.02 -1 -1 33128 -1 -1 24 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65368 32 32 354 285 1 223 88 17 17 289 -1 unnamed_device 25.3 MiB 2.63 1214 63.8 MiB 0.10 0.00 4.26107 -127.141 -4.26107 4.26107 0.81 0.000172407 0.000142438 0.0190146 0.0152444 34 2963 27 6.89349e+06 338252 618332. 2139.56 1.29 0.0728464 0.061445 25762 151098 -1 2421 20 1542 2347 176104 42335 0 0 176104 42335 2347 2030 0 0 8887 7318 0 0 14095 11083 0 0 2347 2115 0 0 73998 10183 0 0 74430 9606 0 0 2347 0 0 805 911 920 7015 0 0 4.68905 4.68905 -153.769 -4.68905 0 0 787024. 2723.27 0.25 0.05 0.10 -1 -1 0.25 0.0114359 0.0101757 149 47 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_002.v common 5.76 vpr 63.85 MiB -1 -1 0.12 20992 1 0.01 -1 -1 33128 -1 -1 26 30 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65380 30 32 363 293 1 228 88 17 17 289 -1 unnamed_device 25.3 MiB 1.65 1167 63.8 MiB 0.07 0.00 3.89968 -122.519 -3.89968 3.89968 0.74 0.000160868 0.00013236 0.0114257 0.00948563 34 3037 24 6.89349e+06 366440 618332. 2139.56 1.26 0.0655706 0.0557698 25762 151098 -1 2485 21 2029 3045 215714 49270 0 0 215714 49270 3045 2481 0 0 11299 9385 0 0 17160 13623 0 0 3045 2645 0 0 94873 9800 0 0 86292 11336 0 0 3045 0 0 1016 920 765 7778 0 0 4.28674 4.28674 -148.118 -4.28674 0 0 787024. 2723.27 0.25 0.05 0.13 -1 -1 0.25 0.0110299 0.00978451 156 58 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_003.v common 6.12 vpr 63.56 MiB -1 -1 0.12 20768 1 0.01 -1 -1 33168 -1 -1 21 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65088 32 32 299 247 1 190 85 17 17 289 -1 unnamed_device 25.1 MiB 1.91 1099 63.6 MiB 0.08 0.00 3.32519 -100.006 -3.32519 3.32519 0.84 0.000141206 0.000115438 0.0129721 0.0107271 34 2513 44 6.89349e+06 295971 618332. 2139.56 1.42 0.0553345 0.0467172 25762 151098 -1 2107 19 1088 1585 104366 24952 0 0 104366 24952 1585 1314 0 0 5931 4945 0 0 8823 7055 0 0 1585 1362 0 0 45534 4878 0 0 40908 5398 0 0 1585 0 0 497 347 515 4118 0 0 3.507 3.507 -119.856 -3.507 0 0 787024. 2723.27 0.26 0.03 0.10 -1 -1 0.26 0.00919703 0.00817653 125 26 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_004.v common 5.79 vpr 63.81 MiB -1 -1 0.11 20684 1 0.01 -1 -1 33324 -1 -1 24 29 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65340 29 32 308 248 1 195 85 17 17 289 -1 unnamed_device 25.3 MiB 1.57 938 63.8 MiB 0.18 0.00 3.92328 -106.805 -3.92328 3.92328 0.80 0.000187992 0.0001586 0.0163583 0.0137425 34 2514 27 6.89349e+06 338252 618332. 2139.56 1.37 0.064228 0.0548767 25762 151098 -1 1848 18 1208 1920 115171 27978 0 0 115171 27978 1920 1338 0 0 6932 5783 0 0 10520 8280 0 0 1920 1433 0 0 47959 5312 0 0 45920 5832 0 0 1920 0 0 712 639 727 5866 0 0 3.72556 3.72556 -116.85 -3.72556 0 0 787024. 2723.27 0.25 0.03 0.10 -1 -1 0.25 0.00904552 0.00807168 134 25 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_005.v common 7.92 vpr 64.11 MiB -1 -1 0.11 21044 1 0.01 -1 -1 33168 -1 -1 23 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65652 32 32 336 268 1 212 87 17 17 289 -1 unnamed_device 25.7 MiB 1.40 1287 64.1 MiB 0.07 0.00 4.24401 -124.601 -4.24401 4.24401 0.77 0.000165627 0.000136483 0.0111665 0.00934966 38 2956 32 6.89349e+06 324158 678818. 2348.85 3.83 0.0937323 0.0800984 26626 170182 -1 2584 22 2033 3695 294730 61349 0 0 294730 61349 3695 2937 0 0 12479 10489 0 0 18913 14358 0 0 3695 3106 0 0 129174 14520 0 0 126774 15939 0 0 3695 0 0 1662 2333 2414 15044 0 0 4.36629 4.36629 -146.121 -4.36629 0 0 902133. 3121.57 0.28 0.06 0.10 -1 -1 0.28 0.0121245 0.0107316 142 31 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_006.v common 6.52 vpr 63.90 MiB -1 -1 0.11 20808 1 0.01 -1 -1 33232 -1 -1 33 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65432 32 32 366 295 1 231 97 17 17 289 -1 unnamed_device 25.4 MiB 2.30 1308 63.9 MiB 0.11 0.00 3.42286 -111.444 -3.42286 3.42286 0.77 0.000185073 0.000151288 0.0173554 0.0143854 36 2802 21 6.89349e+06 465097 648988. 2245.63 1.52 0.0876649 0.0704885 26050 158493 -1 2460 21 1736 3064 214726 47942 0 0 214726 47942 3064 2100 0 0 10767 8824 0 0 16902 12775 0 0 3064 2356 0 0 93179 10473 0 0 87750 11414 0 0 3064 0 0 1328 1637 1657 11910 0 0 3.34165 3.34165 -125.301 -3.34165 0 0 828058. 2865.25 0.27 0.05 0.10 -1 -1 0.27 0.0118006 0.0104557 162 55 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_007.v common 6.93 vpr 63.50 MiB -1 -1 0.11 20680 1 0.02 -1 -1 33304 -1 -1 21 27 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65020 27 32 259 221 1 160 80 17 17 289 -1 unnamed_device 24.9 MiB 1.25 834 63.5 MiB 0.06 0.00 3.25123 -92.5861 -3.25123 3.25123 0.82 0.000122149 9.9553e-05 0.0109785 0.00909915 36 1829 21 6.89349e+06 295971 648988. 2245.63 2.89 0.0595854 0.0505153 26050 158493 -1 1575 21 1172 1715 133972 29349 0 0 133972 29349 1715 1370 0 0 6225 5129 0 0 9415 7477 0 0 1715 1410 0 0 56786 7222 0 0 58116 6741 0 0 1715 0 0 543 658 600 4976 0 0 3.07746 3.07746 -105.545 -3.07746 0 0 828058. 2865.25 0.28 0.03 0.10 -1 -1 0.28 0.00860794 0.00761762 107 26 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_008.v common 6.67 vpr 63.66 MiB -1 -1 0.12 20680 1 0.01 -1 -1 33152 -1 -1 32 31 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65184 31 32 271 219 1 164 95 17 17 289 -1 unnamed_device 25.3 MiB 0.69 870 63.7 MiB 0.08 0.00 2.54074 -78.8558 -2.54074 2.54074 0.78 0.000139181 0.000114112 0.0116886 0.00966917 28 2234 26 6.89349e+06 451003 531479. 1839.03 3.38 0.0657682 0.0559685 24610 126494 -1 1940 18 1059 1805 136995 32693 0 0 136995 32693 1805 1226 0 0 6588 5364 0 0 9530 7648 0 0 1805 1355 0 0 58814 8781 0 0 58453 8319 0 0 1805 0 0 746 1115 1194 8028 0 0 2.70361 2.70361 -97.0959 -2.70361 0 0 648988. 2245.63 0.21 0.03 0.08 -1 -1 0.21 0.00795839 0.00703897 119 -1 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_009.v common 5.91 vpr 63.83 MiB -1 -1 0.11 20708 1 0.01 -1 -1 33228 -1 -1 20 31 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65364 31 32 317 271 1 207 83 17 17 289 -1 unnamed_device 25.2 MiB 1.57 1110 63.8 MiB 0.07 0.00 2.80245 -99.26 -2.80245 2.80245 0.98 0.000159526 0.000128789 0.0119714 0.00989368 34 2728 42 6.89349e+06 281877 618332. 2139.56 1.38 0.0627038 0.0530859 25762 151098 -1 2209 20 1514 2012 171152 36981 0 0 171152 36981 2012 1730 0 0 7542 6230 0 0 11220 8950 0 0 2012 1897 0 0 76429 8870 0 0 71937 9304 0 0 2012 0 0 498 497 330 4333 0 0 3.20626 3.20626 -120.866 -3.20626 0 0 787024. 2723.27 0.25 0.04 0.09 -1 -1 0.25 0.00958744 0.0084497 130 60 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_010.v common 7.13 vpr 63.65 MiB -1 -1 0.11 20492 1 0.01 -1 -1 33348 -1 -1 18 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65180 32 32 298 248 1 185 82 17 17 289 -1 unnamed_device 25.2 MiB 1.97 941 63.7 MiB 0.05 0.00 3.15648 -104.965 -3.15648 3.15648 0.74 0.000160371 0.000134409 0.00944211 0.007997 34 2331 20 6.89349e+06 253689 618332. 2139.56 2.60 0.0698798 0.0592325 25762 151098 -1 1956 19 1135 1530 107800 24988 0 0 107800 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mult_013.v common 6.43 vpr 63.91 MiB -1 -1 0.11 21140 1 0.01 -1 -1 33132 -1 -1 23 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65444 32 32 344 272 1 209 87 17 17 289 -1 unnamed_device 25.5 MiB 1.96 997 63.9 MiB 0.11 0.00 3.19568 -104.214 -3.19568 3.19568 0.97 0.000155752 0.000126832 0.0276788 0.0250309 34 2854 22 6.89349e+06 324158 618332. 2139.56 1.46 0.067266 0.0586355 25762 151098 -1 2281 24 1846 2855 250952 54684 0 0 250952 54684 2855 2445 0 0 10526 8626 0 0 17427 13217 0 0 2855 2488 0 0 110851 13482 0 0 106438 14426 0 0 2855 0 0 1009 1184 1077 8143 0 0 3.28421 3.28421 -121.993 -3.28421 0 0 787024. 2723.27 0.25 0.06 0.09 -1 -1 0.25 0.0123028 0.0108476 143 31 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_014.v common 6.22 vpr 63.93 MiB -1 -1 0.11 20932 1 0.01 -1 -1 33252 -1 -1 24 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65464 32 32 363 295 1 232 88 17 17 289 -1 unnamed_device 25.5 MiB 1.72 1237 63.9 MiB 0.10 0.00 4.42931 -129.469 -4.42931 4.42931 0.86 0.000177487 0.00014811 0.0167794 0.014178 36 2786 22 6.89349e+06 338252 648988. 2245.63 1.46 0.0724529 0.06235 26050 158493 -1 2334 20 1627 2209 140243 33567 0 0 140243 33567 2209 1733 0 0 8020 6574 0 0 11213 9061 0 0 2209 1886 0 0 57609 7488 0 0 58983 6825 0 0 2209 0 0 582 686 356 5211 0 0 4.40225 4.40225 -150.232 -4.40225 0 0 828058. 2865.25 0.28 0.04 0.10 -1 -1 0.28 0.011418 0.0101338 153 58 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_015.v common 7.03 vpr 63.29 MiB -1 -1 0.10 20904 1 0.02 -1 -1 33152 -1 -1 18 29 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64808 29 32 248 215 1 160 79 17 17 289 -1 unnamed_device 24.8 MiB 1.76 828 63.3 MiB 0.04 0.00 2.55142 -81.9482 -2.55142 2.55142 0.77 0.000131575 0.00011007 0.00837642 0.0070777 34 1982 20 6.89349e+06 253689 618332. 2139.56 2.52 0.0597765 0.0511834 25762 151098 -1 1691 22 1094 1568 120876 28308 0 0 120876 28308 1568 1263 0 0 5928 4992 0 0 9334 7334 0 0 1568 1304 0 0 50723 6952 0 0 51755 6463 0 0 1568 0 0 474 482 328 3874 0 0 2.70361 2.70361 -96.2805 -2.70361 0 0 787024. 2723.27 0.41 0.03 0.09 -1 -1 0.41 0.00870065 0.00766926 102 21 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_016.v common 6.37 vpr 63.89 MiB -1 -1 0.12 20824 1 0.01 -1 -1 33272 -1 -1 24 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65420 32 32 370 297 1 234 88 17 17 289 -1 unnamed_device 25.4 MiB 2.04 1341 63.9 MiB 0.09 0.00 3.3439 -110.98 -3.3439 3.3439 0.71 0.00038998 0.000358468 0.0147428 0.0122547 34 3293 23 6.89349e+06 338252 618332. 2139.56 1.52 0.0702368 0.061003 25762 151098 -1 2698 24 2219 3564 314081 66456 0 0 314081 66456 3564 2809 0 0 13236 11136 0 0 20761 16024 0 0 3564 2999 0 0 140314 15281 0 0 132642 18207 0 0 3564 0 0 1345 1708 1871 12370 0 0 3.54705 3.54705 -133.856 -3.54705 0 0 787024. 2723.27 0.26 0.06 0.10 -1 -1 0.26 0.0128497 0.0113397 159 55 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_017.v common 8.00 vpr 64.02 MiB -1 -1 0.11 20788 1 0.01 -1 -1 33232 -1 -1 22 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65560 32 32 338 269 1 205 86 17 17 289 -1 unnamed_device 25.6 MiB 1.84 1142 64.0 MiB 0.07 0.00 3.18768 -107.577 -3.18768 3.18768 0.75 0.000154612 0.000126043 0.0134272 0.0112245 36 2649 20 6.89349e+06 310065 648988. 2245.63 3.33 0.0786984 0.0670963 26050 158493 -1 2239 19 1413 2106 174626 36620 0 0 174626 36620 2106 1673 0 0 7773 6381 0 0 11122 9089 0 0 2106 1809 0 0 76906 8601 0 0 74613 9067 0 0 2106 0 0 693 578 731 5494 0 0 3.02816 3.02816 -119.71 -3.02816 0 0 828058. 2865.25 0.28 0.04 0.10 -1 -1 0.28 0.0111614 0.0100159 142 31 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_018.v common 5.90 vpr 63.90 MiB -1 -1 0.12 20832 1 0.01 -1 -1 33208 -1 -1 21 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65436 32 32 323 276 1 215 85 17 17 289 -1 unnamed_device 25.3 MiB 1.68 1179 63.9 MiB 0.09 0.00 2.80245 -104.61 -2.80245 2.80245 0.82 0.000171682 0.000143467 0.0149139 0.0124324 34 2832 24 6.89349e+06 295971 618332. 2139.56 1.46 0.0634005 0.0542947 25762 151098 -1 2314 20 1433 1886 147787 32839 0 0 147787 32839 1886 1659 0 0 7015 5611 0 0 10833 8454 0 0 1886 1715 0 0 64402 7472 0 0 61765 7928 0 0 1886 0 0 453 599 616 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fixed_k6_frac_uripple_N8_22nm.xml mult_020.v common 9.08 vpr 63.58 MiB -1 -1 0.12 20604 1 0.01 -1 -1 33280 -1 -1 19 31 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65104 31 32 291 243 1 179 82 17 17 289 -1 unnamed_device 25.2 MiB 3.14 931 63.6 MiB 0.08 0.00 3.72732 -118.161 -3.72732 3.72732 0.75 0.000147431 0.00011986 0.0134012 0.0109633 36 2163 24 6.89349e+06 267783 648988. 2245.63 2.93 0.0778847 0.0661411 26050 158493 -1 1798 22 1256 2001 146355 33386 0 0 146355 33386 2001 1614 0 0 7260 6038 0 0 11695 9158 0 0 2001 1766 0 0 63555 7216 0 0 59843 7594 0 0 2001 0 0 745 682 728 5918 0 0 3.36035 3.36035 -125.331 -3.36035 0 0 828058. 2865.25 0.34 0.04 0.10 -1 -1 0.34 0.0105409 0.0094069 117 30 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_021.v common 6.05 vpr 63.93 MiB -1 -1 0.11 20684 1 0.01 -1 -1 33420 -1 -1 34 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65464 32 32 342 271 1 207 98 17 17 289 -1 unnamed_device 25.5 MiB 1.00 1121 63.9 MiB 0.11 0.00 3.68693 -121.727 -3.68693 3.68693 0.89 0.000156829 0.00012901 0.0165407 0.0133336 34 2603 28 6.89349e+06 479191 618332. 2139.56 1.67 0.0890227 0.0725001 25762 151098 -1 2128 20 1447 2093 147012 33714 0 0 147012 33714 2093 1658 0 0 7972 6384 0 0 11694 9488 0 0 2093 1773 0 0 63311 7059 0 0 59849 7352 0 0 2093 0 0 646 811 709 6321 0 0 3.82484 3.82484 -139.547 -3.82484 0 0 787024. 2723.27 0.39 0.04 0.22 -1 -1 0.39 0.0100281 0.00887893 151 31 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_022.v common 6.87 vpr 64.28 MiB -1 -1 0.11 20828 1 0.01 -1 -1 33352 -1 -1 23 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65820 32 32 372 300 1 229 87 17 17 289 -1 unnamed_device 25.7 MiB 1.38 1311 64.3 MiB 0.09 0.00 3.53795 -113.225 -3.53795 3.53795 0.77 0.00138091 0.00134355 0.0248856 0.0229496 34 3186 25 6.89349e+06 324158 618332. 2139.56 2.23 0.125993 0.115134 25762 151098 -1 2568 22 1753 2746 205477 45555 0 0 205477 45555 2746 2218 0 0 10116 8231 0 0 15300 12073 0 0 2746 2404 0 0 88955 10014 0 0 85614 10615 0 0 2746 0 0 993 1388 1213 8912 0 0 3.86596 3.86596 -137.678 -3.86596 0 0 787024. 2723.27 0.60 0.13 0.14 -1 -1 0.60 0.012865 0.0113798 155 59 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_023.v common 5.17 vpr 63.11 MiB -1 -1 0.10 20656 1 0.00 -1 -1 33368 -1 -1 19 26 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64620 26 32 190 182 1 126 77 17 17 289 -1 unnamed_device 24.6 MiB 1.21 442 63.1 MiB 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0.00926993 0.00829509 125 21 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_027.v common 4.73 vpr 63.77 MiB -1 -1 0.11 20824 1 0.01 -1 -1 33248 -1 -1 31 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65300 32 32 297 233 1 177 95 17 17 289 -1 unnamed_device 25.3 MiB 0.93 1065 63.8 MiB 0.09 0.00 2.7033 -91.5418 -2.7033 2.7033 0.80 0.000145692 0.000119358 0.0136964 0.0112254 28 2556 23 6.89349e+06 436909 531479. 1839.03 0.79 0.0455391 0.0386139 24610 126494 -1 2220 20 1287 2320 169519 38159 0 0 169519 38159 2320 1545 0 0 8514 6898 0 0 12313 9894 0 0 2320 1707 0 0 73303 9013 0 0 70749 9102 0 0 2320 0 0 1033 1479 1666 10098 0 0 2.65951 2.65951 -109.072 -2.65951 0 0 648988. 2245.63 0.23 0.04 0.08 -1 -1 0.23 0.010139 0.008966 130 -1 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_028.v common 6.81 vpr 63.73 MiB -1 -1 0.12 20876 1 0.01 -1 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2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65396 32 32 284 241 1 177 81 17 17 289 -1 unnamed_device 25.5 MiB 1.89 995 63.9 MiB 0.06 0.00 2.9839 -102.38 -2.9839 2.9839 0.81 0.000132907 0.000108693 0.0107793 0.00901758 34 2274 20 6.89349e+06 239595 618332. 2139.56 1.35 0.0677334 0.0600827 25762 151098 -1 1895 19 1278 1845 133882 30551 0 0 133882 30551 1845 1575 0 0 6834 5592 0 0 10367 8169 0 0 1845 1656 0 0 56910 6810 0 0 56081 6749 0 0 1845 0 0 567 404 606 4714 0 0 2.84196 2.84196 -113.762 -2.84196 0 0 787024. 2723.27 0.29 0.03 0.09 -1 -1 0.29 0.00995117 0.00893119 112 31 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_030.v common 6.64 vpr 63.48 MiB -1 -1 0.12 20756 1 0.01 -1 -1 33268 -1 -1 17 30 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65004 30 32 262 227 1 161 79 17 17 289 -1 unnamed_device 24.9 MiB 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1 0.01 -1 -1 33260 -1 -1 25 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65544 32 32 367 282 1 224 89 17 17 289 -1 unnamed_device 25.5 MiB 1.58 1321 64.0 MiB 0.21 0.00 3.60205 -109.719 -3.60205 3.60205 0.91 0.000254388 0.000219558 0.0208449 0.0183247 34 3204 25 6.89349e+06 352346 618332. 2139.56 2.17 0.0834627 0.0696256 25762 151098 -1 2583 21 1457 2439 192394 41750 0 0 192394 41750 2439 1874 0 0 9188 7591 0 0 14070 11124 0 0 2439 1967 0 0 82065 9959 0 0 82193 9235 0 0 2439 0 0 982 1477 1849 10839 0 0 3.60416 3.60416 -124.443 -3.60416 0 0 787024. 2723.27 0.32 0.12 0.10 -1 -1 0.32 0.0274008 0.0163023 159 26 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_036.v common 10.84 vpr 64.12 MiB -1 -1 0.11 21024 1 0.02 -1 -1 33012 -1 -1 24 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65664 32 32 391 311 1 250 88 17 17 289 -1 unnamed_device 25.8 MiB 1.96 1342 64.1 MiB 0.09 0.00 3.57677 -122.298 -3.57677 3.57677 0.70 0.000171538 0.000141169 0.0168734 0.014169 34 3666 31 6.89349e+06 338252 618332. 2139.56 5.31 0.121239 0.104335 25762 151098 -1 2853 21 2352 3233 316457 66718 0 0 316457 66718 3233 2938 0 0 12181 10137 0 0 19014 14832 0 0 3233 3032 0 0 139366 18618 0 0 139430 17161 0 0 3233 0 0 881 1166 1271 8691 0 0 3.75255 3.75255 -145.95 -3.75255 0 0 787024. 2723.27 0.47 0.07 0.20 -1 -1 0.47 0.0131763 0.0116913 168 62 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_037.v common 5.36 vpr 63.36 MiB -1 -1 0.11 20824 1 0.01 -1 -1 33184 -1 -1 18 31 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64880 31 32 279 237 1 167 81 17 17 289 -1 unnamed_device 24.8 MiB 1.17 933 63.4 MiB 0.05 0.00 3.21878 -100.089 -3.21878 3.21878 1.00 0.00014204 0.000118187 0.00848433 0.00707119 34 2123 18 6.89349e+06 253689 618332. 2139.56 1.21 0.0405918 0.0346244 25762 151098 -1 1908 20 1091 1728 161407 33905 0 0 161407 33905 1728 1428 0 0 6498 5394 0 0 10334 8142 0 0 1728 1480 0 0 68869 9027 0 0 72250 8434 0 0 1728 0 0 637 905 987 6117 0 0 3.10776 3.10776 -110.937 -3.10776 0 0 787024. 2723.27 0.28 0.04 0.10 -1 -1 0.28 0.00876086 0.0077827 109 30 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_038.v common 6.07 vpr 64.12 MiB -1 -1 0.12 21136 1 0.01 -1 -1 33216 -1 -1 25 31 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65664 31 32 370 297 1 235 88 17 17 289 -1 unnamed_device 25.6 MiB 2.14 1278 64.1 MiB 0.07 0.00 3.42249 -111.085 -3.42249 3.42249 0.80 0.000178921 0.000138366 0.0129493 0.0107818 34 3248 25 6.89349e+06 352346 618332. 2139.56 1.25 0.0546309 0.0463011 25762 151098 -1 2734 20 1692 2513 197814 43486 0 0 197814 43486 2513 2066 0 0 9255 7635 0 0 13732 10887 0 0 2513 2204 0 0 88412 9532 0 0 81389 11162 0 0 2513 0 0 821 983 981 7512 0 0 3.6263 3.6263 -133.82 -3.6263 0 0 787024. 2723.27 0.25 0.05 0.10 -1 -1 0.25 0.0115905 0.0103021 160 57 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_039.v common 11.86 vpr 64.10 MiB -1 -1 0.12 20888 1 0.01 -1 -1 33284 -1 -1 25 31 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65636 31 32 377 302 1 241 88 17 17 289 -1 unnamed_device 25.5 MiB 2.75 1178 64.1 MiB 0.09 0.00 4.34127 -130.272 -4.34127 4.34127 0.84 0.000170267 0.000139829 0.0154598 0.0126253 36 3242 27 6.89349e+06 352346 648988. 2245.63 6.37 0.126347 0.107133 26050 158493 -1 2528 22 1846 2671 214573 45653 0 0 214573 45653 2671 2280 0 0 9405 7471 0 0 13554 10578 0 0 2671 2334 0 0 94081 11333 0 0 92191 11657 0 0 2671 0 0 825 812 879 6837 0 0 4.87568 4.87568 -159.658 -4.87568 0 0 828058. 2865.25 0.28 0.05 0.10 -1 -1 0.28 0.0130368 0.0114973 163 60 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_040.v common 7.65 vpr 64.07 MiB -1 -1 0.14 21168 1 0.01 -1 -1 33120 -1 -1 25 31 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65604 31 32 383 305 1 240 88 17 17 289 -1 unnamed_device 25.4 MiB 2.71 1138 64.1 MiB 0.09 0.00 4.74618 -136.117 -4.74618 4.74618 1.04 0.000169454 0.000139146 0.0167903 0.0141965 34 2944 24 6.89349e+06 352346 618332. 2139.56 1.34 0.0744789 0.0638135 25762 151098 -1 2320 18 1685 2509 168012 39033 0 0 168012 39033 2509 2046 0 0 9177 7601 0 0 13994 10971 0 0 2509 2090 0 0 72941 7776 0 0 66882 8549 0 0 2509 0 0 824 892 703 6896 0 0 4.85604 4.85604 -159.309 -4.85604 0 0 787024. 2723.27 0.29 0.04 0.10 -1 -1 0.29 0.0107439 0.00951696 166 60 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_041.v common 7.61 vpr 63.89 MiB -1 -1 0.13 20672 1 0.01 -1 -1 33152 -1 -1 24 31 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65420 31 32 352 285 1 223 87 17 17 289 -1 unnamed_device 25.4 MiB 2.52 1126 63.9 MiB 0.08 0.00 3.17668 -101.657 -3.17668 3.17668 1.17 0.000164472 0.000135598 0.0134455 0.011336 34 2695 23 6.89349e+06 338252 618332. 2139.56 1.60 0.0829008 0.0716685 25762 151098 -1 2252 21 1674 2509 157770 38972 0 0 157770 38972 2509 2047 0 0 9192 7486 0 0 13718 10795 0 0 2509 2219 0 0 68829 7919 0 0 61013 8506 0 0 2509 0 0 835 1042 1070 7620 0 0 3.09761 3.09761 -116.467 -3.09761 0 0 787024. 2723.27 0.26 0.04 0.09 -1 -1 0.26 0.0115502 0.0101566 148 51 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_042.v common 7.05 vpr 63.71 MiB -1 -1 0.13 20824 1 0.01 -1 -1 33400 -1 -1 20 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65236 32 32 291 242 1 188 84 17 17 289 -1 unnamed_device 25.2 MiB 1.88 989 63.7 MiB 0.08 0.00 3.64925 -99.1057 -3.64925 3.64925 1.05 0.000150429 0.000123241 0.0164294 0.0129449 34 2463 36 6.89349e+06 281877 618332. 2139.56 1.58 0.0631059 0.0536832 25762 151098 -1 2009 19 1102 1581 110671 26213 0 0 110671 26213 1581 1325 0 0 5994 4868 0 0 8922 7250 0 0 1581 1377 0 0 46682 5690 0 0 45911 5703 0 0 1581 0 0 479 703 606 4529 0 0 3.76866 3.76866 -119.427 -3.76866 0 0 787024. 2723.27 0.30 0.04 0.14 -1 -1 0.30 0.0100378 0.00898711 120 24 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_043.v common 8.80 vpr 64.24 MiB -1 -1 0.15 21004 1 0.02 -1 -1 33124 -1 -1 31 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65784 32 32 457 356 1 296 95 17 17 289 -1 unnamed_device 25.8 MiB 2.24 1522 64.2 MiB 0.12 0.00 4.19571 -136.492 -4.19571 4.19571 1.02 0.000258474 0.000217379 0.0196747 0.0170805 36 4131 28 6.89349e+06 436909 648988. 2245.63 2.53 0.114631 0.0983845 26050 158493 -1 3130 20 2338 3543 247950 56353 0 0 247950 56353 3543 2825 0 0 12697 10404 0 0 18202 14425 0 0 3543 3016 0 0 105518 12477 0 0 104447 13206 0 0 3543 0 0 1205 1644 1686 11750 0 0 4.46619 4.46619 -162.795 -4.46619 0 0 828058. 2865.25 0.44 0.16 0.10 -1 -1 0.44 0.0248693 0.0229082 203 84 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_044.v common 7.51 vpr 63.43 MiB -1 -1 0.12 20552 1 0.00 -1 -1 33420 -1 -1 18 31 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64952 31 32 261 225 1 171 81 17 17 289 -1 unnamed_device 24.9 MiB 2.06 1018 63.4 MiB 0.16 0.00 2.974 -92.1126 -2.974 2.974 1.03 0.000176711 0.000149645 0.0115535 0.00997413 34 2212 25 6.89349e+06 253689 618332. 2139.56 1.55 0.0560555 0.0482638 25762 151098 -1 1914 20 1222 1683 129461 29120 0 0 129461 29120 1683 1479 0 0 6429 5217 0 0 9655 7793 0 0 1683 1597 0 0 55475 6648 0 0 54536 6386 0 0 1683 0 0 461 485 414 3999 0 0 3.00446 3.00446 -108.485 -3.00446 0 0 787024. 2723.27 0.39 0.04 0.14 -1 -1 0.39 0.00912027 0.00812828 106 24 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_045.v common 6.09 vpr 63.78 MiB -1 -1 0.13 20852 1 0.01 -1 -1 33096 -1 -1 23 31 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65308 31 32 337 267 1 207 86 17 17 289 -1 unnamed_device 25.4 MiB 1.44 1236 63.8 MiB 0.07 0.00 3.75642 -119.135 -3.75642 3.75642 0.95 0.000225124 0.000191684 0.0111355 0.00939722 34 2803 32 6.89349e+06 324158 618332. 2139.56 1.46 0.0672071 0.0580908 25762 151098 -1 2314 18 1475 2205 151426 35447 0 0 151426 35447 2205 1851 0 0 8310 6906 0 0 12172 9727 0 0 2205 1901 0 0 61662 7769 0 0 64872 7293 0 0 2205 0 0 730 860 843 6490 0 0 3.91596 3.91596 -139.252 -3.91596 0 0 787024. 2723.27 0.32 0.05 0.10 -1 -1 0.32 0.0110892 0.00991172 140 30 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_046.v common 8.58 vpr 63.84 MiB -1 -1 0.11 20912 1 0.01 -1 -1 33216 -1 -1 23 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65376 32 32 349 284 1 222 87 17 17 289 -1 unnamed_device 25.3 MiB 2.50 1301 63.8 MiB 0.22 0.00 3.41329 -109.461 -3.41329 3.41329 1.52 0.000201733 0.000170105 0.018712 0.0159492 34 3323 27 6.89349e+06 324158 618332. 2139.56 1.90 0.0992531 0.0862201 25762 151098 -1 2595 20 1449 2310 173341 38672 0 0 173341 38672 2310 1805 0 0 8494 6843 0 0 12997 10163 0 0 2310 2081 0 0 74996 8766 0 0 72234 9014 0 0 2310 0 0 861 1017 1007 7541 0 0 3.3867 3.3867 -125.31 -3.3867 0 0 787024. 2723.27 0.37 0.06 0.11 -1 -1 0.37 0.0131347 0.0116942 149 50 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_047.v common 6.56 vpr 63.62 MiB -1 -1 0.12 20524 1 0.01 -1 -1 33104 -1 -1 26 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65148 32 32 291 230 1 175 90 17 17 289 -1 unnamed_device 25.2 MiB 0.59 1058 63.6 MiB 0.12 0.00 3.37229 -107.321 -3.37229 3.37229 1.10 0.000198276 0.000167301 0.0332425 0.0311237 34 2370 23 6.89349e+06 366440 618332. 2139.56 2.18 0.112072 0.1018 25762 151098 -1 2069 19 1261 2350 178368 38542 0 0 178368 38542 2350 1635 0 0 8530 6935 0 0 13499 10285 0 0 2350 1808 0 0 78707 8329 0 0 72932 9550 0 0 2350 0 0 1089 1142 1511 9452 0 0 3.5071 3.5071 -123.823 -3.5071 0 0 787024. 2723.27 0.29 0.04 0.15 -1 -1 0.29 0.0106206 0.00953952 123 -1 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_048.v common 7.09 vpr 63.83 MiB -1 -1 0.13 20940 1 0.01 -1 -1 33144 -1 -1 23 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65360 32 32 353 287 1 220 87 17 17 289 -1 unnamed_device 25.5 MiB 2.01 1074 63.8 MiB 0.08 0.00 3.42271 -103.027 -3.42271 3.42271 0.87 0.000177529 0.000147124 0.0150326 0.0125744 34 2955 34 6.89349e+06 324158 618332. 2139.56 1.68 0.0905821 0.0773376 25762 151098 -1 2251 21 1702 2417 190542 44239 0 0 190542 44239 2417 2042 0 0 9333 7924 0 0 14407 11626 0 0 2417 2187 0 0 82069 9935 0 0 79899 10525 0 0 2417 0 0 715 901 880 6565 0 0 2.92916 2.92916 -112.003 -2.92916 0 0 787024. 2723.27 0.33 0.06 0.12 -1 -1 0.33 0.0167153 0.0141669 148 52 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_049.v common 9.78 vpr 63.98 MiB -1 -1 0.14 21116 1 0.01 -1 -1 33136 -1 -1 24 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65512 32 32 361 291 1 233 88 17 17 289 -1 unnamed_device 25.5 MiB 2.28 1108 64.0 MiB 0.08 0.00 3.31619 -102.977 -3.31619 3.31619 1.10 0.000168723 0.000139136 0.0150289 0.012525 36 3146 34 6.89349e+06 338252 648988. 2245.63 3.92 0.124897 0.103217 26050 158493 -1 2392 21 1628 2403 193594 44835 0 0 193594 44835 2403 1993 0 0 8795 7286 0 0 13393 10448 0 0 2403 2045 0 0 84017 11128 0 0 82583 11935 0 0 2403 0 0 775 856 992 7702 0 0 3.729 3.729 -127.784 -3.729 0 0 828058. 2865.25 0.44 0.06 0.11 -1 -1 0.44 0.0156393 0.0129871 154 52 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_050.v common 9.13 vpr 64.04 MiB -1 -1 0.12 20876 1 0.02 -1 -1 33232 -1 -1 26 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65580 32 32 382 305 1 243 90 17 17 289 -1 unnamed_device 25.4 MiB 1.80 1356 64.0 MiB 0.09 0.00 3.22384 -110.279 -3.22384 3.22384 0.84 0.000206178 0.000172416 0.0157848 0.0132427 36 3078 23 6.89349e+06 366440 648988. 2245.63 4.17 0.12723 0.110082 26050 158493 -1 2570 20 1751 2428 201207 44155 0 0 201207 44155 2428 1988 0 0 8797 7133 0 0 13385 10572 0 0 2428 2174 0 0 85817 11529 0 0 88352 10759 0 0 2428 0 0 677 903 804 6466 0 0 3.23156 3.23156 -127.243 -3.23156 0 0 828058. 2865.25 0.30 0.06 0.10 -1 -1 0.30 0.0136782 0.0121399 164 59 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_051.v common 6.36 vpr 63.91 MiB -1 -1 0.12 20496 1 0.01 -1 -1 32996 -1 -1 21 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65440 32 32 306 248 1 188 85 17 17 289 -1 unnamed_device 25.4 MiB 1.85 954 63.9 MiB 0.08 0.00 3.61195 -107.106 -3.61195 3.61195 0.84 0.000150476 0.000123341 0.013567 0.011238 34 2346 34 6.89349e+06 295971 618332. 2139.56 1.40 0.0705169 0.0604726 25762 151098 -1 1901 18 1172 1882 135792 32737 0 0 135792 32737 1882 1478 0 0 7042 5687 0 0 10873 8653 0 0 1882 1597 0 0 60655 7550 0 0 53458 7772 0 0 1882 0 0 710 967 772 6287 0 0 3.5682 3.5682 -121.63 -3.5682 0 0 787024. 2723.27 0.29 0.04 0.10 -1 -1 0.29 0.00951089 0.00842346 128 21 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_052.v common 8.34 vpr 63.67 MiB -1 -1 0.12 20808 1 0.02 -1 -1 33092 -1 -1 22 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65196 32 32 319 257 1 203 86 17 17 289 -1 unnamed_device 25.1 MiB 1.73 1095 63.7 MiB 0.07 0.00 3.93308 -117.677 -3.93308 3.93308 0.86 0.000182677 0.000154605 0.0116331 0.0098323 36 2558 30 6.89349e+06 310065 648988. 2245.63 3.37 0.0916324 0.0786154 26050 158493 -1 2292 22 1449 2122 155473 35421 0 0 155473 35421 2122 1800 0 0 7889 6480 0 0 11735 9360 0 0 2122 1903 0 0 67264 7760 0 0 64341 8118 0 0 2122 0 0 673 679 786 5606 0 0 3.8768 3.8768 -133.547 -3.8768 0 0 828058. 2865.25 0.36 0.05 0.12 -1 -1 0.36 0.0146673 0.0123136 135 26 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_053.v common 6.73 vpr 64.07 MiB -1 -1 0.14 20760 1 0.01 -1 -1 33364 -1 -1 24 31 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65612 31 32 373 299 1 227 87 17 17 289 -1 unnamed_device 25.5 MiB 1.64 1438 64.1 MiB 0.17 0.00 3.81572 -120.928 -3.81572 3.81572 1.11 0.000192448 0.000155039 0.0358036 0.0319643 34 3450 33 6.89349e+06 338252 618332. 2139.56 1.47 0.0975998 0.0848166 25762 151098 -1 2774 31 2138 3426 420382 151461 0 0 420382 151461 3426 2855 0 0 12359 10037 0 0 19821 14646 0 0 3426 3054 0 0 194054 60555 0 0 187296 60314 0 0 3426 0 0 1288 2050 1885 12019 0 0 3.86596 3.86596 -141.891 -3.86596 0 0 787024. 2723.27 0.28 0.11 0.10 -1 -1 0.28 0.0208015 0.0182455 156 58 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_054.v common 7.94 vpr 64.16 MiB -1 -1 0.13 20792 1 0.01 -1 -1 33296 -1 -1 25 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65704 32 32 387 315 1 249 89 17 17 289 -1 unnamed_device 25.8 MiB 2.40 1313 64.2 MiB 0.06 0.00 3.80725 -116.552 -3.80725 3.80725 0.84 0.000185161 0.000152483 0.0103537 0.00873469 34 3795 43 6.89349e+06 352346 618332. 2139.56 2.03 0.0813498 0.0701126 25762 151098 -1 2879 22 2034 3030 217925 50305 0 0 217925 50305 3030 2376 0 0 11076 8994 0 0 16912 13139 0 0 3030 2624 0 0 91137 11797 0 0 92740 11375 0 0 3030 0 0 996 1207 944 8259 0 0 4.0703 4.0703 -140.981 -4.0703 0 0 787024. 2723.27 0.55 0.07 0.12 -1 -1 0.55 0.0162223 0.0136291 166 74 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_055.v common 7.66 vpr 63.35 MiB -1 -1 0.11 20588 1 0.01 -1 -1 32932 -1 -1 15 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64872 32 32 251 219 1 156 79 17 17 289 -1 unnamed_device 24.9 MiB 2.03 846 63.4 MiB 0.05 0.00 2.79059 -89.1076 -2.79059 2.79059 1.00 0.000128287 0.00010635 0.00985457 0.00853166 34 1990 22 6.89349e+06 211408 618332. 2139.56 1.65 0.0490815 0.0426571 25762 151098 -1 1747 19 941 1511 101388 23826 0 0 101388 23826 1511 1131 0 0 5697 4622 0 0 8645 6771 0 0 1511 1204 0 0 40609 5227 0 0 43415 4871 0 0 1511 0 0 570 735 831 5273 0 0 2.60451 2.60451 -97.7705 -2.60451 0 0 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vpr 64.23 MiB -1 -1 0.14 20880 1 0.02 -1 -1 33280 -1 -1 25 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65772 32 32 387 293 1 237 89 17 17 289 -1 unnamed_device 25.6 MiB 1.88 1416 64.2 MiB 0.11 0.00 4.49577 -134.492 -4.49577 4.49577 1.17 0.000204645 0.000169715 0.0207895 0.0175374 38 2983 21 6.89349e+06 352346 678818. 2348.85 4.09 0.165978 0.143834 26626 170182 -1 2630 17 1603 2514 173988 37291 0 0 173988 37291 2514 1901 0 0 8576 6746 0 0 11568 9319 0 0 2514 2112 0 0 77185 8292 0 0 71631 8921 0 0 2514 0 0 911 799 1257 7625 0 0 4.47745 4.47745 -150.867 -4.47745 0 0 902133. 3121.57 0.60 0.06 0.17 -1 -1 0.60 0.0146202 0.0131316 168 28 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_058.v common 8.36 vpr 63.72 MiB -1 -1 0.13 20980 1 0.01 -1 -1 33132 -1 -1 22 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65252 32 32 340 270 1 212 86 17 17 289 -1 unnamed_device 25.4 MiB 2.26 1004 63.7 MiB 0.10 0.00 3.53796 -113.493 -3.53796 3.53796 1.00 0.000182534 0.000152033 0.0157523 0.0129835 34 2878 41 6.89349e+06 310065 618332. 2139.56 2.55 0.137249 0.123884 25762 151098 -1 2321 20 1694 2418 188685 43383 0 0 188685 43383 2418 2048 0 0 9144 7386 0 0 13634 10907 0 0 2418 2115 0 0 77690 11142 0 0 83381 9785 0 0 2418 0 0 724 971 931 6912 0 0 3.29511 3.29511 -127.075 -3.29511 0 0 787024. 2723.27 0.40 0.24 0.12 -1 -1 0.40 0.0494633 0.0463924 144 31 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_059.v common 7.69 vpr 63.54 MiB -1 -1 0.12 20524 1 0.01 -1 -1 33304 -1 -1 27 30 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65068 30 32 278 235 1 175 89 17 17 289 -1 unnamed_device 25.2 MiB 1.40 1008 63.5 MiB 0.08 0.00 3.17564 -102.032 -3.17564 3.17564 0.83 0.000134053 0.000109536 0.0138911 0.0114687 36 2058 19 6.89349e+06 380534 648988. 2245.63 3.31 0.080889 0.0692306 26050 158493 -1 1843 18 1123 1852 130592 29439 0 0 130592 29439 1852 1388 0 0 6768 5571 0 0 10306 8107 0 0 1852 1519 0 0 53442 6636 0 0 56372 6218 0 0 1852 0 0 729 914 911 6964 0 0 3.32045 3.32045 -120.481 -3.32045 0 0 828058. 2865.25 0.31 0.04 0.11 -1 -1 0.31 0.00949645 0.00842403 118 29 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_060.v common 12.19 vpr 64.43 MiB -1 -1 0.12 21264 1 0.02 -1 -1 33264 -1 -1 27 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65976 32 32 431 332 1 270 91 17 17 289 -1 unnamed_device 25.6 MiB 3.49 1598 64.4 MiB 0.29 0.00 5.53985 -161.329 -5.53985 5.53985 1.09 0.000244505 0.00020773 0.0351236 0.0313155 36 4010 24 6.89349e+06 380534 648988. 2245.63 4.78 0.137636 0.121821 26050 158493 -1 3375 20 2414 3743 285578 60897 0 0 285578 60897 3743 3110 0 0 13145 10335 0 0 18919 14750 0 0 3743 3367 0 0 124729 14563 0 0 121299 14772 0 0 3743 0 0 1329 1755 1832 12067 0 0 5.60773 5.60773 -191.701 -5.60773 0 0 828058. 2865.25 0.33 0.14 0.11 -1 -1 0.33 0.044237 0.0424218 188 62 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_061.v common 6.55 vpr 63.91 MiB -1 -1 0.13 20708 1 0.02 -1 -1 33068 -1 -1 21 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65440 32 32 336 268 1 205 85 17 17 289 -1 unnamed_device 25.3 MiB 1.44 1069 63.9 MiB 0.09 0.00 3.82232 -121.404 -3.82232 3.82232 0.84 0.000175264 0.000143405 0.0162363 0.0136252 34 2588 24 6.89349e+06 295971 618332. 2139.56 1.82 0.124208 0.109834 25762 151098 -1 2238 21 1746 2446 178678 41148 0 0 178678 41148 2446 2030 0 0 9124 7384 0 0 13932 10903 0 0 2446 2111 0 0 73723 9914 0 0 77007 8806 0 0 2446 0 0 700 894 827 6753 0 0 3.9728 3.9728 -141.708 -3.9728 0 0 787024. 2723.27 0.46 0.12 0.10 -1 -1 0.46 0.0130898 0.0116659 139 31 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_062.v common 5.58 vpr 63.47 MiB -1 -1 0.12 20296 1 0.01 -1 -1 33044 -1 -1 24 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64992 32 32 231 199 1 142 88 17 17 289 -1 unnamed_device 25.1 MiB 0.64 700 63.5 MiB 0.05 0.00 2.8828 -80.534 -2.8828 2.8828 0.96 0.000135003 0.000111023 0.0088314 0.00731374 34 1745 19 6.89349e+06 338252 618332. 2139.56 1.43 0.0450405 0.0390603 25762 151098 -1 1509 14 787 1391 94469 22333 0 0 94469 22333 1391 939 0 0 5146 4183 0 0 7900 6119 0 0 1391 1025 0 0 38699 5107 0 0 39942 4960 0 0 1391 0 0 604 775 868 5708 0 0 2.86021 2.86021 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mult_064.v common 5.29 vpr 63.39 MiB -1 -1 0.11 20844 1 0.01 -1 -1 33228 -1 -1 19 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64908 32 32 247 207 1 153 83 17 17 289 -1 unnamed_device 25.0 MiB 0.73 705 63.4 MiB 0.04 0.00 2.81765 -87.6139 -2.81765 2.81765 0.92 0.000180525 0.000152803 0.00714721 0.00594142 30 1897 34 6.89349e+06 267783 556674. 1926.21 1.06 0.0468158 0.040435 25186 138497 -1 1476 20 968 1787 101345 25248 0 0 101345 25248 1787 1283 0 0 6143 4860 0 0 8451 6834 0 0 1787 1377 0 0 40166 5445 0 0 43011 5449 0 0 1787 0 0 819 796 898 6592 0 0 2.76606 2.76606 -102.863 -2.76606 0 0 706193. 2443.58 0.51 0.05 0.11 -1 -1 0.51 0.0143225 0.0132519 98 -1 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_065.v common 7.06 vpr 63.67 MiB -1 -1 0.10 20608 1 0.01 -1 -1 33148 -1 -1 20 30 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65196 30 32 278 235 1 175 82 17 17 289 -1 unnamed_device 25.3 MiB 1.61 854 63.7 MiB 0.09 0.00 3.17368 -94.5914 -3.17368 3.17368 1.06 0.000157699 0.000131723 0.0193052 0.0168159 34 2178 24 6.89349e+06 281877 618332. 2139.56 1.96 0.0779499 0.0663108 25762 151098 -1 1948 21 1262 1797 139865 32388 0 0 139865 32388 1797 1568 0 0 6686 5444 0 0 10399 8003 0 0 1797 1627 0 0 56281 8370 0 0 62905 7376 0 0 1797 0 0 535 798 897 5633 0 0 3.16966 3.16966 -112.864 -3.16966 0 0 787024. 2723.27 0.29 0.04 0.10 -1 -1 0.29 0.00972707 0.00860222 113 29 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_066.v common 8.86 vpr 64.09 MiB -1 -1 0.11 20840 1 0.01 -1 -1 33352 -1 -1 26 29 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65628 29 32 355 287 1 224 87 17 17 289 -1 unnamed_device 25.6 MiB 3.71 1099 64.1 MiB 0.07 0.00 3.60013 -107.086 -3.60013 3.60013 0.88 0.000230728 0.000193782 0.0130533 0.0108139 34 2984 24 6.89349e+06 366440 618332. 2139.56 1.54 0.0858134 0.0734175 25762 151098 -1 2411 20 1607 2356 186894 42713 0 0 186894 42713 2356 1978 0 0 8813 7392 0 0 13558 10774 0 0 2356 2035 0 0 79757 10410 0 0 80054 10124 0 0 2356 0 0 749 959 706 6294 0 0 3.53034 3.53034 -125.154 -3.53034 0 0 787024. 2723.27 0.30 0.05 0.10 -1 -1 0.30 0.0136562 0.0121906 154 56 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_067.v common 7.96 vpr 63.90 MiB -1 -1 0.11 20952 1 0.01 -1 -1 33208 -1 -1 22 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65432 32 32 358 289 1 230 86 17 17 289 -1 unnamed_device 25.4 MiB 1.98 1279 63.9 MiB 0.14 0.00 4.11834 -130.881 -4.11834 4.11834 1.20 0.000199919 0.000168369 0.0423578 0.0393154 34 3168 46 6.89349e+06 310065 618332. 2139.56 2.16 0.115593 0.102577 25762 151098 -1 2433 23 1814 2653 184236 43475 0 0 184236 43475 2653 2117 0 0 9948 8198 0 0 15681 12537 0 0 2653 2174 0 0 77489 9268 0 0 75812 9181 0 0 2653 0 0 839 814 842 6980 0 0 4.36825 4.36825 -151.235 -4.36825 0 0 787024. 2723.27 0.38 0.06 0.14 -1 -1 0.38 0.0147893 0.0130891 151 51 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_068.v common 6.76 vpr 64.02 MiB -1 -1 0.11 20920 1 0.00 -1 -1 33100 -1 -1 23 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65556 32 32 353 285 1 228 87 17 17 289 -1 unnamed_device 25.5 MiB 1.74 1306 64.0 MiB 0.07 0.00 4.28447 -128.177 -4.28447 4.28447 1.19 0.000177008 0.000138259 0.0144728 0.0113737 36 3190 28 6.89349e+06 324158 648988. 2245.63 1.46 0.067002 0.0570235 26050 158493 -1 2772 22 2026 2893 251371 53297 0 0 251371 53297 2893 2573 0 0 10400 8506 0 0 16412 12721 0 0 2893 2662 0 0 109081 13427 0 0 109692 13408 0 0 2893 0 0 867 875 1030 7963 0 0 4.47595 4.47595 -151.774 -4.47595 0 0 828058. 2865.25 0.31 0.07 0.11 -1 -1 0.31 0.0174034 0.015761 150 48 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_069.v common 5.63 vpr 63.48 MiB -1 -1 0.10 20620 1 0.01 -1 -1 32944 -1 -1 15 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65000 32 32 276 237 1 165 79 17 17 289 -1 unnamed_device 24.9 MiB 1.60 935 63.5 MiB 0.06 0.00 3.71247 -110.557 -3.71247 3.71247 0.74 0.000128918 0.000105228 0.0106004 0.00871555 30 2193 22 6.89349e+06 211408 556674. 1926.21 0.73 0.0350166 0.029731 25186 138497 -1 1783 22 897 1261 85302 19605 0 0 85302 19605 1261 1002 0 0 4524 3646 0 0 6025 5001 0 0 1261 1038 0 0 36961 4404 0 0 35270 4514 0 0 1261 0 0 364 359 349 3081 0 0 3.13785 3.13785 -117.364 -3.13785 0 0 706193. 2443.58 0.35 0.05 0.18 -1 -1 0.35 0.02936 0.0282904 105 31 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_070.v common 5.97 vpr 63.70 MiB -1 -1 0.13 20800 1 0.01 -1 -1 33320 -1 -1 20 31 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65232 31 32 319 272 1 203 83 17 17 289 -1 unnamed_device 25.2 MiB 1.60 1000 63.7 MiB 0.09 0.00 2.9155 -100.463 -2.9155 2.9155 0.95 0.000156849 0.000130386 0.0147279 0.0122097 34 2702 23 6.89349e+06 281877 618332. 2139.56 1.47 0.0661114 0.0567861 25762 151098 -1 2237 19 1497 2076 148262 33894 0 0 148262 33894 2076 1778 0 0 7588 6047 0 0 11128 8670 0 0 2076 1922 0 0 60332 8354 0 0 65062 7123 0 0 2076 0 0 579 610 588 5011 0 0 3.24211 3.24211 -123.257 -3.24211 0 0 787024. 2723.27 0.26 0.04 0.09 -1 -1 0.26 0.00894181 0.00789861 131 60 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_071.v common 6.45 vpr 64.07 MiB -1 -1 0.12 20884 1 0.01 -1 -1 33164 -1 -1 26 30 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65608 30 32 329 273 1 213 88 17 17 289 -1 unnamed_device 25.7 MiB 2.05 1176 64.1 MiB 0.07 0.00 3.0363 -92.5923 -3.0363 3.0363 0.79 0.000164086 0.000137513 0.0114179 0.00955366 34 2706 34 6.89349e+06 366440 618332. 2139.56 1.66 0.0802387 0.0549617 25762 151098 -1 2330 20 1477 2206 180014 39262 0 0 180014 39262 2206 1823 0 0 8249 6767 0 0 12800 10125 0 0 2206 1927 0 0 78816 9108 0 0 75737 9512 0 0 2206 0 0 729 1216 1287 8070 0 0 2.87446 2.87446 -106.781 -2.87446 0 0 787024. 2723.27 0.26 0.04 0.10 -1 -1 0.26 0.0116563 0.0103826 142 52 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_072.v common 7.41 vpr 63.56 MiB -1 -1 0.12 20488 1 0.01 -1 -1 33224 -1 -1 23 28 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65084 28 32 277 229 1 171 83 17 17 289 -1 unnamed_device 25.2 MiB 1.25 887 63.6 MiB 0.06 0.00 3.50369 -90.3791 -3.50369 3.50369 0.77 0.000130813 0.000106605 0.0111444 0.00921034 36 1955 18 6.89349e+06 324158 648988. 2245.63 3.27 0.0661738 0.0552999 26050 158493 -1 1526 20 1060 1722 97214 23434 0 0 97214 23434 1722 1236 0 0 6036 4847 0 0 9008 6936 0 0 1722 1273 0 0 39142 4480 0 0 39584 4662 0 0 1722 0 0 662 746 1164 6766 0 0 3.70146 3.70146 -101.634 -3.70146 0 0 828058. 2865.25 0.29 0.04 0.12 -1 -1 0.29 0.00912959 0.0081003 119 20 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_073.v common 6.58 vpr 63.77 MiB -1 -1 0.12 20916 1 0.01 -1 -1 33296 -1 -1 21 30 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65300 30 32 317 269 1 202 83 17 17 289 -1 unnamed_device 25.2 MiB 2.47 1085 63.8 MiB 0.08 0.00 3.54502 -110.802 -3.54502 3.54502 0.75 0.000140585 0.000115191 0.0149251 0.0127021 34 2745 50 6.89349e+06 295971 618332. 2139.56 1.42 0.0758016 0.0650353 25762 151098 -1 2180 21 1657 2352 194487 41636 0 0 194487 41636 2352 1919 0 0 8634 7296 0 0 13278 10404 0 0 2352 2119 0 0 84251 9841 0 0 83620 10057 0 0 2352 0 0 695 711 772 6058 0 0 3.84514 3.84514 -133.949 -3.84514 0 0 787024. 2723.27 0.25 0.04 0.09 -1 -1 0.25 0.00976448 0.00862583 130 58 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_074.v common 8.15 vpr 63.73 MiB -1 -1 0.12 21256 1 0.01 -1 -1 33300 -1 -1 20 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65264 32 32 335 282 1 222 84 17 17 289 -1 unnamed_device 25.4 MiB 1.92 1246 63.7 MiB 0.06 0.00 3.03554 -108.938 -3.03554 3.03554 0.76 0.000148019 0.000121026 0.00936759 0.00780712 36 2848 26 6.89349e+06 281877 648988. 2245.63 3.41 0.0824405 0.0697236 26050 158493 -1 2496 20 1832 2484 213261 44912 0 0 213261 44912 2484 2001 0 0 8848 7143 0 0 13291 10333 0 0 2484 2268 0 0 93708 11703 0 0 92446 11464 0 0 2484 0 0 652 649 606 5695 0 0 3.17715 3.17715 -127.33 -3.17715 0 0 828058. 2865.25 0.27 0.05 0.10 -1 -1 0.27 0.0110883 0.00982835 138 62 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_075.v common 6.16 vpr 63.60 MiB -1 -1 0.12 20692 1 0.01 -1 -1 33132 -1 -1 31 31 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65128 31 32 293 230 1 175 94 17 17 289 -1 unnamed_device 25.2 MiB 0.60 1068 63.6 MiB 0.09 0.00 3.69462 -109.783 -3.69462 3.69462 0.80 0.000143476 0.000117975 0.0128732 0.0106002 32 2691 41 6.89349e+06 436909 586450. 2029.24 2.66 0.0773855 0.0659601 25474 144626 -1 2182 21 1375 2588 192544 43216 0 0 192544 43216 2588 1842 0 0 10004 8158 0 0 15255 11951 0 0 2588 2085 0 0 83832 9145 0 0 78277 10035 0 0 2588 0 0 1213 1583 1704 10934 0 0 3.6543 3.6543 -125.499 -3.6543 0 0 744469. 2576.02 0.33 0.04 0.13 -1 -1 0.33 0.00911838 0.0080247 129 -1 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_076.v common 6.57 vpr 63.75 MiB -1 -1 0.11 20576 1 0.01 -1 -1 33184 -1 -1 23 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65276 32 32 350 275 1 214 87 17 17 289 -1 unnamed_device 25.4 MiB 2.20 1013 63.7 MiB 0.08 0.00 3.78342 -121.532 -3.78342 3.78342 0.75 0.000165483 0.000135431 0.0138965 0.0115609 34 3420 26 6.89349e+06 324158 618332. 2139.56 1.60 0.080836 0.0689432 25762 151098 -1 2477 22 1878 2830 250198 55270 0 0 250198 55270 2830 2481 0 0 10238 8234 0 0 16555 12525 0 0 2830 2556 0 0 108226 15107 0 0 109519 14367 0 0 2830 0 0 952 1075 920 7681 0 0 4.0038 4.0038 -144.862 -4.0038 0 0 787024. 2723.27 0.25 0.06 0.09 -1 -1 0.25 0.0118571 0.0104798 148 31 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_077.v common 7.02 vpr 64.16 MiB -1 -1 0.11 20812 1 0.02 -1 -1 33368 -1 -1 27 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65704 32 32 385 308 1 244 91 17 17 289 -1 unnamed_device 25.6 MiB 1.80 1402 64.2 MiB 0.09 0.00 4.36021 -136.876 -4.36021 4.36021 0.87 0.000170835 0.000139592 0.0143753 0.0118721 34 3550 39 6.89349e+06 380534 618332. 2139.56 2.30 0.0898759 0.0776592 25762 151098 -1 2824 23 2170 3044 337671 70008 0 0 337671 70008 3044 2648 0 0 11559 9378 0 0 19562 14841 0 0 3044 2731 0 0 153031 20733 0 0 147431 19677 0 0 3044 0 0 874 1310 1069 8687 0 0 4.48485 4.48485 -159.562 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common 5.89 vpr 63.81 MiB -1 -1 0.10 20808 1 0.01 -1 -1 33372 -1 -1 21 30 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65344 30 32 272 232 1 176 83 17 17 289 -1 unnamed_device 25.2 MiB 1.79 961 63.8 MiB 0.18 0.00 3.29223 -102.912 -3.29223 3.29223 0.85 0.000132589 0.00010837 0.0330393 0.0208634 34 2401 35 6.89349e+06 295971 618332. 2139.56 1.26 0.077449 0.0591742 25762 151098 -1 1947 20 1312 1856 156277 34409 0 0 156277 34409 1856 1688 0 0 6814 5677 0 0 11695 8885 0 0 1856 1796 0 0 66240 8271 0 0 67816 8092 0 0 1856 0 0 544 556 495 4539 0 0 3.11191 3.11191 -111.113 -3.11191 0 0 787024. 2723.27 0.25 0.04 0.10 -1 -1 0.25 0.00905765 0.00789769 112 29 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_080.v common 7.17 vpr 64.05 MiB -1 -1 0.13 20780 1 0.01 -1 -1 33228 -1 -1 26 30 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65584 30 32 375 299 1 236 88 17 17 289 -1 unnamed_device 25.5 MiB 2.57 1248 64.0 MiB 0.07 0.00 4.46357 -133.845 -4.46357 4.46357 0.89 0.000172071 0.000141827 0.0111707 0.00933287 36 2727 22 6.89349e+06 366440 648988. 2245.63 1.51 0.0677862 0.0579492 26050 158493 -1 2385 21 1678 2406 182201 40214 0 0 182201 40214 2406 1970 0 0 8780 7156 0 0 12445 9881 0 0 2406 2045 0 0 75851 9915 0 0 80313 9247 0 0 2406 0 0 728 720 986 6348 0 0 4.44625 4.44625 -154.177 -4.44625 0 0 828058. 2865.25 0.27 0.05 0.15 -1 -1 0.27 0.0121012 0.0107391 162 58 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_081.v common 7.45 vpr 63.80 MiB -1 -1 0.12 20876 1 0.01 -1 -1 33384 -1 -1 23 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65328 32 32 340 270 1 204 87 17 17 289 -1 unnamed_device 25.4 MiB 1.21 987 63.8 MiB 0.05 0.00 4.12775 -120.614 -4.12775 4.12775 0.80 0.000183579 0.000152777 0.00898049 0.00751274 36 2759 23 6.89349e+06 324158 648988. 2245.63 3.48 0.081957 0.0702163 26050 158493 -1 2172 21 1323 2333 219280 48307 0 0 219280 48307 2333 1945 0 0 8873 7380 0 0 13912 10925 0 0 2333 2069 0 0 93518 12571 0 0 98311 13417 0 0 2333 0 0 1010 1868 1869 11032 0 0 3.8045 3.8045 -132.5 -3.8045 0 0 828058. 2865.25 0.28 0.05 0.10 -1 -1 0.28 0.0110889 0.00985536 139 31 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_082.v common 5.87 vpr 63.70 MiB -1 -1 0.11 20864 1 0.01 -1 -1 33208 -1 -1 23 31 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65224 31 32 340 275 1 211 86 17 17 289 -1 unnamed_device 25.3 MiB 1.78 1112 63.7 MiB 0.05 0.00 3.97284 -116.355 -3.97284 3.97284 0.77 0.000174936 0.000146184 0.00766883 0.00643642 34 2909 25 6.89349e+06 324158 618332. 2139.56 1.53 0.0567686 0.048872 25762 151098 -1 2282 19 1576 2362 158802 37729 0 0 158802 37729 2362 1894 0 0 8869 7340 0 0 13655 10765 0 0 2362 2117 0 0 67760 7575 0 0 63794 8038 0 0 2362 0 0 786 896 743 6791 0 0 4.21895 4.21895 -140.226 -4.21895 0 0 787024. 2723.27 0.24 0.04 0.10 -1 -1 0.24 0.01004 0.00891126 142 43 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_083.v common 6.68 vpr 64.23 MiB -1 -1 0.13 20836 1 0.01 -1 -1 33020 -1 -1 27 30 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65776 30 32 377 310 1 241 89 17 17 289 -1 unnamed_device 25.7 MiB 2.05 1409 64.2 MiB 0.09 0.00 3.74362 -115.714 -3.74362 3.74362 0.95 0.000176729 0.00014727 0.0149035 0.01254 36 3060 24 6.89349e+06 380534 648988. 2245.63 1.76 0.0781623 0.0671923 26050 158493 -1 2523 22 1829 2724 208303 44573 0 0 208303 44573 2724 2270 0 0 9771 7857 0 0 14483 11294 0 0 2724 2427 0 0 89531 10480 0 0 89070 10245 0 0 2724 0 0 895 1339 1227 8645 0 0 3.72599 3.72599 -133.694 -3.72599 0 0 828058. 2865.25 0.29 0.05 0.10 -1 -1 0.29 0.0126328 0.0111593 162 78 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_084.v common 7.71 vpr 64.02 MiB -1 -1 0.13 20808 1 0.01 -1 -1 33220 -1 -1 23 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65556 32 32 365 294 1 230 87 17 17 289 -1 unnamed_device 25.5 MiB 2.82 1168 64.0 MiB 0.08 0.00 4.53067 -134.342 -4.53067 4.53067 0.79 0.000179393 0.000150409 0.0129235 0.0108393 36 2953 42 6.89349e+06 324158 648988. 2245.63 2.00 0.0825353 0.0707424 26050 158493 -1 2548 21 1928 2848 206873 48257 0 0 206873 48257 2848 2343 0 0 10254 8414 0 0 14953 11750 0 0 2848 2574 0 0 88042 11181 0 0 87928 11995 0 0 2848 0 0 920 977 904 7735 0 0 4.40635 4.40635 -152.47 -4.40635 0 0 828058. 2865.25 0.32 0.12 0.10 -1 -1 0.32 0.0137077 0.0121825 155 54 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_085.v common 5.98 vpr 64.31 MiB -1 -1 0.12 20932 1 0.01 -1 -1 33160 -1 -1 30 29 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65852 29 32 378 310 1 247 91 17 17 289 -1 unnamed_device 25.9 MiB 1.72 1324 64.3 MiB 0.09 0.00 3.68595 -113.583 -3.68595 3.68595 0.74 0.000184925 0.000145305 0.0140955 0.0114942 34 3074 23 6.89349e+06 422815 618332. 2139.56 1.37 0.0597891 0.0511978 25762 151098 -1 2624 20 1768 2437 167984 38048 0 0 167984 38048 2437 1975 0 0 8889 7304 0 0 13360 10479 0 0 2437 2178 0 0 70588 8128 0 0 70273 7984 0 0 2437 0 0 669 840 635 6189 0 0 3.6001 3.6001 -126.879 -3.6001 0 0 787024. 2723.27 0.27 0.04 0.10 -1 -1 0.27 0.0122598 0.0109144 166 79 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_086.v common 5.64 vpr 63.29 MiB -1 -1 0.11 20452 1 0.00 -1 -1 33136 -1 -1 17 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64808 32 32 243 205 1 149 81 17 17 289 -1 unnamed_device 24.9 MiB 0.50 856 63.3 MiB 0.05 0.00 3.26403 -101.059 -3.26403 3.26403 0.77 0.000124344 0.000101713 0.00752316 0.006241 34 1906 19 6.89349e+06 239595 618332. 2139.56 2.57 0.0573973 0.048983 25762 151098 -1 1668 18 898 1450 111430 25161 0 0 111430 25161 1450 1165 0 0 5421 4409 0 0 8270 6575 0 0 1450 1233 0 0 48178 5753 0 0 46661 6026 0 0 1450 0 0 552 556 583 4425 0 0 2.89916 2.89916 -109.296 -2.89916 0 0 787024. 2723.27 0.25 0.03 0.09 -1 -1 0.25 0.00706147 0.0062681 96 -1 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_087.v common 6.66 vpr 64.00 MiB -1 -1 0.12 21096 1 0.01 -1 -1 33184 -1 -1 25 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65532 32 32 373 302 1 241 89 17 17 289 -1 unnamed_device 25.4 MiB 1.59 1340 64.0 MiB 0.09 0.00 4.4438 -137.071 -4.4438 4.4438 0.77 0.000166153 0.00013626 0.0158815 0.0132433 34 3142 32 6.89349e+06 352346 618332. 2139.56 2.08 0.0791277 0.0680764 25762 151098 -1 2584 21 1815 2507 213453 45838 0 0 213453 45838 2507 2207 0 0 9159 7343 0 0 15237 11768 0 0 2507 2307 0 0 92589 10927 0 0 91454 11286 0 0 2507 0 0 692 684 805 6488 0 0 4.47168 4.47168 -158.42 -4.47168 0 0 787024. 2723.27 0.26 0.05 0.12 -1 -1 0.26 0.0119838 0.0106238 156 62 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_088.v common 9.33 vpr 64.03 MiB -1 -1 0.11 21188 1 0.01 -1 -1 33180 -1 -1 25 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65568 32 32 397 314 1 256 89 17 17 289 -1 unnamed_device 25.6 MiB 3.00 1296 64.0 MiB 0.06 0.00 4.41647 -143.96 -4.41647 4.41647 0.80 0.000183614 0.000151168 0.0100959 0.00851222 36 3363 29 6.89349e+06 352346 648988. 2245.63 3.64 0.096918 0.0816019 26050 158493 -1 2915 22 2248 3276 277372 59299 0 0 277372 59299 3276 2806 0 0 11767 9699 0 0 17876 14027 0 0 3276 2909 0 0 122684 14329 0 0 118493 15529 0 0 3276 0 0 1028 1040 1293 8781 0 0 4.81268 4.81268 -171.588 -4.81268 0 0 828058. 2865.25 0.25 0.06 0.10 -1 -1 0.25 0.0132232 0.0117157 171 62 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_089.v common 6.31 vpr 63.40 MiB -1 -1 0.11 20648 1 0.01 -1 -1 33380 -1 -1 18 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64924 32 32 269 231 1 172 82 17 17 289 -1 unnamed_device 24.9 MiB 2.59 946 63.4 MiB 0.06 0.00 3.14102 -93.6681 -3.14102 3.14102 0.71 0.000139623 0.000116501 0.01061 0.00885027 34 2116 25 6.89349e+06 253689 618332. 2139.56 1.17 0.0506105 0.0431005 25762 151098 -1 1813 19 916 1254 92025 22482 0 0 92025 22482 1254 1127 0 0 4852 4029 0 0 7246 5929 0 0 1254 1161 0 0 38528 5344 0 0 38891 4892 0 0 1254 0 0 338 341 318 2949 0 0 2.8954 2.8954 -106.854 -2.8954 0 0 787024. 2723.27 0.26 0.03 0.09 -1 -1 0.26 0.00856051 0.00764241 108 26 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_090.v common 4.23 vpr 63.35 MiB -1 -1 0.10 20456 1 0.01 -1 -1 33308 -1 -1 20 31 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64868 31 32 245 205 1 153 83 17 17 289 -1 unnamed_device 24.9 MiB 0.56 814 63.3 MiB 0.05 0.00 3.20583 -100.243 -3.20583 3.20583 1.02 0.000122111 0.000100342 0.00680198 0.00565412 32 2104 20 6.89349e+06 281877 586450. 2029.24 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x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64996 27 32 255 219 1 162 79 17 17 289 -1 unnamed_device 25.0 MiB 1.56 801 63.5 MiB 0.06 0.00 3.41829 -92.4304 -3.41829 3.41829 0.75 0.000132115 0.00010926 0.0108633 0.00895768 34 1955 19 6.89349e+06 281877 618332. 2139.56 1.15 0.0397692 0.0336207 25762 151098 -1 1554 16 866 1216 82901 20145 0 0 82901 20145 1216 993 0 0 4728 3887 0 0 6779 5586 0 0 1216 1048 0 0 34040 4541 0 0 34922 4090 0 0 1216 0 0 350 481 377 3318 0 0 3.6904 3.6904 -110.092 -3.6904 0 0 787024. 2723.27 0.27 0.03 0.10 -1 -1 0.27 0.00801908 0.00726936 106 26 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_096.v common 8.08 vpr 64.50 MiB -1 -1 0.12 21064 1 0.01 -1 -1 33236 -1 -1 27 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 66044 32 32 421 327 1 271 91 17 17 289 -1 unnamed_device 25.7 MiB 2.70 1526 64.5 MiB 0.12 0.00 3.70801 -120.691 -3.70801 3.70801 0.80 0.000205732 0.000171643 0.019935 0.0167516 34 4271 39 6.89349e+06 380534 618332. 2139.56 2.51 0.0881686 0.0717829 25762 151098 -1 3333 20 2116 3285 269752 59668 0 0 269752 59668 3285 2801 0 0 12158 10031 0 0 19079 14826 0 0 3285 2890 0 0 114121 15163 0 0 117824 13957 0 0 3285 0 0 1169 1601 1342 10295 0 0 4.74835 4.74835 -153.053 -4.74835 0 0 787024. 2723.27 0.27 0.07 0.10 -1 -1 0.27 0.0148213 0.0132563 185 62 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_097.v common 6.39 vpr 64.13 MiB -1 -1 0.12 21224 1 0.01 -1 -1 33280 -1 -1 24 31 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65672 31 32 365 296 1 233 87 17 17 289 -1 unnamed_device 25.7 MiB 1.76 1045 64.1 MiB 0.09 0.00 4.58387 -130.323 -4.58387 4.58387 0.75 0.000161634 0.000132046 0.0168473 0.0141003 34 3296 27 6.89349e+06 338252 618332. 2139.56 1.76 0.0852274 0.0741628 25762 151098 -1 2411 23 2000 2885 217665 50475 0 0 217665 50475 2885 2564 0 0 10751 8763 0 0 16377 12694 0 0 2885 2621 0 0 96572 11652 0 0 88195 12181 0 0 2885 0 0 885 1100 1082 8322 0 0 4.65895 4.65895 -151.627 -4.65895 0 0 787024. 2723.27 0.25 0.05 0.18 -1 -1 0.25 0.0120094 0.0105719 155 60 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_098.v common 6.18 vpr 63.85 MiB -1 -1 0.11 20844 1 0.01 -1 -1 33188 -1 -1 21 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65380 32 32 331 280 1 221 85 17 17 289 -1 unnamed_device 25.5 MiB 1.86 1152 63.8 MiB 0.07 0.00 3.42429 -116.689 -3.42429 3.42429 0.76 0.000152104 0.000124543 0.0147167 0.0128623 34 2899 25 6.89349e+06 295971 618332. 2139.56 1.43 0.054298 0.0468685 25762 151098 -1 2525 20 1674 2186 181245 39851 0 0 181245 39851 2186 1989 0 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6.17 vpr 63.95 MiB -1 -1 0.11 20748 1 0.01 -1 -1 33240 -1 -1 24 30 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65484 30 32 325 268 1 210 86 17 17 289 -1 unnamed_device 25.6 MiB 1.76 1234 63.9 MiB 0.08 0.00 3.48179 -99.3124 -3.48179 3.48179 0.76 0.00015298 0.000125574 0.0132732 0.011022 34 3015 24 6.89349e+06 338252 618332. 2139.56 1.54 0.0624183 0.0530732 25762 151098 -1 2360 15 1255 2027 135910 31192 0 0 135910 31192 2027 1454 0 0 7516 6137 0 0 10695 8566 0 0 2027 1647 0 0 57763 6501 0 0 55882 6887 0 0 2027 0 0 772 792 879 6558 0 0 3.6096 3.6096 -117.325 -3.6096 0 0 787024. 2723.27 0.33 0.03 0.10 -1 -1 0.33 0.00954832 0.00869296 140 46 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_102.v common 8.75 vpr 63.89 MiB -1 -1 0.10 20800 1 0.01 -1 -1 32936 -1 -1 22 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65428 32 32 350 275 1 215 86 17 17 289 -1 unnamed_device 25.5 MiB 2.29 1282 63.9 MiB 0.09 0.00 3.88598 -128.15 -3.88598 3.88598 0.73 0.000166139 0.000137224 0.0167499 0.0141145 36 3065 23 6.89349e+06 310065 648988. 2245.63 3.47 0.0920493 0.0785002 26050 158493 -1 2588 19 1602 2520 202168 43515 0 0 202168 43515 2520 2059 0 0 9140 7501 0 0 13541 10541 0 0 2520 2225 0 0 85706 11202 0 0 88741 9987 0 0 2520 0 0 918 984 872 7162 0 0 3.87409 3.87409 -143.574 -3.87409 0 0 828058. 2865.25 0.28 0.05 0.10 -1 -1 0.28 0.0105133 0.00934336 148 31 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_103.v common 8.51 vpr 64.11 MiB -1 -1 0.11 20728 1 0.02 -1 -1 33400 -1 -1 26 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65648 32 32 386 307 1 246 90 17 17 289 -1 unnamed_device 25.6 MiB 2.47 1373 64.1 MiB 0.10 0.00 3.31614 -114.102 -3.31614 3.31614 1.01 0.000170849 0.00014053 0.0152393 0.0126751 38 2785 22 6.89349e+06 366440 678818. 2348.85 3.02 0.0987102 0.0841207 26626 170182 -1 2406 17 1473 2127 141266 31314 0 0 141266 31314 2127 1705 0 0 7287 5896 0 0 9941 8072 0 0 2127 1815 0 0 61505 6717 0 0 58279 7109 0 0 2127 0 0 654 757 702 5840 0 0 3.23035 3.23035 -127.132 -3.23035 0 0 902133. 3121.57 0.30 0.04 0.11 -1 -1 0.30 0.0106265 0.00947699 167 59 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_104.v common 5.57 vpr 63.62 MiB -1 -1 0.11 20500 1 0.01 -1 -1 33188 -1 -1 20 29 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65144 29 32 269 229 1 173 81 17 17 289 -1 unnamed_device 25.0 MiB 1.20 748 63.6 MiB 0.05 0.00 3.40033 -100.227 -3.40033 3.40033 0.79 0.000127008 0.000103629 0.00925811 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mult_108.v common 5.80 vpr 63.69 MiB -1 -1 0.11 20464 1 0.01 -1 -1 33132 -1 -1 18 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65216 32 32 278 238 1 182 82 17 17 289 -1 unnamed_device 25.3 MiB 1.92 936 63.7 MiB 0.05 0.00 3.26703 -103.618 -3.26703 3.26703 0.74 0.000130853 0.00010695 0.00705891 0.00590836 34 2205 25 6.89349e+06 253689 618332. 2139.56 1.17 0.0482121 0.0411655 25762 151098 -1 1892 20 1309 1867 140275 32024 0 0 140275 32024 1867 1561 0 0 6851 5590 0 0 10655 8296 0 0 1867 1679 0 0 60115 7382 0 0 58920 7516 0 0 1867 0 0 558 550 611 4702 0 0 3.38931 3.38931 -121.952 -3.38931 0 0 787024. 2723.27 0.29 0.04 0.09 -1 -1 0.29 0.00903683 0.00776061 114 31 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_109.v common 5.77 vpr 63.81 MiB -1 -1 0.13 20984 1 0.02 -1 -1 33328 -1 -1 26 31 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65344 31 32 373 300 1 236 89 17 17 289 -1 unnamed_device 25.2 MiB 1.59 1199 63.8 MiB 0.07 0.00 3.60497 -116.633 -3.60497 3.60497 0.73 0.000197163 0.000165387 0.0108307 0.00905992 34 3272 23 6.89349e+06 366440 618332. 2139.56 1.38 0.067381 0.0575907 25762 151098 -1 2593 21 2167 2971 249063 54906 0 0 249063 54906 2971 2588 0 0 10932 8980 0 0 16726 12993 0 0 2971 2682 0 0 109402 13354 0 0 106061 14309 0 0 2971 0 0 804 969 1097 7759 0 0 3.826 3.826 -140.434 -3.826 0 0 787024. 2723.27 0.27 0.06 0.09 -1 -1 0.27 0.012027 0.0106466 160 60 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_110.v common 5.35 vpr 63.43 MiB -1 -1 0.11 20480 1 0.01 -1 -1 33236 -1 -1 17 31 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64948 31 32 265 230 1 175 80 17 17 289 -1 unnamed_device 24.8 MiB 1.77 871 63.4 MiB 0.05 0.00 2.93195 -93.9974 -2.93195 2.93195 0.80 0.000126179 0.000103352 0.00952398 0.00800527 30 2182 24 6.89349e+06 239595 556674. 1926.21 0.77 0.0346627 0.0295708 25186 138497 -1 1939 22 1246 1734 124686 27774 0 0 124686 27774 1734 1500 0 0 6016 4758 0 0 8425 6751 0 0 1734 1554 0 0 52374 6672 0 0 54403 6539 0 0 1734 0 0 488 467 375 4040 0 0 2.83701 2.83701 -109.839 -2.83701 0 0 706193. 2443.58 0.30 0.07 0.09 -1 -1 0.30 0.0154167 0.0143482 108 30 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_111.v common 5.96 vpr 64.02 MiB -1 -1 0.11 21080 1 0.01 -1 -1 33148 -1 -1 22 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65556 32 32 349 286 1 221 86 17 17 289 -1 unnamed_device 25.5 MiB 1.76 1253 64.0 MiB 0.08 0.00 3.27699 -103.618 -3.27699 3.27699 0.77 0.000169805 0.000139849 0.0140811 0.0117405 34 2957 21 6.89349e+06 310065 618332. 2139.56 1.40 0.0560703 0.0479333 25762 151098 -1 2483 19 1396 2007 150789 33901 0 0 150789 33901 2007 1689 0 0 7473 6039 0 0 11400 8866 0 0 2007 1762 0 0 63483 7962 0 0 64419 7583 0 0 2007 0 0 611 835 824 6301 0 0 3.6406 3.6406 -125.305 -3.6406 0 0 787024. 2723.27 0.35 0.14 0.10 -1 -1 0.35 0.0663648 0.065005 146 54 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_112.v common 8.10 vpr 64.17 MiB -1 -1 0.12 20784 1 0.02 -1 -1 33276 -1 -1 26 31 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65712 31 32 396 325 1 259 89 17 17 289 -1 unnamed_device 25.8 MiB 1.90 1336 64.2 MiB 0.10 0.00 3.92778 -127.361 -3.92778 3.92778 0.77 0.000240246 0.00020252 0.0173608 0.0146326 36 3183 24 6.89349e+06 366440 648988. 2245.63 3.40 0.096953 0.0827635 26050 158493 -1 2737 21 2324 3325 240758 53532 0 0 240758 53532 3325 2779 0 0 11713 9543 0 0 17558 13549 0 0 3325 2957 0 0 103066 12648 0 0 101771 12056 0 0 3325 0 0 1001 1288 1152 9266 0 0 4.03459 4.03459 -151.259 -4.03459 0 0 828058. 2865.25 0.26 0.05 0.10 -1 -1 0.26 0.0115106 0.0100857 170 87 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_113.v common 6.49 vpr 63.79 MiB -1 -1 0.12 20752 1 0.01 -1 -1 33176 -1 -1 18 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65324 32 32 303 262 1 200 82 17 17 289 -1 unnamed_device 25.2 MiB 2.58 1074 63.8 MiB 0.05 0.00 3.0513 -97.8122 -3.0513 3.0513 0.76 0.000142346 0.000116328 0.00825911 0.00687436 34 2606 24 6.89349e+06 253689 618332. 2139.56 1.27 0.0427513 0.0363296 25762 151098 -1 2080 24 1639 2273 155679 35373 0 0 155679 35373 2273 1830 0 0 8173 6690 0 0 12392 9560 0 0 2273 1880 0 0 66359 7594 0 0 64209 7819 0 0 2273 0 0 634 667 511 5377 0 0 2.90926 2.90926 -112.254 -2.90926 0 0 787024. 2723.27 0.26 0.04 0.09 -1 -1 0.26 0.0108329 0.00953203 124 54 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_114.v common 5.07 vpr 63.63 MiB -1 -1 0.10 20400 1 0.00 -1 -1 33272 -1 -1 18 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65156 32 32 290 244 1 177 82 17 17 289 -1 unnamed_device 25.2 MiB 1.03 871 63.6 MiB 0.05 0.00 3.24503 -100.934 -3.24503 3.24503 0.78 0.000142328 0.000115607 0.00891834 0.00749636 34 2523 43 6.89349e+06 253689 618332. 2139.56 1.52 0.0511318 0.0435664 25762 151098 -1 1942 22 1320 1987 148820 36920 0 0 148820 36920 1987 1741 0 0 7406 6142 0 0 11996 9269 0 0 1987 1825 0 0 61858 9119 0 0 63586 8824 0 0 1987 0 0 667 614 619 5221 0 0 3.00505 3.00505 -113.473 -3.00505 0 0 787024. 2723.27 0.28 0.04 0.10 -1 -1 0.28 0.00986064 0.00864752 115 31 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_115.v common 6.72 vpr 63.89 MiB -1 -1 0.11 20892 1 0.01 -1 -1 33196 -1 -1 22 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65428 32 32 318 257 1 198 86 17 17 289 -1 unnamed_device 25.3 MiB 1.89 1058 63.9 MiB 0.08 0.00 3.98738 -115.138 -3.98738 3.98738 0.86 0.000149979 0.000123415 0.0140767 0.011943 34 2683 20 6.89349e+06 310065 618332. 2139.56 1.85 0.0747182 0.0643152 25762 151098 -1 2209 18 1345 1900 134344 31054 0 0 134344 31054 1900 1649 0 0 7148 5788 0 0 10319 8360 0 0 1900 1759 0 0 55047 7277 0 0 58030 6221 0 0 1900 0 0 555 572 547 4694 0 0 3.77296 3.77296 -130.903 -3.77296 0 0 787024. 2723.27 0.37 0.03 0.20 -1 -1 0.37 0.00880754 0.00782864 133 27 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_116.v common 6.43 vpr 63.64 MiB -1 -1 0.11 20832 1 0.01 -1 -1 33220 -1 -1 25 29 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65172 29 32 324 268 1 207 86 17 17 289 -1 unnamed_device 25.1 MiB 2.22 1151 63.6 MiB 0.08 0.00 3.15468 -91.5834 -3.15468 3.15468 0.78 0.00019197 0.000162877 0.013325 0.0112372 34 2532 22 6.89349e+06 352346 618332. 2139.56 1.45 0.0605062 0.0531408 25762 151098 -1 2165 20 1197 1741 124479 28433 0 0 124479 28433 1741 1411 0 0 6516 5182 0 0 9774 7828 0 0 1741 1453 0 0 52705 6410 0 0 52002 6149 0 0 1741 0 0 544 753 754 5574 0 0 3.08015 3.08015 -106.01 -3.08015 0 0 787024. 2723.27 0.30 0.04 0.16 -1 -1 0.30 0.0119054 0.0106731 138 49 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_117.v common 8.62 vpr 63.88 MiB -1 -1 0.12 20780 1 0.01 -1 -1 33128 -1 -1 24 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65416 32 32 393 312 1 243 88 17 17 289 -1 unnamed_device 25.5 MiB 1.96 1226 63.9 MiB 0.08 0.00 4.55604 -146.357 -4.55604 4.55604 0.90 0.000181174 0.000149471 0.0128736 0.010552 36 3116 36 6.89349e+06 338252 648988. 2245.63 3.57 0.119515 0.0969034 26050 158493 -1 2653 22 1983 3100 226456 52023 0 0 226456 52023 3100 2456 0 0 10953 9204 0 0 16651 12906 0 0 3100 2588 0 0 94504 12014 0 0 98148 12855 0 0 3100 0 0 1117 1246 1592 10063 0 0 4.56459 4.56459 -167.653 -4.56459 0 0 828058. 2865.25 0.31 0.05 0.12 -1 -1 0.31 0.0149074 0.0134295 166 62 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_118.v common 3.95 vpr 63.31 MiB -1 -1 0.10 20472 1 0.01 -1 -1 33052 -1 -1 17 31 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64832 31 32 229 197 1 143 80 17 17 289 -1 unnamed_device 24.9 MiB 0.52 760 63.3 MiB 0.05 0.00 2.85355 -89.4893 -2.85355 2.85355 0.84 0.000116839 9.5085e-05 0.009959 0.00843289 30 1852 19 6.89349e+06 239595 556674. 1926.21 0.86 0.0300999 0.0257822 25186 138497 -1 1472 21 679 1045 64018 15169 0 0 64018 15169 1045 788 0 0 3705 2936 0 0 5094 4236 0 0 1045 814 0 0 26961 3129 0 0 26168 3266 0 0 1045 0 0 366 359 263 2887 0 0 2.55636 2.55636 -98.7819 -2.55636 0 0 706193. 2443.58 0.26 0.02 0.10 -1 -1 0.26 0.00767262 0.00677847 92 -1 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_119.v common 6.67 vpr 64.32 MiB -1 -1 0.12 20860 1 0.02 -1 -1 33116 -1 -1 27 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65860 32 32 412 334 1 269 91 17 17 289 -1 unnamed_device 25.6 MiB 1.85 1392 64.3 MiB 0.08 0.00 4.61883 -139.905 -4.61883 4.61883 0.92 0.000188303 0.000150016 0.0133674 0.0111907 36 3350 25 6.89349e+06 380534 648988. 2245.63 1.99 0.0769336 0.0659785 26050 158493 -1 2633 22 1891 2629 198179 43197 0 0 198179 43197 2629 2247 0 0 9336 7527 0 0 13999 10982 0 0 2629 2455 0 0 88622 9585 0 0 80964 10401 0 0 2629 0 0 738 736 850 6743 0 0 4.83884 4.83884 -168.537 -4.83884 0 0 828058. 2865.25 0.26 0.05 0.10 -1 -1 0.26 0.0124565 0.0109029 175 87 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_120.v common 6.70 vpr 64.17 MiB -1 -1 0.12 20788 1 0.01 -1 -1 33132 -1 -1 23 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65712 32 32 376 318 1 259 87 17 17 289 -1 unnamed_device 25.6 MiB 2.27 1317 64.2 MiB 0.09 0.00 3.86068 -135.313 -3.86068 3.86068 0.75 0.0001618 0.000132946 0.0158569 0.013239 36 3171 25 6.89349e+06 324158 648988. 2245.63 1.82 0.0747229 0.064275 26050 158493 -1 2652 24 2582 3249 286315 60039 0 0 286315 60039 3249 2956 0 0 11559 9394 0 0 18426 14001 0 0 3249 3153 0 0 129263 14858 0 0 120569 15677 0 0 3249 0 0 667 706 636 6618 0 0 4.2008 4.2008 -161.842 -4.2008 0 0 828058. 2865.25 0.28 0.07 0.10 -1 -1 0.28 0.0141396 0.0125454 160 93 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_121.v common 6.23 vpr 63.81 MiB -1 -1 0.12 20780 1 0.01 -1 -1 33084 -1 -1 22 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65340 32 32 360 293 1 227 86 17 17 289 -1 unnamed_device 25.3 MiB 1.77 1278 63.8 MiB 0.10 0.00 3.34918 -108.188 -3.34918 3.34918 0.86 0.000191052 0.000159084 0.0165783 0.013755 34 3129 24 6.89349e+06 310065 618332. 2139.56 1.67 0.0774299 0.0682021 25762 151098 -1 2512 20 1463 1964 163558 35555 0 0 163558 35555 1964 1713 0 0 7447 6060 0 0 11274 9103 0 0 1964 1757 0 0 72633 8469 0 0 68276 8453 0 0 1964 0 0 501 753 785 5619 0 0 3.42436 3.42436 -127.422 -3.42436 0 0 787024. 2723.27 0.26 0.04 0.10 -1 -1 0.26 0.0111906 0.00993261 152 57 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_122.v common 7.25 vpr 64.05 MiB -1 -1 0.12 21052 1 0.02 -1 -1 33384 -1 -1 26 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65584 32 32 396 299 1 241 90 17 17 289 -1 unnamed_device 25.7 MiB 2.48 1239 64.0 MiB 0.12 0.00 4.8408 -145.59 -4.8408 4.8408 0.83 0.000226664 0.000191592 0.0171914 0.0144646 34 3525 44 6.89349e+06 366440 618332. 2139.56 1.92 0.082803 0.0707343 25762 151098 -1 2754 23 2278 3577 289843 62792 0 0 289843 62792 3577 2994 0 0 13104 10636 0 0 20413 15688 0 0 3577 3103 0 0 130333 13978 0 0 118839 16393 0 0 3577 0 0 1299 2068 1841 12187 0 0 4.7712 4.7712 -159.816 -4.7712 0 0 787024. 2723.27 0.25 0.06 0.09 -1 -1 0.25 0.013138 0.0115802 172 31 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_123.v common 6.40 vpr 63.33 MiB -1 -1 0.12 20452 1 0.01 -1 -1 33292 -1 -1 15 30 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64852 30 32 224 207 1 138 77 17 17 289 -1 unnamed_device 25.0 MiB 0.88 755 63.3 MiB 0.04 0.00 2.51156 -81.974 -2.51156 2.51156 0.71 0.000107689 8.7527e-05 0.00754027 0.00622645 36 1687 19 6.89349e+06 211408 648988. 2245.63 2.92 0.048961 0.0412807 26050 158493 -1 1505 20 813 1087 91520 19704 0 0 91520 19704 1087 959 0 0 3898 3121 0 0 5901 4664 0 0 1087 1028 0 0 38660 5313 0 0 40887 4619 0 0 1087 0 0 274 224 271 2404 0 0 2.19217 2.19217 -91.1802 -2.19217 0 0 828058. 2865.25 0.31 0.03 0.10 -1 -1 0.31 0.00708385 0.00623608 82 29 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_124.v common 5.22 vpr 63.72 MiB -1 -1 0.12 20900 1 0.01 -1 -1 33148 -1 -1 20 30 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65248 30 32 286 239 1 176 82 17 17 289 -1 unnamed_device 25.3 MiB 1.43 943 63.7 MiB 0.06 0.00 3.72389 -116.987 -3.72389 3.72389 0.72 0.000144483 0.000119941 0.0109651 0.00919193 34 2196 23 6.89349e+06 281877 618332. 2139.56 1.23 0.059723 0.0512063 25762 151098 -1 1914 21 1122 1660 139748 30063 0 0 139748 30063 1660 1265 0 0 6396 5218 0 0 9428 7643 0 0 1660 1319 0 0 58518 8002 0 0 62086 6616 0 0 1660 0 0 538 531 743 4816 0 0 3.5289 3.5289 -129.793 -3.5289 0 0 787024. 2723.27 0.27 0.04 0.09 -1 -1 0.27 0.0098242 0.0087287 119 29 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_125.v common 6.16 vpr 63.64 MiB -1 -1 0.11 20212 1 0.01 -1 -1 33112 -1 -1 18 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65168 32 32 296 247 1 187 82 17 17 289 -1 unnamed_device 25.2 MiB 1.76 992 63.6 MiB 0.08 0.00 3.40529 -111.019 -3.40529 3.40529 0.77 0.000159207 0.000131191 0.0132845 0.0110569 34 2949 37 6.89349e+06 253689 618332. 2139.56 1.82 0.0782011 0.0669903 25762 151098 -1 2250 22 1568 2750 219168 49666 0 0 219168 49666 2750 2135 0 0 10060 8486 0 0 16808 12739 0 0 2750 2331 0 0 93267 12165 0 0 93533 11810 0 0 2750 0 0 1182 1475 1285 10102 0 0 3.8587 3.8587 -141.257 -3.8587 0 0 787024. 2723.27 0.30 0.06 0.11 -1 -1 0.30 0.0130467 0.0114555 120 31 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_126.v common 5.74 vpr 63.38 MiB -1 -1 0.10 20516 1 0.01 -1 -1 33276 -1 -1 21 25 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64904 25 32 216 194 1 138 78 17 17 289 -1 unnamed_device 25.0 MiB 1.34 634 63.4 MiB 0.04 0.00 2.8908 -71.862 -2.8908 2.8908 0.79 0.000110668 9.0512e-05 0.00854883 0.00708055 34 1657 29 6.89349e+06 295971 618332. 2139.56 1.58 0.0502407 0.0432626 25762 151098 -1 1372 20 836 1280 90673 22141 0 0 90673 22141 1280 1090 0 0 4914 4056 0 0 7844 6154 0 0 1280 1176 0 0 38014 5003 0 0 37341 4662 0 0 1280 0 0 444 490 413 3841 0 0 2.82696 2.82696 -80.5452 -2.82696 0 0 787024. 2723.27 0.36 0.03 0.14 -1 -1 0.36 0.00923161 0.00835121 92 19 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_127.v common 7.78 vpr 63.84 MiB -1 -1 0.12 20936 1 0.01 -1 -1 33120 -1 -1 23 32 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65376 32 32 376 307 1 242 87 17 17 289 -1 unnamed_device 25.3 MiB 2.30 1431 63.8 MiB 0.10 0.00 3.47055 -111.327 -3.47055 3.47055 0.81 0.000213163 0.000178519 0.0189925 0.015959 34 3850 48 6.89349e+06 324158 618332. 2139.56 2.83 0.128839 0.113083 25762 151098 -1 3069 21 2038 3058 254336 54332 0 0 254336 54332 3058 2426 0 0 11134 9136 0 0 16844 13132 0 0 3058 2627 0 0 108889 14212 0 0 111353 12799 0 0 3058 0 0 1020 1250 1241 8763 0 0 3.83326 3.83326 -137.965 -3.83326 0 0 787024. 2723.27 0.28 0.06 0.10 -1 -1 0.28 0.0126458 0.0112384 161 69 -1 -1 -1 -1 + fixed_k6_frac_uripple_N8_22nm.xml mult_128.v common 7.50 vpr 64.20 MiB -1 -1 0.13 20528 1 0.02 -1 -1 33272 -1 -1 29 31 0 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65744 31 32 409 331 1 264 92 17 17 289 -1 unnamed_device 25.8 MiB 2.23 1295 64.2 MiB 0.10 0.00 3.87458 -125.043 -3.87458 3.87458 1.05 0.00019259 0.000158188 0.0164648 0.0138378 34 3712 39 6.89349e+06 408721 618332. 2139.56 2.19 0.115834 0.100944 25762 151098 -1 2763 23 2277 3107 256096 55691 0 0 256096 55691 3107 2756 0 0 11352 9062 0 0 17514 13582 0 0 3107 2858 0 0 111794 13969 0 0 109222 13464 0 0 3107 0 0 830 947 865 7653 0 0 4.45449 4.45449 -157.419 -4.45449 0 0 787024. 2723.27 0.28 0.06 0.14 -1 -1 0.28 0.0136894 0.0121077 179 86 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vpr_verify_rr_graph/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vpr_verify_rr_graph/config/config.txt index ee4179df26b..a8d272a09a9 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vpr_verify_rr_graph/config/config.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/vpr_verify_rr_graph/config/config.txt @@ -29,4 +29,4 @@ qor_parse_file=qor_rr_graph.txt pass_requirements_file=pass_requirements_verify_rr_graph.txt # Script parameters -script_params = -verify_rr_graph --route_chan_width 130 +script_params = -verify_rr_graph --route_chan_width 140 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor/config/golden_results.txt index 6d28eb94d08..a8de4ac42cf 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor/config/golden_results.txt @@ -1,21 +1,21 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length - k6_frac_N10_mem32K_40nm.xml arm_core.v common 411.47 vpr 244.16 MiB -1 -1 28.89 125340 25 75.06 -1 -1 71320 -1 -1 880 133 24 0 success 574ed3d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-09T03:32:19 gh-actions-runner-vtr-auto-spawned7 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 250024 133 179 13858 14037 1 6950 1216 37 37 1369 clb auto 138.2 MiB 26.00 125912 172.9 MiB 17.32 0.14 16.6345 -185462 -16.6345 16.6345 6.08 0.0347921 0.0305185 4.55656 3.67723 120 188737 48 7.54166e+07 6.05797e+07 1.02918e+07 7517.79 215.74 21.36 17.6069 172826 16 33131 131561 40775806 8744541 18.8174 18.8174 -203586 -18.8174 -8.09186 -0.296573 1.29213e+07 9438.48 5.89 16.69 2.48407 2.15231 8205 9816 -1 -1 -1 -1 - k6_frac_N10_mem32K_40nm.xml bgm.v common 91.64 yosys 239.27 MiB -1 -1 49.87 245012 13 13.51 -1 -1 50988 -1 -1 273 257 0 0 success 574ed3d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-09T03:32:19 gh-actions-runner-vtr-auto-spawned7 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 97796 257 32 5001 5033 1 2784 562 22 22 484 clb auto 58.5 MiB 4.03 18468 95.5 MiB 2.45 0.03 7.27791 -3408.66 -7.27791 7.27791 1.72 0.00724364 0.0061415 0.817001 0.696131 58 31421 42 2.50602e+07 1.47131e+07 1.81652e+06 3753.13 9.51 3.73585 3.22023 28321 15 10985 34177 991919 195896 8.72272 8.72272 -3911.98 -8.72272 0 0 2.31597e+06 4785.06 1.08 0.85 0.576306 0.522008 2540 2772 -1 -1 -1 -1 - k6_frac_N10_mem32K_40nm.xml blob_merge.v common 113.87 yosys 302.68 MiB -1 -1 18.08 309944 7 20.28 -1 -1 60820 -1 -1 561 36 0 0 success 574ed3d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-09T03:32:19 gh-actions-runner-vtr-auto-spawned7 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 125712 36 100 6697 6797 1 3131 697 30 30 900 clb auto 82.9 MiB 4.80 43230 119.6 MiB 6.57 0.06 5.06388 -1985.85 -5.06388 5.06388 4.02 0.0231138 0.0190123 2.50176 2.10122 66 68872 28 4.8774e+07 3.02345e+07 3.99156e+06 4435.07 42.43 8.04038 6.77078 63697 16 15891 71869 3350299 434879 5.61743 5.61743 -2244.81 -5.61743 0 0 4.95347e+06 5503.86 2.17 2.16 1.2004 1.07155 4768 6047 -1 -1 -1 -1 - k6_frac_N10_mem32K_40nm.xml boundtop.v common 22.39 vpr 66.28 MiB -1 -1 15.41 34956 4 0.22 -1 -1 37512 -1 -1 42 195 1 0 success 574ed3d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-09T03:32:19 gh-actions-runner-vtr-auto-spawned7 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 67872 195 193 1088 1281 1 593 431 15 15 225 io auto 28.5 MiB 0.39 2756 66.3 MiB 0.57 0.01 2.15453 -972.998 -2.15453 2.15453 0.68 0.00227575 0.00204263 0.234782 0.214742 36 6242 49 1.03862e+07 2.81155e+06 520410. 2312.93 2.60 1.04464 0.963012 5375 12 1678 2450 231480 60380 2.77946 2.77946 -1166.76 -2.77946 -0.349489 -0.177205 643451. 2859.78 0.23 0.16 0.0970223 0.0917376 347 525 -1 -1 -1 -1 - k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common 2.99 vpr 62.59 MiB -1 -1 0.29 21472 3 0.07 -1 -1 36436 -1 -1 68 99 1 0 success 574ed3d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-09T03:32:19 gh-actions-runner-vtr-auto-spawned7 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 64092 99 130 343 473 1 225 298 12 12 144 clb auto 24.5 MiB 0.15 576 62.6 MiB 0.17 0.00 1.62851 -110.768 -1.62851 1.62851 0.34 0.000592966 0.000532115 0.0489994 0.0441021 40 1369 8 5.66058e+06 4.21279e+06 333335. 2314.82 0.71 0.169855 0.154008 1251 9 410 649 38544 12402 1.99423 1.99423 -145.271 -1.99423 -0.266634 -0.0836004 419432. 2912.72 0.13 0.04 0.0208542 0.0196835 144 96 -1 -1 -1 -1 - k6_frac_N10_mem32K_40nm.xml diffeq1.v common 11.77 vpr 65.80 MiB -1 -1 0.47 26664 15 0.34 -1 -1 37304 -1 -1 35 162 0 5 success 574ed3d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-09T03:32:19 gh-actions-runner-vtr-auto-spawned7 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 67380 162 96 993 934 1 681 298 16 16 256 mult_36 auto 27.7 MiB 0.31 5113 65.8 MiB 0.50 0.01 20.106 -1618.08 -20.106 20.106 0.77 0.00217296 0.00197923 0.207436 0.190287 50 11513 25 1.21132e+07 3.86629e+06 780512. 3048.87 6.47 0.875804 0.805344 9712 17 3116 5918 1742363 429866 22.6574 22.6574 -1836 -22.6574 0 0 1.00276e+06 3917.05 0.36 0.54 0.133314 0.125579 331 477 -1 -1 -1 -1 - k6_frac_N10_mem32K_40nm.xml diffeq2.v common 11.43 vpr 63.90 MiB -1 -1 0.38 25336 16 0.24 -1 -1 36424 -1 -1 26 66 0 5 success 574ed3d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-09T03:32:19 gh-actions-runner-vtr-auto-spawned7 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 65436 66 96 602 543 1 434 193 16 16 256 mult_36 auto 25.9 MiB 0.28 3693 63.9 MiB 0.31 0.00 15.955 -900.212 -15.955 15.955 0.78 0.00142013 0.00128384 0.13159 0.12001 36 10522 50 1.21132e+07 3.38124e+06 587529. 2295.03 6.77 0.56438 0.523086 8244 23 3003 6631 2356849 611477 18.0281 18.0281 -1080.03 -18.0281 0 0 727248. 2840.81 0.27 0.63 0.105067 0.0991321 228 278 -1 -1 -1 -1 - k6_frac_N10_mem32K_40nm.xml mkDelayWorker32B.v common 108.06 vpr 298.87 MiB -1 -1 15.55 129716 5 5.75 -1 -1 59988 -1 -1 460 506 47 0 success 574ed3d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-09T03:32:19 gh-actions-runner-vtr-auto-spawned7 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 306044 506 553 3055 3608 1 2790 1566 50 50 2500 memory auto 51.7 MiB 3.14 14672 298.9 MiB 4.38 0.08 6.41076 -1782.25 -6.41076 6.41076 34.44 0.0141067 0.0123732 2.02057 1.81825 38 22133 16 1.47946e+08 5.05479e+07 6.86584e+06 2746.33 20.81 6.23546 5.73969 21177 14 3872 4952 4352720 1022551 7.15296 7.15296 -2149.36 -7.15296 -2.7815 -0.200681 8.69095e+06 3476.38 4.62 1.68 0.669759 0.624552 953 407 -1 -1 -1 -1 - k6_frac_N10_mem32K_40nm.xml mkPktMerge.v common 20.48 vpr 67.71 MiB -1 -1 1.18 28880 2 0.13 -1 -1 37268 -1 -1 27 311 15 0 success 574ed3d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-09T03:32:19 gh-actions-runner-vtr-auto-spawned7 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 69336 311 156 972 1128 1 953 509 28 28 784 memory auto 29.7 MiB 0.51 8458 67.7 MiB 0.97 0.01 4.00983 -4155.9 -4.00983 4.00983 3.09 0.00408474 0.00359635 0.440014 0.384928 36 14997 16 4.25198e+07 9.67514e+06 1.94918e+06 2486.20 7.95 1.51894 1.35486 14006 14 2780 3117 2485901 739570 4.35837 4.35837 -4971.48 -4.35837 -21.572 -0.360359 2.40571e+06 3068.51 1.17 0.90 0.18658 0.17194 109 172 -1 -1 -1 -1 - k6_frac_N10_mem32K_40nm.xml mkSMAdapter4B.v common 32.25 vpr 75.44 MiB -1 -1 7.15 57956 7 2.95 -1 -1 42180 -1 -1 153 193 5 0 success 574ed3d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-09T03:32:19 gh-actions-runner-vtr-auto-spawned7 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 77248 193 205 2152 2357 1 1161 556 20 20 400 memory auto 38.0 MiB 1.42 8875 75.4 MiB 1.36 0.01 4.60807 -2645.76 -4.60807 4.60807 1.32 0.00414875 0.00363923 0.530313 0.466051 46 17471 32 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-1 -1 37268 -1 -1 27 311 15 0 success v8.0.0-8313-gbd73e8384d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.1.1 on Linux-6.1.31-2-MANJARO x86_64 2023-07-20T13:36:56 dev /home/vtr-verilog-to-routing 75356 311 156 972 1128 1 953 509 28 28 784 memory auto 35.4 MiB 0.61 8908 73.6 MiB 1.08 0.01 3.91091 -4218.66 -3.91091 3.91091 2.84 0.00230926 0.00200984 0.359046 0.308642 36 15717 19 4.25198e+07 9.67514e+06 1.94918e+06 2486.20 7.22 1.34863 1.19471 74338 387760 -1 14542 14 3080 3479 2680140 773137 0 0 2680140 773137 3479 3217 0 0 83837 82957 0 0 85441 84103 0 0 3518 3281 0 0 1254782 296821 0 0 1249083 302758 0 0 3479 0 0 399 2545 2929 12232 0 0 4.23237 4.23237 -5056.72 -4.23237 -15.8076 -0.339827 2.40571e+06 3068.51 1.04 0.88 0.29 -1 -1 1.04 0.17844 0.164245 109 172 -1 -1 -1 -1 + k6_frac_N10_mem32K_40nm.xml mkSMAdapter4B.v common 31.43 vpr 80.86 MiB -1 -1 5.88 58256 7 3.39 -1 -1 40880 -1 -1 153 193 5 0 success v8.0.0-8313-gbd73e8384d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.1.1 on Linux-6.1.31-2-MANJARO x86_64 2023-07-20T13:36:56 dev /home/vtr-verilog-to-routing 82800 193 205 2152 2357 1 1161 556 20 20 400 memory auto 43.4 MiB 1.94 8943 80.9 MiB 1.66 0.02 4.78473 -2696.64 -4.78473 4.78473 1.53 0.00400297 0.0034052 0.472395 0.410113 48 16781 24 2.07112e+07 1.09858e+07 1.23055e+06 3076.38 11.24 1.93493 1.69409 40448 245963 -1 14742 16 4328 10873 1200255 281400 0 0 1200255 281400 10461 6031 0 0 40538 37788 0 0 45332 40719 0 0 11069 6828 0 0 547455 95851 0 0 545400 94183 0 0 10461 0 0 6311 23915 22852 163514 486 39 5.16776 5.16776 -3186.51 -5.16776 -5.4156 -0.29768 1.57502e+06 3937.55 0.75 0.54 0.30 -1 -1 0.75 0.239954 0.221467 947 1120 -1 -1 -1 -1 + k6_frac_N10_mem32K_40nm.xml or1200.v common 89.48 vpr 115.21 MiB -1 -1 4.85 69064 27 5.97 -1 -1 45296 -1 -1 251 385 2 1 success v8.0.0-8313-gbd73e8384d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.1.1 on Linux-6.1.31-2-MANJARO x86_64 2023-07-20T13:36:56 dev /home/vtr-verilog-to-routing 117980 385 394 3884 4215 1 2355 1033 27 27 729 io auto 59.1 MiB 3.65 30973 96.2 MiB 6.03 0.06 13.1188 -12463.4 -13.1188 13.1188 3.21 0.0109579 0.0097997 1.35065 1.18507 80 49382 38 3.93038e+07 1.50194e+07 3.74040e+06 5130.86 51.71 5.72447 5.12141 91129 774047 -1 43968 14 9967 34459 2922044 557916 0 0 2922044 557916 33383 13994 0 0 74658 66867 0 0 93740 74784 0 0 34958 16026 0 0 1347423 190400 0 0 1337882 195845 0 0 33383 0 0 23997 107693 110664 651095 1126 170 15.0745 15.0745 -14171.5 -15.0745 0 0 4.71674e+06 6470.15 2.20 1.38 0.96 -1 -1 2.20 0.569131 0.530093 2220 2691 -1 -1 -1 -1 + k6_frac_N10_mem32K_40nm.xml raygentop.v common 33.96 vpr 83.09 MiB -1 -1 3.94 47416 8 1.08 -1 -1 42200 -1 -1 116 235 1 6 success v8.0.0-8313-gbd73e8384d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.1.1 on Linux-6.1.31-2-MANJARO x86_64 2023-07-20T13:36:56 dev /home/vtr-verilog-to-routing 85080 235 305 2594 2755 1 1443 663 19 19 361 io auto 45.4 MiB 1.74 11728 83.1 MiB 1.71 0.03 4.56197 -2459.7 -4.56197 4.56197 1.02 0.00514274 0.00446085 0.426807 0.379367 60 24673 37 1.72706e+07 9.1757e+06 1.37250e+06 3801.94 16.44 2.37913 2.12622 39239 274781 -1 20375 14 5989 16204 2539325 570437 0 0 2539325 570437 16204 9559 0 0 98499 94860 0 0 105825 98612 0 0 17294 10778 0 0 1155691 177930 0 0 1145812 178698 0 0 16204 0 0 10307 33334 32584 209541 0 0 4.97453 4.97453 -2881.32 -4.97453 -4.68518 -0.168146 1.72845e+06 4787.94 0.71 0.85 0.31 -1 -1 0.71 0.273433 0.254423 1038 1288 -1 -1 -1 -1 + k6_frac_N10_mem32K_40nm.xml sha.v common 24.93 vpr 83.68 MiB -1 -1 2.44 49324 21 3.11 -1 -1 42448 -1 -1 149 38 0 0 success v8.0.0-8313-gbd73e8384d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.1.1 on Linux-6.1.31-2-MANJARO x86_64 2023-07-20T13:36:56 dev /home/vtr-verilog-to-routing 85688 38 36 2570 2606 1 1074 223 17 17 289 clb auto 46.5 MiB 1.66 9514 83.7 MiB 0.74 0.01 12.4644 -2393.4 -12.4644 12.4644 1.02 0.00481272 0.00415747 0.300222 0.253292 48 16665 38 1.34605e+07 8.03021e+06 864508. 2991.38 7.21 1.51678 1.30377 28519 171069 -1 13641 14 4140 12331 398989 73362 0 0 398989 73362 10963 5247 0 0 16034 12603 0 0 20718 16034 0 0 11418 5863 0 0 174349 16137 0 0 165507 17478 0 0 10963 0 0 7027 33342 33275 197050 1783 212 14.5478 14.5478 -2910.6 -14.5478 0 0 1.10659e+06 3829.03 0.48 0.38 0.19 -1 -1 0.48 0.276267 0.253697 1458 1647 -1 -1 -1 -1 + k6_frac_N10_mem32K_40nm.xml stereovision0.v common 164.71 vpr 218.30 MiB -1 -1 10.05 121516 5 61.88 -1 -1 68980 -1 -1 744 169 0 0 success v8.0.0-8313-gbd73e8384d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.1.1 on Linux-6.1.31-2-MANJARO x86_64 2023-07-20T13:36:56 dev /home/vtr-verilog-to-routing 223544 169 197 21166 21363 1 7142 1110 34 34 1156 clb auto 152.3 MiB 10.44 46165 184.9 MiB 9.27 0.06 3.01927 -12729.8 -3.01927 3.01927 5.26 0.0167966 0.0137124 2.80423 2.30907 56 70282 24 6.50233e+07 4.00974e+07 4.37687e+06 3786.22 40.15 12.3035 10.3507 127124 890184 -1 65055 15 20021 32399 1255132 239317 0 0 1255132 239317 30131 21962 0 0 44899 34059 0 0 60291 44951 0 0 30916 22999 0 0 543661 57588 0 0 545234 57758 0 0 30131 0 0 10297 45427 47407 259322 2718 1311 3.57211 3.57211 -15077.5 -3.57211 0 0 5.58150e+06 4828.29 2.89 1.93 0.81 -1 -1 2.89 1.75263 1.60445 7006 9645 -1 -1 -1 -1 + k6_frac_N10_mem32K_40nm.xml stereovision1.v common 250.30 vpr 242.63 MiB -1 -1 11.90 136124 6 24.83 -1 -1 72356 -1 -1 757 113 0 44 success v8.0.0-8313-gbd73e8384d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.1.1 on Linux-6.1.31-2-MANJARO x86_64 2023-07-20T13:36:56 dev /home/vtr-verilog-to-routing 248456 113 145 21669 19534 1 9921 1059 40 40 1600 mult_36 auto 155.2 MiB 11.02 84966 189.9 MiB 13.52 0.12 5.13703 -21640.5 -5.13703 5.13703 6.10 0.0254963 0.0205479 3.55014 2.96238 80 136248 32 9.16046e+07 5.82227e+07 8.41679e+06 5260.49 144.01 13.5423 11.5404 201376 1751416 -1 121716 14 32286 54656 25487611 4986490 0 0 25487611 4986490 49794 37559 0 0 615639 601806 0 0 643432 616200 0 0 50968 38944 0 0 11616420 1869516 0 0 12511358 1822465 0 0 49794 0 0 18185 237271 200073 850021 5397 6870 5.33749 5.33749 -24758.4 -5.33749 0 0 1.06125e+07 6632.80 3.78 5.71 1.37 -1 -1 3.78 1.34153 1.23692 7327 9008 -1 -1 -1 -1 + k6_frac_N10_mem32K_40nm.xml stereovision2.v common 1056.65 vpr 943.41 MiB -1 -1 31.50 331100 16 133.21 -1 -1 135988 -1 -1 1888 149 0 179 success v8.0.0-8313-gbd73e8384d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.1.1 on Linux-6.1.31-2-MANJARO x86_64 2023-07-20T13:36:56 dev /home/vtr-verilog-to-routing 966048 149 182 46684 38970 1 28472 2398 80 80 6400 mult_36 auto 332.0 MiB 31.28 393214 899.7 MiB 42.95 0.32 15.9487 -50914 -15.9487 15.9487 71.15 0.0597852 0.0512421 7.37159 6.33625 110 515126 25 3.90281e+08 1.72634e+08 4.62465e+07 7226.02 649.24 29.7808 25.664 947776 10037526 -1 486806 15 92407 154782 52999200 10768095 0 0 52999200 10768095 149927 105762 0 0 1007198 962859 0 0 1079400 1010284 0 0 156232 110440 0 0 25404625 4221842 0 0 25201818 4356908 0 0 149927 0 0 57676 219177 213704 847726 5290 6377 17.987 17.987 -58723 -17.987 0 0 5.90184e+07 9221.63 21.20 12.07 7.35 -1 -1 21.20 2.78895 2.56434 17776 23295 -1 -1 -1 -1 + k6_frac_N10_mem32K_40nm.xml stereovision3.v common 9.25 vpr 66.33 MiB -1 -1 0.57 25160 5 0.11 -1 -1 37068 -1 -1 7 10 0 0 success v8.0.0-8313-gbd73e8384d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.1.1 on Linux-6.1.31-2-MANJARO x86_64 2023-07-20T13:36:56 dev /home/vtr-verilog-to-routing 67924 10 2 181 183 1 37 19 6 6 36 clb auto 27.9 MiB 0.06 131 66.3 MiB 0.01 0.00 1.93751 -82.3688 -1.93751 1.93751 0.04 0.000169238 0.000130915 0.00259954 0.0023627 20 190 13 646728 377258 34888.9 969.136 0.07 0.0130989 0.012017 2216 6354 -1 156 6 69 100 1591 585 0 0 1591 585 100 81 0 0 139 100 0 0 155 139 0 0 105 85 0 0 632 70 0 0 460 110 0 0 100 0 0 31 29 32 280 0 0 2.0211 2.0211 -91.3362 -2.0211 0 0 45676.2 1268.78 0.01 0.01 0.01 -1 -1 0.01 0.00803925 0.00765069 52 88 -1 -1 -1 -1 + k6_frac_N10_mem32K_40nm.xml LU8PEEng.v common 466.95 vpr 445.93 MiB -1 -1 59.63 335624 122 82.28 -1 -1 81980 -1 -1 1335 114 45 8 success v8.0.0-8313-gbd73e8384d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.1.1 on Linux-6.1.31-2-MANJARO x86_64 2023-07-20T13:36:56 dev /home/vtr-verilog-to-routing 456628 114 102 21867 21777 1 11032 1604 50 50 2500 memory auto 208.8 MiB 26.32 155124 406.2 MiB 24.67 0.19 67.5178 -51175 -67.5178 67.5178 25.42 0.0453485 0.0387181 5.09578 4.21828 94 232477 22 1.47946e+08 9.97789e+07 1.55181e+07 6207.23 193.62 18.9489 15.9124 341268 3271592 -1 212120 19 40727 161630 45058607 10746751 0 0 45058607 10746751 154686 53843 0 0 613506 564597 0 0 724880 621333 0 0 160007 63242 0 0 21674885 4640633 0 0 21730643 4803103 0 0 154686 0 0 116598 469846 457812 2910250 7265 5157 79.6938 79.6938 -67331.5 -79.6938 -4.63469 -0.293253 1.95446e+07 7817.85 6.28 12.61 2.37 -1 -1 6.28 2.32899 2.05913 12499 14088 -1 -1 -1 -1 + k6_frac_N10_mem32K_40nm.xml LU32PEEng.v common 2140.54 vpr 1.57 GiB -1 -1 186.04 998368 121 513.06 -1 -1 235996 -1 -1 4471 114 168 32 success v8.0.0-8313-gbd73e8384d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.1.1 on Linux-6.1.31-2-MANJARO x86_64 2023-07-20T13:36:56 dev /home/vtr-verilog-to-routing 1642344 114 102 72397 71731 1 37195 4887 92 92 8464 memory auto 651.9 MiB 64.23 725538 1324.1 MiB 147.06 0.93 69.2775 -297336 -69.2775 69.2775 77.41 0.112838 0.0964397 15.7361 13.0779 124 963655 20 5.19428e+08 3.45674e+08 6.83823e+07 8079.19 962.28 58.8085 49.5209 1330926 14951874 -1 905364 20 130555 572169 232286285 61691524 0 0 232286285 61691524 524807 160878 0 0 2225561 2059152 0 0 2651212 2247498 0 0 539806 190687 0 0 112394185 27988380 0 0 113950714 29044929 0 0 524807 0 0 403174 2369250 2339003 11512966 48866 136531 80.1891 80.1891 -428654 -80.1891 -29.9739 -0.29436 8.66909e+07 10242.3 26.17 61.95 11.56 -1 -1 26.17 7.33236 6.54016 42436 46992 -1 -1 -1 -1 + k6_frac_N10_mem32K_40nm.xml mcml.v common 3520.65 vpr 1.45 GiB -1 -1 414.23 1375900 63 2354.27 -1 -1 351976 -1 -1 4791 36 159 27 success v8.0.0-8313-gbd73e8384d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.1.1 on Linux-6.1.31-2-MANJARO x86_64 2023-07-20T13:36:56 dev /home/vtr-verilog-to-routing 1517048 36 356 125074 123859 1 31592 5369 92 92 8464 memory auto 848.1 MiB 44.56 386934 1462.7 MiB 88.58 0.54 58.3963 -256243 -58.3963 58.3963 70.20 0.102126 0.0862249 15.2881 12.8959 78 552717 29 5.19428e+08 3.56007e+08 4.53556e+07 5358.65 392.74 50.871 43.3978 1077038 9588492 -1 516113 20 107011 333616 86438658 20655757 0 0 86438658 20655757 293838 140032 0 0 1564305 1471314 0 0 1739818 1576025 0 0 305295 159752 0 0 41379355 8551879 0 0 41156047 8756755 0 0 293838 0 0 189249 879941 879963 3765557 42162 383411 65.7748 65.7748 -332915 -65.7748 -0.225514 -0.0292962 5.73940e+07 6780.95 18.07 21.16 6.08 -1 -1 18.07 7.29225 6.61107 46619 73802 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor_chain/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor_chain/config/golden_results.txt index 6dd667cb7b3..ae79cfe8d64 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor_chain/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor_chain/config/golden_results.txt @@ -1,22 +1,22 @@ -arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops crit_path_total_internal_heap_pushes crit_path_total_internal_heap_pops crit_path_total_external_heap_pushes crit_path_total_external_heap_pops crit_path_total_external_SOURCE_pushes crit_path_total_external_SOURCE_pops crit_path_total_internal_SOURCE_pushes crit_path_total_internal_SOURCE_pops crit_path_total_external_SINK_pushes crit_path_total_external_SINK_pops crit_path_total_internal_SINK_pushes crit_path_total_internal_SINK_pops crit_path_total_external_IPIN_pushes crit_path_total_external_IPIN_pops crit_path_total_internal_IPIN_pushes crit_path_total_internal_IPIN_pops crit_path_total_external_OPIN_pushes crit_path_total_external_OPIN_pops crit_path_total_internal_OPIN_pushes crit_path_total_internal_OPIN_pops crit_path_total_external_CHANX_pushes crit_path_total_external_CHANX_pops crit_path_total_internal_CHANX_pushes crit_path_total_internal_CHANX_pops crit_path_total_external_CHANY_pushes crit_path_total_external_CHANY_pops crit_path_total_internal_CHANY_pushes crit_path_total_internal_CHANY_pops crit_path_rt_node_SOURCE_pushes crit_path_rt_node_SINK_pushes crit_path_rt_node_IPIN_pushes crit_path_rt_node_OPIN_pushes crit_path_rt_node_CHANX_pushes crit_path_rt_node_CHANY_pushes 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/root/vtr-verilog-to-routing/vtr-verilog-to-routing 85132 38 36 2744 2493 1 1037 206 16 16 256 clb auto 46.1 MiB 2.60 8605 83.1 MiB 1.04 0.02 9.2557 -2488.28 -9.2557 9.2557 0.91 0.00913363 0.00746336 0.564793 0.483165 64 12823 20 1.21132e+07 7.11401e+06 1.00276e+06 3917.05 6.46 3.0148 2.62134 28592 198411 -1 12333 22 4332 9782 375885 65609 0 0 375885 65609 9182 5006 0 0 13374 9992 0 0 20044 13409 0 0 9413 5384 0 0 163146 15567 0 0 160726 16251 0 0 9182 0 0 5051 27553 26289 197761 730 107 10.9115 10.9115 -3081.15 -10.9115 0 0 1.25521e+06 4903.16 0.47 0.70 0.25 -1 -1 0.47 0.557217 0.494414 + k6_frac_N10_frac_chain_mem32K_40nm.xml spree.v common 25.23 vpr 74.60 MiB -1 -1 3.34 34324 16 0.71 -1 -1 37800 -1 -1 61 45 3 1 success 168f007-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.5.0 on Linux-5.10.35-v8 x86_64 2023-09-10T13:47:58 gh-actions-runner-vtr-auto-spawned5 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 76388 45 32 1193 1152 1 791 142 14 14 196 memory auto 36.9 MiB 2.89 6696 74.6 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52413 27638660 5590543 0 0 27638660 5590543 47486 38101 0 0 603337 590193 0 0 638433 604646 0 0 48900 39273 0 0 13116047 2122596 0 0 13184457 2195734 0 0 47486 0 0 14789 194171 200346 743137 5350 2860 5.44068 5.44068 -25073.2 -5.44068 0 0 1.15336e+07 7208.51 5.66 11.18 2.54 -1 -1 5.66 2.46486 2.17612 + k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision2.v common 716.30 vpr 923.09 MiB -1 -1 17.05 197132 3 9.97 -1 -1 155012 -1 -1 1498 149 0 179 success 168f007-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.5.0 on Linux-5.10.35-v8 x86_64 2023-09-10T13:47:58 gh-actions-runner-vtr-auto-spawned5 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 945244 149 182 55416 37075 1 28615 2008 80 80 6400 mult_36 auto 356.7 MiB 29.56 292875 923.1 MiB 86.89 0.59 12.0992 -47669.5 -12.0992 12.0992 126.87 0.132042 0.114467 20.0391 16.3461 96 422372 45 3.90281e+08 1.51617e+08 4.11781e+07 6434.07 312.23 65.3324 53.9182 901880 8701757 -1 383436 19 101430 119780 44985362 9118338 0 0 44985362 9118338 117847 105453 0 0 974905 936173 0 0 1099495 978614 0 0 118863 106726 0 0 21396619 3441321 0 0 21277633 3550051 0 0 117847 0 0 16517 101953 97518 383293 2408 3049 13.7193 13.7193 -54713.6 -13.7193 0 0 5.14892e+07 8045.19 28.90 24.87 12.88 -1 -1 28.90 7.41219 6.41351 + k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 2.79 vpr 66.95 MiB -1 -1 0.73 25044 4 0.18 -1 -1 35640 -1 -1 15 11 0 0 success 168f007-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.5.0 on Linux-5.10.35-v8 x86_64 2023-09-10T13:47:58 gh-actions-runner-vtr-auto-spawned5 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 68560 11 2 303 283 2 80 28 7 7 49 clb auto 28.6 MiB 0.26 262 67.0 MiB 0.05 0.00 1.86328 -148.615 -1.86328 1.77125 0.09 0.000619303 0.000545237 0.0270593 0.024287 26 348 20 1.07788e+06 808410 68696.0 1401.96 0.20 0.121964 0.106082 3516 12294 -1 329 11 202 331 5307 1941 0 0 5307 1941 331 277 0 0 422 331 0 0 488 422 0 0 395 317 0 0 1902 351 0 0 1769 243 0 0 331 0 0 129 177 156 1255 0 0 1.98243 1.82748 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8.82 5.43805 4.71662 + k6_frac_N10_frac_chain_mem32K_40nm.xml LU32PEEng.v common 4696.50 vpr 2.22 GiB -1 -1 224.16 1476188 97 1295.36 -1 -1 357704 -1 -1 7412 114 168 32 success 168f007-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.5.0 on Linux-5.10.35-v8 x86_64 2023-09-10T13:47:58 gh-actions-runner-vtr-auto-spawned5 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 2331516 114 102 120062 107871 1 57253 7828 102 102 10404 clb auto 1117.3 MiB 311.31 1026779 1827.8 MiB 468.75 2.94 64.7172 -343930 -64.7172 64.7172 132.49 0.278765 0.244287 39.56 33.0954 132 1348522 23 6.36957e+08 5.04159e+08 8.88356e+07 8538.60 1927.09 174.105 142.084 1719732 19599881 -1 1294641 20 206456 897577 259367945 68896390 0 0 259367945 68896390 844868 255276 0 0 2617408 2394583 0 0 3226115 2635699 0 0 877238 309016 0 0 124439792 31032970 0 0 127362524 32268846 0 0 844868 0 0 663878 3915548 3927216 21958437 54562 195130 73.1695 73.1695 -478357 -73.1695 0 0 1.13733e+08 10931.6 57.08 112.55 20.01 -1 -1 57.08 18.0642 15.6145 + k6_frac_N10_frac_chain_mem32K_40nm.xml mcml.v common 6538.59 vpr 2.03 GiB -1 -1 293.14 1241956 25 4708.27 -1 -1 371036 -1 -1 6438 36 159 27 success 168f007-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.5.0 on Linux-5.10.35-v8 x86_64 2023-09-10T13:47:58 gh-actions-runner-vtr-auto-spawned5 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 2132944 36 356 184794 159441 1 63873 7016 95 95 9025 clb auto 1304.2 MiB 150.60 762501 1810.7 MiB 483.65 3.05 41.756 -304360 -41.756 41.756 103.52 0.250235 0.198828 37.009 30.2993 142 999026 44 5.4965e+08 4.44764e+08 8.24996e+07 9141.23 565.60 140.497 115.874 1545258 18129248 -1 961473 21 220892 499165 103698408 24915605 0 0 103698408 24915605 438773 253639 0 0 1517742 1393247 0 0 1870287 1525002 0 0 450080 273409 0 0 49548980 10620812 0 0 49872546 10849496 0 0 438773 0 0 220927 1134104 1047230 3824786 68547 252639 45.4769 45.4769 -371165 -45.4769 0 0 1.04574e+08 11587.1 44.65 45.09 18.73 -1 -1 44.65 15.6757 13.7463 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor_chain_depop/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor_chain_depop/config/golden_results.txt index ea0cc60756b..52645d47c66 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor_chain_depop/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor_chain_depop/config/golden_results.txt @@ -1,22 +1,22 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml arm_core.v common 429.79 vpr 254.70 MiB -1 -1 32.42 122848 20 86.82 -1 -1 71680 -1 -1 678 133 25 0 success 574ed3d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-09T03:32:19 gh-actions-runner-vtr-auto-spawned7 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 260812 133 179 14247 14104 1 6984 1015 36 36 1296 memory auto 147.2 MiB 26.63 111456 179.0 MiB 17.66 0.16 19.665 -203737 -19.665 19.665 5.60 0.0429621 0.0375059 4.90513 4.1347 152 203246 41 7.21828e+07 5.02408e+07 1.27723e+07 9855.19 214.08 19.1503 16.0569 185209 16 34107 142030 48694183 11050030 22.5669 22.5669 -223183 -22.5669 -12.1191 -0.298787 1.60965e+07 12420.2 7.25 17.31 2.24903 2.0136 - k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml bgm.v common 735.73 vpr 662.53 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100 10175 7629 1 2974 593 27 27 729 clb auto 101.2 MiB 18.82 41977 136.7 MiB 6.20 0.06 13.8427 -2247.93 -13.8427 13.8427 3.43 0.0237759 0.0214548 2.4615 2.16881 98 90444 47 3.93038e+07 2.46296e+07 4.82856e+06 6623.53 92.63 9.54464 8.07035 77075 18 14547 73925 5506747 1013913 15.2896 15.2896 -2658.37 -15.2896 0 0 6.08869e+06 8352.11 3.03 2.99 1.405 1.23705 - k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml boundtop.v common 26.29 vpr 69.06 MiB -1 -1 17.47 47884 3 0.73 -1 -1 38592 -1 -1 44 196 1 0 success 574ed3d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-09T03:32:19 gh-actions-runner-vtr-auto-spawned7 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 70716 196 193 1202 1347 1 609 434 15 15 225 io auto 31.0 MiB 0.53 2915 69.1 MiB 0.63 0.01 2.07553 -987.105 -2.07553 2.07553 0.75 0.00261807 0.00238414 0.25233 0.228929 40 7329 50 1.03862e+07 2.91934e+06 618415. 2748.51 3.10 1.07576 0.986055 6327 17 2310 3827 378656 103928 2.62347 2.62347 -1211.32 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Linux-5.10.35-v8 x86_64 2023-02-09T03:32:19 gh-actions-runner-vtr-auto-spawned7 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 68508 162 96 1067 884 1 656 289 16 16 256 mult_36 auto 29.1 MiB 0.37 4897 66.9 MiB 0.53 0.01 15.6004 -1183.4 -15.6004 15.6004 0.89 0.00217579 0.00198703 0.21541 0.196596 62 10790 41 1.21132e+07 3.38124e+06 1.04918e+06 4098.38 7.24 0.897709 0.827927 9074 17 3102 5289 1733336 448307 17.1815 17.1815 -1398.02 -17.1815 0 0 1.29183e+06 5046.22 0.52 0.56 0.118194 0.111193 - k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml diffeq2.v common 11.23 vpr 65.50 MiB -1 -1 0.27 23972 5 0.11 -1 -1 36496 -1 -1 16 66 0 5 success 574ed3d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-09T03:32:19 gh-actions-runner-vtr-auto-spawned7 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 67068 66 96 779 596 1 446 183 16 16 256 mult_36 auto 27.4 MiB 0.33 3501 65.5 MiB 0.33 0.00 11.7582 -718.798 -11.7582 11.7582 0.86 0.00136554 0.00122914 0.139381 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LU32PEEng.v common 5106.57 vpr 1.95 GiB -1 -1 221.73 1477812 97 934.20 -1 -1 358556 -1 -1 6215 114 168 32 success 574ed3d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-09T03:32:19 gh-actions-runner-vtr-auto-spawned7 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 2042568 114 102 120062 107871 1 56756 6631 94 94 8836 clb auto 1096.3 MiB 97.45 1034460 1851.2 MiB 278.83 1.97 63.1531 -327075 -63.1531 63.1531 93.44 0.195024 0.157693 25.5404 21.4358 172 1611212 37 5.40921e+08 4.39655e+08 1.03144e+08 11673.2 3224.45 104.648 87.6369 1520135 23 241359 1093079 309344292 76469518 74.372 74.372 -478906 -74.372 -41.9734 -0.176247 1.30092e+08 14722.9 43.43 82.58 12.8659 11.2987 - k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml mcml.v common 5343.29 vpr 2.06 GiB -1 -1 294.81 1239072 25 3928.65 -1 -1 373112 -1 -1 6040 36 159 27 success 574ed3d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-09T03:32:19 gh-actions-runner-vtr-auto-spawned7 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 2160268 36 356 184794 159441 1 63844 6618 93 93 8649 clb auto 1305.9 MiB 93.21 769524 1957.1 MiB 310.95 2.00 43.7051 -268511 -43.7051 43.7051 86.46 0.149355 0.116109 23.3171 18.7608 158 1106269 33 5.27943e+08 4.23316e+08 9.25072e+07 10695.7 427.49 81.8209 67.1208 1049377 20 248345 601971 122293436 27502132 47.0227 47.0227 -334412 -47.0227 0 0 1.17788e+08 13618.7 39.58 35.20 10.3655 9.14164 - k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml mkDelayWorker32B.v common 129.62 vpr 366.71 MiB -1 -1 16.44 122524 5 6.51 -1 -1 47452 -1 -1 456 506 44 0 success 574ed3d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-09T03:32:19 gh-actions-runner-vtr-auto-spawned7 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 375516 506 553 3236 3734 1 2845 1559 50 50 2500 memory auto 55.9 MiB 4.06 16032 366.7 MiB 5.02 0.05 6.80712 -2054 -6.80712 6.80712 45.76 0.0175213 0.015915 2.28393 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/root/vtr-verilog-to-routing/vtr-verilog-to-routing 106428 385 362 4417 4306 1 2338 955 26 26 676 io auto 57.8 MiB 4.25 29898 94.6 MiB 5.35 0.06 8.41209 -8606.11 -8.41209 8.41209 3.04 0.0132573 0.0121657 1.68659 1.50164 124 53895 30 3.69863e+07 1.25403e+07 5.46418e+06 8083.11 59.71 7.45582 6.63407 49421 17 10867 37696 5338027 1021071 9.49228 9.49228 -10001 -9.49228 0 0 6.89526e+06 10200.1 3.79 2.48 0.784424 0.718164 - k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml raygentop.v common 44.56 vpr 82.12 MiB -1 -1 4.14 45508 3 0.80 -1 -1 40260 -1 -1 112 236 1 6 success 574ed3d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-09T03:32:19 gh-actions-runner-vtr-auto-spawned7 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 84096 236 305 3195 3007 1 1538 660 19 19 361 io auto 44.7 MiB 1.68 12630 82.1 MiB 2.09 0.03 4.38488 -2613.2 -4.38488 4.38488 1.40 0.00734113 0.00668463 0.825011 0.750059 84 28775 47 1.72706e+07 8.96013e+06 1.98721e+06 5504.73 27.52 3.95983 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release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-09T03:32:19 gh-actions-runner-vtr-auto-spawned7 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 72132 45 32 1188 1147 1 779 128 14 14 196 memory auto 33.0 MiB 0.89 6343 70.4 MiB 0.46 0.01 9.65905 -6148.72 -9.65905 9.65905 0.63 0.00277918 0.00237587 0.224 0.195358 78 15037 50 9.20055e+06 4.57302e+06 962129. 4908.82 13.37 1.48543 1.29635 12738 37 3920 10917 3210572 967402 11.158 11.158 -7323.72 -11.158 -32.4092 -0.292146 1.21337e+06 6190.68 0.45 1.33 0.304433 0.273601 - k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml stereovision0.v common 116.16 vpr 229.20 MiB -1 -1 12.14 102824 5 13.69 -1 -1 69400 -1 -1 673 169 0 0 success 574ed3d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-09T03:32:19 gh-actions-runner-vtr-auto-spawned7 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 234696 169 197 23321 21461 1 6785 1039 33 33 1089 clb auto 174.0 MiB 9.09 40964 207.7 MiB 11.23 0.10 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k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml stereovision2.v common 919.98 vpr 1.04 GiB -1 -1 11.15 197868 3 6.30 -1 -1 155564 -1 -1 1490 149 0 179 success 574ed3d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-09T03:32:19 gh-actions-runner-vtr-auto-spawned7 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 1089076 149 182 55416 37075 1 28670 2000 80 80 6400 mult_36 auto 356.8 MiB 19.69 304023 1063.6 MiB 92.74 0.67 13.2416 -49841.9 -13.2416 13.2416 121.55 0.0962531 0.0848053 14.9704 12.5803 106 425024 43 3.90281e+08 1.51186e+08 4.81287e+07 7520.11 553.42 45.7326 38.6761 404262 21 97832 118922 48216274 9732760 14.616 14.616 -57830.7 -14.616 0 0 6.06309e+07 9473.58 31.45 17.86 4.59878 4.07441 - k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml stereovision3.v common 2.09 vpr 63.42 MiB -1 -1 0.60 25644 4 0.12 -1 -1 36300 -1 -1 13 11 0 0 success 574ed3d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-09T03:32:19 gh-actions-runner-vtr-auto-spawned7 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 64944 11 2 303 283 2 70 26 7 7 49 clb auto 24.9 MiB 0.14 217 63.4 MiB 0.04 0.00 1.86505 -151.175 -1.86505 1.77348 0.07 0.000327567 0.000244201 0.018376 0.0145168 26 539 18 1.07788e+06 700622 75813.7 1547.22 0.14 0.063896 0.0534703 424 12 250 515 15897 6574 2.07043 1.88 -175.337 -2.07043 0 0 91376.6 1864.83 0.02 0.03 0.0178958 0.0166099 + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles 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release IPO VTR_ASSERT_LEVEL=2 GNU 13.1.1 on Linux-6.1.31-2-MANJARO x86_64 2023-07-20T13:36:56 dev /home/vtr-verilog-to-routing 2461804 36 356 184794 159441 1 63844 6618 93 93 8649 clb auto 1315.9 MiB 101.20 761761 1980.2 MiB 452.96 2.62 42.5926 -275094 -42.5926 42.5926 95.50 0.169429 0.134345 26.7855 22.0562 158 1103853 32 5.27943e+08 4.23316e+08 9.25072e+07 10695.7 1691.99 113.417 94.2878 1667048 21718160 -1 1046278 22 251197 612929 123566250 27262156 0 0 123566250 27262156 526934 313948 0 0 2698183 2576132 0 0 4050018 3326023 0 0 544113 350710 0 0 57911189 10164778 0 0 57835813 10530565 0 0 526934 0 0 279966 1659463 1658463 5585096 94831 756500 45.7759 45.7759 -340713 -45.7759 0 0 1.17788e+08 13618.7 40.92 35.94 17.19 -1 -1 40.92 11.3268 10.0706 + k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml mkDelayWorker32B.v common 183.79 vpr 376.73 MiB -1 -1 15.42 122092 5 7.48 -1 -1 48112 -1 -1 456 506 44 0 success v8.0.0-8313-gbd73e8384d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.1.1 on 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1.41477e+06 6287.88 0.61 0.59 0.27 -1 -1 0.61 0.3587 0.319312 + k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml spree.v common 28.39 vpr 76.00 MiB -1 -1 2.95 34356 16 0.78 -1 -1 38304 -1 -1 46 45 3 1 success v8.0.0-8313-gbd73e8384d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.1.1 on Linux-6.1.31-2-MANJARO x86_64 2023-07-20T13:36:56 dev /home/vtr-verilog-to-routing 77824 45 32 1193 1152 1 771 127 14 14 196 memory auto 38.5 MiB 1.24 6049 76.0 MiB 0.65 0.01 9.279 -6076.56 -9.279 9.279 0.80 0.00288547 0.00239332 0.291076 0.244835 90 13081 35 9.20055e+06 4.51912e+06 1.09403e+06 5581.78 17.44 1.81468 1.53341 26780 228147 -1 11860 14 3540 10244 2006820 500194 0 0 2006820 500194 10244 5702 0 0 69812 68133 0 0 91271 79384 0 0 10702 6685 0 0 913321 175447 0 0 911470 164843 0 0 10244 0 0 6849 25537 25219 171895 0 0 10.2605 10.2605 -7127.39 -10.2605 -14.2672 -0.317384 1.36167e+06 6947.29 0.59 0.65 0.24 -1 -1 0.59 0.147106 0.135394 + k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml stereovision0.v common 141.74 vpr 247.67 MiB -1 -1 9.78 102876 5 9.82 -1 -1 69436 -1 -1 673 169 0 0 success v8.0.0-8313-gbd73e8384d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.1.1 on Linux-6.1.31-2-MANJARO x86_64 2023-07-20T13:36:56 dev /home/vtr-verilog-to-routing 253612 169 197 23321 21461 1 6785 1039 33 33 1089 clb auto 179.3 MiB 10.76 41251 213.2 MiB 10.82 0.10 3.08234 -13147 -3.08234 3.08234 5.55 0.0273427 0.023104 3.42361 2.83565 78 65470 35 6.0475e+07 3.62708e+07 5.97661e+06 5488.16 67.21 18.087 14.9138 148670 1295497 -1 61251 14 16594 29274 1699709 394274 0 0 1699709 394274 25875 19353 0 0 89056 80593 0 0 137119 118902 0 0 26797 20616 0 0 711313 77700 0 0 709549 77110 0 0 25875 0 0 9458 48935 54831 239069 3826 1927 3.87583 3.87583 -15634.2 -3.87583 0 0 7.53085e+06 6915.38 4.02 2.38 1.47 -1 -1 4.02 1.98836 1.77451 + k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml stereovision1.v common 356.60 vpr 298.27 MiB -1 -1 9.50 123468 3 17.20 -1 -1 79532 -1 -1 655 115 0 40 success v8.0.0-8313-gbd73e8384d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.1.1 on Linux-6.1.31-2-MANJARO x86_64 2023-07-20T13:36:56 dev /home/vtr-verilog-to-routing 305432 115 145 22868 19305 1 9712 955 40 40 1600 mult_36 auto 175.4 MiB 10.12 82272 210.1 MiB 13.21 0.12 5.15059 -21406.4 -5.15059 5.15059 8.98 0.0283561 0.0236999 3.68002 3.10504 100 136709 35 9.16046e+07 5.11412e+07 1.10258e+07 6891.10 253.71 21.791 18.0567 242376 2436732 -1 123699 17 34263 54166 18393474 3828800 0 0 18393474 3828800 46677 38279 0 0 561638 549249 0 0 662523 619771 0 0 48054 39439 0 0 8579349 1288609 0 0 8495233 1293453 0 0 46677 0 0 12866 162410 159065 555314 8140 5217 5.48539 5.48539 -24969.7 -5.48539 0 0 1.38359e+07 8647.47 8.02 6.57 2.47 -1 -1 8.02 2.01249 1.77565 + k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml stereovision2.v common 1568.29 vpr 1.06 GiB -1 -1 13.62 197080 3 8.22 -1 -1 157328 -1 -1 1490 149 0 179 success v8.0.0-8313-gbd73e8384d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.1.1 on Linux-6.1.31-2-MANJARO x86_64 2023-07-20T13:36:56 dev /home/vtr-verilog-to-routing 1107964 149 182 55416 37075 1 28670 2000 80 80 6400 mult_36 auto 361.6 MiB 28.98 291939 1082.0 MiB 70.87 0.42 12.5458 -48952.6 -12.5458 12.5458 137.07 0.0571067 0.050096 12.1912 10.3311 100 418048 35 3.90281e+08 1.51186e+08 4.58129e+07 7158.27 1169.23 65.0704 54.0002 988936 10231362 -1 389032 20 98976 121041 47809628 9731402 0 0 47809628 9731402 115777 103569 0 0 1169182 1140059 0 0 1411483 1297865 0 0 116899 105223 0 0 22494027 3480737 0 0 22502260 3603949 0 0 115777 0 0 16949 122925 119822 398678 5579 10350 13.8912 13.8912 -57858.9 -13.8912 0 0 5.74647e+07 8978.85 35.65 20.89 11.96 -1 -1 35.65 5.31911 4.69368 + k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml stereovision3.v common 3.09 vpr 68.77 MiB -1 -1 0.67 24964 4 0.19 -1 -1 36240 -1 -1 13 11 0 0 success v8.0.0-8313-gbd73e8384d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.1.1 on Linux-6.1.31-2-MANJARO x86_64 2023-07-20T13:36:56 dev /home/vtr-verilog-to-routing 70420 11 2 303 283 2 70 26 7 7 49 clb auto 30.4 MiB 0.18 218 68.8 MiB 0.04 0.00 1.86682 -151.802 -1.86682 1.77386 0.09 0.000344302 0.000276027 0.0236224 0.0194743 26 512 13 1.07788e+06 700622 75813.7 1547.22 0.47 0.140131 0.117455 3816 13734 -1 438 11 240 500 16504 6703 0 0 16504 6703 500 416 0 0 1541 1353 0 0 2437 2240 0 0 580 522 0 0 5898 1098 0 0 5548 1074 0 0 500 0 0 260 476 425 2907 0 0 2.16847 1.939 -177.724 -2.16847 0 0 91376.6 1864.83 0.02 0.03 0.01 -1 -1 0.02 0.0203121 0.0186171 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor_chain_predictor_off/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor_chain_predictor_off/config/golden_results.txt index d15d5058be2..8efc4f55c8c 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor_chain_predictor_off/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/vtr_reg_qor_chain_predictor_off/config/golden_results.txt @@ -1,22 +1,22 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_frac_chain_mem32K_40nm.xml arm_core.v common 401.59 vpr 235.50 MiB -1 -1 24.45 123564 20 64.80 -1 -1 71700 -1 -1 847 133 25 0 success 574ed3d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-09T03:32:19 gh-actions-runner-vtr-auto-spawned7 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 241148 133 179 14247 14104 1 7175 1184 36 36 1296 clb memory auto 149.3 MiB 34.82 119184 180.9 MiB 19.00 0.16 20.0132 -196903 -20.0132 20.0132 5.74 0.0402095 0.0345666 4.96051 4.12714 110 177229 22 7.21828e+07 5.93492e+07 8.93497e+06 6894.27 207.46 24.3203 20.0712 163046 14 30059 114974 39117068 9496619 23.104 23.104 -218726 -23.104 0 0 1.14064e+07 8801.20 5.56 19.36 2.69462 2.36102 - k6_frac_N10_frac_chain_mem32K_40nm.xml bgm.v common 846.32 vpr 653.23 MiB -1 -1 46.92 623588 14 91.29 -1 -1 123172 -1 -1 2706 257 0 11 success 574ed3d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-09T03:32:19 gh-actions-runner-vtr-auto-spawned7 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 668904 257 32 35747 33389 1 19410 3006 63 63 3969 clb auto 368.9 MiB 77.60 247661 653.2 MiB 140.97 1.22 17.4309 -23379.6 -17.4309 17.4309 67.78 0.151476 0.129693 17.0733 14.1225 74 396741 39 2.36641e+08 1.50195e+08 2.02178e+07 5093.92 326.56 60.7583 50.3328 379429 20 95731 434516 33467452 5953082 19.895 19.895 -26168.1 -19.895 0 0 2.53694e+07 6391.88 11.42 16.90 6.59753 5.78216 - k6_frac_N10_frac_chain_mem32K_40nm.xml blob_merge.v common 81.71 yosys 260.56 MiB -1 -1 11.06 266812 5 5.11 -1 -1 57568 -1 -1 494 36 0 0 success 574ed3d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-09T03:32:19 gh-actions-runner-vtr-auto-spawned7 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 139240 36 100 10175 7629 1 2793 630 28 28 784 clb auto 102.6 MiB 16.05 42202 136.0 MiB 4.26 0.04 13.9278 -2282.25 -13.9278 13.9278 2.61 0.0142389 0.0125669 1.56966 1.36107 72 70201 32 4.25198e+07 2.66236e+07 3.68518e+06 4700.49 28.08 6.24265 5.3145 63770 16 12754 64960 2911703 417750 15.7024 15.7024 -2628.96 -15.7024 0 0 4.61751e+06 5889.69 1.77 1.62 0.960975 0.857421 - k6_frac_N10_frac_chain_mem32K_40nm.xml boundtop.v common 19.52 vpr 68.58 MiB -1 -1 12.73 47924 3 0.65 -1 -1 38524 -1 -1 44 196 1 0 success 574ed3d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-09T03:32:19 gh-actions-runner-vtr-auto-spawned7 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 70228 196 193 1202 1347 1 614 434 15 15 225 io auto 30.8 MiB 0.66 2777 68.6 MiB 0.53 0.01 1.9758 -972.903 -1.9758 1.9758 0.56 0.00189523 0.00166132 0.191119 0.171077 46 5494 16 1.03862e+07 2.91934e+06 643451. 2859.78 1.73 0.680586 0.615765 5178 11 1592 2268 188386 49647 2.44373 2.44373 -1169.13 -2.44373 0 0 826872. 3674.99 0.24 0.12 0.0831891 0.0786237 - k6_frac_N10_frac_chain_mem32K_40nm.xml ch_intrinsics.v common 2.78 vpr 63.79 MiB -1 -1 0.28 21540 3 0.08 -1 -1 36472 -1 -1 68 99 1 0 success 574ed3d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-09T03:32:19 gh-actions-runner-vtr-auto-spawned7 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 65316 99 130 343 473 1 217 298 12 12 144 clb auto 25.6 MiB 0.20 499 63.8 MiB 0.16 0.00 1.48813 -108.35 -1.48813 1.48813 0.29 0.000437478 0.000384829 0.0391007 0.0347964 36 1263 13 5.66058e+06 4.21279e+06 305235. 2119.69 0.60 0.148441 0.133937 1175 9 426 678 31480 9698 1.91419 1.91419 -136.404 -1.91419 0 0 378966. 2631.71 0.10 0.03 0.0174973 0.016595 - k6_frac_N10_frac_chain_mem32K_40nm.xml diffeq1.v common 10.71 vpr 67.02 MiB -1 -1 0.35 25372 5 0.17 -1 -1 37320 -1 -1 31 162 0 5 success 574ed3d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-09T03:32:19 gh-actions-runner-vtr-auto-spawned7 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 68632 162 96 1067 884 1 657 294 16 16 256 mult_36 auto 29.4 MiB 0.37 4929 67.0 MiB 0.50 0.01 15.4069 -1157.24 -15.4069 15.4069 0.69 0.00162646 0.0014535 0.181087 0.162235 52 11543 27 1.21132e+07 3.65071e+06 805949. 3148.24 5.85 0.666942 0.608091 9181 18 3213 5308 2122214 549335 17.3289 17.3289 -1344.26 -17.3289 0 0 1.06067e+06 4143.25 0.33 0.52 0.0994879 0.093263 - k6_frac_N10_frac_chain_mem32K_40nm.xml diffeq2.v common 13.72 vpr 65.30 MiB -1 -1 0.24 24060 5 0.12 -1 -1 36392 -1 -1 21 66 0 5 success 574ed3d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-09T03:32:19 gh-actions-runner-vtr-auto-spawned7 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 66864 66 96 779 596 1 464 188 16 16 256 mult_36 auto 27.3 MiB 0.48 3624 65.3 MiB 0.28 0.00 11.5637 -707.838 -11.5637 11.5637 0.68 0.000880597 0.000787259 0.103599 0.0933791 52 9001 47 1.21132e+07 3.11177e+06 805949. 3148.24 9.35 0.507328 0.465281 7273 22 3130 6408 2138671 560556 12.8011 12.8011 -836.267 -12.8011 0 0 1.06067e+06 4143.25 0.32 0.49 0.0806144 0.0757338 - k6_frac_N10_frac_chain_mem32K_40nm.xml LU8PEEng.v common 965.35 vpr 549.67 MiB -1 -1 60.81 458628 98 97.83 -1 -1 115580 -1 -1 2126 114 45 8 success 574ed3d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-09T03:32:19 gh-actions-runner-vtr-auto-spawned7 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 562864 114 102 35713 31804 1 16877 2395 56 56 3136 clb auto 342.9 MiB 64.74 226758 546.2 MiB 113.73 0.88 66.3662 -51126.8 -66.3662 66.3662 48.10 0.123685 0.102249 16.7508 13.6156 92 334565 39 1.8697e+08 1.42409e+08 1.91065e+07 6092.62 499.42 63.0602 51.9533 311164 24 67770 267361 38608684 8495640 75.3223 75.3223 -64384.9 -75.3223 0 0 2.42931e+07 7746.54 10.03 17.43 5.94708 5.11818 - k6_frac_N10_frac_chain_mem32K_40nm.xml LU32PEEng.v common 9212.18 vpr 1.88 GiB -1 -1 183.12 1477020 97 1171.93 -1 -1 358392 -1 -1 7412 114 168 32 success 574ed3d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-09T03:32:19 gh-actions-runner-vtr-auto-spawned7 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 1972512 114 102 120062 107871 1 57253 7828 102 102 10404 clb auto 1113.5 MiB 205.82 1032166 1818.6 MiB 295.71 1.97 63.8192 -332189 -63.8192 63.8192 147.96 0.184511 0.159051 25.9767 21.6409 128 1374306 48 6.36957e+08 5.04159e+08 8.68880e+07 8351.40 6967.98 98.2929 81.9271 1315975 20 210218 907708 231114164 56020304 72.0901 72.0901 -466612 -72.0901 0 0 1.09718e+08 10545.7 32.17 57.39 11.1509 9.85478 - k6_frac_N10_frac_chain_mem32K_40nm.xml mcml.v common 4920.64 vpr 2.24 GiB -1 -1 242.42 1231240 25 3286.11 -1 -1 373116 -1 -1 6438 36 159 27 success 574ed3d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-09T03:32:19 gh-actions-runner-vtr-auto-spawned7 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 2351208 36 356 184794 159441 1 63873 7016 95 95 9025 clb auto 1301.7 MiB 103.93 757989 1792.0 MiB 372.24 2.19 42.5152 -304396 -42.5152 42.5152 80.75 0.14362 0.122085 24.2546 19.4922 146 981647 26 5.4965e+08 4.44764e+08 8.47514e+07 9390.74 659.31 100.791 82.3714 954097 20 214050 488776 92150844 20446221 46.0444 46.0444 -412341 -46.0444 0 0 1.07341e+08 11893.7 33.39 29.33 10.4723 9.20196 - k6_frac_N10_frac_chain_mem32K_40nm.xml mkDelayWorker32B.v common 103.71 vpr 309.33 MiB -1 -1 14.62 121628 5 4.99 -1 -1 47536 -1 -1 464 506 44 0 success 574ed3d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-09T03:32:19 gh-actions-runner-vtr-auto-spawned7 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 316752 506 553 3236 3734 1 2873 1567 50 50 2500 memory auto 56.4 MiB 4.30 15880 309.3 MiB 4.42 0.05 6.98731 -2008.29 -6.98731 6.98731 32.29 0.0154594 0.0138507 1.9858 1.77642 38 24049 14 1.47946e+08 4.91194e+07 6.86579e+06 2746.32 19.77 5.93002 5.44682 22999 14 3994 5552 3734232 912354 7.30155 7.30155 -2414.66 -7.30155 0 0 8.69102e+06 3476.41 4.27 1.42 0.654414 0.617007 - k6_frac_N10_frac_chain_mem32K_40nm.xml mkPktMerge.v common 19.62 vpr 69.36 MiB -1 -1 1.13 28740 2 0.11 -1 -1 37592 -1 -1 30 311 15 0 success 574ed3d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-09T03:32:19 gh-actions-runner-vtr-auto-spawned7 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 71024 311 156 1015 1158 1 965 512 28 28 784 memory auto 31.6 MiB 0.70 8264 69.4 MiB 0.96 0.01 4.32456 -4105.61 -4.32456 4.32456 2.97 0.00467183 0.00416033 0.430331 0.376802 40 14779 15 4.25198e+07 9.83682e+06 2.13295e+06 2720.61 7.25 1.50212 1.34149 13699 13 2690 3000 2312975 646587 4.68771 4.68771 -4838.49 -4.68771 0 0 2.67004e+06 3405.67 1.22 0.75 0.180394 0.167387 - k6_frac_N10_frac_chain_mem32K_40nm.xml mkSMAdapter4B.v common 28.06 vpr 81.55 MiB -1 -1 6.92 55712 5 2.10 -1 -1 42404 -1 -1 175 193 5 0 success 574ed3d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-09T03:32:19 gh-actions-runner-vtr-auto-spawned7 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 83504 193 205 2771 2705 1 1368 578 20 20 400 memory auto 44.5 MiB 3.13 11064 81.5 MiB 1.60 0.02 5.3367 -2602.34 -5.3367 5.3367 1.30 0.00498383 0.00430372 0.555302 0.480663 56 19331 29 2.07112e+07 1.21714e+07 1.41661e+06 3541.53 7.40 2.00711 1.75682 16936 15 4582 11285 1084484 261271 6.19483 6.19483 -3011.66 -6.19483 0 0 1.80858e+06 4521.44 0.66 0.54 0.284346 0.262119 - k6_frac_N10_frac_chain_mem32K_40nm.xml or1200.v common 55.35 vpr 97.26 MiB -1 -1 5.42 65136 8 3.85 -1 -1 44572 -1 -1 247 385 2 1 success 574ed3d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-09T03:32:19 gh-actions-runner-vtr-auto-spawned7 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 99592 385 362 4417 4306 1 2360 997 26 26 676 io auto 58.5 MiB 6.20 29628 95.5 MiB 4.71 0.05 8.51754 -8831.73 -8.51754 8.51754 2.53 0.010931 0.00991716 1.34094 1.19551 90 44934 18 3.69863e+07 1.48038e+07 3.84682e+06 5690.57 22.29 5.50537 4.9229 42227 16 9681 31421 2725654 505427 9.30788 9.30788 -10184.3 -9.30788 0 0 4.81243e+06 7118.99 1.94 1.30 0.604419 0.556677 - k6_frac_N10_frac_chain_mem32K_40nm.xml raygentop.v common 28.56 vpr 81.93 MiB -1 -1 4.24 45228 3 0.85 -1 -1 40356 -1 -1 120 236 1 6 success 574ed3d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-09T03:32:19 gh-actions-runner-vtr-auto-spawned7 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 83900 236 305 3195 3007 1 1534 668 19 19 361 io auto 44.9 MiB 2.43 12076 81.9 MiB 1.98 0.03 4.16779 -2594.62 -4.16779 4.16779 1.27 0.00682009 0.00619218 0.737679 0.663516 62 24810 27 1.72706e+07 9.39128e+06 1.42198e+06 3939.00 11.89 2.59885 2.33622 20845 16 6758 18279 3303405 753074 4.76182 4.76182 -2998.77 -4.76182 0 0 1.76637e+06 4892.99 0.72 1.09 0.328957 0.304143 - k6_frac_N10_frac_chain_mem32K_40nm.xml sha.v common 18.94 vpr 79.61 MiB -1 -1 2.52 47632 4 1.86 -1 -1 41684 -1 -1 132 38 0 0 success 574ed3d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-09T03:32:19 gh-actions-runner-vtr-auto-spawned7 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 81520 38 36 2744 2493 1 1037 206 16 16 256 clb auto 42.7 MiB 2.10 8579 79.6 MiB 0.78 0.01 9.37626 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0.62 0.297596 0.276768 + k6_frac_N10_frac_chain_mem32K_40nm.xml or1200.v common 54.97 vpr 99.77 MiB -1 -1 5.11 64368 8 4.23 -1 -1 44020 -1 -1 246 385 2 1 success 222546b-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.5.0 on Linux-5.10.35-v8 x86_64 2023-08-14T20:40:38 gh-actions-runner-vtr-auto-spawned9 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 102164 385 362 4434 4322 1 2384 996 26 26 676 io auto 61.4 MiB 6.64 28983 98.2 MiB 5.42 0.06 8.37172 -9112.86 -8.37172 8.37172 2.56 0.0110248 0.00998232 1.31728 1.17726 98 44050 20 3.69863e+07 1.47499e+07 4.14103e+06 6125.79 20.29 4.85667 4.334 94440 873926 -1 41212 18 9566 30908 3164356 686578 0 0 3164356 686578 29578 13222 0 0 72367 65374 0 0 90854 72415 0 0 31009 15178 0 0 1496171 249331 0 0 1444377 271058 0 0 29578 0 0 20601 95269 103953 611788 1518 151 9.08584 9.08584 -10627.5 -9.08584 0 0 5.25337e+06 7771.26 1.93 1.44 0.92 -1 -1 1.93 0.589899 0.543851 + k6_frac_N10_frac_chain_mem32K_40nm.xml raygentop.v common 34.02 vpr 85.06 MiB -1 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9.5.0 on Linux-5.10.35-v8 x86_64 2023-08-14T20:40:38 gh-actions-runner-vtr-auto-spawned9 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 84332 38 36 2744 2493 1 1037 206 16 16 256 clb auto 45.4 MiB 1.94 9094 82.4 MiB 0.65 0.01 9.21792 -2353.81 -9.21792 9.21792 0.73 0.00331142 0.00270455 0.233559 0.194445 64 13996 28 1.21132e+07 7.11401e+06 1.00276e+06 3917.05 4.18 1.24483 1.05697 28592 198411 -1 13098 20 4462 10129 410165 69903 0 0 410165 69903 9434 5225 0 0 13925 10360 0 0 20102 13953 0 0 9763 5556 0 0 177863 17407 0 0 179078 17402 0 0 9434 0 0 5177 29416 29934 200934 908 43 11.0117 11.0117 -2816.78 -11.0117 0 0 1.25521e+06 4903.16 0.38 0.36 0.21 -1 -1 0.38 0.252119 0.225839 + k6_frac_N10_frac_chain_mem32K_40nm.xml spree.v common 16.20 vpr 73.40 MiB -1 -1 2.75 34200 16 0.62 -1 -1 37792 -1 -1 61 45 3 1 success 222546b-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.5.0 on Linux-5.10.35-v8 x86_64 2023-08-14T20:40:38 gh-actions-runner-vtr-auto-spawned9 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 75164 45 32 1193 1152 1 791 142 14 14 196 memory auto 35.9 MiB 2.08 6701 73.4 MiB 0.48 0.01 9.99115 -6263.09 -9.99115 9.99115 0.54 0.00189234 0.00153902 0.188901 0.15661 68 13672 36 9.20055e+06 5.32753e+06 806220. 4113.37 6.61 0.854896 0.73372 22432 157909 -1 10994 14 3251 8665 1438729 348701 0 0 1438729 348701 8665 4569 0 0 52575 50375 0 0 57686 52977 0 0 9124 5118 0 0 663046 120257 0 0 647633 115405 0 0 8665 0 0 5553 16471 17743 128862 0 0 11.9152 11.9152 -7594.29 -11.9152 0 0 1.00082e+06 5106.22 0.30 0.44 0.17 -1 -1 0.30 0.131079 0.121143 + k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision0.v common 84.12 vpr 234.10 MiB -1 -1 9.36 101804 5 8.60 -1 -1 68676 -1 -1 710 169 0 0 success 222546b-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.5.0 on Linux-5.10.35-v8 x86_64 2023-08-14T20:40:38 gh-actions-runner-vtr-auto-spawned9 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 239720 169 197 23321 21461 1 6583 1076 33 33 1089 clb auto 176.1 MiB 11.11 40276 209.7 MiB 7.82 0.07 3.01195 -12887.4 -3.01195 3.01195 4.28 0.0244363 0.0193993 2.85012 2.30009 52 61461 45 6.0475e+07 3.82649e+07 3.78249e+06 3473.36 22.49 11.4617 9.58218 119479 787594 -1 56930 14 16322 26018 1106643 215190 0 0 1106643 215190 24119 18070 0 0 40353 27971 0 0 50059 40364 0 0 24753 18901 0 0 498884 55509 0 0 468475 54375 0 0 24119 0 0 7964 35873 36057 200311 2203 2011 3.68983 3.68983 -14900.8 -3.68983 0 0 4.97914e+06 4572.21 1.94 1.56 0.76 -1 -1 1.94 1.44502 1.31076 + k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision1.v common 191.84 vpr 249.03 MiB -1 -1 9.00 122504 3 13.32 -1 -1 76840 -1 -1 680 115 0 40 success 222546b-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.5.0 on Linux-5.10.35-v8 x86_64 2023-08-14T20:40:38 gh-actions-runner-vtr-auto-spawned9 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 255004 115 145 22868 19305 1 9678 980 40 40 1600 mult_36 auto 171.6 MiB 9.76 77004 205.2 MiB 9.78 0.09 5.19755 -22073.5 -5.19755 5.19755 6.63 0.0259841 0.0208785 3.0413 2.51003 82 126300 30 9.16046e+07 5.24886e+07 8.58295e+06 5364.35 112.35 14.9224 12.6212 207228 1787768 -1 112388 18 32382 47406 17863323 3704817 0 0 17863323 3704817 43236 36239 0 0 497779 484785 0 0 525475 498215 0 0 44402 37272 0 0 8440865 1301460 0 0 8311566 1346846 0 0 43236 0 0 11390 136837 144195 546408 4491 3306 5.43847 5.43847 -25862.4 -5.43847 0 0 1.07702e+07 6731.38 4.49 6.19 1.84 -1 -1 4.49 1.87222 1.69564 + k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision2.v common 557.68 vpr 922.09 MiB -1 -1 11.73 197080 3 6.82 -1 -1 154968 -1 -1 1498 149 0 179 success 222546b-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.5.0 on Linux-5.10.35-v8 x86_64 2023-08-14T20:40:38 gh-actions-runner-vtr-auto-spawned9 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 944224 149 182 55416 37075 1 28615 2008 80 80 6400 mult_36 auto 355.8 MiB 21.90 293387 922.1 MiB 56.88 0.43 12.6347 -48890.4 -12.6347 12.6347 90.93 0.0696449 0.0622267 9.86421 8.37904 100 402031 35 3.90281e+08 1.51617e+08 4.24662e+07 6635.34 247.92 35.3247 30.1326 921076 9109410 -1 381938 19 97612 116254 45566380 9304288 0 0 45566380 9304288 113832 100969 0 0 953200 921539 0 0 1075260 956931 0 0 114823 102339 0 0 21695650 3559787 0 0 21613615 3662723 0 0 113832 0 0 16321 105646 98215 381612 2857 3837 14.0212 14.0212 -56760.8 -14.0212 0 0 5.35781e+07 8371.59 36.44 20.05 10.37 -1 -1 36.44 4.62859 4.08229 + k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 2.26 vpr 65.96 MiB -1 -1 0.60 24876 4 0.17 -1 -1 35488 -1 -1 15 11 0 0 success 222546b-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.5.0 on Linux-5.10.35-v8 x86_64 2023-08-14T20:40:38 gh-actions-runner-vtr-auto-spawned9 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 67548 11 2 303 283 2 80 28 7 7 49 clb auto 27.6 MiB 0.19 270 66.0 MiB 0.03 0.00 1.87789 -148.64 -1.87789 1.77818 0.07 0.000246349 0.000190922 0.0158209 0.0129447 26 374 9 1.07788e+06 808410 68696.0 1401.96 0.14 0.0606047 0.0513339 3516 12294 -1 307 9 141 212 3276 1221 0 0 3276 1221 212 188 0 0 289 212 0 0 320 289 0 0 247 190 0 0 1188 153 0 0 1020 189 0 0 212 0 0 71 72 62 663 0 0 2.09646 1.95353 -166.28 -2.09646 0 0 84249.8 1719.38 0.02 0.02 0.01 -1 -1 0.02 0.0177215 0.0165685 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_parmys/vexriscv/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_parmys/vexriscv/config/golden_results.txt index 1b53f3d923a..92d8d40b13c 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_parmys/vexriscv/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_parmys/vexriscv/config/golden_results.txt @@ -1,13 +1,13 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_frac_chain_mem32K_40nm.xml VexRiscvFullNoMmuMaxPerf.v common 59.00 vpr 106.71 MiB -1 -1 6.45 58416 6 4.11 -1 -1 47064 -1 -1 269 116 11 2 success 938cd3a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-08T22:57:19 gh-actions-runner-vtr-auto-spawned55 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 109272 116 145 5652 5257 1 2836 543 26 26 676 memory auto 67.6 MiB 8.68 31862 103.4 MiB 3.23 0.03 6.28132 -17468.7 -6.28132 6.28132 2.40 0.0100159 0.0081564 1.10873 0.92293 90 49385 26 3.69863e+07 2.13175e+07 3.84682e+06 5690.57 22.62 4.84206 4.097 46127 16 11001 31791 8146343 1739203 7.08618 7.08618 -20015.6 -7.08618 0 0 4.81243e+06 7118.99 1.65 2.36 0.605454 0.548702 - k6_frac_N10_frac_chain_mem32K_40nm.xml VexRiscvFullNoMmuNoCache.v common 36.20 vpr 92.21 MiB -1 -1 4.27 50872 6 2.53 -1 -1 43496 -1 -1 197 114 1 2 success 938cd3a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-08T22:57:19 gh-actions-runner-vtr-auto-spawned55 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 94424 114 135 4272 3890 1 2138 449 19 19 361 clb auto 55.4 MiB 8.21 20784 92.2 MiB 1.66 0.03 6.49388 -4976.55 -6.49388 6.49388 1.05 0.00547206 0.00451752 0.508201 0.428498 78 35392 39 1.72706e+07 1.19571e+07 1.72840e+06 4787.81 12.12 2.51131 2.15627 29840 22 8812 23935 2142098 422439 6.95497 6.95497 -5660.22 -6.95497 0 0 2.18872e+06 6062.94 0.73 0.89 0.444955 0.403624 - k6_frac_N10_frac_chain_mem32K_40nm.xml VexRiscvFullNoMmu.v common 71.29 vpr 99.89 MiB -1 -1 6.20 57196 6 3.28 -1 -1 46868 -1 -1 246 116 8 2 success 938cd3a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-08T22:57:19 gh-actions-runner-vtr-auto-spawned55 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 102284 116 145 5259 4876 1 2644 517 21 21 441 clb auto 63.5 MiB 7.78 30145 99.9 MiB 2.55 0.03 6.27731 -12959.4 -6.27731 6.27731 1.24 0.00821875 0.00691698 0.8226 0.690336 98 47373 41 2.24358e+07 1.84339e+07 2.60813e+06 5914.13 41.35 5.1451 4.38532 42086 16 10229 29396 4911853 1115584 7.2064 7.2064 -14736.7 -7.2064 0 0 3.30991e+06 7505.47 1.18 1.65 0.553539 0.504243 - k6_frac_N10_frac_chain_mem32K_40nm.xml VexRiscvFull.v common 56.47 vpr 106.80 MiB -1 -1 8.47 64704 8 6.70 -1 -1 44844 -1 -1 291 116 9 2 success 938cd3a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-08T22:57:19 gh-actions-runner-vtr-auto-spawned55 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 109360 116 145 6279 5893 1 2977 563 22 22 484 clb auto 71.1 MiB 10.09 33446 106.8 MiB 3.28 0.03 6.10865 -15032.9 -6.10865 6.10865 1.55 0.0100789 0.00834819 1.07682 0.900307 92 50517 23 2.50602e+07 2.14072e+07 2.74307e+06 5667.50 16.09 4.19807 3.58598 46412 18 11838 35232 4355775 945941 7.88362 7.88362 -17944.8 -7.88362 0 0 3.48426e+06 7198.87 1.37 1.73 0.741867 0.674107 - k6_frac_N10_frac_chain_mem32K_40nm.xml VexRiscvLinuxBalancedSmp.v common 93.51 vpr 129.90 MiB -1 -1 12.34 81648 8 11.73 -1 -1 54080 -1 -1 408 151 9 2 success 938cd3a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-08T22:57:19 gh-actions-runner-vtr-auto-spawned55 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 133020 151 151 8755 8222 1 4004 721 26 26 676 clb auto 89.5 MiB 13.10 49896 124.8 MiB 4.26 0.04 6.88205 -19586.2 -6.88205 6.88205 2.27 0.0127039 0.0108813 1.34982 1.14465 100 72670 23 3.69863e+07 2.77128e+07 4.20647e+06 6222.59 35.62 7.26575 6.2069 66823 15 15627 48071 6275633 1309031 7.79665 7.79665 -22764.9 -7.79665 0 0 5.30968e+06 7854.55 2.01 2.45 0.954258 0.870915 - k6_frac_N10_frac_chain_mem32K_40nm.xml VexRiscvLinuxBalanced.v common 92.57 vpr 119.96 MiB -1 -1 10.98 78556 8 10.19 -1 -1 53040 -1 -1 383 117 8 2 success 938cd3a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-08T22:57:19 gh-actions-runner-vtr-auto-spawned55 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 122836 117 145 8015 7566 1 3693 655 25 25 625 clb auto 84.5 MiB 12.13 45437 120.0 MiB 3.95 0.04 6.90824 -18661.2 -6.90824 6.90824 1.87 0.0118882 0.0100766 1.23624 1.02932 92 69375 33 3.19446e+07 2.58174e+07 3.56241e+06 5699.85 40.14 5.65969 4.77421 62082 18 15778 48729 7281538 1543213 7.54532 7.54532 -21168.8 -7.54532 0 0 4.52717e+06 7243.48 1.83 2.77 1.0083 0.913459 - k6_frac_N10_frac_chain_mem32K_40nm.xml VexRiscvNoCacheNoMmuMaxPerf.v common 47.49 vpr 97.30 MiB -1 -1 5.12 53280 6 2.93 -1 -1 44532 -1 -1 221 116 3 2 success 938cd3a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-08T22:57:19 gh-actions-runner-vtr-auto-spawned55 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 99640 116 135 4896 4504 1 2526 477 19 19 361 clb auto 60.5 MiB 7.95 25713 97.3 MiB 2.11 0.03 7.97997 -9948.57 -7.97997 7.97997 1.02 0.00711584 0.00603491 0.690767 0.58468 88 39067 44 1.72706e+07 1.43466e+07 1.93293e+06 5354.37 21.16 4.14542 3.55704 34982 17 9228 24572 2452493 498640 8.80223 8.80223 -11135.9 -8.80223 0 0 2.42417e+06 6715.16 0.85 1.03 0.524819 0.47938 - k6_frac_N10_frac_chain_mem32K_40nm.xml VexRiscvSecure.v common 106.14 vpr 153.69 MiB -1 -1 12.64 90500 8 13.90 -1 -1 55748 -1 -1 541 116 9 0 success 938cd3a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-08T22:57:19 gh-actions-runner-vtr-auto-spawned55 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 157380 116 145 9593 9215 1 4913 811 30 30 900 clb auto 101.9 MiB 18.88 65959 136.4 MiB 6.45 0.07 8.44325 -21002.4 -8.44325 8.44325 3.23 0.0173685 0.0140207 1.78028 1.48286 92 101197 31 4.8774e+07 3.40887e+07 5.26086e+06 5845.40 33.04 8.14857 6.96509 92037 21 23499 76116 7776602 1477116 8.96194 8.96194 -23680.8 -8.96194 0 0 6.68445e+06 7427.16 2.78 3.32 1.35238 1.21458 - k6_frac_N10_frac_chain_mem32K_40nm.xml VexRiscvSmallAndProductiveICache.v common 21.92 vpr 78.23 MiB -1 -1 2.66 38616 5 1.03 -1 -1 40176 -1 -1 113 71 3 0 success 938cd3a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-08T22:57:19 gh-actions-runner-vtr-auto-spawned55 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 80112 71 104 2165 2136 1 1206 291 15 15 225 clb auto 40.9 MiB 3.87 10306 78.2 MiB 0.79 0.01 6.09155 -5388.76 -6.09155 6.09155 0.55 0.00317508 0.00257552 0.272985 0.226767 74 16829 28 1.03862e+07 7.73402e+06 1.00046e+06 4446.50 9.24 1.77018 1.50525 15404 22 4943 12441 1265568 285354 6.97246 6.97246 -6174.28 -6.97246 0 0 1.25506e+06 5578.04 0.37 0.51 0.246516 0.223344 - k6_frac_N10_frac_chain_mem32K_40nm.xml VexRiscvSmallAndProductive.v common 15.18 vpr 76.95 MiB -1 -1 2.29 37700 5 1.05 -1 -1 40148 -1 -1 105 71 1 0 success 938cd3a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-08T22:57:19 gh-actions-runner-vtr-auto-spawned55 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 78796 71 101 2015 1984 1 1128 278 14 14 196 clb auto 39.6 MiB 3.84 9353 76.9 MiB 0.57 0.01 5.82335 -2884.99 -5.82335 5.82335 0.48 0.00239354 0.0020261 0.188673 0.161264 68 15337 43 9.20055e+06 6.20687e+06 806220. 4113.37 3.63 1.12762 0.967928 13148 21 4285 10901 545872 111453 6.74119 6.74119 -3442.4 -6.74119 0 0 1.00082e+06 5106.22 0.29 0.37 0.231615 0.211691 - k6_frac_N10_frac_chain_mem32K_40nm.xml VexRiscvSmallestNoCsr.v common 12.07 vpr 73.65 MiB -1 -1 1.41 33232 5 0.45 -1 -1 38648 -1 -1 78 68 1 0 success 938cd3a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-08T22:57:19 gh-actions-runner-vtr-auto-spawned55 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 75420 68 101 1681 1650 1 876 248 13 13 169 clb auto 36.3 MiB 2.85 6585 73.7 MiB 0.44 0.01 5.68658 -2537.15 -5.68658 5.68658 0.37 0.00206022 0.00169401 0.152306 0.129814 62 10680 25 6.63067e+06 4.75173e+06 606217. 3587.08 4.00 0.900256 0.772946 9501 16 3134 7329 337783 77661 6.19204 6.19204 -2934.03 -6.19204 0 0 753618. 4459.28 0.22 0.21 0.141993 0.130831 - k6_frac_N10_frac_chain_mem32K_40nm.xml VexRiscvSmallest.v common 13.66 vpr 74.36 MiB -1 -1 2.00 35448 5 0.58 -1 -1 39320 -1 -1 87 71 1 0 success 938cd3a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-08T22:57:19 gh-actions-runner-vtr-auto-spawned55 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 76144 71 101 1831 1800 1 936 260 13 13 169 clb auto 37.0 MiB 2.84 7278 74.4 MiB 0.51 0.01 5.35779 -2602.93 -5.35779 5.35779 0.39 0.00222245 0.00183629 0.172541 0.145834 62 12135 41 6.63067e+06 5.23678e+06 606217. 3587.08 4.48 1.07627 0.918243 10530 18 3652 9388 417884 91751 5.94617 5.94617 -2940.41 -5.94617 0 0 753618. 4459.28 0.23 0.26 0.171152 0.156995 + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops crit_path_total_internal_heap_pushes crit_path_total_internal_heap_pops crit_path_total_external_heap_pushes crit_path_total_external_heap_pops crit_path_total_external_SOURCE_pushes crit_path_total_external_SOURCE_pops crit_path_total_internal_SOURCE_pushes crit_path_total_internal_SOURCE_pops crit_path_total_external_SINK_pushes crit_path_total_external_SINK_pops crit_path_total_internal_SINK_pushes crit_path_total_internal_SINK_pops crit_path_total_external_IPIN_pushes crit_path_total_external_IPIN_pops crit_path_total_internal_IPIN_pushes crit_path_total_internal_IPIN_pops crit_path_total_external_OPIN_pushes crit_path_total_external_OPIN_pops crit_path_total_internal_OPIN_pushes crit_path_total_internal_OPIN_pops crit_path_total_external_CHANX_pushes crit_path_total_external_CHANX_pops crit_path_total_internal_CHANX_pushes crit_path_total_internal_CHANX_pops crit_path_total_external_CHANY_pushes crit_path_total_external_CHANY_pops crit_path_total_internal_CHANY_pushes crit_path_total_internal_CHANY_pops crit_path_rt_node_SOURCE_pushes crit_path_rt_node_SINK_pushes crit_path_rt_node_IPIN_pushes crit_path_rt_node_OPIN_pushes crit_path_rt_node_CHANX_pushes crit_path_rt_node_CHANY_pushes crit_path_adding_all_rt crit_path_adding_high_fanout_rt crit_path_total_number_of_adding_all_rt_from_calling_high_fanout_rt critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time + k6_frac_N10_frac_chain_mem32K_40nm.xml VexRiscvFullNoMmuMaxPerf.v common 64.88 vpr 128.21 MiB -1 -1 5.51 56944 6 4.13 -1 -1 45592 -1 -1 267 116 11 2 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 131292 116 145 5676 5281 1 2880 541 26 26 676 memory auto 70.6 MiB 8.31 32475 106.4 MiB 2.38 0.03 6.23402 -17566.9 -6.23402 6.23402 1.94 0.0070485 0.00607727 0.741486 0.630744 98 49395 22 3.69863e+07 2.12097e+07 4.14103e+06 6125.79 33.47 4.07254 3.50931 94440 873926 -1 46284 20 10741 29862 8239617 1825580 0 0 8239617 1825580 29017 14418 0 0 159020 151600 0 0 175005 159675 0 0 30413 15917 0 0 3877562 742206 0 0 3968600 741764 0 0 29017 0 0 18830 107525 103683 646143 1071 0 7.03887 7.03887 -20131.9 -7.03887 0 0 5.25337e+06 7771.26 1.43 1.76 0.60 -1 -1 1.43 0.499727 0.457326 + k6_frac_N10_frac_chain_mem32K_40nm.xml VexRiscvFullNoMmuNoCache.v common 37.51 vpr 95.39 MiB -1 -1 3.81 50356 5 2.44 -1 -1 43900 -1 -1 193 114 1 2 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 97676 114 135 4317 3935 1 2156 445 19 19 361 clb auto 58.5 MiB 7.58 21032 95.4 MiB 1.65 0.02 5.99361 -4843.86 -5.99361 5.99361 0.98 0.00515553 0.00443653 0.501946 0.433605 90 32124 21 1.72706e+07 1.17415e+07 1.96753e+06 5450.21 15.46 2.83783 2.46134 46963 400631 -1 29757 18 8331 22425 2030709 381003 0 0 2030709 381003 22019 10598 0 0 64450 58617 0 0 77020 64612 0 0 22866 11539 0 0 923028 119812 0 0 921326 115825 0 0 22019 0 0 14243 76637 81020 528508 463 86 6.62888 6.62888 -5559.19 -6.62888 0 0 2.46158e+06 6818.79 0.74 0.68 0.28 -1 -1 0.74 0.341242 0.314329 + k6_frac_N10_frac_chain_mem32K_40nm.xml VexRiscvFullNoMmu.v common 57.71 vpr 102.87 MiB -1 -1 5.31 56116 6 3.85 -1 -1 45164 -1 -1 245 116 8 2 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 105340 116 145 5285 4902 1 2688 516 21 21 441 clb auto 66.4 MiB 7.51 29441 102.9 MiB 2.49 0.03 6.2684 -13279.4 -6.2684 6.2684 1.21 0.007719 0.00680635 0.776241 0.661906 90 46305 20 2.24358e+07 1.838e+07 2.42300e+06 5494.32 29.74 3.55861 3.06953 57512 493860 -1 41847 17 10913 31567 6557781 1496992 0 0 6557781 1496992 30439 14895 0 0 139536 131528 0 0 157588 140031 0 0 31649 16448 0 0 3066642 593403 0 0 3131927 600687 0 0 30439 0 0 20129 120887 117466 753420 1237 230 7.19755 7.19755 -15181.4 -7.19755 0 0 3.03186e+06 6874.97 0.84 1.53 0.34 -1 -1 0.84 0.430871 0.397368 + k6_frac_N10_frac_chain_mem32K_40nm.xml VexRiscvFull.v common 65.23 vpr 109.70 MiB -1 -1 7.16 64136 8 6.89 -1 -1 44956 -1 -1 291 116 9 2 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 112332 116 145 6279 5893 1 2977 563 22 22 484 clb auto 74.0 MiB 10.04 34942 109.7 MiB 2.94 0.04 6.20851 -14914.4 -6.20851 6.20851 1.41 0.00939049 0.008277 0.920872 0.780402 90 57651 42 2.50602e+07 2.14072e+07 2.69141e+06 5560.77 28.54 4.00707 3.43939 63730 551298 -1 48602 15 12647 38372 5716781 1239596 0 0 5716781 1239596 37034 18017 0 0 149183 139455 0 0 170276 149782 0 0 38703 20155 0 0 2677058 453249 0 0 2644527 458938 0 0 37034 0 0 25095 125573 128191 767409 1603 256 7.69362 7.69362 -17716.1 -7.69362 0 0 3.36730e+06 6957.24 1.04 1.51 0.40 -1 -1 1.04 0.522002 0.481045 + k6_frac_N10_frac_chain_mem32K_40nm.xml VexRiscvLinuxBalancedSmp.v common 86.32 vpr 134.07 MiB -1 -1 11.51 81324 8 12.12 -1 -1 54368 -1 -1 419 151 9 2 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 137288 151 151 8780 8247 1 3972 732 26 26 676 clb auto 93.1 MiB 12.63 48109 128.1 MiB 5.44 0.05 6.76834 -19553.8 -6.76834 6.76834 2.29 0.0126783 0.0112312 1.48725 1.27117 94 73908 34 3.69863e+07 2.83056e+07 3.99964e+06 5916.62 30.07 7.14272 6.12223 92412 832514 -1 66265 20 16198 50360 7010537 1408407 0 0 7010537 1408407 48048 21958 0 0 157182 141527 0 0 187654 158091 0 0 50121 24345 0 0 3305295 526491 0 0 3262237 535995 0 0 48048 0 0 32832 184847 195029 1123641 2632 918 7.61751 7.61751 -22550.2 -7.61751 0 0 5.03706e+06 7451.27 1.87 2.27 0.67 -1 -1 1.87 0.903198 0.824295 + k6_frac_N10_frac_chain_mem32K_40nm.xml VexRiscvLinuxBalanced.v common 84.79 vpr 141.32 MiB -1 -1 9.79 78040 8 11.07 -1 -1 52520 -1 -1 386 117 8 2 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 144708 117 145 8035 7586 1 3741 658 25 25 625 clb auto 87.5 MiB 11.33 46348 123.1 MiB 4.08 0.04 6.77426 -17924.6 -6.77426 6.77426 1.76 0.0112978 0.00996361 1.23067 1.02828 98 68686 24 3.19446e+07 2.59791e+07 3.76301e+06 6020.82 35.49 6.14271 5.30074 85587 788084 -1 62342 16 15022 46532 5600305 1080239 0 0 5600305 1080239 44700 19944 0 0 137920 126656 0 0 163202 138490 0 0 46374 22309 0 0 2542487 395547 0 0 2665622 377293 0 0 44700 0 0 30538 175502 181322 1075323 2085 684 7.5086 7.5086 -20087.7 -7.5086 0 0 4.77614e+06 7641.82 1.61 1.82 0.60 -1 -1 1.61 0.721274 0.663362 + k6_frac_N10_frac_chain_mem32K_40nm.xml VexRiscvNoCacheNoMmuMaxPerf.v common 43.70 vpr 100.00 MiB -1 -1 4.60 52812 6 2.85 -1 -1 46048 -1 -1 229 116 3 2 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 102396 116 135 4927 4535 1 2511 485 20 20 400 clb auto 63.2 MiB 7.69 26367 100.0 MiB 2.38 0.03 8.07512 -10178 -8.07512 8.07512 1.26 0.00757252 0.00673756 0.761595 0.66214 88 41879 46 2.07112e+07 1.47777e+07 2.14223e+06 5355.56 17.22 3.31859 2.892 51756 436964 -1 36872 14 9657 26595 2902405 597177 0 0 2902405 597177 25826 12485 0 0 87118 80478 0 0 103463 87772 0 0 26727 13986 0 0 1321287 202563 0 0 1337984 199893 0 0 25826 0 0 16679 92622 90607 594761 1024 116 8.84246 8.84246 -11842.1 -8.84246 0 0 2.68708e+06 6717.69 0.84 0.87 0.32 -1 -1 0.84 0.388273 0.361129 + k6_frac_N10_frac_chain_mem32K_40nm.xml VexRiscvSecure.v common 123.28 vpr 174.73 MiB -1 -1 11.23 90340 8 15.83 -1 -1 55752 -1 -1 536 116 9 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 178920 116 145 9526 9148 1 4817 806 29 29 841 clb auto 103.8 MiB 16.71 67057 138.4 MiB 6.92 0.07 8.23105 -22363.4 -8.23105 8.23105 2.59 0.0177376 0.0138339 1.75089 1.4575 100 98195 36 4.4999e+07 3.38192e+07 5.23311e+06 6222.49 54.31 9.80032 8.2998 117100 1100547 -1 90828 16 21504 69437 7228840 1410971 0 0 7228840 1410971 67841 28757 0 0 159956 143348 0 0 196419 160349 0 0 70905 32109 0 0 3376779 519396 0 0 3356940 527012 0 0 67841 0 0 48142 342593 358065 1890382 1778 913 9.0399 9.0399 -25386.5 -9.0399 0 0 6.60776e+06 7857.02 2.57 2.56 0.83 -1 -1 2.57 1.00849 0.916375 + k6_frac_N10_frac_chain_mem32K_40nm.xml VexRiscvSmallAndProductiveICache.v common 20.80 vpr 80.91 MiB -1 -1 2.28 38028 5 0.99 -1 -1 40544 -1 -1 113 71 3 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 82848 71 104 2159 2130 1 1200 291 15 15 225 clb auto 43.6 MiB 3.73 10158 80.9 MiB 0.71 0.01 6.08029 -5301.44 -6.08029 6.08029 0.64 0.00287972 0.00242977 0.236059 0.203245 76 15343 23 1.03862e+07 7.73402e+06 1.01936e+06 4530.48 9.03 1.56319 1.34483 26934 203922 -1 14591 20 4125 10966 783383 190233 0 0 783383 190233 10966 5340 0 0 31336 28085 0 0 37045 31460 0 0 11508 5916 0 0 346862 59726 0 0 345666 59706 0 0 10966 0 0 7105 26436 31276 233177 0 0 6.83474 6.83474 -6050.63 -6.83474 0 0 1.27523e+06 5667.70 0.38 0.39 0.15 -1 -1 0.38 0.235387 0.215229 + k6_frac_N10_frac_chain_mem32K_40nm.xml VexRiscvSmallAndProductive.v common 18.27 vpr 80.09 MiB -1 -1 2.01 37036 5 1.03 -1 -1 40576 -1 -1 103 71 1 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 82012 71 101 2029 1998 1 1149 276 14 14 196 clb auto 42.5 MiB 3.95 9925 80.1 MiB 0.70 0.01 5.96792 -3020.09 -5.96792 5.96792 0.73 0.00238755 0.0020267 0.219054 0.188116 70 15577 24 9.20055e+06 6.09908e+06 825316. 4210.80 6.65 1.46095 1.25262 22820 164109 -1 13619 16 4297 11506 554018 116973 0 0 554018 116973 11506 5421 0 0 20811 17933 0 0 26009 20833 0 0 11822 6223 0 0 238344 32838 0 0 245526 33725 0 0 11506 0 0 7510 34701 34676 267087 0 0 6.52746 6.52746 -3449.13 -6.52746 0 0 1.03831e+06 5297.50 0.32 0.36 0.13 -1 -1 0.32 0.239172 0.21901 + k6_frac_N10_frac_chain_mem32K_40nm.xml VexRiscvSmallestNoCsr.v common 10.43 vpr 76.50 MiB -1 -1 1.27 32388 5 0.45 -1 -1 38936 -1 -1 78 68 1 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 78332 68 101 1681 1650 1 876 248 13 13 169 clb auto 39.1 MiB 2.77 6512 76.5 MiB 0.44 0.01 5.70073 -2444.17 -5.70073 5.70073 0.35 0.00172071 0.00143399 0.134244 0.115054 58 11578 39 6.63067e+06 4.75173e+06 566871. 3354.27 2.88 0.878177 0.75704 17372 111011 -1 9441 17 3091 7604 360968 84095 0 0 360968 84095 7604 3771 0 0 15038 13150 0 0 18566 15048 0 0 7861 4183 0 0 155276 23425 0 0 156623 24518 0 0 7604 0 0 4699 18200 19268 154523 0 0 6.25805 6.25805 -2894.59 -6.25805 0 0 722590. 4275.68 0.21 0.20 0.08 -1 -1 0.21 0.129797 0.121165 + k6_frac_N10_frac_chain_mem32K_40nm.xml VexRiscvSmallest.v common 13.21 vpr 77.97 MiB -1 -1 1.77 34788 5 0.59 -1 -1 39144 -1 -1 86 71 1 0 success v8.0.0-8315-ga34adbee3 release IPO VTR_ASSERT_LEVEL=2 GNU 11.3.0 on Linux-5.19.0-46-generic x86_64 2023-07-20T17:59:21 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 79840 71 101 1846 1815 1 954 259 13 13 169 clb auto 40.6 MiB 3.05 7562 78.0 MiB 0.52 0.01 5.72864 -2603.47 -5.72864 5.72864 0.34 0.00221769 0.00193827 0.175849 0.152687 64 12034 24 6.63067e+06 5.18288e+06 627572. 3713.44 4.42 1.02236 0.888929 18044 121887 -1 11154 21 3897 10102 487871 110122 0 0 487871 110122 10102 4980 0 0 19264 16151 0 0 25264 19294 0 0 10508 5573 0 0 209696 32175 0 0 213037 31949 0 0 10102 0 0 6442 25724 28918 216576 0 0 6.19061 6.19061 -3020.47 -6.19061 0 0 786660. 4654.79 0.21 0.27 0.09 -1 -1 0.21 0.167357 0.15474 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_parmys/vtr_benchmarks/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_parmys/vtr_benchmarks/config/golden_results.txt index 81611f470d5..e0699ac88f7 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_parmys/vtr_benchmarks/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_parmys/vtr_benchmarks/config/golden_results.txt @@ -1,22 +1,22 @@ -arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops crit_path_total_internal_heap_pushes crit_path_total_internal_heap_pops crit_path_total_external_heap_pushes crit_path_total_external_heap_pops crit_path_total_external_SOURCE_pushes crit_path_total_external_SOURCE_pops crit_path_total_internal_SOURCE_pushes crit_path_total_internal_SOURCE_pops crit_path_total_external_SINK_pushes crit_path_total_external_SINK_pops crit_path_total_internal_SINK_pushes crit_path_total_internal_SINK_pops crit_path_total_external_IPIN_pushes crit_path_total_external_IPIN_pops crit_path_total_internal_IPIN_pushes crit_path_total_internal_IPIN_pops crit_path_total_external_OPIN_pushes crit_path_total_external_OPIN_pops crit_path_total_internal_OPIN_pushes crit_path_total_internal_OPIN_pops crit_path_total_external_CHANX_pushes crit_path_total_external_CHANX_pops crit_path_total_internal_CHANX_pushes crit_path_total_internal_CHANX_pops crit_path_total_external_CHANY_pushes crit_path_total_external_CHANY_pops crit_path_total_internal_CHANY_pushes crit_path_total_internal_CHANY_pops crit_path_rt_node_SOURCE_pushes crit_path_rt_node_SINK_pushes crit_path_rt_node_IPIN_pushes crit_path_rt_node_OPIN_pushes crit_path_rt_node_CHANX_pushes crit_path_rt_node_CHANY_pushes crit_path_adding_all_rt crit_path_adding_high_fanout_rt crit_path_total_number_of_adding_all_rt_from_calling_high_fanout_rt critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6_frac_N10_frac_chain_mem32K_40nm.xml arm_core.v common 303.43 vpr 270.95 MiB -1 -1 16.29 121484 20 39.33 -1 -1 66844 -1 -1 847 133 25 0 success v8.0.0-7664-g40e3ed324 Release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-24T17:06:12 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_2/vtr-verilog-to-routing/vtr_flow/tasks 277452 133 179 14247 14104 1 7175 1184 36 36 1296 clb memory auto 141.5 MiB 25.83 124164 173.1 MiB 9.15 0.08 20.1971 -196187 -20.1971 20.1971 3.45 0.0211573 0.0182062 2.54004 2.10815 116 187778 49 7.21828e+07 5.93492e+07 9.38276e+06 7239.79 178.06 18.6961 15.564 194868 1992610 -1 167737 15 31085 121145 37714750 8673095 0 0 37714750 8673095 107887 41875 0 0 569808 536307 0 0 656693 578754 0 0 111873 46731 0 0 18163012 3686808 0 0 18105477 3782620 0 0 107887 0 0 79519 705051 709713 3730693 15151 3369 22.9198 22.9198 -216591 -22.9198 0 0 1.18192e+07 9119.77 4.56 9.77 2.49 -1 -1 4.56 1.69371 1.5228 -k6_frac_N10_frac_chain_mem32K_40nm.xml bgm.v common 463.35 vpr 649.32 MiB -1 -1 32.28 623864 14 66.82 -1 -1 121408 -1 -1 2706 257 0 11 success v8.0.0-7664-g40e3ed324 Release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-24T17:06:12 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_2/vtr-verilog-to-routing/vtr_flow/tasks 664904 257 32 35747 33389 1 19410 3006 63 63 3969 clb auto 361.5 MiB 76.76 245040 649.3 MiB 72.19 0.42 17.8964 -23643.6 -17.8964 17.8964 38.57 0.0743246 0.0592819 10.3634 8.3391 74 387775 30 2.36641e+08 1.50195e+08 2.02178e+07 5093.92 114.51 33.0289 27.2174 502298 4195434 -1 374011 20 94787 429147 30264915 5033607 0 0 30264915 5033607 429147 157165 0 0 673776 546114 0 0 986423 677468 0 0 452049 179998 0 0 13780740 1723793 0 0 13942780 1749069 0 0 429147 0 0 347343 2299357 2206577 15348486 0 0 20.1551 20.1551 -26250.3 -20.1551 0 0 2.53694e+07 6391.88 8.09 11.30 2.85 -1 -1 8.09 4.76229 4.1903 -k6_frac_N10_frac_chain_mem32K_40nm.xml blob_merge.v common 61.83 parmys 253.89 MiB -1 -1 8.05 259980 5 3.70 -1 -1 53948 -1 -1 494 36 0 0 success v8.0.0-7664-g40e3ed324 Release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-24T17:06:12 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_2/vtr-verilog-to-routing/vtr_flow/tasks 131448 36 100 10175 7629 1 2793 630 28 28 784 clb auto 94.9 MiB 14.23 40406 128.4 MiB 2.83 0.03 13.8907 -2243.5 -13.8907 13.8907 1.93 0.0107285 0.00949865 1.04582 0.914909 70 69977 43 4.25198e+07 2.66236e+07 3.59791e+06 4589.17 20.67 4.29929 3.71573 94322 733910 -1 60173 14 12132 62793 2496462 359922 0 0 2496462 359922 62793 16429 0 0 77899 63275 0 0 112669 77914 0 0 65145 19905 0 0 1072930 86421 0 0 1105026 95978 0 0 62793 0 0 52662 281277 312206 1652688 0 0 15.7475 15.7475 -2567.9 -15.7475 0 0 4.52633e+06 5773.37 1.24 1.12 0.48 -1 -1 1.24 0.702145 0.639391 -k6_frac_N10_frac_chain_mem32K_40nm.xml boundtop.v common 15.40 vpr 61.35 MiB -1 -1 8.22 44600 3 0.75 -1 -1 37160 -1 -1 44 196 1 0 success v8.0.0-7664-g40e3ed324 Release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-24T17:06:12 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_2/vtr-verilog-to-routing/vtr_flow/tasks 62820 196 193 1202 1347 1 614 434 15 15 225 io auto 23.4 MiB 0.82 2959 61.3 MiB 0.68 0.01 2.02269 -977.766 -2.02269 2.02269 0.69 0.00255497 0.00231037 0.223592 0.201957 38 6350 23 1.03862e+07 2.91934e+06 544116. 2418.30 1.91 0.711283 0.650508 21558 109668 -1 5544 15 1869 2868 259845 65220 0 0 259845 65220 2868 2116 0 0 10275 9550 0 0 11163 10288 0 0 2963 2282 0 0 118344 20346 0 0 114232 20638 0 0 2868 0 0 1006 2362 3248 20396 0 0 2.47022 2.47022 -1208.67 -2.47022 0 0 690508. 3068.92 0.16 0.11 0.06 -1 -1 0.16 0.073293 0.0696721 -k6_frac_N10_frac_chain_mem32K_40nm.xml ch_intrinsics.v common 3.29 vpr 56.37 MiB -1 -1 0.32 18660 3 0.08 -1 -1 32728 -1 -1 68 99 1 0 success v8.0.0-7664-g40e3ed324 Release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-24T17:06:12 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_2/vtr-verilog-to-routing/vtr_flow/tasks 57724 99 130 343 473 1 217 298 12 12 144 clb auto 18.0 MiB 0.24 494 56.4 MiB 0.13 0.00 1.48813 -107.16 -1.48813 1.48813 0.22 0.000320411 0.000288053 0.026672 0.0240292 46 1057 9 5.66058e+06 4.21279e+06 378966. 2631.71 1.17 0.108571 0.0998422 13518 73784 -1 1006 11 447 729 31364 10104 0 0 31364 10104 729 514 0 0 1918 1723 0 0 2674 1919 0 0 768 583 0 0 12561 3136 0 0 12714 2229 0 0 729 0 0 282 413 454 3102 0 0 1.91436 1.91436 -129.917 -1.91436 0 0 486261. 3376.82 0.14 0.04 0.07 -1 -1 0.14 0.0236973 0.0224613 -k6_frac_N10_frac_chain_mem32K_40nm.xml diffeq1.v common 9.07 vpr 59.45 MiB -1 -1 0.23 22220 5 0.16 -1 -1 33756 -1 -1 31 162 0 5 success v8.0.0-7664-g40e3ed324 Release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-24T17:06:12 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_2/vtr-verilog-to-routing/vtr_flow/tasks 60872 162 96 1067 884 1 657 294 16 16 256 mult_36 auto 21.6 MiB 0.30 4819 59.4 MiB 0.32 0.00 15.2767 -1149.24 -15.2767 15.2767 0.48 0.000870475 0.000772105 0.0943914 0.0846463 56 10602 26 1.21132e+07 3.65071e+06 870502. 3400.40 5.63 0.566431 0.52029 27064 172478 -1 8985 22 3262 5277 1807822 527093 0 0 1807822 527093 5277 3918 0 0 79260 78063 0 0 84646 79630 0 0 5451 4198 0 0 823992 184597 0 0 809196 176687 0 0 5277 0 0 2040 5552 5598 30559 0 0 17.583 17.583 -1360.67 -17.583 0 0 1.11200e+06 4343.75 0.23 0.32 0.10 -1 -1 0.23 0.0716202 0.0675122 -k6_frac_N10_frac_chain_mem32K_40nm.xml diffeq2.v common 6.94 vpr 57.88 MiB -1 -1 0.15 21520 5 0.08 -1 -1 33296 -1 -1 21 66 0 5 success v8.0.0-7664-g40e3ed324 Release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-24T17:06:12 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_2/vtr-verilog-to-routing/vtr_flow/tasks 59264 66 96 779 596 1 464 188 16 16 256 mult_36 auto 19.8 MiB 0.35 3692 57.9 MiB 0.19 0.00 11.7553 -701.572 -11.7553 11.7553 0.47 0.000587222 0.000519756 0.0612421 0.0548134 46 8762 34 1.21132e+07 3.11177e+06 727244. 2840.79 3.52 0.26415 0.242754 25532 145267 -1 7364 21 3656 7591 2979023 720533 0 0 2979023 720533 7591 5578 0 0 104001 102820 0 0 116457 104645 0 0 8377 6075 0 0 1371364 245643 0 0 1371233 255772 0 0 7591 0 0 3935 9538 9804 46382 0 0 12.9946 12.9946 -850.058 -12.9946 0 0 934704. 3651.19 0.29 0.49 0.14 -1 -1 0.29 0.059237 0.0561242 -k6_frac_N10_frac_chain_mem32K_40nm.xml mkDelayWorker32B.v common 67.02 vpr 303.64 MiB -1 -1 8.53 118628 5 2.85 -1 -1 44492 -1 -1 464 506 44 0 success v8.0.0-7664-g40e3ed324 Release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-24T17:06:12 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_2/vtr-verilog-to-routing/vtr_flow/tasks 310924 506 553 3236 3734 1 2873 1567 50 50 2500 memory auto 48.7 MiB 3.31 16530 303.6 MiB 3.48 0.04 6.5587 -2064.11 -6.5587 6.5587 19.96 0.0105965 0.00971204 1.43432 1.30219 38 25029 15 1.47946e+08 4.91194e+07 6.86579e+06 2746.32 13.81 4.2998 4.00207 258216 1426232 -1 23911 15 4399 5668 4225366 1062649 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9118338 117847 105453 0 0 974905 936173 0 0 1099495 978614 0 0 118863 106726 0 0 21396619 3441321 0 0 21277633 3550051 0 0 117847 0 0 16517 101953 97518 383293 2408 3049 13.7193 13.7193 -54713.6 -13.7193 0 0 5.14892e+07 8045.19 19.05 14.36 7.90 -1 -1 19.05 3.85384 3.4304 + k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 2.74 vpr 66.61 MiB -1 -1 0.72 25192 4 0.20 -1 -1 35396 -1 -1 15 11 0 0 success 168f007-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.5.0 on Linux-5.10.35-v8 x86_64 2023-09-10T13:48:04 gh-actions-runner-vtr-auto-spawned11 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 68212 11 2 303 283 2 80 28 7 7 49 clb auto 28.2 MiB 0.26 262 66.6 MiB 0.05 0.00 1.86328 -148.615 -1.86328 1.77125 0.09 0.000644587 0.000556823 0.0270831 0.0242477 26 348 20 1.07788e+06 808410 68696.0 1401.96 0.20 0.118843 0.10307 3516 12294 -1 329 11 202 331 5307 1941 0 0 5307 1941 331 277 0 0 422 331 0 0 488 422 0 0 395 317 0 0 1902 351 0 0 1769 243 0 0 331 0 0 129 177 156 1255 0 0 1.98243 1.82748 -169.552 -1.98243 0 0 84249.8 1719.38 0.02 0.04 0.02 -1 -1 0.02 0.0301697 0.0278049 + k6_frac_N10_frac_chain_mem32K_40nm.xml LU8PEEng.v common 905.63 vpr 620.64 MiB -1 -1 69.48 456068 98 119.41 -1 -1 115212 -1 -1 2126 114 45 8 success 168f007-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.5.0 on Linux-5.10.35-v8 x86_64 2023-09-10T13:48:04 gh-actions-runner-vtr-auto-spawned11 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 635532 114 102 35713 31804 1 16877 2395 56 56 3136 clb auto 345.2 MiB 94.23 226044 552.6 MiB 99.29 0.74 66.0506 -53632.5 -66.0506 66.0506 57.74 0.12194 0.106592 16.3256 13.0209 96 340308 28 1.8697e+08 1.42409e+08 1.98848e+07 6340.81 384.45 73.8666 58.9705 439150 4183214 -1 313293 23 65139 255112 41062722 8870199 0 0 41062722 8870199 248386 84504 0 0 698308 624575 0 0 868831 704028 0 0 258041 97160 0 0 19237817 3628633 0 0 19751339 3731299 0 0 248386 0 0 190255 880054 894728 5690042 7245 6009 74.2404 74.2404 -68009 -74.2404 0 0 2.48675e+07 7929.69 8.85 16.42 3.73 -1 -1 8.85 5.49143 4.76242 + k6_frac_N10_frac_chain_mem32K_40nm.xml LU32PEEng.v common 4134.34 vpr 2.22 GiB -1 -1 221.44 1458720 97 1028.36 -1 -1 357268 -1 -1 7412 114 168 32 success 168f007-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.5.0 on Linux-5.10.35-v8 x86_64 2023-09-10T13:48:04 gh-actions-runner-vtr-auto-spawned11 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 2331612 114 102 120062 107871 1 57253 7828 102 102 10404 clb auto 1117.4 MiB 211.75 1026779 1828.0 MiB 404.86 2.73 64.7172 -343930 -64.7172 64.7172 124.75 0.260214 0.227779 37.2498 31.0866 132 1348522 23 6.36957e+08 5.04159e+08 8.88356e+07 8538.60 1823.63 167.357 136.322 1719732 19599881 -1 1294641 20 206456 897577 259367945 68896390 0 0 259367945 68896390 844868 255276 0 0 2617408 2394583 0 0 3226115 2635699 0 0 877238 309016 0 0 124439792 31032970 0 0 127362524 32268846 0 0 844868 0 0 663878 3915548 3927216 21958437 54562 195130 73.1695 73.1695 -478357 -73.1695 0 0 1.13733e+08 10931.6 53.37 107.33 19.90 -1 -1 53.37 17.5593 15.1778 + k6_frac_N10_frac_chain_mem32K_40nm.xml mcml.v common 5229.44 vpr 2.03 GiB -1 -1 291.83 1242876 25 3396.92 -1 -1 371272 -1 -1 6438 36 159 27 success 168f007-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.5.0 on Linux-5.10.35-v8 x86_64 2023-09-10T13:48:04 gh-actions-runner-vtr-auto-spawned11 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 2132892 36 356 184794 159441 1 63873 7016 95 95 9025 clb auto 1304.2 MiB 148.63 762501 1810.7 MiB 473.82 3.10 41.756 -304360 -41.756 41.756 103.60 0.24258 0.193661 36.4276 29.8985 142 999026 44 5.4965e+08 4.44764e+08 8.24996e+07 9141.23 574.52 141.95 117.167 1545258 18129248 -1 961473 21 220892 499165 103698408 24915605 0 0 103698408 24915605 438773 253639 0 0 1517742 1393247 0 0 1870287 1525002 0 0 450080 273409 0 0 49548980 10620812 0 0 49872546 10849496 0 0 438773 0 0 220927 1134104 1047230 3824786 68547 252639 45.4769 45.4769 -371165 -45.4769 0 0 1.04574e+08 11587.1 47.40 47.16 18.76 -1 -1 47.40 15.9909 14.0347 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_power/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_power/config/golden_results.txt index 11138c173a7..e90dc4ebc2a 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_power/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_power/config/golden_results.txt @@ -1,3 +1,3 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time total_power routing_power_perc clock_power_perc tile_power_perc - k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common 3.26 vpr 64.44 MiB -1 -1 0.22 21992 3 0.07 -1 -1 36144 -1 -1 68 99 1 0 success v8.0.0-6989-g4a9293e1e-dirty release IPO VTR_ASSERT_LEVEL=3 GNU 11.3.0 on Linux-5.15.0-58-generic x86_64 2023-02-04T01:37:29 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 65984 99 130 343 473 1 225 298 12 12 144 clb auto 26.4 MiB 0.27 574 64.4 MiB 0.18 0.01 1.63028 -109.727 -1.63028 1.63028 0.39 0.000412287 0.000364986 0.0453901 0.0413731 40 1402 20 5.66058e+06 4.21279e+06 333335. 2314.82 0.61 0.128028 0.117926 1214 9 368 547 24816 7381 1.97803 1.97803 -135.798 -1.97803 -1.34293 -0.298787 419432. 2912.72 0.10 0.03 0.0161709 0.0154072 0.01121 0.2159 0.0683 0.7158 - k6_frac_N10_mem32K_40nm.xml diffeq1.v common 16.87 vpr 67.84 MiB -1 -1 0.36 26868 15 0.36 -1 -1 37772 -1 -1 35 162 0 5 success v8.0.0-6989-g4a9293e1e-dirty release IPO VTR_ASSERT_LEVEL=3 GNU 11.3.0 on Linux-5.15.0-58-generic x86_64 2023-02-04T01:37:29 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 69472 162 96 993 934 1 681 298 16 16 256 mult_36 auto 30.0 MiB 0.27 5113 67.8 MiB 0.46 0.01 20.106 -1618.08 -20.106 20.106 0.71 0.00133623 0.00120307 0.133876 0.121203 50 11996 44 1.21132e+07 3.86629e+06 780512. 3048.87 10.48 1.08143 0.990273 9638 21 3161 5922 1683117 415981 22.9194 22.9194 -1865.02 -22.9194 0 0 1.00276e+06 3917.05 0.28 0.39 0.104414 0.0981898 0.007752 0.3559 0.01627 0.6278 + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops crit_path_total_internal_heap_pushes crit_path_total_internal_heap_pops crit_path_total_external_heap_pushes crit_path_total_external_heap_pops crit_path_total_external_SOURCE_pushes crit_path_total_external_SOURCE_pops crit_path_total_internal_SOURCE_pushes crit_path_total_internal_SOURCE_pops crit_path_total_external_SINK_pushes crit_path_total_external_SINK_pops crit_path_total_internal_SINK_pushes crit_path_total_internal_SINK_pops crit_path_total_external_IPIN_pushes crit_path_total_external_IPIN_pops crit_path_total_internal_IPIN_pushes crit_path_total_internal_IPIN_pops crit_path_total_external_OPIN_pushes crit_path_total_external_OPIN_pops crit_path_total_internal_OPIN_pushes crit_path_total_internal_OPIN_pops crit_path_total_external_CHANX_pushes crit_path_total_external_CHANX_pops crit_path_total_internal_CHANX_pushes crit_path_total_internal_CHANX_pops crit_path_total_external_CHANY_pushes crit_path_total_external_CHANY_pops crit_path_total_internal_CHANY_pushes crit_path_total_internal_CHANY_pops crit_path_rt_node_SOURCE_pushes crit_path_rt_node_SINK_pushes crit_path_rt_node_IPIN_pushes crit_path_rt_node_OPIN_pushes crit_path_rt_node_CHANX_pushes crit_path_rt_node_CHANY_pushes crit_path_adding_all_rt crit_path_adding_high_fanout_rt crit_path_total_number_of_adding_all_rt_from_calling_high_fanout_rt critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time total_power routing_power_perc clock_power_perc tile_power_perc + k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common 2.56 vpr 68.86 MiB -1 -1 0.16 21164 3 0.04 -1 -1 36732 -1 -1 68 99 1 0 success v8.0.0-8313-gbd73e8384d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.1.1 on Linux-6.1.31-2-MANJARO x86_64 2023-07-20T13:36:56 dev vtr-verilog-to-routing 70512 99 130 343 473 1 225 298 12 12 144 clb auto 30.0 MiB 0.09 599 68.9 MiB 0.14 0.00 1.62851 -108.153 -1.62851 1.62851 0.24 0.000299717 0.000270177 0.0273918 0.0247539 36 1433 28 5.66058e+06 4.21279e+06 305235. 2119.69 0.89 0.154527 0.142184 12238 58442 -1 1268 11 415 652 36110 11199 0 0 36110 11199 652 509 0 0 1962 1778 0 0 2299 1962 0 0 702 569 0 0 14627 3510 0 0 15868 2871 0 0 652 0 0 237 348 302 2469 0 0 1.99752 1.99752 -139.864 -1.99752 -0.305022 -0.0771249 378970. 2631.74 0.08 0.02 0.03 -1 -1 0.08 0.0122486 0.0116483 0.01106 0.2164 0.06499 0.7186 + k6_frac_N10_mem32K_40nm.xml diffeq1.v common 11.60 vpr 71.82 MiB -1 -1 0.27 26032 15 0.29 -1 -1 39268 -1 -1 36 162 0 5 success v8.0.0-8313-gbd73e8384d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.1.1 on Linux-6.1.31-2-MANJARO x86_64 2023-07-20T13:36:56 dev vtr-verilog-to-routing 73548 162 96 994 935 1 694 299 16 16 256 mult_36 auto 33.9 MiB 0.18 5116 71.8 MiB 0.31 0.00 20.0144 -1558.29 -20.0144 20.0144 0.52 0.000865507 0.000778261 0.0906443 0.0820495 58 11189 29 1.21132e+07 3.92018e+06 904549. 3533.39 6.75 0.600626 0.551765 27012 180273 -1 8988 16 2806 5411 1373904 390089 0 0 1373904 390089 5411 3482 0 0 66539 65294 0 0 69304 66706 0 0 5863 3940 0 0 620903 124434 0 0 605884 126233 0 0 5411 0 0 2632 7125 7046 41280 0 0 22.5339 22.5339 -1730.29 -22.5339 0 0 1.15318e+06 4504.63 0.26 0.22 0.11 -1 -1 0.26 0.0593905 0.0563493 0.007993 0.3665 0.01796 0.6156 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_soft_multipliers/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_soft_multipliers/config/golden_results.txt index dc55407ab9b..3fd4fe85b17 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_soft_multipliers/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_soft_multipliers/config/golden_results.txt @@ -1,7 +1,7 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length - k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_4x4.v common 1.15 vpr 62.37 MiB -1 -1 0.07 20792 1 0.01 -1 -1 33408 -1 -1 3 9 0 -1 success v8.0.0-6989-g4a9293e1e-dirty release IPO VTR_ASSERT_LEVEL=3 GNU 11.3.0 on Linux-5.15.0-58-generic x86_64 2023-02-04T01:37:29 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 63864 9 8 75 70 1 35 20 5 5 25 clb auto 23.7 MiB 0.51 86 62.4 MiB 0.00 0.00 2.25119 -23.8925 -2.25119 2.25119 0.02 4.0791e-05 3.1426e-05 0.00123341 0.00112123 30 221 20 151211 75605.7 41321.0 1652.84 0.11 0.0180922 0.0151969 153 9 82 116 3433 1804 2.87707 2.87707 -32.6583 -2.87707 0 0 50368.7 2014.75 0.00 0.00 0.00303581 0.00285721 14 16 -1 -1 -1 -1 - k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_5x5.v common 6.56 vpr 62.34 MiB -1 -1 0.07 20952 1 0.01 -1 -1 33180 -1 -1 2 11 0 -1 success v8.0.0-6989-g4a9293e1e-dirty release IPO VTR_ASSERT_LEVEL=3 GNU 11.3.0 on Linux-5.15.0-58-generic x86_64 2023-02-04T01:37:29 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 63836 11 10 108 97 1 45 23 4 4 16 clb auto 23.7 MiB 5.91 103 62.3 MiB 0.00 0.00 2.99513 -33.5297 -2.99513 2.99513 0.01 7.2648e-05 6.1289e-05 0.00137746 0.00131127 34 195 16 50403.8 50403.8 21558.4 1347.40 0.08 0.0187565 0.0159988 126 15 97 110 2468 1441 3.42277 3.42277 -42.7779 -3.42277 0 0 26343.3 1646.46 0.00 0.01 0.00450719 0.00419926 14 25 -1 -1 -1 -1 - k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_6x6.v common 3.63 vpr 62.92 MiB -1 -1 0.07 20936 1 0.01 -1 -1 33460 -1 -1 4 13 0 -1 success v8.0.0-6989-g4a9293e1e-dirty release IPO VTR_ASSERT_LEVEL=3 GNU 11.3.0 on Linux-5.15.0-58-generic x86_64 2023-02-04T01:37:29 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64432 13 12 149 129 1 75 29 5 5 25 clb auto 24.3 MiB 2.75 214 62.9 MiB 0.01 0.00 3.06234 -43.4122 -3.06234 3.06234 0.02 7.37e-05 5.8854e-05 0.00532846 0.00483367 36 527 25 151211 100808 46719.2 1868.77 0.26 0.0540875 0.0474551 362 18 397 507 17611 8625 4.61304 4.61304 -66.0114 -4.61304 0 0 57775.2 2311.01 0.01 0.02 0.0110675 0.0104997 25 36 -1 -1 -1 -1 - k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_7x7.v common 3.02 vpr 62.95 MiB -1 -1 0.08 21044 1 0.01 -1 -1 33364 -1 -1 6 15 0 -1 success v8.0.0-6989-g4a9293e1e-dirty release IPO VTR_ASSERT_LEVEL=3 GNU 11.3.0 on Linux-5.15.0-58-generic x86_64 2023-02-04T01:37:29 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64460 15 14 196 165 1 91 35 5 5 25 clb auto 24.4 MiB 2.23 266 62.9 MiB 0.02 0.00 3.1163 -51.153 -3.1163 3.1163 0.02 9.6193e-05 7.7483e-05 0.00537668 0.00465202 40 608 47 151211 151211 50368.7 2014.75 0.15 0.0398337 0.0337376 465 17 456 647 24559 11909 4.0567 4.0567 -78.5637 -4.0567 0 0 63348.9 2533.96 0.00 0.02 0.00900562 0.00834956 36 49 -1 -1 -1 -1 - k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_8x8.v common 3.57 vpr 62.90 MiB -1 -1 0.07 21032 1 0.01 -1 -1 33640 -1 -1 6 17 0 -1 success v8.0.0-6989-g4a9293e1e-dirty release IPO VTR_ASSERT_LEVEL=3 GNU 11.3.0 on Linux-5.15.0-58-generic x86_64 2023-02-04T01:37:29 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64412 17 16 251 206 1 122 39 5 5 25 clb auto 24.5 MiB 2.53 402 62.9 MiB 0.02 0.00 3.26818 -62.072 -3.26818 3.26818 0.02 0.000120689 9.7457e-05 0.00860082 0.00737749 50 665 24 151211 151211 61632.8 2465.31 0.32 0.0813645 0.0711333 637 20 793 1342 44144 19745 6.63254 6.63254 -121.135 -6.63254 0 0 77226.2 3089.05 0.01 0.02 0.0125829 0.0116553 50 64 -1 -1 -1 -1 - k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_9x9.v common 3.34 vpr 63.32 MiB -1 -1 0.09 21356 1 0.02 -1 -1 33576 -1 -1 9 19 0 -1 success v8.0.0-6989-g4a9293e1e-dirty release IPO VTR_ASSERT_LEVEL=3 GNU 11.3.0 on Linux-5.15.0-58-generic x86_64 2023-02-04T01:37:29 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 64844 19 18 308 249 1 147 46 6 6 36 clb auto 25.0 MiB 2.27 485 63.3 MiB 0.03 0.00 3.95816 -76.1438 -3.95816 3.95816 0.03 0.000154833 0.000120934 0.011267 0.00944847 50 1237 28 403230 226817 107229. 2978.57 0.26 0.065296 0.0560774 804 25 969 1551 61045 23897 5.31654 5.31654 -112.485 -5.31654 0 0 134937. 3748.26 0.01 0.03 0.01813 0.0166798 63 81 -1 -1 -1 -1 + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops crit_path_total_internal_heap_pushes crit_path_total_internal_heap_pops crit_path_total_external_heap_pushes crit_path_total_external_heap_pops crit_path_total_external_SOURCE_pushes crit_path_total_external_SOURCE_pops crit_path_total_internal_SOURCE_pushes crit_path_total_internal_SOURCE_pops crit_path_total_external_SINK_pushes crit_path_total_external_SINK_pops crit_path_total_internal_SINK_pushes crit_path_total_internal_SINK_pops crit_path_total_external_IPIN_pushes crit_path_total_external_IPIN_pops crit_path_total_internal_IPIN_pushes crit_path_total_internal_IPIN_pops crit_path_total_external_OPIN_pushes crit_path_total_external_OPIN_pops crit_path_total_internal_OPIN_pushes crit_path_total_internal_OPIN_pops crit_path_total_external_CHANX_pushes crit_path_total_external_CHANX_pops crit_path_total_internal_CHANX_pushes crit_path_total_internal_CHANX_pops crit_path_total_external_CHANY_pushes crit_path_total_external_CHANY_pops crit_path_total_internal_CHANY_pushes crit_path_total_internal_CHANY_pops crit_path_rt_node_SOURCE_pushes crit_path_rt_node_SINK_pushes crit_path_rt_node_IPIN_pushes crit_path_rt_node_OPIN_pushes crit_path_rt_node_CHANX_pushes crit_path_rt_node_CHANY_pushes crit_path_adding_all_rt crit_path_adding_high_fanout_rt crit_path_total_number_of_adding_all_rt_from_calling_high_fanout_rt critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length + k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_4x4.v common 0.80 vpr 65.64 MiB -1 -1 0.05 20132 1 0.01 -1 -1 35492 -1 -1 3 9 0 -1 success v8.0.0-8313-gbd73e8384d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.1.1 on Linux-6.1.31-2-MANJARO x86_64 2023-07-20T13:36:56 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 67216 9 8 75 70 1 37 20 5 5 25 clb auto 27.2 MiB 0.37 87 65.6 MiB 0.00 0.00 2.25879 -24.067 -2.25879 2.25879 0.02 2.8365e-05 2.1278e-05 0.000793206 0.000721571 38 184 14 151211 75605.7 48493.3 1939.73 0.09 0.0133335 0.0110025 2100 8065 -1 153 12 112 136 3959 2021 0 0 3959 2021 136 129 0 0 442 412 0 0 631 559 0 0 137 135 0 0 1357 328 0 0 1256 458 0 0 136 0 0 24 4 23 235 0 0 2.68643 2.68643 -33.1966 -2.68643 0 0 61632.8 2465.31 0.00 0.00 0.00 -1 -1 0.00 0.0023005 0.00214713 14 16 -1 -1 -1 -1 + k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_5x5.v common 4.54 vpr 66.09 MiB -1 -1 0.06 20148 1 0.00 -1 -1 33308 -1 -1 2 11 0 -1 success v8.0.0-8313-gbd73e8384d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.1.1 on Linux-6.1.31-2-MANJARO x86_64 2023-07-20T13:36:56 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 67672 11 10 108 97 1 45 23 4 4 16 clb auto 27.6 MiB 4.13 99 66.1 MiB 0.00 0.00 2.99513 -33.5297 -2.99513 2.99513 0.01 3.8376e-05 2.9951e-05 0.0015057 0.00132617 34 211 26 50403.8 50403.8 21558.4 1347.40 0.05 0.0140163 0.0118251 1020 3049 -1 144 16 139 172 4520 2686 0 0 4520 2686 172 149 0 0 611 547 0 0 873 782 0 0 172 151 0 0 1369 541 0 0 1323 516 0 0 172 0 0 33 30 26 349 0 0 3.42277 3.42277 -45.1479 -3.42277 0 0 26343.3 1646.46 0.00 0.01 0.00 -1 -1 0.00 0.00351111 0.00325521 14 25 -1 -1 -1 -1 + k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_6x6.v common 2.64 vpr 66.34 MiB -1 -1 0.09 20360 1 0.01 -1 -1 33116 -1 -1 4 13 0 -1 success v8.0.0-8313-gbd73e8384d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.1.1 on Linux-6.1.31-2-MANJARO x86_64 2023-07-20T13:36:56 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 67928 13 12 149 129 1 73 29 5 5 25 clb auto 27.9 MiB 1.80 186 66.3 MiB 0.01 0.00 3.20662 -44.3706 -3.20662 3.20662 0.02 5.3265e-05 4.2042e-05 0.00192146 0.00172037 38 359 21 151211 100808 48493.3 1939.73 0.14 0.0261909 0.0222783 2100 8065 -1 355 20 405 583 20015 9844 0 0 20015 9844 583 498 0 0 1879 1764 0 0 3204 2650 0 0 593 545 0 0 6920 2328 0 0 6836 2059 0 0 583 0 0 178 271 163 1783 0 0 4.37604 4.37604 -67.2741 -4.37604 0 0 61632.8 2465.31 0.00 0.01 0.00 -1 -1 0.00 0.0052765 0.00487745 25 36 -1 -1 -1 -1 + k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_7x7.v common 1.95 vpr 66.48 MiB -1 -1 0.06 20280 1 0.00 -1 -1 33480 -1 -1 6 15 0 -1 success v8.0.0-8313-gbd73e8384d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.1.1 on Linux-6.1.31-2-MANJARO x86_64 2023-07-20T13:36:56 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 68080 15 14 196 165 1 95 35 5 5 25 clb auto 28.1 MiB 1.37 279 66.5 MiB 0.01 0.00 3.11103 -51.0846 -3.11103 3.11103 0.02 6.8979e-05 5.5751e-05 0.00344116 0.003024 52 453 15 151211 151211 63348.9 2533.96 0.16 0.0352304 0.0299382 2316 10503 -1 364 17 347 499 18306 8355 0 0 18306 8355 499 399 0 0 1652 1557 0 0 2365 2079 0 0 523 405 0 0 6237 1995 0 0 7030 1920 0 0 499 0 0 152 172 182 1475 0 0 3.91996 3.91996 -70.391 -3.91996 0 0 82390.3 3295.61 0.01 0.01 0.01 -1 -1 0.01 0.00675161 0.0063223 37 49 -1 -1 -1 -1 + k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_8x8.v common 2.38 vpr 66.80 MiB -1 -1 0.06 20404 1 0.00 -1 -1 35664 -1 -1 6 17 0 -1 success v8.0.0-8313-gbd73e8384d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.1.1 on Linux-6.1.31-2-MANJARO x86_64 2023-07-20T13:36:56 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 68404 17 16 251 206 1 122 39 5 5 25 clb auto 28.3 MiB 1.73 403 66.8 MiB 0.01 0.00 3.26818 -62.072 -3.26818 3.26818 0.02 8.7435e-05 7.1081e-05 0.00506313 0.00441863 52 751 31 151211 151211 63348.9 2533.96 0.19 0.0431888 0.0369288 2316 10503 -1 602 18 571 922 30990 13669 0 0 30990 13669 922 668 0 0 2952 2755 0 0 4594 3827 0 0 962 740 0 0 9964 2681 0 0 11596 2998 0 0 922 0 0 351 350 549 3622 0 0 4.58466 4.58466 -97.1505 -4.58466 0 0 82390.3 3295.61 0.01 0.01 0.01 -1 -1 0.01 0.0087006 0.00814138 50 64 -1 -1 -1 -1 + k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_9x9.v common 3.94 vpr 66.96 MiB -1 -1 0.11 20608 1 0.02 -1 -1 33432 -1 -1 9 19 0 -1 success v8.0.0-8313-gbd73e8384d-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 13.1.1 on Linux-6.1.31-2-MANJARO x86_64 2023-07-20T13:36:56 dev /home/dev/Desktop/CAS-Atlantic/vtr-verilog-to-routing 68564 19 18 308 249 1 148 46 6 6 36 clb auto 28.9 MiB 1.40 467 67.0 MiB 0.02 0.00 3.86024 -72.0568 -3.86024 3.86024 0.03 0.000105412 8.6704e-05 0.00551129 0.00484581 48 1117 46 403230 226817 104013. 2889.24 0.16 0.0416688 0.0360682 3910 18599 -1 762 20 817 1362 47477 18799 0 0 47477 18799 1362 963 0 0 4283 3912 0 0 6634 5668 0 0 1421 1022 0 0 17522 3558 0 0 16255 3676 0 0 1362 0 0 545 619 734 5532 0 0 5.49372 5.49372 -116.089 -5.49372 0 0 131137. 3642.71 0.01 0.02 0.01 -1 -1 0.01 0.0117573 0.0109032 63 81 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/f4pga_button_controller/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/f4pga_button_controller/config/golden_results.txt index 1607229e5ad..6948f37097e 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/f4pga_button_controller/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/f4pga_button_controller/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_frac_chain_mem32K_40nm.xml button_controller.sv common 2.64 vpr 62.60 MiB -1 -1 1.30 56932 3 0.08 -1 -1 36196 -1 -1 12 3 0 0 success 938cd3a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-08T22:57:19 gh-actions-runner-vtr-auto-spawned55 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 64104 3 12 254 218 1 129 27 6 6 36 clb auto 24.1 MiB 0.12 445 62.6 MiB 0.02 0.00 1.94686 -119.908 -1.94686 1.94686 0.04 0.000176361 0.000137245 0.00661163 0.00567261 34 661 21 646728 646728 56055.2 1557.09 0.19 0.0596167 0.0498325 582 21 618 819 24614 9120 2.59838 2.59838 -136.683 -2.59838 0 0 68985.8 1916.27 0.01 0.03 0.0159222 0.0142879 + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops crit_path_total_internal_heap_pushes crit_path_total_internal_heap_pops crit_path_total_external_heap_pushes crit_path_total_external_heap_pops crit_path_total_external_SOURCE_pushes crit_path_total_external_SOURCE_pops crit_path_total_internal_SOURCE_pushes crit_path_total_internal_SOURCE_pops crit_path_total_external_SINK_pushes crit_path_total_external_SINK_pops crit_path_total_internal_SINK_pushes crit_path_total_internal_SINK_pops crit_path_total_external_IPIN_pushes crit_path_total_external_IPIN_pops crit_path_total_internal_IPIN_pushes crit_path_total_internal_IPIN_pops crit_path_total_external_OPIN_pushes crit_path_total_external_OPIN_pops crit_path_total_internal_OPIN_pushes crit_path_total_internal_OPIN_pops crit_path_total_external_CHANX_pushes crit_path_total_external_CHANX_pops crit_path_total_internal_CHANX_pushes crit_path_total_internal_CHANX_pops crit_path_total_external_CHANY_pushes crit_path_total_external_CHANY_pops crit_path_total_internal_CHANY_pushes crit_path_total_internal_CHANY_pops crit_path_rt_node_SOURCE_pushes crit_path_rt_node_SINK_pushes crit_path_rt_node_IPIN_pushes crit_path_rt_node_OPIN_pushes crit_path_rt_node_CHANX_pushes crit_path_rt_node_CHANY_pushes crit_path_adding_all_rt crit_path_adding_high_fanout_rt crit_path_total_number_of_adding_all_rt_from_calling_high_fanout_rt critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time + k6_frac_N10_frac_chain_mem32K_40nm.xml button_controller.sv common 1.91 vpr 65.81 MiB -1 -1 0.90 56460 3 0.05 -1 -1 35436 -1 -1 13 3 0 0 success 222546b-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.5.0 on Linux-5.10.35-v8 x86_64 2023-08-14T20:40:44 gh-actions-runner-vtr-auto-spawned20 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 67392 3 12 252 216 1 125 28 7 7 49 clb auto 27.2 MiB 0.09 409 65.8 MiB 0.02 0.00 1.9464 -118.797 -1.9464 1.9464 0.05 9.4184e-05 7.2011e-05 0.00579816 0.0049021 40 685 17 1.07788e+06 700622 95414.1 1947.23 0.26 0.0439795 0.036483 3948 17640 -1 588 12 358 524 12860 4074 0 0 12860 4074 524 432 0 0 745 603 0 0 847 745 0 0 559 475 0 0 4900 981 0 0 5285 838 0 0 524 0 0 166 188 128 1608 0 0 2.28597 2.28597 -135.833 -2.28597 0 0 120731. 2463.90 0.02 0.01 0.01 -1 -1 0.02 0.00890339 0.00832405 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/f4pga_pulse_width_led/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/f4pga_pulse_width_led/config/golden_results.txt index 0959d721be9..0659dc7196e 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/f4pga_pulse_width_led/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/f4pga_pulse_width_led/config/golden_results.txt @@ -1,2 +1,2 @@ -arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops crit_path_total_internal_heap_pushes crit_path_total_internal_heap_pops crit_path_total_external_heap_pushes crit_path_total_external_heap_pops crit_path_total_external_SOURCE_pushes crit_path_total_external_SOURCE_pops crit_path_total_internal_SOURCE_pushes crit_path_total_internal_SOURCE_pops crit_path_total_external_SINK_pushes crit_path_total_external_SINK_pops crit_path_total_internal_SINK_pushes crit_path_total_internal_SINK_pops crit_path_total_external_IPIN_pushes crit_path_total_external_IPIN_pops crit_path_total_internal_IPIN_pushes crit_path_total_internal_IPIN_pops crit_path_total_external_OPIN_pushes crit_path_total_external_OPIN_pops crit_path_total_internal_OPIN_pushes crit_path_total_internal_OPIN_pops crit_path_total_external_CHANX_pushes crit_path_total_external_CHANX_pops crit_path_total_internal_CHANX_pushes crit_path_total_internal_CHANX_pops crit_path_total_external_CHANY_pushes crit_path_total_external_CHANY_pops crit_path_total_internal_CHANY_pushes crit_path_total_internal_CHANY_pops crit_path_rt_node_SOURCE_pushes crit_path_rt_node_SINK_pushes crit_path_rt_node_IPIN_pushes crit_path_rt_node_OPIN_pushes crit_path_rt_node_CHANX_pushes crit_path_rt_node_CHANY_pushes crit_path_adding_all_rt crit_path_adding_high_fanout_rt crit_path_total_number_of_adding_all_rt_from_calling_high_fanout_rt critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6_frac_N10_frac_chain_mem32K_40nm.xml pulse_led.v common 1.73 vpr 71.07 MiB -1 -1 0.40 40760 2 0.04 -1 -1 30548 -1 -1 3 9 0 0 success v8.0.0-7662-gd563ffd8a release VTR_ASSERT_LEVEL=2 gprof GNU 9.4.0 on Linux-4.15.0-197-generic x86_64 2023-04-24T17:25:06 betzgrp-wintermute.eecg.utoronto.ca /home/mahmo494/Desktop/RLplace_final/vtr-verilog-to-routing/vtr_flow/tasks 72776 9 3 145 109 1 14 15 5 5 25 clb auto 32.4 MiB 0.04 24 71.1 MiB 0.01 0.00 1.225 -51.3496 -1.225 1.225 0.05 0.000294908 0.00023425 0.00318007 0.00267849 18 45 2 323364 161682 19301.3 772.054 0.04 0.00899526 0.00789011 1386 3298 -1 35 3 17 17 295 163 0 0 295 163 17 17 0 0 33 24 0 0 34 33 0 0 17 17 0 0 109 37 0 0 85 35 0 0 17 0 0 0 0 0 17 0 0 1.225 1.225 -52.1608 -1.225 0 0 24611.1 984.442 0.00 0.01 0.01 -1 -1 0.00 0.00521159 0.00472024 + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops crit_path_total_internal_heap_pushes crit_path_total_internal_heap_pops crit_path_total_external_heap_pushes crit_path_total_external_heap_pops crit_path_total_external_SOURCE_pushes crit_path_total_external_SOURCE_pops crit_path_total_internal_SOURCE_pushes crit_path_total_internal_SOURCE_pops crit_path_total_external_SINK_pushes crit_path_total_external_SINK_pops crit_path_total_internal_SINK_pushes crit_path_total_internal_SINK_pops crit_path_total_external_IPIN_pushes crit_path_total_external_IPIN_pops crit_path_total_internal_IPIN_pushes crit_path_total_internal_IPIN_pops crit_path_total_external_OPIN_pushes crit_path_total_external_OPIN_pops crit_path_total_internal_OPIN_pushes crit_path_total_internal_OPIN_pops crit_path_total_external_CHANX_pushes crit_path_total_external_CHANX_pops crit_path_total_internal_CHANX_pushes crit_path_total_internal_CHANX_pops crit_path_total_external_CHANY_pushes crit_path_total_external_CHANY_pops crit_path_total_internal_CHANY_pushes crit_path_total_internal_CHANY_pops crit_path_rt_node_SOURCE_pushes crit_path_rt_node_SINK_pushes crit_path_rt_node_IPIN_pushes crit_path_rt_node_OPIN_pushes crit_path_rt_node_CHANX_pushes crit_path_rt_node_CHANY_pushes crit_path_adding_all_rt crit_path_adding_high_fanout_rt crit_path_total_number_of_adding_all_rt_from_calling_high_fanout_rt critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time + k6_frac_N10_frac_chain_mem32K_40nm.xml pulse_led.v common 0.85 vpr 64.62 MiB -1 -1 0.37 48640 2 0.01 -1 -1 34032 -1 -1 3 9 0 0 success 222546b-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.5.0 on Linux-5.10.35-v8 x86_64 2023-08-14T20:40:44 gh-actions-runner-vtr-auto-spawned20 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 66172 9 3 145 109 1 14 15 5 5 25 clb auto 26.3 MiB 0.02 34 64.6 MiB 0.00 0.00 1.225 -51.4337 -1.225 1.225 0.01 4.0899e-05 2.9845e-05 0.000810425 0.000753616 18 46 3 323364 161682 19301.3 772.054 0.02 0.00322405 0.00301952 1386 3298 -1 33 2 13 13 149 85 0 0 149 85 13 13 0 0 21 15 0 0 22 21 0 0 13 13 0 0 47 11 0 0 33 12 0 0 13 0 0 0 0 0 13 0 0 1.225 1.225 -51.8014 -1.225 0 0 24611.1 984.442 0.00 0.00 0.00 -1 -1 0.00 0.0021157 0.00202562 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/f4pga_timer/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/f4pga_timer/config/golden_results.txt index 6ff45167ea8..36401994979 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/f4pga_timer/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/f4pga_timer/config/golden_results.txt @@ -1,2 +1,2 @@ - arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time - k6_frac_N10_frac_chain_mem32K_40nm.xml clock.sv common 2.42 vpr 62.94 MiB -1 -1 1.06 49536 4 0.10 -1 -1 35712 -1 -1 10 3 0 0 success 938cd3a release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-5.10.35-v8 x86_64 2023-02-08T22:57:19 gh-actions-runner-vtr-auto-spawned55 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 64448 3 12 261 222 1 119 25 6 6 36 clb auto 24.4 MiB 0.20 411 62.9 MiB 0.02 0.00 2.37914 -126.114 -2.37914 2.37914 0.04 0.00020851 0.000148565 0.00846143 0.00710341 30 712 25 646728 538940 51438.4 1428.85 0.14 0.0475023 0.0401423 484 12 362 522 9732 3585 2.70845 2.70845 -142.497 -2.70845 0 0 63526.2 1764.62 0.01 0.02 0.0136301 0.0126865 + arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops crit_path_total_internal_heap_pushes crit_path_total_internal_heap_pops crit_path_total_external_heap_pushes crit_path_total_external_heap_pops crit_path_total_external_SOURCE_pushes crit_path_total_external_SOURCE_pops crit_path_total_internal_SOURCE_pushes crit_path_total_internal_SOURCE_pops crit_path_total_external_SINK_pushes crit_path_total_external_SINK_pops crit_path_total_internal_SINK_pushes crit_path_total_internal_SINK_pops crit_path_total_external_IPIN_pushes crit_path_total_external_IPIN_pops crit_path_total_internal_IPIN_pushes crit_path_total_internal_IPIN_pops crit_path_total_external_OPIN_pushes crit_path_total_external_OPIN_pops crit_path_total_internal_OPIN_pushes crit_path_total_internal_OPIN_pops crit_path_total_external_CHANX_pushes crit_path_total_external_CHANX_pops crit_path_total_internal_CHANX_pushes crit_path_total_internal_CHANX_pops crit_path_total_external_CHANY_pushes crit_path_total_external_CHANY_pops crit_path_total_internal_CHANY_pushes crit_path_total_internal_CHANY_pops crit_path_rt_node_SOURCE_pushes crit_path_rt_node_SINK_pushes crit_path_rt_node_IPIN_pushes crit_path_rt_node_OPIN_pushes crit_path_rt_node_CHANX_pushes crit_path_rt_node_CHANY_pushes crit_path_adding_all_rt crit_path_adding_high_fanout_rt crit_path_total_number_of_adding_all_rt_from_calling_high_fanout_rt critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time + k6_frac_N10_frac_chain_mem32K_40nm.xml clock.sv common 1.54 vpr 65.80 MiB -1 -1 0.69 49624 4 0.07 -1 -1 35560 -1 -1 10 3 0 0 success 222546b-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.5.0 on Linux-5.10.35-v8 x86_64 2023-08-14T20:40:44 gh-actions-runner-vtr-auto-spawned20 /root/vtr-verilog-to-routing/vtr-verilog-to-routing 67380 3 12 261 222 1 119 25 6 6 36 clb auto 27.3 MiB 0.13 425 65.8 MiB 0.01 0.00 2.39956 -129.682 -2.39956 2.39956 0.03 9.565e-05 7.3348e-05 0.00427643 0.00376691 30 695 17 646728 538940 51438.4 1428.85 0.08 0.0252184 0.021744 2512 8913 -1 547 11 355 516 15625 5833 0 0 15625 5833 516 418 0 0 882 752 0 0 986 882 0 0 552 459 0 0 6460 1703 0 0 6229 1619 0 0 516 0 0 161 222 192 1871 0 0 2.70547 2.70547 -144.28 -2.70547 0 0 63526.2 1764.62 0.01 0.01 0.01 -1 -1 0.01 0.00924855 0.0087123 diff --git a/yosys/CHANGELOG b/yosys/CHANGELOG index 1d7a6fc9d88..585605abcdd 100644 --- a/yosys/CHANGELOG +++ b/yosys/CHANGELOG @@ -2,6 +2,79 @@ List of major changes and improvements between releases ======================================================= +Yosys 0.31 .. Yosys 0.32 +-------------------------- + * Verific support + - Added sub option "-lib" to reading commands for VHDL and + SystemVerilog, that will later import all units/modules from + marked files as blackboxes. + + * Various + - Added support for $lt, $le, $gt, $ge to the code generating AIGs. + +Yosys 0.30 .. Yosys 0.31 +-------------------------- + * New commands and options + - Added option "-lsbidx" to "write_edif" pass. + + * Various + - Added support for $divfloor operator to cxxrtl backend. + - dfflegalize: allow setting mince and minsrst args from scratchpad. + +Yosys 0.29 .. Yosys 0.30 +-------------------------- + * New commands and options + - Added "recover_names" pass to recover names post-mapping. + + * Gowin support + - Added remaining primitives blackboxes. + + * Various + - "show -colorattr" will now color the cells, wires, and + connection arrows. + - "show -viewer none" will not execute viewer. + +Yosys 0.28 .. Yosys 0.29 +-------------------------- + * New commands and options + - Added "synthprop" pass for synthesizable properties. + + * Verific support + - Handle conditions on clocked concurrent assertions in unclocked + procedural contexts. + + * Verilog + - Fix const eval of unbased unsized constants. + - Handling of attributes for struct / union variables. + +Yosys 0.27 .. Yosys 0.28 +-------------------------- + * Verilog + - Out of bounds checking for struct/union members. + + * Verific support + - Fix enum_values support and signed attribute values. + + * ECP5 support + - Added "synth_ecp5 -iopad" + + * MachXO2 support + - Added "synth_machxo2 -ccu2" + +Yosys 0.26 .. Yosys 0.27 +-------------------------- + * New commands and options + - Added option "-make_assert" to "equiv_make" pass. + - Added option "-coverenable" to "chformal" pass. + + * Verilog + - Resolve package types in interfaces. + - Handle range offsets in packed arrays within packed structs. + - Support for data and array queries on struct/union item expressions. + + * GateMate support + - Enable register initialization. + Yosys 0.25 .. Yosys 0.26 -------------------------- * New commands and options diff --git a/yosys/Makefile b/yosys/Makefile index 826562fdf48..6d831e5665f 100644 --- a/yosys/Makefile +++ b/yosys/Makefile @@ -141,7 +141,7 @@ LDLIBS += -lrt endif endif -YOSYS_VER := 0.26 +YOSYS_VER := 0.32 # Note: We arrange for .gitcommit to contain the (short) commit hash in # tarballs generated with git-archive(1) using .gitattributes. The git repo @@ -149,7 +149,7 @@ YOSYS_VER := 0.26 # back to calling git directly. TARBALL_GIT_REV := $(shell cat $(YOSYS_SRC)/.gitcommit) ifeq ($(TARBALL_GIT_REV),$$Format:%h$$) -GIT_REV := $(shell git ls-remote $(YOSYS_SRC) HEAD -q | $(AWK) 'BEGIN {R = "UNKNOWN"}; ($$2 == "HEAD") {R = substr($$1, 1, 9); exit} END {print R}') +GIT_REV := $(shell GIT_DIR=$(YOSYS_SRC)/.git git rev-parse --short=9 HEAD || echo UNKNOWN) else GIT_REV := $(TARBALL_GIT_REV) endif @@ -157,7 +157,7 @@ endif OBJS = kernel/version_$(GIT_REV).o bumpversion: -# sed -i "/^YOSYS_VER := / s/+[0-9][0-9]*$$/+`git log --oneline e02b7f6.. | wc -l`/;" Makefile +# sed -i "/^YOSYS_VER := / s/+[0-9][0-9]*$$/+`git log --oneline f3c6b41.. | wc -l`/;" Makefile # set 'ABCREV = default' to use abc/ as it is # @@ -165,7 +165,7 @@ bumpversion: # is just a symlink to your actual ABC working directory, as 'make mrproper' # will remove the 'abc' directory and you do not want to accidentally # delete your work on ABC.. -ABCREV = a8f0ef2 +ABCREV = bb64142 ABCPULL = 1 ABCURL ?= https://github.com/YosysHQ/abc ABCMKARGS = CC="$(CXX)" CXX="$(CXX)" ABC_USE_LIBSTDCXX=1 ABC_USE_NAMESPACE=abc VERBOSE=$(Q) @@ -523,6 +523,7 @@ CXXFLAGS += -I$(GHDL_INCLUDE_DIR) -DYOSYS_ENABLE_GHDL LDLIBS += $(GHDL_LIB_DIR)/libghdl.a $(file <$(GHDL_LIB_DIR)/libghdl.link) endif +LDLIBS_VERIFIC = ifeq ($(ENABLE_VERIFIC),1) VERIFIC_DIR ?= /usr/local/src/verific_lib VERIFIC_COMPONENTS ?= verilog database util containers hier_tree @@ -548,9 +549,9 @@ CXXFLAGS += -DYOSYSHQ_VERIFIC_EXTENSIONS endif CXXFLAGS += $(patsubst %,-I$(VERIFIC_DIR)/%,$(VERIFIC_COMPONENTS)) -DYOSYS_ENABLE_VERIFIC ifeq ($(OS), Darwin) -LDLIBS += $(patsubst %,$(VERIFIC_DIR)/%/*-mac.a,$(VERIFIC_COMPONENTS)) -lz +LDLIBS_VERIFIC += $(foreach comp,$(patsubst %,$(VERIFIC_DIR)/%/*-mac.a,$(VERIFIC_COMPONENTS)),-Wl,-force_load $(comp)) -lz else -LDLIBS += $(patsubst %,$(VERIFIC_DIR)/%/*-linux.a,$(VERIFIC_COMPONENTS)) -lz +LDLIBS_VERIFIC += -Wl,--whole-archive $(patsubst %,$(VERIFIC_DIR)/%/*-linux.a,$(VERIFIC_COMPONENTS)) -Wl,--no-whole-archive -lz endif endif @@ -611,6 +612,7 @@ $(eval $(call add_include_file,kernel/log.h)) $(eval $(call add_include_file,kernel/rtlil.h)) $(eval $(call add_include_file,kernel/binding.h)) $(eval $(call add_include_file,kernel/register.h)) +$(eval $(call add_include_file,kernel/cellaigs.h)) $(eval $(call add_include_file,kernel/celltypes.h)) $(eval $(call add_include_file,kernel/celledges.h)) $(eval $(call add_include_file,kernel/consteval.h)) @@ -627,6 +629,8 @@ ifeq ($(ENABLE_ZLIB),1) $(eval $(call add_include_file,kernel/fstdata.h)) endif $(eval $(call add_include_file,kernel/mem.h)) +$(eval $(call add_include_file,kernel/yw.h)) +$(eval $(call add_include_file,kernel/json.h)) $(eval $(call add_include_file,libs/ezsat/ezsat.h)) $(eval $(call add_include_file,libs/ezsat/ezminisat.h)) ifeq ($(ENABLE_ZLIB),1) @@ -740,13 +744,13 @@ yosys.js: $(filter-out yosysjs-$(YOSYS_VER).zip,$(EXTRA_TARGETS)) endif $(PROGRAM_PREFIX)yosys$(EXE): $(OBJS) - $(P) $(LD) -o $(PROGRAM_PREFIX)yosys$(EXE) $(EXE_LDFLAGS) $(LDFLAGS) $(OBJS) $(LDLIBS) + $(P) $(LD) -o $(PROGRAM_PREFIX)yosys$(EXE) $(EXE_LDFLAGS) $(LDFLAGS) $(OBJS) $(LDLIBS) $(LDLIBS_VERIFIC) libyosys.so: $(filter-out kernel/driver.o,$(OBJS)) ifeq ($(OS), Darwin) - $(P) $(LD) -o libyosys.so -shared -Wl,-install_name,$(LIBDIR)/libyosys.so $(LDFLAGS) $^ $(LDLIBS) + $(P) $(LD) -o libyosys.so -shared -Wl,-install_name,$(LIBDIR)/libyosys.so $(LDFLAGS) $^ $(LDLIBS) $(LDLIBS_VERIFIC) else - $(P) $(LD) -o libyosys.so -shared -Wl,-soname,$(LIBDIR)/libyosys.so $(LDFLAGS) $^ $(LDLIBS) + $(P) $(LD) -o libyosys.so -shared -Wl,-soname,$(LIBDIR)/libyosys.so $(LDFLAGS) $^ $(LDLIBS) $(LDLIBS_VERIFIC) endif %.o: %.cc @@ -797,13 +801,13 @@ ifneq ($(ABCREV),default) $(Q) if test -d abc && test -d abc/.git && ! git -C abc diff-index --quiet HEAD; then \ echo 'REEBE: NOP pbagnvaf ybpny zbqvsvpngvbaf! Frg NOPERI=qrsnhyg va Lbflf Znxrsvyr!' | tr 'A-Za-z' 'N-ZA-Mn-za-m'; false; \ fi - $(Q) if test -d abc && ! test -d abc/.git && ! test "`cat abc/.gitcommit | cut -c1-7`" == "$(ABCREV)"; then \ + $(Q) if test -d abc && ! test -d abc/.git && ! test "`cat abc/.gitcommit | cut -c1-7`" = "$(ABCREV)"; then \ echo 'REEBE: Qbjaybnqrq NOP irefvbaf qbrf abg zngpu! Qbjaybnq sebz:' | tr 'A-Za-z' 'N-ZA-Mn-za-m'; echo $(ABCURL)/archive/$(ABCREV).tar.gz; false; \ fi # set a variable so the test fails if git fails to run - when comparing outputs directly, empty string would match empty string - $(Q) if test -d abc && ! test -d abc/.git && test "`cat abc/.gitcommit | cut -c1-7`" == "$(ABCREV)"; then \ + $(Q) if test -d abc && ! test -d abc/.git && test "`cat abc/.gitcommit | cut -c1-7`" = "$(ABCREV)"; then \ echo "Compiling local copy of ABC"; \ - elif ! (cd abc 2> /dev/null && rev="`git rev-parse $(ABCREV)`" && test "`git rev-parse HEAD`" == "$$rev"); then \ + elif ! (cd abc 2> /dev/null && rev="`git rev-parse $(ABCREV)`" && test "`git rev-parse HEAD`" = "$$rev"); then \ test $(ABCPULL) -ne 0 || { echo 'REEBE: NOP abg hc gb qngr naq NOPCHYY frg gb 0 va Znxrsvyr!' | tr 'A-Za-z' 'N-ZA-Mn-za-m'; exit 1; }; \ echo "Pulling ABC from $(ABCURL):"; set -x; \ test -d abc || git clone $(ABCURL) abc; \ @@ -837,6 +841,9 @@ ABCOPT="" endif test: $(TARGETS) $(EXTRA_TARGETS) +ifeq ($(ENABLE_VERIFIC),1) + +cd tests/verific && bash run-test.sh $(SEEDOPT) +endif +cd tests/simple && bash run-test.sh $(SEEDOPT) +cd tests/simple_abc9 && bash run-test.sh $(SEEDOPT) +cd tests/hana && bash run-test.sh $(SEEDOPT) diff --git a/yosys/README.md b/yosys/README.md index f3a63cbec39..5e5a8ec3e12 100644 --- a/yosys/README.md +++ b/yosys/README.md @@ -156,9 +156,10 @@ reading and elaborating the design using the Verilog frontend: yosys> read -sv tests/simple/fiedler-cooley.v yosys> hierarchy -top up3down5 -writing the design to the console in Yosys's internal format: +writing the design to the console in the RTLIL format used by Yosys +internally: - yosys> write_ilang + yosys> write_rtlil convert processes (``always`` blocks) to netlist elements and perform some simple optimizations: diff --git a/yosys/backends/aiger/aiger.cc b/yosys/backends/aiger/aiger.cc index 4ef28be9f3b..bb804f230fb 100644 --- a/yosys/backends/aiger/aiger.cc +++ b/yosys/backends/aiger/aiger.cc @@ -119,14 +119,14 @@ struct AigerWriter if (wire->name.isPublic()) sigmap.add(wire); - // promote input wires + // promote output wires for (auto wire : module->wires()) - if (wire->port_input) + if (wire->port_output) sigmap.add(wire); - // promote output wires + // promote input wires for (auto wire : module->wires()) - if (wire->port_output) + if (wire->port_input) sigmap.add(wire); for (auto wire : module->wires()) @@ -706,6 +706,9 @@ struct AigerWriter for (auto &it : latch_lines) f << it.second; + if (initstate_ff) + f << stringf("ninitff %d\n", ((initstate_ff >> 1)-1-aig_i)); + wire_lines.sort(); for (auto &it : wire_lines) f << it.second; @@ -733,6 +736,9 @@ struct AigerWriter auto sig_qy = cell->getPort(cell->type.in(ID($anyconst), ID($anyseq)) ? ID::Y : ID::Q); SigSpec sig = sigmap(sig_qy); + if (cell->get_bool_attribute(ID(clk2fflogic))) + sig_qy = cell->getPort(ID::D); // For a clk2fflogic $_FF_ the named signal is the D input not the Q output + for (int i = 0; i < GetSize(sig_qy); i++) { if (sig_qy[i].wire == nullptr || sig[i].wire == nullptr) continue; diff --git a/yosys/backends/aiger/xaiger.cc b/yosys/backends/aiger/xaiger.cc index e223f185e5e..68c2ff52f55 100644 --- a/yosys/backends/aiger/xaiger.cc +++ b/yosys/backends/aiger/xaiger.cc @@ -274,6 +274,10 @@ struct XAigerWriter continue; auto offset = i.first.offset; + auto rhs = cell->getPort(i.first.name); + if (offset >= rhs.size()) + continue; + #ifndef NDEBUG if (ys_debug(1)) { static pool> seen; @@ -281,7 +285,7 @@ struct XAigerWriter log_id(cell->type), log_id(i.first.name), offset, d); } #endif - arrival_times[cell->getPort(i.first.name)[offset]] = d; + arrival_times[rhs[offset]] = d; } if (abc9_flop) diff --git a/yosys/backends/blif/blif.cc b/yosys/backends/blif/blif.cc index 23d1d58fc20..8e2c088c484 100644 --- a/yosys/backends/blif/blif.cc +++ b/yosys/backends/blif/blif.cc @@ -512,8 +512,8 @@ struct BlifBackend : public Backend { log(" suppresses the generation of this nets without fanout.\n"); log("\n"); log("The following options can be useful when the generated file is not going to be\n"); - log("read by a BLIF parser but a custom tool. It is recommended to not name the\n"); - log("output file *.blif when any of this options is used.\n"); + log("read by a BLIF parser but a custom tool. It is recommended not to name the\n"); + log("output file *.blif when any of these options are used.\n"); log("\n"); log(" -icells\n"); log(" do not translate Yosys's internal gates to generic BLIF logic\n"); diff --git a/yosys/backends/btor/btor.cc b/yosys/backends/btor/btor.cc index 4c43e91e796..9cfd967e581 100644 --- a/yosys/backends/btor/btor.cc +++ b/yosys/backends/btor/btor.cc @@ -728,7 +728,10 @@ struct BtorWorker else btorf("%d state %d %s\n", nid, sid, log_id(symbol)); - ywmap_state(sig_q); + if (cell->get_bool_attribute(ID(clk2fflogic))) + ywmap_state(cell->getPort(ID::D)); // For a clk2fflogic FF the named signal is the D input not the Q output + else + ywmap_state(sig_q); if (nid_init_val >= 0) { int nid_init = next_nid++; diff --git a/yosys/backends/cxxrtl/cxxrtl.h b/yosys/backends/cxxrtl/cxxrtl.h index 073921cc49e..5d0596f0d61 100644 --- a/yosys/backends/cxxrtl/cxxrtl.h +++ b/yosys/backends/cxxrtl/cxxrtl.h @@ -1595,6 +1595,25 @@ value modfloor_ss(const value &a, const value &b) { return r; } +template +CXXRTL_ALWAYS_INLINE +value divfloor_uu(const value &a, const value &b) { + return divmod_uu(a, b).first; +} + +// Divfloor. Similar to above: returns q=a//b, where q has the sign of a*b and a=b*q+N. +// In other words, returns (truncating) a/b, except if a and b have different signs +// and there's non-zero remainder, subtract one more towards floor. +template +CXXRTL_ALWAYS_INLINE +value divfloor_ss(const value &a, const value &b) { + value q, r; + std::tie(q, r) = divmod_ss(a, b); + if ((b.is_neg() != a.is_neg()) && !r.is_zero()) + return sub_uu(q, value<1> { 1u }); + return q; + +} // Memory helper struct memory_index { diff --git a/yosys/backends/cxxrtl/cxxrtl_backend.cc b/yosys/backends/cxxrtl/cxxrtl_backend.cc index 62768bd3395..1b13985ab4e 100644 --- a/yosys/backends/cxxrtl/cxxrtl_backend.cc +++ b/yosys/backends/cxxrtl/cxxrtl_backend.cc @@ -185,7 +185,7 @@ bool is_binary_cell(RTLIL::IdString type) ID($and), ID($or), ID($xor), ID($xnor), ID($logic_and), ID($logic_or), ID($shl), ID($sshl), ID($shr), ID($sshr), ID($shift), ID($shiftx), ID($eq), ID($ne), ID($eqx), ID($nex), ID($gt), ID($ge), ID($lt), ID($le), - ID($add), ID($sub), ID($mul), ID($div), ID($mod), ID($modfloor)); + ID($add), ID($sub), ID($mul), ID($div), ID($mod), ID($modfloor), ID($divfloor)); } bool is_extending_cell(RTLIL::IdString type) diff --git a/yosys/backends/edif/edif.cc b/yosys/backends/edif/edif.cc index 7722d0c3394..00fd7f54e39 100644 --- a/yosys/backends/edif/edif.cc +++ b/yosys/backends/edif/edif.cc @@ -120,6 +120,9 @@ struct EdifBackend : public Backend { log(" sets the delimiting character for module port rename clauses to\n"); log(" parentheses, square brackets, or angle brackets.\n"); log("\n"); + log(" -lsbidx\n"); + log(" use index 0 for the LSB bit of a net or port instead of MSB.\n"); + log("\n"); log("Unfortunately there are different \"flavors\" of the EDIF file format. This\n"); log("command generates EDIF files for the Xilinx place&route tools. It might be\n"); log("necessary to make small modifications to this command when a different tool\n"); @@ -132,6 +135,7 @@ struct EdifBackend : public Backend { std::string top_module_name; bool port_rename = false; bool attr_properties = false; + bool lsbidx = false; std::map> lib_cell_ports; bool nogndvcc = false, gndvccy = false, keepmode = false; CellTypes ct(design); @@ -173,6 +177,10 @@ struct EdifBackend : public Backend { } continue; } + if (args[argidx] == "-lsbidx") { + lsbidx = true; + continue; + } break; } extra_args(f, filename, args, argidx); @@ -184,6 +192,14 @@ struct EdifBackend : public Backend { for (auto module : design->modules()) { + lib_cell_ports[module->name]; + + for (auto port : module->ports) + { + Wire *wire = module->wire(port); + lib_cell_ports[module->name][port] = std::max(lib_cell_ports[module->name][port], GetSize(wire)); + } + if (module->get_blackbox_attribute()) continue; @@ -200,7 +216,7 @@ struct EdifBackend : public Backend { if (design->module(cell->type) == nullptr || design->module(cell->type)->get_blackbox_attribute()) { lib_cell_ports[cell->type]; for (auto p : cell->connections()) - lib_cell_ports[cell->type][p.first] = GetSize(p.second); + lib_cell_ports[cell->type][p.first] = std::max(lib_cell_ports[cell->type][p.first], GetSize(p.second)); } } } @@ -437,7 +453,7 @@ struct EdifBackend : public Backend { *f << ")\n"; for (int i = 0; i < wire->width; i++) { RTLIL::SigSpec sig = sigmap(RTLIL::SigSpec(wire, i)); - net_join_db[sig].insert(make_pair(stringf("(portRef (member %s %d))", EDIF_REF(wire->name), GetSize(wire)-i-1), wire->port_input)); + net_join_db[sig].insert(make_pair(stringf("(portRef (member %s %d))", EDIF_REF(wire->name), lsbidx ? i : GetSize(wire)-i-1), wire->port_input)); } } } @@ -468,13 +484,13 @@ struct EdifBackend : public Backend { log_warning("Bit %d of cell port %s.%s.%s driven by %s will be left unconnected in EDIF output.\n", i, log_id(module), log_id(cell), log_id(p.first), log_signal(sig[i])); else { - int member_idx = GetSize(sig)-i-1; + int member_idx = lsbidx ? i : GetSize(sig)-i-1; auto m = design->module(cell->type); int width = sig.size(); if (m) { auto w = m->wire(p.first); if (w) { - member_idx = GetSize(w)-i-1; + member_idx = lsbidx ? i : GetSize(w)-i-1; width = GetSize(w); } } diff --git a/yosys/backends/firrtl/firrtl.cc b/yosys/backends/firrtl/firrtl.cc index eb30ab4b948..fc1d628915c 100644 --- a/yosys/backends/firrtl/firrtl.cc +++ b/yosys/backends/firrtl/firrtl.cc @@ -21,7 +21,6 @@ #include "kernel/register.h" #include "kernel/sigtools.h" #include "kernel/celltypes.h" -#include "kernel/cellaigs.h" #include "kernel/log.h" #include "kernel/mem.h" #include @@ -1196,6 +1195,7 @@ struct FirrtlBackend : public Backend { log(" pmuxtree\n"); log(" bmuxmap\n"); log(" demuxmap\n"); + log(" bwmuxmap\n"); log("\n"); } void execute(std::ostream *&f, std::string filename, std::vector args, RTLIL::Design *design) override diff --git a/yosys/backends/jny/jny.cc b/yosys/backends/jny/jny.cc index 0be11a52cca..9989feed599 100644 --- a/yosys/backends/jny/jny.cc +++ b/yosys/backends/jny/jny.cc @@ -21,7 +21,6 @@ #include "kernel/register.h" #include "kernel/sigtools.h" #include "kernel/celltypes.h" -#include "kernel/cellaigs.h" #include "kernel/log.h" #include #include diff --git a/yosys/backends/smt2/smt2.cc b/yosys/backends/smt2/smt2.cc index 48da3f4be57..5e63e62370d 100644 --- a/yosys/backends/smt2/smt2.cc +++ b/yosys/backends/smt2/smt2.cc @@ -626,9 +626,13 @@ struct Smt2Worker } bool init_only = cell->type.in(ID($anyconst), ID($anyinit), ID($allconst)); - for (auto chunk : cell->getPort(QY).chunks()) + bool clk2fflogic = cell->type == ID($anyinit) && cell->get_bool_attribute(ID(clk2fflogic)); + int smtoffset = 0; + for (auto chunk : cell->getPort(clk2fflogic ? ID::D : QY).chunks()) { if (chunk.is_wire()) - decls.push_back(witness_signal(init_only ? "init" : "seq", chunk.width, chunk.offset, "", idcounter, chunk.wire)); + decls.push_back(witness_signal(init_only ? "init" : "seq", chunk.width, chunk.offset, "", idcounter, chunk.wire, smtoffset)); + smtoffset += chunk.width; + } makebits(stringf("%s#%d", get_id(module), idcounter), GetSize(cell->getPort(QY)), log_signal(cell->getPort(QY))); if (cell->type == ID($anyseq)) @@ -769,7 +773,7 @@ struct Smt2Worker int arrayid = idcounter++; memarrays[mem] = arrayid; - int abits = ceil_log2(mem->size); + int abits = max(1, ceil_log2(mem->size)); bool has_sync_wr = false; bool has_async_wr = false; @@ -1216,7 +1220,7 @@ struct Smt2Worker { int arrayid = memarrays.at(mem); - int abits = ceil_log2(mem->size);; + int abits = max(1, ceil_log2(mem->size)); bool has_sync_wr = false; bool has_async_wr = false; diff --git a/yosys/backends/smt2/smtbmc.py b/yosys/backends/smt2/smtbmc.py index cb21eb3aa4b..02e15a1b502 100644 --- a/yosys/backends/smt2/smtbmc.py +++ b/yosys/backends/smt2/smtbmc.py @@ -59,9 +59,12 @@ so = SmtOpts() -def usage(): +def help(): print(os.path.basename(sys.argv[0]) + """ [options] + -h, --help + show this message + -t -t : -t :: @@ -171,6 +174,8 @@ def usage(): further failed assertions. To output multiple traces covering all found failed assertions, the character '%' is replaced in all dump filenames with an increasing number. + In cover mode, don't stop when a cover trace contains a failed + assertion. --check-witness check that the used witness file contains sufficient @@ -181,19 +186,25 @@ def usage(): (this feature is experimental and incomplete) """ + so.helpmsg()) + +def usage(): + help() sys.exit(1) try: - opts, args = getopt.getopt(sys.argv[1:], so.shortopts + "t:igcm:", so.longopts + - ["final-only", "assume-skipped=", "smtc=", "cex=", "aig=", "aig-noheader", "yw=", "btorwit=", "presat", + opts, args = getopt.getopt(sys.argv[1:], so.shortopts + "t:higcm:", so.longopts + + ["help", "final-only", "assume-skipped=", "smtc=", "cex=", "aig=", "aig-noheader", "yw=", "btorwit=", "presat", "dump-vcd=", "dump-yw=", "dump-vlogtb=", "vlogtb-top=", "dump-smtc=", "dump-all", "noinfo", "append=", "smtc-init", "smtc-top=", "noinit", "binary", "keep-going", "check-witness", "detect-loops"]) except: usage() for o, a in opts: - if o == "-t": + if o in ("-h", "--help"): + help() + sys.exit(0) + elif o == "-t": got_topt = True a = a.split(":") if len(a) == 1: @@ -1730,7 +1741,7 @@ def smt_check_sat(expected=["sat", "unsat"]): smt_pop() smt.write("(define-fun covers_%d ((state |%s_s|)) (_ BitVec %d) (bvand (covers_%d state) #b%s))" % (coveridx, topmod, len(cover_desc), coveridx-1, cover_mask)) - if found_failed_assert: + if found_failed_assert and not keep_going: break if "1" not in cover_mask: diff --git a/yosys/backends/smt2/smtio.py b/yosys/backends/smt2/smtio.py index a7374589690..0ec7f08f4dc 100644 --- a/yosys/backends/smt2/smtio.py +++ b/yosys/backends/smt2/smtio.py @@ -245,6 +245,7 @@ def setup(self): self.logic_uf = False self.unroll_idcnt = 0 self.unroll_buffer = "" + self.unroll_level = 0 self.unroll_sorts = set() self.unroll_objs = set() self.unroll_decls = dict() @@ -420,13 +421,15 @@ def write(self, stmt, unroll=True): self.p_close() if unroll and self.unroll: - stmt = self.unroll_buffer + stmt - self.unroll_buffer = "" - s = re.sub(r"\|[^|]*\|", "", stmt) - if s.count("(") != s.count(")"): - self.unroll_buffer = stmt + " " + self.unroll_level += s.count("(") - s.count(")") + if self.unroll_level > 0: + self.unroll_buffer += stmt + self.unroll_buffer += " " return + else: + stmt = self.unroll_buffer + stmt + self.unroll_buffer = "" s = self.parse(stmt) @@ -768,7 +771,7 @@ def check_sat(self, expected=["sat", "unsat", "unknown", "timeout", "interrupted if self.timeinfo: i = 0 - s = "/-\|" + s = r"/-\|" count = 0 num_bs = 0 @@ -1171,7 +1174,7 @@ def set_net(self, path, bits): def escape_name(self, name): name = re.sub(r"\[([0-9a-zA-Z_]*[a-zA-Z_][0-9a-zA-Z_]*)\]", r"<\1>", name) - if re.match("[\[\]]", name) and name[0] != "\\": + if re.match(r"[\[\]]", name) and name[0] != "\\": name = "\\" + name return name diff --git a/yosys/backends/smt2/witness.py b/yosys/backends/smt2/witness.py index 8d0cc8112d1..7d5a2469eb5 100644 --- a/yosys/backends/smt2/witness.py +++ b/yosys/backends/smt2/witness.py @@ -194,7 +194,7 @@ def aiw2yw(input, mapfile, output): values = WitnessValues() for i, v in enumerate(inline): - if v == "x" or outyw.t > 0 and i in aiger_map.init_inputs: + if outyw.t > 0 and i in aiger_map.init_inputs: continue try: diff --git a/yosys/backends/verilog/verilog_backend.cc b/yosys/backends/verilog/verilog_backend.cc index 0a9c0590eb7..5ff191a9c16 100644 --- a/yosys/backends/verilog/verilog_backend.cc +++ b/yosys/backends/verilog/verilog_backend.cc @@ -37,7 +37,7 @@ PRIVATE_NAMESPACE_BEGIN bool verbose, norename, noattr, attr2comment, noexpr, nodec, nohex, nostr, extmem, defparam, decimal, siminit, systemverilog, simple_lhs, noparallelcase; int auto_name_counter, auto_name_offset, auto_name_digits, extmem_counter; -std::map auto_name_map; +dict auto_name_map; std::set reg_wires; std::string auto_prefix, extmem_prefix; @@ -129,7 +129,7 @@ std::string id(RTLIL::IdString internal_id, bool may_rename = true) break; } - const pool keywords = { + static const pool keywords = { // IEEE 1800-2017 Annex B "accept_on", "alias", "always", "always_comb", "always_ff", "always_latch", "and", "assert", "assign", "assume", "automatic", "before", "begin", "bind", "bins", "binsof", "bit", "break", "buf", "bufif0", "bufif1", "byte", "case", "casex", "casez", "cell", "chandle", @@ -2329,7 +2329,6 @@ struct VerilogBackend : public Backend { if (!noexpr) { Pass::call(design, "bmuxmap"); Pass::call(design, "demuxmap"); - Pass::call(design, "bwmuxmap"); } Pass::call(design, "clean_zerowidth"); log_pop(); diff --git a/yosys/docs/source/CHAPTER_CellLib.rst b/yosys/docs/source/CHAPTER_CellLib.rst index c5db434a64f..c8904086879 100644 --- a/yosys/docs/source/CHAPTER_CellLib.rst +++ b/yosys/docs/source/CHAPTER_CellLib.rst @@ -571,7 +571,7 @@ The ``$mem_v2`` cell has the following ports: signals for the read ports. ``\RD_DATA`` - This input is ``\RD_PORTS*\WIDTH`` bits wide, containing all data + This output is ``\RD_PORTS*\WIDTH`` bits wide, containing all data signals for the read ports. ``\RD_ARST`` diff --git a/yosys/docs/source/CHAPTER_Memorymap.rst b/yosys/docs/source/CHAPTER_Memorymap.rst new file mode 100644 index 00000000000..cdc381eed81 --- /dev/null +++ b/yosys/docs/source/CHAPTER_Memorymap.rst @@ -0,0 +1,654 @@ +.. _chapter:memorymap: + +Memory mapping +============== + +Documentation for the Yosys ``memory_libmap`` memory mapper. Note that not all supported patterns +are included in this document, of particular note is that combinations of multiple patterns should +generally work. For example, `Write port with byte enables`_ could be used in conjunction with any +of the simple dual port (SDP) models. In general if a hardware memory definition does not support a +given configuration, additional logic will be instantiated to guarantee behaviour is consistent with +simulation. + +See also: `passes/memory/memlib.md `_ + +Additional notes +---------------- + +Memory kind selection +~~~~~~~~~~~~~~~~~~~~~ + +The memory inference code will automatically pick target memory primitive based on memory geometry +and features used. Depending on the target, there can be up to four memory primitive classes +available for selection: + +- FF RAM (aka logic): no hardware primitive used, memory lowered to a bunch of FFs and multiplexers + + - Can handle arbitrary number of write ports, as long as all write ports are in the same clock domain + - Can handle arbitrary number and kind of read ports + +- LUT RAM (aka distributed RAM): uses LUT storage as RAM + + - Supported on most FPGAs (with notable exception of ice40) + - Usually has one synchronous write port, one or more asynchronous read ports + - Small + - Will never be used for ROMs (lowering to plain LUTs is always better) + +- Block RAM: dedicated memory tiles + + - Supported on basically all FPGAs + - Supports only synchronous reads + - Two ports with separate clocks + - Usually supports true dual port (with notable exception of ice40 that only supports SDP) + - Usually supports asymmetric memories and per-byte write enables + - Several kilobits in size + +- Huge RAM: + + - Only supported on several targets: + + - Some Xilinx UltraScale devices (UltraRAM) + + - Two ports, both with mutually exclusive synchronous read and write + - Single clock + - Initial data must be all-0 + + - Some ice40 devices (SPRAM) + + - Single port with mutually exclusive synchronous read and write + - Does not support initial data + + - Nexus (large RAM) + + - Two ports, both with mutually exclusive synchronous read and write + - Single clock + + - Will not be automatically selected by memory inference code, needs explicit opt-in via + ram_style attribute + +In general, you can expect the automatic selection process to work roughly like this: + +- If any read port is asynchronous, only LUT RAM (or FF RAM) can be used. +- If there is more than one write port, only block RAM can be used, and this needs to be a + hardware-supported true dual port pattern + + - … unless all write ports are in the same clock domain, in which case FF RAM can also be used, + but this is generally not what you want for anything but really small memories + +- Otherwise, either FF RAM, LUT RAM, or block RAM will be used, depending on memory size + +This process can be overridden by attaching a ram_style attribute to the memory: + +- `(* ram_style = "logic" *)` selects FF RAM +- `(* ram_style = "distributed" *)` selects LUT RAM +- `(* ram_style = "block" *)` selects block RAM +- `(* ram_style = "huge" *)` selects huge RAM + +It is an error if this override cannot be realized for the given target. + +Many alternate spellings of the attribute are also accepted, for compatibility with other software. + +Initial data +~~~~~~~~~~~~ + +Most FPGA targets support initializing all kinds of memory to user-provided values. If explicit +initialization is not used the initial memory value is undefined. Initial data can be provided by +either initial statements writing memory cells one by one of ``$readmemh`` or ``$readmemb`` system +tasks. For an example pattern, see `Synchronous read port with initial value`_. + +Write port with byte enables +~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +- Byte enables can be used with any supported pattern +- To ensure that multiple writes will be merged into one port, they need to have disjoint bit + ranges, have the same address, and the same clock +- Any write enable granularity will be accepted (down to per-bit write enables), but using smaller + granularity than natively supported by the target is very likely to be inefficient (eg. using + 4-bit bytes on ECP5 will result in either padding the bytes with 5 dummy bits to native 9-bit + units or splitting the RAM into two block RAMs) + +.. code:: verilog + + reg [31 : 0] mem [2**ADDR_WIDTH - 1 : 0]; + + always @(posedge clk) begin + if (write_enable[0]) + mem[write_addr][7:0] <= write_data[7:0]; + if (write_enable[1]) + mem[write_addr][15:8] <= write_data[15:8]; + if (write_enable[2]) + mem[write_addr][23:16] <= write_data[23:16]; + if (write_enable[3]) + mem[write_addr][31:24] <= write_data[31:24]; + if (read_enable) + read_data <= mem[read_addr]; + end + +Simple dual port (SDP) memory patterns +-------------------------------------- + +Asynchronous-read SDP +~~~~~~~~~~~~~~~~~~~~~ + +- This will result in LUT RAM on supported targets + +.. code:: verilog + + reg [DATA_WIDTH - 1 : 0] mem [2**ADDR_WIDTH - 1 : 0]; + always @(posedge clk) + if (write_enable) + mem[write_addr] <= write_data; + assign read_data = mem[read_addr]; + +Synchronous SDP with clock domain crossing +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +- Will result in block RAM or LUT RAM depending on size +- No behavior guarantees in case of simultaneous read and write to the same address + +.. code:: verilog + + reg [DATA_WIDTH - 1 : 0] mem [2**ADDR_WIDTH - 1 : 0]; + + always @(posedge write_clk) begin + if (write_enable) + mem[write_addr] <= write_data; + end + + always @(posedge read_clk) begin + if (read_enable) + read_data <= mem[read_addr]; + end + +Synchronous SDP read first +~~~~~~~~~~~~~~~~~~~~~~~~~~ + +- The read and write parts can be in the same or different processes. +- Will result in block RAM or LUT RAM depending on size +- As long as the same clock is used for both, yosys will ensure read-first behavior. This may + require extra circuitry on some targets for block RAM. If this is not necessary, use one of the + patterns below. + +.. code:: verilog + + reg [DATA_WIDTH - 1 : 0] mem [2**ADDR_WIDTH - 1 : 0]; + + always @(posedge clk) begin + if (write_enable) + mem[write_addr] <= write_data; + if (read_enable) + read_data <= mem[read_addr]; + end + +Synchronous SDP with undefined collision behavior +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +- Like above, but the read value is undefined when read and write ports target the same address in + the same cycle + +.. code:: verilog + + reg [DATA_WIDTH - 1 : 0] mem [2**ADDR_WIDTH - 1 : 0]; + + always @(posedge clk) begin + if (write_enable) + mem[write_addr] <= write_data; + + if (read_enable) begin + read_data <= mem[read_addr]; + + // 👇 this if block 👇 + if (write_enable && read_addr == write_addr) + read_data <= 'x; + end + end + +- Or below, using the no_rw_check attribute + +.. code:: verilog + + (* no_rw_check *) + reg [DATA_WIDTH - 1 : 0] mem [2**ADDR_WIDTH - 1 : 0]; + + always @(posedge clk) begin + if (write_enable) + mem[write_addr] <= write_data; + + if (read_enable) + read_data <= mem[read_addr]; + end + +Synchronous SDP with write-first behavior +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +- Will result in block RAM or LUT RAM depending on size +- May use additional circuitry for block RAM if write-first is not natively supported. Will always + use additional circuitry for LUT RAM. + +.. code:: verilog + + reg [DATA_WIDTH - 1 : 0] mem [2**ADDR_WIDTH - 1 : 0]; + + always @(posedge clk) begin + if (write_enable) + mem[write_addr] <= write_data; + + if (read_enable) begin + read_data <= mem[read_addr]; + if (write_enable && read_addr == write_addr) + read_data <= write_data; + end + end + +Synchronous SDP with write-first behavior (alternate pattern) +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +- This pattern is supported for compatibility, but is much less flexible than the above + +.. code:: verilog + + reg [DATA_WIDTH - 1 : 0] mem [2**ADDR_WIDTH - 1 : 0]; + + always @(posedge clk) begin + if (write_enable) + mem[write_addr] <= write_data; + read_addr_reg <= read_addr; + end + + assign read_data = mem[read_addr_reg]; + +Single-port RAM memory patterns +------------------------------- + +Asynchronous-read single-port RAM +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +- Will result in single-port LUT RAM on supported targets + +.. code:: verilog + + reg [DATA_WIDTH - 1 : 0] mem [2**ADDR_WIDTH - 1 : 0]; + always @(posedge clk) + if (write_enable) + mem[addr] <= write_data; + assign read_data = mem[addr]; + +Synchronous single-port RAM with mutually exclusive read/write +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +- Will result in single-port block RAM or LUT RAM depending on size +- This is the correct pattern to infer ice40 SPRAM (with manual ram_style selection) +- On targets that don't support read/write block RAM ports (eg. ice40), will result in SDP block RAM instead +- For block RAM, will use "NO_CHANGE" mode if available + +.. code:: verilog + + reg [DATA_WIDTH - 1 : 0] mem [2**ADDR_WIDTH - 1 : 0]; + + always @(posedge clk) begin + if (write_enable) + mem[addr] <= write_data; + else if (read_enable) + read_data <= mem[addr]; + end + +Synchronous single-port RAM with read-first behavior +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +- Will only result in single-port block RAM when read-first behavior is natively supported; + otherwise, SDP RAM with additional circuitry will be used +- Many targets (Xilinx, ECP5, …) can only natively support read-first/write-first single-port RAM + (or TDP RAM) where the write_enable signal implies the read_enable signal (ie. can never write + without reading). The memory inference code will run a simple SAT solver on the control signals to + determine if this is the case, and insert emulation circuitry if it cannot be easily proven. + +.. code:: verilog + + reg [DATA_WIDTH - 1 : 0] mem [2**ADDR_WIDTH - 1 : 0]; + + always @(posedge clk) begin + if (write_enable) + mem[addr] <= write_data; + if (read_enable) + read_data <= mem[addr]; + end + +Synchronous single-port RAM with write-first behavior +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +- Will result in single-port block RAM or LUT RAM when supported +- Block RAMs will require extra circuitry if write-first behavior not natively supported + +.. code:: verilog + + reg [DATA_WIDTH - 1 : 0] mem [2**ADDR_WIDTH - 1 : 0]; + + always @(posedge clk) begin + if (write_enable) + mem[addr] <= write_data; + if (read_enable) + if (write_enable) + read_data <= write_data; + else + read_data <= mem[addr]; + end + +Synchronous read port with initial value +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +- Initial read port values can be combined with any other supported pattern +- If block RAM is used and initial read port values are not natively supported by the target, small + emulation circuit will be inserted + +.. code:: verilog + + reg [DATA_WIDTH - 1 : 0] mem [2**ADDR_WIDTH - 1 : 0]; + reg [DATA_WIDTH - 1 : 0] read_data; + initial read_data = 'h1234; + + always @(posedge clk) begin + if (write_enable) + mem[write_addr] <= write_data; + if (read_enable) + read_data <= mem[read_addr]; + end + +Read register reset patterns +---------------------------- + +Resets can be combined with any other supported pattern (except that synchronous reset and +asynchronous reset cannot both be used on a single read port). If block RAM is used and the +selected reset (synchronous or asynchronous) is used but not natively supported by the target, small +emulation circuitry will be inserted. + +Synchronous reset, reset priority over enable +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +.. code:: verilog + + reg [DATA_WIDTH - 1 : 0] mem [2**ADDR_WIDTH - 1 : 0]; + + always @(posedge clk) begin + if (write_enable) + mem[write_addr] <= write_data; + + if (read_reset) + read_data <= {sval}; + else if (read_enable) + read_data <= mem[read_addr]; + end + +Synchronous reset, enable priority over reset +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +.. code:: verilog + + reg [DATA_WIDTH - 1 : 0] mem [2**ADDR_WIDTH - 1 : 0]; + + always @(posedge clk) begin + if (write_enable) + mem[write_addr] <= write_data; + if (read_enable) + if (read_reset) + read_data <= 'h1234; + else + read_data <= mem[read_addr]; + end + +Synchronous read port with asynchronous reset +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +.. code:: verilog + + reg [DATA_WIDTH - 1 : 0] mem [2**ADDR_WIDTH - 1 : 0]; + + always @(posedge clk) begin + if (write_enable) + mem[write_addr] <= write_data; + end + + always @(posedge clk, posedge reset_read) begin + if (reset_read) + read_data <= 'h1234; + else if (read_enable) + read_data <= mem[read_addr]; + end + +Asymmetric memory patterns +-------------------------- + +To construct an asymmetric memory (memory with read/write ports of differing widths): + +- Declare the memory with the width of the narrowest intended port +- Split all wide ports into multiple narrow ports +- To ensure the wide ports will be correctly merged: + + - For the address, use a concatenation of actual address in the high bits and a constant in the + low bits + - Ensure the actual address is identical for all ports belonging to the wide port + - Ensure that clock is identical + - For read ports, ensure that enable/reset signals are identical (for write ports, the enable + signal may vary — this will result in using the byte enable functionality) + +Asymmetric memory is supported on all targets, but may require emulation circuitry where not +natively supported. Note that when the memory is larger than the underlying block RAM primitive, +hardware asymmetric memory support is likely not to be used even if present as it is more expensive. + +Wide synchronous read port +~~~~~~~~~~~~~~~~~~~~~~~~~~ + +.. code:: verilog + + reg [7:0] mem [0:255]; + wire [7:0] write_addr; + wire [5:0] read_addr; + wire [7:0] write_data; + reg [31:0] read_data; + + always @(posedge clk) begin + if (write_enable) + mem[write_addr] <= write_data; + if (read_enable) begin + read_data[7:0] <= mem[{read_addr, 2'b00}]; + read_data[15:8] <= mem[{read_addr, 2'b01}]; + read_data[23:16] <= mem[{read_addr, 2'b10}]; + read_data[31:24] <= mem[{read_addr, 2'b11}]; + end + end + +Wide asynchronous read port +~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +- Note: the only target natively supporting this pattern is Xilinx UltraScale + +.. code:: verilog + + reg [7:0] mem [0:511]; + wire [8:0] write_addr; + wire [5:0] read_addr; + wire [7:0] write_data; + wire [63:0] read_data; + + always @(posedge clk) begin + if (write_enable) + mem[write_addr] <= write_data; + end + + assign read_data[7:0] = mem[{read_addr, 3'b000}]; + assign read_data[15:8] = mem[{read_addr, 3'b001}]; + assign read_data[23:16] = mem[{read_addr, 3'b010}]; + assign read_data[31:24] = mem[{read_addr, 3'b011}]; + assign read_data[39:32] = mem[{read_addr, 3'b100}]; + assign read_data[47:40] = mem[{read_addr, 3'b101}]; + assign read_data[55:48] = mem[{read_addr, 3'b110}]; + assign read_data[63:56] = mem[{read_addr, 3'b111}]; + +Wide write port +~~~~~~~~~~~~~~~ + +.. code:: verilog + + reg [7:0] mem [0:255]; + wire [5:0] write_addr; + wire [7:0] read_addr; + wire [31:0] write_data; + reg [7:0] read_data; + + always @(posedge clk) begin + if (write_enable[0]) + mem[{write_addr, 2'b00}] <= write_data[7:0]; + if (write_enable[1]) + mem[{write_addr, 2'b01}] <= write_data[15:8]; + if (write_enable[2]) + mem[{write_addr, 2'b10}] <= write_data[23:16]; + if (write_enable[3]) + mem[{write_addr, 2'b11}] <= write_data[31:24]; + if (read_enable) + read_data <= mem[read_addr]; + end + +True dual port (TDP) patterns +----------------------------- + +- Many different variations of true dual port memory can be created by combining two single-port RAM + patterns on the same memory +- When TDP memory is used, memory inference code has much less maneuver room to create requested + semantics compared to individual single-port patterns (which can end up lowered to SDP memory + where necessary) — supported patterns depend strongly on the target +- In particular, when both ports have the same clock, it's likely that "undefined collision" mode + needs to be manually selected to enable TDP memory inference +- The examples below are non-exhaustive — many more combinations of port types are possible +- Note: if two write ports are in the same process, this defines a priority relation between them + (if both ports are active in the same clock, the later one wins). On almost all targets, this will + result in a bit of extra circuitry to ensure the priority semantics. If this is not what you want, + put them in separate processes. + + - Priority is not supported when using the verific front end and any priority semantics are ignored. + +TDP with different clocks, exclusive read/write +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +.. code:: verilog + + reg [DATA_WIDTH - 1 : 0] mem [2**ADDR_WIDTH - 1 : 0]; + + always @(posedge clk_a) begin + if (write_enable_a) + mem[addr_a] <= write_data_a; + else if (read_enable_a) + read_data_a <= mem[addr_a]; + end + + always @(posedge clk_b) begin + if (write_enable_b) + mem[addr_b] <= write_data_b; + else if (read_enable_b) + read_data_b <= mem[addr_b]; + end + +TDP with same clock, read-first behavior +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +- This requires hardware inter-port read-first behavior, and will only work on some targets (Xilinx, Nexus) + +.. code:: verilog + + reg [DATA_WIDTH - 1 : 0] mem [2**ADDR_WIDTH - 1 : 0]; + + always @(posedge clk) begin + if (write_enable_a) + mem[addr_a] <= write_data_a; + if (read_enable_a) + read_data_a <= mem[addr_a]; + end + + always @(posedge clk) begin + if (write_enable_b) + mem[addr_b] <= write_data_b; + if (read_enable_b) + read_data_b <= mem[addr_b]; + end + +TDP with multiple read ports +~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +- The combination of a single write port with an arbitrary amount of read ports is supported on all + targets — if a multi-read port primitive is available (like Xilinx RAM64M), it'll be used as + appropriate. Otherwise, the memory will be automatically split into multiple primitives. + +.. code:: verilog + + reg [31:0] mem [0:31]; + + always @(posedge clk) begin + if (write_enable) + mem[write_addr] <= write_data; + end + + assign read_data_a = mem[read_addr_a]; + assign read_data_b = mem[read_addr_b]; + assign read_data_c = mem[read_addr_c]; + +Not yet supported patterns +-------------------------- + +Synchronous SDP with write-first behavior via blocking assignments +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +- Would require modifications to the Yosys Verilog frontend. +- Use `Synchronous SDP with write-first behavior`_ instead + +.. code:: verilog + + reg [DATA_WIDTH - 1 : 0] mem [2**ADDR_WIDTH - 1 : 0]; + + always @(posedge clk) begin + if (write_enable) + mem[write_addr] = write_data; + + if (read_enable) + read_data <= mem[read_addr]; + end + +Asymmetric memories via part selection +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +- Would require major changes to the Verilog frontend. +- Build wide ports out of narrow ports instead (see `Wide synchronous read port`_) + +.. code:: verilog + + reg [31:0] mem [2**ADDR_WIDTH - 1 : 0]; + + wire [1:0] byte_lane; + wire [7:0] write_data; + + always @(posedge clk) begin + if (write_enable) + mem[write_addr][byte_lane * 8 +: 8] <= write_data; + + if (read_enable) + read_data <= mem[read_addr]; + end + + +Undesired patterns +------------------ + +Asynchronous writes +~~~~~~~~~~~~~~~~~~~ + +- Not supported in modern FPGAs +- Not supported in yosys code anyhow + +.. code:: verilog + + reg [DATA_WIDTH - 1 : 0] mem [2**ADDR_WIDTH - 1 : 0]; + + always @* begin + if (write_enable) + mem[write_addr] = write_data; + end + + assign read_data = mem[read_addr]; + diff --git a/yosys/docs/source/index.rst b/yosys/docs/source/index.rst index fb864307246..111aea873a4 100644 --- a/yosys/docs/source/index.rst +++ b/yosys/docs/source/index.rst @@ -42,6 +42,7 @@ Yosys manual CHAPTER_Verilog.rst CHAPTER_Optimize.rst CHAPTER_Techmap.rst + CHAPTER_Memorymap.rst CHAPTER_Eval.rst .. raw:: latex diff --git a/yosys/frontends/ast/ast.cc b/yosys/frontends/ast/ast.cc index 982943d1ba9..a027295e979 100644 --- a/yosys/frontends/ast/ast.cc +++ b/yosys/frontends/ast/ast.cc @@ -192,7 +192,7 @@ bool AstNode::get_bool_attribute(RTLIL::IdString id) AstNode *attr = attributes.at(id); if (attr->type != AST_CONSTANT) - log_file_error(attr->filename, attr->location.first_line, "Attribute `%s' with non-constant value!\n", id.c_str()); + attr->input_error("Attribute `%s' with non-constant value!\n", id.c_str()); return attr->integer != 0; } @@ -524,7 +524,13 @@ void AstNode::dumpVlog(FILE *f, std::string indent) const break; case AST_IDENTIFIER: - fprintf(f, "%s", id2vl(str).c_str()); + { + AST::AstNode *member_node = AST::get_struct_member(this); + if (member_node) + fprintf(f, "%s[%d:%d]", id2vl(str).c_str(), member_node->range_left, member_node->range_right); + else + fprintf(f, "%s", id2vl(str).c_str()); + } for (auto child : children) child->dumpVlog(f, ""); break; @@ -841,7 +847,7 @@ RTLIL::Const AstNode::bitsAsConst(int width, bool is_signed) bits.resize(width); if (width >= 0 && width > int(bits.size())) { RTLIL::State extbit = RTLIL::State::S0; - if (is_signed && !bits.empty()) + if ((is_signed || is_unsized) && !bits.empty()) extbit = bits.back(); while (width > int(bits.size())) bits.push_back(extbit); @@ -1033,7 +1039,7 @@ static RTLIL::Module *process_module(RTLIL::Design *design, AstNode *ast, bool d { for (const AstNode *node : ast->children) if (node->type == AST_PARAMETER && param_has_no_default(node)) - log_file_error(node->filename, node->location.first_line, "Parameter `%s' has no default value and has not been overridden!\n", node->str.c_str()); + node->input_error("Parameter `%s' has no default value and has not been overridden!\n", node->str.c_str()); bool blackbox_module = flag_lib; @@ -1055,7 +1061,7 @@ static RTLIL::Module *process_module(RTLIL::Design *design, AstNode *ast, bool d // simplify this module or interface using the current design as context // for lookup up ports and wires within cells set_simplify_design_context(design); - while (ast->simplify(!flag_noopt, false, false, 0, -1, false, false)) { } + while (ast->simplify(!flag_noopt, false, 0, -1, false, false)) { } set_simplify_design_context(nullptr); if (flag_dump_ast2) { @@ -1093,14 +1099,14 @@ static RTLIL::Module *process_module(RTLIL::Design *design, AstNode *ast, bool d if (!blackbox_module && ast->attributes.count(ID::blackbox)) { AstNode *n = ast->attributes.at(ID::blackbox); if (n->type != AST_CONSTANT) - log_file_error(ast->filename, ast->location.first_line, "Got blackbox attribute with non-constant value!\n"); + ast->input_error("Got blackbox attribute with non-constant value!\n"); blackbox_module = n->asBool(); } if (blackbox_module && ast->attributes.count(ID::whitebox)) { AstNode *n = ast->attributes.at(ID::whitebox); if (n->type != AST_CONSTANT) - log_file_error(ast->filename, ast->location.first_line, "Got whitebox attribute with non-constant value!\n"); + ast->input_error("Got whitebox attribute with non-constant value!\n"); blackbox_module = !n->asBool(); } @@ -1108,7 +1114,7 @@ static RTLIL::Module *process_module(RTLIL::Design *design, AstNode *ast, bool d if (blackbox_module) { AstNode *n = ast->attributes.at(ID::noblackbox); if (n->type != AST_CONSTANT) - log_file_error(ast->filename, ast->location.first_line, "Got noblackbox attribute with non-constant value!\n"); + ast->input_error("Got noblackbox attribute with non-constant value!\n"); blackbox_module = !n->asBool(); } delete ast->attributes.at(ID::noblackbox); @@ -1152,7 +1158,7 @@ static RTLIL::Module *process_module(RTLIL::Design *design, AstNode *ast, bool d for (auto &attr : ast->attributes) { if (attr.second->type != AST_CONSTANT) - log_file_error(ast->filename, ast->location.first_line, "Attribute `%s' with non-constant value!\n", attr.first.c_str()); + ast->input_error("Attribute `%s' with non-constant value!\n", attr.first.c_str()); module->attributes[attr.first] = attr.second->asAttrConst(); } for (size_t i = 0; i < ast->children.size(); i++) { @@ -1355,7 +1361,7 @@ void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump } else if (child->type == AST_PACKAGE) { // process enum/other declarations - child->simplify(true, false, false, 1, -1, false, false); + child->simplify(true, false, 1, -1, false, false); rename_in_package_stmts(child); design->verilog_packages.push_back(child->clone()); current_scope.clear(); @@ -1835,4 +1841,11 @@ void AstModule::loadconfig() const flag_autowire = autowire; } +void AstNode::input_error(const char *format, ...) const +{ + va_list ap; + va_start(ap, format); + logv_file_error(filename, location.first_line, format, ap); +} + YOSYS_NAMESPACE_END diff --git a/yosys/frontends/ast/ast.h b/yosys/frontends/ast/ast.h index 142ec0801d4..8893d5e010c 100644 --- a/yosys/frontends/ast/ast.h +++ b/yosys/frontends/ast/ast.h @@ -250,7 +250,7 @@ namespace AST // simplify() creates a simpler AST by unrolling for-loops, expanding generate blocks, etc. // it also sets the id2ast pointers so that identifier lookups are fast in genRTLIL() - bool simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, int width_hint, bool sign_hint, bool in_param); + bool simplify(bool const_fold, bool in_lvalue, int stage, int width_hint, bool sign_hint, bool in_param); void replace_result_wire_name_in_function(const std::string &from, const std::string &to); AstNode *readmem(bool is_readmemh, std::string mem_filename, AstNode *memory, int start_addr, int finish_addr, bool unconditional_init); void expand_genblock(const std::string &prefix); @@ -335,6 +335,13 @@ namespace AST // Helper for looking up identifiers which are prefixed with the current module name std::string try_pop_module_prefix() const; + + // helper to clone the node with some of its subexpressions replaced with zero (this is used + // to evaluate widths of dynamic ranges) + AstNode *clone_at_zero(); + + // helper to print errors from simplify/genrtlil code + [[noreturn]] void input_error(const char *format, ...) const YS_ATTRIBUTE(format(printf, 2, 3)); }; // process an AST tree (ast must point to an AST_DESIGN node) and generate RTLIL code @@ -380,6 +387,7 @@ namespace AST // struct helper exposed from simplify for genrtlil AstNode *make_struct_member_range(AstNode *node, AstNode *member_node); + AstNode *get_struct_member(const AstNode *node); // generate standard $paramod... derived module name; parameters should be // in the order they are declared in the instantiated module diff --git a/yosys/frontends/ast/genrtlil.cc b/yosys/frontends/ast/genrtlil.cc index 1016ef636c1..3aa19b70687 100644 --- a/yosys/frontends/ast/genrtlil.cc +++ b/yosys/frontends/ast/genrtlil.cc @@ -56,7 +56,7 @@ static RTLIL::SigSpec uniop2rtlil(AstNode *that, IdString type, int result_width if (gen_attributes) for (auto &attr : that->attributes) { if (attr.second->type != AST_CONSTANT) - log_file_error(that->filename, that->location.first_line, "Attribute `%s' with non-constant value!\n", attr.first.c_str()); + that->input_error("Attribute `%s' with non-constant value!\n", attr.first.c_str()); cell->attributes[attr.first] = attr.second->asAttrConst(); } @@ -88,7 +88,7 @@ static void widthExtend(AstNode *that, RTLIL::SigSpec &sig, int width, bool is_s if (that != NULL) for (auto &attr : that->attributes) { if (attr.second->type != AST_CONSTANT) - log_file_error(that->filename, that->location.first_line, "Attribute `%s' with non-constant value!\n", attr.first.c_str()); + that->input_error("Attribute `%s' with non-constant value!\n", attr.first.c_str()); cell->attributes[attr.first] = attr.second->asAttrConst(); } @@ -114,7 +114,7 @@ static RTLIL::SigSpec binop2rtlil(AstNode *that, IdString type, int result_width for (auto &attr : that->attributes) { if (attr.second->type != AST_CONSTANT) - log_file_error(that->filename, that->location.first_line, "Attribute `%s' with non-constant value!\n", attr.first.c_str()); + that->input_error("Attribute `%s' with non-constant value!\n", attr.first.c_str()); cell->attributes[attr.first] = attr.second->asAttrConst(); } @@ -149,7 +149,7 @@ static RTLIL::SigSpec mux2rtlil(AstNode *that, const RTLIL::SigSpec &cond, const for (auto &attr : that->attributes) { if (attr.second->type != AST_CONSTANT) - log_file_error(that->filename, that->location.first_line, "Attribute `%s' with non-constant value!\n", attr.first.c_str()); + that->input_error("Attribute `%s' with non-constant value!\n", attr.first.c_str()); cell->attributes[attr.first] = attr.second->asAttrConst(); } @@ -179,7 +179,7 @@ struct AST_INTERNAL::LookaheadRewriter wire->str = stringf("$lookahead%s$%d", node->str.c_str(), autoidx++); wire->attributes[ID::nosync] = AstNode::mkconst_int(1, false); wire->is_logic = true; - while (wire->simplify(true, false, false, 1, -1, false, false)) { } + while (wire->simplify(true, false, 1, -1, false, false)) { } current_ast_mod->children.push_back(wire); lookaheadids[node->str] = make_pair(node->id2ast, wire); wire->genRTLIL(); @@ -325,8 +325,7 @@ struct AST_INTERNAL::ProcessGenerator set_src_attr(proc, always); for (auto &attr : always->attributes) { if (attr.second->type != AST_CONSTANT) - log_file_error(always->filename, always->location.first_line, "Attribute `%s' with non-constant value!\n", - attr.first.c_str()); + always->input_error("Attribute `%s' with non-constant value!\n", attr.first.c_str()); proc->attributes[attr.first] = attr.second->asAttrConst(); } current_case = &proc->root_case; @@ -355,7 +354,7 @@ struct AST_INTERNAL::ProcessGenerator if (found_anyedge_syncs) { if (found_global_syncs) - log_file_error(always->filename, always->location.first_line, "Found non-synthesizable event list!\n"); + always->input_error("Found non-synthesizable event list!\n"); log("Note: Assuming pure combinatorial block at %s in\n", always->loc_string().c_str()); log("compliance with IEC 62142(E):2005 / IEEE Std. 1364.1(E):2002. Recommending\n"); log("use of @* instead of @(...) for better match of synthesis and simulation.\n"); @@ -370,12 +369,12 @@ struct AST_INTERNAL::ProcessGenerator continue; found_clocked_sync = true; if (found_global_syncs || found_anyedge_syncs) - log_file_error(always->filename, always->location.first_line, "Found non-synthesizable event list!\n"); + always->input_error("Found non-synthesizable event list!\n"); RTLIL::SyncRule *syncrule = new RTLIL::SyncRule; syncrule->type = child->type == AST_POSEDGE ? RTLIL::STp : RTLIL::STn; syncrule->signal = child->children[0]->genRTLIL(); if (GetSize(syncrule->signal) != 1) - log_file_error(always->filename, always->location.first_line, "Found posedge/negedge event on a signal that is not 1 bit wide!\n"); + always->input_error("Found posedge/negedge event on a signal that is not 1 bit wide!\n"); addChunkActions(syncrule->actions, subst_lvalue_from, subst_lvalue_to, true); proc->syncs.push_back(syncrule); } @@ -604,7 +603,7 @@ struct AST_INTERNAL::ProcessGenerator for (auto &attr : ast->attributes) { if (attr.second->type != AST_CONSTANT) - log_file_error(ast->filename, ast->location.first_line, "Attribute `%s' with non-constant value!\n", attr.first.c_str()); + ast->input_error("Attribute `%s' with non-constant value!\n", attr.first.c_str()); sw->attributes[attr.first] = attr.second->asAttrConst(); } @@ -682,16 +681,16 @@ struct AST_INTERNAL::ProcessGenerator break; case AST_WIRE: - log_file_error(ast->filename, ast->location.first_line, "Found reg declaration in block without label!\n"); + ast->input_error("Found reg declaration in block without label!\n"); break; case AST_ASSIGN: - log_file_error(ast->filename, ast->location.first_line, "Found continous assignment in always/initial block!\n"); + ast->input_error("Found continous assignment in always/initial block!\n"); break; case AST_PARAMETER: case AST_LOCALPARAM: - log_file_error(ast->filename, ast->location.first_line, "Found parameter declaration in block without label!\n"); + ast->input_error("Found parameter declaration in block without label!\n"); break; case AST_NONE: @@ -840,17 +839,18 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun } } if (!id_ast) - log_file_error(filename, location.first_line, "Failed to resolve identifier %s for width detection!\n", str.c_str()); + input_error("Failed to resolve identifier %s for width detection!\n", str.c_str()); if (id_ast->type == AST_PARAMETER || id_ast->type == AST_LOCALPARAM || id_ast->type == AST_ENUM_ITEM) { if (id_ast->children.size() > 1 && id_ast->children[1]->range_valid) { this_width = id_ast->children[1]->range_left - id_ast->children[1]->range_right + 1; - } else - if (id_ast->children[0]->type != AST_CONSTANT) - while (id_ast->simplify(true, false, false, 1, -1, false, true)) { } - if (id_ast->children[0]->type == AST_CONSTANT) - this_width = id_ast->children[0]->bits.size(); - else - log_file_error(filename, location.first_line, "Failed to detect width for parameter %s!\n", str.c_str()); + } else { + if (id_ast->children[0]->type != AST_CONSTANT) + while (id_ast->simplify(true, false, 1, -1, false, true)) { } + if (id_ast->children[0]->type == AST_CONSTANT) + this_width = id_ast->children[0]->bits.size(); + else + input_error("Failed to detect width for parameter %s!\n", str.c_str()); + } if (children.size() != 0) range = children[0]; } else if (id_ast->type == AST_WIRE || id_ast->type == AST_AUTOWIRE) { @@ -862,7 +862,7 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun // log("---\n"); // id_ast->dumpAst(NULL, "decl> "); // dumpAst(NULL, "ref> "); - log_file_error(filename, location.first_line, "Failed to detect width of signal access `%s'!\n", str.c_str()); + input_error("Failed to detect width of signal access `%s'!\n", str.c_str()); } } else { this_width = id_ast->range_left - id_ast->range_right + 1; @@ -873,7 +873,7 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun this_width = 32; } else if (id_ast->type == AST_MEMORY) { if (!id_ast->children[0]->range_valid) - log_file_error(filename, location.first_line, "Failed to detect width of memory access `%s'!\n", str.c_str()); + input_error("Failed to detect width of memory access `%s'!\n", str.c_str()); this_width = id_ast->children[0]->range_left - id_ast->children[0]->range_right + 1; if (children.size() > 1) range = children[1]; @@ -882,17 +882,17 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun this_width = tmp_range->range_left - tmp_range->range_right + 1; delete tmp_range; } else - log_file_error(filename, location.first_line, "Failed to detect width for identifier %s!\n", str.c_str()); + input_error("Failed to detect width for identifier %s!\n", str.c_str()); if (range) { if (range->children.size() == 1) this_width = 1; else if (!range->range_valid) { - AstNode *left_at_zero_ast = children[0]->children[0]->clone(); - AstNode *right_at_zero_ast = children[0]->children.size() >= 2 ? children[0]->children[1]->clone() : left_at_zero_ast->clone(); - while (left_at_zero_ast->simplify(true, true, false, 1, -1, false, false)) { } - while (right_at_zero_ast->simplify(true, true, false, 1, -1, false, false)) { } + AstNode *left_at_zero_ast = children[0]->children[0]->clone_at_zero(); + AstNode *right_at_zero_ast = children[0]->children.size() >= 2 ? children[0]->children[1]->clone_at_zero() : left_at_zero_ast->clone(); + while (left_at_zero_ast->simplify(true, false, 1, -1, false, false)) { } + while (right_at_zero_ast->simplify(true, false, 1, -1, false, false)) { } if (left_at_zero_ast->type != AST_CONSTANT || right_at_zero_ast->type != AST_CONSTANT) - log_file_error(filename, location.first_line, "Unsupported expression on dynamic range select on signal `%s'!\n", str.c_str()); + input_error("Unsupported expression on dynamic range select on signal `%s'!\n", str.c_str()); this_width = abs(int(left_at_zero_ast->integer - right_at_zero_ast->integer)) + 1; delete left_at_zero_ast; delete right_at_zero_ast; @@ -906,9 +906,9 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun break; case AST_TO_BITS: - while (children[0]->simplify(true, false, false, 1, -1, false, false) == true) { } + while (children[0]->simplify(true, false, 1, -1, false, false) == true) { } if (children[0]->type != AST_CONSTANT) - log_file_error(filename, location.first_line, "Left operand of tobits expression is not constant!\n"); + input_error("Left operand of tobits expression is not constant!\n"); children[1]->detectSignWidthWorker(sub_width_hint, sign_hint); width_hint = max(width_hint, children[0]->bitsAsConst().as_int()); break; @@ -928,14 +928,14 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun break; case AST_CAST_SIZE: - while (children.at(0)->simplify(true, false, false, 1, -1, false, false)) { } + while (children.at(0)->simplify(true, false, 1, -1, false, false)) { } if (children.at(0)->type != AST_CONSTANT) - log_file_error(filename, location.first_line, "Static cast with non constant expression!\n"); + input_error("Static cast with non constant expression!\n"); children.at(1)->detectSignWidthWorker(width_hint, sign_hint); this_width = children.at(0)->bitsAsConst().as_int(); width_hint = max(width_hint, this_width); if (width_hint <= 0) - log_file_error(filename, location.first_line, "Static cast with zero or negative size!\n"); + input_error("Static cast with zero or negative size!\n"); break; case AST_CONCAT: @@ -950,9 +950,9 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun break; case AST_REPLICATE: - while (children[0]->simplify(true, false, false, 1, -1, false, true) == true) { } + while (children[0]->simplify(true, false, 1, -1, false, true) == true) { } if (children[0]->type != AST_CONSTANT) - log_file_error(filename, location.first_line, "Left operand of replicate expression is not constant!\n"); + input_error("Left operand of replicate expression is not constant!\n"); children[1]->detectSignWidthWorker(sub_width_hint, sub_sign_hint); width_hint = max(width_hint, children[0]->bitsAsConst().as_int() * sub_width_hint); sign_hint = false; @@ -1028,7 +1028,7 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun if (!id2ast->is_signed) sign_hint = false; if (!id2ast->children[0]->range_valid) - log_file_error(filename, location.first_line, "Failed to detect width of memory access `%s'!\n", str.c_str()); + input_error("Failed to detect width of memory access `%s'!\n", str.c_str()); this_width = id2ast->children[0]->range_left - id2ast->children[0]->range_right + 1; width_hint = max(width_hint, this_width); break; @@ -1062,7 +1062,7 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun case AST_PREFIX: // Prefix nodes always resolve to identifiers in generate loops, so we // can simply perform the resolution to determine the sign and width. - simplify(true, false, false, 1, -1, false, false); + simplify(true, false, 1, -1, false, false); log_assert(type == AST_IDENTIFIER); detectSignWidthWorker(width_hint, sign_hint, found_real); break; @@ -1070,9 +1070,9 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun case AST_FCALL: if (str == "\\$anyconst" || str == "\\$anyseq" || str == "\\$allconst" || str == "\\$allseq") { if (GetSize(children) == 1) { - while (children[0]->simplify(true, false, false, 1, -1, false, true) == true) { } + while (children[0]->simplify(true, false, 1, -1, false, true) == true) { } if (children[0]->type != AST_CONSTANT) - log_file_error(filename, location.first_line, "System function %s called with non-const argument!\n", + input_error("System function %s called with non-const argument!\n", RTLIL::unescape_id(str).c_str()); width_hint = max(width_hint, int(children[0]->asInt(true))); } @@ -1100,7 +1100,7 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun // item expressions. const AstNode *func = current_scope.at(str); if (func->type != AST_FUNCTION) - log_file_error(filename, location.first_line, "Function call to %s resolved to something that isn't a function!\n", RTLIL::unescape_id(str).c_str()); + input_error("Function call to %s resolved to something that isn't a function!\n", RTLIL::unescape_id(str).c_str()); const AstNode *wire = nullptr; for (const AstNode *child : func->children) if (child->str == func->str) { @@ -1117,10 +1117,10 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun log_assert(range->type == AST_RANGE && range->children.size() == 2); AstNode *left = range->children.at(0)->clone(); AstNode *right = range->children.at(1)->clone(); - while (left->simplify(true, false, false, 1, -1, false, true)) { } - while (right->simplify(true, false, false, 1, -1, false, true)) { } + while (left->simplify(true, false, 1, -1, false, true)) { } + while (right->simplify(true, false, 1, -1, false, true)) { } if (left->type != AST_CONSTANT || right->type != AST_CONSTANT) - log_file_error(filename, location.first_line, "Function %s has non-constant width!", + input_error("Function %s has non-constant width!", RTLIL::unescape_id(str).c_str()); result_width = abs(int(left->asInt(true) - right->asInt(true))); delete left; @@ -1136,7 +1136,7 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun AstNode *current_scope_ast = current_ast_mod == nullptr ? current_ast : current_ast_mod; for (auto f : log_files) current_scope_ast->dumpAst(f, "verilog-ast> "); - log_file_error(filename, location.first_line, "Don't know how to detect sign and width for %s node!\n", type2str(type).c_str()); + input_error("Don't know how to detect sign and width for %s node!\n", type2str(type).c_str()); } if (*found_real) @@ -1154,9 +1154,8 @@ void AstNode::detectSignWidth(int &width_hint, bool &sign_hint, bool *found_real constexpr int kWidthLimit = 1 << 24; if (width_hint >= kWidthLimit) - log_file_error(filename, location.first_line, - "Expression width %d exceeds implementation limit of %d!\n", - width_hint, kWidthLimit); + input_error("Expression width %d exceeds implementation limit of %d!\n", + width_hint, kWidthLimit); } static void check_unique_id(RTLIL::Module *module, RTLIL::IdString id, @@ -1167,9 +1166,8 @@ static void check_unique_id(RTLIL::Module *module, RTLIL::IdString id, std::string location_str = "earlier"; if (!src.empty()) location_str = "at " + src; - log_file_error(node->filename, node->location.first_line, - "Cannot add %s `%s' because a %s with the same name was already created %s!\n", - to_add_kind, id.c_str(), existing_kind, location_str.c_str()); + node->input_error("Cannot add %s `%s' because a %s with the same name was already created %s!\n", + to_add_kind, id.c_str(), existing_kind, location_str.c_str()); }; if (const RTLIL::Wire *wire = module->wire(id)) @@ -1264,7 +1262,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) if (flag_pwires) { if (GetSize(children) < 1 || children[0]->type != AST_CONSTANT) - log_file_error(filename, location.first_line, "Parameter `%s' with non-constant value!\n", str.c_str()); + input_error("Parameter `%s' with non-constant value!\n", str.c_str()); RTLIL::Const val = children[0]->bitsAsConst(); RTLIL::IdString id = str; @@ -1278,7 +1276,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) for (auto &attr : attributes) { if (attr.second->type != AST_CONSTANT) - log_file_error(filename, location.first_line, "Attribute `%s' with non-constant value!\n", attr.first.c_str()); + input_error("Attribute `%s' with non-constant value!\n", attr.first.c_str()); wire->attributes[attr.first] = attr.second->asAttrConst(); } } @@ -1287,10 +1285,10 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) // create an RTLIL::Wire for an AST_WIRE node case AST_WIRE: { if (!range_valid) - log_file_error(filename, location.first_line, "Signal `%s' with non-constant width!\n", str.c_str()); + input_error("Signal `%s' with non-constant width!\n", str.c_str()); if (!(range_left + 1 >= range_right)) - log_file_error(filename, location.first_line, "Signal `%s' with invalid width range %d!\n", str.c_str(), range_left - range_right + 1); + input_error("Signal `%s' with invalid width range %d!\n", str.c_str(), range_left - range_right + 1); RTLIL::IdString id = str; check_unique_id(current_module, id, this, "signal"); @@ -1305,7 +1303,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) for (auto &attr : attributes) { if (attr.second->type != AST_CONSTANT) - log_file_error(filename, location.first_line, "Attribute `%s' with non-constant value!\n", attr.first.c_str()); + input_error("Attribute `%s' with non-constant value!\n", attr.first.c_str()); wire->attributes[attr.first] = attr.second->asAttrConst(); } @@ -1321,7 +1319,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) log_assert(children[1]->type == AST_RANGE); if (!children[0]->range_valid || !children[1]->range_valid) - log_file_error(filename, location.first_line, "Memory `%s' with non-constant width or size!\n", str.c_str()); + input_error("Memory `%s' with non-constant width or size!\n", str.c_str()); RTLIL::Memory *memory = new RTLIL::Memory; set_src_attr(memory, this); @@ -1339,7 +1337,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) for (auto &attr : attributes) { if (attr.second->type != AST_CONSTANT) - log_file_error(filename, location.first_line, "Attribute `%s' with non-constant value!\n", attr.first.c_str()); + input_error("Attribute `%s' with non-constant value!\n", attr.first.c_str()); memory->attributes[attr.first] = attr.second->asAttrConst(); } } @@ -1375,6 +1373,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) RTLIL::SigChunk chunk; bool is_interface = false; + AST::AstNode *member_node = NULL; int add_undef_bits_msb = 0; int add_undef_bits_lsb = 0; @@ -1395,11 +1394,11 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) } else if (flag_autowire) log_file_warning(filename, location.first_line, "Identifier `%s' is implicitly declared.\n", str.c_str()); else - log_file_error(filename, location.first_line, "Identifier `%s' is implicitly declared and `default_nettype is set to none.\n", str.c_str()); + input_error("Identifier `%s' is implicitly declared and `default_nettype is set to none.\n", str.c_str()); } else if (id2ast->type == AST_PARAMETER || id2ast->type == AST_LOCALPARAM || id2ast->type == AST_ENUM_ITEM) { if (id2ast->children[0]->type != AST_CONSTANT) - log_file_error(filename, location.first_line, "Parameter %s does not evaluate to constant value!\n", str.c_str()); + input_error("Parameter %s does not evaluate to constant value!\n", str.c_str()); chunk = RTLIL::Const(id2ast->children[0]->bits); goto use_const_chunk; } @@ -1414,11 +1413,11 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) is_interface = true; } else { - log_file_error(filename, location.first_line, "Identifier `%s' doesn't map to any signal!\n", str.c_str()); + input_error("Identifier `%s' doesn't map to any signal!\n", str.c_str()); } if (id2ast->type == AST_MEMORY) - log_file_error(filename, location.first_line, "Identifier `%s' does map to an unexpanded memory!\n", str.c_str()); + input_error("Identifier `%s' does map to an unexpanded memory!\n", str.c_str()); // If identifier is an interface, create a RTLIL::SigSpec with a dummy wire with a attribute called 'is_interface' // This makes it possible for the hierarchy pass to see what are interface connections and then replace them @@ -1438,31 +1437,49 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) chunk.width = wire->width; chunk.offset = 0; + if ((member_node = get_struct_member(this))) { + // Clamp wire chunk to range of member within struct/union. + chunk.width = member_node->range_left - member_node->range_right + 1; + chunk.offset = member_node->range_right; + } + use_const_chunk: if (children.size() != 0) { if (children[0]->type != AST_RANGE) - log_file_error(filename, location.first_line, "Single range expected.\n"); + input_error("Single range expected.\n"); int source_width = id2ast->range_left - id2ast->range_right + 1; int source_offset = id2ast->range_right; + int chunk_left = source_width - 1; + int chunk_right = 0; + + if (member_node) { + // Clamp wire chunk to range of member within struct/union. + log_assert(!source_offset && !id2ast->range_swapped); + chunk_left = chunk.offset + chunk.width - 1; + chunk_right = chunk.offset; + } + if (!children[0]->range_valid) { - AstNode *left_at_zero_ast = children[0]->children[0]->clone(); - AstNode *right_at_zero_ast = children[0]->children.size() >= 2 ? children[0]->children[1]->clone() : left_at_zero_ast->clone(); - while (left_at_zero_ast->simplify(true, true, false, 1, -1, false, false)) { } - while (right_at_zero_ast->simplify(true, true, false, 1, -1, false, false)) { } + AstNode *left_at_zero_ast = children[0]->children[0]->clone_at_zero(); + AstNode *right_at_zero_ast = children[0]->children.size() >= 2 ? children[0]->children[1]->clone_at_zero() : left_at_zero_ast->clone(); + while (left_at_zero_ast->simplify(true, false, 1, -1, false, false)) { } + while (right_at_zero_ast->simplify(true, false, 1, -1, false, false)) { } if (left_at_zero_ast->type != AST_CONSTANT || right_at_zero_ast->type != AST_CONSTANT) - log_file_error(filename, location.first_line, "Unsupported expression on dynamic range select on signal `%s'!\n", str.c_str()); + input_error("Unsupported expression on dynamic range select on signal `%s'!\n", str.c_str()); int width = abs(int(left_at_zero_ast->integer - right_at_zero_ast->integer)) + 1; AstNode *fake_ast = new AstNode(AST_NONE, clone(), children[0]->children.size() >= 2 ? children[0]->children[1]->clone() : children[0]->children[0]->clone()); fake_ast->children[0]->delete_children(); + if (member_node) + fake_ast->children[0]->attributes[ID::wiretype] = member_node->clone(); int fake_ast_width = 0; bool fake_ast_sign = true; fake_ast->children[1]->detectSignWidth(fake_ast_width, fake_ast_sign); RTLIL::SigSpec shift_val = fake_ast->children[1]->genRTLIL(fake_ast_width, fake_ast_sign); - if (id2ast->range_right != 0) { - shift_val = current_module->Sub(NEW_ID, shift_val, id2ast->range_right, fake_ast_sign); + if (source_offset != 0) { + shift_val = current_module->Sub(NEW_ID, shift_val, source_offset, fake_ast_sign); fake_ast->children[1]->is_signed = true; } if (id2ast->range_swapped) { @@ -1478,10 +1495,10 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) return sig; } else { chunk.width = children[0]->range_left - children[0]->range_right + 1; - chunk.offset = children[0]->range_right - source_offset; + chunk.offset += children[0]->range_right - source_offset; if (id2ast->range_swapped) - chunk.offset = (id2ast->range_left - id2ast->range_right + 1) - (chunk.offset + chunk.width); - if (chunk.offset >= source_width || chunk.offset + chunk.width < 0) { + chunk.offset = source_width - (chunk.offset + chunk.width); + if (chunk.offset > chunk_left || chunk.offset + chunk.width < chunk_right) { if (chunk.width == 1) log_file_warning(filename, location.first_line, "Range select out of bounds on signal `%s': Setting result bit to undef.\n", str.c_str()); @@ -1490,12 +1507,12 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) children[0]->range_left, children[0]->range_right, str.c_str(), chunk.width); chunk = RTLIL::SigChunk(RTLIL::State::Sx, chunk.width); } else { - if (chunk.width + chunk.offset > source_width) { - add_undef_bits_msb = (chunk.width + chunk.offset) - source_width; + if (chunk.offset + chunk.width - 1 > chunk_left) { + add_undef_bits_msb = (chunk.offset + chunk.width - 1) - chunk_left; chunk.width -= add_undef_bits_msb; } - if (chunk.offset < 0) { - add_undef_bits_lsb = -chunk.offset; + if (chunk.offset < chunk_right) { + add_undef_bits_lsb = chunk_right - chunk.offset; chunk.width -= add_undef_bits_lsb; chunk.offset += add_undef_bits_lsb; } @@ -1533,10 +1550,10 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) case AST_CAST_SIZE: { RTLIL::SigSpec size = children[0]->genRTLIL(); if (!size.is_fully_const()) - log_file_error(filename, location.first_line, "Static cast with non constant expression!\n"); + input_error("Static cast with non constant expression!\n"); int width = size.as_int(); if (width <= 0) - log_file_error(filename, location.first_line, "Static cast with zero or negative size!\n"); + input_error("Static cast with zero or negative size!\n"); // determine the *signedness* of the expression int sub_width_hint = -1; bool sub_sign_hint = true; @@ -1565,7 +1582,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) RTLIL::SigSpec left = children[0]->genRTLIL(); RTLIL::SigSpec right = children[1]->genRTLIL(); if (!left.is_fully_const()) - log_file_error(filename, location.first_line, "Left operand of replicate expression is not constant!\n"); + input_error("Left operand of replicate expression is not constant!\n"); int count = left.as_int(); RTLIL::SigSpec sig; for (int i = 0; i < count; i++) @@ -1825,7 +1842,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) id2ast->meminfo(mem_width, mem_size, addr_bits); if (children[3]->type != AST_CONSTANT) - log_file_error(filename, location.first_line, "Memory init with non-constant word count!\n"); + input_error("Memory init with non-constant word count!\n"); int num_words = int(children[3]->asInt(false)); cell->parameters[ID::WORDS] = RTLIL::Const(num_words); @@ -1879,7 +1896,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) for (auto &attr : attributes) { if (attr.second->type != AST_CONSTANT) - log_file_error(filename, location.first_line, "Attribute `%s' with non-constant value!\n", attr.first.c_str()); + input_error("Attribute `%s' with non-constant value!\n", attr.first.c_str()); cell->attributes[attr.first] = attr.second->asAttrConst(); } @@ -1938,7 +1955,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) log_file_warning(filename, location.first_line, "Replacing floating point parameter %s.%s = %f with string.\n", log_id(cell), log_id(paraname), value->realvalue); else if (value->type != AST_CONSTANT) - log_file_error(filename, location.first_line, "Parameter %s.%s with non-constant value!\n", + input_error("Parameter %s.%s with non-constant value!\n", log_id(cell), log_id(paraname)); cell->parameters[paraname] = value->asParaConst(); continue; @@ -1986,7 +2003,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) } for (auto &attr : attributes) { if (attr.second->type != AST_CONSTANT) - log_file_error(filename, location.first_line, "Attribute `%s' with non-constant value.\n", attr.first.c_str()); + input_error("Attribute `%s' with non-constant value.\n", attr.first.c_str()); cell->attributes[attr.first] = attr.second->asAttrConst(); } if (cell->type == ID($specify2)) { @@ -1994,7 +2011,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) int dst_width = GetSize(cell->getPort(ID::DST)); bool full = cell->getParam(ID::FULL).as_bool(); if (!full && src_width != dst_width) - log_file_error(filename, location.first_line, "Parallel specify SRC width does not match DST width.\n"); + input_error("Parallel specify SRC width does not match DST width.\n"); cell->setParam(ID::SRC_WIDTH, Const(src_width)); cell->setParam(ID::DST_WIDTH, Const(dst_width)); } @@ -2002,7 +2019,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) int dat_width = GetSize(cell->getPort(ID::DAT)); int dst_width = GetSize(cell->getPort(ID::DST)); if (dat_width != dst_width) - log_file_error(filename, location.first_line, "Specify DAT width does not match DST width.\n"); + input_error("Specify DAT width does not match DST width.\n"); int src_width = GetSize(cell->getPort(ID::SRC)); cell->setParam(ID::SRC_WIDTH, Const(src_width)); cell->setParam(ID::DST_WIDTH, Const(dst_width)); @@ -2044,20 +2061,20 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) log_file_warning(filename, location.first_line, "\n"); } else if (str == "$error") { if (sz > 0) - log_file_error(filename, location.first_line, "%s.\n", children[0]->str.c_str()); + input_error("%s.\n", children[0]->str.c_str()); else - log_file_error(filename, location.first_line, "\n"); + input_error("\n"); } else if (str == "$fatal") { // TODO: 1st parameter, if exists, is 0,1 or 2, and passed to $finish() // if no parameter is given, default value is 1 // dollar_finish(sz ? children[0] : 1); // perhaps create & use log_file_fatal() if (sz > 0) - log_file_error(filename, location.first_line, "FATAL: %s.\n", children[0]->str.c_str()); + input_error("FATAL: %s.\n", children[0]->str.c_str()); else - log_file_error(filename, location.first_line, "FATAL.\n"); + input_error("FATAL.\n"); } else { - log_file_error(filename, location.first_line, "Unknown elabortoon system task '%s'.\n", str.c_str()); + input_error("Unknown elabortoon system task '%s'.\n", str.c_str()); } } break; @@ -2075,18 +2092,18 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) int width = width_hint; if (GetSize(children) > 1) - log_file_error(filename, location.first_line, "System function %s got %d arguments, expected 1 or 0.\n", + input_error("System function %s got %d arguments, expected 1 or 0.\n", RTLIL::unescape_id(str).c_str(), GetSize(children)); if (GetSize(children) == 1) { if (children[0]->type != AST_CONSTANT) - log_file_error(filename, location.first_line, "System function %s called with non-const argument!\n", + input_error("System function %s called with non-const argument!\n", RTLIL::unescape_id(str).c_str()); width = children[0]->asInt(true); } if (width <= 0) - log_file_error(filename, location.first_line, "Failed to detect width of %s!\n", RTLIL::unescape_id(str).c_str()); + input_error("Failed to detect width of %s!\n", RTLIL::unescape_id(str).c_str()); Cell *cell = current_module->addCell(myid, str.substr(1)); set_src_attr(cell, this); @@ -2095,7 +2112,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) if (attributes.count(ID::reg)) { auto &attr = attributes.at(ID::reg); if (attr->type != AST_CONSTANT) - log_file_error(filename, location.first_line, "Attribute `reg' with non-constant value!\n"); + input_error("Attribute `reg' with non-constant value!\n"); cell->attributes[ID::reg] = attr->asAttrConst(); } @@ -2113,7 +2130,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) default: for (auto f : log_files) current_ast_mod->dumpAst(f, "verilog-ast> "); - log_file_error(filename, location.first_line, "Don't know how to generate RTLIL code for %s node!\n", type2str(type).c_str()); + input_error("Don't know how to generate RTLIL code for %s node!\n", type2str(type).c_str()); } return RTLIL::SigSpec(); diff --git a/yosys/frontends/ast/simplify.cc b/yosys/frontends/ast/simplify.cc index 2dbabca2851..64191cd7ebf 100644 --- a/yosys/frontends/ast/simplify.cc +++ b/yosys/frontends/ast/simplify.cc @@ -53,7 +53,7 @@ std::string AstNode::process_format_str(const std::string &sformat, int next_arg { // If there's no next character, that's a problem if (i+1 >= sformat.length()) - log_file_error(filename, location.first_line, "System task `%s' called with `%%' at end of string.\n", str.c_str()); + input_error("System task `%s' called with `%%' at end of string.\n", str.c_str()); char cformat = sformat[++i]; @@ -95,13 +95,13 @@ std::string AstNode::process_format_str(const std::string &sformat, int next_arg case 'x': case 'X': if (next_arg >= GetSize(children)) - log_file_error(filename, location.first_line, "Missing argument for %%%c format specifier in system task `%s'.\n", + input_error("Missing argument for %%%c format specifier in system task `%s'.\n", cformat, str.c_str()); node_arg = children[next_arg++]; - while (node_arg->simplify(true, false, false, stage, width_hint, sign_hint, false)) { } + while (node_arg->simplify(true, false, stage, width_hint, sign_hint, false)) { } if (node_arg->type != AST_CONSTANT) - log_file_error(filename, location.first_line, "Failed to evaluate system task `%s' with non-constant argument.\n", str.c_str()); + input_error("Failed to evaluate system task `%s' with non-constant argument.\n", str.c_str()); break; case 'm': @@ -118,7 +118,7 @@ std::string AstNode::process_format_str(const std::string &sformat, int next_arg default: unsupported_format: - log_file_error(filename, location.first_line, "System task `%s' called with invalid/unsupported format specifier.\n", str.c_str()); + input_error("System task `%s' called with invalid/unsupported format specifier.\n", str.c_str()); break; } @@ -192,7 +192,7 @@ void AstNode::annotateTypedEnums(AstNode *template_node) log_assert(current_scope.count(enum_type) == 1); AstNode *enum_node = current_scope.at(enum_type); log_assert(enum_node->type == AST_ENUM); - while (enum_node->simplify(true, false, false, 1, -1, false, true)) { } + while (enum_node->simplify(true, false, 1, -1, false, true)) { } //get width from 1st enum item: log_assert(enum_node->children.size() >= 1); AstNode *enum_item0 = enum_node->children[0]; @@ -266,7 +266,7 @@ static int range_width(AstNode *node, AstNode *rnode) { log_assert(rnode->type==AST_RANGE); if (!rnode->range_valid) { - log_file_error(node->filename, node->location.first_line, "Size must be constant in packed struct/union member %s\n", node->str.c_str()); + node->input_error("Size must be constant in packed struct/union member %s\n", node->str.c_str()); } // note: range swapping has already been checked for @@ -275,20 +275,24 @@ static int range_width(AstNode *node, AstNode *rnode) [[noreturn]] static void struct_array_packing_error(AstNode *node) { - log_file_error(node->filename, node->location.first_line, "Unpacked array in packed struct/union member %s\n", node->str.c_str()); + node->input_error("Unpacked array in packed struct/union member %s\n", node->str.c_str()); } -static void save_struct_array_width(AstNode *node, int width) +static void save_struct_range_dimensions(AstNode *node, AstNode *rnode) { - // stash the stride for the array - node->multirange_dimensions.push_back(width); - + node->multirange_dimensions.push_back(rnode->range_right); + node->multirange_dimensions.push_back(range_width(node, rnode)); + node->multirange_swapped.push_back(rnode->range_swapped); } -static void save_struct_range_swapped(AstNode *node, bool range_swapped) +static int get_struct_range_offset(AstNode *node, int dimension) { - node->multirange_swapped.push_back(range_swapped); + return node->multirange_dimensions[2*dimension]; +} +static int get_struct_range_width(AstNode *node, int dimension) +{ + return node->multirange_dimensions[2*dimension + 1]; } static int size_packed_struct(AstNode *snode, int base_offset) @@ -322,14 +326,17 @@ static int size_packed_struct(AstNode *snode, int base_offset) if (node->children[1]->type == AST_RANGE) { // Unpacked array, e.g. bit [63:0] a [0:3] auto rnode = node->children[1]; - // C-style array size, e.g. bit [63:0] a [4] - bool c_type = rnode->children.size() == 1; - int array_count = c_type ? rnode->range_left : range_width(node, rnode); - save_struct_array_width(node, array_count); - save_struct_range_swapped(node, rnode->range_swapped || c_type); - save_struct_array_width(node, width); - save_struct_range_swapped(node, node->children[0]->range_swapped); - width *= array_count; + if (rnode->children.size() == 1) { + // C-style array size, e.g. bit [63:0] a [4] + node->multirange_dimensions.push_back(0); + node->multirange_dimensions.push_back(rnode->range_left); + node->multirange_swapped.push_back(true); + width *= rnode->range_left; + } else { + save_struct_range_dimensions(node, rnode); + width *= range_width(node, rnode); + } + save_struct_range_dimensions(node, node->children[0]); } else { // The Yosys extension for unpacked arrays in packed structs / unions @@ -338,8 +345,7 @@ static int size_packed_struct(AstNode *snode, int base_offset) } } else { // Vector - save_struct_array_width(node, width); - save_struct_range_swapped(node, node->children[0]->range_swapped); + save_struct_range_dimensions(node, node->children[0]); } // range nodes are now redundant for (AstNode *child : node->children) @@ -355,10 +361,8 @@ static int size_packed_struct(AstNode *snode, int base_offset) } width = 1; for (auto rnode : node->children[0]->children) { - int rwidth = range_width(node, rnode); - save_struct_array_width(node, rwidth); - save_struct_range_swapped(node, rnode->range_swapped); - width *= rwidth; + save_struct_range_dimensions(node, rnode); + width *= range_width(node, rnode); } // range nodes are now redundant for (AstNode *child : node->children) @@ -390,10 +394,8 @@ static int size_packed_struct(AstNode *snode, int base_offset) packed_width = width; } else { - if (packed_width != width) { - - log_file_error(node->filename, node->location.first_line, "member %s of a packed union has %d bits, expecting %d\n", node->str.c_str(), width, packed_width); - } + if (packed_width != width) + node->input_error("member %s of a packed union has %d bits, expecting %d\n", node->str.c_str(), width, packed_width); } } else { @@ -405,7 +407,7 @@ static int size_packed_struct(AstNode *snode, int base_offset) [[noreturn]] static void struct_op_error(AstNode *node) { - log_file_error(node->filename, node->location.first_line, "Unsupported operation for struct/union member %s\n", node->str.c_str()+1); + node->input_error("Unsupported operation for struct/union member %s\n", node->str.c_str()+1); } static AstNode *node_int(int ival) @@ -422,9 +424,14 @@ static AstNode *normalize_struct_index(AstNode *expr, AstNode *member_node, int { expr = expr->clone(); + int offset = get_struct_range_offset(member_node, dimension); + if (offset) { + expr = new AstNode(AST_SUB, expr, node_int(offset)); + } + if (member_node->multirange_swapped[dimension]) { // The dimension has swapped range; swap index into the struct accordingly. - int msb = member_node->multirange_dimensions[dimension] - 1; + int msb = get_struct_range_width(member_node, dimension) - 1; expr = new AstNode(AST_SUB, node_int(msb), expr); } @@ -433,10 +440,10 @@ static AstNode *normalize_struct_index(AstNode *expr, AstNode *member_node, int static AstNode *struct_index_lsb_offset(AstNode *lsb_offset, AstNode *rnode, AstNode *member_node, int dimension, int &stride) { - stride /= member_node->multirange_dimensions[dimension]; + stride /= get_struct_range_width(member_node, dimension); auto right = normalize_struct_index(rnode->children.back(), member_node, dimension); auto offset = stride > 1 ? multiply_by_const(right, stride) : right; - return new AstNode(AST_ADD, lsb_offset, offset); + return lsb_offset ? new AstNode(AST_ADD, lsb_offset, offset) : offset; } static AstNode *struct_index_msb_offset(AstNode *lsb_offset, AstNode *rnode, AstNode *member_node, int dimension, int stride) @@ -475,7 +482,7 @@ AstNode *AST::make_struct_member_range(AstNode *node, AstNode *member_node) int range_right = member_node->range_right; if (node->children.empty()) { // no range operations apply, return the whole width - return make_range(range_left, range_right); + return make_range(range_left - range_right, 0); } if (node->children.size() != 1) { @@ -484,7 +491,7 @@ AstNode *AST::make_struct_member_range(AstNode *node, AstNode *member_node) // Range operations auto rnode = node->children[0]; - auto lsb_offset = node_int(member_node->range_right); + AstNode *lsb_offset = NULL; int stride = range_left - range_right + 1; size_t i = 0; @@ -511,6 +518,17 @@ AstNode *AST::make_struct_member_range(AstNode *node, AstNode *member_node) return new AstNode(AST_RANGE, msb_offset, lsb_offset); } +AstNode *AST::get_struct_member(const AstNode *node) +{ + AST::AstNode *member_node; + if (node->attributes.count(ID::wiretype) && (member_node = node->attributes.at(ID::wiretype)) && + (member_node->type == AST_STRUCT_ITEM || member_node->type == AST_STRUCT || member_node->type == AST_UNION)) + { + return member_node; + } + return NULL; +} + static void add_members_to_scope(AstNode *snode, std::string name) { // add all the members in a struct or union to local scope @@ -537,7 +555,7 @@ static int get_max_offset(AstNode *node) return node->range_left; } -static AstNode *make_packed_struct(AstNode *template_node, std::string &name) +static AstNode *make_packed_struct(AstNode *template_node, std::string &name, decltype(AstNode::attributes) &attributes) { // create a wire for the packed struct auto wnode = new AstNode(AST_WIRE); @@ -545,6 +563,9 @@ static AstNode *make_packed_struct(AstNode *template_node, std::string &name) wnode->is_logic = true; wnode->range_valid = true; wnode->is_signed = template_node->is_signed; + for (auto &pair : attributes) { + wnode->attributes[pair.first] = pair.second->clone(); + } int offset = get_max_offset(template_node); auto range = make_range(offset, 0); wnode->children.push_back(range); @@ -752,6 +773,71 @@ static IdentUsage always_asgn_before_use(const AstNode *node, const std::string return IdentUsage::NotReferenced; } +AstNode *AstNode::clone_at_zero() +{ + int width_hint; + bool sign_hint; + AstNode *pointee; + + switch (type) { + case AST_IDENTIFIER: + if (id2ast) + pointee = id2ast; + else if (current_scope.count(str)) + pointee = current_scope[str]; + else + break; + + if (pointee->type != AST_WIRE && + pointee->type != AST_AUTOWIRE && + pointee->type != AST_MEMORY) + break; + + YS_FALLTHROUGH; + case AST_MEMRD: + detectSignWidth(width_hint, sign_hint); + return mkconst_int(0, sign_hint, width_hint); + + default: + break; + } + + AstNode *that = new AstNode; + *that = *this; + for (auto &it : that->children) + it = it->clone_at_zero(); + for (auto &it : that->attributes) + it.second = it.second->clone(); + return that; +} + +static bool try_determine_range_width(AstNode *range, int &result_width) +{ + log_assert(range->type == AST_RANGE); + + if (range->children.size() == 1) { + result_width = 1; + return true; + } + + AstNode *left_at_zero_ast = range->children[0]->clone_at_zero(); + AstNode *right_at_zero_ast = range->children[1]->clone_at_zero(); + + while (left_at_zero_ast->simplify(true, false, 1, -1, false, false)) {} + while (right_at_zero_ast->simplify(true, false, 1, -1, false, false)) {} + + bool ok = false; + if (left_at_zero_ast->type == AST_CONSTANT + && right_at_zero_ast->type == AST_CONSTANT) { + ok = true; + result_width = abs(int(left_at_zero_ast->integer - right_at_zero_ast->integer)) + 1; + } + + delete left_at_zero_ast; + delete right_at_zero_ast; + return ok; +} + static const std::string auto_nosync_prefix = "\\AutoNosync"; // mark a local variable in an always_comb block for automatic nosync @@ -823,7 +909,7 @@ static void check_auto_nosync(AstNode *node) // // this function also does all name resolving and sets the id2ast member of all // nodes that link to a different node using names and lexical scoping. -bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, int width_hint, bool sign_hint, bool in_param) +bool AstNode::simplify(bool const_fold, bool in_lvalue, int stage, int width_hint, bool sign_hint, bool in_param) { static int recursion_counter = 0; static bool deep_recursion_warning = false; @@ -841,8 +927,8 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, #if 0 log("-------------\n"); log("AST simplify[%d] depth %d at %s:%d on %s %p:\n", stage, recursion_counter, filename.c_str(), location.first_line, type2str(type).c_str(), this); - log("const_fold=%d, at_zero=%d, in_lvalue=%d, stage=%d, width_hint=%d, sign_hint=%d, in_param=%d\n", - int(const_fold), int(at_zero), int(in_lvalue), int(stage), int(width_hint), int(sign_hint), int(in_param)); + log("const_fold=%d, in_lvalue=%d, stage=%d, width_hint=%d, sign_hint=%d, in_param=%d\n", + int(const_fold), int(in_lvalue), int(stage), int(width_hint), int(sign_hint), int(in_param)); // dumpAst(NULL, "> "); #endif @@ -851,7 +937,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, log_assert(type == AST_MODULE || type == AST_INTERFACE); deep_recursion_warning = true; - while (simplify(const_fold, at_zero, in_lvalue, 1, width_hint, sign_hint, in_param)) { } + while (simplify(const_fold, in_lvalue, 1, width_hint, sign_hint, in_param)) { } if (!flag_nomem2reg && !get_bool_attribute(ID::nomem2reg)) { @@ -934,7 +1020,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, reg->filename = node->filename; reg->location = node->location; children.push_back(reg); - while (reg->simplify(true, false, false, 1, -1, false, false)) { } + while (reg->simplify(true, false, 1, -1, false, false)) { } } } @@ -948,7 +1034,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, delete node; } - while (simplify(const_fold, at_zero, in_lvalue, 2, width_hint, sign_hint, in_param)) { } + while (simplify(const_fold, in_lvalue, 2, width_hint, sign_hint, in_param)) { } recursion_counter--; return false; } @@ -984,14 +1070,14 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, { int nargs = GetSize(children); if (nargs < 1) - log_file_error(filename, location.first_line, "System task `%s' got %d arguments, expected >= 1.\n", + input_error("System task `%s' got %d arguments, expected >= 1.\n", str.c_str(), int(children.size())); // First argument is the format string AstNode *node_string = children[0]; - while (node_string->simplify(true, false, false, stage, width_hint, sign_hint, false)) { } + while (node_string->simplify(true, false, stage, width_hint, sign_hint, false)) { } if (node_string->type != AST_CONSTANT) - log_file_error(filename, location.first_line, "Failed to evaluate system task `%s' with non-constant 1st argument.\n", str.c_str()); + input_error("Failed to evaluate system task `%s' with non-constant 1st argument.\n", str.c_str()); std::string sformat = node_string->bitsAsConst().decode_string(); std::string sout = process_format_str(sformat, 1, stage, width_hint, sign_hint); // Finally, print the message (only include a \n for $display, not for $write) @@ -1016,7 +1102,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, // create name resolution entries for all objects with names // also merge multiple declarations for the same wire (e.g. "output foobar; reg foobar;") - if (type == AST_MODULE) { + if (type == AST_MODULE || type == AST_INTERFACE) { current_scope.clear(); std::set existing; int counter = 0; @@ -1088,7 +1174,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, continue; wires_are_incompatible: if (stage > 1) - log_file_error(filename, location.first_line, "Incompatible re-declaration of wire %s.\n", node->str.c_str()); + input_error("Incompatible re-declaration of wire %s.\n", node->str.c_str()); continue; } this_wire_scope[node->str] = node; @@ -1107,19 +1193,19 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, if (current_scope.count(enode->str) == 0) current_scope[enode->str] = enode; else - log_file_error(filename, location.first_line, "enum item %s already exists\n", enode->str.c_str()); + input_error("enum item %s already exists\n", enode->str.c_str()); } } } for (size_t i = 0; i < children.size(); i++) { AstNode *node = children[i]; if (node->type == AST_PARAMETER || node->type == AST_LOCALPARAM || node->type == AST_WIRE || node->type == AST_AUTOWIRE || node->type == AST_MEMORY || node->type == AST_TYPEDEF) - while (node->simplify(true, false, false, 1, -1, false, node->type == AST_PARAMETER || node->type == AST_LOCALPARAM)) + while (node->simplify(true, false, 1, -1, false, node->type == AST_PARAMETER || node->type == AST_LOCALPARAM)) did_something = true; if (node->type == AST_ENUM) { for (auto enode : node->children){ log_assert(enode->type==AST_ENUM_ITEM); - while (node->simplify(true, false, false, 1, -1, false, in_param)) + while (node->simplify(true, false, 1, -1, false, in_param)) did_something = true; } } @@ -1147,7 +1233,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, if (current_scope.count(enode->str) == 0) current_scope[enode->str] = enode; else - log_file_error(filename, location.first_line, "enum item %s already exists in package\n", enode->str.c_str()); + input_error("enum item %s already exists in package\n", enode->str.c_str()); } } } @@ -1163,7 +1249,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, if (type == AST_ALWAYS || type == AST_INITIAL) { if (current_always != nullptr) - log_file_error(filename, location.first_line, "Invalid nesting of always blocks and/or initializations.\n"); + input_error("Invalid nesting of always blocks and/or initializations.\n"); current_always = this; current_always_clocked = false; @@ -1184,7 +1270,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, for (AstNode *child : children) { // simplify any parameters to constants if (child->type == AST_PARASET) - while (child->simplify(true, false, false, 1, -1, false, true)) { } + while (child->simplify(true, false, 1, -1, false, true)) { } // look for patterns which _may_ indicate ambiguity requiring // resolution of the underlying module @@ -1229,16 +1315,14 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, port_name = child->str; else { if (port_counter >= module->ports.size()) - log_file_error(filename, location.first_line, - "Cell instance has more ports than the module!\n"); + input_error("Cell instance has more ports than the module!\n"); port_name = module->ports[port_counter++]; } // find the port's wire in the underlying module const RTLIL::Wire *ref = module->wire(port_name); if (ref == nullptr) - log_file_error(filename, location.first_line, - "Cell instance refers to port %s which does not exist in module %s!.\n", + input_error("Cell instance refers to port %s which does not exist in module %s!.\n", log_id(port_name), log_id(module->name)); // select the argument, if present @@ -1300,9 +1384,9 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, case AST_ASSIGN_EQ: case AST_ASSIGN_LE: case AST_ASSIGN: - while (!children[0]->basic_prep && children[0]->simplify(false, false, true, stage, -1, false, in_param) == true) + while (!children[0]->basic_prep && children[0]->simplify(false, true, stage, -1, false, in_param) == true) did_something = true; - while (!children[1]->basic_prep && children[1]->simplify(false, false, false, stage, -1, false, in_param) == true) + while (!children[1]->basic_prep && children[1]->simplify(false, false, stage, -1, false, in_param) == true) did_something = true; children[0]->detectSignWidth(backup_width_hint, backup_sign_hint); children[1]->detectSignWidth(width_hint, sign_hint); @@ -1338,7 +1422,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, if (!basic_prep) { for (auto *node : children) { // resolve any ranges - while (!node->basic_prep && node->simplify(true, false, false, stage, -1, false, false)) { + while (!node->basic_prep && node->simplify(true, false, stage, -1, false, false)) { did_something = true; } } @@ -1348,7 +1432,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, // instance rather than just a type in a typedef or outer struct? if (!str.empty() && str[0] == '\\') { // instance so add a wire for the packed structure - auto wnode = make_packed_struct(this, str); + auto wnode = make_packed_struct(this, str, attributes); log_assert(current_ast_mod); current_ast_mod->children.push_back(wnode); } @@ -1357,13 +1441,67 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, break; case AST_STRUCT_ITEM: + if (is_custom_type) { + log_assert(children.size() == 1); + log_assert(children[0]->type == AST_WIRETYPE); + auto type_name = children[0]->str; + if (!current_scope.count(type_name)) { + log_file_error(filename, location.first_line, "Unknown identifier `%s' used as type name\n", type_name.c_str()); + } + AstNode *resolved_type_node = current_scope.at(type_name); + if (resolved_type_node->type != AST_TYPEDEF) + log_file_error(filename, location.first_line, "`%s' does not name a type\n", type_name.c_str()); + log_assert(resolved_type_node->children.size() == 1); + AstNode *template_node = resolved_type_node->children[0]; + + // Ensure typedef itself is fully simplified + while (template_node->simplify(const_fold, in_lvalue, stage, width_hint, sign_hint, in_param)) {}; + + // Remove type reference + delete children[0]; + children.pop_back(); + + switch (template_node->type) { + case AST_WIRE: + type = AST_STRUCT_ITEM; + break; + case AST_STRUCT: + case AST_UNION: + type = template_node->type; + break; + default: + log_file_error(filename, location.first_line, "Invalid type for struct member: %s", type2str(template_node->type).c_str()); + } + + is_reg = template_node->is_reg; + is_logic = template_node->is_logic; + is_signed = template_node->is_signed; + is_string = template_node->is_string; + is_custom_type = template_node->is_custom_type; + + range_valid = template_node->range_valid; + range_swapped = template_node->range_swapped; + range_left = template_node->range_left; + range_right = template_node->range_right; + + attributes[ID::wiretype] = mkconst_str(resolved_type_node->str); + + // Copy clones of children from template + for (auto template_child : template_node->children) { + children.push_back(template_child->clone()); + } + + did_something = true; + + } + log_assert(!is_custom_type); break; case AST_ENUM: //log("\nENUM %s: %d child %d\n", str.c_str(), basic_prep, children[0]->basic_prep); if (!basic_prep) { for (auto item_node : children) { - while (!item_node->basic_prep && item_node->simplify(false, false, false, stage, -1, false, in_param)) + while (!item_node->basic_prep && item_node->simplify(false, false, stage, -1, false, in_param)) did_something = true; } // allocate values (called more than once) @@ -1383,26 +1521,26 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, add_members_to_scope(attributes[ID::wiretype], str); } } - while (!children[0]->basic_prep && children[0]->simplify(false, false, false, stage, -1, false, true) == true) + while (!children[0]->basic_prep && children[0]->simplify(false, false, stage, -1, false, true) == true) did_something = true; children[0]->detectSignWidth(width_hint, sign_hint); if (children.size() > 1 && children[1]->type == AST_RANGE) { - while (!children[1]->basic_prep && children[1]->simplify(false, false, false, stage, -1, false, true) == true) + while (!children[1]->basic_prep && children[1]->simplify(false, false, stage, -1, false, true) == true) did_something = true; if (!children[1]->range_valid) - log_file_error(filename, location.first_line, "Non-constant width range on parameter decl.\n"); + input_error("Non-constant width range on parameter decl.\n"); width_hint = max(width_hint, children[1]->range_left - children[1]->range_right + 1); } break; case AST_ENUM_ITEM: - while (!children[0]->basic_prep && children[0]->simplify(false, false, false, stage, -1, false, in_param)) + while (!children[0]->basic_prep && children[0]->simplify(false, false, stage, -1, false, in_param)) did_something = true; children[0]->detectSignWidth(width_hint, sign_hint); if (children.size() > 1 && children[1]->type == AST_RANGE) { - while (!children[1]->basic_prep && children[1]->simplify(false, false, false, stage, -1, false, in_param)) + while (!children[1]->basic_prep && children[1]->simplify(false, false, stage, -1, false, in_param)) did_something = true; if (!children[1]->range_valid) - log_file_error(filename, location.first_line, "Non-constant width range on enum item decl.\n"); + input_error("Non-constant width range on enum item decl.\n"); width_hint = max(width_hint, children[1]->range_left - children[1]->range_right + 1); } break; @@ -1458,7 +1596,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, width_hint = -1; sign_hint = true; for (auto child : children) { - while (!child->basic_prep && child->simplify(false, false, in_lvalue, stage, -1, false, in_param) == true) + while (!child->basic_prep && child->simplify(false, in_lvalue, stage, -1, false, in_param) == true) did_something = true; child->detectSignWidthWorker(width_hint, sign_hint); } @@ -1493,10 +1631,10 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, if (detect_width_simple && width_hint < 0) { if (type == AST_REPLICATE) - while (children[0]->simplify(true, false, in_lvalue, stage, -1, false, true) == true) + while (children[0]->simplify(true, in_lvalue, stage, -1, false, true) == true) did_something = true; for (auto child : children) - while (!child->basic_prep && child->simplify(false, false, in_lvalue, stage, -1, false, in_param) == true) + while (!child->basic_prep && child->simplify(false, in_lvalue, stage, -1, false, in_param) == true) did_something = true; detectSignWidth(width_hint, sign_hint); } @@ -1506,18 +1644,18 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, if (type == AST_TERNARY) { if (width_hint < 0) { - while (!children[0]->basic_prep && children[0]->simplify(true, false, in_lvalue, stage, -1, false, in_param)) + while (!children[0]->basic_prep && children[0]->simplify(true, in_lvalue, stage, -1, false, in_param)) did_something = true; bool backup_unevaluated_tern_branch = unevaluated_tern_branch; AstNode *chosen = get_tern_choice().first; unevaluated_tern_branch = backup_unevaluated_tern_branch || chosen == children[2]; - while (!children[1]->basic_prep && children[1]->simplify(false, false, in_lvalue, stage, -1, false, in_param)) + while (!children[1]->basic_prep && children[1]->simplify(false, in_lvalue, stage, -1, false, in_param)) did_something = true; unevaluated_tern_branch = backup_unevaluated_tern_branch || chosen == children[1]; - while (!children[2]->basic_prep && children[2]->simplify(false, false, in_lvalue, stage, -1, false, in_param)) + while (!children[2]->basic_prep && children[2]->simplify(false, in_lvalue, stage, -1, false, in_param)) did_something = true; unevaluated_tern_branch = backup_unevaluated_tern_branch; @@ -1549,7 +1687,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, if (const_fold && type == AST_CASE) { detectSignWidth(width_hint, sign_hint); - while (children[0]->simplify(const_fold, at_zero, in_lvalue, stage, width_hint, sign_hint, in_param)) { } + while (children[0]->simplify(const_fold, in_lvalue, stage, width_hint, sign_hint, in_param)) { } if (children[0]->type == AST_CONSTANT && children[0]->bits_only_01()) { children[0]->is_signed = sign_hint; RTLIL::Const case_expr = children[0]->bitsAsConst(width_hint, sign_hint); @@ -1563,7 +1701,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, goto keep_const_cond; if (v->type == AST_BLOCK) continue; - while (v->simplify(const_fold, at_zero, in_lvalue, stage, width_hint, sign_hint, in_param)) { } + while (v->simplify(const_fold, in_lvalue, stage, width_hint, sign_hint, in_param)) { } if (v->type == AST_CONSTANT && v->bits_only_01()) { RTLIL::Const case_item_expr = v->bitsAsConst(width_hint, sign_hint); RTLIL::Const match = const_eq(case_expr, case_item_expr, sign_hint, sign_hint, 1); @@ -1648,7 +1786,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, width_hint_here = -1, sign_hint_here = false; if (children_are_self_determined) width_hint_here = -1, sign_hint_here = false; - did_something_here = children[i]->simplify(const_fold_here, at_zero, in_lvalue_here, stage, width_hint_here, sign_hint_here, in_param_here); + did_something_here = children[i]->simplify(const_fold_here, in_lvalue_here, stage, width_hint_here, sign_hint_here, in_param_here); if (did_something_here) did_something = true; } @@ -1668,7 +1806,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, } } for (auto &attr : attributes) { - while (attr.second->simplify(true, false, false, stage, -1, false, true)) + while (attr.second->simplify(true, false, stage, -1, false, true)) did_something = true; } if (type == AST_CASE && stage == 2) { @@ -1701,14 +1839,14 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, current_filename = filename; - if (type == AST_MODULE) + if (type == AST_MODULE || type == AST_INTERFACE) current_scope.clear(); // convert defparam nodes to cell parameters if (type == AST_DEFPARAM && !children.empty()) { if (children[0]->type != AST_IDENTIFIER) - log_file_error(filename, location.first_line, "Module name in defparam contains non-constant expressions!\n"); + input_error("Module name in defparam contains non-constant expressions!\n"); string modname, paramname = children[0]->str; @@ -1725,12 +1863,12 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, } if (pos == std::string::npos) - log_file_error(filename, location.first_line, "Can't find object for defparam `%s`!\n", RTLIL::unescape_id(paramname).c_str()); + input_error("Can't find object for defparam `%s`!\n", RTLIL::unescape_id(paramname).c_str()); paramname = "\\" + paramname.substr(pos+1); if (current_scope.at(modname)->type != AST_CELL) - log_file_error(filename, location.first_line, "Defparam argument `%s . %s` does not match a cell!\n", + input_error("Defparam argument `%s . %s` does not match a cell!\n", RTLIL::unescape_id(modname).c_str(), RTLIL::unescape_id(paramname).c_str()); AstNode *paraset = new AstNode(AST_PARASET, children[1]->clone(), GetSize(children) > 2 ? children[2]->clone() : NULL); @@ -1746,7 +1884,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, log_assert(children.size() == 1); auto type_node = children[0]; log_assert(type_node->type == AST_WIRE || type_node->type == AST_MEMORY || type_node->type == AST_STRUCT || type_node->type == AST_UNION); - while (type_node->simplify(const_fold, at_zero, in_lvalue, stage, width_hint, sign_hint, in_param)) { + while (type_node->simplify(const_fold, in_lvalue, stage, width_hint, sign_hint, in_param)) { did_something = true; } log_assert(!type_node->is_custom_type); @@ -1759,20 +1897,20 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, log_assert(children[0]->type == AST_WIRETYPE); auto type_name = children[0]->str; if (!current_scope.count(type_name)) { - log_file_error(filename, location.first_line, "Unknown identifier `%s' used as type name\n", type_name.c_str()); + input_error("Unknown identifier `%s' used as type name\n", type_name.c_str()); } AstNode *resolved_type_node = current_scope.at(type_name); if (resolved_type_node->type != AST_TYPEDEF) - log_file_error(filename, location.first_line, "`%s' does not name a type\n", type_name.c_str()); + input_error("`%s' does not name a type\n", type_name.c_str()); log_assert(resolved_type_node->children.size() == 1); AstNode *template_node = resolved_type_node->children[0]; // Ensure typedef itself is fully simplified - while (template_node->simplify(const_fold, at_zero, in_lvalue, stage, width_hint, sign_hint, in_param)) {}; + while (template_node->simplify(const_fold, in_lvalue, stage, width_hint, sign_hint, in_param)) {}; - if (template_node->type == AST_STRUCT || template_node->type == AST_UNION) { - // replace with wire representing the packed structure - newNode = make_packed_struct(template_node, str); + if (!str.empty() && str[0] == '\\' && (template_node->type == AST_STRUCT || template_node->type == AST_UNION)) { + // replace instance with wire representing the packed structure + newNode = make_packed_struct(template_node, str, attributes); newNode->attributes[ID::wiretype] = mkconst_str(resolved_type_node->str); // add original input/output attribute to resolved wire newNode->is_input = this->is_input; @@ -1824,20 +1962,20 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, log_assert(children[1]->type == AST_WIRETYPE); auto type_name = children[1]->str; if (!current_scope.count(type_name)) { - log_file_error(filename, location.first_line, "Unknown identifier `%s' used as type name\n", type_name.c_str()); + input_error("Unknown identifier `%s' used as type name\n", type_name.c_str()); } AstNode *resolved_type_node = current_scope.at(type_name); if (resolved_type_node->type != AST_TYPEDEF) - log_file_error(filename, location.first_line, "`%s' does not name a type\n", type_name.c_str()); + input_error("`%s' does not name a type\n", type_name.c_str()); log_assert(resolved_type_node->children.size() == 1); AstNode *template_node = resolved_type_node->children[0]; // Ensure typedef itself is fully simplified - while (template_node->simplify(const_fold, at_zero, in_lvalue, stage, width_hint, sign_hint, in_param)) {}; + while (template_node->simplify(const_fold, in_lvalue, stage, width_hint, sign_hint, in_param)) {}; if (template_node->type == AST_STRUCT || template_node->type == AST_UNION) { // replace with wire representing the packed structure - newNode = make_packed_struct(template_node, str); + newNode = make_packed_struct(template_node, str, attributes); newNode->attributes[ID::wiretype] = mkconst_str(resolved_type_node->str); newNode->type = type; current_scope[str] = this; @@ -1851,7 +1989,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, children.pop_back(); if (template_node->type == AST_MEMORY) - log_file_error(filename, location.first_line, "unpacked array type `%s' cannot be used for a parameter\n", children[1]->str.c_str()); + input_error("unpacked array type `%s' cannot be used for a parameter\n", children[1]->str.c_str()); is_signed = template_node->is_signed; is_string = template_node->is_string; is_custom_type = template_node->is_custom_type; @@ -1872,10 +2010,10 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, if (type == AST_PREFIX) { if (children[0]->type != AST_CONSTANT) { // dumpAst(NULL, "> "); - log_file_error(filename, location.first_line, "Index in generate block prefix syntax is not constant!\n"); + input_error("Index in generate block prefix syntax is not constant!\n"); } if (children[1]->type == AST_PREFIX) - children[1]->simplify(const_fold, at_zero, in_lvalue, stage, width_hint, sign_hint, in_param); + children[1]->simplify(const_fold, in_lvalue, stage, width_hint, sign_hint, in_param); log_assert(children[1]->type == AST_IDENTIFIER); newNode = children[1]->clone(); const char *second_part = children[1]->str.c_str(); @@ -1888,9 +2026,9 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, // evaluate TO_BITS nodes if (type == AST_TO_BITS) { if (children[0]->type != AST_CONSTANT) - log_file_error(filename, location.first_line, "Left operand of to_bits expression is not constant!\n"); + input_error("Left operand of to_bits expression is not constant!\n"); if (children[1]->type != AST_CONSTANT) - log_file_error(filename, location.first_line, "Right operand of to_bits expression is not constant!\n"); + input_error("Right operand of to_bits expression is not constant!\n"); RTLIL::Const new_value = children[1]->bitsAsConst(children[0]->bitsAsConst().as_int(), children[1]->is_signed); newNode = mkconst_bits(new_value.bits, children[1]->is_signed); goto apply_newNode; @@ -1940,17 +2078,17 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, if (attributes.count(ID::force_upto)) { AstNode *val = attributes[ID::force_upto]; if (val->type != AST_CONSTANT) - log_file_error(filename, location.first_line, "Attribute `force_upto' with non-constant value!\n"); + input_error("Attribute `force_upto' with non-constant value!\n"); force_upto = val->asAttrConst().as_bool(); } if (attributes.count(ID::force_downto)) { AstNode *val = attributes[ID::force_downto]; if (val->type != AST_CONSTANT) - log_file_error(filename, location.first_line, "Attribute `force_downto' with non-constant value!\n"); + input_error("Attribute `force_downto' with non-constant value!\n"); force_downto = val->asAttrConst().as_bool(); } if (force_upto && force_downto) - log_file_error(filename, location.first_line, "Attributes `force_downto' and `force_upto' cannot be both set!\n"); + input_error("Attributes `force_downto' and `force_upto' cannot be both set!\n"); if ((force_upto && !range_swapped) || (force_downto && range_swapped)) { std::swap(range_left, range_right); range_swapped = force_upto; @@ -1974,7 +2112,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, multirange_swapped.clear(); for (auto range : children[1]->children) { if (!range->range_valid) - log_file_error(filename, location.first_line, "Non-constant range on memory decl.\n"); + input_error("Non-constant range on memory decl.\n"); multirange_dimensions.push_back(min(range->range_left, range->range_right)); multirange_dimensions.push_back(max(range->range_left, range->range_right) - min(range->range_left, range->range_right) + 1); multirange_swapped.push_back(range->range_swapped); @@ -1994,7 +2132,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, for (int i = 0; 2*i < GetSize(id2ast->multirange_dimensions); i++) { if (GetSize(children[0]->children) <= i) - log_file_error(filename, location.first_line, "Insufficient number of array indices for %s.\n", log_id(str)); + input_error("Insufficient number of array indices for %s.\n", log_id(str)); AstNode *new_index_expr = children[0]->children[i]->children.at(0)->clone(); @@ -2023,7 +2161,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, if (type == AST_PARAMETER || type == AST_LOCALPARAM || type == AST_ENUM_ITEM) { if (children.size() > 1 && children[1]->type == AST_RANGE) { if (!children[1]->range_valid) - log_file_error(filename, location.first_line, "Non-constant width range on parameter decl.\n"); + input_error("Non-constant width range on parameter decl.\n"); int width = std::abs(children[1]->range_left - children[1]->range_right) + 1; if (children[0]->type == AST_REALVALUE) { RTLIL::Const constvalue = children[0]->realAsConst(width); @@ -2068,6 +2206,14 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, auto range = make_struct_member_range(this, item_node); newNode = new AstNode(AST_IDENTIFIER, range); newNode->str = sname; + // save type and original number of dimensions for $size() etc. + newNode->attributes[ID::wiretype] = item_node->clone(); + if (!item_node->multirange_dimensions.empty() && children.size() > 0) { + if (children[0]->type == AST_RANGE) + newNode->integer = 1; + else if (children[0]->type == AST_MULTIRANGE) + newNode->integer = children[0]->children.size(); + } newNode->basic_prep = true; if (item_node->is_signed) newNode = new AstNode(AST_TO_SIGNED, newNode); @@ -2116,7 +2262,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, } if (current_scope.count(str) == 0) { if (current_ast_mod == nullptr) { - log_file_error(filename, location.first_line, "Identifier `%s' is implicitly declared outside of a module.\n", str.c_str()); + input_error("Identifier `%s' is implicitly declared outside of a module.\n", str.c_str()); } else if (flag_autowire || str == "\\$global_clock") { AstNode *auto_wire = new AstNode(AST_AUTOWIRE); auto_wire->str = str; @@ -2124,7 +2270,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, current_scope[str] = auto_wire; did_something = true; } else { - log_file_error(filename, location.first_line, "Identifier `%s' is implicitly declared and `default_nettype is set to none.\n", str.c_str()); + input_error("Identifier `%s' is implicitly declared and `default_nettype is set to none.\n", str.c_str()); } } if (id2ast != current_scope[str]) { @@ -2137,7 +2283,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, if (type == AST_IDENTIFIER && children.size() == 2 && children[0]->type == AST_RANGE && children[1]->type == AST_RANGE && !in_lvalue && stage == 2) { if (id2ast == NULL || id2ast->type != AST_MEMORY || children[0]->children.size() != 1) - log_file_error(filename, location.first_line, "Invalid bit-select on memory access!\n"); + input_error("Invalid bit-select on memory access!\n"); int mem_width, mem_size, addr_bits; id2ast->meminfo(mem_width, mem_size, addr_bits); @@ -2157,7 +2303,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, if (current_block) wire->attributes[ID::nosync] = AstNode::mkconst_int(1, false); current_ast_mod->children.push_back(wire); - while (wire->simplify(true, false, false, 1, -1, false, false)) { } + while (wire->simplify(true, false, 1, -1, false, false)) { } AstNode *data = clone(); delete data->children[1]; @@ -2191,7 +2337,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, } if (type == AST_WHILE) - log_file_error(filename, location.first_line, "While loops are only allowed in constant functions!\n"); + input_error("While loops are only allowed in constant functions!\n"); if (type == AST_REPEAT) { @@ -2199,10 +2345,10 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, AstNode *body = children[1]; // eval count expression - while (count->simplify(true, false, false, stage, 32, true, false)) { } + while (count->simplify(true, false, stage, 32, true, false)) { } if (count->type != AST_CONSTANT) - log_file_error(filename, location.first_line, "Repeat loops outside must have constant repeat counts!\n"); + input_error("Repeat loops outside must have constant repeat counts!\n"); // convert to a block with the body repeated n times type = AST_BLOCK; @@ -2237,17 +2383,17 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, } if (init_ast->type != AST_ASSIGN_EQ) - log_file_error(filename, location.first_line, "Unsupported 1st expression of %s for-loop!\n", loop_type_str); + input_error("Unsupported 1st expression of %s for-loop!\n", loop_type_str); if (next_ast->type != AST_ASSIGN_EQ) - log_file_error(filename, location.first_line, "Unsupported 3rd expression of %s for-loop!\n", loop_type_str); + input_error("Unsupported 3rd expression of %s for-loop!\n", loop_type_str); if (init_ast->children[0]->id2ast == NULL || init_ast->children[0]->id2ast->type != var_type) - log_file_error(filename, location.first_line, "Left hand side of 1st expression of %s for-loop is not a %s!\n", loop_type_str, var_type_str); + input_error("Left hand side of 1st expression of %s for-loop is not a %s!\n", loop_type_str, var_type_str); if (next_ast->children[0]->id2ast == NULL || next_ast->children[0]->id2ast->type != var_type) - log_file_error(filename, location.first_line, "Left hand side of 3rd expression of %s for-loop is not a %s!\n", loop_type_str, var_type_str); + input_error("Left hand side of 3rd expression of %s for-loop is not a %s!\n", loop_type_str, var_type_str); if (init_ast->children[0]->id2ast != next_ast->children[0]->id2ast) - log_file_error(filename, location.first_line, "Incompatible left-hand sides in 1st and 3rd expression of %s for-loop!\n", loop_type_str); + input_error("Incompatible left-hand sides in 1st and 3rd expression of %s for-loop!\n", loop_type_str); // eval 1st expression AstNode *varbuf = init_ast->children[1]->clone(); @@ -2255,11 +2401,11 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, int expr_width_hint = -1; bool expr_sign_hint = true; varbuf->detectSignWidth(expr_width_hint, expr_sign_hint); - while (varbuf->simplify(true, false, false, stage, 32, true, false)) { } + while (varbuf->simplify(true, false, stage, 32, true, false)) { } } if (varbuf->type != AST_CONSTANT) - log_file_error(filename, location.first_line, "Right hand side of 1st expression of %s for-loop is not constant!\n", loop_type_str); + input_error("Right hand side of 1st expression of %s for-loop is not constant!\n", loop_type_str); auto resolved = current_scope.at(init_ast->children[0]->str); if (resolved->range_valid) { @@ -2296,11 +2442,11 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, int expr_width_hint = -1; bool expr_sign_hint = true; buf->detectSignWidth(expr_width_hint, expr_sign_hint); - while (buf->simplify(true, false, false, stage, expr_width_hint, expr_sign_hint, false)) { } + while (buf->simplify(true, false, stage, expr_width_hint, expr_sign_hint, false)) { } } if (buf->type != AST_CONSTANT) - log_file_error(filename, location.first_line, "2nd expression of %s for-loop is not constant!\n", loop_type_str); + input_error("2nd expression of %s for-loop is not constant!\n", loop_type_str); if (buf->integer == 0) { delete buf; @@ -2331,7 +2477,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, if (type == AST_GENFOR) { for (size_t i = 0; i < buf->children.size(); i++) { - buf->children[i]->simplify(const_fold, false, false, stage, -1, false, false); + buf->children[i]->simplify(const_fold, false, stage, -1, false, false); current_ast_mod->children.push_back(buf->children[i]); } } else { @@ -2347,11 +2493,11 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, int expr_width_hint = -1; bool expr_sign_hint = true; buf->detectSignWidth(expr_width_hint, expr_sign_hint); - while (buf->simplify(true, false, false, stage, expr_width_hint, expr_sign_hint, true)) { } + while (buf->simplify(true, false, stage, expr_width_hint, expr_sign_hint, true)) { } } if (buf->type != AST_CONSTANT) - log_file_error(filename, location.first_line, "Right hand side of 3rd expression of %s for-loop is not constant (%s)!\n", loop_type_str, type2str(buf->type).c_str()); + input_error("Right hand side of 3rd expression of %s for-loop is not constant (%s)!\n", loop_type_str, type2str(buf->type).c_str()); delete varbuf->children[0]; varbuf->children[0] = buf; @@ -2377,7 +2523,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, if (children[i]->type == AST_WIRE || children[i]->type == AST_MEMORY || children[i]->type == AST_PARAMETER || children[i]->type == AST_LOCALPARAM || children[i]->type == AST_TYPEDEF) { log_assert(!VERILOG_FRONTEND::sv_mode); - log_file_error(children[i]->filename, children[i]->location.first_line, "Local declaration in unnamed block is only supported in SystemVerilog mode!\n"); + children[i]->input_error("Local declaration in unnamed block is only supported in SystemVerilog mode!\n"); } } @@ -2399,7 +2545,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, std::vector new_children; for (size_t i = 0; i < children.size(); i++) if (children[i]->type == AST_WIRE || children[i]->type == AST_MEMORY || children[i]->type == AST_PARAMETER || children[i]->type == AST_LOCALPARAM || children[i]->type == AST_TYPEDEF) { - children[i]->simplify(false, false, false, stage, -1, false, false); + children[i]->simplify(false, false, stage, -1, false, false); current_ast_mod->children.push_back(children[i]); current_scope[children[i]->str] = children[i]; } else @@ -2418,7 +2564,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, } for (size_t i = 0; i < children.size(); i++) { - children[i]->simplify(const_fold, false, false, stage, -1, false, false); + children[i]->simplify(const_fold, false, stage, -1, false, false); current_ast_mod->children.push_back(children[i]); } @@ -2430,11 +2576,11 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, if (type == AST_GENIF && children.size() != 0) { AstNode *buf = children[0]->clone(); - while (buf->simplify(true, false, false, stage, width_hint, sign_hint, false)) { } + while (buf->simplify(true, false, stage, width_hint, sign_hint, false)) { } if (buf->type != AST_CONSTANT) { // for (auto f : log_files) // dumpAst(f, "verilog-ast> "); - log_file_error(filename, location.first_line, "Condition for generate if is not constant!\n"); + input_error("Condition for generate if is not constant!\n"); } if (buf->asBool() != 0) { delete buf; @@ -2454,7 +2600,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, } for (size_t i = 0; i < buf->children.size(); i++) { - buf->children[i]->simplify(const_fold, false, false, stage, -1, false, false); + buf->children[i]->simplify(const_fold, false, stage, -1, false, false); current_ast_mod->children.push_back(buf->children[i]); } @@ -2470,11 +2616,11 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, if (type == AST_GENCASE && children.size() != 0) { AstNode *buf = children[0]->clone(); - while (buf->simplify(true, false, false, stage, width_hint, sign_hint, false)) { } + while (buf->simplify(true, false, stage, width_hint, sign_hint, false)) { } if (buf->type != AST_CONSTANT) { // for (auto f : log_files) // dumpAst(f, "verilog-ast> "); - log_file_error(filename, location.first_line, "Condition for generate case is not constant!\n"); + input_error("Condition for generate case is not constant!\n"); } bool ref_signed = buf->is_signed; @@ -2504,11 +2650,11 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, continue; buf = child->clone(); - while (buf->simplify(true, false, false, stage, width_hint, sign_hint, true)) { } + while (buf->simplify(true, false, stage, width_hint, sign_hint, true)) { } if (buf->type != AST_CONSTANT) { // for (auto f : log_files) // dumpAst(f, "verilog-ast> "); - log_file_error(filename, location.first_line, "Expression in generate case is not constant!\n"); + input_error("Expression in generate case is not constant!\n"); } bool is_selected = RTLIL::const_eq(ref_value, buf->bitsAsConst(), ref_signed && buf->is_signed, ref_signed && buf->is_signed, 1).as_bool(); @@ -2532,7 +2678,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, } for (size_t i = 0; i < buf->children.size(); i++) { - buf->children[i]->simplify(const_fold, false, false, stage, -1, false, false); + buf->children[i]->simplify(const_fold, false, stage, -1, false, false); current_ast_mod->children.push_back(buf->children[i]); } @@ -2548,7 +2694,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, if (type == AST_CELLARRAY) { if (!children.at(0)->range_valid) - log_file_error(filename, location.first_line, "Non-constant array range on cell array.\n"); + input_error("Non-constant array range on cell array.\n"); newNode = new AstNode(AST_GENBLOCK); int num = max(children.at(0)->range_left, children.at(0)->range_right) - min(children.at(0)->range_left, children.at(0)->range_right) + 1; @@ -2559,7 +2705,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, newNode->children.push_back(new_cell); new_cell->str += stringf("[%d]", idx); if (new_cell->type == AST_PRIMITIVE) { - log_file_error(filename, location.first_line, "Cell arrays of primitives are currently not supported.\n"); + input_error("Cell arrays of primitives are currently not supported.\n"); } else { log_assert(new_cell->children.at(0)->type == AST_CELLTYPE); new_cell->children.at(0)->str = stringf("$array:%d:%d:%s", i, num, new_cell->children.at(0)->str.c_str()); @@ -2573,7 +2719,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, if (type == AST_PRIMITIVE) { if (children.size() < 2) - log_file_error(filename, location.first_line, "Insufficient number of arguments for primitive `%s'!\n", str.c_str()); + input_error("Insufficient number of arguments for primitive `%s'!\n", str.c_str()); std::vector children_list; for (auto child : children) { @@ -2588,7 +2734,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, if (str == "bufif0" || str == "bufif1" || str == "notif0" || str == "notif1") { if (children_list.size() != 3) - log_file_error(filename, location.first_line, "Invalid number of arguments for primitive `%s'!\n", str.c_str()); + input_error("Invalid number of arguments for primitive `%s'!\n", str.c_str()); std::vector z_const(1, RTLIL::State::Sz); @@ -2679,33 +2825,45 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, goto skip_dynamic_range_lvalue_expansion; int source_width = children[0]->id2ast->range_left - children[0]->id2ast->range_right + 1; + int source_offset = children[0]->id2ast->range_right; int result_width = 1; + int stride = 1; + AST::AstNode *member_node = get_struct_member(children[0]); + if (member_node) { + // Clamp chunk to range of member within struct/union. + log_assert(!source_offset && !children[0]->id2ast->range_swapped); + source_width = member_node->range_left - member_node->range_right + 1; + + // When the (* nowrshmsk *) attribute is set, a CASE block is generated below + // to select the indexed bit slice. When a multirange array is indexed, the + // start of each possible slice is separated by the bit stride of the last + // index dimension, and we can optimize the CASE block accordingly. + // The dimension of the original array expression is saved in the 'integer' field. + int dims = children[0]->integer; + stride = source_width; + for (int dim = 0; dim < dims; dim++) { + stride /= get_struct_range_width(member_node, dim); + } + } AstNode *shift_expr = NULL; AstNode *range = children[0]->children[0]; - if (range->children.size() == 1) { - shift_expr = range->children[0]->clone(); - } else { + if (!try_determine_range_width(range, result_width)) + input_error("Unsupported expression on dynamic range select on signal `%s'!\n", str.c_str()); + + if (range->children.size() >= 2) shift_expr = range->children[1]->clone(); - AstNode *left_at_zero_ast = range->children[0]->clone(); - AstNode *right_at_zero_ast = range->children[1]->clone(); - while (left_at_zero_ast->simplify(true, true, false, stage, -1, false, false)) { } - while (right_at_zero_ast->simplify(true, true, false, stage, -1, false, false)) { } - if (left_at_zero_ast->type != AST_CONSTANT || right_at_zero_ast->type != AST_CONSTANT) - log_file_error(filename, location.first_line, "Unsupported expression on dynamic range select on signal `%s'!\n", str.c_str()); - result_width = abs(int(left_at_zero_ast->integer - right_at_zero_ast->integer)) + 1; - delete left_at_zero_ast; - delete right_at_zero_ast; - } + else + shift_expr = range->children[0]->clone(); bool use_case_method = false; if (children[0]->id2ast->attributes.count(ID::nowrshmsk)) { AstNode *node = children[0]->id2ast->attributes.at(ID::nowrshmsk); - while (node->simplify(true, false, false, stage, -1, false, false)) { } + while (node->simplify(true, false, stage, -1, false, false)) { } if (node->type != AST_CONSTANT) - log_file_error(filename, location.first_line, "Non-constant value for `nowrshmsk' attribute on `%s'!\n", children[0]->id2ast->str.c_str()); + input_error("Non-constant value for `nowrshmsk' attribute on `%s'!\n", children[0]->id2ast->str.c_str()); if (node->asAttrConst().as_bool()) use_case_method = true; } @@ -2719,12 +2877,14 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, did_something = true; newNode = new AstNode(AST_CASE, shift_expr); - for (int i = 0; i < source_width; i++) { - int start_bit = children[0]->id2ast->range_right + i; + for (int i = 0; i < source_width; i += stride) { + int start_bit = source_offset + i; int end_bit = std::min(start_bit+result_width,source_width) - 1; AstNode *cond = new AstNode(AST_COND, mkconst_int(start_bit, true)); AstNode *lvalue = children[0]->clone(); lvalue->delete_children(); + if (member_node) + lvalue->attributes[ID::wiretype] = member_node->clone(); lvalue->children.push_back(new AstNode(AST_RANGE, mkconst_int(end_bit, true), mkconst_int(start_bit, true))); cond->children.push_back(new AstNode(AST_BLOCK, new AstNode(type, lvalue, children[1]->clone()))); @@ -2739,14 +2899,14 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, wire_mask->str = stringf("$bitselwrite$mask$%s:%d$%d", RTLIL::encode_filename(filename).c_str(), location.first_line, autoidx++); wire_mask->attributes[ID::nosync] = AstNode::mkconst_int(1, false); wire_mask->is_logic = true; - while (wire_mask->simplify(true, false, false, 1, -1, false, false)) { } + while (wire_mask->simplify(true, false, 1, -1, false, false)) { } current_ast_mod->children.push_back(wire_mask); AstNode *wire_data = new AstNode(AST_WIRE, new AstNode(AST_RANGE, mkconst_int(source_width-1, true), mkconst_int(0, true))); wire_data->str = stringf("$bitselwrite$data$%s:%d$%d", RTLIL::encode_filename(filename).c_str(), location.first_line, autoidx++); wire_data->attributes[ID::nosync] = AstNode::mkconst_int(1, false); wire_data->is_logic = true; - while (wire_data->simplify(true, false, false, 1, -1, false, false)) { } + while (wire_data->simplify(true, false, 1, -1, false, false)) { } current_ast_mod->children.push_back(wire_data); int shamt_width_hint = -1; @@ -2758,7 +2918,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, wire_sel->attributes[ID::nosync] = AstNode::mkconst_int(1, false); wire_sel->is_logic = true; wire_sel->is_signed = shamt_sign_hint; - while (wire_sel->simplify(true, false, false, 1, -1, false, false)) { } + while (wire_sel->simplify(true, false, 1, -1, false, false)) { } current_ast_mod->children.push_back(wire_sel); did_something = true; @@ -2766,6 +2926,8 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, AstNode *lvalue = children[0]->clone(); lvalue->delete_children(); + if (member_node) + lvalue->attributes[ID::wiretype] = member_node->clone(); AstNode *ref_mask = new AstNode(AST_IDENTIFIER); ref_mask->str = wire_mask->str; @@ -2796,7 +2958,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, shamt = new AstNode(AST_TO_SIGNED, shamt); // offset the shift amount by the lower bound of the dimension - int start_bit = children[0]->id2ast->range_right; + int start_bit = source_offset; shamt = new AstNode(AST_SUB, shamt, mkconst_int(start_bit, true)); // reflect the shift amount if the dimension is swapped @@ -2839,7 +3001,7 @@ skip_dynamic_range_lvalue_expansion:; wire_check->was_checked = true; current_ast_mod->children.push_back(wire_check); current_scope[wire_check->str] = wire_check; - while (wire_check->simplify(true, false, false, 1, -1, false, false)) { } + while (wire_check->simplify(true, false, 1, -1, false, false)) { } AstNode *wire_en = new AstNode(AST_WIRE); wire_en->str = id_en; @@ -2851,7 +3013,7 @@ skip_dynamic_range_lvalue_expansion:; current_ast_mod->children.back()->children[0]->children[0]->children[0]->was_checked = true; } current_scope[wire_en->str] = wire_en; - while (wire_en->simplify(true, false, false, 1, -1, false, false)) { } + while (wire_en->simplify(true, false, 1, -1, false, false)) { } AstNode *check_defval; if (type == AST_LIVE || type == AST_FAIR) { @@ -2944,7 +3106,7 @@ skip_dynamic_range_lvalue_expansion:; current_ast_mod->children.push_back(wire_tmp); current_scope[wire_tmp->str] = wire_tmp; wire_tmp->attributes[ID::nosync] = AstNode::mkconst_int(1, false); - while (wire_tmp->simplify(true, false, false, 1, -1, false, false)) { } + while (wire_tmp->simplify(true, false, 1, -1, false, false)) { } wire_tmp->is_logic = true; AstNode *wire_tmp_id = new AstNode(AST_IDENTIFIER); @@ -3014,7 +3176,7 @@ skip_dynamic_range_lvalue_expansion:; wire_addr->was_checked = true; current_ast_mod->children.push_back(wire_addr); current_scope[wire_addr->str] = wire_addr; - while (wire_addr->simplify(true, false, false, 1, -1, false, false)) { } + while (wire_addr->simplify(true, false, 1, -1, false, false)) { } AstNode *assign_addr = new AstNode(AST_ASSIGN_EQ, new AstNode(AST_IDENTIFIER), mkconst_bits(x_bits_addr, false)); assign_addr->children[0]->str = id_addr; @@ -3040,7 +3202,7 @@ skip_dynamic_range_lvalue_expansion:; wire_data->is_signed = mem_signed; current_ast_mod->children.push_back(wire_data); current_scope[wire_data->str] = wire_data; - while (wire_data->simplify(true, false, false, 1, -1, false, false)) { } + while (wire_data->simplify(true, false, 1, -1, false, false)) { } AstNode *assign_data = new AstNode(AST_ASSIGN_EQ, new AstNode(AST_IDENTIFIER), mkconst_bits(x_bits_data, false)); assign_data->children[0]->str = id_data; @@ -3056,7 +3218,7 @@ skip_dynamic_range_lvalue_expansion:; wire_en->was_checked = true; current_ast_mod->children.push_back(wire_en); current_scope[wire_en->str] = wire_en; - while (wire_en->simplify(true, false, false, 1, -1, false, false)) { } + while (wire_en->simplify(true, false, 1, -1, false, false)) { } AstNode *assign_en_first = new AstNode(AST_ASSIGN_EQ, new AstNode(AST_IDENTIFIER), mkconst_int(0, false, mem_width)); assign_en_first->children[0]->str = id_en; @@ -3097,19 +3259,20 @@ skip_dynamic_range_lvalue_expansion:; else { AstNode *the_range = children[0]->children[1]; - AstNode *left_at_zero_ast = the_range->children[0]->clone(); - AstNode *right_at_zero_ast = the_range->children.size() >= 2 ? the_range->children[1]->clone() : left_at_zero_ast->clone(); - AstNode *offset_ast = right_at_zero_ast->clone(); + AstNode *offset_ast; + int width; + + if (!try_determine_range_width(the_range, width)) + input_error("Unsupported expression on dynamic range select on signal `%s'!\n", str.c_str()); + + if (the_range->children.size() >= 2) + offset_ast = the_range->children[1]->clone(); + else + offset_ast = the_range->children[0]->clone(); if (mem_data_range_offset) offset_ast = new AstNode(AST_SUB, offset_ast, mkconst_int(mem_data_range_offset, true)); - while (left_at_zero_ast->simplify(true, true, false, 1, -1, false, false)) { } - while (right_at_zero_ast->simplify(true, true, false, 1, -1, false, false)) { } - if (left_at_zero_ast->type != AST_CONSTANT || right_at_zero_ast->type != AST_CONSTANT) - log_file_error(filename, location.first_line, "Unsupported expression on dynamic range select on signal `%s'!\n", str.c_str()); - int width = abs(int(left_at_zero_ast->integer - right_at_zero_ast->integer)) + 1; - assign_data = new AstNode(AST_ASSIGN_EQ, new AstNode(AST_IDENTIFIER), new AstNode(AST_SHIFT_LEFT, children[1]->clone(), offset_ast->clone())); assign_data->children[0]->str = id_data; @@ -3121,9 +3284,6 @@ skip_dynamic_range_lvalue_expansion:; new AstNode(AST_SHIFT_LEFT, mkconst_bits(set_bits_en, false), offset_ast->clone())); assign_en->children[0]->str = id_en; assign_en->children[0]->was_checked = true; - - delete left_at_zero_ast; - delete right_at_zero_ast; delete offset_ast; } } @@ -3186,7 +3346,7 @@ skip_dynamic_range_lvalue_expansion:; AstNode *wire = new AstNode(AST_WIRE); wire->str = stringf("$initstate$%d_wire", myidx); current_ast_mod->children.push_back(wire); - while (wire->simplify(true, false, false, 1, -1, false, false)) { } + while (wire->simplify(true, false, 1, -1, false, false)) { } AstNode *cell = new AstNode(AST_CELL, new AstNode(AST_CELLTYPE), new AstNode(AST_ARGUMENT, new AstNode(AST_IDENTIFIER))); cell->str = stringf("$initstate$%d", myidx); @@ -3195,7 +3355,7 @@ skip_dynamic_range_lvalue_expansion:; cell->children[1]->children[0]->str = wire->str; cell->children[1]->children[0]->id2ast = wire; current_ast_mod->children.push_back(cell); - while (cell->simplify(true, false, false, 1, -1, false, false)) { } + while (cell->simplify(true, false, 1, -1, false, false)) { } newNode = new AstNode(AST_IDENTIFIER); newNode->str = wire->str; @@ -3211,19 +3371,19 @@ skip_dynamic_range_lvalue_expansion:; int num_steps = 1; if (GetSize(children) != 1 && GetSize(children) != 2) - log_file_error(filename, location.first_line, "System function %s got %d arguments, expected 1 or 2.\n", + input_error("System function %s got %d arguments, expected 1 or 2.\n", RTLIL::unescape_id(str).c_str(), int(children.size())); if (!current_always_clocked) - log_file_error(filename, location.first_line, "System function %s is only allowed in clocked blocks.\n", + input_error("System function %s is only allowed in clocked blocks.\n", RTLIL::unescape_id(str).c_str()); if (GetSize(children) == 2) { AstNode *buf = children[1]->clone(); - while (buf->simplify(true, false, false, stage, -1, false, false)) { } + while (buf->simplify(true, false, stage, -1, false, false)) { } if (buf->type != AST_CONSTANT) - log_file_error(filename, location.first_line, "Failed to evaluate system function `%s' with non-constant value.\n", str.c_str()); + input_error("Failed to evaluate system function `%s' with non-constant value.\n", str.c_str()); num_steps = buf->asInt(true); delete buf; @@ -3256,7 +3416,7 @@ skip_dynamic_range_lvalue_expansion:; current_ast_mod->children.push_back(reg); - while (reg->simplify(true, false, false, 1, -1, false, false)) { } + while (reg->simplify(true, false, 1, -1, false, false)) { } AstNode *regid = new AstNode(AST_IDENTIFIER); regid->str = reg->str; @@ -3286,11 +3446,11 @@ skip_dynamic_range_lvalue_expansion:; if (str == "\\$stable" || str == "\\$rose" || str == "\\$fell" || str == "\\$changed") { if (GetSize(children) != 1) - log_file_error(filename, location.first_line, "System function %s got %d arguments, expected 1.\n", + input_error("System function %s got %d arguments, expected 1.\n", RTLIL::unescape_id(str).c_str(), int(children.size())); if (!current_always_clocked) - log_file_error(filename, location.first_line, "System function %s is only allowed in clocked blocks.\n", + input_error("System function %s is only allowed in clocked blocks.\n", RTLIL::unescape_id(str).c_str()); AstNode *present = children.at(0)->clone(); @@ -3328,13 +3488,13 @@ skip_dynamic_range_lvalue_expansion:; if (str == "\\$clog2") { if (children.size() != 1) - log_file_error(filename, location.first_line, "System function %s got %d arguments, expected 1.\n", + input_error("System function %s got %d arguments, expected 1.\n", RTLIL::unescape_id(str).c_str(), int(children.size())); AstNode *buf = children[0]->clone(); - while (buf->simplify(true, false, false, stage, width_hint, sign_hint, false)) { } + while (buf->simplify(true, false, stage, width_hint, sign_hint, false)) { } if (buf->type != AST_CONSTANT) - log_file_error(filename, location.first_line, "Failed to evaluate system function `%s' with non-constant value.\n", str.c_str()); + input_error("Failed to evaluate system function `%s' with non-constant value.\n", str.c_str()); RTLIL::Const arg_value = buf->bitsAsConst(); if (arg_value.as_bool()) @@ -3355,16 +3515,16 @@ skip_dynamic_range_lvalue_expansion:; int dim = 1; if (str == "\\$bits") { if (children.size() != 1) - log_file_error(filename, location.first_line, "System function %s got %d arguments, expected 1.\n", + input_error("System function %s got %d arguments, expected 1.\n", RTLIL::unescape_id(str).c_str(), int(children.size())); } else { if (children.size() != 1 && children.size() != 2) - log_file_error(filename, location.first_line, "System function %s got %d arguments, expected 1 or 2.\n", + input_error("System function %s got %d arguments, expected 1 or 2.\n", RTLIL::unescape_id(str).c_str(), int(children.size())); if (children.size() == 2) { AstNode *buf = children[1]->clone(); // Evaluate constant expression - while (buf->simplify(true, false, false, stage, width_hint, sign_hint, false)) { } + while (buf->simplify(true, false, stage, width_hint, sign_hint, false)) { } dim = buf->asInt(false); delete buf; } @@ -3375,7 +3535,7 @@ skip_dynamic_range_lvalue_expansion:; AstNode *id_ast = NULL; // Is this needed? - //while (buf->simplify(true, false, false, stage, width_hint, sign_hint, false)) { } + //while (buf->simplify(true, false, stage, width_hint, sign_hint, false)) { } buf->detectSignWidth(width_hint, sign_hint); if (buf->type == AST_IDENTIFIER) { @@ -3383,25 +3543,40 @@ skip_dynamic_range_lvalue_expansion:; if (id_ast == NULL && current_scope.count(buf->str)) id_ast = current_scope.at(buf->str); if (!id_ast) - log_file_error(filename, location.first_line, "Failed to resolve identifier %s for width detection!\n", buf->str.c_str()); - // a slice of our identifier means we advance to the next dimension, e.g. $size(a[3]) - if (buf->children.size() > 0) { - // something is hanging below this identifier - if (buf->children[0]->type == AST_RANGE && buf->integer == 0) - // if integer == 0, this node was originally created as AST_RANGE so it's dimension is 1 - dim++; - // more than one range, e.g. $size(a[3][2]) - else // created an AST_MULTIRANGE, converted to AST_RANGE, but original dimension saved in 'integer' field - dim += buf->integer; // increment by multirange size + input_error("Failed to resolve identifier %s for width detection!\n", buf->str.c_str()); + + // Check for item in packed struct / union + AST::AstNode *item_node = get_struct_member(buf); + if (id_ast->type == AST_WIRE && item_node) { + // The dimension of the original array expression is saved in the 'integer' field + dim += buf->integer; + if (item_node->multirange_dimensions.empty()) { + if (dim != 1) + input_error("Dimension %d out of range in `%s', as it only has one dimension!\n", dim, item_node->str.c_str()); + left = high = item_node->range_left; + right = low = item_node->range_right; + } else { + int dims = GetSize(item_node->multirange_dimensions)/2; + if (dim < 1 || dim > dims) + input_error("Dimension %d out of range in `%s', as it only has dimensions 1..%d!\n", dim, item_node->str.c_str(), dims); + right = low = get_struct_range_offset(item_node, dim - 1); + left = high = low + get_struct_range_width(item_node, dim - 1) - 1; + if (item_node->multirange_swapped[dim - 1]) { + std::swap(left, right); + } + for (int i = dim; i < dims; i++) { + mem_depth *= get_struct_range_width(item_node, i); + } + } } - // We have 4 cases: + // Otherwise, we have 4 cases: // wire x; ==> AST_WIRE, no AST_RANGE children // wire [1:0]x; ==> AST_WIRE, AST_RANGE children // wire [1:0]x[1:0]; ==> AST_MEMORY, two AST_RANGE children (1st for packed, 2nd for unpacked) // wire [1:0]x[1:0][1:0]; ==> AST_MEMORY, one AST_RANGE child (0) for packed, then AST_MULTIRANGE child (1) for unpacked // (updated: actually by the time we are here, AST_MULTIRANGE is converted into one big AST_RANGE) // case 0 handled by default - if ((id_ast->type == AST_WIRE || id_ast->type == AST_MEMORY) && id_ast->children.size() > 0) { + else if ((id_ast->type == AST_WIRE || id_ast->type == AST_MEMORY) && id_ast->children.size() > 0) { // handle packed array left/right for case 1, and cases 2/3 when requesting the last dimension (packed side) AstNode *wire_range = id_ast->children[0]; left = wire_range->children[0]->integer; @@ -3410,23 +3585,34 @@ skip_dynamic_range_lvalue_expansion:; low = min(left, right); } if (id_ast->type == AST_MEMORY) { + // a slice of our identifier means we advance to the next dimension, e.g. $size(a[3]) + if (buf->children.size() > 0) { + // something is hanging below this identifier + if (buf->children[0]->type == AST_RANGE && buf->integer == 0) + // if integer == 0, this node was originally created as AST_RANGE so it's dimension is 1 + dim++; + // more than one range, e.g. $size(a[3][2]) + else // created an AST_MULTIRANGE, converted to AST_RANGE, but original dimension saved in 'integer' field + dim += buf->integer; // increment by multirange size + } + // We got here only if the argument is a memory // Otherwise $size() and $bits() return the expression width AstNode *mem_range = id_ast->children[1]; if (str == "\\$bits") { if (mem_range->type == AST_RANGE) { if (!mem_range->range_valid) - log_file_error(filename, location.first_line, "Failed to detect width of memory access `%s'!\n", buf->str.c_str()); + input_error("Failed to detect width of memory access `%s'!\n", buf->str.c_str()); mem_depth = mem_range->range_left - mem_range->range_right + 1; } else - log_file_error(filename, location.first_line, "Unknown memory depth AST type in `%s'!\n", buf->str.c_str()); + input_error("Unknown memory depth AST type in `%s'!\n", buf->str.c_str()); } else { // $size(), $left(), $right(), $high(), $low() int dims = 1; if (mem_range->type == AST_RANGE) { if (id_ast->multirange_dimensions.empty()) { if (!mem_range->range_valid) - log_file_error(filename, location.first_line, "Failed to detect width of memory access `%s'!\n", buf->str.c_str()); + input_error("Failed to detect width of memory access `%s'!\n", buf->str.c_str()); if (dim == 1) { left = mem_range->range_right; right = mem_range->range_left; @@ -3447,10 +3633,10 @@ skip_dynamic_range_lvalue_expansion:; left = high; } } else if ((dim > dims+1) || (dim < 0)) - log_file_error(filename, location.first_line, "Dimension %d out of range in `%s', as it only has dimensions 1..%d!\n", dim, buf->str.c_str(), dims+1); + input_error("Dimension %d out of range in `%s', as it only has dimensions 1..%d!\n", dim, buf->str.c_str(), dims+1); } } else { - log_file_error(filename, location.first_line, "Unknown memory depth AST type in `%s'!\n", buf->str.c_str()); + input_error("Unknown memory depth AST type in `%s'!\n", buf->str.c_str()); } } } @@ -3469,7 +3655,7 @@ skip_dynamic_range_lvalue_expansion:; result = right; else if (str == "\\$size") result = width; - else { + else { // str == "\\$bits" result = width * mem_depth; } newNode = mkconst_int(result, true); @@ -3487,18 +3673,18 @@ skip_dynamic_range_lvalue_expansion:; if (func_with_two_arguments) { if (children.size() != 2) - log_file_error(filename, location.first_line, "System function %s got %d arguments, expected 2.\n", + input_error("System function %s got %d arguments, expected 2.\n", RTLIL::unescape_id(str).c_str(), int(children.size())); } else { if (children.size() != 1) - log_file_error(filename, location.first_line, "System function %s got %d arguments, expected 1.\n", + input_error("System function %s got %d arguments, expected 1.\n", RTLIL::unescape_id(str).c_str(), int(children.size())); } if (children.size() >= 1) { - while (children[0]->simplify(true, false, false, stage, width_hint, sign_hint, false)) { } + while (children[0]->simplify(true, false, stage, width_hint, sign_hint, false)) { } if (!children[0]->isConst()) - log_file_error(filename, location.first_line, "Failed to evaluate system function `%s' with non-constant argument.\n", + input_error("Failed to evaluate system function `%s' with non-constant argument.\n", RTLIL::unescape_id(str).c_str()); int child_width_hint = width_hint; bool child_sign_hint = sign_hint; @@ -3507,9 +3693,9 @@ skip_dynamic_range_lvalue_expansion:; } if (children.size() >= 2) { - while (children[1]->simplify(true, false, false, stage, width_hint, sign_hint, false)) { } + while (children[1]->simplify(true, false, stage, width_hint, sign_hint, false)) { } if (!children[1]->isConst()) - log_file_error(filename, location.first_line, "Failed to evaluate system function `%s' with non-constant argument.\n", + input_error("Failed to evaluate system function `%s' with non-constant argument.\n", RTLIL::unescape_id(str).c_str()); int child_width_hint = width_hint; bool child_sign_hint = sign_hint; @@ -3550,9 +3736,9 @@ skip_dynamic_range_lvalue_expansion:; if (str == "\\$sformatf") { AstNode *node_string = children[0]; - while (node_string->simplify(true, false, false, stage, width_hint, sign_hint, false)) { } + while (node_string->simplify(true, false, stage, width_hint, sign_hint, false)) { } if (node_string->type != AST_CONSTANT) - log_file_error(filename, location.first_line, "Failed to evaluate system function `%s' with non-constant 1st argument.\n", str.c_str()); + input_error("Failed to evaluate system function `%s' with non-constant 1st argument.\n", str.c_str()); std::string sformat = node_string->bitsAsConst().decode_string(); std::string sout = process_format_str(sformat, 1, stage, width_hint, sign_hint); newNode = AstNode::mkconst_str(sout); @@ -3561,7 +3747,7 @@ skip_dynamic_range_lvalue_expansion:; if (str == "\\$countbits") { if (children.size() < 2) - log_file_error(filename, location.first_line, "System function %s got %d arguments, expected at least 2.\n", + input_error("System function %s got %d arguments, expected at least 2.\n", RTLIL::unescape_id(str).c_str(), int(children.size())); std::vector control_bits; @@ -3569,11 +3755,11 @@ skip_dynamic_range_lvalue_expansion:; // Determine which bits to count for (size_t i = 1; i < children.size(); i++) { AstNode *node = children[i]; - while (node->simplify(true, false, false, stage, -1, false, false)) { } + while (node->simplify(true, false, stage, -1, false, false)) { } if (node->type != AST_CONSTANT) - log_file_error(filename, location.first_line, "Failed to evaluate system function `%s' with non-constant control bit argument.\n", str.c_str()); + input_error("Failed to evaluate system function `%s' with non-constant control bit argument.\n", str.c_str()); if (node->bits.size() != 1) - log_file_error(filename, location.first_line, "Failed to evaluate system function `%s' with control bit width != 1.\n", str.c_str()); + input_error("Failed to evaluate system function `%s' with control bit width != 1.\n", str.c_str()); control_bits.push_back(node->bits[0]); } @@ -3620,7 +3806,7 @@ skip_dynamic_range_lvalue_expansion:; if (str == "\\$countones" || str == "\\$isunknown" || str == "\\$onehot" || str == "\\$onehot0") { if (children.size() != 1) - log_file_error(filename, location.first_line, "System function %s got %d arguments, expected 1.\n", + input_error("System function %s got %d arguments, expected 1.\n", RTLIL::unescape_id(str).c_str(), int(children.size())); AstNode *countbits = clone(); @@ -3660,14 +3846,14 @@ skip_dynamic_range_lvalue_expansion:; for (int i = 2; i < GetSize(dpi_decl->children); i++) { if (i-2 >= GetSize(children)) - log_file_error(filename, location.first_line, "Insufficient number of arguments in DPI function call.\n"); + input_error("Insufficient number of arguments in DPI function call.\n"); argtypes.push_back(RTLIL::unescape_id(dpi_decl->children.at(i)->str)); args.push_back(children.at(i-2)->clone()); - while (args.back()->simplify(true, false, false, stage, -1, false, true)) { } + while (args.back()->simplify(true, false, stage, -1, false, true)) { } if (args.back()->type != AST_CONSTANT && args.back()->type != AST_REALVALUE) - log_file_error(filename, location.first_line, "Failed to evaluate DPI function with non-constant argument.\n"); + input_error("Failed to evaluate DPI function with non-constant argument.\n"); } newNode = dpi_call(rtype, fname, argtypes, args); @@ -3681,7 +3867,7 @@ skip_dynamic_range_lvalue_expansion:; if (current_scope.count(str) == 0) str = try_pop_module_prefix(); if (current_scope.count(str) == 0 || current_scope[str]->type != AST_FUNCTION) - log_file_error(filename, location.first_line, "Can't resolve function name `%s'.\n", str.c_str()); + input_error("Can't resolve function name `%s'.\n", str.c_str()); } if (type == AST_TCALL) @@ -3689,42 +3875,42 @@ skip_dynamic_range_lvalue_expansion:; if (str == "$finish" || str == "$stop") { if (!current_always || current_always->type != AST_INITIAL) - log_file_error(filename, location.first_line, "System task `%s' outside initial block is unsupported.\n", str.c_str()); + input_error("System task `%s' outside initial block is unsupported.\n", str.c_str()); - log_file_error(filename, location.first_line, "System task `%s' executed.\n", str.c_str()); + input_error("System task `%s' executed.\n", str.c_str()); } if (str == "\\$readmemh" || str == "\\$readmemb") { if (GetSize(children) < 2 || GetSize(children) > 4) - log_file_error(filename, location.first_line, "System function %s got %d arguments, expected 2-4.\n", + input_error("System function %s got %d arguments, expected 2-4.\n", RTLIL::unescape_id(str).c_str(), int(children.size())); AstNode *node_filename = children[0]->clone(); - while (node_filename->simplify(true, false, false, stage, width_hint, sign_hint, false)) { } + while (node_filename->simplify(true, false, stage, width_hint, sign_hint, false)) { } if (node_filename->type != AST_CONSTANT) - log_file_error(filename, location.first_line, "Failed to evaluate system function `%s' with non-constant 1st argument.\n", str.c_str()); + input_error("Failed to evaluate system function `%s' with non-constant 1st argument.\n", str.c_str()); AstNode *node_memory = children[1]->clone(); - while (node_memory->simplify(true, false, false, stage, width_hint, sign_hint, false)) { } + while (node_memory->simplify(true, false, stage, width_hint, sign_hint, false)) { } if (node_memory->type != AST_IDENTIFIER || node_memory->id2ast == nullptr || node_memory->id2ast->type != AST_MEMORY) - log_file_error(filename, location.first_line, "Failed to evaluate system function `%s' with non-memory 2nd argument.\n", str.c_str()); + input_error("Failed to evaluate system function `%s' with non-memory 2nd argument.\n", str.c_str()); int start_addr = -1, finish_addr = -1; if (GetSize(children) > 2) { AstNode *node_addr = children[2]->clone(); - while (node_addr->simplify(true, false, false, stage, width_hint, sign_hint, false)) { } + while (node_addr->simplify(true, false, stage, width_hint, sign_hint, false)) { } if (node_addr->type != AST_CONSTANT) - log_file_error(filename, location.first_line, "Failed to evaluate system function `%s' with non-constant 3rd argument.\n", str.c_str()); + input_error("Failed to evaluate system function `%s' with non-constant 3rd argument.\n", str.c_str()); start_addr = int(node_addr->asInt(false)); } if (GetSize(children) > 3) { AstNode *node_addr = children[3]->clone(); - while (node_addr->simplify(true, false, false, stage, width_hint, sign_hint, false)) { } + while (node_addr->simplify(true, false, stage, width_hint, sign_hint, false)) { } if (node_addr->type != AST_CONSTANT) - log_file_error(filename, location.first_line, "Failed to evaluate system function `%s' with non-constant 4th argument.\n", str.c_str()); + input_error("Failed to evaluate system function `%s' with non-constant 4th argument.\n", str.c_str()); finish_addr = int(node_addr->asInt(false)); } @@ -3754,7 +3940,7 @@ skip_dynamic_range_lvalue_expansion:; if (current_scope.count(str) == 0) str = try_pop_module_prefix(); if (current_scope.count(str) == 0 || current_scope[str]->type != AST_TASK) - log_file_error(filename, location.first_line, "Can't resolve task name `%s'.\n", str.c_str()); + input_error("Can't resolve task name `%s'.\n", str.c_str()); } @@ -3774,7 +3960,7 @@ skip_dynamic_range_lvalue_expansion:; bool require_const_eval = decl->has_const_only_constructs(); bool all_args_const = true; for (auto child : children) { - while (child->simplify(true, false, false, 1, -1, false, true)) { } + while (child->simplify(true, false, 1, -1, false, true)) { } if (child->type != AST_CONSTANT && child->type != AST_REALVALUE) all_args_const = false; } @@ -3791,9 +3977,9 @@ skip_dynamic_range_lvalue_expansion:; } if (in_param) - log_file_error(filename, location.first_line, "Non-constant function call in constant expression.\n"); + input_error("Non-constant function call in constant expression.\n"); if (require_const_eval) - log_file_error(filename, location.first_line, "Function %s can only be called with constant arguments.\n", str.c_str()); + input_error("Function %s can only be called with constant arguments.\n", str.c_str()); } size_t arg_count = 0; @@ -3818,7 +4004,7 @@ skip_dynamic_range_lvalue_expansion:; current_scope[wire->str] = wire; current_ast_mod->children.push_back(wire); - while (wire->simplify(true, false, false, 1, -1, false, false)) { } + while (wire->simplify(true, false, 1, -1, false, false)) { } AstNode *lvalue = new AstNode(AST_IDENTIFIER); lvalue->str = wire->str; @@ -3864,7 +4050,7 @@ skip_dynamic_range_lvalue_expansion:; wire->is_input = false; wire->is_output = false; current_ast_mod->children.push_back(wire); - while (wire->simplify(true, false, false, 1, -1, false, false)) { } + while (wire->simplify(true, false, 1, -1, false, false)) { } AstNode *wire_id = new AstNode(AST_IDENTIFIER); wire_id->str = wire->str; @@ -3907,14 +4093,14 @@ skip_dynamic_range_lvalue_expansion:; for (auto c : child->children) wire->children.push_back(c->clone()); } else if (!child->children.empty()) { - while (child->simplify(true, false, false, stage, -1, false, false)) { } + while (child->simplify(true, false, stage, -1, false, false)) { } if (GetSize(child->children) == GetSize(wire->children) - contains_value) { for (int i = 0; i < GetSize(child->children); i++) if (*child->children.at(i) != *wire->children.at(i + contains_value)) goto tcall_incompatible_wires; } else { tcall_incompatible_wires: - log_file_error(filename, location.first_line, "Incompatible re-declaration of wire %s.\n", child->str.c_str()); + input_error("Incompatible re-declaration of wire %s.\n", child->str.c_str()); } } } @@ -3935,7 +4121,7 @@ skip_dynamic_range_lvalue_expansion:; current_ast_mod->children.push_back(wire); } - while (wire->simplify(true, false, false, 1, -1, false, false)) { } + while (wire->simplify(true, false, 1, -1, false, false)) { } if ((child->is_input || child->is_output) && arg_count < children.size()) { @@ -3967,7 +4153,7 @@ skip_dynamic_range_lvalue_expansion:; } } // updates the sizing - while (wire->simplify(true, false, false, 1, -1, false, false)) { } + while (wire->simplify(true, false, 1, -1, false, false)) { } delete arg; continue; } @@ -4036,10 +4222,13 @@ replace_fcall_later:; tmp_range_left = (param_width + 2*param_offset) - children[0]->range_right - 1; tmp_range_right = (param_width + 2*param_offset) - children[0]->range_left - 1; } + AST::AstNode *member_node = get_struct_member(this); + int chunk_offset = member_node ? member_node->range_right : 0; + log_assert(!(chunk_offset && param_upto)); for (int i = tmp_range_right; i <= tmp_range_left; i++) { int index = i - param_offset; if (0 <= index && index < param_width) - data.push_back(current_scope[str]->children[0]->bits[index]); + data.push_back(current_scope[str]->children[0]->bits[chunk_offset + index]); else data.push_back(RTLIL::State::Sx); } @@ -4051,16 +4240,6 @@ replace_fcall_later:; if (current_scope[str]->children[0]->isConst()) newNode = current_scope[str]->children[0]->clone(); } - else if (at_zero && current_scope.count(str) > 0) { - AstNode *node = current_scope[str]; - if (node->type == AST_WIRE || node->type == AST_AUTOWIRE || node->type == AST_MEMORY) - newNode = mkconst_int(0, sign_hint, width_hint); - } - break; - case AST_MEMRD: - if (at_zero) { - newNode = mkconst_int(0, sign_hint, width_hint); - } break; case AST_BIT_NOT: if (children[0]->type == AST_CONSTANT) { @@ -4343,7 +4522,7 @@ AstNode *AstNode::readmem(bool is_readmemh, std::string mem_filename, AstNode *m yosys_input_files.insert(mem_filename); } if (f.fail() || GetSize(mem_filename) == 0) - log_file_error(filename, location.first_line, "Can not open file `%s` for %s.\n", mem_filename.c_str(), str.c_str()); + input_error("Can not open file `%s` for %s.\n", mem_filename.c_str(), str.c_str()); log_assert(GetSize(memory->children) == 2 && memory->children[1]->type == AST_RANGE && memory->children[1]->range_valid); int range_left = memory->children[1]->range_left, range_right = memory->children[1]->range_right; @@ -4389,7 +4568,7 @@ AstNode *AstNode::readmem(bool is_readmemh, std::string mem_filename, AstNode *m char *endptr; cursor = strtol(nptr, &endptr, 16); if (!*nptr || *endptr) - log_file_error(filename, location.first_line, "Can not parse address `%s` for %s.\n", nptr, str.c_str()); + input_error("Can not parse address `%s` for %s.\n", nptr, str.c_str()); continue; } @@ -4691,7 +4870,7 @@ void AstNode::mem2reg_as_needed_pass1(dict> &mem2reg if (type == AST_MEMORY && (get_bool_attribute(ID::mem2reg) || (flags & AstNode::MEM2REG_FL_ALL) || !(is_reg || is_logic))) mem2reg_candidates[this] |= AstNode::MEM2REG_FL_FORCED; - if (type == AST_MODULE && get_bool_attribute(ID::mem2reg)) + if ((type == AST_MODULE || type == AST_INTERFACE) && get_bool_attribute(ID::mem2reg)) children_flags |= AstNode::MEM2REG_FL_ALL; dict *proc_flags_p = NULL; @@ -4750,7 +4929,7 @@ bool AstNode::mem2reg_check(pool &mem2reg_set) return false; if (children.empty() || children[0]->type != AST_RANGE || GetSize(children[0]->children) != 1) - log_file_error(filename, location.first_line, "Invalid array access.\n"); + input_error("Invalid array access.\n"); return true; } @@ -4884,7 +5063,7 @@ bool AstNode::mem2reg_as_needed_pass2(pool &mem2reg_set, AstNode *mod, wire_addr->was_checked = true; wire_addr->attributes[ID::nosync] = AstNode::mkconst_int(1, false); mod->children.push_back(wire_addr); - while (wire_addr->simplify(true, false, false, 1, -1, false, false)) { } + while (wire_addr->simplify(true, false, 1, -1, false, false)) { } AstNode *wire_data = new AstNode(AST_WIRE, new AstNode(AST_RANGE, mkconst_int(mem_width-1, true), mkconst_int(0, true))); wire_data->str = id_data; @@ -4893,7 +5072,7 @@ bool AstNode::mem2reg_as_needed_pass2(pool &mem2reg_set, AstNode *mod, wire_data->is_signed = mem_signed; wire_data->attributes[ID::nosync] = AstNode::mkconst_int(1, false); mod->children.push_back(wire_data); - while (wire_data->simplify(true, false, false, 1, -1, false, false)) { } + while (wire_data->simplify(true, false, 1, -1, false, false)) { } log_assert(block != NULL); size_t assign_idx = 0; @@ -5001,7 +5180,7 @@ bool AstNode::mem2reg_as_needed_pass2(pool &mem2reg_set, AstNode *mod, if (block) wire_addr->attributes[ID::nosync] = AstNode::mkconst_int(1, false); mod->children.push_back(wire_addr); - while (wire_addr->simplify(true, false, false, 1, -1, false, false)) { } + while (wire_addr->simplify(true, false, 1, -1, false, false)) { } AstNode *wire_data = new AstNode(AST_WIRE, new AstNode(AST_RANGE, mkconst_int(mem_width-1, true), mkconst_int(0, true))); wire_data->str = id_data; @@ -5011,7 +5190,7 @@ bool AstNode::mem2reg_as_needed_pass2(pool &mem2reg_set, AstNode *mod, if (block) wire_data->attributes[ID::nosync] = AstNode::mkconst_int(1, false); mod->children.push_back(wire_data); - while (wire_data->simplify(true, false, false, 1, -1, false, false)) { } + while (wire_data->simplify(true, false, 1, -1, false, false)) { } AstNode *assign_addr = new AstNode(block ? AST_ASSIGN_EQ : AST_ASSIGN, new AstNode(AST_IDENTIFIER), children[0]->children[0]->clone()); assign_addr->children[0]->str = id_addr; @@ -5184,16 +5363,16 @@ bool AstNode::replace_variables(std::map &varia if (children.size() != 1 || children.at(0)->type != AST_RANGE) { if (!must_succeed) return false; - log_file_error(filename, location.first_line, "Memory access in constant function is not supported\n%s: ...called from here.\n", + input_error("Memory access in constant function is not supported\n%s: ...called from here.\n", fcall->loc_string().c_str()); } if (!children.at(0)->replace_variables(variables, fcall, must_succeed)) return false; - while (simplify(true, false, false, 1, -1, false, true)) { } + while (simplify(true, false, 1, -1, false, true)) { } if (!children.at(0)->range_valid) { if (!must_succeed) return false; - log_file_error(filename, location.first_line, "Non-constant range\n%s: ... called from here.\n", + input_error("Non-constant range\n%s: ... called from here.\n", fcall->loc_string().c_str()); } offset = min(children.at(0)->range_left, children.at(0)->range_right); @@ -5244,11 +5423,11 @@ AstNode *AstNode::eval_const_function(AstNode *fcall, bool must_succeed) if (stmt->type == AST_WIRE) { - while (stmt->simplify(true, false, false, 1, -1, false, true)) { } + while (stmt->simplify(true, false, 1, -1, false, true)) { } if (!stmt->range_valid) { if (!must_succeed) goto finished; - log_file_error(stmt->filename, stmt->location.first_line, "Can't determine size of variable %s\n%s: ... called from here.\n", + stmt->input_error("Can't determine size of variable %s\n%s: ... called from here.\n", stmt->str.c_str(), fcall->loc_string().c_str()); } AstNode::varinfo_t &variable = variables[stmt->str]; @@ -5256,7 +5435,7 @@ AstNode *AstNode::eval_const_function(AstNode *fcall, bool must_succeed) // if this variable has already been declared as an input, check the // sizes match if it already had an explicit size if (variable.arg && variable.explicitly_sized && variable.val.size() != width) { - log_file_error(filename, location.first_line, "Incompatible re-declaration of constant function wire %s.\n", stmt->str.c_str()); + input_error("Incompatible re-declaration of constant function wire %s.\n", stmt->str.c_str()); } variable.val = RTLIL::Const(RTLIL::State::Sx, width); variable.offset = stmt->range_swapped ? stmt->range_left : stmt->range_right; @@ -5288,7 +5467,7 @@ AstNode *AstNode::eval_const_function(AstNode *fcall, bool must_succeed) if (stmt->type == AST_LOCALPARAM) { - while (stmt->simplify(true, false, false, 1, -1, false, true)) { } + while (stmt->simplify(true, false, 1, -1, false, true)) { } current_scope[stmt->str] = stmt; @@ -5305,7 +5484,7 @@ AstNode *AstNode::eval_const_function(AstNode *fcall, bool must_succeed) goto finished; if (!stmt->children.at(1)->replace_variables(variables, fcall, must_succeed)) goto finished; - while (stmt->simplify(true, false, false, 1, -1, false, true)) { } + while (stmt->simplify(true, false, 1, -1, false, true)) { } if (stmt->type != AST_ASSIGN_EQ) continue; @@ -5313,21 +5492,21 @@ AstNode *AstNode::eval_const_function(AstNode *fcall, bool must_succeed) if (stmt->children.at(1)->type != AST_CONSTANT) { if (!must_succeed) goto finished; - log_file_error(stmt->filename, stmt->location.first_line, "Non-constant expression in constant function\n%s: ... called from here. X\n", + stmt->input_error("Non-constant expression in constant function\n%s: ... called from here. X\n", fcall->loc_string().c_str()); } if (stmt->children.at(0)->type != AST_IDENTIFIER) { if (!must_succeed) goto finished; - log_file_error(stmt->filename, stmt->location.first_line, "Unsupported composite left hand side in constant function\n%s: ... called from here.\n", + stmt->input_error("Unsupported composite left hand side in constant function\n%s: ... called from here.\n", fcall->loc_string().c_str()); } if (!variables.count(stmt->children.at(0)->str)) { if (!must_succeed) goto finished; - log_file_error(stmt->filename, stmt->location.first_line, "Assignment to non-local variable in constant function\n%s: ... called from here.\n", + stmt->input_error("Assignment to non-local variable in constant function\n%s: ... called from here.\n", fcall->loc_string().c_str()); } @@ -5338,8 +5517,7 @@ AstNode *AstNode::eval_const_function(AstNode *fcall, bool must_succeed) if (!range->range_valid) { if (!must_succeed) goto finished; - log_file_error(range->filename, range->location.first_line, "Non-constant range\n%s: ... called from here.\n", - fcall->loc_string().c_str()); + range->input_error("Non-constant range\n%s: ... called from here.\n", fcall->loc_string().c_str()); } int offset = min(range->range_left, range->range_right); int width = std::abs(range->range_left - range->range_right) + 1; @@ -5373,12 +5551,12 @@ AstNode *AstNode::eval_const_function(AstNode *fcall, bool must_succeed) AstNode *cond = stmt->children.at(0)->clone(); if (!cond->replace_variables(variables, fcall, must_succeed)) goto finished; - while (cond->simplify(true, false, false, 1, -1, false, true)) { } + while (cond->simplify(true, false, 1, -1, false, true)) { } if (cond->type != AST_CONSTANT) { if (!must_succeed) goto finished; - log_file_error(stmt->filename, stmt->location.first_line, "Non-constant expression in constant function\n%s: ... called from here.\n", + stmt->input_error("Non-constant expression in constant function\n%s: ... called from here.\n", fcall->loc_string().c_str()); } @@ -5398,12 +5576,12 @@ AstNode *AstNode::eval_const_function(AstNode *fcall, bool must_succeed) AstNode *num = stmt->children.at(0)->clone(); if (!num->replace_variables(variables, fcall, must_succeed)) goto finished; - while (num->simplify(true, false, false, 1, -1, false, true)) { } + while (num->simplify(true, false, 1, -1, false, true)) { } if (num->type != AST_CONSTANT) { if (!must_succeed) goto finished; - log_file_error(stmt->filename, stmt->location.first_line, "Non-constant expression in constant function\n%s: ... called from here.\n", + stmt->input_error("Non-constant expression in constant function\n%s: ... called from here.\n", fcall->loc_string().c_str()); } @@ -5421,7 +5599,7 @@ AstNode *AstNode::eval_const_function(AstNode *fcall, bool must_succeed) AstNode *expr = stmt->children.at(0)->clone(); if (!expr->replace_variables(variables, fcall, must_succeed)) goto finished; - while (expr->simplify(true, false, false, 1, -1, false, true)) { } + while (expr->simplify(true, false, 1, -1, false, true)) { } AstNode *sel_case = NULL; for (size_t i = 1; i < stmt->children.size(); i++) @@ -5441,12 +5619,12 @@ AstNode *AstNode::eval_const_function(AstNode *fcall, bool must_succeed) goto finished; cond = new AstNode(AST_EQ, expr->clone(), cond); - while (cond->simplify(true, false, false, 1, -1, false, true)) { } + while (cond->simplify(true, false, 1, -1, false, true)) { } if (cond->type != AST_CONSTANT) { if (!must_succeed) goto finished; - log_file_error(stmt->filename, stmt->location.first_line, "Non-constant expression in constant function\n%s: ... called from here.\n", + stmt->input_error("Non-constant expression in constant function\n%s: ... called from here.\n", fcall->loc_string().c_str()); } @@ -5482,7 +5660,7 @@ AstNode *AstNode::eval_const_function(AstNode *fcall, bool must_succeed) if (!must_succeed) goto finished; - log_file_error(stmt->filename, stmt->location.first_line, "Unsupported language construct in constant function\n%s: ... called from here.\n", + stmt->input_error("Unsupported language construct in constant function\n%s: ... called from here.\n", fcall->loc_string().c_str()); log_abort(); } diff --git a/yosys/frontends/verific/verific.cc b/yosys/frontends/verific/verific.cc index c1e9fc7d027..b0d789d8fa3 100644 --- a/yosys/frontends/verific/verific.cc +++ b/yosys/frontends/verific/verific.cc @@ -112,15 +112,26 @@ void msg_func(msg_type_t msg_type, const char *message_id, linefile_type linefil string message = linefile ? stringf("%s:%d: ", LineFile::GetFileName(linefile), LineFile::GetLineNo(linefile)) : ""; message += vstringf(msg, args); - if (msg_type == VERIFIC_ERROR || msg_type == VERIFIC_WARNING || msg_type == VERIFIC_PROGRAM_ERROR) - log_warning_noprefix("%s%s\n", message_prefix.c_str(), message.c_str()); - else - log("%s%s\n", message_prefix.c_str(), message.c_str()); - + if (log_verific_callback) { + string full_message = stringf("%s%s\n", message_prefix.c_str(), message.c_str()); + log_verific_callback(int(msg_type), message_id, LineFile::GetFileName(linefile), LineFile::GetLineNo(linefile), full_message.c_str()); + } else { + if (msg_type == VERIFIC_ERROR || msg_type == VERIFIC_WARNING || msg_type == VERIFIC_PROGRAM_ERROR) + log_warning_noprefix("%s%s\n", message_prefix.c_str(), message.c_str()); + else + log("%s%s\n", message_prefix.c_str(), message.c_str()); + } if (verific_error_msg.empty() && (msg_type == VERIFIC_ERROR || msg_type == VERIFIC_PROGRAM_ERROR)) verific_error_msg = message; } +void set_verific_logging(void (*cb)(int msg_type, const char *message_id, const char* file_path, unsigned int line_no, const char *msg)) +{ + Message::SetConsoleOutput(0); + Message::RegisterCallBackMsg(msg_func); + log_verific_callback = cb; +} + string get_full_netlist_name(Netlist *nl) { if (nl->NumOfRefs() == 1) { @@ -134,29 +145,29 @@ string get_full_netlist_name(Netlist *nl) class YosysStreamCallBackHandler : public VerificStreamCallBackHandler { public: - YosysStreamCallBackHandler() : VerificStreamCallBackHandler() { } - virtual ~YosysStreamCallBackHandler() { } - - virtual verific_stream *GetSysCallStream(const char *file_path) - { - if (!file_path) return nullptr; - - linefile_type src_loc = GetFromLocation(); - - char *this_file_name = nullptr; - if (src_loc && !FileSystem::IsAbsolutePath(file_path)) { - const char *src_file_name = LineFile::GetFileName(src_loc); - char *dir_name = FileSystem::DirectoryPath(src_file_name); - if (dir_name) { - this_file_name = Strings::save(dir_name, "/", file_path); - Strings::free(dir_name); - file_path = this_file_name; - } - } - verific_stream *strm = new verific_ifstream(file_path); - Strings::free(this_file_name); - return strm; - } + YosysStreamCallBackHandler() : VerificStreamCallBackHandler() { } + virtual ~YosysStreamCallBackHandler() { } + + virtual verific_stream *GetSysCallStream(const char *file_path) + { + if (!file_path) return nullptr; + + linefile_type src_loc = GetFromLocation(); + + char *this_file_name = nullptr; + if (src_loc && !FileSystem::IsAbsolutePath(file_path)) { + const char *src_file_name = LineFile::GetFileName(src_loc); + char *dir_name = FileSystem::DirectoryPath(src_file_name); + if (dir_name) { + this_file_name = Strings::save(dir_name, "/", file_path); + Strings::free(dir_name); + file_path = this_file_name; + } + } + verific_stream *strm = new verific_ifstream(file_path); + Strings::free(this_file_name); + return strm; + } }; YosysStreamCallBackHandler verific_read_cb; @@ -200,14 +211,6 @@ RTLIL::IdString VerificImporter::new_verific_id(Verific::DesignObj *obj) return s; } -static bool isNumber(const string& str) -{ - for (auto &c : str) { - if (std::isdigit(c) == 0) return false; - } - return true; -} - // When used as attributes or parameter values Verific constants come already processed. // - Real string values are already under quotes // - Numeric values with specified width are always converted to binary @@ -215,19 +218,37 @@ static bool isNumber(const string& str) // - There could be some internal values that are strings without quotes // so we check if value is all digits or not // -static const RTLIL::Const verific_const(const char *value) +// Note: For signed values, verific uses 'sb and decimal values can +// also be negative. +static const RTLIL::Const verific_const(const char *value, bool allow_string = true, bool output_signed = false) { + size_t found; + char *end; + int decimal; + bool is_signed = false; + RTLIL::Const c; std::string val = std::string(value); - if (val.size()>1 && val[0]=='\"' && val.back()=='\"') - return RTLIL::Const(val.substr(1,val.size()-2)); - else - if (val.find("'b") != std::string::npos) - return RTLIL::Const::from_string(val.substr(val.find("'b") + 2)); - else - if (isNumber(val)) - return RTLIL::Const(std::stoi(val),32); - else - return RTLIL::Const(val); + if (allow_string && val.size()>1 && val[0]=='\"' && val.back()=='\"') { + c = RTLIL::Const(val.substr(1,val.size()-2)); + } else if ((found = val.find("'sb")) != std::string::npos) { + is_signed = output_signed; + c = RTLIL::Const::from_string(val.substr(found + 3)); + } else if ((found = val.find("'b")) != std::string::npos) { + c = RTLIL::Const::from_string(val.substr(found + 2)); + } else if ((value[0] == '-' || (value[0] >= '0' && value[0] <= '9')) && + ((decimal = std::strtol(value, &end, 10)), !end[0])) { + is_signed = output_signed; + c = RTLIL::Const((int)decimal, 32); + } else if (allow_string) { + c = RTLIL::Const(val); + } else { + log_error("expected numeric constant but found '%s'", value); + } + + if (is_signed) + c.flags |= RTLIL::CONST_FLAG_SIGNED; + + return c; } void VerificImporter::import_attributes(dict &attributes, DesignObj *obj, Netlist *nl) @@ -263,21 +284,9 @@ void VerificImporter::import_attributes(dict &att const char *k, *v; FOREACH_MAP_ITEM(type_range->GetEnumIdMap(), mi, &k, &v) { if (nl->IsFromVerilog()) { - // Expect 'b - auto p = strchr(v, '\''); - if (p) { - if (*(p+1) != 'b') - p = nullptr; - else - for (auto q = p+2; *q != '\0'; q++) - if (*q != '0' && *q != '1' && *q != 'x' && *q != 'z') { - p = nullptr; - break; - } - } - if (p == nullptr) - log_error("Expected TypeRange value '%s' to be of form 'b.\n", v); - attributes.emplace(stringf("\\enum_value_%s", p+2), RTLIL::escape_id(k)); + auto const value = verific_const(v, false); + + attributes.emplace(stringf("\\enum_value_%s", value.as_string().c_str()), RTLIL::escape_id(k)); } #ifdef VERIFIC_VHDL_SUPPORT else if (nl->IsFromVhdl()) { @@ -1043,21 +1052,49 @@ bool VerificImporter::import_netlist_instance_cells(Instance *inst, RTLIL::IdStr sw->signal = sig_select; current_case->switches.push_back(sw); - int select_width = inst->InputSize(); - int data_width = inst->OutputSize(); - int select_num = inst->Input1Size() / inst->InputSize(); + unsigned select_width = inst->InputSize(); + unsigned data_width = inst->OutputSize(); + unsigned offset_data = 0; + unsigned offset_select = 0; - int offset_select = 0; - int offset_data = 0; + OperWideCaseSelector* selector = (OperWideCaseSelector*) inst->View(); - for (int i = 0; i < select_num; i++) { - RTLIL::CaseRule *cs = new RTLIL::CaseRule; - cs->compare.push_back(sig_select_values.extract(offset_select, select_width)); - cs->actions.push_back(SigSig(sig_out_val, sig_data_values.extract(offset_data, data_width))); - sw->cases.push_back(cs); - - offset_select += select_width; + for (unsigned i = 0 ; i < selector->GetNumBranches() ; ++i) { + + SigSig action(sig_out_val, sig_data_values.extract(offset_data, data_width)); offset_data += data_width; + + for (unsigned j = 0 ; j < selector->GetNumConditions(i) ; ++j) { + Array left_bound, right_bound ; + selector->GetCondition(i, j, &left_bound, &right_bound); + + SigSpec sel_left = sig_select_values.extract(offset_select, select_width); + offset_select += select_width; + + if (right_bound.Size()) { + SigSpec sel_right = sig_select_values.extract(offset_select, select_width); + offset_select += select_width; + + log_assert(sel_right.is_fully_const() && sel_right.is_fully_def()); + log_assert(sel_left.is_fully_const() && sel_right.is_fully_def()); + + int32_t left = sel_left.as_int(); + int32_t right = sel_right.as_int(); + int width = sel_left.size(); + + for (int32_t i = right; icompare.push_back(RTLIL::Const(i,width)); + cs->actions.push_back(action); + sw->cases.push_back(cs); + } + } + + RTLIL::CaseRule *cs = new RTLIL::CaseRule; + cs->compare.push_back(sel_left); + cs->actions.push_back(action); + sw->cases.push_back(cs); + } } RTLIL::CaseRule *cs_default = new RTLIL::CaseRule; cs_default->actions.push_back(SigSig(sig_out_val, sig_data_default)); @@ -1160,13 +1197,13 @@ static std::string sha1_if_contain_spaces(std::string str) void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::map &nl_todo, bool norename) { - std::string netlist_name = nl->GetAtt(" \\top") ? nl->CellBaseName() : nl->Owner()->Name(); + std::string netlist_name = nl->GetAtt(" \\top") || is_blackbox(nl) ? nl->CellBaseName() : nl->Owner()->Name(); std::string module_name = netlist_name; if (nl->IsOperator() || nl->IsPrimitive()) { module_name = "$verific$" + module_name; } else { - if (!norename && *nl->Name()) { + if (!norename && *nl->Name() && !is_blackbox(nl)) { module_name += "("; module_name += nl->Name(); module_name += ")"; @@ -1439,6 +1476,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma import_attributes(wire->attributes, net, nl); break; } + import_attributes(wire->attributes, netbus, nl); RTLIL::Const initval = Const(State::Sx, GetSize(wire)); bool initval_valid = false; @@ -1611,6 +1649,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma cell->parameters[ID::TRANSPARENT] = false; cell->parameters[ID::ABITS] = GetSize(addr); cell->parameters[ID::WIDTH] = GetSize(data); + import_attributes(cell->attributes, inst); cell->setPort(ID::CLK, RTLIL::State::Sx); cell->setPort(ID::EN, RTLIL::State::Sx); cell->setPort(ID::ADDR, addr); @@ -1640,6 +1679,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma cell->parameters[ID::PRIORITY] = 0; cell->parameters[ID::ABITS] = GetSize(addr); cell->parameters[ID::WIDTH] = GetSize(data); + import_attributes(cell->attributes, inst); cell->setPort(ID::EN, RTLIL::SigSpec(net_map_at(inst->GetControl())).repeat(GetSize(data))); cell->setPort(ID::CLK, RTLIL::State::S0); cell->setPort(ID::ADDR, addr); @@ -1853,14 +1893,14 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma } import_verific_cells: - std::string inst_type = inst->View()->Owner()->Name(); + std::string inst_type = is_blackbox(inst->View()) ? inst->View()->CellBaseName() : inst->View()->Owner()->Name(); nl_todo[inst_type] = inst->View(); if (inst->View()->IsOperator() || inst->View()->IsPrimitive()) { inst_type = "$verific$" + inst_type; } else { - if (*inst->View()->Name()) { + if (*inst->View()->Name() && !is_blackbox(inst->View())) { inst_type += "("; inst_type += inst->View()->Name(); inst_type += ")"; @@ -1878,6 +1918,14 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma if (verific_verbose) log(" ports in verific db:\n"); + const char *param_name ; + const char *param_value ; + if (is_blackbox(inst->View())) { + FOREACH_PARAMETER_OF_INST(inst, mi2, param_name, param_value) { + cell->setParam(RTLIL::escape_id(param_name), verific_const(param_value)); + } + } + FOREACH_PORTREF_OF_INST(inst, mi2, pr) { if (verific_verbose) log(" .%s(%s)\n", pr->GetPort()->Name(), pr->GetNet()->Name()); @@ -1967,7 +2015,10 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma initval[i] = State::Sx; } - if (initval.is_fully_undef()) + if (wire->port_input) { + wire->attributes[ID::defaultvalue] = Const(initval); + wire->attributes.erase(ID::init); + } else if (initval.is_fully_undef()) wire->attributes.erase(ID::init); } } @@ -1984,6 +2035,28 @@ VerificClocking::VerificClocking(VerificImporter *importer, Net *net, bool sva_a Instance *inst = net->Driver(); + // Detect condition expression in sva_at_only mode + if (sva_at_only) + do { + Instance *inst_mux = net->Driver(); + if (inst_mux->Type() != PRIM_MUX) + break; + + bool pwr1 = inst_mux->GetInput1()->IsPwr(); + bool pwr2 = inst_mux->GetInput2()->IsPwr(); + + if (!pwr1 && !pwr2) + break; + + Net *sva_net = pwr1 ? inst_mux->GetInput2() : inst_mux->GetInput1(); + if (!verific_is_sva_net(importer, sva_net)) + break; + + inst = sva_net->Driver(); + cond_net = inst_mux->GetControl(); + cond_pol = pwr1; + } while (0); + if (inst != nullptr && inst->Type() == PRIM_SVA_AT) { net = inst->GetInput1(); @@ -2419,6 +2492,7 @@ std::string verific_import(Design *design, const std::mapAddAtt(new Att(" \\top", NULL)); nl_todo.emplace(nl->CellBaseName(), nl); + cell_name = nl->Owner()->Name(); } + if (top.empty()) cell_name = top; delete netlists; @@ -2434,7 +2510,7 @@ std::string verific_import(Design *design, const std::mapChangePortBusStructures(1 /* hierarchical */); + nl.second->ChangePortBusStructures(1 /* hierarchical */); VerificExtNets worker; for (auto nl : nl_todo) @@ -2446,7 +2522,7 @@ std::string verific_import(Design *design, const std::mapfirst) == 0) { VerificImporter importer(false, false, false, false, false, false, false); nl_done[it->first] = it->second; - importer.import_netlist(design, nl, nl_todo, nl->Owner()->Name() == top); + importer.import_netlist(design, nl, nl_todo, nl->Owner()->Name() == cell_name); } nl_todo.erase(it); } @@ -2766,6 +2842,87 @@ struct VerificPass : public Pass { return filename; } +#ifdef VERIFIC_VHDL_SUPPORT + msg_type_t prev_1240 ; + msg_type_t prev_1241 ; + + void add_units_to_map(Map &map, std::string work, bool flag_lib) + { + MapIter mi ; + VhdlPrimaryUnit *unit ; + if (!flag_lib) return; + VhdlLibrary *vhdl_lib = vhdl_file::GetLibrary(work.c_str(), 1); + if (vhdl_lib) { + FOREACH_VHDL_PRIMARY_UNIT(vhdl_lib, mi, unit) { + if (!unit) continue; + map.Insert(unit,unit); + } + } + + prev_1240 = Message::GetMessageType("VHDL-1240") ; + prev_1241 = Message::GetMessageType("VHDL-1241") ; + Message::SetMessageType("VHDL-1240", VERIFIC_INFO); + Message::SetMessageType("VHDL-1241", VERIFIC_INFO); + } + + void set_units_to_blackbox(Map &map, std::string work, bool flag_lib) + { + MapIter mi ; + VhdlPrimaryUnit *unit ; + if (!flag_lib) return; + VhdlLibrary *vhdl_lib = vhdl_file::GetLibrary(work.c_str(), 1); + FOREACH_VHDL_PRIMARY_UNIT(vhdl_lib, mi, unit) { + if (!unit) continue; + if (!map.GetValue(unit)) { + unit->SetCompileAsBlackbox(); + } + } + Message::ClearMessageType("VHDL-1240") ; + Message::ClearMessageType("VHDL-1241") ; + if (Message::GetMessageType("VHDL-1240")!=prev_1240) + Message::SetMessageType("VHDL-1240", prev_1240); + if (Message::GetMessageType("VHDL-1241")!=prev_1241) + Message::SetMessageType("VHDL-1241", prev_1241); + + } +#endif + + msg_type_t prev_1063; + + void add_modules_to_map(Map &map, std::string work, bool flag_lib) + { + MapIter mi ; + VeriModule *veri_module ; + if (!flag_lib) return; + VeriLibrary *veri_lib = veri_file::GetLibrary(work.c_str(), 1); + if (veri_lib) { + FOREACH_VERILOG_MODULE_IN_LIBRARY(veri_lib, mi, veri_module) { + if (!veri_module) continue; + map.Insert(veri_module,veri_module); + } + } + + prev_1063 = Message::GetMessageType("VERI-1063") ; + Message::SetMessageType("VERI-1063", VERIFIC_INFO); + } + + void set_modules_to_blackbox(Map &map, std::string work, bool flag_lib) + { + MapIter mi ; + VeriModule *veri_module ; + if (!flag_lib) return; + VeriLibrary *veri_lib = veri_file::GetLibrary(work.c_str(), 1); + FOREACH_VERILOG_MODULE_IN_LIBRARY(veri_lib, mi, veri_module) { + if (!veri_module) continue; + if (!map.GetValue(veri_module)) { + veri_module->SetCompileAsBlackbox(); + } + } + Message::ClearMessageType("VERI-1063") ; + if (Message::GetMessageType("VERI-1063")!=prev_1063) + Message::SetMessageType("VERI-1063", prev_1063); + } + void execute(std::vector args, RTLIL::Design *design) override { static bool set_verific_global_flags = true; @@ -3062,15 +3219,27 @@ struct VerificPass : public Pass { for (auto &ext : verific_libexts) veri_file::AddLibExt(ext.c_str()); + bool flag_lib = false; while (argidx < GetSize(args)) { + if (args[argidx] == "-lib") { + flag_lib = true; + argidx++; + continue; + } + if (args[argidx].compare(0, 1, "-") == 0) { + cmd_error(args, argidx, "unknown option"); + goto check_error; + } std::string filename = frontent_rewrite(args, argidx, tmp_files); file_names.Insert(strdup(filename.c_str())); } + Map map(POINTER_HASH); + add_modules_to_map(map, work, flag_lib); if (!veri_file::AnalyzeMultipleFiles(&file_names, verilog_mode, work.c_str(), veri_file::MFCU)) { verific_error_msg.clear(); log_cmd_error("Reading Verilog/SystemVerilog sources failed.\n"); } - + set_modules_to_blackbox(map, work, flag_lib); verific_import_pending = true; goto check_error; } @@ -3078,11 +3247,22 @@ struct VerificPass : public Pass { #ifdef VERIFIC_VHDL_SUPPORT if (GetSize(args) > argidx && args[argidx] == "-vhdl87") { vhdl_file::SetDefaultLibraryPath((proc_share_dirname() + "verific/vhdl_vdbs_1987").c_str()); - argidx++; - while (argidx < GetSize(args)) { + bool flag_lib = false; + for (argidx++; argidx < GetSize(args); argidx++) { + if (args[argidx] == "-lib") { + flag_lib = true; + continue; + } + if (args[argidx].compare(0, 1, "-") == 0) { + cmd_error(args, argidx, "unknown option"); + goto check_error; + } + Map map(POINTER_HASH); + add_units_to_map(map, work, flag_lib); std::string filename = frontent_rewrite(args, argidx, tmp_files); if (!vhdl_file::Analyze(filename.c_str(), work.c_str(), vhdl_file::VHDL_87)) log_cmd_error("Reading `%s' in VHDL_87 mode failed.\n", filename.c_str()); + set_units_to_blackbox(map, work, flag_lib); } verific_import_pending = true; goto check_error; @@ -3090,11 +3270,22 @@ struct VerificPass : public Pass { if (GetSize(args) > argidx && args[argidx] == "-vhdl93") { vhdl_file::SetDefaultLibraryPath((proc_share_dirname() + "verific/vhdl_vdbs_1993").c_str()); - argidx++; - while (argidx < GetSize(args)) { + bool flag_lib = false; + for (argidx++; argidx < GetSize(args); argidx++) { + if (args[argidx] == "-lib") { + flag_lib = true; + continue; + } + if (args[argidx].compare(0, 1, "-") == 0) { + cmd_error(args, argidx, "unknown option"); + goto check_error; + } + Map map(POINTER_HASH); + add_units_to_map(map, work, flag_lib); std::string filename = frontent_rewrite(args, argidx, tmp_files); if (!vhdl_file::Analyze(filename.c_str(), work.c_str(), vhdl_file::VHDL_93)) log_cmd_error("Reading `%s' in VHDL_93 mode failed.\n", filename.c_str()); + set_units_to_blackbox(map, work, flag_lib); } verific_import_pending = true; goto check_error; @@ -3102,11 +3293,22 @@ struct VerificPass : public Pass { if (GetSize(args) > argidx && args[argidx] == "-vhdl2k") { vhdl_file::SetDefaultLibraryPath((proc_share_dirname() + "verific/vhdl_vdbs_1993").c_str()); - argidx++; - while (argidx < GetSize(args)) { + bool flag_lib = false; + for (argidx++; argidx < GetSize(args); argidx++) { + if (args[argidx] == "-lib") { + flag_lib = true; + continue; + } + if (args[argidx].compare(0, 1, "-") == 0) { + cmd_error(args, argidx, "unknown option"); + goto check_error; + } + Map map(POINTER_HASH); + add_units_to_map(map, work, flag_lib); std::string filename = frontent_rewrite(args, argidx, tmp_files); if (!vhdl_file::Analyze(filename.c_str(), work.c_str(), vhdl_file::VHDL_2K)) log_cmd_error("Reading `%s' in VHDL_2K mode failed.\n", filename.c_str()); + set_units_to_blackbox(map, work, flag_lib); } verific_import_pending = true; goto check_error; @@ -3114,11 +3316,22 @@ struct VerificPass : public Pass { if (GetSize(args) > argidx && (args[argidx] == "-vhdl2008" || args[argidx] == "-vhdl")) { vhdl_file::SetDefaultLibraryPath((proc_share_dirname() + "verific/vhdl_vdbs_2008").c_str()); - argidx++; - while (argidx < GetSize(args)) { + bool flag_lib = false; + for (argidx++; argidx < GetSize(args); argidx++) { + if (args[argidx] == "-lib") { + flag_lib = true; + continue; + } + if (args[argidx].compare(0, 1, "-") == 0) { + cmd_error(args, argidx, "unknown option"); + goto check_error; + } + Map map(POINTER_HASH); + add_units_to_map(map, work, flag_lib); std::string filename = frontent_rewrite(args, argidx, tmp_files); if (!vhdl_file::Analyze(filename.c_str(), work.c_str(), vhdl_file::VHDL_2008)) log_cmd_error("Reading `%s' in VHDL_2008 mode failed.\n", filename.c_str()); + set_units_to_blackbox(map, work, flag_lib); } verific_import_pending = true; goto check_error; @@ -3280,7 +3493,7 @@ struct VerificPass : public Pass { const std::string &key = args[++argidx]; const std::string &value = args[++argidx]; unsigned new_insertion = parameters.Insert(key.c_str(), value.c_str(), - 1 /* force_overwrite */); + 1 /* force_overwrite */); if (!new_insertion) log_warning_noprefix("-chparam %s already specified: overwriting.\n", key.c_str()); continue; @@ -3561,7 +3774,7 @@ struct VerificPass : public Pass { } #ifdef YOSYSHQ_VERIFIC_EXTENSIONS if (VerificExtensions::Execute(args, argidx, work, - [this](const std::vector &args, size_t argidx, std::string msg) + [this](const std::vector &args, size_t argidx, std::string msg) { cmd_error(args, argidx, msg); } )) { goto check_error; } diff --git a/yosys/frontends/verific/verificsva.cc b/yosys/frontends/verific/verificsva.cc index 986a9864326..222c7d2e917 100644 --- a/yosys/frontends/verific/verificsva.cc +++ b/yosys/frontends/verific/verificsva.cc @@ -1598,12 +1598,17 @@ struct VerificSvaImporter if (inst == nullptr) { - log_assert(trig == State::S1); - - if (accept_p != nullptr) - *accept_p = importer->net_map_at(net); - if (reject_p != nullptr) - *reject_p = module->Not(NEW_ID, importer->net_map_at(net)); + if (trig != State::S1) { + if (accept_p != nullptr) + *accept_p = module->And(NEW_ID, trig, importer->net_map_at(net)); + if (reject_p != nullptr) + *reject_p = module->And(NEW_ID, trig, module->Not(NEW_ID, importer->net_map_at(net))); + } else { + if (accept_p != nullptr) + *accept_p = importer->net_map_at(net); + if (reject_p != nullptr) + *reject_p = module->Not(NEW_ID, importer->net_map_at(net)); + } } else if (inst->Type() == PRIM_SVA_OVERLAPPED_IMPLICATION || diff --git a/yosys/frontends/verilog/verilog_lexer.l b/yosys/frontends/verilog/verilog_lexer.l index 958809319ef..24998666828 100644 --- a/yosys/frontends/verilog/verilog_lexer.l +++ b/yosys/frontends/verilog/verilog_lexer.l @@ -276,6 +276,7 @@ TIME_SCALE_SUFFIX [munpf]?s "byte" { SV_KEYWORD(TOK_BYTE); } "shortint" { SV_KEYWORD(TOK_SHORTINT); } "longint" { SV_KEYWORD(TOK_LONGINT); } +"void" { SV_KEYWORD(TOK_VOID); } "eventually" { if (formal_mode) return TOK_EVENTUALLY; SV_KEYWORD(TOK_EVENTUALLY); } "s_eventually" { if (formal_mode) return TOK_EVENTUALLY; SV_KEYWORD(TOK_EVENTUALLY); } diff --git a/yosys/frontends/verilog/verilog_parser.y b/yosys/frontends/verilog/verilog_parser.y index 87b50438a5f..98bdbf9e5c5 100644 --- a/yosys/frontends/verilog/verilog_parser.y +++ b/yosys/frontends/verilog/verilog_parser.y @@ -171,36 +171,6 @@ static bool isInLocalScope(const std::string *name) return (user_types.count(*name) > 0); } -static AstNode *getTypeDefinitionNode(std::string type_name) -{ - // check package types - if (type_name.find("::") != std::string::npos && pkg_user_types.count(type_name) > 0) { - auto typedef_node = pkg_user_types[type_name]; - log_assert(typedef_node->type == AST_TYPEDEF); - return typedef_node->children[0]; - } - - // check current scope then outer scopes for a name - for (auto it = user_type_stack.rbegin(); it != user_type_stack.rend(); ++it) { - if (it->count(type_name) > 0) { - // return the definition nodes from the typedef statement - auto typedef_node = (*it)[type_name]; - log_assert(typedef_node->type == AST_TYPEDEF); - return typedef_node->children[0]; - } - } - - // The lexer recognized the name as a TOK_USER_TYPE, but now we can't find it anymore? - log_error("typedef for user type `%s' not found", type_name.c_str()); -} - -static AstNode *copyTypeDefinition(std::string type_name) -{ - // return a copy of the template from a typedef definition - auto typedef_node = getTypeDefinitionNode(type_name); - return typedef_node->clone(); -} - static AstNode *makeRange(int msb = 31, int lsb = 0, bool isSigned = true) { auto range = new AstNode(AST_RANGE); @@ -372,7 +342,7 @@ static void rewriteGenForDeclInit(AstNode *loop) %token TOK_POS_INDEXED TOK_NEG_INDEXED TOK_PROPERTY TOK_ENUM TOK_TYPEDEF %token TOK_RAND TOK_CONST TOK_CHECKER TOK_ENDCHECKER TOK_EVENTUALLY %token TOK_INCREMENT TOK_DECREMENT TOK_UNIQUE TOK_UNIQUE0 TOK_PRIORITY -%token TOK_STRUCT TOK_PACKED TOK_UNSIGNED TOK_INT TOK_BYTE TOK_SHORTINT TOK_LONGINT TOK_UNION +%token TOK_STRUCT TOK_PACKED TOK_UNSIGNED TOK_INT TOK_BYTE TOK_SHORTINT TOK_LONGINT TOK_VOID TOK_UNION %token TOK_BIT_OR_ASSIGN TOK_BIT_AND_ASSIGN TOK_BIT_XOR_ASSIGN TOK_ADD_ASSIGN %token TOK_SUB_ASSIGN TOK_DIV_ASSIGN TOK_MOD_ASSIGN TOK_MUL_ASSIGN %token TOK_SHL_ASSIGN TOK_SHR_ASSIGN TOK_SSHL_ASSIGN TOK_SSHR_ASSIGN @@ -1020,6 +990,23 @@ task_func_decl: current_function_or_task = NULL; ast_stack.pop_back(); } | + attr TOK_FUNCTION opt_automatic TOK_VOID TOK_ID { + // The difference between void functions and tasks is that + // always_comb's implicit sensitivity list behaves as if functions were + // inlined, but ignores signals read only in tasks. This only matters + // for event based simulation, and for synthesis we can treat a void + // function like a task. + current_function_or_task = new AstNode(AST_TASK); + current_function_or_task->str = *$5; + append_attr(current_function_or_task, $1); + ast_stack.back()->children.push_back(current_function_or_task); + ast_stack.push_back(current_function_or_task); + current_function_or_task_port_id = 1; + delete $5; + } task_func_args_opt ';' task_func_body TOK_ENDFUNCTION { + current_function_or_task = NULL; + ast_stack.pop_back(); + } | attr TOK_FUNCTION opt_automatic func_return_type TOK_ID { current_function_or_task = new AstNode(AST_FUNCTION); current_function_or_task->str = *$5; @@ -1616,10 +1603,7 @@ param_implicit_type: param_signed param_range; param_type: param_integer_type | param_real | param_range_type | param_implicit_type | hierarchical_type_id { - astbuf1->is_custom_type = true; - astbuf1->children.push_back(new AstNode(AST_WIRETYPE)); - astbuf1->children.back()->str = *$1; - delete $1; + addWiretypeNode($1, astbuf1); }; param_decl: @@ -1792,7 +1776,12 @@ enum_decl: enum_type enum_var_list ';' { delete $1; } // struct or union ////////////////// -struct_decl: struct_type struct_var_list ';' { delete astbuf2; } +struct_decl: + attr struct_type { + append_attr($2, $1); + } struct_var_list ';' { + delete astbuf2; + } ; struct_type: struct_union { astbuf2 = $1; } struct_body { $$ = astbuf2; } @@ -1843,21 +1832,7 @@ struct_member_type: { astbuf1 = new AstNode(AST_STRUCT_ITEM); } member_type_toke member_type_token: member_type | hierarchical_type_id { - // use a clone of the typedef definition nodes - auto template_node = copyTypeDefinition(*$1); - delete $1; - switch (template_node->type) { - case AST_WIRE: - template_node->type = AST_STRUCT_ITEM; - break; - case AST_STRUCT: - case AST_UNION: - break; - default: - frontend_verilog_yyerror("Invalid type for struct member: %s", type2str(template_node->type).c_str()); - } - delete astbuf1; - astbuf1 = template_node; + addWiretypeNode($1, astbuf1); } | { delete astbuf1; diff --git a/yosys/kernel/cellaigs.cc b/yosys/kernel/cellaigs.cc index 292af3f51b0..332f821b76c 100644 --- a/yosys/kernel/cellaigs.cc +++ b/yosys/kernel/cellaigs.cc @@ -318,7 +318,7 @@ Aig::Aig(Cell *cell) goto optimize; } - if (cell->type.in(ID($mux), ID($_MUX_))) + if (cell->type.in(ID($mux), ID($_MUX_), ID($_NMUX_))) { int S = mk.inport(ID::S); for (int i = 0; i < GetSize(cell->getPort(ID::Y)); i++) { @@ -385,6 +385,26 @@ Aig::Aig(Cell *cell) goto optimize; } + if (cell->type.in({ID($lt), ID($gt), ID($le), ID($ge)})) + { + int width = std::max(GetSize(cell->getPort(ID::A)), + GetSize(cell->getPort(ID::B))) + 1; + vector A = mk.inport_vec(ID::A, width); + vector B = mk.inport_vec(ID::B, width); + + if (cell->type.in({ID($gt), ID($ge)})) + std::swap(A, B); + + int carry = mk.bool_node(!cell->type.in({ID($le), ID($ge)})); + for (auto &n : B) + n = mk.not_gate(n); + vector Y = mk.adder(A, B, carry); + mk.outport(Y.back(), ID::Y); + for (int i = 1; i < GetSize(cell->getPort(ID::Y)); i++) + mk.outport(mk.bool_node(false), ID::Y, i); + goto optimize; + } + if (cell->type == ID($alu)) { int width = GetSize(cell->getPort(ID::Y)); diff --git a/yosys/kernel/hashlib.h b/yosys/kernel/hashlib.h index af282715356..b3f99bf730f 100644 --- a/yosys/kernel/hashlib.h +++ b/yosys/kernel/hashlib.h @@ -84,6 +84,12 @@ template<> struct hash_ops : hash_int_ops return mkhash((unsigned int)(a), (unsigned int)(a >> 32)); } }; +template<> struct hash_ops : hash_int_ops +{ + static inline unsigned int hash(uint32_t a) { + return a; + } +}; template<> struct hash_ops { static inline bool cmp(const std::string &a, const std::string &b) { diff --git a/yosys/kernel/log.cc b/yosys/kernel/log.cc index 75a1ffb4559..73e7f16eca5 100644 --- a/yosys/kernel/log.cc +++ b/yosys/kernel/log.cc @@ -59,6 +59,7 @@ bool log_quiet_warnings = false; int log_verbose_level; string log_last_error; void (*log_error_atexit)() = NULL; +void (*log_verific_callback)(int msg_type, const char *message_id, const char* file_path, unsigned int line_no, const char *msg) = NULL; int log_make_debug = 0; int log_force_debug = 0; @@ -146,6 +147,12 @@ void logv(const char *format, va_list ap) if (format[0] && format[strlen(format)-1] == '\n') next_print_log = true; + // Special case to detect newlines in Python log output, since + // the binding always calls `log("%s", payload)` and the newline + // is then in the first formatted argument + if (!strcmp(format, "%s") && str.back() == '\n') + next_print_log = true; + for (auto f : log_files) fputs(time_str.c_str(), f); @@ -377,14 +384,20 @@ void logv_error(const char *format, va_list ap) logv_error_with_prefix("ERROR: ", format, ap); } +void logv_file_error(const string &filename, int lineno, + const char *format, va_list ap) +{ + std::string prefix = stringf("%s:%d: ERROR: ", + filename.c_str(), lineno); + logv_error_with_prefix(prefix.c_str(), format, ap); +} + void log_file_error(const string &filename, int lineno, const char *format, ...) { va_list ap; va_start(ap, format); - std::string prefix = stringf("%s:%d: ERROR: ", - filename.c_str(), lineno); - logv_error_with_prefix(prefix.c_str(), format, ap); + logv_file_error(filename, lineno, format, ap); } void log(const char *format, ...) diff --git a/yosys/kernel/log.h b/yosys/kernel/log.h index 3a6ec87587a..78a2e434c7a 100644 --- a/yosys/kernel/log.h +++ b/yosys/kernel/log.h @@ -124,12 +124,16 @@ void logv_header(RTLIL::Design *design, const char *format, va_list ap); void logv_warning(const char *format, va_list ap); void logv_warning_noprefix(const char *format, va_list ap); [[noreturn]] void logv_error(const char *format, va_list ap); +[[noreturn]] void logv_file_error(const string &filename, int lineno, const char *format, va_list ap); void log(const char *format, ...) YS_ATTRIBUTE(format(printf, 1, 2)); void log_header(RTLIL::Design *design, const char *format, ...) YS_ATTRIBUTE(format(printf, 2, 3)); void log_warning(const char *format, ...) YS_ATTRIBUTE(format(printf, 1, 2)); void log_experimental(const char *format, ...) YS_ATTRIBUTE(format(printf, 1, 2)); +void set_verific_logging(void (*cb)(int msg_type, const char *message_id, const char* file_path, unsigned int line_no, const char *msg)); +extern void (*log_verific_callback)(int msg_type, const char *message_id, const char* file_path, unsigned int line_no, const char *msg); + // Log with filename to report a problem in a source file. void log_file_warning(const std::string &filename, int lineno, const char *format, ...) YS_ATTRIBUTE(format(printf, 3, 4)); void log_file_info(const std::string &filename, int lineno, const char *format, ...) YS_ATTRIBUTE(format(printf, 3, 4)); diff --git a/yosys/kernel/mem.cc b/yosys/kernel/mem.cc index ed01a086713..628f6210499 100644 --- a/yosys/kernel/mem.cc +++ b/yosys/kernel/mem.cc @@ -451,6 +451,7 @@ void Mem::check() { log_assert(GetSize(port.en) == 1); log_assert(GetSize(port.arst) == 1); log_assert(GetSize(port.srst) == 1); + log_assert(GetSize(port.addr) >= port.wide_log2); log_assert(GetSize(port.data) == (width << port.wide_log2)); log_assert(GetSize(port.init_value) == (width << port.wide_log2)); log_assert(GetSize(port.arst_value) == (width << port.wide_log2)); @@ -484,6 +485,7 @@ void Mem::check() { log_assert(GetSize(port.clk) == 1); log_assert(GetSize(port.en) == (width << port.wide_log2)); log_assert(GetSize(port.data) == (width << port.wide_log2)); + log_assert(GetSize(port.addr) >= port.wide_log2); for (int j = 0; j < port.wide_log2; j++) { log_assert(port.addr[j] == State::S0); } diff --git a/yosys/kernel/rtlil.cc b/yosys/kernel/rtlil.cc index 7f3508b2f49..7011429ff5a 100644 --- a/yosys/kernel/rtlil.cc +++ b/yosys/kernel/rtlil.cc @@ -30,6 +30,7 @@ YOSYS_NAMESPACE_BEGIN +bool RTLIL::IdString::destruct_guard_ok = false; RTLIL::IdString::destruct_guard_t RTLIL::IdString::destruct_guard; std::vector RTLIL::IdString::global_id_storage_; dict RTLIL::IdString::global_id_index_; diff --git a/yosys/kernel/rtlil.h b/yosys/kernel/rtlil.h index 7c7669caa88..a69ce480baf 100644 --- a/yosys/kernel/rtlil.h +++ b/yosys/kernel/rtlil.h @@ -85,10 +85,10 @@ namespace RTLIL // the global id string cache + static bool destruct_guard_ok; // POD, will be initialized to zero static struct destruct_guard_t { - bool ok; // POD, will be initialized to zero - destruct_guard_t() { ok = true; } - ~destruct_guard_t() { ok = false; } + destruct_guard_t() { destruct_guard_ok = true; } + ~destruct_guard_t() { destruct_guard_ok = false; } } destruct_guard; static std::vector global_id_storage_; @@ -147,7 +147,7 @@ namespace RTLIL static int get_reference(const char *p) { - log_assert(destruct_guard.ok); + log_assert(destruct_guard_ok); if (!p[0]) return 0; @@ -225,7 +225,7 @@ namespace RTLIL { // put_reference() may be called from destructors after the destructor of // global_refcount_storage_ has been run. in this case we simply do nothing. - if (!destruct_guard.ok || !idx) + if (!destruct_guard_ok || !idx) return; #ifdef YOSYS_XTRACE_GET_PUT @@ -443,13 +443,13 @@ namespace RTLIL static inline std::string encode_filename(const std::string &filename) { std::stringstream val; - if (!std::any_of(filename.begin(), filename.end(), [](char c) { - return static_cast(c) < 33 || static_cast(c) > 126; + if (!std::any_of(filename.begin(), filename.end(), [](char c) { + return static_cast(c) < 33 || static_cast(c) > 126; })) return filename; for (unsigned char const c : filename) { if (c < 33 || c > 126) val << stringf("$%02x", c); - else + else val << c; } return val.str(); diff --git a/yosys/kernel/yw.cc b/yosys/kernel/yw.cc index 73e7710db43..ef043fb0d0f 100644 --- a/yosys/kernel/yw.cc +++ b/yosys/kernel/yw.cc @@ -190,8 +190,6 @@ RTLIL::Const ReadWitness::get_bits(int t, int bits_offset, int width) const int read_begin = GetSize(bits) - 1 - bits_offset; int read_end = max(-1, read_begin - width); - min(width, GetSize(bits) - bits_offset); - for (int i = read_begin, j = 0; i > read_end; i--, j++) { RTLIL::State bit = State::Sa; switch (bits[i]) { diff --git a/yosys/misc/py_wrap_generator.py b/yosys/misc/py_wrap_generator.py index 4d9a6011326..7fe78e03a58 100644 --- a/yosys/misc/py_wrap_generator.py +++ b/yosys/misc/py_wrap_generator.py @@ -178,6 +178,8 @@ def from_string(str_def, containing_file, line_number): t.cont = None t.attr_type = attr_types.default if str_def.find("<") != -1:# and str_def.find("<") < str_def.find(" "): + str_def = str_def.replace("const ", "") + candidate = WContainer.from_string(str_def, containing_file, line_number) if candidate == None: return None @@ -203,8 +205,12 @@ def from_string(str_def, containing_file, line_number): prefix = "" + if str.startswith(str_def, "const "): + if "char_p" in str_def: + prefix = "const " + str_def = str_def[6:] if str.startswith(str_def, "unsigned "): - prefix = "unsigned " + prefix = "unsigned " + prefix str_def = str_def[9:] while str.startswith(str_def, "long "): prefix= "long " + prefix @@ -1285,7 +1291,7 @@ def from_string(str_def, containing_file, class_, line_number, namespace): prefix = "" i = 0 for part in parts: - if part in ["unsigned", "long", "short"]: + if part in ["unsigned", "long", "short", "const"]: prefix += part + " " i += 1 else: @@ -1361,10 +1367,17 @@ def from_string(str_def, containing_file, class_, line_number, namespace): func.args.append(parsed) return func + @property + def mangled_name(self): + mangled_typename = lambda code: code.replace("::", "_").replace("<","_").replace(">","_") \ + .replace(" ","").replace("*","").replace(",","") + + return self.name + "".join( + f"__{mangled_typename(arg.wtype.gen_text_cpp())}" for arg in self.args + ) + def gen_alias(self): - self.alias = self.name - for arg in self.args: - self.alias += "__" + arg.wtype.gen_text_cpp().replace("::", "_").replace("<","_").replace(">","_").replace(" ","").replace("*","").replace(",","") + self.alias = self.mangled_name def gen_decl(self): if self.duplicate: @@ -2190,12 +2203,15 @@ def clean_duplicates(): for fun in class_.found_funs: if fun.gen_decl_hash_py() in known_decls: debug("Multiple declarations of " + fun.gen_decl_hash_py(),3) + other = known_decls[fun.gen_decl_hash_py()] - other.gen_alias() - fun.gen_alias() - if fun.gen_decl_hash_py() == other.gen_decl_hash_py(): + if fun.mangled_name == other.mangled_name: fun.duplicate = True debug("Disabled \"" + fun.gen_decl_hash_py() + "\"", 3) + continue + + other.gen_alias() + fun.gen_alias() else: known_decls[fun.gen_decl_hash_py()] = fun known_decls = [] diff --git a/yosys/passes/cmds/check.cc b/yosys/passes/cmds/check.cc index ee0f0a58fae..d1c83f04d88 100644 --- a/yosys/passes/cmds/check.cc +++ b/yosys/passes/cmds/check.cc @@ -112,11 +112,10 @@ struct CheckPass : public Pass { for (size_t i = 0; i < all_cases.size(); i++) { for (auto action : all_cases[i]->actions) { for (auto bit : sigmap(action.first)) - if (bit.wire) { - wire_drivers[bit].push_back( - stringf("action %s <= %s (case rule) in process %s", - log_signal(action.first), log_signal(action.second), log_id(proc_it.first))); - } + wire_drivers[bit].push_back( + stringf("action %s <= %s (case rule) in process %s", + log_signal(action.first), log_signal(action.second), log_id(proc_it.first))); + for (auto bit : sigmap(action.second)) if (bit.wire) used_wires.insert(bit); } @@ -134,10 +133,9 @@ struct CheckPass : public Pass { if (bit.wire) used_wires.insert(bit); for (auto action : sync->actions) { for (auto bit : sigmap(action.first)) - if (bit.wire) - wire_drivers[bit].push_back( - stringf("action %s <= %s (sync rule) in process %s", - log_signal(action.first), log_signal(action.second), log_id(proc_it.first))); + wire_drivers[bit].push_back( + stringf("action %s <= %s (sync rule) in process %s", + log_signal(action.first), log_signal(action.second), log_id(proc_it.first))); for (auto bit : sigmap(action.second)) if (bit.wire) used_wires.insert(bit); } @@ -176,7 +174,8 @@ struct CheckPass : public Pass { if (logic_cell) topo.edge(stringf("cell %s (%s)", log_id(cell), log_id(cell->type)), stringf("wire %s", log_signal(sig[i]))); - if (sig[i].wire) + + if (sig[i].wire || !cell->input(conn.first)) wire_drivers[sig[i]].push_back(stringf("port %s[%d] of cell %s (%s)", log_id(conn.first), i, log_id(cell), log_id(cell->type))); } @@ -192,7 +191,8 @@ struct CheckPass : public Pass { if (wire->port_input) { SigSpec sig = sigmap(wire); for (int i = 0; i < GetSize(sig); i++) - wire_drivers[sig[i]].push_back(stringf("module input %s[%d]", log_id(wire), i)); + if (sig[i].wire || !wire->port_output) + wire_drivers[sig[i]].push_back(stringf("module input %s[%d]", log_id(wire), i)); } if (wire->port_output) for (auto bit : sigmap(wire)) @@ -212,6 +212,15 @@ struct CheckPass : public Pass { } } + for (auto state : {State::S0, State::S1, State::Sx}) + if (wire_drivers.count(state)) { + string message = stringf("Drivers conflicting with a constant %s driver:\n", log_signal(state)); + for (auto str : wire_drivers[state]) + message += stringf(" %s\n", str.c_str()); + log_warning("%s", message.c_str()); + counter++; + } + for (auto it : wire_drivers) if (wire_drivers_count[it.first] > 1) { string message = stringf("multiple conflicting drivers for %s.%s:\n", log_id(module), log_signal(it.first)); diff --git a/yosys/passes/cmds/chformal.cc b/yosys/passes/cmds/chformal.cc index 66044b161c9..da97ff71d69 100644 --- a/yosys/passes/cmds/chformal.cc +++ b/yosys/passes/cmds/chformal.cc @@ -55,6 +55,14 @@ struct ChformalPass : public Pass { log(" -skip \n"); log(" ignore activation of the constraint in the first clock cycles\n"); log("\n"); + log(" -coverenable\n"); + log(" add cover statements for the enable signals of the constraints\n"); + log("\n"); +#ifdef YOSYS_ENABLE_VERIFIC + log(" Note: For the Verific frontend it is currently not guaranteed that a\n"); + log(" reachable SVA statement corresponds to an active enable signal.\n"); + log("\n"); +#endif log(" -assert2assume\n"); log(" -assume2assert\n"); log(" -live2fair\n"); @@ -114,6 +122,10 @@ struct ChformalPass : public Pass { mode_arg = atoi(args[++argidx].c_str()); continue; } + if (mode == 0 && args[argidx] == "-coverenable") { + mode = 'p'; + continue; + } if ((mode == 0 || mode == 'c') && args[argidx] == "-assert2assume") { assert2assume = true; mode = 'c'; @@ -263,6 +275,13 @@ struct ChformalPass : public Pass { cell->setPort(ID::EN, module->LogicAnd(NEW_ID, en, cell->getPort(ID::EN))); } else + if (mode =='p') + { + for (auto cell : constr_cells) + module->addCover(NEW_ID_SUFFIX("coverenable"), + cell->getPort(ID::EN), State::S1, cell->get_src_attribute()); + } + else if (mode == 'c') { for (auto cell : constr_cells) diff --git a/yosys/passes/cmds/plugin.cc b/yosys/passes/cmds/plugin.cc index 3a1ae2850b5..08b4aa8c4ee 100644 --- a/yosys/passes/cmds/plugin.cc +++ b/yosys/passes/cmds/plugin.cc @@ -41,50 +41,70 @@ std::map loaded_plugin_aliases; void load_plugin(std::string filename, std::vector aliases) { std::string orig_filename = filename; + rewrite_filename(filename); - if (filename.find('/') == std::string::npos) + // Would something like this better be put in `rewrite_filename`? + if (filename.find("/") == std::string::npos) filename = "./" + filename; + #ifdef WITH_PYTHON - if (!loaded_plugins.count(filename) && !loaded_python_plugins.count(filename)) { + const bool is_loaded = loaded_plugins.count(orig_filename) && loaded_python_plugins.count(orig_filename); #else - if (!loaded_plugins.count(filename)) { + const bool is_loaded = loaded_plugins.count(orig_filename); #endif - #ifdef WITH_PYTHON - - boost::filesystem::path full_path(filename); - - if(strcmp(full_path.extension().c_str(), ".py") == 0) + if (!is_loaded) { + // Check if we're loading a python script + if(filename.find(".py") != std::string::npos) { - std::string path(full_path.parent_path().c_str()); - filename = full_path.filename().c_str(); - filename = filename.substr(0,filename.size()-3); - PyRun_SimpleString(("sys.path.insert(0,\""+path+"\")").c_str()); - PyErr_Print(); - PyObject *module_p = PyImport_ImportModule(filename.c_str()); - if(module_p == NULL) - { + #ifdef WITH_PYTHON + boost::filesystem::path full_path(filename); + std::string path(full_path.parent_path().c_str()); + filename = full_path.filename().c_str(); + filename = filename.substr(0,filename.size()-3); + PyRun_SimpleString(("sys.path.insert(0,\""+path+"\")").c_str()); PyErr_Print(); - log_cmd_error("Can't load python module `%s'\n", full_path.filename().c_str()); - return; - } - loaded_python_plugins[orig_filename] = module_p; - Pass::init_register(); + PyObject *module_p = PyImport_ImportModule(filename.c_str()); + if(module_p == NULL) + { + PyErr_Print(); + log_cmd_error("Can't load python module `%s'\n", full_path.filename().c_str()); + return; + } + loaded_python_plugins[orig_filename] = module_p; + Pass::init_register(); + #else + log_error( + "\n This version of Yosys cannot load python plugins.\n" + " Ensure Yosys is built with Python support to do so.\n" + ); + #endif } else { - #endif + // Otherwise we assume it's a native plugin + + void *hdl = dlopen(filename.c_str(), RTLD_LAZY|RTLD_LOCAL); + + // We were unable to open the file, try to do so from the plugin directory + if (hdl == NULL && orig_filename.find('/') == std::string::npos) { + hdl = dlopen([orig_filename]() { + std::string new_path = proc_share_dirname() + "plugins/" + orig_filename; - void *hdl = dlopen(filename.c_str(), RTLD_LAZY|RTLD_LOCAL); - if (hdl == NULL && orig_filename.find('/') == std::string::npos) - hdl = dlopen((proc_share_dirname() + "plugins/" + orig_filename + ".so").c_str(), RTLD_LAZY|RTLD_LOCAL); - if (hdl == NULL) - log_cmd_error("Can't load module `%s': %s\n", filename.c_str(), dlerror()); - loaded_plugins[orig_filename] = hdl; - Pass::init_register(); + // Check if we need to append .so + if (new_path.find(".so") == std::string::npos) + new_path.append(".so"); + + return new_path; + }().c_str(), RTLD_LAZY|RTLD_LOCAL); + } + + if (hdl == NULL) + log_cmd_error("Can't load module `%s': %s\n", filename.c_str(), dlerror()); + + loaded_plugins[orig_filename] = hdl; + Pass::init_register(); - #ifdef WITH_PYTHON } - #endif } for (auto &alias : aliases) @@ -182,4 +202,3 @@ struct PluginPass : public Pass { } PluginPass; YOSYS_NAMESPACE_END - diff --git a/yosys/passes/cmds/rename.cc b/yosys/passes/cmds/rename.cc index 45576c91c2b..da4ba2f17e9 100644 --- a/yosys/passes/cmds/rename.cc +++ b/yosys/passes/cmds/rename.cc @@ -116,6 +116,8 @@ static bool rename_witness(RTLIL::Design *design, dict &ca } cache.emplace(module, -1); + std::vector> renames; + bool has_witness_signals = false; for (auto cell : module->cells()) { @@ -130,13 +132,19 @@ static bool rename_witness(RTLIL::Design *design, dict &ca c = '_'; auto new_id = module->uniquify("\\_witness_." + name); cell->set_hdlname_attribute({ "_witness_", strstr(new_id.c_str(), ".") + 1 }); - module->rename(cell, new_id); + renames.emplace_back(cell, new_id); } + break; } if (cell->type.in(ID($anyconst), ID($anyseq), ID($anyinit), ID($allconst), ID($allseq))) { has_witness_signals = true; - auto QY = cell->type == ID($anyinit) ? ID::Q : ID::Y; + IdString QY; + bool clk2fflogic = false; + if (cell->type == ID($anyinit)) + QY = (clk2fflogic = cell->get_bool_attribute(ID(clk2fflogic))) ? ID::D : ID::Q; + else + QY = ID::Y; auto sig_out = cell->getPort(QY); for (auto chunk : sig_out.chunks()) { @@ -148,13 +156,19 @@ static bool rename_witness(RTLIL::Design *design, dict &ca auto new_id = module->uniquify("\\_witness_." + name); auto new_wire = module->addWire(new_id, GetSize(sig_out)); new_wire->set_hdlname_attribute({ "_witness_", strstr(new_id.c_str(), ".") + 1 }); - module->connect({sig_out, new_wire}); + if (clk2fflogic) + module->connect({new_wire, sig_out}); + else + module->connect({sig_out, new_wire}); cell->setPort(QY, new_wire); break; } } } } + for (auto rename : renames) { + module->rename(rename.first, rename.second); + } cache[module] = has_witness_signals; return has_witness_signals; diff --git a/yosys/passes/cmds/show.cc b/yosys/passes/cmds/show.cc index dd7de827331..0dc5c452c09 100644 --- a/yosys/passes/cmds/show.cc +++ b/yosys/passes/cmds/show.cc @@ -84,7 +84,7 @@ struct ShowWorker std::string nextColor() { if (currentColor == 0) - return "color=\"black\""; + return "color=\"black\", fontcolor=\"black\""; return stringf("colorscheme=\"dark28\", color=\"%d\", fontcolor=\"%d\"", currentColor%8+1, currentColor%8+1); } @@ -97,19 +97,16 @@ struct ShowWorker std::string nextColor(RTLIL::SigSpec sig, std::string defaultColor) { - sig.sort_and_unify(); - for (auto &c : sig.chunks()) { - if (c.wire != nullptr) - for (auto &s : color_selections) - if (s.second.selected_members.count(module->name) > 0 && s.second.selected_members.at(module->name).count(c.wire->name) > 0) - return stringf("color=\"%s\"", s.first.c_str()); - } + std::string color = findColor(sig); + if (!color.empty()) return color; return defaultColor; } std::string nextColor(const RTLIL::SigSig &conn, std::string defaultColor) { - return nextColor(conn.first, nextColor(conn.second, defaultColor)); + std::string color = findColor(conn); + if (!color.empty()) return color; + return defaultColor; } std::string nextColor(const RTLIL::SigSpec &sig) @@ -131,12 +128,28 @@ struct ShowWorker return stringf("style=\"setlinewidth(3)\", label=\"<%d>\"", bits); } - const char *findColor(std::string member_name) + std::string findColor(RTLIL::SigSpec sig) + { + sig.sort_and_unify(); + for (auto &c : sig.chunks()) { + if (c.wire != nullptr) + return findColor(c.wire->name); + } + return ""; + } + + std::string findColor(const RTLIL::SigSig &conn) + { + std::string firstColor = findColor(conn.first); + if (findColor(conn.second) == firstColor) return firstColor; + return ""; + } + + std::string findColor(IdString member_name) { for (auto &s : color_selections) if (s.second.selected_member(module->name, member_name)) { - dot_escape_store.push_back(stringf(", color=\"%s\"", s.first.c_str())); - return dot_escape_store.back().c_str(); + return stringf("color=\"%s\", fontcolor=\"%s\"", s.first.c_str(), s.first.c_str()); } RTLIL::Const colorattr_value; @@ -155,8 +168,7 @@ struct ShowWorker colorattr_cache[colorattr_value] = (next_id % 8) + 1; } - dot_escape_store.push_back(stringf(", colorscheme=\"dark28\", color=\"%d\", fontcolor=\"%d\"", colorattr_cache.at(colorattr_value), colorattr_cache.at(colorattr_value))); - return dot_escape_store.back().c_str(); + return stringf("colorscheme=\"dark28\", color=\"%d\", fontcolor=\"%d\"", colorattr_cache.at(colorattr_value), colorattr_cache.at(colorattr_value)); } const char *findLabel(std::string member_name) @@ -189,6 +201,12 @@ struct ShowWorker if (id[0] == '\\') id = id.substr(1); + // TODO: optionally include autoname + print correspondence in case of ambiguity + size_t max_label_len = abbreviateIds ? 256 : 16384; + if (id.size() > max_label_len) { + id = id.substr(0,max_label_len-3) + "..."; + } + std::string str; for (char ch : id) { if (ch == '\\') { @@ -196,7 +214,7 @@ struct ShowWorker str += "╲"; continue; } - if (ch == '"') + if (ch == '"' || ch == '<' || ch == '>') str += "\\"; str += ch; } @@ -317,7 +335,7 @@ struct ShowWorker } code += stringf("x%d [ shape=record, style=rounded, label=\"", dot_idx) \ - + join_label_pieces(label_pieces) + "\" ];\n"; + + join_label_pieces(label_pieces) + stringf("\", %s ];\n", nextColor(sig).c_str()); if (!port.empty()) { currentColor = xorshift32(currentColor); @@ -414,9 +432,9 @@ struct ShowWorker if (wire->port_input || wire->port_output) shape = "octagon"; if (wire->name.isPublic()) { - fprintf(f, "n%d [ shape=%s, label=\"%s\", %s, fontcolor=\"black\" ];\n", + fprintf(f, "n%d [ shape=%s, label=\"%s\", %s ];\n", id2num(wire->name), shape, findLabel(wire->name.str()), - nextColor(RTLIL::SigSpec(wire), "color=\"black\"").c_str()); + nextColor(RTLIL::SigSpec(wire), "color=\"black\", fontcolor=\"black\"").c_str()); if (wire->port_input) all_sources.insert(stringf("n%d", id2num(wire->name))); else if (wire->port_output) @@ -481,11 +499,11 @@ struct ShowWorker #ifdef CLUSTER_CELLS_AND_PORTBOXES if (!code.empty()) fprintf(f, "subgraph cluster_c%d {\nc%d [ shape=record, label=\"%s\"%s ];\n%s}\n", - id2num(cell->name), id2num(cell->name), label_string.c_str(), findColor(cell->name), code.c_str()); + id2num(cell->name), id2num(cell->name), label_string.c_str(), color.c_str(), code.c_str()); else #endif - fprintf(f, "c%d [ shape=record, label=\"%s\"%s ];\n%s", - id2num(cell->name), label_string.c_str(), findColor(cell->name.str()), code.c_str()); + fprintf(f, "c%d [ shape=record, label=\"%s\", %s ];\n%s", + id2num(cell->name), label_string.c_str(), findColor(cell->name).c_str(), code.c_str()); } for (auto &it : module->processes) @@ -555,9 +573,9 @@ struct ShowWorker } else if (right_node[0] == 'x') { net_conn_map[left_node].out.insert({right_node, GetSize(conn.first)}); } else { - net_conn_map[right_node].in.insert({stringf("x%d:e", single_idx_count), GetSize(conn.first)}); - net_conn_map[left_node].out.insert({stringf("x%d:w", single_idx_count), GetSize(conn.first)}); - fprintf(f, "x%d [shape=box, style=rounded, label=\"BUF\"];\n", single_idx_count++); + net_conn_map[right_node].in.insert({stringf("x%d", single_idx_count), GetSize(conn.first)}); + net_conn_map[left_node].out.insert({stringf("x%d", single_idx_count), GetSize(conn.first)}); + fprintf(f, "x%d [shape=box, style=rounded, label=\"BUF\", %s];\n", single_idx_count++, findColor(conn).c_str()); } } } @@ -643,6 +661,7 @@ struct ShowPass : public Pass { log(" -viewer \n"); log(" Run the specified command with the graphics file as parameter.\n"); log(" On Windows, this pauses yosys until the viewer exits.\n"); + log(" Use \"-viewer none\" to not run any command.\n"); log("\n"); log(" -format \n"); log(" Generate a graphics file in the specified format. Use 'dot' to just\n"); @@ -903,28 +922,30 @@ struct ShowPass : public Pass { #if defined(YOSYS_DISABLE_SPAWN) log_assert(viewer_exe.empty() && !format.empty()); #else - if (!viewer_exe.empty()) { - #ifdef _WIN32 - // system()/cmd.exe does not understand single quotes nor - // background tasks on Windows. So we have to pause yosys - // until the viewer exits. - std::string cmd = stringf("%s \"%s\"", viewer_exe.c_str(), out_file.c_str()); - #else - std::string cmd = stringf("%s '%s' %s", viewer_exe.c_str(), out_file.c_str(), background.c_str()); - #endif - log("Exec: %s\n", cmd.c_str()); - if (run_command(cmd) != 0) - log_cmd_error("Shell command failed!\n"); - } else - if (format.empty()) { - #ifdef __APPLE__ - std::string cmd = stringf("ps -fu %d | grep -q '[ ]%s' || xdot '%s' %s", getuid(), dot_file.c_str(), dot_file.c_str(), background.c_str()); - #else - std::string cmd = stringf("{ test -f '%s.pid' && fuser -s '%s.pid' 2> /dev/null; } || ( echo $$ >&3; exec xdot '%s'; ) 3> '%s.pid' %s", dot_file.c_str(), dot_file.c_str(), dot_file.c_str(), dot_file.c_str(), background.c_str()); - #endif - log("Exec: %s\n", cmd.c_str()); - if (run_command(cmd) != 0) - log_cmd_error("Shell command failed!\n"); + if (viewer_exe != "none") { + if (!viewer_exe.empty()) { + #ifdef _WIN32 + // system()/cmd.exe does not understand single quotes nor + // background tasks on Windows. So we have to pause yosys + // until the viewer exits. + std::string cmd = stringf("%s \"%s\"", viewer_exe.c_str(), out_file.c_str()); + #else + std::string cmd = stringf("%s '%s' %s", viewer_exe.c_str(), out_file.c_str(), background.c_str()); + #endif + log("Exec: %s\n", cmd.c_str()); + if (run_command(cmd) != 0) + log_cmd_error("Shell command failed!\n"); + } else + if (format.empty()) { + #ifdef __APPLE__ + std::string cmd = stringf("ps -fu %d | grep -q '[ ]%s' || xdot '%s' %s", getuid(), dot_file.c_str(), dot_file.c_str(), background.c_str()); + #else + std::string cmd = stringf("{ test -f '%s.pid' && fuser -s '%s.pid' 2> /dev/null; } || ( echo $$ >&3; exec xdot '%s'; ) 3> '%s.pid' %s", dot_file.c_str(), dot_file.c_str(), dot_file.c_str(), dot_file.c_str(), background.c_str()); + #endif + log("Exec: %s\n", cmd.c_str()); + if (run_command(cmd) != 0) + log_cmd_error("Shell command failed!\n"); + } } #endif diff --git a/yosys/passes/cmds/stat.cc b/yosys/passes/cmds/stat.cc index 522957f3959..f0021cf8769 100644 --- a/yosys/passes/cmds/stat.cc +++ b/yosys/passes/cmds/stat.cc @@ -316,7 +316,7 @@ statdata_t hierarchy_worker(std::map &mod_stat, RTL if (mod_stat.count(it.first) > 0) { if (!quiet) log(" %*s%-*s %6u\n", 2*level, "", 26-2*level, log_id(it.first), it.second); - mod_data = mod_data + hierarchy_worker(mod_stat, it.first, level+1) * it.second; + mod_data = mod_data + hierarchy_worker(mod_stat, it.first, level+1, quiet) * it.second; mod_data.num_cells -= it.second; } else { mod_data.num_cells_by_type[it.first] += it.second; diff --git a/yosys/passes/equiv/equiv_make.cc b/yosys/passes/equiv/equiv_make.cc index 27cec75499e..e15e510be90 100644 --- a/yosys/passes/equiv/equiv_make.cc +++ b/yosys/passes/equiv/equiv_make.cc @@ -33,6 +33,7 @@ struct EquivMakeWorker bool inames; vector blacklists; vector encfiles; + bool make_assert; pool blacklist_names; dict> encdata; @@ -133,6 +134,12 @@ struct EquivMakeWorker delete gate_clone; } + void add_eq_assertion(const SigSpec &gold_sig, const SigSpec &gate_sig) + { + auto eq_wire = equiv_mod->Eqx(NEW_ID, gold_sig, gate_sig); + equiv_mod->addAssert(NEW_ID_SUFFIX("assert"), eq_wire, State::S1); + } + void find_same_wires() { SigMap assign_map(equiv_mod); @@ -231,15 +238,24 @@ struct EquivMakeWorker if (gold_wire->port_output || gate_wire->port_output) { - Wire *wire = equiv_mod->addWire(id, gold_wire->width); - wire->port_output = true; gold_wire->port_input = false; gate_wire->port_input = false; gold_wire->port_output = false; gate_wire->port_output = false; - for (int i = 0; i < wire->width; i++) - equiv_mod->addEquiv(NEW_ID, SigSpec(gold_wire, i), SigSpec(gate_wire, i), SigSpec(wire, i)); + Wire *wire = equiv_mod->addWire(id, gold_wire->width); + wire->port_output = true; + + if (make_assert) + { + add_eq_assertion(gold_wire, gate_wire); + equiv_mod->connect(wire, gold_wire); + } + else + { + for (int i = 0; i < wire->width; i++) + equiv_mod->addEquiv(NEW_ID, SigSpec(gold_wire, i), SigSpec(gate_wire, i), SigSpec(wire, i)); + } rd_signal_map.add(assign_map(gold_wire), wire); rd_signal_map.add(assign_map(gate_wire), wire); @@ -259,26 +275,31 @@ struct EquivMakeWorker } else { - Wire *wire = equiv_mod->addWire(id, gold_wire->width); - SigSpec rdmap_gold, rdmap_gate, rdmap_equiv; + if (make_assert) + add_eq_assertion(gold_wire, gate_wire); - for (int i = 0; i < wire->width; i++) { - if (undriven_bits.count(assign_map(SigBit(gold_wire, i)))) { - log(" Skipping signal bit %s [%d]: undriven on gold side.\n", id2cstr(gold_wire->name), i); - continue; - } - if (undriven_bits.count(assign_map(SigBit(gate_wire, i)))) { - log(" Skipping signal bit %s [%d]: undriven on gate side.\n", id2cstr(gate_wire->name), i); - continue; + else { + Wire *wire = equiv_mod->addWire(id, gold_wire->width); + SigSpec rdmap_gold, rdmap_gate, rdmap_equiv; + + for (int i = 0; i < wire->width; i++) { + if (undriven_bits.count(assign_map(SigBit(gold_wire, i)))) { + log(" Skipping signal bit %s [%d]: undriven on gold side.\n", id2cstr(gold_wire->name), i); + continue; + } + if (undriven_bits.count(assign_map(SigBit(gate_wire, i)))) { + log(" Skipping signal bit %s [%d]: undriven on gate side.\n", id2cstr(gate_wire->name), i); + continue; + } + equiv_mod->addEquiv(NEW_ID, SigSpec(gold_wire, i), SigSpec(gate_wire, i), SigSpec(wire, i)); + rdmap_gold.append(SigBit(gold_wire, i)); + rdmap_gate.append(SigBit(gate_wire, i)); + rdmap_equiv.append(SigBit(wire, i)); } - equiv_mod->addEquiv(NEW_ID, SigSpec(gold_wire, i), SigSpec(gate_wire, i), SigSpec(wire, i)); - rdmap_gold.append(SigBit(gold_wire, i)); - rdmap_gate.append(SigBit(gate_wire, i)); - rdmap_equiv.append(SigBit(wire, i)); - } - rd_signal_map.add(rdmap_gold, rdmap_equiv); - rd_signal_map.add(rdmap_gate, rdmap_equiv); + rd_signal_map.add(rdmap_gold, rdmap_equiv); + rd_signal_map.add(rdmap_gate, rdmap_equiv); + } } } @@ -335,12 +356,20 @@ struct EquivMakeWorker continue; } - for (int i = 0; i < GetSize(gold_sig); i++) - if (gold_sig[i] != gate_sig[i]) { - Wire *w = equiv_mod->addWire(NEW_ID); - equiv_mod->addEquiv(NEW_ID, gold_sig[i], gate_sig[i], w); - gold_sig[i] = w; - } + if (make_assert) + { + if (gold_sig != gate_sig) + add_eq_assertion(gold_sig, gate_sig); + } + else + { + for (int i = 0; i < GetSize(gold_sig); i++) + if (gold_sig[i] != gate_sig[i]) { + Wire *w = equiv_mod->addWire(NEW_ID); + equiv_mod->addEquiv(NEW_ID, gold_sig[i], gate_sig[i], w); + gold_sig[i] = w; + } + } gold_cell->setPort(gold_conn.first, gold_sig); } @@ -417,6 +446,10 @@ struct EquivMakePass : public Pass { log(" Match FSM encodings using the description from the file.\n"); log(" See 'help fsm_recode' for details.\n"); log("\n"); + log(" -make_assert\n"); + log(" Check equivalence with $assert cells instead of $equiv.\n"); + log(" $eqx (===) is used to compare signals."); + log("\n"); log("Note: The circuit created by this command is not a miter (with something like\n"); log("a trigger output), but instead uses $equiv cells to encode the equivalence\n"); log("checking problem. Use 'miter -equiv' if you want to create a miter circuit.\n"); @@ -427,6 +460,7 @@ struct EquivMakePass : public Pass { EquivMakeWorker worker; worker.ct.setup(design); worker.inames = false; + worker.make_assert = false; size_t argidx; for (argidx = 1; argidx < args.size(); argidx++) @@ -443,6 +477,10 @@ struct EquivMakePass : public Pass { worker.encfiles.push_back(args[++argidx]); continue; } + if (args[argidx] == "-make_assert") { + worker.make_assert = true; + continue; + } break; } diff --git a/yosys/passes/memory/memory_libmap.cc b/yosys/passes/memory/memory_libmap.cc index 9e147b0bf06..6e5a806fd0e 100644 --- a/yosys/passes/memory/memory_libmap.cc +++ b/yosys/passes/memory/memory_libmap.cc @@ -183,6 +183,7 @@ struct MemMapping { dict, bool> wr_implies_rd_cache; dict, bool> wr_excludes_rd_cache; dict, bool> wr_excludes_srst_cache; + std::string rejected_cfg_debug_msgs; MemMapping(MapWorker &worker, Mem &mem, const Library &lib, const PassOptions &opts) : worker(worker), qcsat(worker.modwalker), mem(mem), lib(lib), opts(opts) { determine_style(); @@ -201,8 +202,10 @@ struct MemMapping { continue; if (!check_init(rdef)) continue; - if (rdef.prune_rom && mem.wr_ports.empty()) + if (rdef.prune_rom && mem.wr_ports.empty()) { + log_debug("memory %s.%s: rejecting mapping to %s: ROM mapping disabled (prune_rom set)\n", log_id(mem.module->name), log_id(mem.memid), log_id(rdef.id)); continue; + } MemConfig cfg; cfg.def = &rdef; for (auto &cdef: rdef.shared_clocks) { @@ -309,6 +312,59 @@ struct MemMapping { void prune_post_geom(); void emit_port(const MemConfig &cfg, std::vector &cells, const PortVariant &pdef, const char *name, int wpidx, int rpidx, const std::vector &hw_addr_swizzle); void emit(const MemConfig &cfg); + + void log_reject(std::string message){ + if(ys_debug(1)) { + rejected_cfg_debug_msgs += message; + rejected_cfg_debug_msgs += "\n"; + } + } + + void log_reject(const Ram &ram, std::string message) { + if(ys_debug(1)) { + rejected_cfg_debug_msgs += stringf("can't map to to %s: ", log_id(ram.id)); + rejected_cfg_debug_msgs += message; + rejected_cfg_debug_msgs += "\n"; + } + } + + void log_reject(const Ram &ram, const PortGroup &pg, std::string message) { + if(ys_debug(1)) { + rejected_cfg_debug_msgs += stringf("can't map to port group ["); + bool first = true; + for (std::string portname : pg.names){ + if (!first) rejected_cfg_debug_msgs += ", "; + rejected_cfg_debug_msgs += portname; + first = false; + } + rejected_cfg_debug_msgs += stringf("] of %s: ", log_id(ram.id)); + rejected_cfg_debug_msgs += message; + rejected_cfg_debug_msgs += "\n"; + } + } + + void log_reject(const Ram &ram, const PortGroup &pg, int pvi, std::string message) { + if(ys_debug(1)) { + rejected_cfg_debug_msgs += stringf("can't map to option selection ["); + bool first = true; + for(auto opt : pg.variants[pvi].options){ + if (!first) rejected_cfg_debug_msgs += ", "; + rejected_cfg_debug_msgs += opt.first; + rejected_cfg_debug_msgs += stringf(" = %s", log_const(opt.second)); + first = false; + } + rejected_cfg_debug_msgs += "] of port group ["; + first = true; + for (std::string portname : pg.names){ + if (!first) rejected_cfg_debug_msgs += ", "; + rejected_cfg_debug_msgs += portname; + first = false; + } + rejected_cfg_debug_msgs += stringf("] of %s: ", log_id(ram.id)); + rejected_cfg_debug_msgs += message; + rejected_cfg_debug_msgs += "\n"; + } + } }; void MemMapping::dump_configs(int stage) { @@ -431,6 +487,7 @@ void MemMapping::determine_style() { style = ""; if (mem.get_bool_attribute(ID::lram)) { kind = RamKind::Huge; + log("found attribute 'lram' on memory %s.%s, forced mapping to huge RAM\n", log_id(mem.module->name), log_id(mem.memid)); return; } for (auto attr: {ID::ram_block, ID::rom_block, ID::ram_style, ID::rom_style, ID::ramstyle, ID::romstyle, ID::syn_ramstyle, ID::syn_romstyle}) { @@ -438,6 +495,7 @@ void MemMapping::determine_style() { Const val = mem.attributes.at(attr); if (val == 1) { kind = RamKind::NotLogic; + log("found attribute '%s = 1' on memory %s.%s, disabled mapping to FF\n", log_id(attr), log_id(mem.module->name), log_id(mem.memid)); return; } std::string val_s = val.decode_string(); @@ -450,15 +508,20 @@ void MemMapping::determine_style() { // Nothing. } else if (val_s == "logic" || val_s == "registers") { kind = RamKind::Logic; + log("found attribute '%s = %s' on memory %s.%s, forced mapping to FF\n", log_id(attr), val_s.c_str(), log_id(mem.module->name), log_id(mem.memid)); } else if (val_s == "distributed") { kind = RamKind::Distributed; + log("found attribute '%s = %s' on memory %s.%s, forced mapping to distributed RAM\n", log_id(attr), val_s.c_str(), log_id(mem.module->name), log_id(mem.memid)); } else if (val_s == "block" || val_s == "block_ram" || val_s == "ebr") { kind = RamKind::Block; + log("found attribute '%s = %s' on memory %s.%s, forced mapping to block RAM\n", log_id(attr), val_s.c_str(), log_id(mem.module->name), log_id(mem.memid)); } else if (val_s == "huge" || val_s == "ultra") { kind = RamKind::Huge; + log("found attribute '%s = %s' on memory %s.%s, forced mapping to huge RAM\n", log_id(attr), val_s.c_str(), log_id(mem.module->name), log_id(mem.memid)); } else { kind = RamKind::NotLogic; style = val_s; + log("found attribute '%s = %s' on memory %s.%s, forced mapping to %s RAM\n", log_id(attr), val_s.c_str(), log_id(mem.module->name), log_id(mem.memid), val_s.c_str()); } return; } @@ -469,18 +532,26 @@ void MemMapping::determine_style() { // Determine whether the memory can be mapped entirely to soft logic. bool MemMapping::determine_logic_ok() { - if (kind != RamKind::Auto && kind != RamKind::Logic) + if (kind != RamKind::Auto && kind != RamKind::Logic) { + log_reject("can't map to logic: RAM kind conflicts with attribute"); return false; + } // Memory is mappable entirely to soft logic iff all its write ports are in the same clock domain. if (mem.wr_ports.empty()) return true; for (auto &port: mem.wr_ports) { - if (!port.clk_enable) + if (!port.clk_enable){ + log_reject("can't map to logic: unclocked port"); return false; - if (port.clk != mem.wr_ports[0].clk) + } + if (port.clk != mem.wr_ports[0].clk) { + log_reject("can't map to logic: ports have different write clock domains"); return false; - if (port.clk_polarity != mem.wr_ports[0].clk_polarity) + } + if (port.clk_polarity != mem.wr_ports[0].clk_polarity) { + log_reject("can't map to logic: ports have different write clock polarity"); return false; + } } return true; } @@ -492,14 +563,21 @@ bool MemMapping::check_ram_kind(const Ram &ram) { if (ram.kind == kind) return true; if (kind == RamKind::Auto || kind == RamKind::NotLogic) { - if (ram.kind == RamKind::Distributed && opts.no_auto_distributed) + if (ram.kind == RamKind::Distributed && opts.no_auto_distributed) { + log_reject(ram, "option -no-auto-distributed given"); return false; - if (ram.kind == RamKind::Block && opts.no_auto_block) + } + if (ram.kind == RamKind::Block && opts.no_auto_block) { + log_reject(ram, "option -no-auto-block given"); return false; - if (ram.kind == RamKind::Huge && opts.no_auto_huge) + } + if (ram.kind == RamKind::Huge && opts.no_auto_huge) { + log_reject(ram, "option -no-auto-huge given"); return false; + } return true; } + log_reject(ram, "RAM kind conflicts with attribute"); return false; } @@ -510,6 +588,7 @@ bool MemMapping::check_ram_style(const Ram &ram) { for (auto &s: ram.style) if (s == style) return true; + log_reject(ram, "RAM style conflicts with attribute"); return false; } @@ -529,8 +608,10 @@ bool MemMapping::check_init(const Ram &ram) { switch (ram.init) { case MemoryInitKind::None: + if(has_nonx) log_reject(ram, "does not support initialization"); return !has_nonx; case MemoryInitKind::Zero: + if(has_one) log_reject(ram, "does not support non-zero initialization"); return !has_one; default: return true; @@ -566,10 +647,12 @@ bool apply_clock(MemConfig &cfg, const PortVariant &def, SigBit clk, bool clk_po // Perform write port assignment, validating clock options as we go. void MemMapping::assign_wr_ports() { + log_reject(stringf("Assigning write ports... (candidate configs: %lu)", cfgs.size())); for (auto &port: mem.wr_ports) { if (!port.clk_enable) { // Async write ports not supported. cfgs.clear(); + log_reject("can't map at all: async write port"); return; } MemConfigs new_cfgs; @@ -581,21 +664,27 @@ void MemMapping::assign_wr_ports() { for (auto &oport: cfg.wr_ports) if (oport.port_group == pgi) used++; - if (used >= GetSize(pg.names)) + if (used >= GetSize(pg.names)) { + log_reject(*cfg.def, pg, "not enough unassigned ports remaining"); continue; + } for (int pvi = 0; pvi < GetSize(pg.variants); pvi++) { auto &def = pg.variants[pvi]; // Make sure the target is a write port. - if (def.kind == PortKind::Ar || def.kind == PortKind::Sr) + if (def.kind == PortKind::Ar || def.kind == PortKind::Sr) { + log_reject(*cfg.def, pg, pvi, "not a write port"); continue; + } MemConfig new_cfg = cfg; WrPortConfig pcfg; pcfg.rd_port = -1; pcfg.port_group = pgi; pcfg.port_variant = pvi; pcfg.def = &def; - if (!apply_clock(new_cfg, def, port.clk, port.clk_polarity)) + if (!apply_clock(new_cfg, def, port.clk, port.clk_polarity)) { + log_reject(*cfg.def, pg, pvi, "incompatible clock polarity"); continue; + } new_cfg.wr_ports.push_back(pcfg); new_cfgs.push_back(new_cfg); } @@ -607,6 +696,7 @@ void MemMapping::assign_wr_ports() { // Perform read port assignment, validating clock and rden options as we go. void MemMapping::assign_rd_ports() { + log_reject(stringf("Assigning read ports... (candidate configs: %lu)", cfgs.size())); for (int pidx = 0; pidx < GetSize(mem.rd_ports); pidx++) { auto &port = mem.rd_ports[pidx]; MemConfigs new_cfgs; @@ -621,17 +711,23 @@ void MemMapping::assign_rd_ports() { for (auto &oport: cfg.wr_ports) if (oport.port_group == pgi) used++; - if (used >= GetSize(pg.names)) + if (used >= GetSize(pg.names)) { + log_reject(*cfg.def, pg, "not enough unassigned ports remaining"); continue; + } for (int pvi = 0; pvi < GetSize(pg.variants); pvi++) { auto &def = pg.variants[pvi]; // Make sure the target is a read port. - if (def.kind == PortKind::Sw) + if (def.kind == PortKind::Sw) { + log_reject(*cfg.def, pg, pvi, "not a read port"); continue; + } // If mapping an async port, accept only async defs. if (!port.clk_enable) { - if (def.kind == PortKind::Sr || def.kind == PortKind::Srsw) + if (def.kind == PortKind::Sr || def.kind == PortKind::Srsw) { + log_reject(*cfg.def, pg, pvi, "not an asynchronous read port"); continue; + } } MemConfig new_cfg = cfg; RdPortConfig pcfg; @@ -641,8 +737,10 @@ void MemMapping::assign_rd_ports() { pcfg.def = &def; if (def.kind == PortKind::Sr || def.kind == PortKind::Srsw) { pcfg.emu_sync = false; - if (!apply_clock(new_cfg, def, port.clk, port.clk_polarity)) + if (!apply_clock(new_cfg, def, port.clk, port.clk_polarity)) { + log_reject(*cfg.def, pg, pvi, "incompatible clock polarity"); continue; + } // Decide if rden is usable. if (port.en != State::S1) { if (def.clk_en) { @@ -664,22 +762,34 @@ void MemMapping::assign_rd_ports() { auto &wpcfg = cfg.wr_ports[wpidx]; auto &def = *wpcfg.def; // Make sure the write port is not yet shared. - if (wpcfg.rd_port != -1) + if (wpcfg.rd_port != -1) { + log_reject(stringf("can't share write port %d: already shared by a different read port", wpidx)); continue; + } // Make sure the target is a read port. - if (def.kind == PortKind::Sw) + if (def.kind == PortKind::Sw) { + log_reject(stringf("can't share write port %d: not a read-write port", wpidx)); continue; + } // Validate address compatibility. - if (!addr_compatible(wpidx, pidx)) + if (!addr_compatible(wpidx, pidx)) { + log_reject(stringf("can't share write port %d: addresses are not compatible", wpidx)); continue; + } // Validate clock compatibility, if needed. if (def.kind == PortKind::Srsw) { - if (!port.clk_enable) + if (!port.clk_enable) { + log_reject(stringf("can't share write port %d: incompatible enable", wpidx)); continue; - if (port.clk != wport.clk) + } + if (port.clk != wport.clk) { + log_reject(stringf("can't share write port %d: different clock signal", wpidx)); continue; - if (port.clk_polarity != wport.clk_polarity) + } + if (port.clk_polarity != wport.clk_polarity) { + log_reject(stringf("can't share write port %d: incompatible clock polarity", wpidx)); continue; + } } // Okay, let's fill it in. MemConfig new_cfg = cfg; @@ -696,8 +806,10 @@ void MemMapping::assign_rd_ports() { bool col_x = port.collision_x_mask[wpidx]; if (def.rdwr == RdWrKind::NoChange) { if (!get_wr_excludes_rd(wpidx, pidx)) { - if (!trans && !col_x) + if (!trans && !col_x) { + log_reject(stringf("can't share write port %d: conflict in simultaneous read and write operations", wpidx)); continue; + } if (trans) pcfg.emu_trans.push_back(wpidx); new_cfg.wr_ports[wpidx].force_uniform = true; @@ -710,8 +822,10 @@ void MemMapping::assign_rd_ports() { } } } else { - if (!col_x && !trans && def.rdwr != RdWrKind::Old) + if (!col_x && !trans && def.rdwr != RdWrKind::Old) { + log_reject(stringf("can't share write port %d: simultaneous read and write operations should result in new value but port reads old", wpidx)); continue; + } if (trans) { if (def.rdwr != RdWrKind::New && def.rdwr != RdWrKind::NewOnly) pcfg.emu_trans.push_back(wpidx); @@ -743,6 +857,7 @@ void MemMapping::assign_rd_ports() { // Validate transparency restrictions, determine where to add soft transparency logic. void MemMapping::handle_trans() { + log_reject(stringf("Handling transparency... (candidate configs: %lu)", cfgs.size())); if (mem.emulate_read_first_ok()) { MemConfigs new_cfgs; for (auto &cfg: cfgs) { @@ -801,15 +916,21 @@ void MemMapping::handle_trans() { bool found = false; for (auto &tdef: wpcfg.def->wrtrans) { // Check if the target matches. - if (tdef.target_kind == WrTransTargetKind::Group && rpcfg.port_group != tdef.target_group) + if (tdef.target_kind == WrTransTargetKind::Group && rpcfg.port_group != tdef.target_group) { + log_reject(*cfg.def, stringf("transparency with target port group %d not supported", tdef.target_group)); continue; + } // Check if the transparency kind is acceptable. if (transparent) { - if (tdef.kind == WrTransKind::Old) + if (tdef.kind == WrTransKind::Old) { + log_reject(*cfg.def, stringf("target %d has wrong transparency kind: new value required", tdef.target_group)); continue; + } } else { - if (tdef.kind != WrTransKind::Old) + if (tdef.kind != WrTransKind::Old) { + log_reject(*cfg.def, stringf("target %d has wrong transparency kind: old value required", tdef.target_group)); continue; + } } // Okay, we can use this cap. new_cfgs.push_back(cfg); @@ -2073,8 +2194,11 @@ struct MemoryLibMapPass : public Pass { int idx = -1; int best = map.logic_cost; if (!map.logic_ok) { - if (map.cfgs.empty()) + if (map.cfgs.empty()) { + log_debug("Rejected candidates for mapping memory %s.%s:\n", log_id(module->name), log_id(mem.memid)); + log_debug("%s", map.rejected_cfg_debug_msgs.c_str()); log_error("no valid mapping found for memory %s.%s\n", log_id(module->name), log_id(mem.memid)); + } idx = 0; best = map.cfgs[0].cost; } diff --git a/yosys/passes/opt/opt_clean.cc b/yosys/passes/opt/opt_clean.cc index dde7c5299c6..cb2490dc72e 100644 --- a/yosys/passes/opt/opt_clean.cc +++ b/yosys/passes/opt/opt_clean.cc @@ -292,10 +292,12 @@ bool rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool verbos if (!purge_mode) for (auto &it : module->cells_) { RTLIL::Cell *cell = it.second; - if (ct_reg.cell_known(cell->type)) + if (ct_reg.cell_known(cell->type)) { + bool clk2fflogic = cell->get_bool_attribute(ID(clk2fflogic)); for (auto &it2 : cell->connections()) - if (ct_reg.cell_output(cell->type, it2.first)) + if (clk2fflogic ? it2.first == ID::D : ct_reg.cell_output(cell->type, it2.first)) register_signals.add(it2.second); + } for (auto &it2 : cell->connections()) connected_signals.add(it2.second); } diff --git a/yosys/passes/opt/opt_expr.cc b/yosys/passes/opt/opt_expr.cc index 9d5ca4ef9a1..46773a344b1 100644 --- a/yosys/passes/opt/opt_expr.cc +++ b/yosys/passes/opt/opt_expr.cc @@ -2165,7 +2165,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons { condition = "signed X>=0"; replacement = stringf("X[%d]", var_width - 1); - module->addNot(NEW_ID, var_sig[var_width - 1], cell->getPort(ID::Y)); + module->addLogicNot(NEW_ID, var_sig[var_width - 1], cell->getPort(ID::Y)); remove = true; } } diff --git a/yosys/passes/opt/opt_share.cc b/yosys/passes/opt/opt_share.cc index ba85df975f9..bf9569d9905 100644 --- a/yosys/passes/opt/opt_share.cc +++ b/yosys/passes/opt/opt_share.cc @@ -131,6 +131,9 @@ RTLIL::IdString decode_port_semantics(RTLIL::Cell *cell, RTLIL::IdString port_na if (cell->type.in(ID($lt), ID($le), ID($ge), ID($gt), ID($div), ID($mod), ID($divfloor), ID($modfloor), ID($concat), SHIFT_OPS) && port_name == ID::B) return port_name; + if (cell->type.in(ID($_ANDNOT_), ID($_ORNOT_))) + return port_name; + return ""; } diff --git a/yosys/passes/opt/wreduce.cc b/yosys/passes/opt/wreduce.cc index 8fd4c788c92..87a5cb56d86 100644 --- a/yosys/passes/opt/wreduce.cc +++ b/yosys/passes/opt/wreduce.cc @@ -364,10 +364,16 @@ struct WreduceWorker if (cell->type == ID($mul)) max_y_size = a_size + b_size; - while (GetSize(sig) > 1 && GetSize(sig) > max_y_size) { - module->connect(sig[GetSize(sig)-1], is_signed ? sig[GetSize(sig)-2] : State::S0); - sig.remove(GetSize(sig)-1); - bits_removed++; + max_y_size = std::max(max_y_size, 1); + + if (GetSize(sig) > max_y_size) { + SigSpec extra_bits = sig.extract(max_y_size, GetSize(sig) - max_y_size); + + bits_removed += GetSize(extra_bits); + sig.remove(max_y_size, GetSize(extra_bits)); + + SigBit padbit = is_signed ? sig[GetSize(sig)-1] : State::S0; + module->connect(extra_bits, SigSpec(padbit, GetSize(extra_bits))); } } diff --git a/yosys/passes/proc/proc_prune.cc b/yosys/passes/proc/proc_prune.cc index 9f1080ef635..3433557eea1 100644 --- a/yosys/passes/proc/proc_prune.cc +++ b/yosys/passes/proc/proc_prune.cc @@ -91,7 +91,7 @@ struct PruneWorker if (GetSize(new_lhs) == 0) { if (GetSize(conn_lhs) == 0) removed_count++; - cs->actions.erase((it++).base() - 1); + it = decltype(cs->actions)::reverse_iterator(cs->actions.erase(it.base() - 1)); } else { it->first = new_lhs; it->second = new_rhs; diff --git a/yosys/passes/sat/Makefile.inc b/yosys/passes/sat/Makefile.inc index ebe3dc53682..d9bf69dcb90 100644 --- a/yosys/passes/sat/Makefile.inc +++ b/yosys/passes/sat/Makefile.inc @@ -16,6 +16,8 @@ OBJS += passes/sat/fmcombine.o OBJS += passes/sat/mutate.o OBJS += passes/sat/cutpoint.o OBJS += passes/sat/fminit.o +OBJS += passes/sat/recover_names.o ifeq ($(DISABLE_SPAWN),0) OBJS += passes/sat/qbfsat.o endif +OBJS += passes/sat/synthprop.o diff --git a/yosys/passes/sat/clk2fflogic.cc b/yosys/passes/sat/clk2fflogic.cc index bba2cbbecc7..3dc96ecce2a 100644 --- a/yosys/passes/sat/clk2fflogic.cc +++ b/yosys/passes/sat/clk2fflogic.cc @@ -80,15 +80,27 @@ struct Clk2fflogicPass : public Pass { return module->Eqx(NEW_ID, {sampled_sig, sig}, polarity ? SigSpec {State::S0, State::S1} : SigSpec {State::S1, State::S0}); } // Sampled and current value of a data signal. - SampledSig sample_data(Module *module, SigSpec sig, RTLIL::Const init, bool is_fine) { + SampledSig sample_data(Module *module, SigSpec sig, RTLIL::Const init, bool is_fine, bool set_attribute = false) { std::string sig_str = log_signal(sig); sig_str.erase(std::remove(sig_str.begin(), sig_str.end(), ' '), sig_str.end()); + + Wire *sampled_sig = module->addWire(NEW_ID_SUFFIX(stringf("%s#sampled", sig_str.c_str())), GetSize(sig)); sampled_sig->attributes[ID::init] = init; + + Cell *cell; if (is_fine) - module->addFfGate(NEW_ID, sig, sampled_sig); + cell = module->addFfGate(NEW_ID, sig, sampled_sig); else - module->addFf(NEW_ID, sig, sampled_sig); + cell = module->addFf(NEW_ID, sig, sampled_sig); + + if (set_attribute) { + for (auto &chunk : sig.chunks()) + if (chunk.wire != nullptr) + chunk.wire->set_bool_attribute(ID::keep); + cell->set_bool_attribute(ID(clk2fflogic)); + } + return {sampled_sig, sig}; } SigSpec mux(Module *module, SigSpec a, SigSpec b, SigSpec s, bool is_fine) { @@ -213,7 +225,7 @@ struct Clk2fflogicPass : public Pass { if (ff.has_clk) ff.unmap_ce_srst(); - auto next_q = sample_data(module, ff.sig_q, ff.val_init, ff.is_fine).sampled; + auto next_q = sample_data(module, ff.sig_q, ff.val_init, ff.is_fine, true).sampled; if (ff.has_clk) { // The init value for the sampled d is never used, so we can set it to fixed zero, reducing uninit'd FFs diff --git a/yosys/passes/sat/recover_names.cc b/yosys/passes/sat/recover_names.cc new file mode 100644 index 00000000000..2d7e7f01cfa --- /dev/null +++ b/yosys/passes/sat/recover_names.cc @@ -0,0 +1,730 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2021 gatecat + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include "kernel/yosys.h" +#include "kernel/sigtools.h" +#include "kernel/consteval.h" +#include "kernel/celltypes.h" +#include "kernel/utils.h" +#include "kernel/satgen.h" + +#include +#include + +USING_YOSYS_NAMESPACE + +template<> struct hashlib::hash_ops : hashlib::hash_int_ops +{ + static inline unsigned int hash(uint64_t a) { + return mkhash((unsigned int)(a), (unsigned int)(a >> 32)); + } +}; + +PRIVATE_NAMESPACE_BEGIN + +// xorshift128 params +#define INIT_X 123456789 +#define INIT_Y 362436069 +#define INIT_Z 521288629 +#define INIT_W 88675123 + + +// Similar to a SigBit; but module-independent +struct IdBit { + IdBit() : name(), bit(0) {}; + IdBit(IdString name, int bit = 0) : name(name), bit(bit) {}; + + bool operator==(const IdBit &other) const { return name == other.name && bit == other.bit; }; + bool operator!=(const IdBit &other) const { return name != other.name || bit != other.bit; }; + unsigned hash() const + { + return mkhash_add(name.hash(), bit); + } + + IdString name; + int bit; +}; + +// As above; but can be inverted +struct InvBit { + InvBit() : bit(), inverted(false) {}; + explicit InvBit(IdBit bit, bool inverted = false) : bit(bit), inverted(inverted) {}; + + bool operator==(const InvBit &other) const { return bit == other.bit && inverted == other.inverted; }; + bool operator!=(const InvBit &other) const { return bit != other.bit || inverted != other.inverted; }; + unsigned hash() const + { + return mkhash(bit.hash(), inverted); + } + + IdBit bit; + bool inverted; +}; + +typedef uint64_t equiv_cls_t; +static const int sim_length = sizeof(equiv_cls_t) * 8; + +struct RecoverModuleWorker { + Design *design = nullptr; + Module *mod, *flat = nullptr; + RecoverModuleWorker(Module *mod) : design(mod->design), mod(mod) {}; + + ConstEval *ce = nullptr; + SigMap *sigmap = nullptr; + + dict flat2orig; + dict bit2primary; + dict bit2driver; + + void prepare() + { + // Create a derivative of the module with whiteboxes flattened so we can + // run eval and sat on it + flat = design->addModule(NEW_ID); + mod->cloneInto(flat); + Pass::call_on_module(design, flat, "flatten -wb"); + ce = new ConstEval(flat); + sigmap = new SigMap(flat); + // Create a mapping from primary name-bit in the box-flattened module to original sigbit + SigMap orig_sigmap(mod); + for (auto wire : mod->wires()) { + Wire *flat_wire = flat->wire(wire->name); + if (!flat_wire) + continue; + for (int i = 0; i < wire->width; i++) { + SigBit orig_sigbit = orig_sigmap(SigBit(wire, i)); + SigBit flat_sigbit = (*sigmap)(SigBit(flat_wire, i)); + if (!orig_sigbit.wire || !flat_sigbit.wire) + continue; + flat2orig[IdBit(flat_sigbit.wire->name, flat_sigbit.offset)] = orig_sigbit; + } + } + find_driven_bits(); + } + + void find_driven_bits() + { + // Add primary inputs + for (auto wire : flat->wires()) { + if (!wire->port_input) + continue; + for (int i = 0; i < wire->width; i++) { + SigBit bit(wire, i); + bit = (*sigmap)(bit); + if (bit.wire) + bit2driver[IdBit(bit.wire->name, bit.offset)] = nullptr; + } + } + // Add cell outputs + for (auto cell : flat->cells()) { + for (auto conn : cell->connections()) { + if (!cell->output(conn.first)) + continue; + for (auto bit : conn.second) { + auto resolved = (*sigmap)(bit); + if (resolved.wire) + bit2driver[IdBit(resolved.wire->name, resolved.offset)] = cell; + } + } + } + // Setup bit2primary + for (auto wire : flat->wires()) { + for (int i = 0; i < wire->width; i++) { + SigBit bit(wire, i); + bit = (*sigmap)(bit); + if (bit.wire) + bit2primary[IdBit(wire->name, i)] = IdBit(bit.wire->name, bit.offset); + } + } + } + + // Mapping from bit to (candidate) equivalence classes + dict bit2cls; + void sim_cycle(int t, const dict &anchors) + { + ce->clear(); + for (auto anchor : anchors) { + SigBit bit = (*sigmap)(SigBit(flat->wire(anchor.first.name), anchor.first.bit)); + // Ignore in the rare case that it's already determined + SigSpec res(bit); + if (ce->eval(res)) + continue; + ce->set(bit, anchor.second); + } + // Only evaluate IdBits that exist in the non-flat design; as they are all we care about + for (auto idbit : flat2orig) { + if (anchors.count(idbit.first)) + continue; + SigBit bit = (*sigmap)(SigBit(flat->wire(idbit.first.name), idbit.first.bit)); + SigSpec res(bit); + if (!ce->eval(res)) + continue; + if (res != State::S0 && res != State::S1) + continue; + // Update equivalence classes + if (res == State::S1) + bit2cls[idbit.first] = bit2cls[idbit.first] | (equiv_cls_t(1) << t); + } + } + + // Update the equivalence class groupings + void group_classes(dict, pool>> &cls2bits, bool is_gate) + { + equiv_cls_t all_ones = 0; + for (int i = 0; i < sim_length; i++) all_ones |= (equiv_cls_t(1) << i); + for (auto pair : bit2cls) { + if (pair.second == 0 || pair.second == all_ones) + continue; // skip stuck-ats + if (is_gate) { + // True doesn't exist in gold; but inverted does + if (!cls2bits.count(pair.second) && cls2bits.count(pair.second ^ all_ones)) + cls2bits[pair.second ^ all_ones].second.emplace(pair.first, true); + else + cls2bits[pair.second].second.emplace(pair.first, false); + } else { + cls2bits[pair.second].first.insert(pair.first); + } + } + } + + // Compute depths of IdBits + dict bit2depth; + void compute_depths(const dict &anchor_bits) + { + dict> bit_drivers, bit_users; + TopoSort toposort; + + for (auto cell : flat->cells()) + for (auto conn : cell->connections()) + { + for (auto bit : (*sigmap)(conn.second)) { + if (!bit.wire) + continue; + IdBit idbit(bit.wire->name, bit.offset); + if (anchor_bits.count(idbit)) + continue; + if (cell->input(conn.first)) + bit_users[bit].insert(cell->name); + + if (cell->output(conn.first)) + bit_drivers[bit].insert(cell->name); + } + + toposort.node(cell->name); + } + + for (auto &it : bit_users) + if (bit_drivers.count(it.first)) + for (auto driver_cell : bit_drivers.at(it.first)) + for (auto user_cell : it.second) + toposort.edge(driver_cell, user_cell); + + toposort.sort(); + for (auto cell_name : toposort.sorted) { + Cell *cell = flat->cell(cell_name); + int cell_depth = 0; + for (auto conn : cell->connections()) { + if (!cell->input(conn.first)) + continue; + for (auto bit : (*sigmap)(conn.second)) { + if (!bit.wire) + continue; + IdBit idbit(bit.wire->name, bit.offset); + if (!bit2depth.count(idbit)) + continue; + cell_depth = std::max(cell_depth, bit2depth.at(idbit)); + } + } + for (auto conn : cell->connections()) { + if (!cell->output(conn.first)) + continue; + for (auto bit : (*sigmap)(conn.second)) { + if (!bit.wire) + continue; + IdBit idbit(bit.wire->name, bit.offset); + bit2depth[idbit] = std::max(bit2depth[idbit], cell_depth + 1); + } + } + } + } + + // SAT thresholds + const int max_sat_cells = 50; + + SigBit id2bit(IdBit bit) { return SigBit(flat->wire(bit.name), bit.bit); } + + // Set up the SAT problem for an IdBit + // the value side of 'anchors' will be populated with the SAT variable for anchor bits + int setup_sat(SatGen *sat, const std::string &prefix, IdBit bit, const dict &anchor_bits, dict &anchor2var) + { + sat->setContext(sigmap, prefix); + pool imported_cells; + int result = sat->importSigBit(id2bit(bit)); + // Recursively import driving cells + std::queue to_import; + to_import.push(bit); + while (!to_import.empty()) { + // Too many cells imported + if (GetSize(imported_cells) > max_sat_cells) + return -1; + IdBit cursor = to_import.front(); + to_import.pop(); + if (anchor_bits.count(cursor)) { + if (!anchor2var.count(cursor)) { + anchor2var[cursor] = sat->importSigBit(id2bit(cursor)); + } + continue; + } + // Import driver if it exists + if (!bit2driver.count(cursor)) + continue; + Cell *driver = bit2driver.at(cursor); + if (!driver || imported_cells.count(driver->name)) + continue; + if (!sat->importCell(driver)) + return -1; // cell can't be imported + imported_cells.insert(driver->name); + // Add cell inputs to queue + for (auto conn : driver->connections()) { + if (!driver->input(conn.first)) + continue; + for (SigBit in_bit : (*sigmap)(conn.second)) { + if (!in_bit.wire) + continue; + IdBit in_idbit(in_bit.wire->name, in_bit.offset); + to_import.push(in_idbit); + } + } + } + return result; + } + + void find_buffers(const pool &buffer_types, dict> &root2buffered) + { + SigMap orig_sigmap(mod); + dict buffer2root; + for (auto cell : mod->cells()) { + if (!buffer_types.count(cell->type)) + continue; + SigBit in, out; + for (auto conn : cell->connections()) { + if (cell->input(conn.first)) { + in = orig_sigmap(conn.second[0]); + } + if (cell->output(conn.first)) { + out = orig_sigmap(conn.second[0]); + } + } + if (!in.wire || !out.wire) + continue; + SigBit root = in; + if (buffer2root.count(root)) + root = buffer2root[root]; + if (root2buffered.count(out)) { + for (auto out_sig : root2buffered.at(out)) + root2buffered[root].insert(out_sig); + root2buffered.erase(out); + } + root2buffered[root].insert(out); + buffer2root[out] = root; + } + } + + void do_rename(Module *gold, const dict &gate2gold, const pool &buffer_types) + { + dict>> bit2port; + pool unused_bits; + SigMap orig_sigmap(mod); + for (auto wire : mod->wires()) { + if (wire->port_input || wire->port_output) + continue; + for (int i = 0; i < wire->width; i++) + unused_bits.insert(orig_sigmap(SigBit(wire, i))); + } + for (auto cell : mod->cells()) { + for (auto conn : cell->connections()) { + for (int i = 0; i < GetSize(conn.second); i++) { + SigBit bit = orig_sigmap(conn.second[i]); + if (!bit.wire) + continue; + bit2port[bit].emplace_back(cell, conn.first, i); + unused_bits.erase(bit); + } + } + } + dict> root2buffered; + find_buffers(buffer_types, root2buffered); + + // An extension of gate2gold that deals with buffers too + // gate sigbit --> (new name, invert, gold wire) + dict> rename_map; + for (auto pair : gate2gold) { + SigBit gate_bit = flat2orig.at(pair.first); + Wire *gold_wire = gold->wire(pair.second.bit.name); + rename_map[gate_bit] = std::make_pair(pair.second, gold_wire); + if (root2buffered.count(gate_bit)) { + int buf_idx = 0; + for (auto buf_bit : root2buffered.at(gate_bit)) { + std::string buf_name_str = stringf("%s_buf_%d", pair.second.bit.name.c_str(), ++buf_idx); + if (buf_name_str[0] == '\\') + buf_name_str[0] = '$'; + rename_map[buf_bit] = std::make_pair( + InvBit(IdBit(IdString(buf_name_str), pair.second.bit.bit), pair.second.inverted), gold_wire); + } + } + } + + for (auto rule : rename_map) { + // Pick a uniq new name + IdBit new_name = rule.second.first.bit; + int dup_idx = 0; + bool must_invert_name = rule.second.first.inverted; + while (must_invert_name || + (mod->wire(new_name.name) && !unused_bits.count(SigBit(mod->wire(new_name.name), new_name.bit)))) { + std::string new_name_str = stringf("%s_%s_%d", rule.second.first.bit.name.c_str(), + rule.second.first.inverted ? "inv" : "dup", ++dup_idx); + if (new_name_str[0] == '\\') + new_name_str[0] = '$'; + new_name.name = IdString(new_name_str); + must_invert_name = false; + } + // Create the wire if needed + Wire *new_wire = mod->wire(new_name.name); + if (!new_wire) { + Wire *gold_wire = rule.second.second; + new_wire = mod->addWire(new_name.name, gold_wire->width); + new_wire->start_offset = gold_wire->start_offset; + new_wire->upto = gold_wire->upto; + for (const auto &attr : gold_wire->attributes) + new_wire->attributes[attr.first] = attr.second; + for (int i = 0; i < new_wire->width; i++) + unused_bits.insert(SigBit(new_wire, i)); + } + // Ensure it's wide enough + if (new_wire->width <= new_name.bit) + new_wire->width = new_name.bit + 1; + SigBit old_bit = rule.first; + SigBit new_bit(new_wire, new_name.bit); + unused_bits.erase(new_bit); + // Replace all users + if (bit2port.count(old_bit)) + for (auto port_ref : bit2port.at(old_bit)) { + Cell *cell = std::get<0>(port_ref); + IdString port_name = std::get<1>(port_ref); + int port_bit = std::get<2>(port_ref); + SigSpec port_sig = cell->getPort(port_name); + port_sig.replace(port_bit, new_bit); + cell->unsetPort(port_name); + cell->setPort(port_name, port_sig); + } + } + } + + ~RecoverModuleWorker() + { + delete ce; + delete sigmap; + if (flat) + design->remove(flat); + } +}; + +struct RecoverNamesWorker { + Design *design, *gold_design = nullptr; + CellTypes ct_all; + RecoverNamesWorker(Design *design) : design(design) {} + + pool comb_whiteboxes, buffer_types; + + // class -> (gold, (gate, inverted)) + dict, dict>> cls2bits; + + void analyse_boxes() + { + for (auto mod : design->modules()) { + if (!mod->get_bool_attribute(ID::whitebox)) + continue; + bool is_comb = true; + for (auto cell : mod->cells()) { + if (ct_all.cell_evaluable(cell->type)) { + is_comb = false; + break; + } + } + if (!is_comb) + continue; + comb_whiteboxes.insert(mod->name); + // Buffers have one input and one output; exactly + SigBit in{}, out{}; + ConstEval eval(mod); + for (auto wire : mod->wires()) { + if (wire->port_input) { + if (wire->width != 1 || in.wire) + goto not_buffer; + in = SigBit(wire, 0); + } + if (wire->port_output) { + if (wire->width != 1 || out.wire) + goto not_buffer; + out = SigBit(wire, 0); + } + } + if (!in.wire || !out.wire) + goto not_buffer; + // Buffer input mirrors output + for (auto bit : {State::S0, State::S1}) { + eval.clear(); + eval.set(in, bit); + SigSpec result(out); + if (!eval.eval(result)) + goto not_buffer; + if (result != bit) + goto not_buffer; + } + buffer_types.insert(mod->name); + if (false) { + not_buffer: + continue; + } + } + log_debug("Found %d combinational cells and %d buffer whiteboxes.\n", GetSize(comb_whiteboxes), GetSize(buffer_types)); + } + + uint32_t x, y, z, w, rng_val; + int rng_bit; + void rng_init() + { + x = INIT_X; + y = INIT_Y; + z = INIT_Z; + w = INIT_W; + rng_bit = 32; + } + uint32_t xorshift128() + { + uint32_t t = x ^ (x << 11); + x = y; y = z; z = w; + w ^= (w >> 19) ^ t ^ (t >> 8); + return w; + } + RTLIL::State next_randbit() + { + if (rng_bit >= 32) { + rng_bit = 0; + rng_val = xorshift128(); + } + return ((rng_val >> (rng_bit++)) & 0x1) ? RTLIL::State::S1 : RTLIL::State::S0; + } + + int popcount(equiv_cls_t cls) { + int result = 0; + for (unsigned i = 0; i < 8*sizeof(equiv_cls_t); i++) + if ((cls >> i) & 0x1) + ++result; + return result; + } + + bool prove_equiv(RecoverModuleWorker &gold_worker, RecoverModuleWorker &gate_worker, + const dict &gold_anchors, const dict &gate_anchors, + IdBit gold_bit, IdBit gate_bit, bool invert) { + ezSatPtr ez; + SatGen satgen(ez.get(), nullptr); + dict anchor2var_gold, anchor2var_gate; + int gold_var = gold_worker.setup_sat(&satgen, "gold", gold_bit, gold_anchors, anchor2var_gold); + if (gold_var == -1) + return false; + int gate_var = gate_worker.setup_sat(&satgen, "gate", gate_bit, gate_anchors, anchor2var_gate); + if (gate_var == -1) + return false; + // Assume anchors are equal + for (auto anchor : anchor2var_gate) { + IdBit gold_anchor = gate_anchors.at(anchor.first); + if (!anchor2var_gold.count(gold_anchor)) + continue; + ez->assume(ez->IFF(anchor.second, anchor2var_gold.at(gold_anchor))); + } + // Prove equivalence + return !ez->solve(ez->NOT(ez->IFF(gold_var, invert ? ez->NOT(gate_var) : gate_var))); + } + + void analyse_mod(Module *gate_mod) + { + Module *gold_mod = gold_design->module(gate_mod->name); + if (!gold_mod) + return; + + RecoverModuleWorker gold_worker(gold_mod); + RecoverModuleWorker gate_worker(gate_mod); + + gold_worker.prepare(); + gate_worker.prepare(); + + // Find anchors (same-name wire-bits driven in both gold and gate) + dict gold_anchors, gate_anchors; + + for (auto gold_bit : gold_worker.bit2driver) { + if (gate_worker.bit2primary.count(gold_bit.first)) { + IdBit gate_bit = gate_worker.bit2primary.at(gold_bit.first); + if (!gate_worker.bit2driver.count(gate_bit)) + continue; + gold_anchors[gold_bit.first] = gate_bit; + gate_anchors[gate_bit] = gold_bit.first; + } + } + // Run a random-value combinational simulation to find candidate equivalence classes + dict gold_anchor_vals, gate_anchor_vals; + rng_init(); + for (int t = 0; t < sim_length; t++) { + for (auto anchor : gold_anchors) { + gold_anchor_vals[anchor.first] = next_randbit(); + gate_anchor_vals[anchor.second] = gold_anchor_vals[anchor.first]; + } + gold_worker.sim_cycle(t, gold_anchor_vals); + gate_worker.sim_cycle(t, gate_anchor_vals); + } + log_debug("%d candidate equiv classes in gold; %d in gate\n", GetSize(gold_worker.bit2cls), GetSize(gate_worker.bit2cls)); + // Group bits by equivalence classes together + dict, pool>> cls2bits; + gold_worker.group_classes(cls2bits, false); + gate_worker.group_classes(cls2bits, true); + gate_worker.compute_depths(gate_anchors); + // Sort equivalence classes by shallowest first (so we have as many anchors as possible when reaching deeper bits) + std::vector> cls_depth; + for (auto &cls : cls2bits) { + if (cls.second.second.empty()) + continue; + int depth = 0; + for (auto gate_bit : cls.second.second) { + if (!gate_worker.bit2depth.count(gate_bit.bit)) + continue; + depth = std::max(depth, gate_worker.bit2depth.at(gate_bit.bit)); + } + cls_depth.emplace_back(cls.first, depth); + } + std::stable_sort(cls_depth.begin(), cls_depth.end(), + [](const std::pair &a, const std::pair &b) { + return a.second < b.second; + }); + // The magic result we've worked hard for.... + dict gate2gold; + // Solve starting from shallowest + for (auto cls : cls_depth) { + int pop = popcount(cls.first); + // Equivalence classes with only one set bit are invariably a waste of SAT time + if (pop == 1 || pop == (8*sizeof(equiv_cls_t) - 1)) + continue; + + log_debug("equivalence class: %016lx\n", cls.first); + const pool &gold_bits = cls2bits.at(cls.first).first; + const pool &gate_bits = cls2bits.at(cls.first).second; + if (gold_bits.empty() || gate_bits.empty()) + continue; + pool solved_gate; + if (GetSize(gold_bits) > 10) + continue; // large equivalence classes are not very interesting; skip + for (IdBit gold_bit : gold_bits) { + for (auto gate_bit : gate_bits) { + if (solved_gate.count(gate_bit.bit)) + continue; + log_debug(" attempting to prove %s[%d] == %s%s[%d]\n", log_id(gold_bit.name), gold_bit.bit, + gate_bit.inverted ? "" : "!", log_id(gate_bit.bit.name), gate_bit.bit.bit); + if (!prove_equiv(gold_worker, gate_worker, gold_anchors, gate_anchors, gold_bit, gate_bit.bit, gate_bit.inverted)) + continue; + log_debug(" success!\n"); + // Success! + gate2gold[gate_bit.bit] = InvBit(gold_bit, gate_bit.inverted); + if (!gate_bit.inverted) { + // Only add as anchor if not inverted + gold_anchors[gold_bit] = gate_bit.bit; + gate_anchors[gate_bit.bit] = gold_bit; + } + solved_gate.insert(gate_bit.bit); + } + // All solved... + if (GetSize(solved_gate) == GetSize(gate_bits)) + break; + } + } + log("Recovered %d net name pairs in module `%s' out.\n", GetSize(gate2gold), log_id(gate_mod)); + gate_worker.do_rename(gold_mod, gate2gold, buffer_types); + } + + void operator()(string command) + { + // Make a backup copy of the pre-mapping design for later + gold_design = new RTLIL::Design; + + for (auto mod : design->modules()) + gold_design->add(mod->clone()); + + run_pass(command, design); + + analyse_boxes(); + + // keeping our own std::vector here avoids modify-while-iterating issues + std::vector to_analyse; + for (auto mod : design->modules()) + if (!mod->get_blackbox_attribute()) + to_analyse.push_back(mod); + for (auto mod : to_analyse) + analyse_mod(mod); + } + ~RecoverNamesWorker() { + delete gold_design; + } +}; + +struct RecoverNamesPass : public Pass { + RecoverNamesPass() : Pass("recover_names", "Execute a lossy mapping command and recover original netnames") { } + void help() override + { + // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| + log("\n"); + log(" recover_names [command]\n"); + log("\n"); + log("This pass executes a lossy mapping command and uses a combination of simulation\n"); + log(" to find candidate equivalences and SAT to recover exact original net names.\n"); + log("\n"); + } + void execute(std::vector args, RTLIL::Design *design) override + { + log_header(design, "Executing RECOVER_NAMES pass (run mapping and recover original names).\n"); + string command; + + size_t argidx = 1; + for (; argidx < args.size(); argidx++) { + if (command.empty()) { + if (args[argidx].compare(0, 1, "-") == 0) + cmd_error(args, argidx, "Unknown option."); + } else { + command += " "; + } + command += args[argidx]; + } + + if (command.empty()) + log_cmd_error("No mapping pass specified!\n"); + + RecoverNamesWorker worker(design); + worker(command); + + } +} RecoverNamesPass; + +PRIVATE_NAMESPACE_END diff --git a/yosys/passes/sat/sim.cc b/yosys/passes/sat/sim.cc index cfe31968dd3..325e123201c 100644 --- a/yosys/passes/sat/sim.cc +++ b/yosys/passes/sat/sim.cc @@ -139,6 +139,9 @@ struct SimInstance dict> upd_cells; dict> upd_outports; + dict in_parent_drivers; + dict clk2fflogic_drivers; + pool dirty_bits; pool dirty_cells; pool dirty_memories; @@ -185,6 +188,10 @@ struct SimInstance { log_assert(module); + if (module->get_blackbox_attribute(true)) + log_error("Cannot simulate blackbox module %s (instanced at %s).\n", + log_id(module->name), hiername().c_str()); + if (parent) { log_assert(parent->children.count(instance) == 0); parent->children[instance] = this; @@ -218,6 +225,13 @@ struct SimInstance dirty_bits.insert(sig[i]); } } + + if (wire->port_input && instance != nullptr && parent != nullptr) { + for (int i = 0; i < GetSize(sig); i++) { + if (instance->hasPort(wire->name)) + in_parent_drivers.emplace(sig[i], parent->sigmap(instance->getPort(wire->name)[i])); + } + } } memories = Mem::get_all_memories(module); @@ -261,6 +275,11 @@ struct SimInstance ff.past_srst = State::Sx; ff.data = ff_data; ff_database[cell] = ff; + + if (cell->get_bool_attribute(ID(clk2fflogic))) { + for (int i = 0; i < ff_data.width; i++) + clk2fflogic_drivers.emplace(sigmap(ff_data.sig_d[i]), sigmap(ff_data.sig_q[i])); + } } if (cell->is_mem_cell()) @@ -372,6 +391,26 @@ struct SimInstance return did_something; } + void set_state_parent_drivers(SigSpec sig, Const value) + { + sigmap.apply(sig); + + for (int i = 0; i < GetSize(sig); i++) { + auto sigbit = sig[i]; + auto sigval = value[i]; + + auto clk2fflogic_driver = clk2fflogic_drivers.find(sigbit); + if (clk2fflogic_driver != clk2fflogic_drivers.end()) + sigbit = clk2fflogic_driver->second; + + auto in_parent_driver = in_parent_drivers.find(sigbit); + if (in_parent_driver == in_parent_drivers.end()) + set_state(sigbit, sigval); + else + parent->set_state_parent_drivers(in_parent_driver->second, sigval); + } + } + void set_memory_state(IdString memid, Const addr, Const data) { set_memory_state(memid, addr.as_int(), data); @@ -564,7 +603,7 @@ struct SimInstance } } - bool update_ph2(bool gclk) + bool update_ph2(bool gclk, bool stable_past_update = false) { bool did_something = false; @@ -575,7 +614,7 @@ struct SimInstance Const current_q = get_state(ff.data.sig_q); - if (ff_data.has_clk) { + if (ff_data.has_clk && !stable_past_update) { // flip-flops State current_clk = get_state(ff_data.sig_clk)[0]; if (ff_data.pol_clk ? (ff.past_clk == State::S0 && current_clk != State::S0) : @@ -596,7 +635,7 @@ struct SimInstance if (ff_data.has_aload) { State current_aload = get_state(ff_data.sig_aload)[0]; if (current_aload == (ff_data.pol_aload ? State::S1 : State::S0)) { - current_q = ff_data.has_clk ? ff.past_ad : get_state(ff.data.sig_ad); + current_q = ff_data.has_clk && !stable_past_update ? ff.past_ad : get_state(ff.data.sig_ad); } } // async reset @@ -647,6 +686,8 @@ struct SimInstance } else { + if (stable_past_update) + continue; if (port.clk_polarity ? (mdb.past_wr_clk[port_idx] == State::S1 || get_state(port.clk) != State::S1) : (mdb.past_wr_clk[port_idx] == State::S0 || get_state(port.clk) != State::S0)) @@ -676,7 +717,7 @@ struct SimInstance } for (auto it : children) - if (it.second->update_ph2(gclk)) { + if (it.second->update_ph2(gclk, stable_past_update)) { dirty_children.insert(it.second); did_something = true; } @@ -1138,6 +1179,11 @@ struct SimWorker : SimShared } for(auto& writer : outputfiles) writer->write(use_signal); + + if (writeback) { + pool wbmods; + top->writeback(wbmods); + } } void update(bool gclk) @@ -1167,9 +1213,21 @@ struct SimWorker : SimShared void initialize_stable_past() { - if (debug) - log("\n-- ph1 (initialize) --\n"); - top->update_ph1(); + + while (1) + { + if (debug) + log("\n-- ph1 (initialize) --\n"); + + top->update_ph1(); + + if (debug) + log("\n-- ph2 (initialize) --\n"); + + if (!top->update_ph2(false, true)) + break; + } + if (debug) log("\n-- ph3 (initialize) --\n"); top->update_ph3(true); @@ -1241,11 +1299,6 @@ struct SimWorker : SimShared register_output_step(10*numcycles + 2); write_output_files(); - - if (writeback) { - pool wbmods; - top->writeback(wbmods); - } } void run_cosim_fst(Module *topmod, int numcycles) @@ -1370,11 +1423,6 @@ struct SimWorker : SimShared } write_output_files(); - - if (writeback) { - pool wbmods; - top->writeback(wbmods); - } delete fst; } @@ -1760,7 +1808,7 @@ struct SimWorker : SimShared log("yw: set %s to %s\n", signal.path.str().c_str(), log_const(value)); if (found_path.wire != nullptr) { - found_path.instance->set_state( + found_path.instance->set_state_parent_drivers( SigChunk(found_path.wire, signal.offset, signal.width), value); } else if (!found_path.memid.empty()) { diff --git a/yosys/passes/sat/synthprop.cc b/yosys/passes/sat/synthprop.cc new file mode 100644 index 00000000000..25416b6c4c3 --- /dev/null +++ b/yosys/passes/sat/synthprop.cc @@ -0,0 +1,269 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2023 Miodrag Milanovic + * Copyright (C) 2023 + * National Technology & Engineering Solutions of Sandia, LLC (NTESS) + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ +#include "kernel/yosys.h" + +YOSYS_NAMESPACE_BEGIN + +struct TrackingItem +{ + pool assertion_cells; + std::vector names; +}; + +typedef dict TrackingData; + +struct SynthPropWorker +{ + // pointer to main design + RTLIL::Design *design; + + RTLIL::IdString top_name; + + RTLIL::Module *module; + + std::string map_file; + + bool or_outputs; + + IdString port_name; + + IdString reset_name; + + bool reset_pol; + + // basic contrcutor + SynthPropWorker(RTLIL::Design *design) : design(design), or_outputs(false), port_name(RTLIL::escape_id("assertions")) {} + + void tracing(RTLIL::Module *mod, int depth, TrackingData &tracing_data, std::string hier_path); + void run(); +}; + +void SynthPropWorker::tracing(RTLIL::Module *mod, int depth, TrackingData &tracing_data, std::string hier_path) +{ + log("%*sTracing in module %s..\n", 2*depth, "", log_id(mod)); + tracing_data[mod] = TrackingItem(); + int cnt = 0; + for (auto cell : mod->cells()) { + if (cell->type == ID($assert)) { + log("%*sFound assert %s..\n", 2*(depth+1), "", log_id(cell)); + tracing_data[mod].assertion_cells.emplace(cell); + if (!or_outputs) { + tracing_data[mod].names.push_back(hier_path + "." + log_id(cell)); + } + cnt++; + } + else if (RTLIL::Module *submod = design->module(cell->type)) { + tracing(submod, depth+1, tracing_data, hier_path + "." + log_id(cell)); + if (!or_outputs) { + for (size_t i = 0; i < tracing_data[submod].names.size(); i++) + tracing_data[mod].names.push_back(tracing_data[submod].names[i]); + } else { + cnt += tracing_data[submod].names.size(); + } + } + } + if (or_outputs && (cnt > 0)) { + tracing_data[mod].names.push_back("merged_asserts"); + } +} + +void SynthPropWorker::run() +{ + if (!module->get_bool_attribute(ID::top)) + log_error("Module is not TOP module\n"); + + TrackingData tracing_data; + tracing(module, 0, tracing_data, log_id(module->name)); + + for (auto &data : tracing_data) { + if (data.second.names.size() == 0) continue; + RTLIL::Wire *wire = data.first->addWire(port_name, data.second.names.size()); + wire->port_output = true; + data.first->fixup_ports(); + } + + RTLIL::Wire *output = nullptr; + for (auto &data : tracing_data) { + int num = 0; + RTLIL::Wire *port_wire = data.first->wire(port_name); + if (!reset_name.empty() && data.first == module) { + port_wire = data.first->addWire(NEW_ID, data.second.names.size()); + output = port_wire; + } + pool connected; + for (auto cell : data.second.assertion_cells) { + if (cell->type == ID($assert)) { + RTLIL::Wire *neg_wire = data.first->addWire(NEW_ID); + RTLIL::Wire *result_wire = data.first->addWire(NEW_ID); + data.first->addNot(NEW_ID, cell->getPort(ID::A), neg_wire); + data.first->addAnd(NEW_ID, cell->getPort(ID::EN), neg_wire, result_wire); + if (!or_outputs) { + data.first->connect(SigBit(port_wire,num), result_wire); + } else { + connected.emplace(result_wire); + } + num++; + } + } + + for (auto cell : data.first->cells()) { + if (RTLIL::Module *submod = design->module(cell->type)) { + if (tracing_data[submod].names.size() > 0) { + if (!or_outputs) { + cell->setPort(port_name, SigChunk(port_wire, num, tracing_data[submod].names.size())); + } else { + RTLIL::Wire *result_wire = data.first->addWire(NEW_ID); + cell->setPort(port_name, result_wire); + connected.emplace(result_wire); + } + num += tracing_data[submod].names.size(); + } + } + } + if (or_outputs && connected.size() > 0) { + RTLIL::Wire *prev_wire = nullptr; + for (auto wire : connected ) { + if (!prev_wire) { + prev_wire = wire; + } else { + RTLIL::Wire *result = data.first->addWire(NEW_ID); + data.first->addOr(NEW_ID, prev_wire, wire, result); + prev_wire = result; + } + } + data.first->connect(port_wire, prev_wire); + } + } + + // If no assertions found + if (tracing_data[module].names.size() == 0) return; + + if (!reset_name.empty()) { + int width = tracing_data[module].names.size(); + SigSpec reset = module->wire(reset_name); + reset.extend_u0(width, true); + + module->addDlatchsr(NEW_ID, State::S1, Const(State::S0,width), reset, output, module->wire(port_name), true, true, reset_pol); + } + + if (!map_file.empty()) { + std::ofstream fout; + fout.open(map_file, std::ios::out | std::ios::trunc); + if (!fout.is_open()) + log_error("Could not open file \"%s\" with write access.\n", map_file.c_str()); + + for (auto name : tracing_data[module].names) { + fout << name << std::endl; + } + } +} + +struct SyntProperties : public Pass { + SyntProperties() : Pass("synthprop", "synthesize SVA properties") { } + + virtual void help() + { + // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| + log("\n"); + log(" synthprop [options]\n"); + log("\n"); + log("This creates synthesizable properties for selected module.\n"); + log("\n"); + log("\n"); + log(" -name \n"); + log("\n"); + log("Name output port for assertions (default: assertions).\n"); + log("\n"); + log("\n"); + log(" -map \n"); + log("\n"); + log("Write port mapping for synthesizable properties.\n"); + log("\n"); + log("\n"); + log(" -or_outputs\n"); + log("\n"); + log("Or all outputs together to create a single output that goes high when any\n"); + log("property is violated, instead of generating individual output bits.\n"); + log("\n"); + log("\n"); + log(" -reset \n"); + log("\n"); + log("Name of top-level reset input. Latch a high state on the generated outputs\n"); + log("until an asynchronous top-level reset input is activated.\n"); + log("\n"); + log("\n"); + log(" -resetn \n"); + log("\n"); + log("Name of top-level reset input (inverse polarity). Latch a high state on the\n"); + log("generated outputs until an asynchronous top-level reset input is activated.\n"); + log("\n"); + log("\n"); + } + + virtual void execute(std::vector args, RTLIL::Design* design) + { + log_header(design, "Executing SYNTHPROP pass.\n"); + SynthPropWorker worker(design); + size_t argidx; + for (argidx = 1; argidx < args.size(); argidx++) + { + if (args[argidx] == "-name" && argidx+1 < args.size()) { + worker.port_name = RTLIL::escape_id(args[++argidx]); + continue; + } + if (args[argidx] == "-map" && argidx+1 < args.size()) { + worker.map_file = args[++argidx]; + continue; + } + if (args[argidx] == "-reset" && argidx+1 < args.size()) { + worker.reset_name = RTLIL::escape_id(args[++argidx]); + worker.reset_pol = true; + continue; + } + if (args[argidx] == "-resetn" && argidx+1 < args.size()) { + worker.reset_name = RTLIL::escape_id(args[++argidx]); + worker.reset_pol = false; + continue; + } + if (args[argidx] == "-or_outputs") { + worker.or_outputs = true; + continue; + } + break; + } + + if (args.size() != argidx) + cmd_error(args, argidx, "Extra argument."); + + auto *top = design->top_module(); + if (top == nullptr) + log_cmd_error("Can't find top module in current design!\n"); + + auto *reset = top->wire(worker.reset_name); + if (!worker.reset_name.empty() && reset == nullptr) + log_cmd_error("Can't find reset line in current design!\n"); + + worker.module = top; + worker.run(); + } +} SyntProperties; + +YOSYS_NAMESPACE_END diff --git a/yosys/passes/techmap/abc.cc b/yosys/passes/techmap/abc.cc index da601a85606..364a8e54458 100644 --- a/yosys/passes/techmap/abc.cc +++ b/yosys/passes/techmap/abc.cc @@ -1095,6 +1095,24 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin abc_output_filter filt(tempdir_name, show_tempdir); int ret = run_command(buffer, std::bind(&abc_output_filter::next_line, filt, std::placeholders::_1)); #else + string temp_stdouterr_name = stringf("%s/stdouterr.txt", tempdir_name.c_str()); + FILE *temp_stdouterr_w = fopen(temp_stdouterr_name.c_str(), "w"); + if (temp_stdouterr_w == NULL) + log_error("ABC: cannot open a temporary file for output redirection"); + fflush(stdout); + fflush(stderr); + FILE *old_stdout = fopen(temp_stdouterr_name.c_str(), "r"); // need any fd for renumbering + FILE *old_stderr = fopen(temp_stdouterr_name.c_str(), "r"); // need any fd for renumbering +#if defined(__wasm) +#define fd_renumber(from, to) (void)__wasi_fd_renumber(from, to) +#else +#define fd_renumber(from, to) dup2(from, to) +#endif + fd_renumber(fileno(stdout), fileno(old_stdout)); + fd_renumber(fileno(stderr), fileno(old_stderr)); + fd_renumber(fileno(temp_stdouterr_w), fileno(stdout)); + fd_renumber(fileno(temp_stdouterr_w), fileno(stderr)); + fclose(temp_stdouterr_w); // These needs to be mutable, supposedly due to getopt char *abc_argv[5]; string tmp_script_name = stringf("%s/abc.script", tempdir_name.c_str()); @@ -1108,6 +1126,17 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin free(abc_argv[1]); free(abc_argv[2]); free(abc_argv[3]); + fflush(stdout); + fflush(stderr); + fd_renumber(fileno(old_stdout), fileno(stdout)); + fd_renumber(fileno(old_stderr), fileno(stderr)); + fclose(old_stdout); + fclose(old_stderr); + std::ifstream temp_stdouterr_r(temp_stdouterr_name); + abc_output_filter filt(tempdir_name, show_tempdir); + for (std::string line; std::getline(temp_stdouterr_r, line); ) + filt.next_line(line + "\n"); + temp_stdouterr_r.close(); #endif if (ret != 0) log_error("ABC: execution of command \"%s\" failed: return code %d.\n", buffer.c_str(), ret); diff --git a/yosys/passes/techmap/abc9_exe.cc b/yosys/passes/techmap/abc9_exe.cc index 1d9bb433211..8e02e25a4bf 100644 --- a/yosys/passes/techmap/abc9_exe.cc +++ b/yosys/passes/techmap/abc9_exe.cc @@ -271,6 +271,24 @@ void abc9_module(RTLIL::Design *design, std::string script_file, std::string exe abc9_output_filter filt(tempdir_name, show_tempdir); int ret = run_command(buffer, std::bind(&abc9_output_filter::next_line, filt, std::placeholders::_1)); #else + string temp_stdouterr_name = stringf("%s/stdouterr.txt", tempdir_name.c_str()); + FILE *temp_stdouterr_w = fopen(temp_stdouterr_name.c_str(), "w"); + if (temp_stdouterr_w == NULL) + log_error("ABC: cannot open a temporary file for output redirection"); + fflush(stdout); + fflush(stderr); + FILE *old_stdout = fopen(temp_stdouterr_name.c_str(), "r"); // need any fd for renumbering + FILE *old_stderr = fopen(temp_stdouterr_name.c_str(), "r"); // need any fd for renumbering +#if defined(__wasm) +#define fd_renumber(from, to) (void)__wasi_fd_renumber(from, to) +#else +#define fd_renumber(from, to) dup2(from, to) +#endif + fd_renumber(fileno(stdout), fileno(old_stdout)); + fd_renumber(fileno(stderr), fileno(old_stderr)); + fd_renumber(fileno(temp_stdouterr_w), fileno(stdout)); + fd_renumber(fileno(temp_stdouterr_w), fileno(stderr)); + fclose(temp_stdouterr_w); // These needs to be mutable, supposedly due to getopt char *abc9_argv[5]; string tmp_script_name = stringf("%s/abc.script", tempdir_name.c_str()); @@ -284,6 +302,17 @@ void abc9_module(RTLIL::Design *design, std::string script_file, std::string exe free(abc9_argv[1]); free(abc9_argv[2]); free(abc9_argv[3]); + fflush(stdout); + fflush(stderr); + fd_renumber(fileno(old_stdout), fileno(stdout)); + fd_renumber(fileno(old_stderr), fileno(stderr)); + fclose(old_stdout); + fclose(old_stderr); + std::ifstream temp_stdouterr_r(temp_stdouterr_name); + abc9_output_filter filt(tempdir_name, show_tempdir); + for (std::string line; std::getline(temp_stdouterr_r, line); ) + filt.next_line(line + "\n"); + temp_stdouterr_r.close(); #endif if (ret != 0) { if (check_file_exists(stringf("%s/output.aig", tempdir_name.c_str()))) diff --git a/yosys/passes/techmap/abc9_ops.cc b/yosys/passes/techmap/abc9_ops.cc index 9766e81cbf0..4eaed1f75dc 100644 --- a/yosys/passes/techmap/abc9_ops.cc +++ b/yosys/passes/techmap/abc9_ops.cc @@ -233,22 +233,23 @@ void prep_hier(RTLIL::Design *design, bool dff_mode) if (derived_type != cell->type) { auto unmap_module = unmap_design->addModule(derived_type); + auto replace_cell = unmap_module->addCell(ID::_TECHMAP_REPLACE_, cell->type); for (auto port : derived_module->ports) { auto w = unmap_module->addWire(port, derived_module->wire(port)); // Do not propagate (* init *) values into the box, // in fact, remove it from outside too if (w->port_output) w->attributes.erase(ID::init); + // Attach (* techmap_autopurge *) to all ports to ensure that + // undriven inputs/unused outputs are propagated through to + // the techmapped cell + w->attributes[ID::techmap_autopurge] = 1; + + replace_cell->setPort(port, w); } unmap_module->ports = derived_module->ports; unmap_module->check(); - auto replace_cell = unmap_module->addCell(ID::_TECHMAP_REPLACE_, cell->type); - for (const auto &conn : cell->connections()) { - auto w = unmap_module->wire(conn.first); - log_assert(w); - replace_cell->setPort(conn.first, w); - } replace_cell->parameters = cell->parameters; } } @@ -674,8 +675,12 @@ void prep_delays(RTLIL::Design *design, bool dff_mode) continue; auto offset = i.first.offset; - auto O = module->addWire(NEW_ID); + if (!cell->hasPort(i.first.name)) + continue; auto rhs = cell->getPort(i.first.name); + if (offset >= rhs.size()) + continue; + auto O = module->addWire(NEW_ID); #ifndef NDEBUG if (ys_debug(1)) { diff --git a/yosys/passes/techmap/dfflegalize.cc b/yosys/passes/techmap/dfflegalize.cc index c6c3a58c588..64f07b708c6 100644 --- a/yosys/passes/techmap/dfflegalize.cc +++ b/yosys/passes/techmap/dfflegalize.cc @@ -1021,8 +1021,8 @@ struct DffLegalizePass : public Pass { supported_cells_neg[i][j] = 0; supported_cells[i] = 0; } - mince = 0; - minsrst = 0; + mince = design->scratchpad_get_int("dfflegalize.mince", 0); + minsrst = design->scratchpad_get_int("dfflegalize.minsrst", 0); size_t argidx; for (argidx = 1; argidx < args.size(); argidx++) diff --git a/yosys/passes/techmap/extract_counter.cc b/yosys/passes/techmap/extract_counter.cc index 9c814af231b..b780f7df06c 100644 --- a/yosys/passes/techmap/extract_counter.cc +++ b/yosys/passes/techmap/extract_counter.cc @@ -120,8 +120,6 @@ struct CounterExtractionSettings }; //attempt to extract a counter centered on the given adder cell -//For now we only support DOWN counters. -//TODO: up/down support int counter_tryextract( ModIndex& index, Cell *cell, @@ -766,9 +764,9 @@ struct ExtractCounterPass : public Pass { log("\n"); log(" extract_counter [options] [selection]\n"); log("\n"); - log("This pass converts non-resettable or async resettable down counters to\n"); - log("counter cells. Use a target-specific 'techmap' map file to convert those cells\n"); - log("to the actual target cells.\n"); + log("This pass converts non-resettable or async resettable counters to counter cells.\n"); + log("Use a target-specific 'techmap' map file to convert those cells to the actual\n"); + log("target cells.\n"); log("\n"); log(" -maxwidth N\n"); log(" Only extract counters up to N bits wide (default 64)\n"); diff --git a/yosys/passes/techmap/libparse.cc b/yosys/passes/techmap/libparse.cc index 3d0ebaea366..efe00c105e4 100644 --- a/yosys/passes/techmap/libparse.cc +++ b/yosys/passes/techmap/libparse.cc @@ -236,10 +236,10 @@ LibertyAst *LibertyParser::parse() if (tok == ':' && ast->value.empty()) { tok = lexer(ast->value); - if (tok != 'v') - error(); - tok = lexer(str); - while (tok == '+' || tok == '-' || tok == '*' || tok == '/') { + if (tok == 'v') { + tok = lexer(str); + } + while (tok == '+' || tok == '-' || tok == '*' || tok == '/' || tok == '!') { ast->value += tok; tok = lexer(str); if (tok != 'v') @@ -314,8 +314,7 @@ LibertyAst *LibertyParser::parse() switch(tok) { case 'n': - error("Unexpected newline."); - break; + continue; case '[': case ']': case '}': diff --git a/yosys/passes/techmap/muxcover.cc b/yosys/passes/techmap/muxcover.cc index a90d8198578..2656f30ce56 100644 --- a/yosys/passes/techmap/muxcover.cc +++ b/yosys/passes/techmap/muxcover.cc @@ -179,7 +179,7 @@ struct MuxcoverWorker int prepare_decode_mux(SigBit &A, SigBit B, SigBit sel, SigBit bit) { - if (A == B || sel == State::Sx) + if (A == B || A == State::Sx || B == State::Sx || sel == State::Sx) return 0; tuple key(A, B, sel); @@ -197,9 +197,6 @@ struct MuxcoverWorker if (std::get<2>(entry)) return 0; - if (A == State::Sx || B == State::Sx) - return 0; - return cost_dmux / GetSize(std::get<1>(entry)); } diff --git a/yosys/techlibs/ecp5/cells_bb.v b/yosys/techlibs/ecp5/cells_bb.v index fc352a52c5c..316671f3ce1 100644 --- a/yosys/techlibs/ecp5/cells_bb.v +++ b/yosys/techlibs/ecp5/cells_bb.v @@ -187,8 +187,16 @@ endmodule (* blackbox *) (* keep *) module JTAGG( - input TCK, TMS, TDI, JTDO2, JTDO1, - output TDO, JTDI, JTCK, JRTI2, JRTI1, + (* iopad_external_pin *) + input TCK, + (* iopad_external_pin *) + input TMS, + (* iopad_external_pin *) + input TDI, + input JTDO2, JTDO1, + (* iopad_external_pin *) + output TDO, + output JTDI, JTCK, JRTI2, JRTI1, output JSHIFT, JUPDATE, JRSTN, JCE2, JCE1 ); parameter ER1 = "ENABLED"; @@ -390,7 +398,14 @@ endmodule (* blackbox *) (* keep *) module DCUA( - input CH0_HDINP, CH1_HDINP, CH0_HDINN, CH1_HDINN, + (* iopad_external_pin *) + input CH0_HDINP, + (* iopad_external_pin *) + input CH1_HDINP, + (* iopad_external_pin *) + input CH0_HDINN, + (* iopad_external_pin *) + input CH1_HDINN, input D_TXBIT_CLKP_FROM_ND, D_TXBIT_CLKN_FROM_ND, D_SYNC_ND, D_TXPLL_LOL_FROM_ND, input CH0_RX_REFCLK, CH1_RX_REFCLK, CH0_FF_RXI_CLK, CH1_FF_RXI_CLK, CH0_FF_TXI_CLK, CH1_FF_TXI_CLK, CH0_FF_EBRD_CLK, CH1_FF_EBRD_CLK, input CH0_FF_TX_D_0, CH1_FF_TX_D_0, CH0_FF_TX_D_1, CH1_FF_TX_D_1, CH0_FF_TX_D_2, CH1_FF_TX_D_2, CH0_FF_TX_D_3, CH1_FF_TX_D_3, @@ -701,7 +716,10 @@ endmodule (* blackbox *) module EXTREFB ( - input REFCLKP, REFCLKN, + (* iopad_external_pin *) + input REFCLKP, + (* iopad_external_pin *) + input REFCLKN, output REFCLKO ); parameter REFCK_PWDNB = "0b0"; diff --git a/yosys/techlibs/ecp5/cells_io.vh b/yosys/techlibs/ecp5/cells_io.vh index 02e66e8a579..220460c4467 100644 --- a/yosys/techlibs/ecp5/cells_io.vh +++ b/yosys/techlibs/ecp5/cells_io.vh @@ -1,14 +1,14 @@ // Diamond I/O buffers -module IB (input I, output O); (* PULLMODE="NONE" *) TRELLIS_IO #(.DIR("INPUT")) _TECHMAP_REPLACE_ (.B(I), .O(O)); endmodule -module IBPU (input I, output O); (* PULLMODE="UP" *) TRELLIS_IO #(.DIR("INPUT")) _TECHMAP_REPLACE_ (.B(I), .O(O)); endmodule -module IBPD (input I, output O); (* PULLMODE="DOWN" *) TRELLIS_IO #(.DIR("INPUT")) _TECHMAP_REPLACE_ (.B(I), .O(O)); endmodule -module OB (input I, output O); (* PULLMODE="NONE" *) TRELLIS_IO #(.DIR("OUTPUT")) _TECHMAP_REPLACE_ (.B(O), .I(I)); endmodule -module OBZ (input I, T, output O); (* PULLMODE="NONE" *) TRELLIS_IO #(.DIR("OUTPUT")) _TECHMAP_REPLACE_ (.B(O), .I(I), .T(T)); endmodule -module OBZPU(input I, T, output O); (* PULLMODE="UP" *) TRELLIS_IO #(.DIR("OUTPUT")) _TECHMAP_REPLACE_ (.B(O), .I(I), .T(T)); endmodule -module OBZPD(input I, T, output O); (* PULLMODE="DOWN" *) TRELLIS_IO #(.DIR("OUTPUT")) _TECHMAP_REPLACE_ (.B(O), .I(I), .T(T)); endmodule +module IB ((* iopad_external_pin *) input I, output O); (* PULLMODE="NONE" *) TRELLIS_IO #(.DIR("INPUT")) _TECHMAP_REPLACE_ (.B(I), .O(O)); endmodule +module IBPU ((* iopad_external_pin *) input I, output O); (* PULLMODE="UP" *) TRELLIS_IO #(.DIR("INPUT")) _TECHMAP_REPLACE_ (.B(I), .O(O)); endmodule +module IBPD ((* iopad_external_pin *) input I, output O); (* PULLMODE="DOWN" *) TRELLIS_IO #(.DIR("INPUT")) _TECHMAP_REPLACE_ (.B(I), .O(O)); endmodule +module OB (input I, (* iopad_external_pin *) output O); (* PULLMODE="NONE" *) TRELLIS_IO #(.DIR("OUTPUT")) _TECHMAP_REPLACE_ (.B(O), .I(I)); endmodule +module OBZ (input I, T, (* iopad_external_pin *) output O); (* PULLMODE="NONE" *) TRELLIS_IO #(.DIR("OUTPUT")) _TECHMAP_REPLACE_ (.B(O), .I(I), .T(T)); endmodule +module OBZPU(input I, T, (* iopad_external_pin *) output O); (* PULLMODE="UP" *) TRELLIS_IO #(.DIR("OUTPUT")) _TECHMAP_REPLACE_ (.B(O), .I(I), .T(T)); endmodule +module OBZPD(input I, T, (* iopad_external_pin *) output O); (* PULLMODE="DOWN" *) TRELLIS_IO #(.DIR("OUTPUT")) _TECHMAP_REPLACE_ (.B(O), .I(I), .T(T)); endmodule module OBCO (input I, output OT, OC); OLVDS olvds (.A(I), .Z(OT), .ZN(OC)); endmodule -module BB (input I, T, output O, inout B); (* PULLMODE="NONE" *) TRELLIS_IO #(.DIR("BIDIR")) _TECHMAP_REPLACE_ (.B(B), .I(I), .O(O), .T(T)); endmodule -module BBPU (input I, T, output O, inout B); (* PULLMODE="UP" *) TRELLIS_IO #(.DIR("BIDIR")) _TECHMAP_REPLACE_ (.B(B), .I(I), .O(O), .T(T)); endmodule -module BBPD (input I, T, output O, inout B); (* PULLMODE="DOWN" *) TRELLIS_IO #(.DIR("BIDIR")) _TECHMAP_REPLACE_ (.B(B), .I(I), .O(O), .T(T)); endmodule -module ILVDS(input A, AN, output Z ); TRELLIS_IO #(.DIR("INPUT")) _TECHMAP_REPLACE_ (.B(A), .O(Z)); endmodule -module OLVDS(input A, output Z, ZN); TRELLIS_IO #(.DIR("OUTPUT")) _TECHMAP_REPLACE_ (.B(Z), .I(A)); endmodule +module BB (input I, T, output O, (* iopad_external_pin *) inout B); (* PULLMODE="NONE" *) TRELLIS_IO #(.DIR("BIDIR")) _TECHMAP_REPLACE_ (.B(B), .I(I), .O(O), .T(T)); endmodule +module BBPU (input I, T, output O, (* iopad_external_pin *) inout B); (* PULLMODE="UP" *) TRELLIS_IO #(.DIR("BIDIR")) _TECHMAP_REPLACE_ (.B(B), .I(I), .O(O), .T(T)); endmodule +module BBPD (input I, T, output O, (* iopad_external_pin *) inout B); (* PULLMODE="DOWN" *) TRELLIS_IO #(.DIR("BIDIR")) _TECHMAP_REPLACE_ (.B(B), .I(I), .O(O), .T(T)); endmodule +module ILVDS(input A, AN, (* iopad_external_pin *) output Z ); TRELLIS_IO #(.DIR("INPUT")) _TECHMAP_REPLACE_ (.B(A), .O(Z)); endmodule +module OLVDS(input A, (* iopad_external_pin *) output Z, output ZN); TRELLIS_IO #(.DIR("OUTPUT")) _TECHMAP_REPLACE_ (.B(Z), .I(A)); endmodule diff --git a/yosys/techlibs/ecp5/cells_sim.v b/yosys/techlibs/ecp5/cells_sim.v index f9d503deb7a..950d12c9130 100644 --- a/yosys/techlibs/ecp5/cells_sim.v +++ b/yosys/techlibs/ecp5/cells_sim.v @@ -378,6 +378,7 @@ endmodule // --------------------------------------- (* keep *) module TRELLIS_IO( + (* iopad_external_pin *) inout B, input I, input T, @@ -412,177 +413,47 @@ endmodule // --------------------------------------- -module TRELLIS_SLICE( - input A0, B0, C0, D0, - input A1, B1, C1, D1, - input M0, M1, - input FCI, FXA, FXB, - - input CLK, LSR, CE, - input DI0, DI1, - - input WD0, WD1, +module TRELLIS_COMB( + input A, B, C, D, M, + input FCI, F1, FXA, FXB, + input WD, input WAD0, WAD1, WAD2, WAD3, input WRE, WCK, - - output F0, Q0, - output F1, Q1, - output FCO, OFX0, OFX1, - - output WDO0, WDO1, WDO2, WDO3, - output WADO0, WADO1, WADO2, WADO3 + output F, FCO, OFX ); - parameter MODE = "LOGIC"; - parameter GSR = "ENABLED"; - parameter SRMODE = "LSR_OVER_CE"; - parameter [127:0] CEMUX = "1"; - parameter CLKMUX = "CLK"; - parameter LSRMUX = "LSR"; - parameter LUT0_INITVAL = 16'h0000; - parameter LUT1_INITVAL = 16'h0000; - parameter REG0_SD = "0"; - parameter REG1_SD = "0"; - parameter REG0_REGSET = "RESET"; - parameter REG1_REGSET = "RESET"; - parameter REG0_LSRMODE = "LSR"; - parameter REG1_LSRMODE = "LSR"; - parameter [127:0] CCU2_INJECT1_0 = "NO"; - parameter [127:0] CCU2_INJECT1_1 = "NO"; + parameter INITVAL = 16'h0; + parameter CCU2_INJECT1 = "NO"; parameter WREMUX = "WRE"; - parameter WCKMUX = "WCK"; - - parameter A0MUX = "A0"; - parameter A1MUX = "A1"; - parameter B0MUX = "B0"; - parameter B1MUX = "B1"; - parameter C0MUX = "C0"; - parameter C1MUX = "C1"; - parameter D0MUX = "D0"; - parameter D1MUX = "D1"; - - wire A0m, B0m, C0m, D0m; - wire A1m, B1m, C1m, D1m; + parameter IS_Z1 = 1'b0; generate - if (A0MUX == "1") assign A0m = 1'b1; else assign A0m = A0; - if (B0MUX == "1") assign B0m = 1'b1; else assign B0m = B0; - if (C0MUX == "1") assign C0m = 1'b1; else assign C0m = C0; - if (D0MUX == "1") assign D0m = 1'b1; else assign D0m = D0; - if (A1MUX == "1") assign A1m = 1'b1; else assign A1m = A1; - if (B1MUX == "1") assign B1m = 1'b1; else assign B1m = B1; - if (C1MUX == "1") assign C1m = 1'b1; else assign C1m = C1; - if (D1MUX == "1") assign D1m = 1'b1; else assign D1m = D1; - - endgenerate - - function [15:0] permute_initval; - input [15:0] initval; - integer i; - begin - for (i = 0; i < 16; i = i + 1) begin - permute_initval[{i[0], i[2], i[1], i[3]}] = initval[i]; - end - end - endfunction - - generate - if (MODE == "LOGIC") begin - // LUTs - LUT4 #( - .INIT(LUT0_INITVAL) - ) lut4_0 ( - .A(A0m), .B(B0m), .C(C0m), .D(D0m), - .Z(F0) - ); - LUT4 #( - .INIT(LUT1_INITVAL) - ) lut4_1 ( - .A(A1m), .B(B1m), .C(C1m), .D(D1m), - .Z(F1) - ); - // LUT expansion muxes - PFUMX lut5_mux (.ALUT(F1), .BLUT(F0), .C0(M0), .Z(OFX0)); - L6MUX21 lutx_mux (.D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); - end else if (MODE == "CCU2") begin - CCU2C #( - .INIT0(LUT0_INITVAL), - .INIT1(LUT1_INITVAL), - .INJECT1_0(CCU2_INJECT1_0), - .INJECT1_1(CCU2_INJECT1_1) - ) ccu2c_i ( - .CIN(FCI), - .A0(A0m), .B0(B0m), .C0(C0m), .D0(D0m), - .A1(A1m), .B1(B1m), .C1(C1m), .D1(D1m), - .S0(F0), .S1(F1), - .COUT(FCO) - ); - end else if (MODE == "RAMW") begin - assign WDO0 = C1m; - assign WDO1 = A1m; - assign WDO2 = D1m; - assign WDO3 = B1m; - assign WADO0 = D0m; - assign WADO1 = B0m; - assign WADO2 = C0m; - assign WADO3 = A0m; - end else if (MODE == "DPRAM") begin - TRELLIS_RAM16X2 #( - .INITVAL_0(permute_initval(LUT0_INITVAL)), - .INITVAL_1(permute_initval(LUT1_INITVAL)), - .WREMUX(WREMUX) - ) ram_i ( - .DI0(WD0), .DI1(WD1), - .WAD0(WAD0), .WAD1(WAD1), .WAD2(WAD2), .WAD3(WAD3), - .WRE(WRE), .WCK(WCK), - .RAD0(D0m), .RAD1(B0m), .RAD2(C0m), .RAD3(A0m), - .DO0(F0), .DO1(F1) - ); - // TODO: confirm RAD and INITVAL ordering - // DPRAM mode contract? -`ifdef FORMAL - always @(*) begin - assert(A0m==A1m); - assert(B0m==B1m); - assert(C0m==C1m); - assert(D0m==D1m); - end -`endif + if (MODE == "LOGIC") begin: mode_logic + LUT4 #(.INIT(INITVAL)) lut4 (.A(A), .B(B), .C(C), .D(D), .Z(F)); + end else if (MODE == "CCU2") begin: mode_ccu2 + wire l4o, l2o; + LUT4 #(.INIT(INITVAL)) lut4_0(.A(A), .B(B), .C(C), .D(D), .Z(l4o)); + LUT2 #(.INIT(INITVAL[3:0])) lut2_0(.A(A), .B(B), .Z(l2o)); + wire gated_cin_0 = (CCU2_INJECT1 == "YES") ? 1'b0 : FCI; + assign F = l4o ^ gated_cin_0; + wire gated_lut2_0 = (CCU2_INJECT1 == "YES") ? 1'b0 : l2o; + wire FCO = (~l4o & gated_lut2_0) | (l4o & FCI); + end else if (MODE == "DPRAM") begin: mode_dpram + reg [15:0] ram = INITVAL; + always @(posedge WCK) + if (WRE) + ram[{WAD3, WAD2, WAD1, WAD0}] <= WD; + assign F = ram[{A, C, B, D}]; end else begin - ERROR_UNKNOWN_SLICE_MODE error(); + $error("unsupported COMB mode %s", MODE); end + + if (IS_Z1) + L6MUX21 lutx_mux (.D0(FXA), .D1(FXB), .SD(M), .Z(OFX)); + else + PFUMX lut5_mux (.ALUT(F1), .BLUT(F), .C0(M), .Z(OFX)); endgenerate - // FF input selection muxes - wire muxdi0 = (REG0_SD == "1") ? DI0 : M0; - wire muxdi1 = (REG1_SD == "1") ? DI1 : M1; - // Flipflops - TRELLIS_FF #( - .GSR(GSR), - .CEMUX(CEMUX), - .CLKMUX(CLKMUX), - .LSRMUX(LSRMUX), - .SRMODE(SRMODE), - .REGSET(REG0_REGSET), - .LSRMODE(REG0_LSRMODE) - ) ff_0 ( - .CLK(CLK), .LSR(LSR), .CE(CE), - .DI(muxdi0), .M(M0), - .Q(Q0) - ); - TRELLIS_FF #( - .GSR(GSR), - .CEMUX(CEMUX), - .CLKMUX(CLKMUX), - .LSRMUX(LSRMUX), - .SRMODE(SRMODE), - .REGSET(REG1_REGSET), - .LSRMODE(REG1_LSRMODE) - ) ff_1 ( - .CLK(CLK), .LSR(LSR), .CE(CE), - .DI(muxdi1), .M(M1), - .Q(Q1) - ); endmodule (* blackbox *) diff --git a/yosys/techlibs/ecp5/synth_ecp5.cc b/yosys/techlibs/ecp5/synth_ecp5.cc index f2dc534f90e..82e23486844 100644 --- a/yosys/techlibs/ecp5/synth_ecp5.cc +++ b/yosys/techlibs/ecp5/synth_ecp5.cc @@ -100,6 +100,9 @@ struct SynthEcp5Pass : public ScriptPass log(" generate an output netlist (and BLIF file) suitable for VPR\n"); log(" (this feature is experimental and incomplete)\n"); log("\n"); + log(" -iopad\n"); + log(" insert IO buffers\n"); + log("\n"); log(" -nodsp\n"); log(" do not map multipliers to MULT18X18D\n"); log("\n"); @@ -115,7 +118,7 @@ struct SynthEcp5Pass : public ScriptPass } string top_opt, blif_file, edif_file, json_file; - bool noccu2, nodffe, nobram, nolutram, nowidelut, asyncprld, flatten, dff, retime, abc2, abc9, nodsp, vpr, no_rw_check; + bool noccu2, nodffe, nobram, nolutram, nowidelut, asyncprld, flatten, dff, retime, abc2, abc9, iopad, nodsp, vpr, no_rw_check; void clear_flags() override { @@ -135,6 +138,7 @@ struct SynthEcp5Pass : public ScriptPass abc2 = false; vpr = false; abc9 = false; + iopad = false; nodsp = false; no_rw_check = false; } @@ -223,6 +227,10 @@ struct SynthEcp5Pass : public ScriptPass abc9 = true; continue; } + if (args[argidx] == "-iopad") { + iopad = true; + continue; + } if (args[argidx] == "-nodsp") { nodsp = true; continue; @@ -319,6 +327,11 @@ struct SynthEcp5Pass : public ScriptPass run("techmap"); else run("techmap -map +/techmap.v -map +/ecp5/arith_map.v"); + if (help_mode || iopad) { + run("iopadmap -bits -outpad OB I:O -inpad IB O:I -toutpad OBZ ~T:I:O -tinoutpad BB ~T:O:I:B A:top", "(only if '-iopad')"); + run("attrmvcp -attr src -attr LOC t:OB %x:+[O] t:OBZ %x:+[O] t:BB %x:+[B]"); + run("attrmvcp -attr src -attr LOC -driven t:IB %x:+[I]"); + } run("opt -fast"); if (retime || help_mode) run("abc -dff -D 1", "(only if -retime)"); diff --git a/yosys/techlibs/fabulous/Makefile.inc b/yosys/techlibs/fabulous/Makefile.inc index 44d57542b90..28b0d5ef026 100644 --- a/yosys/techlibs/fabulous/Makefile.inc +++ b/yosys/techlibs/fabulous/Makefile.inc @@ -8,3 +8,4 @@ $(eval $(call add_share_file,share/fabulous,techlibs/fabulous/ff_map.v)) $(eval $(call add_share_file,share/fabulous,techlibs/fabulous/ram_regfile.txt)) $(eval $(call add_share_file,share/fabulous,techlibs/fabulous/regfile_map.v)) $(eval $(call add_share_file,share/fabulous,techlibs/fabulous/io_map.v)) +$(eval $(call add_share_file,share/fabulous,techlibs/fabulous/arith_map.v)) diff --git a/yosys/techlibs/fabulous/arith_map.v b/yosys/techlibs/fabulous/arith_map.v new file mode 100644 index 00000000000..eca96855693 --- /dev/null +++ b/yosys/techlibs/fabulous/arith_map.v @@ -0,0 +1,65 @@ +`default_nettype none + +`ifdef ARITH_ha +(* techmap_celltype = "$alu" *) +module _80_fabulous_ha_alu (A, B, CI, BI, X, Y, CO); + +parameter A_SIGNED = 0; +parameter B_SIGNED = 0; +parameter A_WIDTH = 1; +parameter B_WIDTH = 1; +parameter Y_WIDTH = 1; + +parameter _TECHMAP_CONSTMSK_CI_ = 0; +parameter _TECHMAP_CONSTVAL_CI_ = 0; + +(* force_downto *) +input [A_WIDTH-1:0] A; +(* force_downto *) +input [B_WIDTH-1:0] B; +input CI, BI; +(* force_downto *) +output [Y_WIDTH-1:0] X, Y, CO; + +(* force_downto *) +wire [Y_WIDTH-1:0] A_buf, B_buf; +\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf)); +\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf)); + +(* force_downto *) +wire [Y_WIDTH-1:0] AA = A_buf; +(* force_downto *) +wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf; +wire [Y_WIDTH:0] CARRY; + + +LUT4_HA #( + .INIT(16'b0), + .I0MUX(1'b1) +) carry_statrt ( + .I0(), .I1(CI), .I2(CI), .I3(), + .Ci(), + .Co(CARRY[0]) +); + +// Carry chain +genvar i; +generate for (i = 0; i < Y_WIDTH; i = i + 1) begin:slice + LUT4_HA #( + .INIT(16'b1001_0110_1001_0110), // full adder sum over (I2, I1, I0) + .I0MUX(1'b1) + ) lut_i ( + .I0(), .I1(AA[i]), .I2(BB[i]), .I3(), + .Ci(CARRY[i]), + .O(Y[i]), + .Co(CARRY[i+1]) + ); + + assign CO[i] = (AA[i] && BB[i]) || ((Y[i] ^ AA[i] ^ BB[i]) && (AA[i] || BB[i])); +end endgenerate + +assign X = AA ^ BB; + +endmodule +`endif + diff --git a/yosys/techlibs/fabulous/cells_map.v b/yosys/techlibs/fabulous/cells_map.v index eadd18b6f08..e33e641a8ac 100644 --- a/yosys/techlibs/fabulous/cells_map.v +++ b/yosys/techlibs/fabulous/cells_map.v @@ -16,10 +16,15 @@ module \$lut (A, Y); end else if (WIDTH == 3) begin LUT3 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y), .I0(A[0]), .I1(A[1]), .I2(A[2])); - end else if (WIDTH == 4) begin LUT4 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y), .I0(A[0]), .I1(A[1]), .I2(A[2]), .I3(A[3])); + end else + if (WIDTH == 5) begin + LUT5 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y), .I0(A[0]), .I1(A[1]), .I2(A[2]), .I3(A[3]), .I4(A[4])); + end else + if (WIDTH == 6) begin + LUT6 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y), .I0(A[0]), .I1(A[1]), .I2(A[2]), .I3(A[3]), .I4(A[4]), .I5(A[5])); end else begin wire _TECHMAP_FAIL_ = 1; end diff --git a/yosys/techlibs/fabulous/prims.v b/yosys/techlibs/fabulous/prims.v index 8ddae5beb72..21dc5223d23 100644 --- a/yosys/techlibs/fabulous/prims.v +++ b/yosys/techlibs/fabulous/prims.v @@ -24,6 +24,52 @@ module LUT4(output O, input I0, I1, I2, I3); assign O = I0 ? s1[1] : s1[0]; endmodule +module LUT4_HA(output O, Co, input I0, I1, I2, I3, Ci); + parameter [15:0] INIT = 0; + parameter I0MUX = 1'b1; + + wire [ 7: 0] s3 = I3 ? INIT[15: 8] : INIT[ 7: 0]; + wire [ 3: 0] s2 = I2 ? s3[ 7: 4] : s3[ 3: 0]; + wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0]; + + wire I0_sel = I0MUX ? Ci : I0; + assign O = I0_sel ? s1[1] : s1[0]; + + assign Co = (Ci & I1) | (Ci & I2) | (I1 & I2); +endmodule + +module LUT5(output O, input I0, I1, I2, I3, I4); + parameter [31:0] INIT = 0; + wire [15: 0] s4 = I4 ? INIT[31:16] : INIT[15: 0]; + wire [ 7: 0] s3 = I3 ? s4[15: 8] : s4[ 7: 0]; + wire [ 3: 0] s2 = I2 ? s3[ 7: 4] : s3[ 3: 0]; + wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0]; + assign O = I0 ? s1[1] : s1[0]; +endmodule + +module LUT6(output O, input I0, I1, I2, I3, I4, I5); + parameter [63:0] INIT = 0; + wire [31: 0] s5 = I5 ? INIT[63:32] : INIT[31: 0]; + wire [15: 0] s4 = I4 ? s5[31:16] : s5[15: 0]; + wire [ 7: 0] s3 = I3 ? s4[15: 8] : s4[ 7: 0]; + wire [ 3: 0] s2 = I2 ? s3[ 7: 4] : s3[ 3: 0]; + wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0]; + assign O = I0 ? s1[1] : s1[0]; +endmodule + +module LUT55_FCY (output O, Co, input I0, I1, I2, I3, I4, Ci); + parameter [63:0] INIT = 0; + + wire comb1, comb2; + + LUT5 #(.INIT(INIT[31: 0])) l5_1 (.I0(I0), .I1(I1), .I2(I2), .I3(I3), .I4(I4), .O(comb1)); + LUT5 #(.INIT(INIT[63:32])) l5_2 (.I0(I0), .I1(I1), .I2(I2), .I3(I3), .I4(I4), .O(comb2)); + + assign O = comb1 ^ Ci; + assign Co = comb1 ? Ci : comb2; +endmodule + + module LUTFF(input CLK, D, output reg O); initial O = 1'b0; always @ (posedge CLK) begin @@ -93,13 +139,13 @@ module Global_Clock (output CLK); endmodule (* blackbox, keep *) -module InPass4_frame_config (output O0, O1, O2, O3); +module InPass4_frame_config (input CLK, output O0, O1, O2, O3); endmodule (* blackbox, keep *) -module OutPass4_frame_config (input I0, I1, I2, I3); +module OutPass4_frame_config (input CLK, I0, I1, I2, I3); endmodule @@ -414,4 +460,4 @@ module LUTFF_ESS ( O <= D; end endmodule -`endif // COMPLEX_DFF \ No newline at end of file +`endif // COMPLEX_DFF diff --git a/yosys/techlibs/fabulous/synth_fabulous.cc b/yosys/techlibs/fabulous/synth_fabulous.cc index d7c45e094c6..b4a7ab2dc6f 100644 --- a/yosys/techlibs/fabulous/synth_fabulous.cc +++ b/yosys/techlibs/fabulous/synth_fabulous.cc @@ -83,6 +83,9 @@ struct SynthPass : public ScriptPass log(" do not run 'alumacc' pass. i.e. keep arithmetic operators in\n"); log(" their direct form ($add, $sub, etc.).\n"); log("\n"); + log(" -carry \n"); + log(" carry mapping style (none, half-adders, ...) default=none\n"); + log("\n"); log(" -noregfile\n"); log(" do not map register files\n"); log("\n"); @@ -119,7 +122,7 @@ struct SynthPass : public ScriptPass log("\n"); } - string top_module, json_file, blif_file, plib, fsm_opts, memory_opts; + string top_module, json_file, blif_file, plib, fsm_opts, memory_opts, carry_mode; std::vector extra_plib, extra_map; bool autotop, forvpr, noalumacc, nofsm, noshare, noregfile, iopad, complexdff, flatten; @@ -137,6 +140,7 @@ struct SynthPass : public ScriptPass noshare = false; iopad = false; complexdff = false; + carry_mode = "none"; flatten = true; json_file = ""; blif_file = ""; @@ -229,6 +233,12 @@ struct SynthPass : public ScriptPass complexdff = true; continue; } + if (args[argidx] == "-carry") { + carry_mode = args[++argidx]; + if (carry_mode != "none" && carry_mode != "ha") + log_cmd_error("Unsupported carry style: %s\n", carry_mode.c_str()); + continue; + } if (args[argidx] == "-noflatten") { flatten = false; continue; @@ -326,7 +336,8 @@ struct SynthPass : public ScriptPass if (check_label("map_gates")) { run("opt -full"); - run("techmap -map +/techmap.v"); + run(stringf("techmap -map +/techmap.v -map +/fabulous/arith_map.v -D ARITH_%s", + help_mode ? "" : carry_mode.c_str())); run("opt -fast"); } diff --git a/yosys/techlibs/gatemate/cells_bb.v b/yosys/techlibs/gatemate/cells_bb.v index 2bb8154ef5e..8df74e2a0d7 100644 --- a/yosys/techlibs/gatemate/cells_bb.v +++ b/yosys/techlibs/gatemate/cells_bb.v @@ -22,6 +22,9 @@ module CC_PLL #( parameter REF_CLK = "", // e.g. "10.0" parameter OUT_CLK = "", // e.g. "50.0" parameter PERF_MD = "", // LOWPOWER, ECONOMY, SPEED + parameter LOCK_REQ = 1, + parameter CLK270_DOUB = 0, + parameter CLK180_DOUB = 0, parameter LOW_JITTER = 1, parameter CI_FILTER_CONST = 2, parameter CP_FILTER_CONST = 4 @@ -123,69 +126,8 @@ module CC_CFG_CTRL( ); endmodule -(* blackbox *) -module CC_FIFO_40K ( - output A_ECC_1B_ERR, - output B_ECC_1B_ERR, - output A_ECC_2B_ERR, - output B_ECC_2B_ERR, - // FIFO pop port - output [39:0] A_DO, - output [39:0] B_DO, - (* clkbuf_sink *) - input A_CLK, - input A_EN, - // FIFO push port - input [39:0] A_DI, - input [39:0] B_DI, - input [39:0] A_BM, - input [39:0] B_BM, - (* clkbuf_sink *) - input B_CLK, - input B_EN, - input B_WE, - // FIFO control - input F_RST_N, - input [12:0] F_ALMOST_FULL_OFFSET, - input [12:0] F_ALMOST_EMPTY_OFFSET, - // FIFO status signals - output F_FULL, - output F_EMPTY, - output F_ALMOST_FULL, - output F_ALMOST_EMPTY, - output F_RD_ERROR, - output F_WR_ERROR, - output [15:0] F_RD_PTR, - output [15:0] F_WR_PTR +(* blackbox *) (* keep *) +module CC_USR_RSTN ( + output USR_RSTN ); - // Location format: D(0..N-1)X(0..3)Y(0..7) or UNPLACED - parameter LOC = "UNPLACED"; - - // Offset configuration - parameter [12:0] ALMOST_FULL_OFFSET = 12'b0; - parameter [12:0] ALMOST_EMPTY_OFFSET = 12'b0; - - // Port Widths - parameter A_WIDTH = 0; - parameter B_WIDTH = 0; - - // RAM and Write Modes - parameter RAM_MODE = "SDP"; // "TPD" or "SDP" - parameter FIFO_MODE = "SYNC"; // "ASYNC" or "SYNC" - - // Inverting Control Pins - parameter A_CLK_INV = 1'b0; - parameter B_CLK_INV = 1'b0; - parameter A_EN_INV = 1'b0; - parameter B_EN_INV = 1'b0; - parameter A_WE_INV = 1'b0; - parameter B_WE_INV = 1'b0; - - // Output Register - parameter A_DO_REG = 1'b0; - parameter B_DO_REG = 1'b0; - - // Error Checking and Correction - parameter A_ECC_EN = 1'b0; - parameter B_ECC_EN = 1'b0; endmodule diff --git a/yosys/techlibs/gatemate/cells_sim.v b/yosys/techlibs/gatemate/cells_sim.v index 3f009890023..cb680d32bde 100644 --- a/yosys/techlibs/gatemate/cells_sim.v +++ b/yosys/techlibs/gatemate/cells_sim.v @@ -114,10 +114,10 @@ module CC_LVDS_IBUF #( parameter [0:0] FF_IBF = 1'bx )( (* iopad_external_pin *) - input IP, IN, + input I_P, I_N, output Y ); - assign Y = IP; + assign Y = I_P; endmodule @@ -133,10 +133,10 @@ module CC_LVDS_OBUF #( )( input A, (* iopad_external_pin *) - output OP, ON + output O_P, O_N ); - assign OP = A; - assign ON = ~A; + assign O_P = A; + assign O_N = ~A; endmodule @@ -152,10 +152,10 @@ module CC_LVDS_TOBUF #( )( input A, T, (* iopad_external_pin *) - output OP, ON + output O_P, O_N ); - assign OP = T ? 1'bz : A; - assign ON = T ? 1'bz : ~A; + assign O_P = T ? 1'bz : A; + assign O_N = T ? 1'bz : ~A; endmodule @@ -174,12 +174,12 @@ module CC_LVDS_IOBUF #( )( input A, T, (* iopad_external_pin *) - inout IOP, ION, + inout IO_P, IO_N, output Y ); - assign IOP = T ? 1'bz : A; - assign ION = T ? 1'bz : ~A; - assign Y = IOP; + assign IO_P = T ? 1'bz : A; + assign IO_N = T ? 1'bz : ~A; + assign Y = IO_P; endmodule @@ -242,7 +242,8 @@ module CC_DFF #( parameter [0:0] CLK_INV = 1'b0, parameter [0:0] EN_INV = 1'b0, parameter [0:0] SR_INV = 1'b0, - parameter [0:0] SR_VAL = 1'b0 + parameter [0:0] SR_VAL = 1'b0, + parameter [0:0] INIT = 1'bx )( input D, (* clkbuf_sink *) @@ -256,7 +257,7 @@ module CC_DFF #( assign en = (EN_INV) ? ~EN : EN; assign sr = (SR_INV) ? ~SR : SR; - initial Q = 1'bX; + initial Q = INIT; always @(posedge clk or posedge sr) begin @@ -272,9 +273,10 @@ endmodule module CC_DLT #( - parameter [0:0] G_INV = 1'b0, + parameter [0:0] G_INV = 1'b0, parameter [0:0] SR_INV = 1'b0, - parameter [0:0] SR_VAL = 1'b0 + parameter [0:0] SR_VAL = 1'b0, + parameter [0:0] INIT = 1'bx )( input D, input G, @@ -285,7 +287,7 @@ module CC_DLT #( assign en = (G_INV) ? ~G : G; assign sr = (SR_INV) ? ~SR : SR; - initial Q = 1'bX; + initial Q = INIT; always @(*) begin @@ -731,13 +733,12 @@ module CC_BRAM_20K ( // SDP read port always @(posedge clkb) begin - // "NO_CHANGE" only for (k=0; k < B_RD_WIDTH; k=k+1) begin if (k < 20) begin - if (enb && !wea) A_DO_out[k] <= memory[addrb+k]; + if (enb) A_DO_out[k] <= memory[addrb+k]; end else begin // use both ports - if (enb && !wea) B_DO_out[k-20] <= memory[addrb+k]; + if (enb) B_DO_out[k-20] <= memory[addrb+k]; end end end @@ -1272,13 +1273,12 @@ module CC_BRAM_40K ( // SDP read port always @(posedge clkb) begin - // "NO_CHANGE" only for (k=0; k < B_RD_WIDTH; k=k+1) begin if (k < 40) begin - if (enb && !wea) A_DO_out[k] <= memory[addrb+k]; + if (enb) A_DO_out[k] <= memory[addrb+k]; end else begin // use both ports - if (enb && !wea) B_DO_out[k-40] <= memory[addrb+k]; + if (enb) B_DO_out[k-40] <= memory[addrb+k]; end end end @@ -1410,6 +1410,393 @@ module CC_BRAM_40K ( endgenerate endmodule +module CC_FIFO_40K ( + output A_ECC_1B_ERR, + output B_ECC_1B_ERR, + output A_ECC_2B_ERR, + output B_ECC_2B_ERR, + // FIFO pop port + output [39:0] A_DO, + output [39:0] B_DO, + (* clkbuf_sink *) + input A_CLK, + input A_EN, + // FIFO push port + input [39:0] A_DI, + input [39:0] B_DI, + input [39:0] A_BM, + input [39:0] B_BM, + (* clkbuf_sink *) + input B_CLK, + input B_EN, + input B_WE, + // FIFO control + input F_RST_N, + input [14:0] F_ALMOST_FULL_OFFSET, + input [14:0] F_ALMOST_EMPTY_OFFSET, + // FIFO status signals + output F_FULL, + output F_EMPTY, + output F_ALMOST_FULL, + output F_ALMOST_EMPTY, + output F_RD_ERROR, + output F_WR_ERROR, + output [15:0] F_RD_PTR, + output [15:0] F_WR_PTR +); + // Location format: D(0..N-1)X(0..3)Y(0..7) or UNPLACED + parameter LOC = "UNPLACED"; + + // Offset configuration + parameter DYN_STAT_SELECT = 1'b0; + parameter [14:0] ALMOST_FULL_OFFSET = 15'b0; + parameter [14:0] ALMOST_EMPTY_OFFSET = 15'b0; + + // Port Widths + parameter A_WIDTH = 0; + parameter B_WIDTH = 0; + + // RAM and Write Modes + parameter RAM_MODE = "TDP"; // "TDP" or "SDP" + parameter FIFO_MODE = "SYNC"; // "ASYNC" or "SYNC" + + // Inverting Control Pins + parameter A_CLK_INV = 1'b0; + parameter B_CLK_INV = 1'b0; + parameter A_EN_INV = 1'b0; + parameter B_EN_INV = 1'b0; + parameter A_WE_INV = 1'b0; + parameter B_WE_INV = 1'b0; + + // Output Register + parameter A_DO_REG = 1'b0; + parameter B_DO_REG = 1'b0; + + // Error Checking and Correction + parameter A_ECC_EN = 1'b0; + parameter B_ECC_EN = 1'b0; + + integer i, k; + + // 512 x 80 bit + reg [40959:0] memory = 40960'b0; + + reg [15:0] counter_max; + reg [15:0] sram_depth; + localparam tp = (A_WIDTH == 1) ? 15 : + (A_WIDTH == 2) ? 14 : + (A_WIDTH == 5) ? 13 : + (A_WIDTH == 10) ? 12 : + (A_WIDTH == 20) ? 11 : + (A_WIDTH == 40) ? 10 : 9; + + initial begin + // Check parameters + if ((RAM_MODE != "SDP") && (RAM_MODE != "TDP")) begin + $display("ERROR: Illegal RAM MODE %d.", RAM_MODE); + $finish(); + end + if ((FIFO_MODE != "ASYNC") && (FIFO_MODE != "SYNC")) begin + $display("ERROR: Illegal FIFO MODE %d.", FIFO_MODE); + $finish(); + end + if ((RAM_MODE == "SDP") && (DYN_STAT_SELECT == 1)) begin + $display("ERROR: Dynamic offset configuration is not supported in %s mode.", RAM_MODE); + $finish(); + end + if ((RAM_MODE == "SDP") && ((A_WIDTH != 80) || (B_WIDTH != 80))) begin + $display("ERROR: SDP is ony supported in 80 bit mode."); + $finish(); + end + if ((A_WIDTH == 80) && (RAM_MODE == "TDP")) begin + $display("ERROR: Port A width of 80 bits is only supported in SDP mode."); + $finish(); + end + if ((B_WIDTH == 80) && (RAM_MODE == "TDP")) begin + $display("ERROR: Port B width of 80 bits is only supported in SDP mode."); + $finish(); + end + if ((A_WIDTH != 80) && (A_WIDTH != 40) && (A_WIDTH != 20) && (A_WIDTH != 10) && + (A_WIDTH != 5) && (A_WIDTH != 2) && (A_WIDTH != 1) && (A_WIDTH != 0)) begin + $display("ERROR: Illegal %s Port A width configuration %d.", RAM_MODE, A_WIDTH); + $finish(); + end + if ((B_WIDTH != 80) && (B_WIDTH != 40) && (B_WIDTH != 20) && (B_WIDTH != 10) && + (B_WIDTH != 5) && (B_WIDTH != 2) && (B_WIDTH != 1) && (B_WIDTH != 0)) begin + $display("ERROR: Illegal %s Port B width configuration %d.", RAM_MODE, B_WIDTH); + $finish(); + end + if (A_WIDTH != B_WIDTH) begin + $display("ERROR: The values of A_WIDTH and B_WIDTH must be equal."); + end + if ((A_ECC_EN == 1'b1) && (RAM_MODE != "SDP") && (A_WIDTH != 40)) begin + $display("ERROR: Illegal ECC Port A configuration. ECC mode requires TDP >=40 bit or SDP 80 bit, but is %s %d.", RAM_MODE, A_WIDTH); + $finish(); + end + // Set local parameters + if (A_WIDTH == 1) begin // A_WIDTH=B_WIDTH + counter_max = 2 * 32*1024 - 1; + sram_depth = 32*1024; + end + else if (A_WIDTH == 2) begin + counter_max = 2 * 16*1024 - 1; + sram_depth = 16*1024; + end + else if (A_WIDTH == 5) begin + counter_max = 2 * 8*1024 - 1; + sram_depth = 8*1024; + end + else if (A_WIDTH == 10) begin + counter_max = 2 * 4*1024 - 1; + sram_depth = 4*1024; + end + else if (A_WIDTH == 20) begin + counter_max = 2 * 2*1024 - 1; + sram_depth = 2*1024; + end + else if (A_WIDTH == 40) begin + counter_max = 2 * 1*1024 - 1; + sram_depth = 1*1024; + end + else begin // 80 bit SDP + counter_max = 2 * 512 - 1; + sram_depth = 512; + end + end + + // Internal signals + wire fifo_rdclk = A_CLK ^ A_CLK_INV; + wire fifo_wrclk = (FIFO_MODE == "ASYNC") ? (B_CLK ^ B_CLK_INV) : (A_CLK ^ A_CLK_INV); + wire [15:0] almost_full_offset = DYN_STAT_SELECT ? F_ALMOST_FULL_OFFSET : ALMOST_FULL_OFFSET; + wire [15:0] almost_empty_offset = DYN_STAT_SELECT ? F_ALMOST_EMPTY_OFFSET : ALMOST_EMPTY_OFFSET; + reg [39:0] A_DO_out = 0, A_DO_reg = 0; + reg [39:0] B_DO_out = 0, B_DO_reg = 0; + + // Status signals + reg fifo_full; + reg fifo_empty; + reg fifo_almost_full; + reg fifo_almost_empty; + assign F_FULL = fifo_full; + assign F_EMPTY = fifo_empty; + assign F_ALMOST_FULL = fifo_almost_full; + assign F_ALMOST_EMPTY = fifo_almost_empty; + assign F_WR_ERROR = (F_FULL && (B_EN ^ B_EN_INV) && (B_WE ^ B_WE_INV)); + assign F_RD_ERROR = (F_EMPTY && (A_EN ^ A_EN_INV)); + wire ram_we = (~F_FULL && (B_EN ^ B_EN_INV) && (B_WE ^ B_WE_INV)); + wire ram_en = (~F_EMPTY && (A_EN ^ A_EN_INV)); + + // Reset synchronizers + reg [1:0] aclk_reset_q, bclk_reset_q; + wire fifo_sync_rstn = aclk_reset_q; + wire fifo_async_wrrstn = bclk_reset_q; + wire fifo_async_rdrstn = aclk_reset_q; + + always @(posedge fifo_rdclk or negedge F_RST_N) + begin + if (F_RST_N == 1'b0) begin + aclk_reset_q <= 2'b0; + end + else begin + aclk_reset_q[1] <= aclk_reset_q[0]; + aclk_reset_q[0] <= 1'b1; + end + end + + always @(posedge fifo_wrclk or negedge F_RST_N) + begin + if (F_RST_N == 1'b0) begin + bclk_reset_q <= 2'b0; + end + else begin + bclk_reset_q[1] <= bclk_reset_q[0]; + bclk_reset_q[0] <= 1'b1; + end + end + + // Push/pop pointers + reg [15:0] rd_pointer, rd_pointer_int; + reg [15:0] wr_pointer, wr_pointer_int; + reg [15:0] rd_pointer_cmp, wr_pointer_cmp; + wire [15:0] rd_pointer_nxt; + wire [15:0] wr_pointer_nxt; + reg [15:0] fifo_rdaddr, rdaddr; + reg [15:0] fifo_wraddr, wraddr; + assign F_RD_PTR = fifo_rdaddr; + assign F_WR_PTR = fifo_wraddr; + + always @(posedge fifo_rdclk or negedge F_RST_N) + begin + if (F_RST_N == 1'b0) begin + rd_pointer <= 0; + rd_pointer_int <= 0; + end + else if (ram_en) begin + rd_pointer <= rd_pointer_nxt; + rd_pointer_int <= rd_pointer_nxt[15:1] ^ rd_pointer_nxt[14:0]; + end + end + + assign rd_pointer_nxt = (rd_pointer == counter_max) ? (0) : (rd_pointer + 1'b1); + + always @(posedge fifo_wrclk or negedge F_RST_N) + begin + if (F_RST_N == 1'b0) begin + wr_pointer <= 0; + wr_pointer_int <= 0; + end + else if (ram_we) begin + wr_pointer <= wr_pointer_nxt; + wr_pointer_int <= wr_pointer_nxt[15:1] ^ wr_pointer_nxt[14:0]; + end + end + + assign wr_pointer_nxt = (wr_pointer == counter_max) ? (0) : (wr_pointer + 1'b1); + + // Address synchronizers + reg [15:0] rd_pointer_sync, wr_pointer_sync; + reg [15:0] rd_pointer_sync_0, rd_pointer_sync_1; + reg [15:0] wr_pointer_sync_0, wr_pointer_sync_1; + + always @(posedge fifo_rdclk or negedge F_RST_N) + begin + if (F_RST_N == 1'b0) begin + wr_pointer_sync_0 <= 0; + wr_pointer_sync_1 <= 0; + end + else begin + wr_pointer_sync_0 <= wraddr; + wr_pointer_sync_1 <= wr_pointer_sync_0; + end + end + + always @(posedge fifo_wrclk or negedge F_RST_N) + begin + if (F_RST_N == 1'b0) begin + rd_pointer_sync_0 <= 0; + rd_pointer_sync_1 <= 0; + end + else begin + rd_pointer_sync_0 <= rdaddr; + rd_pointer_sync_1 <= rd_pointer_sync_0; + end + end + + always @(*) begin + fifo_wraddr = {wr_pointer[tp-1:0], {(15-tp){1'b0}}}; + fifo_rdaddr = {rd_pointer[tp-1:0], {(15-tp){1'b0}}}; + + rdaddr = {rd_pointer[tp], rd_pointer_int[tp-1:0]}; + wraddr = {{(15-tp){1'b0}}, wr_pointer[tp], wr_pointer_int[tp:0]}; + + if (FIFO_MODE == "ASYNC") + fifo_full = (wraddr[tp-2:0] == rd_pointer_sync_1[tp-2:0] ) && (wraddr[tp] != rd_pointer_sync_1[tp] ) && ( wraddr[tp-1] != rd_pointer_sync_1[tp-1] ); + else + fifo_full = (wr_pointer[tp-1:0] == rd_pointer[tp-1:0]) && (wr_pointer[tp] ^ rd_pointer[tp]); + + if (FIFO_MODE == "ASYNC") + fifo_empty = (wr_pointer_sync_1[tp:0] == rdaddr[tp:0]); + else + fifo_empty = (wr_pointer[tp:0] == rd_pointer[tp:0]); + + rd_pointer_cmp = (FIFO_MODE == "ASYNC") ? rd_pointer_sync : rd_pointer; + if (wr_pointer[tp] == rd_pointer_cmp[tp]) + fifo_almost_full = ((wr_pointer[tp-1:0] - rd_pointer_cmp[tp-1:0]) >= (sram_depth - almost_full_offset)); + else + fifo_almost_full = ((rd_pointer_cmp[tp-1:0] - wr_pointer[tp-1:0]) <= almost_full_offset); + + wr_pointer_cmp = (FIFO_MODE == "ASYNC") ? wr_pointer_sync : wr_pointer; + if (wr_pointer_cmp[tp] == rd_pointer[tp]) + fifo_almost_empty = ((wr_pointer_cmp[tp-1:0] - rd_pointer[tp-1:0]) <= almost_empty_offset); + else + fifo_almost_empty = ((rd_pointer[tp-1:0] - wr_pointer_cmp[tp-1:0]) >= (sram_depth - almost_empty_offset)); + end + + generate + always @(*) begin + wr_pointer_sync = 0; + rd_pointer_sync = 0; + for (i=tp; i >= 0; i=i-1) begin + if (i == tp) begin + wr_pointer_sync[i] = wr_pointer_sync_1[i]; + rd_pointer_sync[i] = rd_pointer_sync_1[i]; + end + else begin + wr_pointer_sync[i] = wr_pointer_sync_1[i] ^ wr_pointer_sync[i+1]; + rd_pointer_sync[i] = rd_pointer_sync_1[i] ^ rd_pointer_sync[i+1]; + end + end + end + if (RAM_MODE == "SDP") begin + // SDP push ports A+B + always @(posedge fifo_wrclk) + begin + for (k=0; k < A_WIDTH; k=k+1) begin + if (k < 40) begin + if (ram_we && A_BM[k]) memory[fifo_wraddr+k] <= A_DI[k]; + end + else begin // use both ports + if (ram_we && B_BM[k-40]) memory[fifo_wraddr+k] <= B_DI[k-40]; + end + end + end + // SDP pop ports A+B + always @(posedge fifo_rdclk) + begin + for (k=0; k < B_WIDTH; k=k+1) begin + if (k < 40) begin + if (ram_en) A_DO_out[k] <= memory[fifo_rdaddr+k]; + end + else begin // use both ports + if (ram_en) B_DO_out[k-40] <= memory[fifo_rdaddr+k]; + end + end + end + end + else if (RAM_MODE == "TDP") begin + // TDP pop port A + always @(posedge fifo_rdclk) + begin + for (i=0; i < A_WIDTH; i=i+1) begin + if (ram_en) begin + A_DO_out[i] <= memory[fifo_rdaddr+i]; + end + end + end + // TDP push port B + always @(posedge fifo_wrclk) + begin + for (i=0; i < B_WIDTH; i=i+1) begin + if (ram_we && B_BM[i]) + memory[fifo_wraddr+i] <= B_DI[i]; + end + end + end + endgenerate + + // Optional output register + generate + if (A_DO_REG) begin + always @(posedge fifo_rdclk) begin + A_DO_reg <= A_DO_out; + end + assign A_DO = A_DO_reg; + end + else begin + assign A_DO = A_DO_out; + end + if (B_DO_REG) begin + always @(posedge fifo_rdclk) begin + B_DO_reg <= B_DO_out; + end + assign B_DO = B_DO_reg; + end + else begin + assign B_DO = B_DO_out; + end + endgenerate +endmodule + // Models of the LUT2 tree primitives module CC_L2T4( output O, diff --git a/yosys/techlibs/gatemate/reg_map.v b/yosys/techlibs/gatemate/reg_map.v index 26cfb71d858..8debc64c34e 100644 --- a/yosys/techlibs/gatemate/reg_map.v +++ b/yosys/techlibs/gatemate/reg_map.v @@ -21,25 +21,31 @@ module \$_DFFE_xxxx_ (input D, C, R, E, output Q); parameter _TECHMAP_CELLTYPE_ = ""; + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; CC_DFF #( .CLK_INV(_TECHMAP_CELLTYPE_[39:32] == "N"), .EN_INV(_TECHMAP_CELLTYPE_[15:8] == "N"), .SR_INV(_TECHMAP_CELLTYPE_[31:24] == "N"), - .SR_VAL(_TECHMAP_CELLTYPE_[23:16] == "1") + .SR_VAL(_TECHMAP_CELLTYPE_[23:16] == "1"), + .INIT(_TECHMAP_WIREINIT_Q_) ) _TECHMAP_REPLACE_ (.D(D), .EN(E), .CLK(C), .SR(R), .Q(Q)); + wire _TECHMAP_REMOVEINIT_Q_ = 1; endmodule (* techmap_celltype = "$_DLATCH_[NP][NP][01]_" *) module \$_DLATCH_xxx_ (input E, R, D, output Q); parameter _TECHMAP_CELLTYPE_ = ""; + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; CC_DLT #( .G_INV(_TECHMAP_CELLTYPE_[31:24] == "N"), .SR_INV(_TECHMAP_CELLTYPE_[23:16] == "N"), - .SR_VAL(_TECHMAP_CELLTYPE_[15:8] == "1") + .SR_VAL(_TECHMAP_CELLTYPE_[15:8] == "1"), + .INIT(_TECHMAP_WIREINIT_Q_) ) _TECHMAP_REPLACE_ (.D(D), .G(E), .SR(R), .Q(Q)); + wire _TECHMAP_REMOVEINIT_Q_ = 1; endmodule diff --git a/yosys/techlibs/gatemate/synth_gatemate.cc b/yosys/techlibs/gatemate/synth_gatemate.cc index dd4fde64368..1d46d79295c 100644 --- a/yosys/techlibs/gatemate/synth_gatemate.cc +++ b/yosys/techlibs/gatemate/synth_gatemate.cc @@ -283,7 +283,7 @@ struct SynthGateMatePass : public ScriptPass if (check_label("map_regs")) { run("opt_clean"); - run("dfflegalize -cell $_DFFE_????_ x -cell $_DLATCH_???_ x"); + run("dfflegalize -cell $_DFFE_????_ 01 -cell $_DLATCH_???_ 01"); run("techmap -map +/gatemate/reg_map.v"); run("opt_expr -mux_undef"); run("simplemap"); diff --git a/yosys/techlibs/gowin/Makefile.inc b/yosys/techlibs/gowin/Makefile.inc index 4f3a33f369e..0e24b91e5ff 100644 --- a/yosys/techlibs/gowin/Makefile.inc +++ b/yosys/techlibs/gowin/Makefile.inc @@ -3,6 +3,7 @@ OBJS += techlibs/gowin/synth_gowin.o $(eval $(call add_share_file,share/gowin,techlibs/gowin/cells_map.v)) $(eval $(call add_share_file,share/gowin,techlibs/gowin/cells_sim.v)) +$(eval $(call add_share_file,share/gowin,techlibs/gowin/cells_xtra.v)) $(eval $(call add_share_file,share/gowin,techlibs/gowin/arith_map.v)) $(eval $(call add_share_file,share/gowin,techlibs/gowin/brams_map.v)) $(eval $(call add_share_file,share/gowin,techlibs/gowin/brams.txt)) diff --git a/yosys/techlibs/gowin/arith_map.v b/yosys/techlibs/gowin/arith_map.v index 2d48fa752a2..828bb35b8d3 100644 --- a/yosys/techlibs/gowin/arith_map.v +++ b/yosys/techlibs/gowin/arith_map.v @@ -62,6 +62,6 @@ module _80_gw1n_alu(A, B, CI, BI, X, Y, CO); .SUM(Y[i]) ); end endgenerate - assign X = AA ^ BB; + assign X = AA ^ BB ^ {Y_WIDTH{BI}}; endmodule diff --git a/yosys/techlibs/gowin/cells_sim.v b/yosys/techlibs/gowin/cells_sim.v index ab8207ef107..86bd677e229 100644 --- a/yosys/techlibs/gowin/cells_sim.v +++ b/yosys/techlibs/gowin/cells_sim.v @@ -582,6 +582,14 @@ module IOBUF (O, IO, I, OEN); assign I = IO; endmodule +module ELVDS_OBUF (I, O, OB); + input I; + output O; + output OB; + assign O = I; + assign OB = ~I; +endmodule + module TLVDS_OBUF (I, O, OB); input I; output O; @@ -590,6 +598,250 @@ module TLVDS_OBUF (I, O, OB); assign OB = ~I; endmodule +module OSER4(D3, D2, D1, D0, TX1, TX0, FCLK, PCLK, RESET, Q1, Q0); + output Q1; + output Q0; + + input D3; + input D2; + input D1; + input D0; + input TX1; + input TX0; + input FCLK; + input PCLK; + input RESET; + + parameter GSREN = "false"; + parameter LSREN = "true"; + parameter TXCLK_POL = 0; + parameter HWL = "false"; +endmodule + +module OSER8(D7, D6, D5, D4, D3, D2, D1, D0, TX3, TX2, TX1, TX0, FCLK, PCLK, RESET, Q1, Q0); + output Q1; + output Q0; + + input D7; + input D6; + input D5; + input D4; + input D3; + input D2; + input D1; + input D0; + input TX3; + input TX2; + input TX1; + input TX0; + input FCLK; + input PCLK; + input RESET; + + parameter GSREN = "false"; + parameter LSREN = "true"; + parameter TXCLK_POL = 0; + parameter HWL = "false"; +endmodule + +module OSER10(D9, D8, D7, D6, D5, D4, D3, D2, D1, D0, FCLK, PCLK, RESET, Q); + output Q; + + input D9; + input D8; + input D7; + input D6; + input D5; + input D4; + input D3; + input D2; + input D1; + input D0; + input FCLK; + input PCLK; + input RESET; + + parameter GSREN = "false"; + parameter LSREN = "true"; +endmodule + +module OVIDEO(D6, D5, D4, D3, D2, D1, D0, FCLK, PCLK, RESET, Q); + output Q; + + input D6; + input D5; + input D4; + input D3; + input D2; + input D1; + input D0; + input FCLK; + input PCLK; + input RESET; + + parameter GSREN = "false"; + parameter LSREN = "true"; +endmodule + +module OSER16(D15, D14, D13, D12, D11, D10, +D9, D8, D7, D6, D5, D4, D3, D2, D1, D0, FCLK, PCLK, +RESET, Q); + output Q; + + input D15; + input D14; + input D13; + input D12; + input D11; + input D10; + input D9; + input D8; + input D7; + input D6; + input D5; + input D4; + input D3; + input D2; + input D1; + input D0; + input FCLK; + input PCLK; + input RESET; + + parameter GSREN = "false"; + parameter LSREN = "true"; +endmodule + +module IDES4(Q3, Q2, Q1, Q0, FCLK, PCLK, +RESET, CALIB, D); + input D; + input FCLK; + input PCLK; + input RESET; + input CALIB; + + output Q3; + output Q2; + output Q1; + output Q0; + + parameter GSREN = "false"; + parameter LSREN = "true"; +endmodule + +module IDES8(Q7, Q6, Q5, Q4, Q3, Q2, Q1, Q0, FCLK, PCLK, +RESET, CALIB, D); + input D; + input FCLK; + input PCLK; + input RESET; + input CALIB; + + output Q7; + output Q6; + output Q5; + output Q4; + output Q3; + output Q2; + output Q1; + output Q0; + + parameter GSREN = "false"; + parameter LSREN = "true"; +endmodule + +module IDES10(Q9, Q8, Q7, Q6, Q5, Q4, Q3, Q2, Q1, Q0, FCLK, PCLK, +RESET, CALIB, D); + input D; + input FCLK; + input PCLK; + input RESET; + input CALIB; + + output Q9; + output Q8; + output Q7; + output Q6; + output Q5; + output Q4; + output Q3; + output Q2; + output Q1; + output Q0; + + parameter GSREN = "false"; + parameter LSREN = "true"; +endmodule + +module IVIDEO(Q6, Q5, Q4, Q3, Q2, Q1, Q0, FCLK, PCLK, +RESET, CALIB, D); + input D; + input FCLK; + input PCLK; + input RESET; + input CALIB; + + output Q6; + output Q5; + output Q4; + output Q3; + output Q2; + output Q1; + output Q0; + + parameter GSREN = "false"; + parameter LSREN = "true"; +endmodule + +module IDES16(Q15, Q14, Q13, Q12, Q11, Q10, +Q9, Q8, Q7, Q6, Q5, Q4, Q3, Q2, Q1, Q0, FCLK, PCLK, +RESET, CALIB, D); + input D; + input FCLK; + input PCLK; + input RESET; + input CALIB; + + output Q15; + output Q14; + output Q13; + output Q12; + output Q11; + output Q10; + output Q9; + output Q8; + output Q7; + output Q6; + output Q5; + output Q4; + output Q3; + output Q2; + output Q1; + output Q0; + + parameter GSREN = "false"; + parameter LSREN = "true"; +endmodule + +module IDDR(D, CLK, Q0, Q1); + input D; + input CLK; + output Q0; + output Q1; + parameter Q0_INIT = 1'b0; + parameter Q1_INIT = 1'b0; +endmodule + +module IDDRC(D, CLK, CLEAR, Q0, Q1); + input D; + input CLK; + input CLEAR; + output Q0; + output Q1; + parameter Q0_INIT = 1'b0; + parameter Q1_INIT = 1'b0; +endmodule + (* blackbox *) module ODDR(D0, D1, TX, CLK, Q0, Q1); input D0; @@ -1632,3 +1884,20 @@ output OSCOUT; parameter FREQ_DIV = 96; endmodule + +(* blackbox *) +module OSCW(OSCOUT); +output OSCOUT; + +parameter FREQ_DIV = 80; +endmodule + +(* blackbox *) +module OSCO(OSCOUT, OSCEN); +input OSCEN; + +output OSCOUT; + +parameter FREQ_DIV = 100; +parameter REGULATOR_EN = 1'b0; +endmodule diff --git a/yosys/techlibs/gowin/cells_xtra.py b/yosys/techlibs/gowin/cells_xtra.py new file mode 100644 index 00000000000..4d117e428c3 --- /dev/null +++ b/yosys/techlibs/gowin/cells_xtra.py @@ -0,0 +1,76 @@ +#!/usr/bin/env python3 + +# Base on Nexus cells_xtra.py + +from argparse import ArgumentParser +import os.path +from enum import Enum, auto +import sys +import re + +class State(Enum): + OUTSIDE = auto() + IN_MODULE = auto() + IN_PARAMETER = auto() + +_skip = { 'ALU', 'DFF', 'DFFC', 'DFFCE', 'DFFE', 'DFFN', 'DFFNC', 'DFFNCE', + 'DFFNE', 'DFFNP', 'DFFNPE', 'DFFNR', 'DFFNRE', 'DFFNS', 'DFFNSE', + 'DFFP', 'DFFPE', 'DFFR', 'DFFRE', 'DFFS', 'DFFSE', 'DP', 'DPX9', + 'ELVDS_OBUF', 'GND', 'GSR', 'IBUF', 'IDDR', 'IDDRC', 'IDES10', + 'IDES16', 'IDES4', 'IDES8', 'IOBUF', 'IVIDEO', 'LUT1', 'LUT2', + 'LUT3', 'LUT4', 'MUX2', 'MUX2_LUT5', 'MUX2_LUT6', 'MUX2_LUT7', + 'MUX2_LUT8', 'OBUF', 'ODDR', 'ODDRC', 'OSC', 'OSCF', 'OSCH', + 'OSCO', 'OSCW', 'OSCZ', 'OSER10', 'OSER16', 'OSER10', 'OSER4', + 'OSER8', 'OVIDEO', 'PLLVR', 'RAM16S1', 'RAM16S2', 'RAM16S4', + 'RAM16SDP1', 'RAM16SDP2', 'RAM16SDP4', 'rPLL', 'SDP', + 'SDPX9', 'SP', 'SPX9', 'TBUF', 'TLVDS_OBUF', 'VCC' + } +def xtract_cells_decl(dir, fout): + fname = os.path.join(dir, 'prim_sim.v') + with open(fname) as f: + state = State.OUTSIDE + for l in f: + l, _, comment = l.partition('//') + if l.startswith("module "): + cell_name = l[7:l.find('(')].strip() + if cell_name not in _skip: + state = State.IN_MODULE + fout.write(f'\nmodule {cell_name} (...);\n') + elif l.startswith(('input', 'output', 'inout')) and state == State.IN_MODULE: + fout.write(l) + if l[-1] != '\n': + fout.write('\n') + elif l.startswith('parameter') and state == State.IN_MODULE: + fout.write(l) + if l.rstrip()[-1] == ',': + state = State.IN_PARAMETER + if l[-1] != '\n': + fout.write('\n') + elif state == State.IN_PARAMETER: + fout.write(l) + if l.rstrip()[-1] == ';': + state = State.IN_MODULE + if l[-1] != '\n': + fout.write('\n') + elif l.startswith('endmodule') and state == State.IN_MODULE: + state = State.OUTSIDE + fout.write('endmodule\n') + if l[-1] != '\n': + fout.write('\n') + +if __name__ == '__main__': + parser = ArgumentParser(description='Extract Gowin blackbox cell definitions.') + parser.add_argument('gowin_dir', nargs='?', default='/opt/gowin/') + args = parser.parse_args() + + dirs = [ + os.path.join(args.gowin_dir, 'IDE/simlib/gw1n/'), + ] + + with open('cells_xtra.v', 'w') as fout: + fout.write('// Created by cells_xtra.py\n') + fout.write('\n') + for dir in dirs: + if not os.path.isdir(dir): + print(f'{dir} is not a directory') + xtract_cells_decl(dir, fout) diff --git a/yosys/techlibs/gowin/cells_xtra.v b/yosys/techlibs/gowin/cells_xtra.v new file mode 100644 index 00000000000..4b89b8098aa --- /dev/null +++ b/yosys/techlibs/gowin/cells_xtra.v @@ -0,0 +1,2003 @@ +// Created by cells_xtra.py + + +module MUX2_MUX8 (...); +input I0,I1; +input S0; +output O; +endmodule + + +module MUX2_MUX16 (...); +input I0,I1; +input S0; +output O; +endmodule + + +module MUX2_MUX32 (...); +input I0,I1; +input S0; +output O; +endmodule + + +module MUX4 (...); +input I0, I1, I2, I3; +input S0, S1; +output O; +endmodule + + +module MUX8 (...); +input I0, I1, I2, I3, I4, I5, I6, I7; +input S0, S1, S2; +output O; +endmodule + + +module MUX16 (...); +input I0, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, I14, I15; +input S0, S1, S2, S3; +output O; +endmodule + +module MUX32 (...); +input I0, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, I14, I15, I16, I17, I18, I19, I20, I21, I22, I23, I24, I25, I26, I27, I28, I29, I30, I31; +input S0, S1, S2, S3, S4; +output O; +endmodule + +module LUT5 (...); +parameter INIT = 32'h00000000; +input I0, I1, I2, I3, I4; +output F; +endmodule + + +module LUT6 (...); +parameter INIT = 64'h0000_0000_0000_0000; +input I0, I1, I2, I3, I4, I5; +output F; +endmodule + + +module LUT7 (...); +parameter INIT = 128'h0000_0000_0000_0000_0000_0000_0000_0000; +input I0, I1, I2, I3, I4, I5, I6; +output F; +endmodule + + +module LUT8 (...); +parameter INIT = 256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000; +input I0, I1, I2, I3, I4, I5, I6, I7; +output F; +endmodule + + +module DL (...); +input D, G; +output Q; +parameter INIT = 1'b0; +endmodule + + +module DLE (...); +input D, G, CE; +output Q; +parameter INIT = 1'b0; +endmodule + + +module DLC (...); +input D, G, CLEAR; +output Q; +parameter INIT = 1'b0; +endmodule + + +module DLCE (...); +input D, G, CLEAR, CE; +output Q; +parameter INIT = 1'b0; +endmodule + + +module DLP (...); +input D, G, PRESET; +output Q; +parameter INIT = 1'b1; +endmodule + + +module DLPE (...); +input D, G, PRESET, CE; +output Q; +parameter INIT = 1'b1; +endmodule + + +module DLN (...); +input D, G; +output Q; +parameter INIT = 1'b0; +endmodule + + +module DLNE (...); +input D, G, CE; +output Q; +parameter INIT = 1'b0; +endmodule + + +module DLNC (...); +input D, G, CLEAR; +output Q; +parameter INIT = 1'b0; +endmodule + + +module DLNCE (...); +input D, G, CLEAR, CE; +output Q; +parameter INIT = 1'b0; +endmodule + + +module DLNP (...); +input D, G, PRESET; +output Q; +parameter INIT = 1'b1; +endmodule + + +module DLNPE (...); +input D, G, PRESET, CE; +output Q; +parameter INIT = 1'b1; +endmodule + + +module INV (...); +input I; +output O; +endmodule + + +module IODELAY (...); +parameter C_STATIC_DLY = 0; +input DI; +input SDTAP; +input SETN; +input VALUE; +output DF; +output DO; +endmodule + + +module IEM (...); +parameter WINSIZE = "SMALL"; +parameter GSREN = "false"; +parameter LSREN = "true"; +input D, CLK, RESET, MCLK; +output LAG, LEAD; +endmodule + + +module ROM16 (...); +parameter INIT_0 = 16'h0000; +input [3:0] AD; +output DO; +endmodule + + +module ROM (...); +parameter READ_MODE = 1'b0; +parameter BIT_WIDTH = 32; +parameter BLK_SEL = 3'b000; +parameter RESET_MODE = "SYNC"; +parameter INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; +input CLK, CE; +input OCE; +input RESET; +input WRE; +input [13:0] AD; +input [2:0] BLKSEL; +output [31:0] DO; +endmodule + + +module ROMX9 (...); +parameter READ_MODE = 1'b0; +parameter BIT_WIDTH = 36; +parameter BLK_SEL = 3'b000; +parameter RESET_MODE = "SYNC"; +parameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_01 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_02 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_03 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_04 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_05 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_06 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_07 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_08 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_09 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_0A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_0B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_0C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_0D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_0E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_0F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_10 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_11 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_12 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_13 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_14 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_15 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_16 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_17 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_18 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_19 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_1A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_1B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_1C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_1D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_1E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_1F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_20 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_21 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_22 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_23 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_24 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_25 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_26 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_27 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_28 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_29 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_2A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_2B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_2C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_2D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_2E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_2F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_30 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_31 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_32 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_33 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_34 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_35 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_36 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_37 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_38 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_39 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_3A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_3B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_3C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_3D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_3E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_3F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +input CLK, CE; +input OCE; +input RESET; +input WRE; +input [13:0] AD; +input [2:0] BLKSEL; +output [35:0] DO; +endmodule + + +module rSDP (...); +parameter READ_MODE = 1'b0; +parameter BIT_WIDTH_0 = 32; +parameter BIT_WIDTH_1 = 32; +parameter BLK_SEL = 3'b000; +parameter RESET_MODE = "SYNC"; +parameter INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; +input CLKA, CEA, CLKB, CEB; +input OCE; +input RESETA, RESETB; +input [13:0] ADA, ADB; +input [31:0] DI; +input [2:0] BLKSEL; +output [31:0] DO; +endmodule + + +module rSDPX9 (...); +parameter READ_MODE = 1'b0; +parameter BIT_WIDTH_0 = 36; +parameter BIT_WIDTH_1 = 36; +parameter BLK_SEL = 3'b000; +parameter RESET_MODE = "SYNC"; +parameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_01 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_02 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_03 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_04 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_05 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_06 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_07 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_08 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_09 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_0A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_0B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_0C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_0D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_0E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_0F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_10 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_11 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_12 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_13 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_14 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_15 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_16 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_17 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_18 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_19 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_1A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_1B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_1C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_1D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_1E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_1F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_20 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_21 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_22 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_23 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_24 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_25 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_26 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_27 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_28 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_29 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_2A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_2B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_2C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_2D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_2E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_2F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_30 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_31 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_32 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_33 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_34 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_35 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_36 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_37 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_38 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_39 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_3A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_3B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_3C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_3D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_3E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_3F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +input CLKA, CEA, CLKB, CEB; +input OCE; +input RESETA, RESETB; +input [13:0] ADA, ADB; +input [2:0] BLKSEL; +input [35:0] DI; +output [35:0] DO; +endmodule + + +module rROM (...); +parameter READ_MODE = 1'b0; +parameter BIT_WIDTH = 32; +parameter BLK_SEL = 3'b000; +parameter RESET_MODE = "SYNC"; +parameter INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; +input CLK, CE; +input OCE; +input RESET; +input [13:0] AD; +input [2:0] BLKSEL; +output [31:0] DO; +endmodule + + +module rROMX9 (...); +parameter READ_MODE = 1'b0; +parameter BIT_WIDTH = 36; +parameter BLK_SEL = 3'b000; +parameter RESET_MODE = "SYNC"; +parameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_01 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_02 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_03 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_04 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_05 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_06 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_07 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_08 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_09 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_0A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_0B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_0C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_0D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_0E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_0F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_10 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_11 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_12 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_13 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_14 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_15 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_16 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_17 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_18 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_19 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_1A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_1B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_1C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_1D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_1E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_1F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_20 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_21 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_22 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_23 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_24 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_25 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_26 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_27 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_28 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_29 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_2A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_2B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_2C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_2D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_2E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_2F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_30 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_31 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_32 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_33 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_34 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_35 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_36 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_37 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_38 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_39 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_3A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_3B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_3C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_3D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_3E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_3F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +input CLK, CE; +input OCE; +input RESET; +input [13:0] AD; +input [2:0] BLKSEL; +output [35:0] DO; +endmodule + + +module pROM (...); +parameter READ_MODE = 1'b0; +parameter BIT_WIDTH = 32; +parameter RESET_MODE = "SYNC"; +parameter INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; +input CLK, CE; +input OCE; +input RESET; +input [13:0] AD; +output [31:0] DO; +endmodule + + +module pROMX9 (...); +parameter READ_MODE = 1'b0; +parameter BIT_WIDTH = 36; +parameter RESET_MODE = "SYNC"; +parameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_01 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_02 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_03 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_04 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_05 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_06 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_07 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_08 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_09 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_0A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_0B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_0C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_0D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_0E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_0F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_10 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_11 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_12 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_13 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_14 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_15 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_16 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_17 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_18 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_19 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_1A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_1B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_1C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_1D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_1E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_1F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_20 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_21 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_22 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_23 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_24 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_25 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_26 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_27 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_28 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_29 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_2A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_2B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_2C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_2D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_2E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_2F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_30 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_31 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_32 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_33 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_34 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_35 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_36 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_37 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_38 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_39 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_3A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_3B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_3C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_3D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_3E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_3F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +input CLK, CE; +input OCE; +input RESET; +input [13:0] AD; +output [35:0] DO; +endmodule + + +module SDPB (...); +parameter READ_MODE = 1'b0; +parameter BIT_WIDTH_0 = 32; +parameter BIT_WIDTH_1 = 32; +parameter BLK_SEL_0 = 3'b000; +parameter BLK_SEL_1 = 3'b000; +parameter RESET_MODE = "SYNC"; +parameter INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; +input CLKA, CEA, CLKB, CEB; +input OCE; +input RESETA, RESETB; +input [13:0] ADA, ADB; +input [31:0] DI; +input [2:0] BLKSELA, BLKSELB; +output [31:0] DO; +endmodule + + +module SDPX9B (...); +parameter READ_MODE = 1'b0; +parameter BIT_WIDTH_0 = 36; +parameter BIT_WIDTH_1 = 36; +parameter BLK_SEL_0 = 3'b000; +parameter BLK_SEL_1 = 3'b000; +parameter RESET_MODE = "SYNC"; +parameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_01 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_02 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_03 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_04 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_05 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_06 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_07 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_08 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_09 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_0A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_0B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_0C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_0D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_0E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_0F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_10 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_11 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_12 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_13 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_14 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_15 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_16 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_17 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_18 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_19 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_1A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_1B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_1C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_1D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_1E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_1F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_20 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_21 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_22 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_23 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_24 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_25 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_26 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_27 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_28 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_29 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_2A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_2B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_2C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_2D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_2E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_2F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_30 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_31 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_32 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_33 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_34 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_35 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_36 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_37 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_38 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_39 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_3A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_3B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_3C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_3D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_3E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_3F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +input CLKA, CEA, CLKB, CEB; +input OCE; +input RESETA, RESETB; +input [13:0] ADA, ADB; +input [2:0] BLKSELA, BLKSELB; +input [35:0] DI; +output [35:0] DO; +endmodule + + +module DPB (...); +parameter READ_MODE0 = 1'b0; +parameter READ_MODE1 = 1'b0; +parameter WRITE_MODE0 = 2'b00; +parameter WRITE_MODE1 = 2'b00; +parameter BIT_WIDTH_0 = 16; +parameter BIT_WIDTH_1 = 16; +parameter BLK_SEL_0 = 3'b000; +parameter BLK_SEL_1 = 3'b000; +parameter RESET_MODE = "SYNC"; +parameter INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; +input CLKA, CEA, CLKB, CEB; +input OCEA, OCEB; +input RESETA, RESETB; +input WREA, WREB; +input [13:0] ADA, ADB; +input [2:0] BLKSELA, BLKSELB; +input [15:0] DIA, DIB; +output [15:0] DOA, DOB; +endmodule + + +module DPX9B (...); +parameter READ_MODE0 = 1'b0; +parameter READ_MODE1 = 1'b0; +parameter WRITE_MODE0 = 2'b00; +parameter WRITE_MODE1 = 2'b00; +parameter BIT_WIDTH_0 = 18; +parameter BIT_WIDTH_1 = 18; +parameter BLK_SEL_0 = 3'b000; +parameter BLK_SEL_1 = 3'b000; +parameter RESET_MODE = "SYNC"; +parameter INIT_RAM_00 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_01 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_02 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_03 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_04 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_05 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_06 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_07 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_08 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_09 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_0A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_0B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_0C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_0D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_0E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_0F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_10 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_11 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_12 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_13 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_14 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_15 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_16 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_17 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_18 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_19 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_1A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_1B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_1C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_1D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_1E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_1F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_20 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_21 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_22 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_23 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_24 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_25 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_26 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_27 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_28 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_29 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_2A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_2B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_2C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_2D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_2E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_2F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_30 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_31 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_32 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_33 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_34 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_35 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_36 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_37 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_38 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_39 = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_3A = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_3B = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_3C = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_3D = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_3E = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +parameter INIT_RAM_3F = 288'h000000000000000000000000000000000000000000000000000000000000000000000000; +input CLKA, CEA, CLKB, CEB; +input OCEA, OCEB; +input RESETA, RESETB; +input WREA, WREB; +input [13:0] ADA, ADB; +input [17:0] DIA, DIB; +input [2:0] BLKSELA, BLKSELB; +output [17:0] DOA, DOB; +endmodule + + +module PADD18 (...); +input [17:0] A; +input [17:0] B; +input ASEL; +input CE,CLK,RESET; +input [17:0] SI,SBI; +output [17:0] SO,SBO; +output [17:0] DOUT; +parameter AREG = 1'b0; +parameter BREG = 1'b0; +parameter ADD_SUB = 1'b0; +parameter PADD_RESET_MODE = "SYNC"; +parameter BSEL_MODE = 1'b1; +parameter SOREG = 1'b0; +endmodule + +module PADD9 (...); +input [8:0] A; +input [8:0] B; +input ASEL; +input CE,CLK,RESET; +input [8:0] SI,SBI; +output [8:0] SO,SBO; +output [8:0] DOUT; +parameter AREG = 1'b0; +parameter BREG = 1'b0; +parameter ADD_SUB = 1'b0; +parameter PADD_RESET_MODE = "SYNC"; +parameter BSEL_MODE = 1'b1; +parameter SOREG = 1'b0; +endmodule + +module MULT9X9 (...); +input [8:0] A,SIA; +input [8:0] B,SIB; +input ASIGN,BSIGN; +input ASEL,BSEL; +input CE; +input CLK; +input RESET; +output [17:0] DOUT; +output [8:0] SOA,SOB; +parameter AREG = 1'b0; +parameter BREG = 1'b0; +parameter OUT_REG = 1'b0; +parameter PIPE_REG = 1'b0; +parameter ASIGN_REG = 1'b0; +parameter BSIGN_REG = 1'b0; +parameter SOA_REG = 1'b0; +parameter MULT_RESET_MODE = "SYNC"; +endmodule + +module MULT18X18 (...); +input [17:0] A,SIA; +input [17:0] B,SIB; +input ASIGN,BSIGN; +input ASEL,BSEL; +input CE; +input CLK; +input RESET; +output [35:0] DOUT; +output [17:0] SOA,SOB; +parameter AREG = 1'b0; +parameter BREG = 1'b0; +parameter OUT_REG = 1'b0; +parameter PIPE_REG = 1'b0; +parameter ASIGN_REG = 1'b0; +parameter BSIGN_REG = 1'b0; +parameter SOA_REG = 1'b0; +parameter MULT_RESET_MODE = "SYNC"; +endmodule + +module MULT36X36 (...); +input [35:0] A; +input [35:0] B; +input ASIGN,BSIGN; +input CE; +input CLK; +input RESET; +output [71:0] DOUT; +parameter AREG = 1'b0; +parameter BREG = 1'b0; +parameter OUT0_REG = 1'b0; +parameter OUT1_REG = 1'b0; +parameter PIPE_REG = 1'b0; +parameter ASIGN_REG = 1'b0; +parameter BSIGN_REG = 1'b0; +parameter MULT_RESET_MODE = "SYNC"; +endmodule + +module MULTALU36X18 (...); +input [17:0] A; +input [35:0] B; +input [53:0] C; +input ASIGN,BSIGN,ACCLOAD; +input CE; +input CLK; +input RESET; +input [54:0] CASI; +output [53:0] DOUT; +output [54:0] CASO; +parameter AREG = 1'b0; +parameter BREG = 1'b0; +parameter CREG = 1'b0; +parameter OUT_REG = 1'b0; +parameter PIPE_REG = 1'b0; +parameter ASIGN_REG = 1'b0; +parameter BSIGN_REG = 1'b0; +parameter ACCLOAD_REG0 = 1'b0; +parameter ACCLOAD_REG1 = 1'b0; +parameter MULT_RESET_MODE = "SYNC"; +parameter MULTALU36X18_MODE = 0; +parameter C_ADD_SUB = 1'b0; +endmodule + +module MULTADDALU18X18 (...); +input [17:0] A0; +input [17:0] B0; +input [17:0] A1; +input [17:0] B1; +input [53:0] C; +input [17:0] SIA, SIB; +input [1:0] ASIGN, BSIGN; +input [1:0] ASEL, BSEL; +input [54:0] CASI; +input CE; +input CLK; +input RESET; +input ACCLOAD; +output [53:0] DOUT; +output [54:0] CASO; +output [17:0] SOA, SOB; +parameter A0REG = 1'b0; +parameter A1REG = 1'b0; +parameter B0REG = 1'b0; +parameter B1REG = 1'b0; +parameter CREG = 1'b0; +parameter PIPE0_REG = 1'b0; +parameter PIPE1_REG = 1'b0; +parameter OUT_REG = 1'b0; +parameter ASIGN0_REG = 1'b0; +parameter ASIGN1_REG = 1'b0; +parameter ACCLOAD_REG0 = 1'b0; +parameter ACCLOAD_REG1 = 1'b0; +parameter BSIGN0_REG = 1'b0; +parameter BSIGN1_REG = 1'b0; +parameter SOA_REG = 1'b0; +parameter B_ADD_SUB = 1'b0; +parameter C_ADD_SUB = 1'b0; +parameter MULTADDALU18X18_MODE = 0; +parameter MULT_RESET_MODE = "SYNC"; +endmodule + +module MULTALU18X18 (...); +input [17:0] A, B; +input CLK,CE,RESET; +input ASIGN, BSIGN; +input ACCLOAD,DSIGN; +input [53:0] C,D; +input [54:0] CASI; +output [53:0] DOUT; +output [54:0] CASO; +parameter AREG = 1'b0; +parameter BREG = 1'b0; +parameter CREG = 1'b0; +parameter DREG = 1'b0; +parameter DSIGN_REG = 1'b0; +parameter ASIGN_REG = 1'b0; +parameter BSIGN_REG = 1'b0; +parameter ACCLOAD_REG0 = 1'b0; +parameter ACCLOAD_REG1 = 1'b0; +parameter MULT_RESET_MODE = "SYNC"; +parameter PIPE_REG = 1'b0; +parameter OUT_REG = 1'b0; +parameter B_ADD_SUB = 1'b0; +parameter C_ADD_SUB = 1'b0; +parameter MULTALU18X18_MODE = 0; +endmodule + +module ALU54D (...); +input [53:0] A, B; +input ASIGN,BSIGN; +input ACCLOAD; +input [54:0] CASI; +input CLK, CE, RESET; +output [53:0] DOUT; +output [54:0] CASO; +parameter AREG = 1'b0; +parameter BREG = 1'b0; +parameter ASIGN_REG = 1'b0; +parameter BSIGN_REG = 1'b0; +parameter ACCLOAD_REG = 1'b0; +parameter OUT_REG = 1'b0; +parameter B_ADD_SUB = 1'b0; +parameter C_ADD_SUB = 1'b0; +parameter ALUD_MODE = 0; +parameter ALU_RESET_MODE = "SYNC"; +endmodule + +module BUFG (...); +output O; +input I; +endmodule + + +module BUFS (...); +output O; +input I; +endmodule + + +module PLL (...); +input CLKIN; +input CLKFB; +input RESET; +input RESET_P; +input RESET_I; +input RESET_S; +input [5:0] FBDSEL; +input [5:0] IDSEL; +input [5:0] ODSEL; +input [3:0] PSDA,FDLY; +input [3:0] DUTYDA; +output CLKOUT; +output LOCK; +output CLKOUTP; +output CLKOUTD; +output CLKOUTD3; +parameter FCLKIN = "100.0"; +parameter DYN_IDIV_SEL= "false"; +parameter IDIV_SEL = 0; +parameter DYN_FBDIV_SEL= "false"; +parameter FBDIV_SEL = 0; +parameter DYN_ODIV_SEL= "false"; +parameter ODIV_SEL = 8; +parameter PSDA_SEL= "0000"; +parameter DYN_DA_EN = "false"; +parameter DUTYDA_SEL= "1000"; +parameter CLKOUT_FT_DIR = 1'b1; +parameter CLKOUTP_FT_DIR = 1'b1; +parameter CLKOUT_DLY_STEP = 0; +parameter CLKOUTP_DLY_STEP = 0; +parameter CLKFB_SEL = "internal"; +parameter CLKOUT_BYPASS = "false"; +parameter CLKOUTP_BYPASS = "false"; +parameter CLKOUTD_BYPASS = "false"; +parameter DYN_SDIV_SEL = 2; +parameter CLKOUTD_SRC = "CLKOUT"; +parameter CLKOUTD3_SRC = "CLKOUT"; +parameter DEVICE = "GW1N-4"; +endmodule + +module TLVDS_IBUF (...); +output O; +input I, IB; +endmodule + +module TLVDS_TBUF (...); +output O, OB; +input I, OEN; +endmodule + +module TLVDS_IOBUF (...); +output O; +inout IO, IOB; +input I, OEN; +endmodule + +module ELVDS_IBUF (...); +output O; +input I, IB; +endmodule + +module ELVDS_TBUF (...); +output O, OB; +input I, OEN; +endmodule + +module ELVDS_IOBUF (...); +output O; +inout IO, IOB; +input I, OEN; +endmodule + +module MIPI_IBUF (...); +output OH, OL, OB; +inout IO, IOB; +input I, IB; +input OEN, OENB; +input HSREN; +endmodule + +module MIPI_IBUF_HS (...); +output OH; +input I, IB; +endmodule + +module MIPI_IBUF_LP (...); +output OL; +output OB; +input I; +input IB; +endmodule + +module MIPI_OBUF (...); +output O, OB; +input I, IB, MODESEL; +endmodule + +module MIPI_OBUF_A (...); +output O, OB; +input I, IB, IL, MODESEL; +endmodule + +module I3C_IOBUF (...); +output O; +inout IO; +input I, MODESEL; +endmodule + +module CLKDIV (...); +input HCLKIN; +input RESETN; +input CALIB; +output CLKOUT; +parameter DIV_MODE = "2"; +parameter GSREN = "false"; +endmodule + +module DHCEN (...); +input CLKIN,CE; +output CLKOUT; +endmodule + +module DLL (...); +input CLKIN; +input STOP; +input UPDNCNTL; +input RESET; +output [7:0]STEP; +output LOCK; +parameter DLL_FORCE = 0; +parameter CODESCAL="000"; +parameter SCAL_EN="true"; +parameter DIV_SEL = 1'b0; +endmodule + +module DLLDLY (...); +input CLKIN; +input [7:0] DLLSTEP; +input DIR,LOADN,MOVE; +output CLKOUT; +output FLAG; +parameter DLL_INSEL = 1'b1; +parameter DLY_SIGN = 1'b0; +parameter DLY_ADJ = 0; +endmodule + +module FLASH96K (...); +input [5:0] RA,CA,PA; +input [3:0] MODE; +input [1:0] SEQ; +input ACLK,PW,RESET,PE,OE; +input [1:0] RMODE,WMODE; +input [1:0] RBYTESEL,WBYTESEL; +input [31:0] DIN; +output [31:0] DOUT; +endmodule + +module FLASH256K (...); +input[6:0]XADR; +input[5:0]YADR; +input XE,YE,SE; +input ERASE,PROG,NVSTR; +input [31:0] DIN; +output reg [31:0] DOUT; +parameter IDLE = 4'd0, + ERA_S1 = 4'd1, + ERA_S2 = 4'd2, + ERA_S3 = 4'd3, + ERA_S4 = 4'd4, + ERA_S5 = 4'd5, + PRO_S1 = 4'd6, + PRO_S2 = 4'd7, + PRO_S3 = 4'd8, + PRO_S4 = 4'd9, + PRO_S5 = 4'd10, + RD_S1 = 4'd11, + RD_S2 = 4'd12; +endmodule + +module FLASH608K (...); +input[8:0]XADR; +input[5:0]YADR; +input XE,YE,SE; +input ERASE,PROG,NVSTR; +input [31:0] DIN; +output reg [31:0] DOUT; +parameter IDLE = 4'd0, + ERA_S1 = 4'd1, + ERA_S2 = 4'd2, + ERA_S3 = 4'd3, + ERA_S4 = 4'd4, + ERA_S5 = 4'd5, + PRO_S1 = 4'd6, + PRO_S2 = 4'd7, + PRO_S3 = 4'd8, + PRO_S4 = 4'd9, + PRO_S5 = 4'd10, + RD_S1 = 4'd11, + RD_S2 = 4'd12; +endmodule + +module DCS (...); +input CLK0, CLK1, CLK2, CLK3, SELFORCE; +input [3:0] CLKSEL; +output CLKOUT; +endmodule + +module DQCE (...); +input CLKIN; +input CE; +output CLKOUT; +endmodule + +module FLASH128K (...); +input [31:0] DIN; +input [14:0] ADDR; +input CS,AE,OE; +input PCLK; +input PROG, SERA, MASE; +input NVSTR; +input IFREN; +input RESETN; +output [31:0] DOUT; +output TBIT; +parameter IDLE = 4'd0, + READ_S1 = 4'd1, + READ_S2 = 4'd2, + PROG_S1 = 4'd3, + PROG_S2 = 4'd4, + PROG_S3 = 4'd5, + PROG_S4 = 4'd6, + SERA_S1 = 4'd7, + SERA_S2 = 4'd8, + SERA_S3 = 4'd9, + SERA_S4 = 4'd10, + MASE_S1 = 4'd11, + MASE_S2 = 4'd12, + MASE_S3 = 4'd13, + MASE_S4 = 4'd14; +endmodule + +module MCU (...); +endmodule + +module USB20_PHY (...); +parameter DATABUS16_8 = 1'b0; +parameter ADP_PRBEN = 1'b0; +parameter TEST_MODE = 5'b00000; +parameter HSDRV1 = 1'b0; +parameter HSDRV0 = 1'b0; +parameter CLK_SEL = 1'b0; +parameter M = 4'b0000; +parameter N = 6'b101000; +parameter C = 2'b01; +parameter FOC_LOCK = 1'b0; +input [15:0] DATAIN; +input TXVLD; +input TXVLDH; +input RESET; +input SUSPENDM; +input [1:0] XCVRSEL; +input TERMSEL; +input [1:0] OPMODE; +output [15:0] DATAOUT; +output TXREADY; +output RXACTIVE; +output RXVLD; +output RXVLDH; +output CLK; +output RXERROR; +inout DP; +inout DM; +output [1:0] LINESTATE; +input IDPULLUP; +input DPPD; +input DMPD; +input CHARGVBUS; +input DISCHARGVBUS; +input TXBITSTUFFEN; +input TXBITSTUFFENH; +input TXENN; +input TXDAT; +input TXSE0; +input FSLSSERIAL; +output HOSTDIS; +output IDDIG; +output ADPPRB; +output ADPSNS; +output SESSVLD; +output VBUSVLD; +output RXDP; +output RXDM; +output RXRCV; +output LBKERR; +output CLKRDY; +input INTCLK; +inout ID; +inout VBUS; +inout REXT; +input XIN; +inout XOUT; +input TEST; +output CLK480PAD; +input SCANCLK; +input SCANEN; +input SCANMODE; +input TRESETN; +input SCANIN1; +output SCANOUT1; +input SCANIN2; +output SCANOUT2; +input SCANIN3; +output SCANOUT3; +input SCANIN4; +output SCANOUT4; +input SCANIN5; +output SCANOUT5; +input SCANIN6; +output SCANOUT6; +endmodule + +module ADC (...); +endmodule + +module BANDGAP (...); +input BGEN; +endmodule + +module CLKDIV2 (...); +parameter GSREN = "false"; +input HCLKIN, RESETN; +output CLKOUT; +endmodule + +module DCC (...); +output CLKOUT; +input CLKIN; +parameter DCC_EN = 1'b1; +parameter FCLKIN = 50.0; +endmodule + +module DHCENC (...); +input CLKIN, CE; +output CLKOUT, CLKOUTN; +endmodule + +module EMCU (...); +endmodule + +module FLASH64K (...); +input[4:0]XADR; +input[5:0]YADR; +input XE,YE,SE; +input ERASE,PROG,NVSTR; +input SLEEP; +input [31:0] DIN; +output reg [31:0] DOUT; +parameter IDLE = 4'd0, + ERA_S1 = 4'd1, + ERA_S2 = 4'd2, + ERA_S3 = 4'd3, + ERA_S4 = 4'd4, + ERA_S5 = 4'd5, + PRO_S1 = 4'd6, + PRO_S2 = 4'd7, + PRO_S3 = 4'd8, + PRO_S4 = 4'd9, + PRO_S5 = 4'd10, + RD_S1 = 4'd11, + RD_S2 = 4'd12; +endmodule + +module FLASH64KZ (...); +input[4:0]XADR; +input[5:0]YADR; +input XE,YE,SE; +input ERASE,PROG,NVSTR; +input [31:0] DIN; +output reg [31:0] DOUT; +parameter IDLE = 4'd0, + ERA_S1 = 4'd1, + ERA_S2 = 4'd2, + ERA_S3 = 4'd3, + ERA_S4 = 4'd4, + ERA_S5 = 4'd5, + PRO_S1 = 4'd6, + PRO_S2 = 4'd7, + PRO_S3 = 4'd8, + PRO_S4 = 4'd9, + PRO_S5 = 4'd10, + RD_S1 = 4'd11, + RD_S2 = 4'd12; +endmodule + +module I3C (...); +parameter ADDRESS = 7'b0000000; +input LGYS, CMS, ACS, AAS, STOPS, STRTS; +output LGYO, CMO, ACO, AAO, SIO, STOPO, STRTO; +input LGYC, CMC, ACC, AAC, SIC, STOPC, STRTC; +input STRTHDS, SENDAHS, SENDALS, ACKHS; +input ACKLS, STOPSUS, STOPHDS, SENDDHS; +input SENDDLS, RECVDHS, RECVDLS, ADDRS; +output PARITYERROR; +input [7:0] DI; +output [7:0] DOBUF; +output [7:0] DO; +output [7:0] STATE; +input SDAI, SCLI; +output SDAO, SCLO; +output SDAOEN, SCLOEN; +output SDAPULLO, SCLPULLO; +output SDAPULLOEN, SCLPULLOEN; +input CE, RESET, CLK; +endmodule + +module IODELAYA (...); +parameter C_STATIC_DLY = 0; +input DI; +input SDTAP; +input SETN; +input VALUE; +output DF; +output DO; +endmodule + +module IODELAYC (...); +parameter C_STATIC_DLY = 0; +parameter DYN_DA_SEL = "false"; +parameter DA_SEL = 2'b00; +input DI; +input SDTAP; +input SETN; +input VALUE; +input [1:0] DASEL; +input [1:0] DAADJ; +output DF; +output DO; +output DAO; +endmodule + + +module SPMI (...); +parameter FUNCTION_CTRL = 7'b0000000; +parameter MSID_CLKSEL = 7'b0000000; +parameter RESPOND_DELAY = 4'b0000; +parameter SCLK_NORMAL_PERIOD = 7'b0000000; +parameter SCLK_LOW_PERIOD = 7'b0000000; +parameter CLK_FREQ = 7'b0000000; +parameter SHUTDOWN_BY_ENABLE = 1'b0; +input CLKEXT, ENEXT; +inout SDATA, SCLK; +input CLK, CE, RESETN, LOCRESET; +input PA, SA, CA; +input [3:0] ADDRI; +input [7:0] DATAI; +output [3:0] ADDRO; +output [7:0] DATAO; +output [15:0] STATE; +output [3:0] CMD; +endmodule + +module IODELAYB (...); +parameter C_STATIC_DLY = 0; +parameter DELAY_MUX = 2'b00; +parameter DA_SEL = 2'b00; +input DI; +input SDTAP; +input SETN; +input VALUE; +input [1:0] DAADJ; +output DF; +output DO; +output DAO; +endmodule + + +module PLLO (...); +input CLKIN; +input CLKFB; +input RESET; +input RESET_P; +input RESET_I; +input RESET_S; +input [5:0] FBDSEL; +input [5:0] IDSEL; +input [6:0] ODSELA; +input [6:0] ODSELB; +input [6:0] ODSELC; +input [6:0] ODSELD; +input [3:0] DTA; +input [3:0] DTB; +input [4:0] ICPSEL; +input [2:0] LPFRES; +input [1:0] PSSEL; +input PSDIR; +input PSPULSE; +input ENCLKA; +input ENCLKB; +input ENCLKC; +input ENCLKD; +output LOCK; +output CLKOUTA; +output CLKOUTB; +output CLKOUTC; +output CLKOUTD; +parameter FCLKIN = "100.0"; +parameter DYN_IDIV_SEL= "FALSE"; +parameter IDIV_SEL = 0; +parameter DYN_FBDIV_SEL= "FALSE"; +parameter FBDIV_SEL = 0; +parameter DYN_ODIVA_SEL= "FALSE"; +parameter ODIVA_SEL = 6; +parameter DYN_ODIVB_SEL= "FALSE"; +parameter ODIVB_SEL = 6; +parameter DYN_ODIVC_SEL= "FALSE"; +parameter ODIVC_SEL = 6; +parameter DYN_ODIVD_SEL= "FALSE"; +parameter ODIVD_SEL = 6; +parameter CLKOUTA_EN = "TRUE"; +parameter CLKOUTB_EN = "TRUE"; +parameter CLKOUTC_EN = "TRUE"; +parameter CLKOUTD_EN = "TRUE"; +parameter DYN_DTA_SEL = "FALSE"; +parameter DYN_DTB_SEL = "FALSE"; +parameter CLKOUTA_DT_DIR = 1'b1; +parameter CLKOUTB_DT_DIR = 1'b1; +parameter CLKOUTA_DT_STEP = 0; +parameter CLKOUTB_DT_STEP = 0; +parameter CLKA_IN_SEL = 2'b00; +parameter CLKA_OUT_SEL = 1'b0; +parameter CLKB_IN_SEL = 2'b00; +parameter CLKB_OUT_SEL = 1'b0; +parameter CLKC_IN_SEL = 2'b00; +parameter CLKC_OUT_SEL = 1'b0; +parameter CLKD_IN_SEL = 2'b00; +parameter CLKD_OUT_SEL = 1'b0; +parameter CLKFB_SEL = "INTERNAL"; +parameter DYN_DPA_EN = "FALSE"; +parameter DYN_PSB_SEL = "FALSE"; +parameter DYN_PSC_SEL = "FALSE"; +parameter DYN_PSD_SEL = "FALSE"; +parameter PSB_COARSE = 1; +parameter PSB_FINE = 0; +parameter PSC_COARSE = 1; +parameter PSC_FINE = 0; +parameter PSD_COARSE = 1; +parameter PSD_FINE = 0; +parameter DTMS_ENB = "FALSE"; +parameter DTMS_ENC = "FALSE"; +parameter DTMS_END = "FALSE"; +parameter RESET_I_EN = "FALSE"; +parameter RESET_S_EN = "FALSE"; +parameter DYN_ICP_SEL= "FALSE"; +parameter ICP_SEL = 5'bXXXXX; +parameter DYN_RES_SEL= "FALSE"; +parameter LPR_REF = 7'bXXXXXXX; +endmodule + +module DCCG (...); +output CLKOUT; +input CLKIN; +parameter DCC_MODE = 2'b00; +parameter FCLKIN = 50.0; +endmodule + +module FLASH96KA (...); +input[5:0]XADR; +input[5:0]YADR; +input XE,YE,SE; +input ERASE,PROG,NVSTR; +input [31:0] DIN; +input SLEEP; +output reg [31:0] DOUT; +parameter IDLE = 4'd0, + ERA_S1 = 4'd1, + ERA_S2 = 4'd2, + ERA_S3 = 4'd3, + ERA_S4 = 4'd4, + ERA_S5 = 4'd5, + PRO_S1 = 4'd6, + PRO_S2 = 4'd7, + PRO_S3 = 4'd8, + PRO_S4 = 4'd9, + PRO_S5 = 4'd10, + RD_S1 = 4'd11, + RD_S2 = 4'd12; +endmodule + +module MIPI_DPHY_RX (...); +output [15:0] D0LN_HSRXD, D1LN_HSRXD, D2LN_HSRXD, D3LN_HSRXD; +output D0LN_HSRXD_VLD,D1LN_HSRXD_VLD,D2LN_HSRXD_VLD,D3LN_HSRXD_VLD; +output DI_LPRX0_N, DI_LPRX0_P, DI_LPRX1_N, DI_LPRX1_P, DI_LPRX2_N, DI_LPRX2_P, DI_LPRX3_N, DI_LPRX3_P; +output DI_LPRXCK_N, DI_LPRXCK_P; +output RX_CLK_O; +output DESKEW_ERROR; +inout CK_N, CK_P, RX0_N, RX0_P, RX1_N, RX1_P, RX2_N, RX2_P, RX3_N, RX3_P; +input LPRX_EN_CK, LPRX_EN_D0, LPRX_EN_D1, LPRX_EN_D2, LPRX_EN_D3; +input HSRX_ODTEN_CK, HSRX_ODTEN_D0, HSRX_ODTEN_D1, HSRX_ODTEN_D2, HSRX_ODTEN_D3; +input D0LN_HSRX_DREN, D1LN_HSRX_DREN, D2LN_HSRX_DREN, D3LN_HSRX_DREN; +input HSRX_EN_CK; +input HS_8BIT_MODE; +input RX_CLK_1X; +input RX_INVERT; +input LALIGN_EN; +input WALIGN_BY; +input DO_LPTX0_N, DO_LPTX0_P, DO_LPTX1_N, DO_LPTX1_P, DO_LPTX2_N, DO_LPTX2_P, DO_LPTX3_N, DO_LPTX3_P; +input DO_LPTXCK_N, DO_LPTXCK_P; +input LPTX_EN_CK, LPTX_EN_D0, LPTX_EN_D1, LPTX_EN_D2, LPTX_EN_D3; +input BYTE_LENDIAN; +input HSRX_STOP; +input LPRX_ULP_LN0, LPRX_ULP_LN1, LPRX_ULP_LN2, LPRX_ULP_LN3, LPRX_ULP_CK; +input PWRON; +input RESET; +input [2:0] DESKEW_LNSEL; +input [7:0] DESKEW_MTH; +input [6:0] DESKEW_OWVAL; +input DESKEW_REQ; +input DRST_N; +input ONE_BYTE0_MATCH; +input WORD_LENDIAN; +input [2:0] FIFO_RD_STD; +parameter ALIGN_BYTE = 8'b10111000; +parameter MIPI_LANE0_EN = 1'b0; +parameter MIPI_LANE1_EN = 1'b0; +parameter MIPI_LANE2_EN = 1'b0; +parameter MIPI_LANE3_EN = 1'b0; +parameter MIPI_CK_EN = 1'b1; +parameter SYNC_CLK_SEL = 1'b1; +endmodule + +module CLKDIVG (...); +input CLKIN; +input RESETN; +input CALIB; +output CLKOUT; +parameter DIV_MODE = "2"; +parameter GSREN = "false"; +endmodule diff --git a/yosys/techlibs/gowin/synth_gowin.cc b/yosys/techlibs/gowin/synth_gowin.cc index 0dffdf498b3..3b9d7424a7b 100644 --- a/yosys/techlibs/gowin/synth_gowin.cc +++ b/yosys/techlibs/gowin/synth_gowin.cc @@ -207,6 +207,7 @@ struct SynthGowinPass : public ScriptPass if (check_label("begin")) { run("read_verilog -specify -lib +/gowin/cells_sim.v"); + run("read_verilog -specify -lib +/gowin/cells_xtra.v"); run(stringf("hierarchy -check %s", help_mode ? "-top " : top_opt.c_str())); } diff --git a/yosys/techlibs/ice40/cells_sim.v b/yosys/techlibs/ice40/cells_sim.v index 52e8e2e3acc..8943815bff4 100644 --- a/yosys/techlibs/ice40/cells_sim.v +++ b/yosys/techlibs/ice40/cells_sim.v @@ -1674,7 +1674,7 @@ module SB_RAM40_4K ( // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L400 $setup(WE, posedge WCLK, 133); // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L401 - (posedge RCLK => (RDATA : 16'bx)) = 2146; + (posedge RCLK *> (RDATA : 16'bx)) = 2146; endspecify `endif `ifdef ICE40_LP @@ -1696,7 +1696,7 @@ module SB_RAM40_4K ( // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L400 $setup(WE, posedge WCLK, 196); // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L401 - (posedge RCLK => (RDATA : 16'bx)) = 3163; + (posedge RCLK *> (RDATA : 16'bx)) = 3163; endspecify `endif `ifdef ICE40_U @@ -1718,7 +1718,7 @@ module SB_RAM40_4K ( // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13025 $setup(WE, posedge WCLK, 252); // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13026 - (posedge RCLK => (RDATA : 16'bx)) = 1179; + (posedge RCLK *> (RDATA : 16'bx)) = 1179; endspecify `endif endmodule @@ -1810,7 +1810,7 @@ module SB_RAM40_4KNR ( // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L400 $setup(WE, posedge WCLK, 133); // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L401 - (posedge RCLKN => (RDATA : 16'bx)) = 2146; + (posedge RCLKN *> (RDATA : 16'bx)) = 2146; endspecify `endif `ifdef ICE40_LP @@ -1832,7 +1832,7 @@ module SB_RAM40_4KNR ( // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L400 $setup(WE, posedge WCLK, 196); // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L401 - (posedge RCLKN => (RDATA : 16'bx)) = 3163; + (posedge RCLKN *> (RDATA : 16'bx)) = 3163; endspecify `endif `ifdef ICE40_U @@ -1854,7 +1854,7 @@ module SB_RAM40_4KNR ( // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13025 $setup(WE, posedge WCLK, 252); // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13026 - (posedge RCLKN => (RDATA : 16'bx)) = 1179; + (posedge RCLKN *> (RDATA : 16'bx)) = 1179; endspecify `endif endmodule @@ -1946,7 +1946,7 @@ module SB_RAM40_4KNW ( // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L400 $setup(WE, posedge WCLKN, 133); // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L401 - (posedge RCLK => (RDATA : 16'bx)) = 2146; + (posedge RCLK *> (RDATA : 16'bx)) = 2146; endspecify `endif `ifdef ICE40_LP @@ -1968,7 +1968,7 @@ module SB_RAM40_4KNW ( // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L400 $setup(WE, posedge WCLKN, 196); // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L401 - (posedge RCLK => (RDATA : 16'bx)) = 3163; + (posedge RCLK *> (RDATA : 16'bx)) = 3163; endspecify `endif `ifdef ICE40_U @@ -1990,7 +1990,7 @@ module SB_RAM40_4KNW ( // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13025 $setup(WE, posedge WCLKN, 252); // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13026 - (posedge RCLK => (RDATA : 16'bx)) = 1179; + (posedge RCLK *> (RDATA : 16'bx)) = 1179; endspecify `endif endmodule @@ -2082,7 +2082,7 @@ module SB_RAM40_4KNRNW ( // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L400 $setup(WE, posedge WCLKN, 133); // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L401 - (posedge RCLKN => (RDATA : 16'bx)) = 2146; + (posedge RCLKN *> (RDATA : 16'bx)) = 2146; endspecify `endif `ifdef ICE40_LP @@ -2104,7 +2104,7 @@ module SB_RAM40_4KNRNW ( // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L400 $setup(WE, posedge WCLKN, 196); // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L401 - (posedge RCLKN => (RDATA : 16'bx)) = 3163; + (posedge RCLKN *> (RDATA : 16'bx)) = 3163; endspecify `endif `ifdef ICE40_U @@ -2126,7 +2126,7 @@ module SB_RAM40_4KNRNW ( // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13025 $setup(WE, posedge WCLKN, 252); // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13026 - (posedge RCLKN => (RDATA : 16'bx)) = 1179; + (posedge RCLKN *> (RDATA : 16'bx)) = 1179; endspecify `endif endmodule @@ -2653,9 +2653,9 @@ module SB_SPRAM256KA ( // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13206 $setup(WREN, posedge CLOCK, 289); // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13207-L13222 - (posedge CLOCK => (DATAOUT : 16'bx)) = 1821; + (posedge CLOCK *> (DATAOUT : 16'bx)) = 1821; // https://github.com/YosysHQ/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L13223-L13238 - (posedge SLEEP => (DATAOUT : 16'b0)) = 1099; + (posedge SLEEP *> (DATAOUT : 16'b0)) = 1099; endspecify `endif endmodule diff --git a/yosys/techlibs/intel_alm/common/alm_sim.v b/yosys/techlibs/intel_alm/common/alm_sim.v index 242f1003f2f..d3bd673903f 100644 --- a/yosys/techlibs/intel_alm/common/alm_sim.v +++ b/yosys/techlibs/intel_alm/common/alm_sim.v @@ -1,5 +1,5 @@ // The core logic primitive of the Cyclone V/10GX is the Adaptive Logic Module -// (ALM). Each ALM is made up of an 8-input, 2-output look-up table, covered +// (ALM). Each ALM is made up of an 8-input, 2-output look-up table, covered // in this file, connected to combinational outputs, a carry chain, and four // D flip-flops (which are covered as MISTRAL_FF in dff_sim.v). // @@ -283,10 +283,8 @@ assign Q = ~A; endmodule -// Despite the abc9_carry attributes, this doesn't seem to stop ABC9 adding illegal fanout to the carry chain that nextpnr cannot handle. -// So we treat it as a total blackbox from ABC9's perspective for now. -// (* abc9_box, lib_whitebox *) -module MISTRAL_ALUT_ARITH(input A, B, C, D0, D1, /* (* abc9_carry *) */ input CI, output SO, /* (* abc9_carry *) */ output CO); +(* abc9_box, lib_whitebox *) +module MISTRAL_ALUT_ARITH(input A, B, C, D0, D1, (* abc9_carry *) input CI, output SO, (* abc9_carry *) output CO); parameter LUT0 = 16'h0000; parameter LUT1 = 16'h0000; diff --git a/yosys/techlibs/intel_alm/common/bram_m10k.txt b/yosys/techlibs/intel_alm/common/bram_m10k.txt index 560711b658e..14688a04c94 100644 --- a/yosys/techlibs/intel_alm/common/bram_m10k.txt +++ b/yosys/techlibs/intel_alm/common/bram_m10k.txt @@ -1,5 +1,5 @@ bram $__MISTRAL_M10K - init 0 # TODO: Re-enable when I figure out how BRAM init works + init 1 abits 13 @D8192x1 dbits 1 @D8192x1 abits 12 @D4096x2 @@ -10,6 +10,8 @@ bram $__MISTRAL_M10K dbits 10 @D1024x10 abits 9 @D512x20 dbits 20 @D512x20 + abits 8 @D256x40 + dbits 40 @D256x40 groups 2 ports 1 1 wrmode 1 0 diff --git a/yosys/techlibs/intel_alm/common/bram_m10k_map.v b/yosys/techlibs/intel_alm/common/bram_m10k_map.v index 8f9d4a3b3ff..d48a1999c05 100644 --- a/yosys/techlibs/intel_alm/common/bram_m10k_map.v +++ b/yosys/techlibs/intel_alm/common/bram_m10k_map.v @@ -2,6 +2,8 @@ module \$__MISTRAL_M10K (CLK1, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN); +parameter INIT = 0; + parameter CFG_ABITS = 10; parameter CFG_DBITS = 10; @@ -11,6 +13,14 @@ input [CFG_DBITS-1:0] A1DATA; input A1EN, B1EN; output reg [CFG_DBITS-1:0] B1DATA; -MISTRAL_M10K #(.CFG_ABITS(CFG_ABITS), .CFG_DBITS(CFG_DBITS)) _TECHMAP_REPLACE_ (.CLK1(CLK1), .A1ADDR(A1ADDR), .A1DATA(A1DATA), .A1EN(!A1EN), .B1ADDR(B1ADDR), .B1DATA(B1DATA), .B1EN(B1EN)); +// Normal M10K configs use WREN[1], which is negative-true. +// However, 8x40-bit mode uses WREN[0], which is positive-true. +wire a1en; +if (CFG_DBITS == 40) + assign a1en = A1EN; +else + assign a1en = !A1EN; + +MISTRAL_M10K #(.INIT(INIT), .CFG_ABITS(CFG_ABITS), .CFG_DBITS(CFG_DBITS)) _TECHMAP_REPLACE_ (.CLK1(CLK1), .A1ADDR(A1ADDR), .A1DATA(A1DATA), .A1EN(a1en), .B1ADDR(B1ADDR), .B1DATA(B1DATA), .B1EN(B1EN)); -endmodule \ No newline at end of file +endmodule diff --git a/yosys/techlibs/intel_alm/common/mem_sim.v b/yosys/techlibs/intel_alm/common/mem_sim.v index c9ba8c7f129..563f1d2413e 100644 --- a/yosys/techlibs/intel_alm/common/mem_sim.v +++ b/yosys/techlibs/intel_alm/common/mem_sim.v @@ -3,7 +3,7 @@ // In addition to Logic Array Blocks (LABs) that contain ten Adaptive Logic // Modules (ALMs, see alm_sim.v), the Cyclone V/10GX also contain // Memory/Logic Array Blocks (MLABs) that can act as either ten ALMs, or utilise -// the memory the ALM uses to store the look-up table data for general usage, +// the memory the ALM uses to store the look-up table data for general usage, // producing a 32 address by 20-bit block of memory. MLABs are spread out // around the chip, so they can be placed near where they are needed, rather than // being comparatively limited in placement for a deep but narrow memory such as @@ -43,7 +43,7 @@ // Quartus will pack external flops into the MLAB, but this is an assumption // that needs testing. -// The vendor sim model outputs 'x for a very short period (a few +// The vendor sim model outputs 'x for a very short period (a few // combinational delta cycles) after each write. This has been omitted from // the following model because it's very difficult to trigger this in practice // as clock cycles will be much longer than any potential blip of 'x, so the @@ -110,6 +110,8 @@ endmodule module MISTRAL_M10K(CLK1, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN); +parameter INIT = 0; + parameter CFG_ABITS = 10; parameter CFG_DBITS = 10; @@ -119,7 +121,7 @@ input [CFG_DBITS-1:0] A1DATA; input A1EN, B1EN; output reg [CFG_DBITS-1:0] B1DATA; -reg [2**CFG_ABITS * CFG_DBITS - 1 : 0] mem = 0; +reg [2**CFG_ABITS * CFG_DBITS - 1 : 0] mem = INIT; `ifdef cyclonev specify diff --git a/yosys/techlibs/machxo2/Makefile.inc b/yosys/techlibs/machxo2/Makefile.inc index f6aafbd2bde..cd4e27884fc 100644 --- a/yosys/techlibs/machxo2/Makefile.inc +++ b/yosys/techlibs/machxo2/Makefile.inc @@ -1,10 +1,14 @@ OBJS += techlibs/machxo2/synth_machxo2.o +$(eval $(call add_share_file,share/machxo2,techlibs/ecp5/cells_io.vh)) $(eval $(call add_share_file,share/machxo2,techlibs/machxo2/cells_map.v)) $(eval $(call add_share_file,share/machxo2,techlibs/machxo2/cells_sim.v)) +$(eval $(call add_share_file,share/machxo2,techlibs/machxo2/cells_bb.v)) + +$(eval $(call add_share_file,share/machxo2,techlibs/ecp5/lutrams.txt)) +$(eval $(call add_share_file,share/machxo2,techlibs/ecp5/lutrams_map.v)) -$(eval $(call add_share_file,share/machxo2,techlibs/machxo2/lutrams.txt)) -$(eval $(call add_share_file,share/machxo2,techlibs/machxo2/lutrams_map.v)) $(eval $(call add_share_file,share/machxo2,techlibs/machxo2/brams.txt)) $(eval $(call add_share_file,share/machxo2,techlibs/machxo2/brams_map.v)) +$(eval $(call add_share_file,share/machxo2,techlibs/machxo2/arith_map.v)) diff --git a/yosys/techlibs/machxo2/arith_map.v b/yosys/techlibs/machxo2/arith_map.v new file mode 100644 index 00000000000..ab4a6b1da6c --- /dev/null +++ b/yosys/techlibs/machxo2/arith_map.v @@ -0,0 +1,90 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2012 Claire Xenia Wolf + * Copyright (C) 2018 gatecat + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +(* techmap_celltype = "$alu" *) +module _80_ecp5_alu (A, B, CI, BI, X, Y, CO); + parameter A_SIGNED = 0; + parameter B_SIGNED = 0; + parameter A_WIDTH = 1; + parameter B_WIDTH = 1; + parameter Y_WIDTH = 1; + + (* force_downto *) + input [A_WIDTH-1:0] A; + (* force_downto *) + input [B_WIDTH-1:0] B; + (* force_downto *) + output [Y_WIDTH-1:0] X, Y; + + input CI, BI; + (* force_downto *) + output [Y_WIDTH-1:0] CO; + + wire _TECHMAP_FAIL_ = Y_WIDTH <= 4; + + (* force_downto *) + wire [Y_WIDTH-1:0] A_buf, B_buf; + \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf)); + \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf)); + + function integer round_up2; + input integer N; + begin + round_up2 = ((N + 1) / 2) * 2; + end + endfunction + + localparam Y_WIDTH2 = round_up2(Y_WIDTH); + + (* force_downto *) + wire [Y_WIDTH2-1:0] AA = A_buf; + (* force_downto *) + wire [Y_WIDTH2-1:0] BB = BI ? ~B_buf : B_buf; + (* force_downto *) + wire [Y_WIDTH2-1:0] BX = B_buf; + (* force_downto *) + wire [Y_WIDTH2-1:0] C = {CO, CI}; + (* force_downto *) + wire [Y_WIDTH2-1:0] FCO, Y1; + + genvar i; + generate for (i = 0; i < Y_WIDTH2; i = i + 2) begin:slice + CCU2D #( + .INIT0(16'b0101_1010_1001_0110), + .INIT1(16'b0101_1010_1001_0110), + .INJECT1_0("NO"), + .INJECT1_1("NO") + ) ccu2d_i ( + .CIN(C[i]), + .A0(AA[i]), .B0(BX[i]), .C0(BI), .D0(1'b0), + .A1(AA[i+1]), .B1(BX[i+1]), .C1(BI), .D1(1'b0), + .S0(Y[i]), .S1(Y1[i]), + .COUT(FCO[i]) + ); + + assign CO[i] = (AA[i] && BB[i]) || (C[i] && (AA[i] || BB[i])); + if (i+1 < Y_WIDTH) begin + assign CO[i+1] = FCO[i]; + assign Y[i+1] = Y1[i]; + end + end endgenerate + + assign X = AA ^ BB; +endmodule diff --git a/yosys/techlibs/machxo2/brams_map.v b/yosys/techlibs/machxo2/brams_map.v index 05a8e8a9b09..6783e5b2902 100644 --- a/yosys/techlibs/machxo2/brams_map.v +++ b/yosys/techlibs/machxo2/brams_map.v @@ -45,38 +45,38 @@ assign PORT_A_RD_DATA = DOA; assign PORT_B_RD_DATA = DOB; DP8KC #( - .INITVAL_00($sformatf("0x%080x", init_slice('h00))), - .INITVAL_01($sformatf("0x%080x", init_slice('h01))), - .INITVAL_02($sformatf("0x%080x", init_slice('h02))), - .INITVAL_03($sformatf("0x%080x", init_slice('h03))), - .INITVAL_04($sformatf("0x%080x", init_slice('h04))), - .INITVAL_05($sformatf("0x%080x", init_slice('h05))), - .INITVAL_06($sformatf("0x%080x", init_slice('h06))), - .INITVAL_07($sformatf("0x%080x", init_slice('h07))), - .INITVAL_08($sformatf("0x%080x", init_slice('h08))), - .INITVAL_09($sformatf("0x%080x", init_slice('h09))), - .INITVAL_0A($sformatf("0x%080x", init_slice('h0a))), - .INITVAL_0B($sformatf("0x%080x", init_slice('h0b))), - .INITVAL_0C($sformatf("0x%080x", init_slice('h0c))), - .INITVAL_0D($sformatf("0x%080x", init_slice('h0d))), - .INITVAL_0E($sformatf("0x%080x", init_slice('h0e))), - .INITVAL_0F($sformatf("0x%080x", init_slice('h0f))), - .INITVAL_10($sformatf("0x%080x", init_slice('h10))), - .INITVAL_11($sformatf("0x%080x", init_slice('h11))), - .INITVAL_12($sformatf("0x%080x", init_slice('h12))), - .INITVAL_13($sformatf("0x%080x", init_slice('h13))), - .INITVAL_14($sformatf("0x%080x", init_slice('h14))), - .INITVAL_15($sformatf("0x%080x", init_slice('h15))), - .INITVAL_16($sformatf("0x%080x", init_slice('h16))), - .INITVAL_17($sformatf("0x%080x", init_slice('h17))), - .INITVAL_18($sformatf("0x%080x", init_slice('h18))), - .INITVAL_19($sformatf("0x%080x", init_slice('h19))), - .INITVAL_1A($sformatf("0x%080x", init_slice('h1a))), - .INITVAL_1B($sformatf("0x%080x", init_slice('h1b))), - .INITVAL_1C($sformatf("0x%080x", init_slice('h1c))), - .INITVAL_1D($sformatf("0x%080x", init_slice('h1d))), - .INITVAL_1E($sformatf("0x%080x", init_slice('h1e))), - .INITVAL_1F($sformatf("0x%080x", init_slice('h1f))), + .INITVAL_00(init_slice('h00)), + .INITVAL_01(init_slice('h01)), + .INITVAL_02(init_slice('h02)), + .INITVAL_03(init_slice('h03)), + .INITVAL_04(init_slice('h04)), + .INITVAL_05(init_slice('h05)), + .INITVAL_06(init_slice('h06)), + .INITVAL_07(init_slice('h07)), + .INITVAL_08(init_slice('h08)), + .INITVAL_09(init_slice('h09)), + .INITVAL_0A(init_slice('h0a)), + .INITVAL_0B(init_slice('h0b)), + .INITVAL_0C(init_slice('h0c)), + .INITVAL_0D(init_slice('h0d)), + .INITVAL_0E(init_slice('h0e)), + .INITVAL_0F(init_slice('h0f)), + .INITVAL_10(init_slice('h10)), + .INITVAL_11(init_slice('h11)), + .INITVAL_12(init_slice('h12)), + .INITVAL_13(init_slice('h13)), + .INITVAL_14(init_slice('h14)), + .INITVAL_15(init_slice('h15)), + .INITVAL_16(init_slice('h16)), + .INITVAL_17(init_slice('h17)), + .INITVAL_18(init_slice('h18)), + .INITVAL_19(init_slice('h19)), + .INITVAL_1A(init_slice('h1a)), + .INITVAL_1B(init_slice('h1b)), + .INITVAL_1C(init_slice('h1c)), + .INITVAL_1D(init_slice('h1d)), + .INITVAL_1E(init_slice('h1e)), + .INITVAL_1F(init_slice('h1f)), .DATA_WIDTH_A(PORT_A_WIDTH), .DATA_WIDTH_B(PORT_B_WIDTH), .REGMODE_A("NOREG"), @@ -211,38 +211,38 @@ wire [17:0] DO; assign PORT_R_RD_DATA = PORT_R_WIDTH == 18 ? DO : DO[17:9]; DP8KC #( - .INITVAL_00($sformatf("0x%080x", init_slice('h00))), - .INITVAL_01($sformatf("0x%080x", init_slice('h01))), - .INITVAL_02($sformatf("0x%080x", init_slice('h02))), - .INITVAL_03($sformatf("0x%080x", init_slice('h03))), - .INITVAL_04($sformatf("0x%080x", init_slice('h04))), - .INITVAL_05($sformatf("0x%080x", init_slice('h05))), - .INITVAL_06($sformatf("0x%080x", init_slice('h06))), - .INITVAL_07($sformatf("0x%080x", init_slice('h07))), - .INITVAL_08($sformatf("0x%080x", init_slice('h08))), - .INITVAL_09($sformatf("0x%080x", init_slice('h09))), - .INITVAL_0A($sformatf("0x%080x", init_slice('h0a))), - .INITVAL_0B($sformatf("0x%080x", init_slice('h0b))), - .INITVAL_0C($sformatf("0x%080x", init_slice('h0c))), - .INITVAL_0D($sformatf("0x%080x", init_slice('h0d))), - .INITVAL_0E($sformatf("0x%080x", init_slice('h0e))), - .INITVAL_0F($sformatf("0x%080x", init_slice('h0f))), - .INITVAL_10($sformatf("0x%080x", init_slice('h10))), - .INITVAL_11($sformatf("0x%080x", init_slice('h11))), - .INITVAL_12($sformatf("0x%080x", init_slice('h12))), - .INITVAL_13($sformatf("0x%080x", init_slice('h13))), - .INITVAL_14($sformatf("0x%080x", init_slice('h14))), - .INITVAL_15($sformatf("0x%080x", init_slice('h15))), - .INITVAL_16($sformatf("0x%080x", init_slice('h16))), - .INITVAL_17($sformatf("0x%080x", init_slice('h17))), - .INITVAL_18($sformatf("0x%080x", init_slice('h18))), - .INITVAL_19($sformatf("0x%080x", init_slice('h19))), - .INITVAL_1A($sformatf("0x%080x", init_slice('h1a))), - .INITVAL_1B($sformatf("0x%080x", init_slice('h1b))), - .INITVAL_1C($sformatf("0x%080x", init_slice('h1c))), - .INITVAL_1D($sformatf("0x%080x", init_slice('h1d))), - .INITVAL_1E($sformatf("0x%080x", init_slice('h1e))), - .INITVAL_1F($sformatf("0x%080x", init_slice('h1f))), + .INITVAL_00(init_slice('h00)), + .INITVAL_01(init_slice('h01)), + .INITVAL_02(init_slice('h02)), + .INITVAL_03(init_slice('h03)), + .INITVAL_04(init_slice('h04)), + .INITVAL_05(init_slice('h05)), + .INITVAL_06(init_slice('h06)), + .INITVAL_07(init_slice('h07)), + .INITVAL_08(init_slice('h08)), + .INITVAL_09(init_slice('h09)), + .INITVAL_0A(init_slice('h0a)), + .INITVAL_0B(init_slice('h0b)), + .INITVAL_0C(init_slice('h0c)), + .INITVAL_0D(init_slice('h0d)), + .INITVAL_0E(init_slice('h0e)), + .INITVAL_0F(init_slice('h0f)), + .INITVAL_10(init_slice('h10)), + .INITVAL_11(init_slice('h11)), + .INITVAL_12(init_slice('h12)), + .INITVAL_13(init_slice('h13)), + .INITVAL_14(init_slice('h14)), + .INITVAL_15(init_slice('h15)), + .INITVAL_16(init_slice('h16)), + .INITVAL_17(init_slice('h17)), + .INITVAL_18(init_slice('h18)), + .INITVAL_19(init_slice('h19)), + .INITVAL_1A(init_slice('h1a)), + .INITVAL_1B(init_slice('h1b)), + .INITVAL_1C(init_slice('h1c)), + .INITVAL_1D(init_slice('h1d)), + .INITVAL_1E(init_slice('h1e)), + .INITVAL_1F(init_slice('h1f)), .DATA_WIDTH_A(PORT_W_WIDTH), .DATA_WIDTH_B(PORT_R_WIDTH), .REGMODE_A("NOREG"), diff --git a/yosys/techlibs/machxo2/cells_bb.v b/yosys/techlibs/machxo2/cells_bb.v new file mode 100644 index 00000000000..3d047b1692a --- /dev/null +++ b/yosys/techlibs/machxo2/cells_bb.v @@ -0,0 +1,227 @@ +(* blackbox *) +module EHXPLLJ ( + input CLKI, CLKFB, + input PHASESEL1, PHASESEL0, PHASEDIR, PHASESTEP, + input LOADREG, STDBY, PLLWAKESYNC, RST, RESETM, RESETC, RESETD, + input ENCLKOP, ENCLKOS, ENCLKOS2, ENCLKOS3, PLLCLK, PLLRST, PLLSTB, PLLWE, + input PLLDATI7, PLLDATI6, PLLDATI5, PLLDATI4, PLLDATI3, PLLDATI2, PLLDATI1, PLLDATI0, + input PLLADDR4, PLLADDR3, PLLADDR2, PLLADDR1, PLLADDR0, + output CLKOP, CLKOS, CLKOS2, CLKOS3, LOCK, INTLOCK, REFCLK, + output PLLDATO7, PLLDATO6, PLLDATO5, PLLDATO4, PLLDATO3, PLLDATO2, PLLDATO1, PLLDATO0, PLLACK, + output DPHSRC, CLKINTFB +); + parameter CLKI_DIV = 1; + parameter CLKFB_DIV = 1; + parameter CLKOP_DIV = 8; + parameter CLKOS_DIV = 8; + parameter CLKOS2_DIV = 8; + parameter CLKOS3_DIV = 8; + parameter CLKOP_ENABLE = "ENABLED"; + parameter CLKOS_ENABLE = "ENABLED"; + parameter CLKOS2_ENABLE = "ENABLED"; + parameter CLKOS3_ENABLE = "ENABLED"; + parameter VCO_BYPASS_A0 = "DISABLED"; + parameter VCO_BYPASS_B0 = "DISABLED"; + parameter VCO_BYPASS_C0 = "DISABLED"; + parameter VCO_BYPASS_D0 = "DISABLED"; + parameter CLKOP_CPHASE = 0; + parameter CLKOS_CPHASE = 0; + parameter CLKOS2_CPHASE = 0; + parameter CLKOS3_CPHASE = 0; + parameter CLKOP_FPHASE = 0; + parameter CLKOS_FPHASE = 0; + parameter CLKOS2_FPHASE = 0; + parameter CLKOS3_FPHASE = 0; + parameter FEEDBK_PATH = "CLKOP"; + parameter FRACN_ENABLE = "DISABLED"; + parameter FRACN_DIV = 0; + parameter CLKOP_TRIM_POL = "RISING"; + parameter CLKOP_TRIM_DELAY = 0; + parameter CLKOS_TRIM_POL = "RISING"; + parameter CLKOS_TRIM_DELAY = 0; + parameter PLL_USE_WB = "DISABLED"; + parameter PREDIVIDER_MUXA1 = 0; + parameter PREDIVIDER_MUXB1 = 0; + parameter PREDIVIDER_MUXC1 = 0; + parameter PREDIVIDER_MUXD1 = 0; + parameter OUTDIVIDER_MUXA2 = "DIVA"; + parameter OUTDIVIDER_MUXB2 = "DIVB"; + parameter OUTDIVIDER_MUXC2 = "DIVC"; + parameter OUTDIVIDER_MUXD2 = "DIVD"; + parameter PLL_LOCK_MODE = 0; + parameter STDBY_ENABLE = "DISABLED"; + parameter DPHASE_SOURCE = "DISABLED"; + parameter PLLRST_ENA = "DISABLED"; + parameter MRST_ENA = "DISABLED"; + parameter DCRST_ENA = "DISABLED"; + parameter DDRST_ENA = "DISABLED"; + parameter INTFB_WAKE = "DISABLED"; +endmodule + +(* blackbox *) +module OSCH #( + parameter NOM_FREQ = "2.08" +) ( + input STDBY, + output OSC, + output SEDSTDBY +); +endmodule + +(* blackbox *) +module DCCA ( + input CLKI, + input CE, + output CLKO +); +endmodule + +(* blackbox *) +module DCMA ( + input CLK0, + input CLK1, + input SEL, + output DCMOUT +); +endmodule + +(* blackbox *) +module PDPW8KC ( + input DI17, DI16, DI15, DI14, DI13, DI12, DI11, DI10, DI9, DI8, DI7, DI6, DI5, DI4, DI3, DI2, DI1, DI0, + input ADW8, ADW7, ADW6, ADW5, ADW4, ADW3, ADW2, ADW1, ADW0, + input BE1, BE0, + input CEW, CLKW, CSW2, CSW1, CSW0, + input ADR12, ADR11, ADR10, ADR9, ADR8, ADR7, ADR6, ADR5, ADR4, ADR3, ADR2, ADR1, ADR0, + input CER, OCER, CLKR, CSR2, CSR1, CSR0, RST, + output DO17, DO16, DO15, DO14, DO13, DO12, DO11, DO10, DO9, DO8, DO7, DO6, DO5, DO4, DO3, DO2, DO1, DO0 +); + parameter DATA_WIDTH_W = 18; + parameter DATA_WIDTH_R = 9; + + parameter GSR = "ENABLED"; + + parameter REGMODE = "NOREG"; + + parameter RESETMODE = "SYNC"; + parameter ASYNC_RESET_RELEASE = "SYNC"; + + parameter CSDECODE_W = "0b000"; + parameter CSDECODE_R = "0b000"; + + parameter INITVAL_00 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_01 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_02 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_03 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_04 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_05 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_06 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_07 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_08 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_09 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_10 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_11 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_12 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_13 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_14 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_15 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_16 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_17 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_18 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_19 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_DATA = "STATIC"; + +endmodule + +(* blackbox *) +module SP8KC ( + input DI8, DI7, DI6, DI5, DI4, DI3, DI2, DI1, DI0, + input AD12, AD11, AD10, AD9, AD8, AD7, AD6, AD5, AD4, AD3, AD2, AD1, AD0, + input CE, OCE, CLK, WE, CS2, CS1, CS0, RST, + output DO8, DO7, DO6, DO5, DO4, DO3, DO2, DO1, DO0 +); + parameter DATA_WIDTH = 9; + parameter GSR = "ENABLED"; + + parameter REGMODE = "NOREG"; + + parameter RESETMODE = "SYNC"; + parameter ASYNC_RESET_RELEASE = "SYNC"; + + parameter CSDECODE = "0b000"; + + parameter WRITEMODE = "NORMAL"; + + parameter INITVAL_00 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_01 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_02 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_03 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_04 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_05 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_06 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_07 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_08 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_09 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_10 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_11 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_12 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_13 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_14 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_15 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_16 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_17 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_18 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_19 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_DATA = "STATIC"; +endmodule + +(* blackbox *) +module FIFO8KB ( + input DI0, DI1, DI2, DI3, DI4, DI5, DI6, DI7, DI8, DI9, DI10, DI11, DI12, DI13, DI14, DI15, DI16, DI17, + input CSW0, CSW1, CSR0, CSR1, WE, RE, ORE, CLKW, CLKR, RST, RPRST, FULLI, EMPTYI, + output DO0, DO1, DO2, DO3, DO4, DO5, DO6, DO7, DO8, DO9, DO10, DO11, DO12, DO13, DO14, DO15, DO16, DO17, + input EF, AEF, AFF, FF +); + parameter DATA_WIDTH_W = 18; + parameter DATA_WIDTH_R = 18; + + parameter GSR = "DISABLED"; + + parameter REGMODE = "NOREG"; + + parameter RESETMODE = "ASYNC"; + parameter ASYNC_RESET_RELEASE = "SYNC"; + + parameter CSDECODE_W = "0b00"; + parameter CSDECODE_R = "0b00"; + + parameter AEPOINTER = "0b00000000000000"; + parameter AEPOINTER1 = "0b00000000000000"; + parameter AFPOINTER = "0b00000000000000"; + parameter AFPOINTER1 = "0b00000000000000"; + parameter FULLPOINTER = "0b00000000000000"; + parameter FULLPOINTER1 = "0b00000000000000"; +endmodule diff --git a/yosys/techlibs/machxo2/cells_map.v b/yosys/techlibs/machxo2/cells_map.v index 9c370f246aa..22994a634df 100644 --- a/yosys/techlibs/machxo2/cells_map.v +++ b/yosys/techlibs/machxo2/cells_map.v @@ -1,3 +1,93 @@ +module \$_DFF_N_ (input D, C, output Q); + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + generate if (_TECHMAP_WIREINIT_Q_ === 1'b1) + TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(1'b0), .DI(D), .Q(Q)); + else + TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(1'b0), .DI(D), .Q(Q)); + endgenerate + wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; +endmodule + +module \$_DFF_P_ (input D, C, output Q); + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + generate if (_TECHMAP_WIREINIT_Q_ === 1'b1) + TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(1'b0), .DI(D), .Q(Q)); + else + TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(1'b0), .DI(D), .Q(Q)); + endgenerate + wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; +endmodule + +module \$_DFFE_NN_ (input D, C, E, output Q); + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + generate if (_TECHMAP_WIREINIT_Q_ === 1'b1) + TRELLIS_FF #(.GSR("AUTO"), .CEMUX("INV"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(1'b0), .DI(D), .Q(Q)); + else + TRELLIS_FF #(.GSR("AUTO"), .CEMUX("INV"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(1'b0), .DI(D), .Q(Q)); + endgenerate + wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; +endmodule + +module \$_DFFE_PN_ (input D, C, E, output Q); + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + generate if (_TECHMAP_WIREINIT_Q_ === 1'b1) + TRELLIS_FF #(.GSR("AUTO"), .CEMUX("INV"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(1'b0), .DI(D), .Q(Q)); + else + TRELLIS_FF #(.GSR("AUTO"), .CEMUX("INV"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(1'b0), .DI(D), .Q(Q)); + endgenerate + wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; +endmodule + +module \$_DFFE_NP_ (input D, C, E, output Q); + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + generate if (_TECHMAP_WIREINIT_Q_ === 1'b1) + TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(1'b0), .DI(D), .Q(Q)); + else + TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(1'b0), .DI(D), .Q(Q)); + endgenerate + wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; +endmodule + +module \$_DFFE_PP_ (input D, C, E, output Q); + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + generate if (_TECHMAP_WIREINIT_Q_ === 1'b1) + TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(1'b0), .DI(D), .Q(Q)); + else + TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(1'b0), .DI(D), .Q(Q)); + endgenerate + wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; +endmodule + +module \$_DFF_NP0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule +module \$_DFF_NP1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule +module \$_DFF_PP0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule +module \$_DFF_PP1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule + +module \$_SDFF_NP0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule +module \$_SDFF_NP1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule +module \$_SDFF_PP0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule +module \$_SDFF_PP1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule + +module \$_DFFE_NP0P_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule +module \$_DFFE_NP1P_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule +module \$_DFFE_PP0P_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule +module \$_DFFE_PP1P_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule + +module \$_DFFE_NP0N_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("INV"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule +module \$_DFFE_NP1N_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("INV"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule +module \$_DFFE_PP0N_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("INV"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule +module \$_DFFE_PP1N_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("INV"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule + +module \$_SDFFE_NP0P_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule +module \$_SDFFE_NP1P_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule +module \$_SDFFE_PP0P_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule +module \$_SDFFE_PP1P_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule + +module \$_SDFFE_NP0N_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("INV"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule +module \$_SDFFE_NP1N_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("INV"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule +module \$_SDFFE_PP0N_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("INV"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule +module \$_SDFFE_PP1N_ (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("AUTO"), .CEMUX("INV"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); wire _TECHMAP_REMOVEINIT_Q_ = 1'b1; endmodule + module \$lut (A, Y); parameter WIDTH = 0; parameter LUT = 0; @@ -24,11 +114,4 @@ module \$lut (A, Y); LUT4 #(.INIT({rep{LUT}})) _TECHMAP_REPLACE_ (.A(I[0]), .B(I[1]), .C(I[2]), .D(I[3]), .Z(Y)); endmodule -// DFFs -module \$_DFF_P_ (input D, C, output Q); FACADE_FF #(.CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(1'b0), .DI(D), .Q(Q)); endmodule - -// IO- "$__" cells for the iopadmap pass. -module \$__FACADE_OUTPAD (input I, output O); FACADE_IO #(.DIR("OUTPUT")) _TECHMAP_REPLACE_ (.PAD(O), .I(I), .T(1'b0)); endmodule -module \$__FACADE_INPAD (input I, output O); FACADE_IO #(.DIR("INPUT")) _TECHMAP_REPLACE_ (.PAD(I), .O(O)); endmodule -module \$__FACADE_TOUTPAD (input I, T, output O); FACADE_IO #(.DIR("OUTPUT")) _TECHMAP_REPLACE_ (.PAD(O), .I(I), .T(T)); endmodule -module \$__FACADE_TINOUTPAD (input I, T, output O, inout B); FACADE_IO #(.DIR("BIDIR")) _TECHMAP_REPLACE_ (.PAD(B), .I(I), .O(O), .T(T)); endmodule +`include "cells_io.vh" diff --git a/yosys/techlibs/machxo2/cells_sim.v b/yosys/techlibs/machxo2/cells_sim.v index 82c9d8c4b83..8e0e411791c 100644 --- a/yosys/techlibs/machxo2/cells_sim.v +++ b/yosys/techlibs/machxo2/cells_sim.v @@ -1,3 +1,9 @@ +module LUT2(input A, B, output Z); + parameter [3:0] INIT = 4'h0; + wire [1:0] s1 = B ? INIT[ 3:2] : INIT[1:0]; + assign Z = A ? s1[1] : s1[0]; +endmodule + module LUT4 #( parameter [15:0] INIT = 0 ) ( @@ -11,7 +17,7 @@ module LUT4 #( assign Z = A ? s1[1] : s1[0]; endmodule -module FACADE_FF #( +module TRELLIS_FF #( parameter GSR = "ENABLED", parameter CEMUX = "1", parameter CLKMUX = "0", @@ -77,7 +83,7 @@ endmodule /* For consistency, input order matches TRELLIS_SLICE even though the BELs in prjtrellis were filled in clockwise order from bottom left. */ -module FACADE_SLICE #( +module TRELLIS_SLICE #( parameter MODE = "LOGIC", parameter GSR = "ENABLED", parameter SRMODE = "LSR_OVER_CE", @@ -139,64 +145,82 @@ module FACADE_SLICE #( endgenerate /* Reg can be fed either by M, or DI inputs; DI inputs muxes OFX and F - outputs (in other words, feeds back into FACADE_SLICE). */ + outputs (in other words, feeds back into TRELLIS_SLICE). */ wire di0 = (REG0_SD == "1") ? DI0 : M0; wire di1 = (REG1_SD == "1") ? DI1 : M1; - FACADE_FF#(.GSR(GSR), .CEMUX(CEMUX), .CLKMUX(CLKMUX), .LSRMUX(LSRMUX), + TRELLIS_FF#(.GSR(GSR), .CEMUX(CEMUX), .CLKMUX(CLKMUX), .LSRMUX(LSRMUX), .LSRONMUX(LSRONMUX), .SRMODE(SRMODE), .REGSET(REG0_REGSET), .REGMODE(REGMODE)) REG_0 (.CLK(CLK), .DI(di0), .LSR(LSR), .CE(CE), .Q(Q0)); - FACADE_FF#(.GSR(GSR), .CEMUX(CEMUX), .CLKMUX(CLKMUX), .LSRMUX(LSRMUX), + TRELLIS_FF#(.GSR(GSR), .CEMUX(CEMUX), .CLKMUX(CLKMUX), .LSRMUX(LSRMUX), .LSRONMUX(LSRONMUX), .SRMODE(SRMODE), .REGSET(REG1_REGSET), .REGMODE(REGMODE)) REG_1 (.CLK(CLK), .DI(di1), .LSR(LSR), .CE(CE), .Q(Q1)); endmodule -module FACADE_IO #( +module TRELLIS_IO #( parameter DIR = "INPUT" ) ( - inout PAD, + (* iopad_external_pin *) + inout B, input I, T, output O ); generate if (DIR == "INPUT") begin - assign O = PAD; + assign O = B; end else if (DIR == "OUTPUT") begin - assign PAD = T ? 1'bz : I; + assign B = T ? 1'bz : I; end else if (DIR == "BIDIR") begin - assign PAD = T ? 1'bz : I; - assign O = PAD; + assign B = T ? 1'bz : I; + assign O = B; end else begin ERROR_UNKNOWN_IO_MODE error(); end endgenerate endmodule -(* blackbox *) -module OSCH #( - parameter NOM_FREQ = "2.08" -) ( - input STDBY, - output OSC, - output SEDSTDBY +(* abc9_box, lib_whitebox *) +module TRELLIS_DPR16X4 ( + input [3:0] DI, + input [3:0] WAD, + input WRE, + input WCK, + input [3:0] RAD, + output [3:0] DO ); -endmodule + parameter WCKMUX = "WCK"; + parameter WREMUX = "WRE"; + parameter [63:0] INITVAL = 64'h0000000000000000; -(* blackbox *) -module DCCA ( - input CLKI, - input CE, - output CLKO -); -endmodule + reg [3:0] mem[15:0]; -(* blackbox *) -module DCMA ( - input CLK0, - input CLK1, - input SEL, - output DCMOUT -); + integer i; + initial begin + for (i = 0; i < 16; i = i + 1) + mem[i] <= INITVAL[4*i +: 4]; + end + + wire muxwck = (WCKMUX == "INV") ? ~WCK : WCK; + + reg muxwre; + always @(*) + case (WREMUX) + "1": muxwre = 1'b1; + "0": muxwre = 1'b0; + "INV": muxwre = ~WRE; + default: muxwre = WRE; + endcase + + always @(posedge muxwck) + if (muxwre) + mem[WAD] <= DI; + + assign DO = mem[RAD]; + + specify + // TODO + (RAD *> DO) = 0; + endspecify endmodule (* abc9_box, lib_whitebox *) @@ -254,6 +278,40 @@ module DPR16X4C ( assign DO = ram[RAD]; endmodule +// --------------------------------------- +(* lib_whitebox *) +module CCU2D ( + input CIN, + input A0, B0, C0, D0, A1, B1, C1, D1, + output S0, S1, + output COUT +); + parameter [15:0] INIT0 = 16'h0000; + parameter [15:0] INIT1 = 16'h0000; + parameter INJECT1_0 = "YES"; + parameter INJECT1_1 = "YES"; + + // First half + wire LUT4_0, LUT2_0; + LUT4 #(.INIT(INIT0)) lut4_0(.A(A0), .B(B0), .C(C0), .D(D0), .Z(LUT4_0)); + LUT2 #(.INIT(~INIT0[15:12])) lut2_0(.A(A0), .B(B0), .Z(LUT2_0)); + wire gated_cin_0 = (INJECT1_0 == "YES") ? 1'b0 : CIN; + assign S0 = LUT4_0 ^ gated_cin_0; + + wire gated_lut2_0 = (INJECT1_0 == "YES") ? 1'b0 : LUT2_0; + wire cout_0 = (~LUT4_0 & gated_lut2_0) | (LUT4_0 & CIN); + + // Second half + wire LUT4_1, LUT2_1; + LUT4 #(.INIT(INIT1)) lut4_1(.A(A1), .B(B1), .C(C1), .D(D1), .Z(LUT4_1)); + LUT2 #(.INIT(~INIT1[15:12])) lut2_1(.A(A1), .B(B1), .Z(LUT2_1)); + wire gated_cin_1 = (INJECT1_1 == "YES") ? 1'b0 : cout_0; + assign S1 = LUT4_1 ^ gated_cin_1; + + wire gated_lut2_1 = (INJECT1_1 == "YES") ? 1'b0 : LUT2_1; + assign COUT = (~LUT4_1 & gated_lut2_1) | (LUT4_1 & cout_0); +endmodule + (* blackbox *) module DP8KC( input DIA8, DIA7, DIA6, DIA5, DIA4, DIA3, DIA2, DIA1, DIA0, @@ -286,48 +344,42 @@ module DP8KC( parameter GSR = "ENABLED"; parameter INIT_DATA = "STATIC"; - parameter INITVAL_00 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - parameter INITVAL_01 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - parameter INITVAL_02 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - parameter INITVAL_03 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - parameter INITVAL_04 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - parameter INITVAL_05 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - parameter INITVAL_06 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - parameter INITVAL_07 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - parameter INITVAL_08 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - parameter INITVAL_09 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - parameter INITVAL_0A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - parameter INITVAL_0B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - parameter INITVAL_0C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - parameter INITVAL_0D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - parameter INITVAL_0E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - parameter INITVAL_0F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - parameter INITVAL_10 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - parameter INITVAL_11 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - parameter INITVAL_12 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - parameter INITVAL_13 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - parameter INITVAL_14 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - parameter INITVAL_15 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - parameter INITVAL_16 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - parameter INITVAL_17 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - parameter INITVAL_18 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - parameter INITVAL_19 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - parameter INITVAL_1A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - parameter INITVAL_1B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - parameter INITVAL_1C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - parameter INITVAL_1D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - parameter INITVAL_1E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; - parameter INITVAL_1F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; + parameter INITVAL_00 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_01 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_02 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_03 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_04 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_05 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_06 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_07 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_08 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_09 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_0F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_10 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_11 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_12 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_13 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_14 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_15 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_16 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_17 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_18 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_19 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter INITVAL_1F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000; endmodule -// IO- "$__" cells for the iopadmap pass. These are temporary cells not meant -// to be instantiated by the end user. They are required in this file for -// attrmvcp to work. -(* blackbox *) -module \$__FACADE_OUTPAD (input I, output O); endmodule -(* blackbox *) -module \$__FACADE_INPAD (input I, output O); endmodule -(* blackbox *) -module \$__FACADE_TOUTPAD (input I, T, output O); endmodule -(* blackbox *) -module \$__FACADE_TINOUTPAD (input I, T, output O, inout B); endmodule +`ifndef NO_INCLUDES + +`include "cells_io.vh" + +`endif diff --git a/yosys/techlibs/machxo2/synth_machxo2.cc b/yosys/techlibs/machxo2/synth_machxo2.cc index dbd01bbfd4d..2b684a7d8fd 100644 --- a/yosys/techlibs/machxo2/synth_machxo2.cc +++ b/yosys/techlibs/machxo2/synth_machxo2.cc @@ -69,6 +69,9 @@ struct SynthMachXO2Pass : public ScriptPass log(" -noiopad\n"); log(" do not insert IO buffers\n"); log("\n"); + log(" -ccu2\n"); + log(" use CCU2 cells in output netlist\n"); + log("\n"); log(" -vpr\n"); log(" generate an output netlist (and BLIF file) suitable for VPR\n"); log(" (this feature is experimental and incomplete)\n"); @@ -80,7 +83,7 @@ struct SynthMachXO2Pass : public ScriptPass } string top_opt, blif_file, edif_file, json_file; - bool nobram, nolutram, flatten, vpr, noiopad; + bool ccu2, nobram, nolutram, flatten, vpr, noiopad; void clear_flags() override { @@ -88,6 +91,7 @@ struct SynthMachXO2Pass : public ScriptPass blif_file = ""; edif_file = ""; json_file = ""; + ccu2 = false; nobram = false; nolutram = false; flatten = true; @@ -147,6 +151,10 @@ struct SynthMachXO2Pass : public ScriptPass noiopad = true; continue; } + if (args[argidx] == "-ccu2") { + ccu2 = true; + continue; + } if (args[argidx] == "-vpr") { vpr = true; continue; @@ -170,7 +178,7 @@ struct SynthMachXO2Pass : public ScriptPass { if (check_label("begin")) { - run("read_verilog -lib -icells +/machxo2/cells_sim.v"); + run("read_verilog -lib -icells +/machxo2/cells_sim.v +/machxo2/cells_bb.v"); run(stringf("hierarchy -check %s", help_mode ? "-top " : top_opt.c_str())); } @@ -204,25 +212,36 @@ struct SynthMachXO2Pass : public ScriptPass if (check_label("fine")) { + run("opt -fast -mux_undef -undriven -fine"); run("memory_map"); - run("opt -full"); - run("techmap -map +/techmap.v"); - run("opt -fast"); + run("opt -undriven -fine"); } - if (check_label("map_ios", "(unless -noiopad)")) + if (check_label("map_gates", "(unless -noiopad)")) { + if (!ccu2) + run("techmap"); + else + run("techmap -map +/techmap.v -map +/machxo2/arith_map.v"); if (!noiopad || help_mode) { - run("iopadmap -bits -outpad $__FACADE_OUTPAD I:O -inpad $__FACADE_INPAD O:I -toutpad $__FACADE_TOUTPAD ~T:I:O -tinoutpad $__FACADE_TINOUTPAD ~T:O:I:B A:top"); - run("attrmvcp -attr src -attr LOC t:$__FACADE_OUTPAD %x:+[O] t:$__FACADE_TOUTPAD %x:+[O] t:$__FACADE_TINOUTPAD %x:+[B]"); - run("attrmvcp -attr src -attr LOC -driven t:$__FACADE_INPAD %x:+[I]"); + run("iopadmap -bits -outpad OB I:O -inpad IB O:I -toutpad OBZ ~T:I:O -tinoutpad BB ~T:O:I:B A:top", "(only if '-iopad')"); + run("attrmvcp -attr src -attr LOC t:OB %x:+[O] t:OBZ %x:+[O] t:BB %x:+[B]"); + run("attrmvcp -attr src -attr LOC -driven t:IB %x:+[I]"); } } if (check_label("map_ffs")) { - run("dfflegalize -cell $_DFF_P_ 0"); + run("opt_clean"); + std::string dfflegalize_args = " -cell $_DFF_?_ 01 -cell $_DFF_?P?_ r -cell $_SDFF_?P?_ r"; + run("dfflegalize" + dfflegalize_args); + run("techmap -D NO_LUT -map +/machxo2/cells_map.v"); + run("opt_expr -undriven -mux_undef"); + run("simplemap"); + run("ecp5_gsr"); + run("attrmvcp -copy -attr syn_useioff"); + run("opt_clean"); } if (check_label("map_luts")) diff --git a/yosys/techlibs/xilinx/cells_sim.v b/yosys/techlibs/xilinx/cells_sim.v index ee5a89e2272..8b0c913aa6b 100644 --- a/yosys/techlibs/xilinx/cells_sim.v +++ b/yosys/techlibs/xilinx/cells_sim.v @@ -33,8 +33,12 @@ module IBUF( output O, (* iopad_external_pin *) input I); - parameter IOSTANDARD = "default"; - parameter IBUF_LOW_PWR = 0; + parameter CCIO_EN = "TRUE"; + parameter CAPACITANCE = "DONT_CARE"; + parameter IBUF_DELAY_VALUE = "0"; + parameter IBUF_LOW_PWR = "TRUE"; + parameter IFD_DELAY_VALUE = "AUTO"; + parameter IOSTANDARD = "DEFAULT"; assign O = I; specify (I => O) = 0; @@ -56,7 +60,8 @@ module OBUF( (* iopad_external_pin *) output O, input I); - parameter IOSTANDARD = "default"; + parameter CAPACITANCE = "DONT_CARE"; + parameter IOSTANDARD = "DEFAULT"; parameter DRIVE = 12; parameter SLEW = "SLOW"; assign O = I; @@ -3614,7 +3619,7 @@ module DSP48E1 ( if (CREG == 1) begin always @(posedge CLK) if (RSTC) Cr <= 48'b0; else if (CEC) Cr <= C; end else always @* Cr <= C; - if (CREG == 1) initial Dr = 25'b0; + if (DREG == 1) initial Dr = 25'b0; if (DREG == 1) begin always @(posedge CLK) if (RSTD) Dr <= 25'b0; else if (CED) Dr <= D; end else always @* Dr <= D; diff --git a/yosys/techlibs/xilinx/cells_xtra.py b/yosys/techlibs/xilinx/cells_xtra.py index 2630c7a0f64..08fe6f35e38 100644 --- a/yosys/techlibs/xilinx/cells_xtra.py +++ b/yosys/techlibs/xilinx/cells_xtra.py @@ -706,7 +706,7 @@ def xtract_cell_decl(cell, dirs, outf): if __name__ == '__main__': parser = ArgumentParser(description='Extract Xilinx blackbox cell definitions from ISE and Vivado.') - parser.add_argument('vivado_dir', nargs='?', default='/opt/Xilinx/Vivado/2018.1') + parser.add_argument('vivado_dir', nargs='?', default='/opt/Xilinx/Vivado/2022.2') parser.add_argument('ise_dir', nargs='?', default='/opt/Xilinx/ISE/14.7') args = parser.parse_args() diff --git a/yosys/techlibs/xilinx/cells_xtra.v b/yosys/techlibs/xilinx/cells_xtra.v index aae0d3ee5d4..8dc74b16ea2 100644 --- a/yosys/techlibs/xilinx/cells_xtra.v +++ b/yosys/techlibs/xilinx/cells_xtra.v @@ -7550,10 +7550,12 @@ module IBUF_ANALOG (...); endmodule module IBUFE3 (...); + parameter CCIO_EN = "TRUE"; parameter IBUF_LOW_PWR = "TRUE"; parameter IOSTANDARD = "DEFAULT"; - parameter USE_IBUFDISABLE = "FALSE"; + parameter SIM_DEVICE = "ULTRASCALE"; parameter integer SIM_INPUT_BUFFER_OFFSET = 0; + parameter USE_IBUFDISABLE = "FALSE"; output O; (* iopad_external_pin *) input I; @@ -7760,8 +7762,9 @@ module IOBUFE3 (...); parameter integer DRIVE = 12; parameter IBUF_LOW_PWR = "TRUE"; parameter IOSTANDARD = "DEFAULT"; - parameter USE_IBUFDISABLE = "FALSE"; + parameter SIM_DEVICE = "ULTRASCALE"; parameter integer SIM_INPUT_BUFFER_OFFSET = 0; + parameter USE_IBUFDISABLE = "FALSE"; output O; (* iopad_external_pin *) inout IO; @@ -19721,6 +19724,7 @@ module HSADC (...); endmodule module RFDAC (...); + parameter integer LD_DEVICE = 0; parameter integer OPT_CLK_DIST = 0; parameter SIM_DEVICE = "ULTRASCALE_PLUS"; parameter integer XPA_ACTIVE_DUTYCYCLE = 100; @@ -19784,6 +19788,7 @@ module RFDAC (...); endmodule module RFADC (...); + parameter integer LD_DEVICE = 0; parameter integer OPT_ANALOG = 0; parameter integer OPT_CLK_DIST = 0; parameter SIM_DEVICE = "ULTRASCALE_PLUS"; diff --git a/yosys/tests/arch/anlogic/mux.ys b/yosys/tests/arch/anlogic/mux.ys index 3d5fe7c9a61..89014b5e057 100644 --- a/yosys/tests/arch/anlogic/mux.ys +++ b/yosys/tests/arch/anlogic/mux.ys @@ -26,10 +26,12 @@ proc equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux8 # Constrain all select calls below inside the top module -select -assert-count 3 t:AL_MAP_LUT4 -select -assert-count 1 t:AL_MAP_LUT6 +select -assert-max 3 t:AL_MAP_LUT3 +select -assert-max 3 t:AL_MAP_LUT4 +select -assert-max 1 t:AL_MAP_LUT5 +select -assert-max 1 t:AL_MAP_LUT6 -select -assert-none t:AL_MAP_LUT4 t:AL_MAP_LUT6 %% t:* %D +select -assert-none t:AL_MAP_LUT3 t:AL_MAP_LUT4 t:AL_MAP_LUT5 t:AL_MAP_LUT6 %% t:* %D design -load read hierarchy -top mux16 diff --git a/yosys/tests/arch/common/blockram.v b/yosys/tests/arch/common/blockram.v index 5ed0736d01b..c06ac96d5bc 100644 --- a/yosys/tests/arch/common/blockram.v +++ b/yosys/tests/arch/common/blockram.v @@ -22,7 +22,6 @@ module sync_ram_sp #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=10) endmodule // sync_ram_sp -`default_nettype none module sync_ram_sdp #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=10) (input wire clk, write_enable, input wire [DATA_WIDTH-1:0] data_in, @@ -45,3 +44,33 @@ module sync_ram_sdp #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=10) endmodule // sync_ram_sdp + +module sync_ram_tdp #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=10) + (input wire clk_a, clk_b, + input wire write_enable_a, write_enable_b, + input wire read_enable_a, read_enable_b, + input wire [DATA_WIDTH-1:0] write_data_a, write_data_b, + input wire [ADDRESS_WIDTH-1:0] addr_a, addr_b, + output reg [DATA_WIDTH-1:0] read_data_a, read_data_b); + + localparam WORD = (DATA_WIDTH-1); + localparam DEPTH = (2**ADDRESS_WIDTH-1); + + reg [WORD:0] mem [0:DEPTH]; + + always @(posedge clk_a) begin + if (write_enable_a) + mem[addr_a] <= write_data_a; + else + read_data_a <= mem[addr_a]; + end + + always @(posedge clk_b) begin + if (write_enable_b) + mem[addr_b] <= write_data_b; + else + read_data_b <= mem[addr_b]; + end + +endmodule // sync_ram_tdp + diff --git a/yosys/tests/arch/ecp5/bug1836.mem b/yosys/tests/arch/ecp5/bug1836.mem new file mode 100644 index 00000000000..1e904d87cf6 --- /dev/null +++ b/yosys/tests/arch/ecp5/bug1836.mem @@ -0,0 +1,32 @@ +0x8000,0x8324,0x8647,0x896a,0x8c8b,0x8fab,0x92c7,0x95e1, +0x98f8,0x9c0b,0x9f19,0xa223,0xa527,0xa826,0xab1f,0xae10, +0xb0fb,0xb3de,0xb6b9,0xb98c,0xbc56,0xbf17,0xc1cd,0xc47a, +0xc71c,0xc9b3,0xcc3f,0xcebf,0xd133,0xd39a,0xd5f5,0xd842, +0xda82,0xdcb3,0xded7,0xe0eb,0xe2f1,0xe4e8,0xe6cf,0xe8a6, +0xea6d,0xec23,0xedc9,0xef5e,0xf0e2,0xf254,0xf3b5,0xf504, +0xf641,0xf76b,0xf884,0xf989,0xfa7c,0xfb5c,0xfc29,0xfce3, +0xfd89,0xfe1d,0xfe9c,0xff09,0xff61,0xffa6,0xffd8,0xfff5, +0xffff,0xfff5,0xffd8,0xffa6,0xff61,0xff09,0xfe9c,0xfe1d, +0xfd89,0xfce3,0xfc29,0xfb5c,0xfa7c,0xf989,0xf884,0xf76b, +0xf641,0xf504,0xf3b5,0xf254,0xf0e2,0xef5e,0xedc9,0xec23, +0xea6d,0xe8a6,0xe6cf,0xe4e8,0xe2f1,0xe0eb,0xded7,0xdcb3, +0xda82,0xd842,0xd5f5,0xd39a,0xd133,0xcebf,0xcc3f,0xc9b3, +0xc71c,0xc47a,0xc1cd,0xbf17,0xbc56,0xb98c,0xb6b9,0xb3de, +0xb0fb,0xae10,0xab1f,0xa826,0xa527,0xa223,0x9f19,0x9c0b, +0x98f8,0x95e1,0x92c7,0x8fab,0x8c8b,0x896a,0x8647,0x8324, +0x8000,0x7cdb,0x79b8,0x7695,0x7374,0x7054,0x6d38,0x6a1e, +0x6707,0x63f4,0x60e6,0x5ddc,0x5ad8,0x57d9,0x54e0,0x51ef, +0x4f04,0x4c21,0x4946,0x4673,0x43a9,0x40e8,0x3e32,0x3b85, +0x38e3,0x364c,0x33c0,0x3140,0x2ecc,0x2c65,0x2a0a,0x27bd, +0x257d,0x234c,0x2128,0x1f14,0x1d0e,0x1b17,0x1930,0x1759, +0x1592,0x13dc,0x1236,0x10a1,0xf1d,0xdab,0xc4a,0xafb, +0x9be,0x894,0x77b,0x676,0x583,0x4a3,0x3d6,0x31c, +0x276,0x1e2,0x163,0xf6,0x9e,0x59,0x27,0xa, +0x0,0xa,0x27,0x59,0x9e,0xf6,0x163,0x1e2, +0x276,0x31c,0x3d6,0x4a3,0x583,0x676,0x77b,0x894, +0x9be,0xafb,0xc4a,0xdab,0xf1d,0x10a1,0x1236,0x13dc, +0x1592,0x1759,0x1930,0x1b17,0x1d0e,0x1f14,0x2128,0x234c, +0x257d,0x27bd,0x2a0a,0x2c65,0x2ecc,0x3140,0x33c0,0x364c, +0x38e3,0x3b85,0x3e32,0x40e8,0x43a9,0x4673,0x4946,0x4c21, +0x4f04,0x51ef,0x54e0,0x57d9,0x5ad8,0x5ddc,0x60e6,0x63f4, +0x6707,0x6a1e,0x6d38,0x7054,0x7374,0x7695,0x79b8,0x7cdb, \ No newline at end of file diff --git a/yosys/tests/arch/ecp5/bug1836.ys b/yosys/tests/arch/ecp5/bug1836.ys new file mode 100644 index 00000000000..15cdf422868 --- /dev/null +++ b/yosys/tests/arch/ecp5/bug1836.ys @@ -0,0 +1,23 @@ +read_verilog < DP16KD + +design -reset; read_verilog -defer ../common/blockram.v +chparam -set ADDRESS_WIDTH 9 -set DATA_WIDTH 18 sync_ram_tdp +hierarchy -top sync_ram_tdp +synth_ecp5 -top sync_ram_tdp; cd sync_ram_tdp +select -assert-count 1 t:DP16KD +select -assert-none t:LUT4 diff --git a/yosys/tests/arch/ecp5/mux.ys b/yosys/tests/arch/ecp5/mux.ys index db63dda5f94..daa9e86f269 100644 --- a/yosys/tests/arch/ecp5/mux.ys +++ b/yosys/tests/arch/ecp5/mux.ys @@ -28,8 +28,8 @@ equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux8 # Constrain all select calls below inside the top module select -assert-max 1 t:L6MUX21 -select -assert-max 7 t:LUT4 -select -assert-max 2 t:PFUMX +select -assert-max 8 t:LUT4 +select -assert-max 3 t:PFUMX select -assert-none t:LUT4 t:L6MUX21 t:PFUMX %% t:* %D diff --git a/yosys/tests/arch/fabulous/carry.ys b/yosys/tests/arch/fabulous/carry.ys new file mode 100644 index 00000000000..bba969d37d1 --- /dev/null +++ b/yosys/tests/arch/fabulous/carry.ys @@ -0,0 +1,9 @@ +read_verilog ../common/add_sub.v +hierarchy -top top +proc +equiv_opt -assert -map +/fabulous/prims.v synth_fabulous -carry ha # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-max 10 t:LUT4_HA +select -assert-max 4 t:LUT1 +select -assert-none t:LUT1 t:LUT4_HA %% t:* %D diff --git a/yosys/tests/arch/gatemate/fsm.ys b/yosys/tests/arch/gatemate/fsm.ys index 6b43ead7ac7..506862c908e 100644 --- a/yosys/tests/arch/gatemate/fsm.ys +++ b/yosys/tests/arch/gatemate/fsm.ys @@ -15,6 +15,6 @@ cd fsm # Constrain all select calls below inside the top module select -assert-count 1 t:CC_BUFG select -assert-count 6 t:CC_DFF select -assert-max 5 t:CC_LUT2 -select -assert-max 4 t:CC_LUT3 +select -assert-max 6 t:CC_LUT3 select -assert-max 9 t:CC_LUT4 select -assert-none t:CC_BUFG t:CC_DFF t:CC_LUT2 t:CC_LUT3 t:CC_LUT4 %% t:* %D diff --git a/yosys/tests/arch/gatemate/memory.ys b/yosys/tests/arch/gatemate/memory.ys index e919920f893..c4bf11cd357 100644 --- a/yosys/tests/arch/gatemate/memory.ys +++ b/yosys/tests/arch/gatemate/memory.ys @@ -6,6 +6,14 @@ cd sync_ram_sdp select -assert-count 1 t:CC_BUFG select -assert-count 1 t:CC_BRAM_20K +# 512 x 20 bit x 2 -> CC_BRAM_20K TDP RAM +design -reset +read_verilog ../common/blockram.v +chparam -set ADDRESS_WIDTH 9 -set DATA_WIDTH 20 sync_ram_tdp +synth_gatemate -top sync_ram_tdp -noiopad +select -assert-count 2 t:CC_BUFG +select -assert-count 1 t:CC_BRAM_20K + # 512 x 80 bit -> CC_BRAM_40K SDP RAM design -reset read_verilog ../common/blockram.v diff --git a/yosys/tests/arch/gowin/compare.v b/yosys/tests/arch/gowin/compare.v new file mode 100644 index 00000000000..0ed3c2fa4f9 --- /dev/null +++ b/yosys/tests/arch/gowin/compare.v @@ -0,0 +1,20 @@ +module top +( + input [4:0] x, + input [4:0] y, + + output lt, + output le, + output gt, + output ge, + output eq, + output ne +); + + assign lt = x < y; + assign le = x <= y; + assign gt = x > y; + assign ge = x >= y; + assign eq = x == y; + assign ne = x != y; +endmodule diff --git a/yosys/tests/arch/gowin/compare.ys b/yosys/tests/arch/gowin/compare.ys new file mode 100644 index 00000000000..a3aba6dea90 --- /dev/null +++ b/yosys/tests/arch/gowin/compare.ys @@ -0,0 +1,9 @@ +read_verilog compare.v +hierarchy -top top +proc +equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 5 t:ALU + + diff --git a/yosys/tests/arch/ice40/rom.ys b/yosys/tests/arch/ice40/rom.ys index 41d214e2a91..d795e206b4a 100644 --- a/yosys/tests/arch/ice40/rom.ys +++ b/yosys/tests/arch/ice40/rom.ys @@ -4,5 +4,5 @@ flatten equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module -select -assert-count 5 t:SB_LUT4 +select -assert-max 6 t:SB_LUT4 select -assert-none t:SB_LUT4 %% t:* %D diff --git a/yosys/tests/arch/ice40/spram.v b/yosys/tests/arch/ice40/spram.v new file mode 100644 index 00000000000..4e1aef2c601 --- /dev/null +++ b/yosys/tests/arch/ice40/spram.v @@ -0,0 +1,22 @@ +module top (clk, write_enable, read_enable, write_data, addr, read_data); +parameter DATA_WIDTH = 8; +parameter ADDR_WIDTH = 8; +parameter SKIP_RDEN = 1; + +input clk; +input write_enable, read_enable; +input [DATA_WIDTH - 1 : 0] write_data; +input [ADDR_WIDTH - 1 : 0] addr; +output [DATA_WIDTH - 1 : 0] read_data; + +(* ram_style = "huge" *) +reg [DATA_WIDTH - 1 : 0] mem [2**ADDR_WIDTH - 1 : 0]; + +always @(posedge clk) begin + if (write_enable) + mem[addr] <= write_data; + else if (SKIP_RDEN || read_enable) + read_data <= mem[addr]; +end + +endmodule diff --git a/yosys/tests/arch/ice40/spram.ys b/yosys/tests/arch/ice40/spram.ys new file mode 100644 index 00000000000..709c218621e --- /dev/null +++ b/yosys/tests/arch/ice40/spram.ys @@ -0,0 +1,15 @@ +read_verilog spram.v +hierarchy -top top +synth_ice40 +select -assert-count 1 t:SB_SPRAM256KA +select -assert-none t:SB_SPRAM256KA %% t:* %D + +# Testing with pattern as described in pattern document +design -reset +read_verilog spram.v +chparam -set SKIP_RDEN 0 +hierarchy -top top +synth_ice40 +select -assert-count 1 t:SB_SPRAM256KA +# Below fails due to extra SB_LUT4 +# select -assert-none t:SB_SPRAM256KA %% t:* %D diff --git a/yosys/tests/arch/intel_alm/blockram.ys b/yosys/tests/arch/intel_alm/blockram.ys index 3b61b93390c..21b5ecbfb60 100644 --- a/yosys/tests/arch/intel_alm/blockram.ys +++ b/yosys/tests/arch/intel_alm/blockram.ys @@ -1,6 +1,6 @@ read_verilog ../common/blockram.v chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 10 sync_ram_sdp -synth_intel_alm -family cyclonev -noiopad -noclkbuf +synth_intel_alm -top sync_ram_sdp -family cyclonev -noiopad -noclkbuf cd sync_ram_sdp select -assert-count 1 t:MISTRAL_NOT select -assert-count 1 t:MISTRAL_M10K diff --git a/yosys/tests/arch/intel_alm/counter.ys b/yosys/tests/arch/intel_alm/counter.ys index 0a5b9356ab7..2b428fb3e51 100644 --- a/yosys/tests/arch/intel_alm/counter.ys +++ b/yosys/tests/arch/intel_alm/counter.ys @@ -6,7 +6,7 @@ equiv_opt -assert -async2sync -map +/intel_alm/common/alm_sim.v -map +/intel_alm design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module -select -assert-count 1 t:MISTRAL_NOT +select -assert-count 2 t:MISTRAL_NOT select -assert-count 8 t:MISTRAL_ALUT_ARITH select -assert-count 8 t:MISTRAL_FF select -assert-none t:MISTRAL_NOT t:MISTRAL_ALUT_ARITH t:MISTRAL_FF %% t:* %D @@ -21,7 +21,7 @@ equiv_opt -assert -async2sync -map +/intel_alm/common/alm_sim.v -map +/intel_alm design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module -select -assert-count 1 t:MISTRAL_NOT +select -assert-count 2 t:MISTRAL_NOT select -assert-count 8 t:MISTRAL_ALUT_ARITH select -assert-count 8 t:MISTRAL_FF select -assert-none t:MISTRAL_NOT t:MISTRAL_ALUT_ARITH t:MISTRAL_FF %% t:* %D diff --git a/yosys/tests/arch/intel_alm/mux.ys b/yosys/tests/arch/intel_alm/mux.ys index 6fb6ae80a42..20969ead35f 100644 --- a/yosys/tests/arch/intel_alm/mux.ys +++ b/yosys/tests/arch/intel_alm/mux.ys @@ -69,7 +69,7 @@ proc equiv_opt -assert -map +/intel_alm/common/alm_sim.v synth_intel_alm -family cyclonev -noiopad -noclkbuf # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux16 # Constrain all select calls below inside the top module -select -assert-count 1 t:MISTRAL_ALUT3 +select -assert-max 1 t:MISTRAL_ALUT3 select -assert-max 2 t:MISTRAL_ALUT5 select -assert-max 5 t:MISTRAL_ALUT6 select -assert-none t:MISTRAL_ALUT3 t:MISTRAL_ALUT5 t:MISTRAL_ALUT6 %% t:* %D @@ -81,8 +81,8 @@ proc equiv_opt -assert -map +/intel_alm/common/alm_sim.v synth_intel_alm -family cyclone10gx -noiopad -noclkbuf # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux16 # Constrain all select calls below inside the top module -select -assert-count 1 t:MISTRAL_ALUT3 -select -assert-count 2 t:MISTRAL_ALUT5 -select -assert-count 4 t:MISTRAL_ALUT6 +select -assert-max 1 t:MISTRAL_ALUT3 +select -assert-max 2 t:MISTRAL_ALUT5 +select -assert-max 5 t:MISTRAL_ALUT6 select -assert-none t:MISTRAL_ALUT3 t:MISTRAL_ALUT5 t:MISTRAL_ALUT6 %% t:* %D diff --git a/yosys/tests/arch/machxo2/add_sub.ys b/yosys/tests/arch/machxo2/add_sub.ys index d9497b8182b..97ee90fbbe2 100644 --- a/yosys/tests/arch/machxo2/add_sub.ys +++ b/yosys/tests/arch/machxo2/add_sub.ys @@ -5,4 +5,4 @@ equiv_opt -assert -map +/machxo2/cells_sim.v synth_machxo2 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module select -assert-count 10 t:LUT4 -select -assert-none t:LUT4 t:FACADE_IO %% t:* %D +select -assert-none t:LUT4 t:TRELLIS_IO %% t:* %D diff --git a/yosys/tests/arch/machxo2/adffs.ys b/yosys/tests/arch/machxo2/adffs.ys new file mode 100644 index 00000000000..a9f8980c6e4 --- /dev/null +++ b/yosys/tests/arch/machxo2/adffs.ys @@ -0,0 +1,40 @@ +read_verilog ../common/adffs.v +design -save read + +hierarchy -top adff +proc +equiv_opt -async2sync -assert -map +/machxo2/cells_sim.v synth_machxo2 -noiopad # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd adff # Constrain all select calls below inside the top module +select -assert-count 1 t:TRELLIS_FF +select -assert-none t:TRELLIS_FF %% t:* %D + +design -load read +hierarchy -top adffn +proc +equiv_opt -async2sync -assert -map +/machxo2/cells_sim.v synth_machxo2 -noiopad # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd adffn # Constrain all select calls below inside the top module +select -assert-count 1 t:TRELLIS_FF +select -assert-count 1 t:LUT4 +select -assert-none t:TRELLIS_FF t:LUT4 %% t:* %D + +design -load read +hierarchy -top dffs +proc +equiv_opt -async2sync -assert -map +/machxo2/cells_sim.v synth_machxo2 -noiopad # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd dffs # Constrain all select calls below inside the top module +select -assert-count 1 t:TRELLIS_FF +select -assert-count 1 t:LUT4 +select -assert-none t:TRELLIS_FF t:LUT4 %% t:* %D + +design -load read +hierarchy -top ndffnr +proc +equiv_opt -async2sync -assert -map +/machxo2/cells_sim.v synth_machxo2 -noiopad # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd ndffnr # Constrain all select calls below inside the top module +select -assert-count 1 t:TRELLIS_FF +select -assert-count 1 t:LUT4 +select -assert-none t:TRELLIS_FF t:LUT4 %% t:* %D diff --git a/yosys/tests/arch/machxo2/counter.ys b/yosys/tests/arch/machxo2/counter.ys new file mode 100644 index 00000000000..54ee80066ff --- /dev/null +++ b/yosys/tests/arch/machxo2/counter.ys @@ -0,0 +1,10 @@ +read_verilog ../common/counter.v +hierarchy -top top +proc +flatten +equiv_opt -assert -multiclock -map +/machxo2/cells_sim.v synth_machxo2 -ccu2 -noiopad # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 4 t:CCU2D +select -assert-count 8 t:TRELLIS_FF +select -assert-none t:CCU2D t:TRELLIS_FF %% t:* %D diff --git a/yosys/tests/arch/machxo2/dffs.ys b/yosys/tests/arch/machxo2/dffs.ys index 83a79a9d6b3..29dcafe2383 100644 --- a/yosys/tests/arch/machxo2/dffs.ys +++ b/yosys/tests/arch/machxo2/dffs.ys @@ -6,8 +6,8 @@ proc equiv_opt -assert -map +/machxo2/cells_sim.v synth_machxo2 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd dff # Constrain all select calls below inside the top module -select -assert-count 1 t:FACADE_FF -select -assert-none t:FACADE_FF t:FACADE_IO %% t:* %D +select -assert-count 1 t:TRELLIS_FF +select -assert-none t:TRELLIS_FF t:TRELLIS_IO %% t:* %D design -load read hierarchy -top dffe @@ -15,5 +15,5 @@ proc equiv_opt -assert -map +/machxo2/cells_sim.v synth_machxo2 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd dffe # Constrain all select calls below inside the top module -select -assert-count 2 t:FACADE_FF t:LUT4 -select -assert-none t:FACADE_FF t:LUT4 t:FACADE_IO %% t:* %D +select -assert-count 2 t:TRELLIS_FF t:LUT4 +select -assert-none t:TRELLIS_FF t:LUT4 t:TRELLIS_IO %% t:* %D diff --git a/yosys/tests/arch/machxo2/fsm.ys b/yosys/tests/arch/machxo2/fsm.ys index 847a61161b0..a61357fcdd2 100644 --- a/yosys/tests/arch/machxo2/fsm.ys +++ b/yosys/tests/arch/machxo2/fsm.ys @@ -11,5 +11,5 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p cd fsm # Constrain all select calls below inside the top module select -assert-max 16 t:LUT4 -select -assert-count 6 t:FACADE_FF -select -assert-none t:FACADE_FF t:LUT4 t:FACADE_IO %% t:* %D +select -assert-count 6 t:TRELLIS_FF +select -assert-none t:TRELLIS_FF t:LUT4 t:TRELLIS_IO %% t:* %D diff --git a/yosys/tests/arch/machxo2/logic.ys b/yosys/tests/arch/machxo2/logic.ys index bf93ab128ae..0cf57310c81 100644 --- a/yosys/tests/arch/machxo2/logic.ys +++ b/yosys/tests/arch/machxo2/logic.ys @@ -5,4 +5,4 @@ equiv_opt -assert -map +/machxo2/cells_sim.v synth_machxo2 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module select -assert-count 9 t:LUT4 -select -assert-none t:LUT4 t:FACADE_IO %% t:* %D +select -assert-none t:LUT4 t:TRELLIS_IO %% t:* %D diff --git a/yosys/tests/arch/machxo2/lutram.ys b/yosys/tests/arch/machxo2/lutram.ys new file mode 100644 index 00000000000..dc6b86fd349 --- /dev/null +++ b/yosys/tests/arch/machxo2/lutram.ys @@ -0,0 +1,17 @@ +read_verilog ../common/lutram.v +hierarchy -top lutram_1w1r +proc +memory -nomap +equiv_opt -run :prove -map +/machxo2/cells_sim.v synth_machxo2 -noiopad +memory +opt -full + +miter -equiv -flatten -make_assert -make_outputs gold gate miter +sat -verify -prove-asserts -seq 5 -set-init-zero -show-inputs -show-outputs miter + +design -load postopt +cd lutram_1w1r +select -assert-count 20 t:LUT4 +select -assert-count 8 t:TRELLIS_DPR16X4 +select -assert-count 8 t:TRELLIS_FF +select -assert-none t:LUT4 t:TRELLIS_DPR16X4 t:TRELLIS_FF %% t:* %D diff --git a/yosys/tests/arch/machxo2/mux.ys b/yosys/tests/arch/machxo2/mux.ys index 7b7e62d4caa..27bffbe63aa 100644 --- a/yosys/tests/arch/machxo2/mux.ys +++ b/yosys/tests/arch/machxo2/mux.ys @@ -7,7 +7,7 @@ equiv_opt -assert -map +/machxo2/cells_sim.v synth_machxo2 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux2 # Constrain all select calls below inside the top module select -assert-count 1 t:LUT4 -select -assert-none t:LUT4 t:FACADE_IO %% t:* %D +select -assert-none t:LUT4 t:TRELLIS_IO %% t:* %D design -load read hierarchy -top mux4 @@ -17,7 +17,7 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p cd mux4 # Constrain all select calls below inside the top module select -assert-count 2 t:LUT4 -select -assert-none t:LUT4 t:FACADE_IO %% t:* %D +select -assert-none t:LUT4 t:TRELLIS_IO %% t:* %D design -load read hierarchy -top mux8 @@ -27,7 +27,7 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p cd mux8 # Constrain all select calls below inside the top module select -assert-count 5 t:LUT4 -select -assert-none t:LUT4 t:FACADE_IO %% t:* %D +select -assert-none t:LUT4 t:TRELLIS_IO %% t:* %D design -load read hierarchy -top mux16 @@ -37,4 +37,4 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p cd mux16 # Constrain all select calls below inside the top module select -assert-max 12 t:LUT4 -select -assert-none t:LUT4 t:FACADE_IO %% t:* %D +select -assert-none t:LUT4 t:TRELLIS_IO %% t:* %D diff --git a/yosys/tests/arch/machxo2/shifter.ys b/yosys/tests/arch/machxo2/shifter.ys index 87fdab0fa36..bff881fb734 100644 --- a/yosys/tests/arch/machxo2/shifter.ys +++ b/yosys/tests/arch/machxo2/shifter.ys @@ -6,5 +6,5 @@ equiv_opt -assert -map +/machxo2/cells_sim.v synth_machxo2 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module -select -assert-count 8 t:FACADE_FF -select -assert-none t:FACADE_FF t:FACADE_IO %% t:* %D +select -assert-count 8 t:TRELLIS_FF +select -assert-none t:TRELLIS_FF t:TRELLIS_IO %% t:* %D diff --git a/yosys/tests/arch/machxo2/tribuf.ys b/yosys/tests/arch/machxo2/tribuf.ys index fce342e183f..840979439f8 100644 --- a/yosys/tests/arch/machxo2/tribuf.ys +++ b/yosys/tests/arch/machxo2/tribuf.ys @@ -5,6 +5,6 @@ flatten equiv_opt -assert -map +/machxo2/cells_sim.v synth_machxo2 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd tristate # Constrain all select calls below inside the top module -select -assert-count 3 t:FACADE_IO +select -assert-count 3 t:TRELLIS_IO select -assert-count 1 t:LUT4 -select -assert-none t:FACADE_IO t:LUT4 %% t:* %D +select -assert-none t:TRELLIS_IO t:LUT4 %% t:* %D diff --git a/yosys/tests/arch/nexus/mux.ys b/yosys/tests/arch/nexus/mux.ys index 0e12d674a7c..280d3e48f95 100644 --- a/yosys/tests/arch/nexus/mux.ys +++ b/yosys/tests/arch/nexus/mux.ys @@ -36,8 +36,7 @@ proc equiv_opt -assert -map +/nexus/cells_sim.v synth_nexus # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux16 # Constrain all select calls below inside the top module -select -assert-min 11 t:LUT4 select -assert-max 12 t:LUT4 -select -assert-count 1 t:WIDEFN9 +select -assert-max 2 t:WIDEFN9 select -assert-none t:IB t:OB t:VLO t:VHI t:LUT4 t:WIDEFN9 %% t:* %D diff --git a/yosys/tests/arch/xilinx/asym_ram_sdp.ys b/yosys/tests/arch/xilinx/asym_ram_sdp.ys new file mode 100644 index 00000000000..37f6f314d39 --- /dev/null +++ b/yosys/tests/arch/xilinx/asym_ram_sdp.ys @@ -0,0 +1,50 @@ +# Memory bits <= 18K; Data width <= 36; Address width <= 14: -> RAMB18E1 + +# w4b | r16b +design -reset +read_verilog asym_ram_sdp_read_wider.v +synth_xilinx -top asym_ram_sdp_read_wider -noiopad +select -assert-count 1 t:RAMB18E1 + +# w8b | r16b +design -reset +read_verilog asym_ram_sdp_read_wider.v +chparam -set WIDTHA 8 -set SIZEA 512 -set ADDRWIDTHA 9 asym_ram_sdp_read_wider +synth_xilinx -top asym_ram_sdp_read_wider -noiopad +select -assert-count 1 t:RAMB18E1 + +# w4b | r32b +design -reset +read_verilog asym_ram_sdp_read_wider.v +chparam -set WIDTHB 32 -set SIZEB 128 -set ADDRWIDTHB 7 asym_ram_sdp_read_wider +synth_xilinx -top asym_ram_sdp_read_wider -noiopad +select -assert-count 1 t:RAMB18E1 + +# w16b | r4b +design -reset +read_verilog asym_ram_sdp_write_wider.v +synth_xilinx -top asym_ram_sdp_write_wider -noiopad +select -assert-count 1 t:RAMB18E1 + +# w16b | r8b +design -reset +read_verilog asym_ram_sdp_write_wider.v +chparam -set WIDTHB 8 -set SIZEB 512 -set ADDRWIDTHB 9 asym_ram_sdp_read_wider +synth_xilinx -top asym_ram_sdp_write_wider -noiopad +select -assert-count 1 t:RAMB18E1 + +# w32b | r4b +design -reset +read_verilog asym_ram_sdp_write_wider.v +chparam -set WIDTHA 32 -set SIZEA 128 -set ADDRWIDTHA 7 asym_ram_sdp_read_wider +synth_xilinx -top asym_ram_sdp_write_wider -noiopad +select -assert-count 1 t:RAMB18E1 + +# w4b | r24b +design -reset +read_verilog asym_ram_sdp_read_wider.v +chparam -set SIZEA 768 +chparam -set WIDTHB 24 -set SIZEB 128 -set ADDRWIDTHB 7 asym_ram_sdp_read_wider +synth_xilinx -top asym_ram_sdp_read_wider -noiopad +select -assert-count 1 t:RAMB18E1 + diff --git a/yosys/tests/arch/xilinx/asym_ram_sdp_read_wider.v b/yosys/tests/arch/xilinx/asym_ram_sdp_read_wider.v new file mode 100644 index 00000000000..8743209e313 --- /dev/null +++ b/yosys/tests/arch/xilinx/asym_ram_sdp_read_wider.v @@ -0,0 +1,72 @@ +// Asymmetric port RAM +// Read Wider than Write. Read Statement in loop +//asym_ram_sdp_read_wider.v +module asym_ram_sdp_read_wider (clkA, clkB, enaA, weA, enaB, addrA, addrB, diA, doB); + parameter WIDTHA = 4; + parameter SIZEA = 1024; + parameter ADDRWIDTHA = 10; + + parameter WIDTHB = 16; + parameter SIZEB = 256; + parameter ADDRWIDTHB = 8; + + input clkA; + input clkB; + input weA; + input enaA, enaB; + input [ADDRWIDTHA-1:0] addrA; + input [ADDRWIDTHB-1:0] addrB; + input [WIDTHA-1:0] diA; + output [WIDTHB-1:0] doB; + + `define max(a,b) {(a) > (b) ? (a) : (b)} + `define min(a,b) {(a) < (b) ? (a) : (b)} + + function integer log2; + input integer value; + reg [31:0] shifted; + integer res; + begin + if (value < 2) + log2 = value; + else + begin + shifted = value-1; + for (res=0; shifted>0; res=res+1) + shifted = shifted>>1; + log2 = res; + end + end + endfunction + + localparam maxSIZE = `max(SIZEA, SIZEB); + localparam maxWIDTH = `max(WIDTHA, WIDTHB); + localparam minWIDTH = `min(WIDTHA, WIDTHB); + + localparam RATIO = maxWIDTH / minWIDTH; + localparam log2RATIO = log2(RATIO); + + reg [minWIDTH-1:0] RAM [0:maxSIZE-1]; + reg [WIDTHB-1:0] readB; + + always @(posedge clkA) + begin + if (enaA) begin + if (weA) + RAM[addrA] <= diA; + end + end + + always @(posedge clkB) + begin : ramread + integer i; + reg [log2RATIO-1:0] lsbaddr; + if (enaB) begin + for (i = 0; i < RATIO; i = i+1) begin + lsbaddr = i; + readB[(i+1)*minWIDTH-1 -: minWIDTH] <= RAM[{addrB, lsbaddr}]; + end + end + end + assign doB = readB; +endmodule \ No newline at end of file diff --git a/yosys/tests/arch/xilinx/asym_ram_sdp_write_wider.v b/yosys/tests/arch/xilinx/asym_ram_sdp_write_wider.v new file mode 100644 index 00000000000..cd61a3ccc75 --- /dev/null +++ b/yosys/tests/arch/xilinx/asym_ram_sdp_write_wider.v @@ -0,0 +1,71 @@ +// Asymmetric port RAM +// Write wider than Read. Write Statement in a loop. +// asym_ram_sdp_write_wider.v +module asym_ram_sdp_write_wider (clkA, clkB, weA, enaA, enaB, addrA, addrB, diA, doB); + parameter WIDTHB = 4; + parameter SIZEB = 1024; + parameter ADDRWIDTHB = 10; + + parameter WIDTHA = 16; + parameter SIZEA = 256; + parameter ADDRWIDTHA = 8; + + input clkA; + input clkB; + input weA; + input enaA, enaB; + input [ADDRWIDTHA-1:0] addrA; + input [ADDRWIDTHB-1:0] addrB; + input [WIDTHA-1:0] diA; + output [WIDTHB-1:0] doB; + + `define max(a,b) {(a) > (b) ? (a) : (b)} + `define min(a,b) {(a) < (b) ? (a) : (b)} + + function integer log2; + input integer value; + reg [31:0] shifted; + integer res; + begin + if (value < 2) + log2 = value; + else + begin + shifted = value-1; + for (res=0; shifted>0; res=res+1) + shifted = shifted>>1; + log2 = res; + end + end + endfunction + + localparam maxSIZE = `max(SIZEA, SIZEB); + localparam maxWIDTH = `max(WIDTHA, WIDTHB); + localparam minWIDTH = `min(WIDTHA, WIDTHB); + + localparam RATIO = maxWIDTH / minWIDTH; + localparam log2RATIO = log2(RATIO); + + reg [minWIDTH-1:0] RAM [0:maxSIZE-1]; + reg [WIDTHB-1:0] readB; + + always @(posedge clkB) begin + if (enaB) begin + readB <= RAM[addrB]; + end + end + assign doB = readB; + + always @(posedge clkA) + begin : ramwrite + integer i; + reg [log2RATIO-1:0] lsbaddr; + for (i=0; i< RATIO; i= i+ 1) begin : write1 + lsbaddr = i; + if (enaA) begin + if (weA) + RAM[{addrA, lsbaddr}] <= diA[(i+1)*minWIDTH-1 -: minWIDTH]; + end + end + end +endmodule \ No newline at end of file diff --git a/yosys/tests/arch/xilinx/bug3670.v b/yosys/tests/arch/xilinx/bug3670.v new file mode 100644 index 00000000000..c7dd1807923 --- /dev/null +++ b/yosys/tests/arch/xilinx/bug3670.v @@ -0,0 +1,13 @@ +module bug3670(input we, output [31:0] o1, o2, output o3); + // Completely missing port connections, where first affected port + // (ADDRARDADDR) has a $setup delay + RAMB36E1 ram1(.DOADO(o1)); + + // Under-specified input port connections (WEA is 4 bits) which + // has a $setup delay + RAMB36E1 ram2(.WEA(we), .DOADO(o2)); + + // Under-specified output port connections (DOADO is 32 bits) + // with clk-to-q delay + RAMB36E1 ram3(.DOADO(o3)); +endmodule diff --git a/yosys/tests/arch/xilinx/bug3670.ys b/yosys/tests/arch/xilinx/bug3670.ys new file mode 100644 index 00000000000..772072c1ee4 --- /dev/null +++ b/yosys/tests/arch/xilinx/bug3670.ys @@ -0,0 +1,3 @@ +read_verilog bug3670.v +read_verilog -lib -specify +/xilinx/cells_sim.v +abc9 diff --git a/yosys/tests/arch/xilinx/dsp_abc9.ys b/yosys/tests/arch/xilinx/dsp_abc9.ys index 909e54149b9..ae4839d7f1f 100644 --- a/yosys/tests/arch/xilinx/dsp_abc9.ys +++ b/yosys/tests/arch/xilinx/dsp_abc9.ys @@ -1,3 +1,5 @@ +logger -nowarn "Yosys has only limited support for tri-state logic at the moment\. .*" + read_verilog < 0) begin + reg [WDBITS-1:0] mem_read; + reg [OFFSET-1:0] subaddr_r; + always @(posedge clk) begin + mem_read <= mem[ra[RABITS-1:OFFSET]]; + subaddr_r <= ra[OFFSET-1:0]; + end + + always @(mem_read, subaddr_r) + rd <= mem_read[subaddr_r*RDBITS+:RDBITS]; +end +else +begin + always @(posedge clk) + case (OFFSET) + 0: rd <= mem[ra]; + -1: rd <= {{ mem[ra], mem[ra+1] }}; + endcase +end +endmodule +""" + +UNMIXED = MIXED_WRITE.format(wabits=4, wdbits=9, rabits=4, rdbits=9) +MIXED_9_18 = MIXED_WRITE.format(wabits=5, wdbits=9, rabits=4, rdbits=18) +MIXED_18_9 = MIXED_WRITE.format(wabits=3, wdbits=18, rabits=4, rdbits=9) +MIXED_36_9 = MIXED_WRITE.format(wabits=3, wdbits=36, rabits=5, rdbits=9) +MIXED_4_2 = MIXED_WRITE.format(wabits=5, wdbits=4, rabits=6, rdbits=2); + +TESTS += [ + Test("unmixed", UNMIXED, ["9b1B"], [], {"RAM_9b1B":1}), + Test("mixed_9_18", MIXED_9_18, ["9b1B"], [], {"RAM_9b1B":4}), #CHECK: only using half the memory + Test("mixed_18_9", MIXED_18_9, ["9b1B"], [], {"RAM_9b1B":1}), + Test("mixed_36_9", MIXED_36_9, ["9b1B"], [], {"RAM_9b1B":2}), + Test("mixed_4_2", MIXED_4_2, ["9b1B"], [], {"RAM_9b1B":1}), +] + ### basic TDP test TDP = """ @@ -131,7 +381,7 @@ def __init__(self, name, src, libs, defs, cells): ] # shared clock - +# Synchronous SDP with clock domain crossing SYNC_2CLK = """ module top(rclk, wclk, ra, wa, rd, wd, we); @@ -163,7 +413,7 @@ def __init__(self, name, src, libs, defs, cells): ] # inter-port transparency - +# Synchronous SDP with write-first behaviour SYNC_TRANS = """ module top(clk, ra, wa, rd, wd, we); @@ -201,7 +451,7 @@ def __init__(self, name, src, libs, defs, cells): ] # rdwr checks - +# Synchronous single-port RAM with mutually exclusive read/write SP_NO_CHANGE = """ module top(clk, addr, rd, wd, we); @@ -247,6 +497,7 @@ def __init__(self, name, src, libs, defs, cells): endmodule """ +# Synchronous single-port RAM with write-first behaviour SP_NEW = """ module top(clk, addr, rd, wd, we); @@ -295,6 +546,7 @@ def __init__(self, name, src, libs, defs, cells): endmodule """ +# Synchronous single-port RAM with read-first behaviour SP_OLD = """ module top(clk, addr, rd, wd, we); @@ -373,6 +625,7 @@ def __init__(self, name, src, libs, defs, cells): Test("sp_old_auto_be", SP_OLD_BE, ["block_sp"], ["RDWR_NO_CHANGE", "RDWR_OLD", "RDWR_NEW"], {"RAM_BLOCK_SP": (1, {"OPTION_RDWR": "OLD"})}), ] +# Synchronous read port with initial value SP_INIT = """ module top(clk, addr, rd, wd, we, re); @@ -418,6 +671,7 @@ def __init__(self, name, src, libs, defs, cells): Test("sp_init_v_any_re", SP_INIT_V, ["block_sp"], ["RDINIT_ANY", "RDEN", "RDWR_OLD"], {"RAM_BLOCK_SP": 1}), ] +# Synchronous read port with asynchronous reset SP_ARST = """ module top(clk, addr, rd, wd, we, re, ar); @@ -488,6 +742,7 @@ def __init__(self, name, src, libs, defs, cells): Test("sp_arst_n_init_re", SP_ARST_N, ["block_sp"], ["RDINIT_ANY", "RDARST_INIT", "RDEN", "RDWR_OLD"], {"RAM_BLOCK_SP": 1}), ] +# Synchronous read port with synchronous reset (reset priority over enable) SP_SRST = """ module top(clk, addr, rd, wd, we, re, sr); @@ -515,6 +770,7 @@ def __init__(self, name, src, libs, defs, cells): endmodule """ +# Synchronous read port with synchronous reet (enable priority over reset) SP_SRST_G = """ module top(clk, addr, rd, wd, we, re, sr); @@ -602,6 +858,180 @@ def __init__(self, name, src, libs, defs, cells): Test("sp_srst_gv_init_re", SP_SRST_GV, ["block_sp"], ["RDINIT_ANY", "RDSRST_INIT", "RDEN", "RDWR_OLD"], {"RAM_BLOCK_SP": 1}), ] +# Byte enables, wrbe_separate +SYNC_ENABLE = """ +module top(clk, rwa, rd, wd, we); + +localparam ABITS = {abits}; +localparam DBITS = {dbits}; + +input wire clk; +input wire we; +input wire [ABITS-1:0] rwa; +input wire [DBITS-1:0] wd; +output reg [DBITS-1:0] rd; + +reg [DBITS-1:0] mem [0:2**ABITS-1]; + +always @(posedge clk) begin + if (we) + mem[rwa] <= wd; + else + rd <= mem[rwa]; +end + +endmodule +""" + +for (abits, dbits, sep, defs, cells) in [ + (4, 4, False, ["NO_BYTE"], {"RAM_WREN": 1}), + (5, 4, False, ["NO_BYTE"], {"RAM_WREN": 2}), + (6, 4, False, ["NO_BYTE"], {"RAM_WREN": 4}), + # (4, 4, True, ["NO_BYTE"], {"RAM_WREN": 1}), # should throw an error + (3, 8, False, ["NO_BYTE"], {"RAM_WREN": 2}), # needs two write ports + (4, 8, False, ["NO_BYTE"], {"RAM_WREN": 2}), + (4, 4, False, ["W4_B4"], {"RAM_WREN": 1}), + (4, 8, True, ["W4_B4"], {"RAM_WREN": 2}), + (4, 8, False, ["W8_B4"], {"RAM_WREN": 1}), + (4, 8, True, ["W8_B4"], {"RAM_WREN": 1}), + (4, 8, False, ["W8_B8"], {"RAM_WREN": 1}), + (4, 8, True, ["W8_B8"], {"RAM_WREN": 1}), + +]: + name = f"wren_a{abits}d{dbits}_{defs[0]}" + if (sep): + defs.append("WRBE_SEPARATE") + name += "_separate" + + TESTS.append(Test( + name, SYNC_ENABLE.format(abits=abits, dbits=dbits), + ["wren"], defs, cells + )) + +# Write port with byte enables +ENABLES = """ +module top(clk, we, be, rwa, wd, rd); + +localparam ABITS = {abits}; +localparam WBITS = {wbits}; +localparam WORDS = {words}; + +input wire clk; +input wire we; +input wire [WORDS-1:0] be; +input wire [ABITS-1:0] rwa; +input wire [(WBITS*WORDS)-1:0] wd; +output reg [(WBITS*WORDS)-1:0] rd; + +reg [(WBITS*WORDS)-1:0] mem [0:2**ABITS-1]; + +integer i; +always @(posedge clk) + for (i=0; i= 0); +endmodule +EOF + +equiv_opt -assert opt_expr -fine diff --git a/yosys/tests/svinterfaces/resolve_types.sv b/yosys/tests/svinterfaces/resolve_types.sv new file mode 100644 index 00000000000..3c6644e334d --- /dev/null +++ b/yosys/tests/svinterfaces/resolve_types.sv @@ -0,0 +1,24 @@ +// This test checks that types, including package types, are resolved from within an interface. + +typedef logic [7:0] x_t; + +package pkg; + typedef logic [7:0] y_t; +endpackage + +interface iface; + x_t x; + pkg::y_t y; +endinterface + +module dut (input logic [7:0] x, output logic [7:0] y); + iface intf(); + assign intf.x = x; + assign y = intf.y; + + ondemand u(.intf); +endmodule + +module ref (input logic [7:0] x, output logic [7:0] y); + assign y = ~x; +endmodule diff --git a/yosys/tests/svinterfaces/resolve_types.ys b/yosys/tests/svinterfaces/resolve_types.ys new file mode 100644 index 00000000000..a25791f3785 --- /dev/null +++ b/yosys/tests/svinterfaces/resolve_types.ys @@ -0,0 +1,6 @@ +read_verilog -sv resolve_types.sv +hierarchy -libdir . -check +flatten +equiv_make ref dut equiv +equiv_simple +equiv_status -assert diff --git a/yosys/tests/svinterfaces/run-test.sh b/yosys/tests/svinterfaces/run-test.sh index 9ef53926c3c..afa222766aa 100755 --- a/yosys/tests/svinterfaces/run-test.sh +++ b/yosys/tests/svinterfaces/run-test.sh @@ -4,3 +4,4 @@ ./runone.sh svinterface_at_top ./run_simple.sh load_and_derive +./run_simple.sh resolve_types diff --git a/yosys/tests/svtypes/struct_array.sv b/yosys/tests/svtypes/struct_array.sv index 739f202ab14..bedc05b6f26 100644 --- a/yosys/tests/svtypes/struct_array.sv +++ b/yosys/tests/svtypes/struct_array.sv @@ -12,12 +12,16 @@ module top; s.a[2:1] = 16'h1234; s.a[5] = 8'h42; + s.a[-1] = '0; s.b = '1; s.b[1:0] = '0; end always_comb assert(s==64'h4200_0012_3400_FFFC); + always_comb assert(s.a[0][3:-4]===8'h0x); + always_comb assert(s.b[23:16]===8'hxx); + always_comb assert(s.b[19:12]===8'hxf); struct packed { bit [7:0] [7:0] a; // 8 element packed array of bytes @@ -141,6 +145,26 @@ module top; always_comb assert(s3_llb==80'hFC00_4200_0012_3400_FFFC); + struct packed { + bit [-10:-3] [-2:-1] [5:2] a; + bit [0:15] b; // filler for non-zero offset + } s3_off; + + initial begin + s3_off = '0; + + s3_off.a[-5:-4] = 16'h1234; + s3_off.a[-8] = 8'h42; + + s3_off.a[-10] = '1; + s3_off.a[-10][-1][3:0] = '0; + + s3_off.b = '1; + s3_off.b[14:15] = '0; + end + + always_comb assert(s3_off==80'hFC00_4200_0012_3400_FFFC); + `ifndef VERIFIC // Note that the tests below for unpacked arrays in structs rely on the // fact that they are actually packed in Yosys. diff --git a/yosys/tests/svtypes/struct_dynamic_range.sv b/yosys/tests/svtypes/struct_dynamic_range.sv new file mode 100644 index 00000000000..12c493d1f14 --- /dev/null +++ b/yosys/tests/svtypes/struct_dynamic_range.sv @@ -0,0 +1,67 @@ +module range_shift_mask( + input logic [2:0] addr_i, + input logic [7:0] data_i, + input logic [2:0] addr_o, + output logic [7:0] data_o +); + (* nowrshmsk = 0 *) + struct packed { + logic [7:0] msb; + logic [0:3][7:0] data; + logic [7:0] lsb; + } s; + + always_comb begin + s = '1; + s.data[addr_i] = data_i; + data_o = s.data[addr_o]; + end +endmodule + +module range_case( + input logic [2:0] addr_i, + input logic [7:0] data_i, + input logic [2:0] addr_o, + output logic [7:0] data_o +); + (* nowrshmsk = 1 *) + struct packed { + logic [7:0] msb; + logic [0:3][7:0] data; + logic [7:0] lsb; + } s; + + always_comb begin + s = '1; + s.data[addr_i] = data_i; + data_o = s.data[addr_o]; + end +endmodule + +module top; + logic [7:0] data_shift_mask1; + range_shift_mask range_shift_mask1(3'd1, 8'h7e, 3'd1, data_shift_mask1); + logic [7:0] data_shift_mask2; + range_shift_mask range_shift_mask2(3'd1, 8'h7e, 3'd2, data_shift_mask2); + logic [7:0] data_shift_mask3; + range_shift_mask range_shift_mask3(3'd1, 8'h7e, 3'd4, data_shift_mask3); + + always_comb begin + assert(data_shift_mask1 === 8'h7e); + assert(data_shift_mask2 === 8'hff); + assert(data_shift_mask3 === 8'hxx); + end + + logic [7:0] data_case1; + range_case range_case1(3'd1, 8'h7e, 3'd1, data_case1); + logic [7:0] data_case2; + range_case range_case2(3'd1, 8'h7e, 3'd2, data_case2); + logic [7:0] data_case3; + range_case range_case3(3'd1, 8'h7e, 3'd4, data_case3); + + always_comb begin + assert(data_case1 === 8'h7e); + assert(data_case2 === 8'hff); + assert(data_case3 === 8'hxx); + end +endmodule diff --git a/yosys/tests/svtypes/struct_dynamic_range.ys b/yosys/tests/svtypes/struct_dynamic_range.ys new file mode 100644 index 00000000000..9606e73840c --- /dev/null +++ b/yosys/tests/svtypes/struct_dynamic_range.ys @@ -0,0 +1,7 @@ +read_verilog -sv struct_dynamic_range.sv +select -assert-count 4 t:$mul +select -assert-count 2 t:$shift +select -assert-count 2 t:$shiftx +prep -top top +flatten +sat -enable_undef -verify -prove-asserts diff --git a/yosys/tests/svtypes/struct_sizebits.sv b/yosys/tests/svtypes/struct_sizebits.sv new file mode 100644 index 00000000000..092d9ecef63 --- /dev/null +++ b/yosys/tests/svtypes/struct_sizebits.sv @@ -0,0 +1,112 @@ +// These tests are adapted from tests/sat/sizebits.sv + +module top; + +typedef struct packed { + logic [2:7][3:0] y; +} sy_t; + +struct packed { + logic t; + logic [5:2] x; + sy_t sy; + union packed { + logic [7:2][2:9][1:4] z; + logic [1:6*8*4] z2; + } sz; +} s; + +//wire [$size(s.x)-1:0]x_size; +//wire [$size({s.x, s.x})-1:0]xx_size; +//wire [$size(s.sy.y)-1:0]y_size; +//wire [$size(s.sz.z)-1:0]z_size; + +//wire [$bits(s.x)-1:0]x_bits; +//wire [$bits({s.x, s.x})-1:0]xx_bits; + +always_comb begin + assert ($size(s) == $size(s.t) + $size(s.x) + $size(s.sy) + $size(s.sz)); + assert ($size(s) == 1 + 4 + 6*4 + 6*8*4); + + assert ($size(s.t) == 1); + assert ($size(s.x) == 4); +`ifndef VERIFIC + assert ($size({3{s.x}}) == 3*4); +`endif + assert ($size(s.sy.y) == 6); + assert ($size(s.sy.y, 1) == 6); + assert ($size(s.sy.y, (1+1)) == 4); + assert ($size(s.sy.y[2], 1) == 4); + // This is unsupported at the moment + // assert ($size(s.sy.y[2][1], 1) == 1); + + assert ($size(s.sz.z) == 6); + assert ($size(s.sz.z, 1) == 6); + assert ($size(s.sz.z, 2) == 8); + assert ($size(s.sz.z, 3) == 4); + assert ($size(s.sz.z[3], 1) == 8); + assert ($size(s.sz.z[3][3], 1) == 4); + // This is unsupported at the moment + // assert ($size(s.sz.z[3][3][3], 1) == 1); + // This should trigger an error if enabled (it does). + // assert ($size(s.sz.z, 4) == 4); + + assert ($bits(s.t) == 1); + assert ($bits(s.x) == 4); + assert ($bits(s.sy.y) == 4*6); + assert ($bits(s.sz.z) == 4*6*8); + + assert ($high(s.x) == 5); + assert ($high(s.sy.y) == 7); + assert ($high(s.sy.y, 1) == 7); + assert ($high(s.sy.y, (1+1)) == 3); + + assert ($high(s.sz.z) == 7); + assert ($high(s.sz.z, 1) == 7); + assert ($high(s.sz.z, 2) == 9); + assert ($high(s.sz.z, 3) == 4); + assert ($high(s.sz.z[3]) == 9); + assert ($high(s.sz.z[3][3]) == 4); + assert ($high(s.sz.z[3], 2) == 4); + + assert ($low(s.x) == 2); + assert ($low(s.sy.y) == 2); + assert ($low(s.sy.y, 1) == 2); + assert ($low(s.sy.y, (1+1)) == 0); + + assert ($low(s.sz.z) == 2); + assert ($low(s.sz.z, 1) == 2); + assert ($low(s.sz.z, 2) == 2); + assert ($low(s.sz.z, 3) == 1); + assert ($low(s.sz.z[3]) == 2); + assert ($low(s.sz.z[3][3]) == 1); + assert ($low(s.sz.z[3], 2) == 1); + + assert ($left(s.x) == 5); + assert ($left(s.sy.y) == 2); + assert ($left(s.sy.y, 1) == 2); + assert ($left(s.sy.y, (1+1)) == 3); + + assert ($left(s.sz.z) == 7); + assert ($left(s.sz.z, 1) == 7); + assert ($left(s.sz.z, 2) == 2); + assert ($left(s.sz.z, 3) == 1); + assert ($left(s.sz.z[3]) == 2); + assert ($left(s.sz.z[3][3]) == 1); + assert ($left(s.sz.z[3], 2) == 1); + + assert ($right(s.x) == 2); + assert ($right(s.sy.y) == 7); + assert ($right(s.sy.y, 1) == 7); + assert ($right(s.sy.y, (1+1)) == 0); + + assert ($right(s.sz.z) == 2); + assert ($right(s.sz.z, 1) == 2); + assert ($right(s.sz.z, 2) == 9); + assert ($right(s.sz.z, 3) == 4); + assert ($right(s.sz.z[3]) == 9); + assert ($right(s.sz.z[3][3]) == 4); + assert ($right(s.sz.z[3], 2) == 4); +end + +endmodule diff --git a/yosys/tests/svtypes/typedef_scopes.sv b/yosys/tests/svtypes/typedef_scopes.sv index 9a898fac8a4..5ac9a4664c4 100644 --- a/yosys/tests/svtypes/typedef_scopes.sv +++ b/yosys/tests/svtypes/typedef_scopes.sv @@ -17,6 +17,12 @@ module top; always @(*) assert(inner_i1 == 4'hA); always @(*) assert(inner_enum1 == 3'h3); + // adapted from tests/verilog/typedef_const_shadow.sv + localparam W = 5; + typedef logic [W-1:0] T; + T x; // width 5 + always @(*) assert($bits(x) == 5); + if (1) begin: genblock // type declarations in child scopes shadow their parents typedef logic [7:0] inner_type; @@ -34,6 +40,20 @@ module top; } mystruct_t; mystruct_t mystruct; always @(*) assert($bits(mystruct) == 4); + + // adapted from tests/verilog/typedef_const_shadow.sv + localparam W = 10; + typedef T U; + typedef logic [W-1:0] V; + struct packed { + logic [W-1:0] x; // width 10 + U y; // width 5 + V z; // width 10 + } shadow; + // This currently only works as long as long as shadow is not typedef'ed + always @(*) assert($bits(shadow.x) == 10); + always @(*) assert($bits(shadow.y) == 5); + always @(*) assert($bits(shadow.z) == 10); end inner_type inner_i2 = 8'h42; diff --git a/yosys/tests/svtypes/typedef_struct.sv b/yosys/tests/svtypes/typedef_struct.sv index 8df8e32b0bd..136bb5c1bbc 100644 --- a/yosys/tests/svtypes/typedef_struct.sv +++ b/yosys/tests/svtypes/typedef_struct.sv @@ -19,8 +19,10 @@ module top; p::p_t ps; } s_t; + typedef s_t s1_t; + s_t s; - s_t s1; + s1_t s1; p::p_t ps; diff --git a/yosys/tests/techmap/aigmap.ys b/yosys/tests/techmap/aigmap.ys index a40aa39f14b..6f6cdd1f21a 100644 --- a/yosys/tests/techmap/aigmap.ys +++ b/yosys/tests/techmap/aigmap.ys @@ -1,3 +1,118 @@ +read_verilog -icells <, 3, 3, 1) +`BIOP(logic_ge, >=, 3, 3, 1) +`UNOP(pos, +, 3) +`UNOP(neg, ~, 3) +`UNOP_REDUCE(logic_not, !, 3) +`UNOP_REDUCE(reduce_and, &, 3) +`UNOP_REDUCE(reduce_or, |, 3) +`UNOP_REDUCE(reduce_xor, ^, 3) +`UNOP_REDUCE(reduce_xnor, ~^, 3) + +wire [3:0] mux_a, mux_b, mux_s, mux_y; +assign mux_y = mux_s ? mux_b : mux_a; +endmodule +EOF + +expose -input c:* %ci* w:* %i +expose c:* %co* w:* %i +copy test gold +aigmap test +select -assert-none test/t:$_AND_ test/t:$_NOT_ %% test/c:* %D +miter -equiv -flatten gold test miter +sat -verify -prove trigger 0 miter + + +design -reset read_verilog < test.log 2>&1 || echo {workdir}: failed > status\n" f"\t@cat {workdir}/status\n" - # f"\t@grep '^.*: ok' {workdir}/status\n" + f"\t@grep '^.*: ok' {workdir}/status\n" , file=makefile, ) @@ -123,50 +124,55 @@ def dffe_test(width, pol, enpol, defclock): print("all:\n\t@echo done\n", file=makefile) for cell in ["not", "pos", "neg"]: - unary_test(cell, 1, False, 1) - unary_test(cell, 3, False, 3) - unary_test(cell, 3, True, 3) - unary_test(cell, 3, True, 1) - unary_test(cell, 3, False, 5) + if args.more: + unary_test(cell, 1, False, 1) + unary_test(cell, 3, False, 3) + unary_test(cell, 3, True, 3) + unary_test(cell, 3, True, 1) + unary_test(cell, 3, False, 5) unary_test(cell, 3, True, 5) for cell in ["and", "or", "xor", "xnor"]: binary_test(cell, 1, 1, False, 1) binary_test(cell, 1, 1, True, 2) binary_test(cell, 2, 2, False, 2) - binary_test(cell, 2, 2, False, 1) - binary_test(cell, 2, 1, False, 2) - binary_test(cell, 2, 1, False, 1) + if args.more: + binary_test(cell, 2, 2, False, 1) + binary_test(cell, 2, 1, False, 2) + binary_test(cell, 2, 1, False, 1) # [, "pow"] are not implemented yet for cell in ["add", "sub", "mul", "div", "mod", "divfloor", "modfloor"]: - binary_test(cell, 1, 1, False, 1) - binary_test(cell, 1, 1, False, 2) - binary_test(cell, 3, 3, False, 1) - binary_test(cell, 3, 3, False, 3) - binary_test(cell, 3, 3, False, 6) - binary_test(cell, 3, 3, True, 1) - binary_test(cell, 3, 3, True, 3) - binary_test(cell, 3, 3, True, 6) + if args.more: + binary_test(cell, 1, 1, False, 1) + binary_test(cell, 1, 1, False, 2) + binary_test(cell, 3, 3, False, 1) + binary_test(cell, 3, 3, False, 3) + binary_test(cell, 3, 3, False, 6) + binary_test(cell, 3, 3, True, 1) + binary_test(cell, 3, 3, True, 3) + binary_test(cell, 3, 3, True, 6) binary_test(cell, 5, 3, False, 3) binary_test(cell, 5, 3, True, 3) for cell in ["lt", "le", "eq", "ne", "eqx", "nex", "ge", "gt"]: - binary_test(cell, 1, 1, False, 1) - binary_test(cell, 1, 1, False, 2) - binary_test(cell, 3, 3, False, 1) - binary_test(cell, 3, 3, False, 2) - binary_test(cell, 3, 3, True, 1) - binary_test(cell, 3, 3, True, 2) - binary_test(cell, 5, 3, False, 1) - binary_test(cell, 5, 3, True, 1) + if args.more: + binary_test(cell, 1, 1, False, 1) + binary_test(cell, 1, 1, False, 2) + binary_test(cell, 3, 3, False, 1) + binary_test(cell, 3, 3, False, 2) + binary_test(cell, 3, 3, True, 1) + binary_test(cell, 3, 3, True, 2) + binary_test(cell, 5, 3, False, 1) + binary_test(cell, 5, 3, True, 1) binary_test(cell, 5, 3, False, 2) binary_test(cell, 5, 3, True, 2) for cell in ["reduce_and", "reduce_or", "reduce_xor", "reduce_xnor"]: - unary_test(cell, 1, False, 1) - unary_test(cell, 3, False, 1) - unary_test(cell, 3, True, 1) + if args.more: + unary_test(cell, 1, False, 1) + unary_test(cell, 3, False, 1) + unary_test(cell, 3, True, 1) unary_test(cell, 3, False, 3) unary_test(cell, 3, True, 3) @@ -183,33 +189,36 @@ def dffe_test(width, pol, enpol, defclock): binary_test(cell, 3, 3, True, 1) for cell in ["shl", "shr", "sshl", "sshr", "shift"]: - shift_test(cell, 2, 1, False, False, 2) - shift_test(cell, 2, 1, True, False, 2) - shift_test(cell, 2, 1, False, False, 4) - shift_test(cell, 2, 1, True, False, 4) - shift_test(cell, 4, 2, False, False, 4) - shift_test(cell, 4, 2, True, False, 4) - shift_test(cell, 4, 2, False, False, 8) - shift_test(cell, 4, 2, True, False, 8) + if args.more: + shift_test(cell, 2, 1, False, False, 2) + shift_test(cell, 2, 1, True, False, 2) + shift_test(cell, 2, 1, False, False, 4) + shift_test(cell, 2, 1, True, False, 4) + shift_test(cell, 4, 2, False, False, 4) + shift_test(cell, 4, 2, True, False, 4) + shift_test(cell, 4, 2, False, False, 8) + shift_test(cell, 4, 2, True, False, 8) shift_test(cell, 4, 3, False, False, 3) shift_test(cell, 4, 3, True, False, 3) for cell in ["shift"]: - shift_test(cell, 2, 1, False, True, 2) - shift_test(cell, 2, 1, True, True, 2) - shift_test(cell, 2, 1, False, True, 4) - shift_test(cell, 2, 1, True, True, 4) - shift_test(cell, 4, 2, False, True, 4) - shift_test(cell, 4, 2, True, True, 4) + if args.more: + shift_test(cell, 2, 1, False, True, 2) + shift_test(cell, 2, 1, True, True, 2) + shift_test(cell, 2, 1, False, True, 4) + shift_test(cell, 2, 1, True, True, 4) + shift_test(cell, 4, 2, False, True, 4) + shift_test(cell, 4, 2, True, True, 4) shift_test(cell, 4, 2, False, True, 8) shift_test(cell, 4, 2, True, True, 8) shift_test(cell, 4, 3, False, True, 3) shift_test(cell, 4, 3, True, True, 3) for cell in ["shiftx"]: - shift_test(cell, 2, 1, False, True, 2) - shift_test(cell, 2, 1, False, True, 4) - shift_test(cell, 4, 2, False, True, 4) + if args.more: + shift_test(cell, 2, 1, False, True, 2) + shift_test(cell, 2, 1, False, True, 4) + shift_test(cell, 4, 2, False, True, 4) shift_test(cell, 4, 2, False, True, 8) shift_test(cell, 4, 3, False, True, 3) diff --git a/yosys/tests/xprop/run-test.sh b/yosys/tests/xprop/run-test.sh index 1fc7e10b6f2..db4b7ca82dd 100755 --- a/yosys/tests/xprop/run-test.sh +++ b/yosys/tests/xprop/run-test.sh @@ -2,4 +2,4 @@ set -e python3 generate.py $@ -make -f run-test.mk +${MAKE:-make} -f run-test.mk diff --git a/yosys/tests/xprop/test.py b/yosys/tests/xprop/test.py index 84ad0a1f49e..a275b0d93f2 100644 --- a/yosys/tests/xprop/test.py +++ b/yosys/tests/xprop/test.py @@ -47,7 +47,7 @@ def yosys(command): - subprocess.check_call(["yosys", "-Qp", command]) + subprocess.check_call(["../../../yosys", "-Qp", command]) def remove(file): try: @@ -275,7 +275,7 @@ def vcdextract(signals, on_change, file, output, limit=None): file=tb_file, ) - print(" $finish;", file=tb_file) + print(" $finish(0);", file=tb_file) print("end", file=tb_file) print("endmodule", file=tb_file) @@ -344,8 +344,8 @@ def vcdextract(signals, on_change, file, output, limit=None): read_rtlil wrapped{mode}.il chformal -remove dffunmap - write_verilog -noparallelcase vsim_expr{mode}.v write_verilog -noexpr vsim_noexpr{mode}.v + write_verilog -noparallelcase vsim_expr{mode}.v """ ) @@ -357,15 +357,15 @@ def vcdextract(signals, on_change, file, output, limit=None): "-DSIMLIB_FF", "-DSIMLIB_GLOBAL_CLOCK=top.gclk", f"-DDUMPFILE=\"vsim_{expr}.vcd\"", + "-o", + f"vsim_{expr}", "verilog_sim_tb.v", f"vsim_{expr}.v", *simlibs, - "-o", - f"vsim_{expr}", ] ) with open(f"vsim_{expr}.out", "w") as f: - subprocess.check_call([f"./vsim_{expr}"], stdout=f) + subprocess.check_call(["vvp", f"./vsim_{expr}"], stdout=f) for mode in ["", "_xprop"]: if f"sim{mode}" not in steps: