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Merge branch 'master' of https://github.com/verilog-to-routing/vtr-ve…
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…rilog-to-routing into enable_simple_place_delay_matrix
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@amin1377
amin1377 committed Jul 4, 2024
2 parents a26bbbb + 9ddb7d5 commit c276183
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10 changes: 5 additions & 5 deletions ...ression_tests/vtr_reg_nightly_test2_odin/vtr_reg_netlist_writer/config/golden_results.txt
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arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time placement_technique reward uniform_percentage median_percentage wmedian_percentage wcent_percentage fr_percentage critUni_percentage centroid_percentage
k6_frac_N10_frac_chain_mem32K_40nm.xml or1200.v common 46.77 0.49 39160 8 4.13 -1 -1 41800 -1 -1 251 385 2 1 success v8.0.0-3151-g91780fa55 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-11-24T20:22:40 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/gold/vtr-verilog-to-routing 138776 385 394 4649 4513 1 2401 1033 27 27 729 io auto 6.76 30535 4.20 0.04 8.37774 -9522.24 -8.37774 8.37774 1.59 0.00762603 0.00673234 1.23445 0.997069 94 45704 22 3.93038e+07 1.50194e+07 4.32855e+06 5937.65 21.75 4.30652 3.74351 43030 18 9178 31621 3221515 626848 9.02636 9.02636 -10569.8 -9.02636 0 0 5.45059e+06 7476.80 1.24 0.99 0.446411 0.409549 simple RL 'Softmax agent' -1 -1 -1 -1 -1 -1 -1 -1
k6_frac_N10_frac_chain_mem32K_40nm.xml sha.v common 274.10 0.68 36632 3 258.41 -1 -1 95124 -1 -1 156 38 0 0 success v8.0.0-3151-g91780fa55 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-11-24T20:22:40 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/gold/vtr-verilog-to-routing 78456 38 36 2995 2744 1 1210 230 17 17 289 clb auto 1.81 11099 1.05 0.01 8.60024 -2289.89 -8.60024 8.60024 0.45 0.00260047 0.00216983 0.404214 0.306061 66 16854 22 1.34605e+07 8.40746e+06 1.18400e+06 4096.89 5.96 1.89147 1.53826 15692 22 4746 12707 469422 81010 9.99242 9.99242 -2671.82 -9.99242 0 0 1.47169e+06 5092.36 0.25 0.30 0.216914 0.193404 simple RL 'Softmax agent' -1 -1 -1 -1 -1 -1 -1 -1
k6_frac_N10_frac_chain_mem32K_40nm.xml boundtop.v common 5.28 0.48 43800 3 0.40 -1 -1 37540 -1 -1 93 142 0 0 success v8.0.0-3151-g91780fa55 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-11-24T20:22:40 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/gold/vtr-verilog-to-routing 47708 142 192 1069 1139 1 566 427 14 14 196 clb auto 0.60 1719 0.65 0.00 2.89823 -451.929 -2.89823 2.89823 0.29 0.00100274 0.000878888 0.199563 0.172168 38 3929 16 9.20055e+06 5.01214e+06 467348. 2384.43 0.79 0.439179 0.38845 3370 10 1156 1738 87127 23536 3.536 3.536 -547.719 -3.536 0 0 593372. 3027.41 0.11 0.06 0.045063 0.0423974 simple RL 'Softmax agent' -1 -1 -1 -1 -1 -1 -1 -1
k6_frac_N10_frac_chain_mem32K_40nm.xml raygentop.v common 19.91 0.31 30760 3 0.89 -1 -1 40300 -1 -1 111 214 0 8 success v8.0.0-3151-g91780fa55 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-11-24T20:22:40 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/gold/vtr-verilog-to-routing 79568 214 305 2963 2869 1 1440 638 19 19 361 io auto 2.12 11058 1.27 0.01 4.28804 -2547.99 -4.28804 4.28804 0.60 0.00301613 0.00263093 0.424224 0.360855 58 23745 38 1.72706e+07 9.15023e+06 1.32779e+06 3678.09 10.83 1.91038 1.67702 19546 16 5825 13540 3597927 808321 4.87643 4.87643 -2976.1 -4.87643 0 0 1.69263e+06 4688.74 0.31 0.64 0.181044 0.168161 simple RL 'Softmax agent' -1 -1 -1 -1 -1 -1 -1 -1
arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time
k6_frac_N10_frac_chain_mem32K_40nm.xml or1200.v common 68.70 vpr 141.21 MiB 0.93 39844 -1 -1 8 4.37 -1 -1 41924 -1 -1 258 385 2 1 success v8.0.0-10540-ge7ec2194c release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-07-02T21:29:38 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 144600 385 394 4673 4537 1 2422 1040 27 27 729 io auto 62.8 MiB 9.25 31099 601478 234916 341577 24985 100.0 MiB 5.37 0.06 7.91028 -9390.87 -7.91028 7.91028 2.16 0.0160116 0.0148357 1.92959 1.75908 98 45582 18 3.93038e+07 1.53967e+07 4.48119e+06 6147.03 34.34 8.78739 8.0602 101765 947141 -1 43516 17 9970 36172 3767326 768291 8.49882 8.49882 -10225.8 -8.49882 0 0 5.68448e+06 7797.64 1.45 1.61 0.90 -1 -1 1.45 0.711623 0.664406
k6_frac_N10_frac_chain_mem32K_40nm.xml sha.v common 248.04 abc 92.62 MiB 2.07 38132 -1 -1 3 222.88 -1 -1 94848 -1 -1 156 38 0 0 success v8.0.0-10540-ge7ec2194c release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-07-02T21:29:38 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 85708 38 36 2995 2744 1 1210 230 17 17 289 clb auto 46.9 MiB 2.35 11187 48102 12239 32898 2965 83.7 MiB 1.02 0.02 8.50665 -2425.54 -8.50665 8.50665 0.68 0.00648791 0.00577114 0.492669 0.42844 86 15535 20 1.34605e+07 8.40746e+06 1.47169e+06 5092.36 8.86 2.72296 2.3536 36379 299185 -1 14997 15 3639 10555 369332 60267 10.0216 10.0216 -2922.92 -10.0216 0 0 1.86203e+06 6443.01 0.42 0.41 0.32 -1 -1 0.42 0.297614 0.2695
k6_frac_N10_frac_chain_mem32K_40nm.xml boundtop.v common 8.70 vpr 70.45 MiB 0.75 45128 -1 -1 3 0.52 -1 -1 37948 -1 -1 92 142 0 0 success v8.0.0-10540-ge7ec2194c release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-07-02T21:29:38 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 72136 142 193 1069 1140 1 565 427 14 14 196 clb auto 32.4 MiB 0.82 1818 153092 57142 75216 20734 70.4 MiB 0.62 0.01 2.94229 -453.47 -2.94229 2.94229 0.43 0.00270225 0.00251819 0.270422 0.252062 36 4119 16 9.20055e+06 4.95825e+06 447080. 2281.02 1.25 0.678648 0.626119 18336 87587 -1 3545 13 1258 1911 94099 25244 3.69367 3.69367 -542.415 -3.69367 0 0 553089. 2821.88 0.13 0.13 0.06 -1 -1 0.13 0.0968577 0.090647
k6_frac_N10_frac_chain_mem32K_40nm.xml raygentop.v common 24.99 vpr 84.66 MiB 0.47 31528 -1 -1 3 1.06 -1 -1 40312 -1 -1 112 214 0 8 success v8.0.0-10540-ge7ec2194c release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-07-02T21:29:38 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 86692 214 305 2963 2869 1 1445 639 19 19 361 io auto 46.9 MiB 2.82 10827 256482 85370 157603 13509 84.7 MiB 1.63 0.02 4.36739 -2477.41 -4.36739 4.36739 0.89 0.00721181 0.00661461 0.712875 0.654201 56 24300 32 1.72706e+07 9.20413e+06 1.27879e+06 3542.35 11.31 2.9929 2.72715 39043 256479 -1 19887 20 6510 14395 4285781 1013890 4.87643 4.87643 -2933.55 -4.87643 0 0 1.63234e+06 4521.70 0.37 1.20 0.23 -1 -1 0.37 0.376058 0.348776
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