From d94ad2de78cf7a10b0062616e966d8b5bdd63a77 Mon Sep 17 00:00:00 2001 From: amin1377 Date: Wed, 14 Aug 2024 15:33:24 -0400 Subject: [PATCH] Revert "[libs][librrgraph] update uxsdcxx generate files" This reverts commit ec8fee7c13f747c3db7e25f59ff6db814b1489cc. --- libs/librrgraph/src/io/gen/rr_graph_uxsdcxx.h | 40 ++++--------------- .../src/io/gen/rr_graph_uxsdcxx_capnp.h | 9 ++--- .../src/io/gen/rr_graph_uxsdcxx_interface.h | 9 ++--- libs/librrgraph/src/io/rr_graph.xsd | 1 - .../src/io/rr_graph_uxsdcxx_serializer.h | 4 -- .../gen/rr_graph_uxsdcxx.capnp | 15 ++++--- 6 files changed, 20 insertions(+), 58 deletions(-) diff --git a/libs/librrgraph/src/io/gen/rr_graph_uxsdcxx.h b/libs/librrgraph/src/io/gen/rr_graph_uxsdcxx.h index cfb34f754ec..e276ba29f1a 100644 --- a/libs/librrgraph/src/io/gen/rr_graph_uxsdcxx.h +++ b/libs/librrgraph/src/io/gen/rr_graph_uxsdcxx.h @@ -4,9 +4,9 @@ * https://github.com/duck2/uxsdcxx * Modify only if your build process doesn't involve regenerating this file. * - * Cmdline: uxsdcxx/uxsdcxx.py /home/mohagh18/vtr-verilog-to-routing/libs/librrgraph/src/io/rr_graph.xsd - * Input file: /home/mohagh18/vtr-verilog-to-routing/libs/librrgraph/src/io/rr_graph.xsd - * md5sum of input file: 65eddcc840064bbb91d7f4cf0b8bf821 + * Cmdline: /home/talaeikh/uxsdcxx/uxsdcxx.py /home/talaeikh/vtr-verilog-to-routing/libs/librrgraph/src/io/rr_graph.xsd + * Input file: /home/talaeikh/vtr-verilog-to-routing/libs/librrgraph/src/io/rr_graph.xsd + * md5sum of input file: 9c14a0ddd3c6bc1e690ca6abf467bae6 */ #include @@ -247,8 +247,8 @@ constexpr const char *atok_lookup_t_segment_timing[] = {"C_per_meter", "R_per_me enum class gtok_t_segment {TIMING}; constexpr const char *gtok_lookup_t_segment[] = {"timing"}; -enum class atok_t_segment {ID, LENGTH, NAME, RES_TYPE}; -constexpr const char *atok_lookup_t_segment[] = {"id", "length", "name", "res_type"}; +enum class atok_t_segment {ID, NAME, RES_TYPE}; +constexpr const char *atok_lookup_t_segment[] = {"id", "name", "res_type"}; enum class gtok_t_segments {SEGMENT}; constexpr const char *gtok_lookup_t_segments[] = {"segment"}; @@ -792,24 +792,6 @@ inline atok_t_segment lex_attr_t_segment(const char *in, const std::function * report_error){ - std::bitset<4> astate = 0; + std::bitset<3> astate = 0; for(pugi::xml_attribute attr = root.first_attribute(); attr; attr = attr.next_attribute()){ atok_t_segment in = lex_attr_t_segment(attr.name(), report_error); if(astate[(int)in] == 0) astate[(int)in] = 1; @@ -2352,9 +2334,6 @@ inline void load_segment_required_attributes(const pugi::xml_node &root, int * i case atok_t_segment::ID: *id = load_int(attr.value(), report_error); break; - case atok_t_segment::LENGTH: - /* Attribute length set after element init */ - break; case atok_t_segment::NAME: /* Attribute name set after element init */ break; @@ -2364,7 +2343,7 @@ inline void load_segment_required_attributes(const pugi::xml_node &root, int * i default: break; /* Not possible. */ } } - std::bitset<4> test_astate = astate | std::bitset<4>(0b1010); + std::bitset<3> test_astate = astate | std::bitset<3>(0b100); if(!test_astate.all()) attr_error(test_astate, atok_lookup_t_segment, report_error); } @@ -2957,9 +2936,6 @@ inline void load_segment(const pugi::xml_node &root, T &out, Context &context, c case atok_t_segment::ID: /* Attribute id is already set */ break; - case atok_t_segment::LENGTH: - out.set_segment_length(load_int(attr.value(), report_error), context); - break; case atok_t_segment::NAME: out.set_segment_name(attr.value(), context); break; @@ -4030,8 +4006,6 @@ inline void write_segments(T &in, std::ostream &os, Context &context){ auto child_context = in.get_segments_segment(i, context); os << " @@ -601,7 +601,6 @@ inline void load_segment_capnp_type(const ucap::Segment::Reader &root, T &out, C (void)report_error; (void)stack; - out.set_segment_length(root.getLength(), context); out.set_segment_name(root.getName().cStr(), context); out.set_segment_res_type(conv_enum_segment_res_type(root.getResType(), report_error), context); stack->push_back(std::make_pair("getTiming", 0)); @@ -1102,8 +1101,6 @@ inline void write_segments_capnp_type(T &in, ucap::Segments::Builder &root, Cont auto segments_segment = segments_segments[i]; auto child_context = in.get_segments_segment(i, context); segments_segment.setId(in.get_segment_id(child_context)); - if((bool)in.get_segment_length(child_context)) - segments_segment.setLength(in.get_segment_length(child_context)); segments_segment.setName(in.get_segment_name(child_context)); if((bool)in.get_segment_res_type(child_context)) segments_segment.setResType(conv_to_enum_segment_res_type(in.get_segment_res_type(child_context))); diff --git a/libs/librrgraph/src/io/gen/rr_graph_uxsdcxx_interface.h b/libs/librrgraph/src/io/gen/rr_graph_uxsdcxx_interface.h index ac0e16d1418..4edff09238b 100644 --- a/libs/librrgraph/src/io/gen/rr_graph_uxsdcxx_interface.h +++ b/libs/librrgraph/src/io/gen/rr_graph_uxsdcxx_interface.h @@ -4,9 +4,9 @@ * https://github.com/duck2/uxsdcxx * Modify only if your build process doesn't involve regenerating this file. * - * Cmdline: uxsdcxx/uxsdcxx.py /home/mohagh18/vtr-verilog-to-routing/libs/librrgraph/src/io/rr_graph.xsd - * Input file: /home/mohagh18/vtr-verilog-to-routing/libs/librrgraph/src/io/rr_graph.xsd - * md5sum of input file: 65eddcc840064bbb91d7f4cf0b8bf821 + * Cmdline: /home/talaeikh/uxsdcxx/uxsdcxx.py /home/talaeikh/vtr-verilog-to-routing/libs/librrgraph/src/io/rr_graph.xsd + * Input file: /home/talaeikh/vtr-verilog-to-routing/libs/librrgraph/src/io/rr_graph.xsd + * md5sum of input file: 9c14a0ddd3c6bc1e690ca6abf467bae6 */ #include @@ -245,14 +245,11 @@ class RrGraphBase { * * * - * * * * */ virtual inline int get_segment_id(typename ContextTypes::SegmentReadContext &ctx) = 0; - virtual inline int get_segment_length(typename ContextTypes::SegmentReadContext &ctx) = 0; - virtual inline void set_segment_length(int length, typename ContextTypes::SegmentWriteContext &ctx) = 0; virtual inline const char * get_segment_name(typename ContextTypes::SegmentReadContext &ctx) = 0; virtual inline void set_segment_name(const char * name, typename ContextTypes::SegmentWriteContext &ctx) = 0; virtual inline enum_segment_res_type get_segment_res_type(typename ContextTypes::SegmentReadContext &ctx) = 0; diff --git a/libs/librrgraph/src/io/rr_graph.xsd b/libs/librrgraph/src/io/rr_graph.xsd index cea5a0f7b22..b990c488682 100644 --- a/libs/librrgraph/src/io/rr_graph.xsd +++ b/libs/librrgraph/src/io/rr_graph.xsd @@ -155,7 +155,6 @@ - diff --git a/libs/librrgraph/src/io/rr_graph_uxsdcxx_serializer.h b/libs/librrgraph/src/io/rr_graph_uxsdcxx_serializer.h index c65ec9b2f54..53d365b24e6 100644 --- a/libs/librrgraph/src/io/rr_graph_uxsdcxx_serializer.h +++ b/libs/librrgraph/src/io/rr_graph_uxsdcxx_serializer.h @@ -1347,9 +1347,6 @@ class RrGraphSerializer final : public uxsd::RrGraphBase { inline const char* get_segment_name(const t_segment_inf*& segment) final { return segment->name.c_str(); } - inline int get_segment_length(const t_segment_inf*& segment) final { - return segment->length; - } inline void set_segment_name(const char* name, const t_segment_inf*& segment) final { if (segment->name != name) { report_error( @@ -1357,7 +1354,6 @@ class RrGraphSerializer final : public uxsd::RrGraphBase { segment->name.c_str(), name); } } - inline void set_segment_length(int /*length*/, const t_segment_inf*& /*segment*/) final {} inline uxsd::enum_segment_res_type get_segment_res_type(const t_segment_inf*& segment) final { return to_uxsd_segment_res_type(segment->res_type); } diff --git a/libs/libvtrcapnproto/gen/rr_graph_uxsdcxx.capnp b/libs/libvtrcapnproto/gen/rr_graph_uxsdcxx.capnp index 4ea37de3f7e..b8ae564a385 100644 --- a/libs/libvtrcapnproto/gen/rr_graph_uxsdcxx.capnp +++ b/libs/libvtrcapnproto/gen/rr_graph_uxsdcxx.capnp @@ -2,11 +2,11 @@ # https://github.com/duck2/uxsdcxx # Modify only if your build process doesn't involve regenerating this file. # -# Cmdline: uxsdcxx/uxsdcap.py /home/mohagh18/vtr-verilog-to-routing/libs/librrgraph/src/io/rr_graph.xsd -# Input file: /home/mohagh18/vtr-verilog-to-routing/libs/librrgraph/src/io/rr_graph.xsd -# md5sum of input file: 65eddcc840064bbb91d7f4cf0b8bf821 +# Cmdline: /home/talaeikh/uxsdcxx/uxsdcap.py /home/talaeikh/vtr-verilog-to-routing/libs/librrgraph/src/io/rr_graph.xsd +# Input file: /home/talaeikh/vtr-verilog-to-routing/libs/librrgraph/src/io/rr_graph.xsd +# md5sum of input file: 9c14a0ddd3c6bc1e690ca6abf467bae6 -@0xe787bf7696810419; +@0xa136dd28cdc8783b; using Cxx = import "/capnp/c++.capnp"; $Cxx.namespace("ucap"); @@ -129,10 +129,9 @@ struct SegmentTiming { struct Segment { id @0 :Int32; - length @1 :Int32; - name @2 :Text; - resType @3 :SegmentResType; - timing @4 :SegmentTiming; + name @1 :Text; + resType @2 :SegmentResType; + timing @3 :SegmentTiming; } struct Segments {