From ff6dd80b40ce394bc1bd5bf93796d20b111e08a6 Mon Sep 17 00:00:00 2001 From: "Amir.A" Date: Mon, 16 Dec 2024 00:10:32 -0400 Subject: [PATCH] f4pga systemverilog tests flattened --- .github/workflows/nightly_test.yml | 2 +- libs/EXTERNAL/CMakeLists.txt | 16 +- .../benchmarks/system_verilog/f4pga/README.md | 12 +- .../flattened_button_controller.sv | 241 ++++++++++++++++++ .../button_controller/make_sv_flattened.py | 63 +++++ .../flattened_pulse_width_led.sv | 52 ++++ .../pulse_width_led/make_sv_flattened.py | 63 +++++ .../f4pga/timer/flattened_timer.sv | 230 +++++++++++++++++ .../f4pga/timer/make_sv_flattened.py | 63 +++++ vtr_flow/misc/yosys/synthesis.tcl | 6 +- .../f4pga_button_controller/config/config.txt | 10 +- .../f4pga_pulse_width_led/config/config.txt | 5 +- .../f4pga_timer/config/config.txt | 10 +- .../vtr_reg_system_verilog/task_list.txt | 2 +- 14 files changed, 755 insertions(+), 20 deletions(-) create mode 100644 vtr_flow/benchmarks/system_verilog/f4pga/button_controller/flattened_button_controller.sv create mode 100644 vtr_flow/benchmarks/system_verilog/f4pga/button_controller/make_sv_flattened.py create mode 100644 vtr_flow/benchmarks/system_verilog/f4pga/pulse_width_led/flattened_pulse_width_led.sv create mode 100644 vtr_flow/benchmarks/system_verilog/f4pga/pulse_width_led/make_sv_flattened.py create mode 100644 vtr_flow/benchmarks/system_verilog/f4pga/timer/flattened_timer.sv create mode 100644 vtr_flow/benchmarks/system_verilog/f4pga/timer/make_sv_flattened.py diff --git a/.github/workflows/nightly_test.yml b/.github/workflows/nightly_test.yml index 2806e0ba94b..c39d4d4a8f1 100644 --- a/.github/workflows/nightly_test.yml +++ b/.github/workflows/nightly_test.yml @@ -41,7 +41,7 @@ jobs: # Prevents from running on forks where no custom runners are available if: ${{ github.repository_owner == 'verilog-to-routing' }} - timeout-minutes: 700 #420 + timeout-minutes: 420 container: ubuntu:jammy diff --git a/libs/EXTERNAL/CMakeLists.txt b/libs/EXTERNAL/CMakeLists.txt index 1e1fabc3c56..556a9f8dd75 100644 --- a/libs/EXTERNAL/CMakeLists.txt +++ b/libs/EXTERNAL/CMakeLists.txt @@ -1,4 +1,5 @@ include(ExternalProject) +include(ProcessorCount) #Manually synchronized external libraries add_subdirectory(libpugixml) @@ -9,8 +10,17 @@ add_subdirectory(libsdcparse) add_subdirectory(libblifparse) add_subdirectory(libtatum) add_subdirectory(libcatch2) +#add_subdirectory(synlig) #add_subdirectory(parmys) +#Proc numbers +ProcessorCount(PROCESSOR_COUNT) + +if(PROCESSOR_COUNT EQUAL 0) + # Fallback to 1 if the processor count cannot be determined + set(PROCESSOR_COUNT 1) +endif() + #VPR_USE_SERVER is initialized in the root CMakeLists #compile sockpp only if server mode is enabled if (VPR_USE_SERVER) @@ -63,7 +73,7 @@ if (${WITH_PARMYS}) LOG_OUTPUT_ON_FAILURE ON # dependency - DEPENDS yosys + DEPENDS yosys ) # Synlig integration (manages Surelog and UHDM internally) @@ -92,7 +102,7 @@ if (${WITH_PARMYS}) UPDATE_COMMAND git submodule update --init --recursive third_party/surelog WORKING_DIRECTORY ${SYNLIG_SOURCE_DIR} - BUILD_COMMAND ${MAKE_PROGRAM} -C ${SYNLIG_SOURCE_DIR} install DESTDIR=${CMAKE_BINARY_DIR}/bin/synlig_install -j${CUSTOM_BUILD_PARALLEL_LEVEL} + BUILD_COMMAND ${MAKE_PROGRAM} -C ${SYNLIG_SOURCE_DIR} install DESTDIR=${CMAKE_BINARY_DIR}/bin/synlig_install -j${PROCESSOR_COUNT} INSTALL_COMMAND "" CONFIGURE_COMMAND "" @@ -114,7 +124,7 @@ if (${WITH_PARMYS}) # Ensure dependencies like Yosys are built first DEPENDS yosys # Ensure submodule sync runs before synlig build ) - + endif () endif () diff --git a/vtr_flow/benchmarks/system_verilog/f4pga/README.md b/vtr_flow/benchmarks/system_verilog/f4pga/README.md index 1887a0a2681..2d3e481d3a4 100644 --- a/vtr_flow/benchmarks/system_verilog/f4pga/README.md +++ b/vtr_flow/benchmarks/system_verilog/f4pga/README.md @@ -4,4 +4,14 @@ This folder contains the `button_controller`, `pulse_width_led` and `timer` benc The benchmarks are directly copied to avoid dealing with a significant amount of code by adding the F4PGA repository as a subtree to the VTR repository. The primary purpose of these benchmarks is to utilize them in VTR GitHub CI tests to continuously monitor the functionality of the Yosys SystemVerilog and UHDM plugins. -For more information please see the ['ChipsAlliance/F4PGA'](https://github.com/chipsalliance/f4pga) Github repository. \ No newline at end of file +For more information please see the ['ChipsAlliance/F4PGA'](https://github.com/chipsalliance/f4pga) Github repository. + +## SystemVerilog File Flattening with `make_sv_flattened.py` + +The current SystemVerilog tool, **Synlig**, cannot process multiple files as input (e.g., a top module and its dependencies). To address this limitation, use the script `make_sv_flattened.py` to flatten the files into a single SystemVerilog file. This will convert any design with dependencies into one flattened SystemVerilog file, ensuring compatibility with Synlig. + +### Instructions: +1. Ensure the `make_sv_flattened.py` script is located in the folder where your SystemVerilog files (e.g., the top module and its dependencies) are gathered. +2. Run the `make_sv_flattened.py` script on the gathered files in that folder. +3. The script will output a single flattened SystemVerilog file, ready for use with Synlig. + diff --git a/vtr_flow/benchmarks/system_verilog/f4pga/button_controller/flattened_button_controller.sv b/vtr_flow/benchmarks/system_verilog/f4pga/button_controller/flattened_button_controller.sv new file mode 100644 index 00000000000..13883b1f424 --- /dev/null +++ b/vtr_flow/benchmarks/system_verilog/f4pga/button_controller/flattened_button_controller.sv @@ -0,0 +1,241 @@ +// Content from button_controller.sv +`timescale 1ns / 1ps `default_nettype none + +module top ( + input wire logic clk, + btnu, + btnc, + output logic [3:0] anode, + output logic [7:0] segment +); + + + logic sync; + logic syncToDebounce; + logic debounceToOneShot; + logic f1, f2; + logic f3, f4; + logic oneShotToCounter; + logic [7:0] counterToSevenSegment; + logic [7:0] counterToSevenSegment2; + logic oneShotToCounter2; + logic s0, s1; + debounce d0 ( + .clk(clk), + .reset(btnu), + .noisy(syncToDebounce), + .debounced(debounceToOneShot) + ); + + assign oneShotToCounter = f1 && ~f2; + + assign oneShotToCounter2 = f3 && ~f4; + + timer #(.MOD_VALUE(256), .BIT_WIDTH(8)) T0 ( + .clk(clk), + .reset(btnu), + .increment(oneShotToCounter), + .rolling_over(s0), + .count(counterToSevenSegment) + ); + + timer #(.MOD_VALUE(256), .BIT_WIDTH(8)) T1 ( + .clk(clk), + .reset(btnu), + .increment(oneShotToCounter2), + .rolling_over(s1), + .count(counterToSevenSegment2) + ); + + + display_control DC0 ( + .clk(clk), + .reset(btnu), + .dataIn({counterToSevenSegment2, counterToSevenSegment}), + .digitDisplay(4'b1111), + .digitPoint(4'b0000), + .anode(anode), + .segment(segment) + ); + + always_ff @(posedge clk) begin + + sync <= btnc; + syncToDebounce <= sync; + + f1 <= debounceToOneShot; + f2 <= f1; + + f3 <= syncToDebounce; + f4 <= f3; + end +endmodule + + +// Content from debounce.sv +`timescale 1ns / 1ps `default_nettype none + +module debounce ( + input wire logic clk, + reset, + noisy, + output logic debounced +); + + logic timerDone, clrTimer; + + typedef enum logic [1:0] { + s0, + s1, + s2, + s3, + ERR = 'X + } state_type_e; + state_type_e ns, cs; + + logic [18:0] tA; + + timer #(.MOD_VALUE(500000), .BIT_WIDTH(19)) T0 ( + .clk(clk), + .reset(clrTimer), + .increment(1'b1), + .rolling_over(timerDone), + .count(tA) + ); + + always_comb begin + ns = ERR; + clrTimer = 0; + debounced = 0; + + if (reset) ns = s0; + else + case (cs) + s0: begin + clrTimer = 1'b1; + if (noisy) ns = s1; + else ns = s0; + end + s1: + if (noisy && timerDone) ns = s2; + else if (noisy && ~timerDone) ns = s1; + else ns = s0; + s2: begin + debounced = 1'b1; + clrTimer = 1'b1; + if (noisy) ns = s2; + else ns = s3; + end + s3: begin + debounced = 1'b1; + if (~noisy && timerDone) ns = s0; + else if (~noisy && ~timerDone) ns = s3; + else ns = s2; + end + endcase + end + + always_ff @(posedge clk) cs <= ns; +endmodule + + +// Content from display_control.sv +`default_nettype none + +module display_control ( + input wire logic clk, + input wire logic reset, + input wire logic [15:0] dataIn, + input wire logic [ 3:0] digitDisplay, + input wire logic [ 3:0] digitPoint, + output logic [ 3:0] anode, + output logic [ 7:0] segment +); + + parameter integer COUNT_BITS = 17; + + logic [COUNT_BITS-1:0] count_val; + logic [ 1:0] anode_select; + logic [ 3:0] cur_anode; + logic [ 3:0] cur_data_in; + + always_ff @(posedge clk) begin + if (reset) count_val <= 0; + else count_val <= count_val + 1; + end + + assign anode_select = count_val[COUNT_BITS-1:COUNT_BITS-2]; + + assign cur_anode = + (anode_select == 2'b00) ? 4'b1110 : + (anode_select == 2'b01) ? 4'b1101 : + (anode_select == 2'b10) ? 4'b1011 : + 4'b0111; + + assign anode = cur_anode | (~digitDisplay); + + assign cur_data_in = + (anode_select == 2'b00) ? dataIn[3:0] : + (anode_select == 2'b01) ? dataIn[7:4] : + (anode_select == 2'b10) ? dataIn[11:8] : + dataIn[15:12] ; + + assign segment[7] = + (anode_select == 2'b00) ? ~digitPoint[0] : + (anode_select == 2'b01) ? ~digitPoint[1] : + (anode_select == 2'b10) ? ~digitPoint[2] : + ~digitPoint[3] ; + + assign segment[6:0] = + (cur_data_in == 0) ? 7'b1000000 : + (cur_data_in == 1) ? 7'b1111001 : + (cur_data_in == 2) ? 7'b0100100 : + (cur_data_in == 3) ? 7'b0110000 : + (cur_data_in == 4) ? 7'b0011001 : + (cur_data_in == 5) ? 7'b0010010 : + (cur_data_in == 6) ? 7'b0000010 : + (cur_data_in == 7) ? 7'b1111000 : + (cur_data_in == 8) ? 7'b0000000 : + (cur_data_in == 9) ? 7'b0010000 : + (cur_data_in == 10) ? 7'b0001000 : + (cur_data_in == 11) ? 7'b0000011 : + (cur_data_in == 12) ? 7'b1000110 : + (cur_data_in == 13) ? 7'b0100001 : + (cur_data_in == 14) ? 7'b0000110 : + 7'b0001110; + + +endmodule + + +// Content from timer.sv +`timescale 1ns / 1ps `default_nettype none + +module timer #( + parameter MOD_VALUE = 1, + parameter BIT_WIDTH = 1 +) ( + input wire logic clk, + reset, + increment, + output logic rolling_over, + output logic [BIT_WIDTH-1:0] count = 0 +); + + always_ff @(posedge clk) begin + if (reset) count <= 0; + else if (increment) begin + if (rolling_over) count <= 0; + else count <= count + 1'b1; + end + + end + + always_comb begin + if (increment && (count == MOD_VALUE - 1)) rolling_over = 1'b1; + else rolling_over = 1'b0; + end + +endmodule + + diff --git a/vtr_flow/benchmarks/system_verilog/f4pga/button_controller/make_sv_flattened.py b/vtr_flow/benchmarks/system_verilog/f4pga/button_controller/make_sv_flattened.py new file mode 100644 index 00000000000..8c3cf2ac402 --- /dev/null +++ b/vtr_flow/benchmarks/system_verilog/f4pga/button_controller/make_sv_flattened.py @@ -0,0 +1,63 @@ +import os +import re + +def find_verilog_files(): + """Find all Verilog (.sv, .v) files in the current directory.""" + return [f for f in os.listdir('.') if f.endswith(('.sv', '.v'))] + +def identify_top_module(file_list): + """Identify the file containing the top module definition.""" + top_module_regex = re.compile(r"module\s+top\s*\(") + for file in file_list: + with open(file, 'r') as f: + for line in f: + if top_module_regex.search(line): + return file + return None + +def create_flattened_file(top_file, file_list): + """Create a flattened Verilog file with all file contents.""" + current_dir = os.path.basename(os.getcwd()) + output_file_name = f"flattened_{current_dir}.sv" + + with open(output_file_name, 'w') as output_file: + if top_file: + # Write the top module first + with open(top_file, 'r') as top_module: + output_file.write(f"// Content from {top_file}\n") + output_file.write(top_module.read()) + output_file.write("\n\n") + + # Write the rest of the files + for file in file_list: + if file != top_file: + with open(file, 'r') as verilog_file: + output_file.write(f"// Content from {file}\n") + output_file.write(verilog_file.read()) + output_file.write("\n\n") + + print(f"Flattened file created: {output_file_name}") + +def main(): + """Main function to generate the flattened Verilog file.""" + print("Searching for Verilog files...") + verilog_files = find_verilog_files() + + if not verilog_files: + print("No Verilog files found in the current directory.") + return + + print("Identifying the top module...") + top_file = identify_top_module(verilog_files) + + if top_file: + print(f"Top module found in: {top_file}") + else: + print("No top module found. Files will be combined in arbitrary order.") + + print("Creating flattened file...") + create_flattened_file(top_file, verilog_files) + +if __name__ == "__main__": + main() + diff --git a/vtr_flow/benchmarks/system_verilog/f4pga/pulse_width_led/flattened_pulse_width_led.sv b/vtr_flow/benchmarks/system_verilog/f4pga/pulse_width_led/flattened_pulse_width_led.sv new file mode 100644 index 00000000000..74e32cc07fe --- /dev/null +++ b/vtr_flow/benchmarks/system_verilog/f4pga/pulse_width_led/flattened_pulse_width_led.sv @@ -0,0 +1,52 @@ +// Content from pulse_led.v +module top ( + input wire clk, + input wire [3:0] sw, + input wire [3:0] btn, + output wire pulse_red, + pulse_blue, + pulse_green +); + wire [13:0] pulse_wideR, pulse_wideB, pulse_wideG; + + assign pulse_wideR = {1'b0, sw[3:1], 10'd0}; + assign pulse_wideG = {1'b0, sw[0], btn[3:2], 10'd0}; + assign pulse_wideB = {btn[1:0], 11'd0}; + + PWM R0 ( + .clk (clk), + .pulse(pulse_red), + .width(pulse_wideR) + ); + PWM B0 ( + .clk (clk), + .pulse(pulse_green), + .width(pulse_wideB) + ); + PWM G0 ( + .clk (clk), + .pulse(pulse_blue), + .width(pulse_wideG) + ); + + +endmodule + + +// Content from PWM.v +module PWM ( + input wire clk, + input wire [13:0] width, + output reg pulse +); + + reg [13:0] counter = 0; + + always @(posedge clk) begin + counter <= counter + 1; + if (counter < width) pulse <= 1'b1; + else pulse <= 1'b0; + end +endmodule + + diff --git a/vtr_flow/benchmarks/system_verilog/f4pga/pulse_width_led/make_sv_flattened.py b/vtr_flow/benchmarks/system_verilog/f4pga/pulse_width_led/make_sv_flattened.py new file mode 100644 index 00000000000..8c3cf2ac402 --- /dev/null +++ b/vtr_flow/benchmarks/system_verilog/f4pga/pulse_width_led/make_sv_flattened.py @@ -0,0 +1,63 @@ +import os +import re + +def find_verilog_files(): + """Find all Verilog (.sv, .v) files in the current directory.""" + return [f for f in os.listdir('.') if f.endswith(('.sv', '.v'))] + +def identify_top_module(file_list): + """Identify the file containing the top module definition.""" + top_module_regex = re.compile(r"module\s+top\s*\(") + for file in file_list: + with open(file, 'r') as f: + for line in f: + if top_module_regex.search(line): + return file + return None + +def create_flattened_file(top_file, file_list): + """Create a flattened Verilog file with all file contents.""" + current_dir = os.path.basename(os.getcwd()) + output_file_name = f"flattened_{current_dir}.sv" + + with open(output_file_name, 'w') as output_file: + if top_file: + # Write the top module first + with open(top_file, 'r') as top_module: + output_file.write(f"// Content from {top_file}\n") + output_file.write(top_module.read()) + output_file.write("\n\n") + + # Write the rest of the files + for file in file_list: + if file != top_file: + with open(file, 'r') as verilog_file: + output_file.write(f"// Content from {file}\n") + output_file.write(verilog_file.read()) + output_file.write("\n\n") + + print(f"Flattened file created: {output_file_name}") + +def main(): + """Main function to generate the flattened Verilog file.""" + print("Searching for Verilog files...") + verilog_files = find_verilog_files() + + if not verilog_files: + print("No Verilog files found in the current directory.") + return + + print("Identifying the top module...") + top_file = identify_top_module(verilog_files) + + if top_file: + print(f"Top module found in: {top_file}") + else: + print("No top module found. Files will be combined in arbitrary order.") + + print("Creating flattened file...") + create_flattened_file(top_file, verilog_files) + +if __name__ == "__main__": + main() + diff --git a/vtr_flow/benchmarks/system_verilog/f4pga/timer/flattened_timer.sv b/vtr_flow/benchmarks/system_verilog/f4pga/timer/flattened_timer.sv new file mode 100644 index 00000000000..5891e940a15 --- /dev/null +++ b/vtr_flow/benchmarks/system_verilog/f4pga/timer/flattened_timer.sv @@ -0,0 +1,230 @@ +// Content from clock.sv +`timescale 1ns / 1ps `default_nettype none + +module top ( + input wire logic clk, + btnc, + sw, + output logic [3:0] anode, + output logic [7:0] segment +); + + logic [15:0] digitData; + + timer TC0 ( + .clk(clk), + .reset(btnc), + .run(sw), + .digit0(digitData[3:0]), + .digit1(digitData[7:4]), + .digit2(digitData[11:8]), + .digit3(digitData[15:12]) + ); + display_control SSC0 ( + .clk(clk), + .reset(btnc), + .dataIn(digitData), + .digitDisplay(4'b1111), + .digitPoint(4'b0100), + .anode(anode), + .segment(segment) + ); +endmodule + + +// Content from modify_count.sv +`default_nettype none + +module modify_count #( + parameter MOD_VALUE = 10 +) ( + input wire logic clk, + reset, + increment, + output logic rolling_over, + output logic [3:0] count = 0 +); + + always_ff @(posedge clk) begin + if (reset) count <= 4'b0000; + else if (increment) begin + if (rolling_over) count <= 4'b0000; + else count <= count + 4'b0001; + end + end + + always_comb begin + if (increment && (count == MOD_VALUE - 1)) rolling_over = 1'b1; + else rolling_over = 1'b0; + end + +endmodule + + +// Content from display_control.sv +`default_nettype none + + +module display_control ( + input wire logic clk, + input wire logic reset, + input wire logic [15:0] dataIn, + input wire logic [ 3:0] digitDisplay, + input wire logic [ 3:0] digitPoint, + output logic [ 3:0] anode, + output logic [ 7:0] segment +); + + parameter integer COUNT_BITS = 17; + + logic [COUNT_BITS-1:0] count_val; + logic [ 1:0] anode_select; + logic [ 3:0] cur_anode; + logic [ 3:0] cur_data_in; + + + always_ff @(posedge clk) begin + if (reset) count_val <= 0; + else count_val <= count_val + 1; + end + + assign anode_select = count_val[COUNT_BITS-1:COUNT_BITS-2]; + + assign cur_anode = + (anode_select == 2'b00) ? 4'b1110 : + (anode_select == 2'b01) ? 4'b1101 : + (anode_select == 2'b10) ? 4'b1011 : + 4'b0111; + + assign anode = cur_anode | (~digitDisplay); + + assign cur_data_in = + (anode_select == 2'b00) ? dataIn[3:0] : + (anode_select == 2'b01) ? dataIn[7:4] : + (anode_select == 2'b10) ? dataIn[11:8] : + dataIn[15:12] ; + + assign segment[7] = + (anode_select == 2'b00) ? ~digitPoint[0] : + (anode_select == 2'b01) ? ~digitPoint[1] : + (anode_select == 2'b10) ? ~digitPoint[2] : + ~digitPoint[3] ; + + assign segment[6:0] = + (cur_data_in == 0) ? 7'b1000000 : + (cur_data_in == 1) ? 7'b1111001 : + (cur_data_in == 2) ? 7'b0100100 : + (cur_data_in == 3) ? 7'b0110000 : + (cur_data_in == 4) ? 7'b0011001 : + (cur_data_in == 5) ? 7'b0010010 : + (cur_data_in == 6) ? 7'b0000010 : + (cur_data_in == 7) ? 7'b1111000 : + (cur_data_in == 8) ? 7'b0000000 : + (cur_data_in == 9) ? 7'b0010000 : + (cur_data_in == 10) ? 7'b0001000 : + (cur_data_in == 11) ? 7'b0000011 : + (cur_data_in == 12) ? 7'b1000110 : + (cur_data_in == 13) ? 7'b0100001 : + (cur_data_in == 14) ? 7'b0000110 : + 7'b0001110; + + +endmodule + + +// Content from timer.sv +`timescale 1ns / 1ps `default_nettype none + +module timer ( + input wire logic clk, + reset, + run, + output logic [3:0] digit0, + digit1, + digit2, + digit3 +); + + logic inc0, inc1, inc2, inc3, inc4; + + logic [23:0] timerCount; + + modify_count #( + .MOD_VALUE(10) + ) M0 ( + .clk(clk), + .reset(reset), + .increment(inc0), + .rolling_over(inc1), + .count(digit0) + ); + modify_count #( + .MOD_VALUE(10) + ) M1 ( + .clk(clk), + .reset(reset), + .increment(inc1), + .rolling_over(inc2), + .count(digit1) + ); + modify_count #( + .MOD_VALUE(10) + ) M2 ( + .clk(clk), + .reset(reset), + .increment(inc2), + .rolling_over(inc3), + .count(digit2) + ); + modify_count #( + .MOD_VALUE(6) + ) M3 ( + .clk(clk), + .reset(reset), + .increment(inc3), + .rolling_over(inc4), + .count(digit3) + ); + + time_counter #( + .MOD_VALUE(1000000) + ) T0 ( + .clk(clk), + .reset(reset), + .increment(run), + .rolling_over(inc0), + .count(timerCount) + ); +endmodule + + +// Content from time_counter.sv +`timescale 1ns / 1ps `default_nettype none + +module time_counter #( + parameter MOD_VALUE = 1000000 +) ( + input wire logic clk, + reset, + increment, + output logic rolling_over, + output logic [23:0] count = 0 +); + + always_ff @(posedge clk) begin + if (reset) count <= 0; + else if (increment) begin + if (rolling_over) count <= 0; + else count <= count + 1'b1; + end + + end + + always_comb begin + if (increment && (count == MOD_VALUE - 1)) rolling_over = 1'b1; + else rolling_over = 1'b0; + end + +endmodule + + diff --git a/vtr_flow/benchmarks/system_verilog/f4pga/timer/make_sv_flattened.py b/vtr_flow/benchmarks/system_verilog/f4pga/timer/make_sv_flattened.py new file mode 100644 index 00000000000..8c3cf2ac402 --- /dev/null +++ b/vtr_flow/benchmarks/system_verilog/f4pga/timer/make_sv_flattened.py @@ -0,0 +1,63 @@ +import os +import re + +def find_verilog_files(): + """Find all Verilog (.sv, .v) files in the current directory.""" + return [f for f in os.listdir('.') if f.endswith(('.sv', '.v'))] + +def identify_top_module(file_list): + """Identify the file containing the top module definition.""" + top_module_regex = re.compile(r"module\s+top\s*\(") + for file in file_list: + with open(file, 'r') as f: + for line in f: + if top_module_regex.search(line): + return file + return None + +def create_flattened_file(top_file, file_list): + """Create a flattened Verilog file with all file contents.""" + current_dir = os.path.basename(os.getcwd()) + output_file_name = f"flattened_{current_dir}.sv" + + with open(output_file_name, 'w') as output_file: + if top_file: + # Write the top module first + with open(top_file, 'r') as top_module: + output_file.write(f"// Content from {top_file}\n") + output_file.write(top_module.read()) + output_file.write("\n\n") + + # Write the rest of the files + for file in file_list: + if file != top_file: + with open(file, 'r') as verilog_file: + output_file.write(f"// Content from {file}\n") + output_file.write(verilog_file.read()) + output_file.write("\n\n") + + print(f"Flattened file created: {output_file_name}") + +def main(): + """Main function to generate the flattened Verilog file.""" + print("Searching for Verilog files...") + verilog_files = find_verilog_files() + + if not verilog_files: + print("No Verilog files found in the current directory.") + return + + print("Identifying the top module...") + top_file = identify_top_module(verilog_files) + + if top_file: + print(f"Top module found in: {top_file}") + else: + print("No top module found. Files will be combined in arbitrary order.") + + print("Creating flattened file...") + create_flattened_file(top_file, verilog_files) + +if __name__ == "__main__": + main() + diff --git a/vtr_flow/misc/yosys/synthesis.tcl b/vtr_flow/misc/yosys/synthesis.tcl index 6dad1978f99..836224eb34f 100644 --- a/vtr_flow/misc/yosys/synthesis.tcl +++ b/vtr_flow/misc/yosys/synthesis.tcl @@ -16,6 +16,7 @@ if {[catch {set synlig $::env(synlig_exe_path)} err]} { puts "Using parmys as partial mapper" } + # arch file: QQQ # input files: [XXX] # other args: [YYY] @@ -26,12 +27,11 @@ parmys_arch -a QQQ if {$env(PARSER) == "surelog" } { puts "Using Synlig read_uhdm command" - + exec $synlig -p "read_uhdm XXX" } elseif {$env(PARSER) == "system-verilog" } { - puts "Using Synlig read_systemverilog command" - + puts "Using Synlig read_systemverilog " exec $synlig -p "read_systemverilog XXX" } elseif {$env(PARSER) == "default" } { diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/f4pga_button_controller/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/f4pga_button_controller/config/config.txt index f20ab703070..5005a12aaca 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/f4pga_button_controller/config/config.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/f4pga_button_controller/config/config.txt @@ -12,12 +12,14 @@ archs_dir=arch/timing # Add circuits to list to sweep -include_list_add=display_control.sv -include_list_add=timer.sv -include_list_add=debounce.sv +#include_list_add=display_control.sv +#include_list_add=timer.sv +#include_list_add=debounce.sv # Add circuits to list to sweep -circuit_list_add=button_controller.sv +#circuit_list_add=button_controller.sv + +circuit_list_add=flattened_button_controller.sv # Add architectures to list to sweep diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/f4pga_pulse_width_led/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/f4pga_pulse_width_led/config/config.txt index 6c7dd369b44..c59221ce1d4 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/f4pga_pulse_width_led/config/config.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/f4pga_pulse_width_led/config/config.txt @@ -12,11 +12,12 @@ archs_dir=arch/timing # Add circuits to list to sweep -include_list_add=PWM.v +#include_list_add=PWM.v # Add circuits to list to sweep -circuit_list_add=pulse_led.v +#circuit_list_add=pulse_led.v +circuit_list_add=flattened_pulse_width_led.sv # Add architectures to list to sweep arch_list_add=k6_frac_N10_frac_chain_mem32K_40nm.xml diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/f4pga_timer/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/f4pga_timer/config/config.txt index 6b753bb4aa6..c2c180dab1d 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/f4pga_timer/config/config.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/f4pga_timer/config/config.txt @@ -12,13 +12,13 @@ archs_dir=arch/timing # Add circuits to list to sweep -include_list_add=timer.sv -include_list_add=display_control.sv -include_list_add=time_counter.sv -include_list_add=modify_count.sv +#include_list_add=timer.sv +#include_list_add=display_control.sv +#include_list_add=time_counter.sv +#include_list_add=modify_count.sv # Add circuits to list to sweep -circuit_list_add=clock.sv +circuit_list_add=flattened_timer.sv # Add architectures to list to sweep diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/task_list.txt b/vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/task_list.txt index 27a696e2c05..509f77a6434 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/task_list.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/task_list.txt @@ -1,3 +1,3 @@ regression_tests/vtr_reg_system_verilog/f4pga_button_controller/ regression_tests/vtr_reg_system_verilog/f4pga_pulse_width_led/ -regression_tests/vtr_reg_system_verilog/f4pga_timer/ \ No newline at end of file +regression_tests/vtr_reg_system_verilog/f4pga_timer/