diff --git a/ODIN_II/SRC/output_blif.cpp b/ODIN_II/SRC/output_blif.cpp index 1b7c8702349..da5992ad597 100644 --- a/ODIN_II/SRC/output_blif.cpp +++ b/ODIN_II/SRC/output_blif.cpp @@ -65,25 +65,26 @@ static bool warn_undriven(nnode_t* node, nnet_t* net) { return false; } -// TODO Uncomment this for In Outs -//static void merge_with_inputs(nnode_t* node, long pin_idx) { -// oassert(pin_idx < node->num_input_pins); -// nnet_t* net = node->input_pins[pin_idx]->net; -// warn_undriven(node, net); -// // Merge node with all inputs with fanout of 1 -// if (net->num_fanout_pins <= 1) { -// for (int i = 0; i < net->num_driver_pins; i++) { -// npin_t* driver = net->driver_pins[i]; -// if (driver->name != NULL && ((driver->node->type == MULTIPLY) || (driver->node->type == HARD_IP) || (driver->node->type == MEMORY) || (driver->node->type == ADD) || (driver->node->type == MINUS))) { -// vtr::free(driver->name); -// driver->name = vtr::strdup(node->name); -// } else { -// vtr::free(driver->node->name); -// driver->node->name = vtr::strdup(node->name); -// } -// } -// } -//} +static void merge_with_inputs(nnode_t* node, long pin_idx) { + oassert(pin_idx < node->num_input_pins); + oassert(node->type == OUTPUT_NODE); + nnet_t* net = node->input_pins[pin_idx]->net; + warn_undriven(node, net); + // Merge node with all inputs with fanout of 1 + if (net->num_fanout_pins <= 1) { + for (int i = 0; i < net->num_driver_pins; i++) { + npin_t* driver = net->driver_pins[i]; + if (driver->name != NULL && ((driver->node->type == MULTIPLY) || (driver->node->type == HARD_IP) || (driver->node->type == MEMORY) || (driver->node->type == ADD) || (driver->node->type == MINUS))) { + vtr::free(driver->name); + driver->name = vtr::strdup(node->name); + } else { + vtr::free(driver->node->name); + oassert(driver->node->num_output_pins == 1); + driver->node->name = vtr::strdup(node->name); + } + } + } +} static void print_net_driver(FILE* out, nnode_t* node, nnet_t* net, long driver_idx) { oassert(driver_idx < net->num_driver_pins); @@ -105,6 +106,7 @@ static void print_net_driver(FILE* out, nnode_t* node, nnet_t* net, long driver_ if (driver->name != NULL && ((driver->node->type == MULTIPLY) || (driver->node->type == HARD_IP) || (driver->node->type == MEMORY) || (driver->node->type == ADD) || (driver->node->type == MINUS))) { fprintf(out, " %s", driver->name); } else { + oassert(driver->node->num_output_pins == 1); fprintf(out, " %s", driver->node->name); } } @@ -133,21 +135,27 @@ static void print_output_pin(FILE* out, nnode_t* node) { fprintf(out, " %s", node->name); } +static char* buffer_multi_drivers(FILE* out, nnode_t* node, long pin_idx) +{ + nnet_t* net = node->input_pins[pin_idx]->net; + if (net->num_driver_pins > 1) { + char* name = op_node_name(BUF_NODE, node->name); + // Assign each driver to the implicit buffer + for (int j = 0; j < net->num_driver_pins; j++) { + fprintf(out, ".names"); + print_net_driver(out, node, net, j); + fprintf(out, " %s\n1 1\n\n", name); + } + return name; + } + return NULL; +} + static void print_dot_names_header(FILE* out, nnode_t* node) { char** names = (char**)vtr::calloc(node->num_input_pins, sizeof(char*)); - // Create an implicit buffer if there are multiple drivers to the component for (int i = 0; i < node->num_input_pins; i++) { - nnet_t* input_net = node->input_pins[i]->net; - if (input_net->num_driver_pins > 1) { - names[i] = op_node_name(BUF_NODE, node->name); - // Assign each driver to the implicit buffer - for (int j = 0; j < input_net->num_driver_pins; j++) { - fprintf(out, ".names"); - print_net_driver(out, node, input_net, j); - fprintf(out, " %s\n1 1\n\n", names[i]); - } - } + names[i] = buffer_multi_drivers(out, node, i); } // Print the actual header @@ -221,14 +229,13 @@ void output_blif(FILE* out, netlist_t* netlist) { fprintf(out, "\n.names gnd\n.names unconn\n.names vcc\n1\n"); fprintf(out, "\n"); - // TODO Uncomment this for In Outs // connect all the outputs up to the last gate - // for (long i = 0; i < netlist->num_top_output_nodes; i++) { - // nnode_t* node = netlist->top_output_nodes[i]; - // for (int j = 0; j < node->num_input_pins; j++) { - // merge_with_inputs(node, j); - // } - // } + for (long i = 0; i < netlist->num_top_output_nodes; i++) { + nnode_t* node = netlist->top_output_nodes[i]; + for (int j = 0; j < node->num_input_pins; j++) { + merge_with_inputs(node, j); + } + } /* traverse the internals of the flat net-list */ if (strcmp(configuration.output_type.c_str(), "blif") == 0) { @@ -240,9 +247,7 @@ void output_blif(FILE* out, netlist_t* netlist) { /* connect all the outputs up to the last gate */ for (long i = 0; i < netlist->num_top_output_nodes; i++) { nnode_t* node = netlist->top_output_nodes[i]; - - // TODO Change this to > 1 for In Outs - if (node->input_pins[0]->net->num_fanout_pins > 0) { + if (node->input_pins[0]->net->num_fanout_pins > 1) { nnet_t* net = node->input_pins[0]->net; warn_undriven(node, net); for (int j = 0; j < net->num_driver_pins; j++) { @@ -541,14 +546,18 @@ void define_ff(nnode_t* node, FILE* out) { // grab the edge sensitivity of the flip flop const char* edge_type_str = edge_type_blif_str(node); - std::string input; - std::string output; - std::string clock_driver; + char* input_driver = buffer_multi_drivers(out, node, 0); fprintf(out, ".latch"); /* input */ - print_input_single_driver(out, node, 0); + if(!input_driver) + print_input_single_driver(out, node, 0); + else { + // Use the implicit buffer we created before + fprintf(out, " %s", input_driver); + vtr::free(input_driver); + } /* output */ print_output_pin(out, node); @@ -556,6 +565,7 @@ void define_ff(nnode_t* node, FILE* out) { /* sensitivity */ fprintf(out, " %s", edge_type_str); + // TODO Should clocks support mutliple drivers? /* clock */ print_input_single_driver(out, node, 1); diff --git a/ODIN_II/regression_test/benchmark/task/FIR/simulation_result.json b/ODIN_II/regression_test/benchmark/task/FIR/simulation_result.json index d97cef60685..ce6d18202eb 100644 --- a/ODIN_II/regression_test/benchmark/task/FIR/simulation_result.json +++ b/ODIN_II/regression_test/benchmark/task/FIR/simulation_result.json @@ -10,13 +10,13 @@ "Latch Drivers": 1, "Pi": 12, "Po": 29, - "logic element": 1876, + "logic element": 1847, "latch": 2105, "generic logic size": 6, - "Longest Path": 166, - "Average Path": 5, - "Estimated LUTs": 1876, - "Total Node": 3982 + "Longest Path": 165, + "Average Path": 4, + "Estimated LUTs": 1847, + "Total Node": 3953 }, "FIR/ex1BT16_fir_20/k6_N10_mem32K_40nm": { "test_name": "FIR/ex1BT16_fir_20/k6_N10_mem32K_40nm", @@ -29,13 +29,13 @@ "Latch Drivers": 1, "Pi": 12, "Po": 29, - "logic element": 1876, + "logic element": 1847, "latch": 2105, "generic logic size": 6, - "Longest Path": 166, - "Average Path": 5, - "Estimated LUTs": 1876, - "Total Node": 3982 + "Longest Path": 165, + "Average Path": 4, + "Estimated LUTs": 1847, + "Total Node": 3953 }, "FIR/ex1BT16_fir_20/no_arch": { "test_name": "FIR/ex1BT16_fir_20/no_arch", @@ -47,12 +47,12 @@ "Latch Drivers": 1, "Pi": 12, "Po": 29, - "logic element": 1876, + "logic element": 1847, "latch": 2105, - "Longest Path": 166, - "Average Path": 5, - "Estimated LUTs": 1876, - "Total Node": 3982 + "Longest Path": 165, + "Average Path": 4, + "Estimated LUTs": 1847, + "Total Node": 3953 }, "FIR/ex1EP16_fir_6/k6_N10_40nm": { "test_name": "FIR/ex1EP16_fir_6/k6_N10_40nm", @@ -65,13 +65,13 @@ "Latch Drivers": 1, "Pi": 12, "Po": 29, - "logic element": 608, + "logic element": 579, "latch": 688, "generic logic size": 6, - "Longest Path": 112, - "Average Path": 5, - "Estimated LUTs": 608, - "Total Node": 1297 + "Longest Path": 111, + "Average Path": 4, + "Estimated LUTs": 579, + "Total Node": 1268 }, "FIR/ex1EP16_fir_6/k6_N10_mem32K_40nm": { "test_name": "FIR/ex1EP16_fir_6/k6_N10_mem32K_40nm", @@ -84,13 +84,13 @@ "Latch Drivers": 1, "Pi": 12, "Po": 29, - "logic element": 608, + "logic element": 579, "latch": 688, "generic logic size": 6, - "Longest Path": 112, - "Average Path": 5, - "Estimated LUTs": 608, - "Total Node": 1297 + "Longest Path": 111, + "Average Path": 4, + "Estimated LUTs": 579, + "Total Node": 1268 }, "FIR/ex1EP16_fir_6/no_arch": { "test_name": "FIR/ex1EP16_fir_6/no_arch", @@ -102,12 +102,12 @@ "Latch Drivers": 1, "Pi": 12, "Po": 29, - "logic element": 608, + "logic element": 579, "latch": 688, - "Longest Path": 112, - "Average Path": 5, - "Estimated LUTs": 608, - "Total Node": 1297 + "Longest Path": 111, + "Average Path": 4, + "Estimated LUTs": 579, + "Total Node": 1268 }, "FIR/ex1LS16_fir_41/k6_N10_40nm": { "test_name": "FIR/ex1LS16_fir_41/k6_N10_40nm", @@ -120,13 +120,13 @@ "Latch Drivers": 1, "Pi": 12, "Po": 29, - "logic element": 4196, + "logic element": 4167, "latch": 5430, "generic logic size": 6, - "Longest Path": 189, - "Average Path": 5, - "Estimated LUTs": 4196, - "Total Node": 9627 + "Longest Path": 188, + "Average Path": 4, + "Estimated LUTs": 4167, + "Total Node": 9598 }, "FIR/ex1LS16_fir_41/k6_N10_mem32K_40nm": { "test_name": "FIR/ex1LS16_fir_41/k6_N10_mem32K_40nm", @@ -139,13 +139,13 @@ "Latch Drivers": 1, "Pi": 12, "Po": 29, - "logic element": 4196, + "logic element": 4167, "latch": 5430, "generic logic size": 6, - "Longest Path": 189, - "Average Path": 5, - "Estimated LUTs": 4196, - "Total Node": 9627 + "Longest Path": 188, + "Average Path": 4, + "Estimated LUTs": 4167, + "Total Node": 9598 }, "FIR/ex1LS16_fir_41/no_arch": { "test_name": "FIR/ex1LS16_fir_41/no_arch", @@ -157,12 +157,12 @@ "Latch Drivers": 1, "Pi": 12, "Po": 29, - "logic element": 4196, + "logic element": 4167, "latch": 5430, - "Longest Path": 189, - "Average Path": 5, - "Estimated LUTs": 4196, - "Total Node": 9627 + "Longest Path": 188, + "Average Path": 4, + "Estimated LUTs": 4167, + "Total Node": 9598 }, "FIR/ex1PM16_fir_28/k6_N10_40nm": { "test_name": "FIR/ex1PM16_fir_28/k6_N10_40nm", @@ -175,13 +175,13 @@ "Latch Drivers": 1, "Pi": 12, "Po": 29, - "logic element": 2905, + "logic element": 2876, "latch": 3223, "generic logic size": 6, - "Longest Path": 190, - "Average Path": 5, - "Estimated LUTs": 2905, - "Total Node": 6129 + "Longest Path": 189, + "Average Path": 4, + "Estimated LUTs": 2876, + "Total Node": 6100 }, "FIR/ex1PM16_fir_28/k6_N10_mem32K_40nm": { "test_name": "FIR/ex1PM16_fir_28/k6_N10_mem32K_40nm", @@ -194,13 +194,13 @@ "Latch Drivers": 1, "Pi": 12, "Po": 29, - "logic element": 2905, + "logic element": 2876, "latch": 3223, "generic logic size": 6, - "Longest Path": 190, - "Average Path": 5, - "Estimated LUTs": 2905, - "Total Node": 6129 + "Longest Path": 189, + "Average Path": 4, + "Estimated LUTs": 2876, + "Total Node": 6100 }, "FIR/ex1PM16_fir_28/no_arch": { "test_name": "FIR/ex1PM16_fir_28/no_arch", @@ -212,12 +212,12 @@ "Latch Drivers": 1, "Pi": 12, "Po": 29, - "logic element": 2905, + "logic element": 2876, "latch": 3223, - "Longest Path": 190, - "Average Path": 5, - "Estimated LUTs": 2905, - "Total Node": 6129 + "Longest Path": 189, + "Average Path": 4, + "Estimated LUTs": 2876, + "Total Node": 6100 }, "FIR/ex2BT16_fir_71/k6_N10_40nm": { "test_name": "FIR/ex2BT16_fir_71/k6_N10_40nm", @@ -230,13 +230,13 @@ "Latch Drivers": 1, "Pi": 12, "Po": 29, - "logic element": 5326, + "logic element": 5297, "latch": 5906, "generic logic size": 6, - "Longest Path": 243, - "Average Path": 5, - "Estimated LUTs": 5326, - "Total Node": 11233 + "Longest Path": 242, + "Average Path": 4, + "Estimated LUTs": 5297, + "Total Node": 11204 }, "FIR/ex2BT16_fir_71/k6_N10_mem32K_40nm": { "test_name": "FIR/ex2BT16_fir_71/k6_N10_mem32K_40nm", @@ -249,13 +249,13 @@ "Latch Drivers": 1, "Pi": 12, "Po": 29, - "logic element": 5326, + "logic element": 5297, "latch": 5906, "generic logic size": 6, - "Longest Path": 243, - "Average Path": 5, - "Estimated LUTs": 5326, - "Total Node": 11233 + "Longest Path": 242, + "Average Path": 4, + "Estimated LUTs": 5297, + "Total Node": 11204 }, "FIR/ex2BT16_fir_71/no_arch": { "test_name": "FIR/ex2BT16_fir_71/no_arch", @@ -267,12 +267,12 @@ "Latch Drivers": 1, "Pi": 12, "Po": 29, - "logic element": 5326, + "logic element": 5297, "latch": 5906, - "Longest Path": 243, - "Average Path": 5, - "Estimated LUTs": 5326, - "Total Node": 11233 + "Longest Path": 242, + "Average Path": 4, + "Estimated LUTs": 5297, + "Total Node": 11204 }, "FIR/ex2EP16_fir_13/k6_N10_40nm": { "test_name": "FIR/ex2EP16_fir_13/k6_N10_40nm", @@ -285,13 +285,13 @@ "Latch Drivers": 1, "Pi": 12, "Po": 29, - "logic element": 937, + "logic element": 908, "latch": 873, "generic logic size": 6, - "Longest Path": 129, - "Average Path": 5, - "Estimated LUTs": 937, - "Total Node": 1811 + "Longest Path": 128, + "Average Path": 4, + "Estimated LUTs": 908, + "Total Node": 1782 }, "FIR/ex2EP16_fir_13/k6_N10_mem32K_40nm": { "test_name": "FIR/ex2EP16_fir_13/k6_N10_mem32K_40nm", @@ -304,13 +304,13 @@ "Latch Drivers": 1, "Pi": 12, "Po": 29, - "logic element": 937, + "logic element": 908, "latch": 873, "generic logic size": 6, - "Longest Path": 129, - "Average Path": 5, - "Estimated LUTs": 937, - "Total Node": 1811 + "Longest Path": 128, + "Average Path": 4, + "Estimated LUTs": 908, + "Total Node": 1782 }, "FIR/ex2EP16_fir_13/no_arch": { "test_name": "FIR/ex2EP16_fir_13/no_arch", @@ -322,12 +322,12 @@ "Latch Drivers": 1, "Pi": 12, "Po": 29, - "logic element": 937, + "logic element": 908, "latch": 873, - "Longest Path": 129, - "Average Path": 5, - "Estimated LUTs": 937, - "Total Node": 1811 + "Longest Path": 128, + "Average Path": 4, + "Estimated LUTs": 908, + "Total Node": 1782 }, "FIR/ex2PM16_fir_119/k6_N10_40nm": { "test_name": "FIR/ex2PM16_fir_119/k6_N10_40nm", @@ -340,13 +340,13 @@ "Latch Drivers": 1, "Pi": 12, "Po": 29, - "logic element": 11426, + "logic element": 11397, "latch": 15211, "generic logic size": 6, - "Longest Path": 431, - "Average Path": 5, - "Estimated LUTs": 11426, - "Total Node": 26638 + "Longest Path": 430, + "Average Path": 4, + "Estimated LUTs": 11397, + "Total Node": 26609 }, "FIR/ex2PM16_fir_119/k6_N10_mem32K_40nm": { "test_name": "FIR/ex2PM16_fir_119/k6_N10_mem32K_40nm", @@ -359,13 +359,13 @@ "Latch Drivers": 1, "Pi": 12, "Po": 29, - "logic element": 11426, + "logic element": 11397, "latch": 15211, "generic logic size": 6, - "Longest Path": 431, - "Average Path": 5, - "Estimated LUTs": 11426, - "Total Node": 26638 + "Longest Path": 430, + "Average Path": 4, + "Estimated LUTs": 11397, + "Total Node": 26609 }, "FIR/ex2PM16_fir_119/no_arch": { "test_name": "FIR/ex2PM16_fir_119/no_arch", @@ -377,12 +377,12 @@ "Latch Drivers": 1, "Pi": 12, "Po": 29, - "logic element": 11426, + "logic element": 11397, "latch": 15211, - "Longest Path": 431, - "Average Path": 5, - "Estimated LUTs": 11426, - "Total Node": 26638 + "Longest Path": 430, + "Average Path": 4, + "Estimated LUTs": 11397, + "Total Node": 26609 }, "FIR/ex3PM16_fir_61/k6_N10_40nm": { "test_name": "FIR/ex3PM16_fir_61/k6_N10_40nm", @@ -395,13 +395,13 @@ "Latch Drivers": 1, "Pi": 12, "Po": 29, - "logic element": 6159, + "logic element": 6130, "latch": 8296, "generic logic size": 6, - "Longest Path": 254, - "Average Path": 5, - "Estimated LUTs": 6159, - "Total Node": 14456 + "Longest Path": 253, + "Average Path": 4, + "Estimated LUTs": 6130, + "Total Node": 14427 }, "FIR/ex3PM16_fir_61/k6_N10_mem32K_40nm": { "test_name": "FIR/ex3PM16_fir_61/k6_N10_mem32K_40nm", @@ -414,13 +414,13 @@ "Latch Drivers": 1, "Pi": 12, "Po": 29, - "logic element": 6159, + "logic element": 6130, "latch": 8296, "generic logic size": 6, - "Longest Path": 254, - "Average Path": 5, - "Estimated LUTs": 6159, - "Total Node": 14456 + "Longest Path": 253, + "Average Path": 4, + "Estimated LUTs": 6130, + "Total Node": 14427 }, "FIR/ex3PM16_fir_61/no_arch": { "test_name": "FIR/ex3PM16_fir_61/no_arch", @@ -432,12 +432,12 @@ "Latch Drivers": 1, "Pi": 12, "Po": 29, - "logic element": 6159, + "logic element": 6130, "latch": 8296, - "Longest Path": 254, - "Average Path": 5, - "Estimated LUTs": 6159, - "Total Node": 14456 + "Longest Path": 253, + "Average Path": 4, + "Estimated LUTs": 6130, + "Total Node": 14427 }, "FIR/ex4EP16_fir_10/k6_N10_40nm": { "test_name": "FIR/ex4EP16_fir_10/k6_N10_40nm", @@ -450,13 +450,13 @@ "Latch Drivers": 1, "Pi": 12, "Po": 29, - "logic element": 1100, + "logic element": 1071, "latch": 1239, "generic logic size": 6, - "Longest Path": 136, - "Average Path": 5, - "Estimated LUTs": 1100, - "Total Node": 2340 + "Longest Path": 135, + "Average Path": 4, + "Estimated LUTs": 1071, + "Total Node": 2311 }, "FIR/ex4EP16_fir_10/k6_N10_mem32K_40nm": { "test_name": "FIR/ex4EP16_fir_10/k6_N10_mem32K_40nm", @@ -469,13 +469,13 @@ "Latch Drivers": 1, "Pi": 12, "Po": 29, - "logic element": 1100, + "logic element": 1071, "latch": 1239, "generic logic size": 6, - "Longest Path": 136, - "Average Path": 5, - "Estimated LUTs": 1100, - "Total Node": 2340 + "Longest Path": 135, + "Average Path": 4, + "Estimated LUTs": 1071, + "Total Node": 2311 }, "FIR/ex4EP16_fir_10/no_arch": { "test_name": "FIR/ex4EP16_fir_10/no_arch", @@ -487,12 +487,12 @@ "Latch Drivers": 1, "Pi": 12, "Po": 29, - "logic element": 1100, + "logic element": 1071, "latch": 1239, - "Longest Path": 136, - "Average Path": 5, - "Estimated LUTs": 1100, - "Total Node": 2340 + "Longest Path": 135, + "Average Path": 4, + "Estimated LUTs": 1071, + "Total Node": 2311 }, "FIR/ex4LS16_fir/k6_N10_40nm": { "test_name": "FIR/ex4LS16_fir/k6_N10_40nm", @@ -505,13 +505,13 @@ "Latch Drivers": 1, "Pi": 12, "Po": 29, - "logic element": 20458, + "logic element": 20429, "latch": 30814, "generic logic size": 6, - "Longest Path": 800, - "Average Path": 5, - "Estimated LUTs": 20458, - "Total Node": 51273 + "Longest Path": 799, + "Average Path": 4, + "Estimated LUTs": 20429, + "Total Node": 51244 }, "FIR/ex4LS16_fir/k6_N10_mem32K_40nm": { "test_name": "FIR/ex4LS16_fir/k6_N10_mem32K_40nm", @@ -524,13 +524,13 @@ "Latch Drivers": 1, "Pi": 12, "Po": 29, - "logic element": 20458, + "logic element": 20429, "latch": 30814, "generic logic size": 6, - "Longest Path": 800, - "Average Path": 5, - "Estimated LUTs": 20458, - "Total Node": 51273 + "Longest Path": 799, + "Average Path": 4, + "Estimated LUTs": 20429, + "Total Node": 51244 }, "FIR/ex4LS16_fir/no_arch": { "test_name": "FIR/ex4LS16_fir/no_arch", @@ -542,12 +542,12 @@ "Latch Drivers": 1, "Pi": 12, "Po": 29, - "logic element": 20458, + "logic element": 20429, "latch": 30814, - "Longest Path": 800, - "Average Path": 5, - "Estimated LUTs": 20458, - "Total Node": 51273 + "Longest Path": 799, + "Average Path": 4, + "Estimated LUTs": 20429, + "Total Node": 51244 }, "FIR/ex4PM16_fir_152/k6_N10_40nm": { "test_name": "FIR/ex4PM16_fir_152/k6_N10_40nm", @@ -560,13 +560,13 @@ "Latch Drivers": 1, "Pi": 12, "Po": 29, - "logic element": 14455, + "logic element": 14426, "latch": 19260, "generic logic size": 6, - "Longest Path": 533, - "Average Path": 5, - "Estimated LUTs": 14455, - "Total Node": 33716 + "Longest Path": 532, + "Average Path": 4, + "Estimated LUTs": 14426, + "Total Node": 33687 }, "FIR/ex4PM16_fir_152/k6_N10_mem32K_40nm": { "test_name": "FIR/ex4PM16_fir_152/k6_N10_mem32K_40nm", @@ -579,13 +579,13 @@ "Latch Drivers": 1, "Pi": 12, "Po": 29, - "logic element": 14455, + "logic element": 14426, "latch": 19260, "generic logic size": 6, - "Longest Path": 533, - "Average Path": 5, - "Estimated LUTs": 14455, - "Total Node": 33716 + "Longest Path": 532, + "Average Path": 4, + "Estimated LUTs": 14426, + "Total Node": 33687 }, "FIR/ex4PM16_fir_152/no_arch": { "test_name": "FIR/ex4PM16_fir_152/no_arch", @@ -597,12 +597,12 @@ "Latch Drivers": 1, "Pi": 12, "Po": 29, - "logic element": 14455, + "logic element": 14426, "latch": 19260, - "Longest Path": 533, - "Average Path": 5, - "Estimated LUTs": 14455, - "Total Node": 33716 + "Longest Path": 532, + "Average Path": 4, + "Estimated LUTs": 14426, + "Total Node": 33687 }, "DEFAULT": { "test_name": "n/a", diff --git a/ODIN_II/regression_test/benchmark/task/cmd_line_args/batch_simulation/simulation_result.json b/ODIN_II/regression_test/benchmark/task/cmd_line_args/batch_simulation/simulation_result.json index 65e99f880e6..dd7aea9c214 100644 --- a/ODIN_II/regression_test/benchmark/task/cmd_line_args/batch_simulation/simulation_result.json +++ b/ODIN_II/regression_test/benchmark/task/cmd_line_args/batch_simulation/simulation_result.json @@ -10,14 +10,14 @@ "Latch Drivers": 1, "Pi": 5, "Po": 5, - "logic element": 12, + "logic element": 8, "latch": 4, "Multiplier": 1, "generic logic size": 6, - "Longest Path": 8, - "Average Path": 5, - "Estimated LUTs": 12, - "Total Node": 18 + "Longest Path": 7, + "Average Path": 4, + "Estimated LUTs": 8, + "Total Node": 14 }, "DEFAULT": { "test_name": "n/a", diff --git a/ODIN_II/regression_test/benchmark/task/cmd_line_args/best_coverage/simulation_result.json b/ODIN_II/regression_test/benchmark/task/cmd_line_args/best_coverage/simulation_result.json index b5afbb3e0b9..9dd3015bc67 100644 --- a/ODIN_II/regression_test/benchmark/task/cmd_line_args/best_coverage/simulation_result.json +++ b/ODIN_II/regression_test/benchmark/task/cmd_line_args/best_coverage/simulation_result.json @@ -10,13 +10,13 @@ "Latch Drivers": 2, "Pi": 4, "Po": 4, - "logic element": 144, + "logic element": 140, "latch": 34, "generic logic size": 6, - "Longest Path": 27, - "Average Path": 5, - "Estimated LUTs": 250, - "Total Node": 180 + "Longest Path": 26, + "Average Path": 4, + "Estimated LUTs": 246, + "Total Node": 176 }, "DEFAULT": { "test_name": "n/a", diff --git a/ODIN_II/regression_test/benchmark/task/cmd_line_args/coverage/simulation_result.json b/ODIN_II/regression_test/benchmark/task/cmd_line_args/coverage/simulation_result.json index 12aa09bd2ee..7a65f671631 100644 --- a/ODIN_II/regression_test/benchmark/task/cmd_line_args/coverage/simulation_result.json +++ b/ODIN_II/regression_test/benchmark/task/cmd_line_args/coverage/simulation_result.json @@ -10,13 +10,13 @@ "Latch Drivers": 2, "Pi": 4, "Po": 4, - "logic element": 144, + "logic element": 140, "latch": 34, "generic logic size": 6, - "Longest Path": 27, - "Average Path": 5, - "Estimated LUTs": 250, - "Total Node": 180 + "Longest Path": 26, + "Average Path": 4, + "Estimated LUTs": 246, + "Total Node": 176 }, "coverage/multi_clock_reader_writer/k6_N10_mem32K_40nm": { "test_name": "coverage/multi_clock_reader_writer/k6_N10_mem32K_40nm", @@ -29,13 +29,13 @@ "Latch Drivers": 2, "Pi": 4, "Po": 4, - "logic element": 144, + "logic element": 140, "latch": 34, "generic logic size": 6, - "Longest Path": 27, - "Average Path": 5, - "Estimated LUTs": 250, - "Total Node": 180 + "Longest Path": 26, + "Average Path": 4, + "Estimated LUTs": 246, + "Total Node": 176 }, "coverage/multi_clock_reader_writer/no_arch": { "test_name": "coverage/multi_clock_reader_writer/no_arch", @@ -47,12 +47,12 @@ "Latch Drivers": 2, "Pi": 4, "Po": 4, - "logic element": 144, + "logic element": 140, "latch": 34, - "Longest Path": 27, - "Average Path": 5, - "Estimated LUTs": 144, - "Total Node": 180 + "Longest Path": 26, + "Average Path": 4, + "Estimated LUTs": 140, + "Total Node": 176 }, "DEFAULT": { "test_name": "n/a", diff --git a/ODIN_II/regression_test/benchmark/task/cmd_line_args/parallel_simulation/simulation_result.json b/ODIN_II/regression_test/benchmark/task/cmd_line_args/parallel_simulation/simulation_result.json index 6b325803a3b..70d15ea6a1d 100644 --- a/ODIN_II/regression_test/benchmark/task/cmd_line_args/parallel_simulation/simulation_result.json +++ b/ODIN_II/regression_test/benchmark/task/cmd_line_args/parallel_simulation/simulation_result.json @@ -10,14 +10,14 @@ "Latch Drivers": 1, "Pi": 5, "Po": 5, - "logic element": 12, + "logic element": 8, "latch": 4, "Multiplier": 1, "generic logic size": 6, - "Longest Path": 8, - "Average Path": 5, - "Estimated LUTs": 12, - "Total Node": 18 + "Longest Path": 7, + "Average Path": 4, + "Estimated LUTs": 8, + "Total Node": 14 }, "DEFAULT": { "test_name": "n/a", diff --git a/ODIN_II/regression_test/benchmark/task/full/simulation_result.json b/ODIN_II/regression_test/benchmark/task/full/simulation_result.json index 3900852f639..3406a90af76 100644 --- a/ODIN_II/regression_test/benchmark/task/full/simulation_result.json +++ b/ODIN_II/regression_test/benchmark/task/full/simulation_result.json @@ -143,14 +143,14 @@ "Latch Drivers": 1, "Pi": 13, "Po": 12, - "logic element": 32, + "logic element": 28, "latch": 12, "Memory": 4, "generic logic size": 4, - "Longest Path": 12, - "Average Path": 5, - "Estimated LUTs": 32, - "Total Node": 49 + "Longest Path": 11, + "Average Path": 4, + "Estimated LUTs": 28, + "Total Node": 45 }, "full/bm_sfifo_rtl/k6_frac_N10_frac_chain_mem32K_40nm": { "test_name": "full/bm_sfifo_rtl/k6_frac_N10_frac_chain_mem32K_40nm", @@ -433,7 +433,7 @@ "Latch Drivers": 1, "Pi": 35, "Po": 356, - "logic element": 184389, + "logic element": 184388, "latch": 56235, "Adder": 24448, "Multiplier": 27, @@ -441,8 +441,8 @@ "generic logic size": 4, "Longest Path": 25520, "Average Path": 5, - "Estimated LUTs": 194394, - "Total Node": 265448 + "Estimated LUTs": 194393, + "Total Node": 265447 }, "full/memory_controller/k6_frac_N10_frac_chain_mem32K_40nm": { "test_name": "full/memory_controller/k6_frac_N10_frac_chain_mem32K_40nm", @@ -455,14 +455,12 @@ "Latch Drivers": 1, "Pi": 18, "Po": 12, - "logic element": 12, "latch": 12, "Memory": 8, "generic logic size": 4, - "Longest Path": 5, + "Longest Path": 4, "Average Path": 4, - "Estimated LUTs": 12, - "Total Node": 33 + "Total Node": 21 }, "full/mkPktMerge/k6_frac_N10_frac_chain_mem32K_40nm": { "test_name": "full/mkPktMerge/k6_frac_N10_frac_chain_mem32K_40nm", @@ -557,15 +555,15 @@ "Latch Drivers": 1, "Pi": 92, "Po": 104, - "logic element": 16141, + "logic element": 16119, "latch": 13495, "Adder": 2920, "Memory": 1024, "generic logic size": 4, - "Longest Path": 203, + "Longest Path": 202, "Average Path": 5, - "Estimated LUTs": 22348, - "Total Node": 33581 + "Estimated LUTs": 22326, + "Total Node": 33559 }, "full/stereovision1/k6_frac_N10_frac_chain_mem32K_40nm": { "test_name": "full/stereovision1/k6_frac_N10_frac_chain_mem32K_40nm", @@ -578,15 +576,15 @@ "Latch Drivers": 1, "Pi": 132, "Po": 145, - "logic element": 13812, + "logic element": 13761, "latch": 11789, "Adder": 2388, "Multiplier": 152, "generic logic size": 4, - "Longest Path": 211, + "Longest Path": 210, "Average Path": 5, - "Estimated LUTs": 20744, - "Total Node": 28142 + "Estimated LUTs": 20693, + "Total Node": 28091 }, "full/stereovision2/k6_frac_N10_frac_chain_mem32K_40nm": { "test_name": "full/stereovision2/k6_frac_N10_frac_chain_mem32K_40nm", @@ -599,15 +597,15 @@ "Latch Drivers": 1, "Pi": 148, "Po": 182, - "logic element": 12100, + "logic element": 12012, "latch": 18416, "Adder": 14347, "Multiplier": 540, "generic logic size": 4, - "Longest Path": 145, + "Longest Path": 144, "Average Path": 5, - "Estimated LUTs": 14489, - "Total Node": 45404 + "Estimated LUTs": 14401, + "Total Node": 45316 }, "full/stereovision3/k6_frac_N10_frac_chain_mem32K_40nm": { "test_name": "full/stereovision3/k6_frac_N10_frac_chain_mem32K_40nm", @@ -620,14 +618,14 @@ "Latch Drivers": 2, "Pi": 9, "Po": 30, - "logic element": 1256, + "logic element": 1254, "latch": 102, "Adder": 28, "generic logic size": 4, "Longest Path": 64, "Average Path": 6, - "Estimated LUTs": 2083, - "Total Node": 1388 + "Estimated LUTs": 2081, + "Total Node": 1386 }, "DEFAULT": { "test_name": "n/a", diff --git a/ODIN_II/regression_test/benchmark/task/keywords/always/simulation_result.json b/ODIN_II/regression_test/benchmark/task/keywords/always/simulation_result.json index af9e3906b2f..259b569d25e 100644 --- a/ODIN_II/regression_test/benchmark/task/keywords/always/simulation_result.json +++ b/ODIN_II/regression_test/benchmark/task/keywords/always/simulation_result.json @@ -24,12 +24,10 @@ "Latch Drivers": 1, "Pi": 1, "Po": 1, - "logic element": 1, "latch": 1, - "Longest Path": 4, - "Average Path": 4, - "Estimated LUTs": 1, - "Total Node": 3 + "Longest Path": 3, + "Average Path": 3, + "Total Node": 2 }, "always/always_clk/no_arch": { "test_name": "always/always_clk/no_arch", diff --git a/ODIN_II/regression_test/benchmark/task/keywords/and/simulation_result.json b/ODIN_II/regression_test/benchmark/task/keywords/and/simulation_result.json index bd115c7fc64..285fb6d9173 100644 --- a/ODIN_II/regression_test/benchmark/task/keywords/and/simulation_result.json +++ b/ODIN_II/regression_test/benchmark/task/keywords/and/simulation_result.json @@ -8,11 +8,11 @@ "test_coverage(%)": 100, "Pi": 4, "Po": 2, - "logic element": 4, - "Longest Path": 4, - "Average Path": 4, - "Estimated LUTs": 4, - "Total Node": 4 + "logic element": 2, + "Longest Path": 3, + "Average Path": 3, + "Estimated LUTs": 2, + "Total Node": 2 }, "and/and_wire/no_arch": { "test_name": "and/and_wire/no_arch", @@ -23,11 +23,11 @@ "test_coverage(%)": 100, "Pi": 2, "Po": 1, - "logic element": 2, - "Longest Path": 4, - "Average Path": 4, - "Estimated LUTs": 2, - "Total Node": 2 + "logic element": 1, + "Longest Path": 3, + "Average Path": 3, + "Estimated LUTs": 1, + "Total Node": 1 }, "DEFAULT": { "test_name": "n/a", diff --git a/ODIN_II/regression_test/benchmark/task/keywords/begin_end/simulation_result.json b/ODIN_II/regression_test/benchmark/task/keywords/begin_end/simulation_result.json index 605366b1123..de3f000fbd9 100644 --- a/ODIN_II/regression_test/benchmark/task/keywords/begin_end/simulation_result.json +++ b/ODIN_II/regression_test/benchmark/task/keywords/begin_end/simulation_result.json @@ -41,12 +41,10 @@ "Latch Drivers": 1, "Pi": 1, "Po": 1, - "logic element": 1, "latch": 1, - "Longest Path": 4, - "Average Path": 4, - "Estimated LUTs": 1, - "Total Node": 3 + "Longest Path": 3, + "Average Path": 3, + "Total Node": 2 }, "DEFAULT": { "test_name": "n/a", diff --git a/ODIN_II/regression_test/benchmark/task/keywords/defparam/simulation_result.json b/ODIN_II/regression_test/benchmark/task/keywords/defparam/simulation_result.json index d8baf7118c4..e6151116ccd 100644 --- a/ODIN_II/regression_test/benchmark/task/keywords/defparam/simulation_result.json +++ b/ODIN_II/regression_test/benchmark/task/keywords/defparam/simulation_result.json @@ -50,12 +50,10 @@ "test_coverage(%)": 100, "Latch Drivers": 1, "Po": 1, - "logic element": 1, "latch": 1, - "Longest Path": 4, - "Average Path": 4, - "Estimated LUTs": 1, - "Total Node": 3 + "Longest Path": 3, + "Average Path": 3, + "Total Node": 2 }, "defparam/defparam_depth_1_failure/no_arch": { "test_name": "defparam/defparam_depth_1_failure/no_arch", diff --git a/ODIN_II/regression_test/benchmark/task/keywords/nand/simulation_result.json b/ODIN_II/regression_test/benchmark/task/keywords/nand/simulation_result.json index 773f879c443..80c8933e76d 100644 --- a/ODIN_II/regression_test/benchmark/task/keywords/nand/simulation_result.json +++ b/ODIN_II/regression_test/benchmark/task/keywords/nand/simulation_result.json @@ -8,11 +8,11 @@ "test_coverage(%)": 100, "Pi": 4, "Po": 2, - "logic element": 4, - "Longest Path": 4, - "Average Path": 4, - "Estimated LUTs": 4, - "Total Node": 4 + "logic element": 2, + "Longest Path": 3, + "Average Path": 3, + "Estimated LUTs": 2, + "Total Node": 2 }, "DEFAULT": { "test_name": "n/a", diff --git a/ODIN_II/regression_test/benchmark/task/keywords/negedge/simulation_result.json b/ODIN_II/regression_test/benchmark/task/keywords/negedge/simulation_result.json index 2b7603a4df5..2c525eccfc2 100644 --- a/ODIN_II/regression_test/benchmark/task/keywords/negedge/simulation_result.json +++ b/ODIN_II/regression_test/benchmark/task/keywords/negedge/simulation_result.json @@ -9,12 +9,10 @@ "Latch Drivers": 1, "Pi": 1, "Po": 1, - "logic element": 1, "latch": 1, - "Longest Path": 4, - "Average Path": 4, - "Estimated LUTs": 1, - "Total Node": 3 + "Longest Path": 3, + "Average Path": 3, + "Total Node": 2 }, "DEFAULT": { "test_name": "n/a", diff --git a/ODIN_II/regression_test/benchmark/task/keywords/nor/simulation_result.json b/ODIN_II/regression_test/benchmark/task/keywords/nor/simulation_result.json index 96d5f6a07bd..f9a2b247972 100644 --- a/ODIN_II/regression_test/benchmark/task/keywords/nor/simulation_result.json +++ b/ODIN_II/regression_test/benchmark/task/keywords/nor/simulation_result.json @@ -8,11 +8,11 @@ "test_coverage(%)": 100, "Pi": 4, "Po": 2, - "logic element": 4, - "Longest Path": 4, - "Average Path": 4, - "Estimated LUTs": 4, - "Total Node": 4 + "logic element": 2, + "Longest Path": 3, + "Average Path": 3, + "Estimated LUTs": 2, + "Total Node": 2 }, "nor/nor_wire/no_arch": { "test_name": "nor/nor_wire/no_arch", @@ -23,11 +23,11 @@ "test_coverage(%)": 100, "Pi": 2, "Po": 1, - "logic element": 2, - "Longest Path": 4, - "Average Path": 4, - "Estimated LUTs": 2, - "Total Node": 2 + "logic element": 1, + "Longest Path": 3, + "Average Path": 3, + "Estimated LUTs": 1, + "Total Node": 1 }, "DEFAULT": { "test_name": "n/a", diff --git a/ODIN_II/regression_test/benchmark/task/keywords/not/simulation_result.json b/ODIN_II/regression_test/benchmark/task/keywords/not/simulation_result.json index 8213fd161b9..7435ef62e1f 100644 --- a/ODIN_II/regression_test/benchmark/task/keywords/not/simulation_result.json +++ b/ODIN_II/regression_test/benchmark/task/keywords/not/simulation_result.json @@ -8,11 +8,11 @@ "test_coverage(%)": 100, "Pi": 2, "Po": 2, - "logic element": 4, - "Longest Path": 4, - "Average Path": 4, - "Estimated LUTs": 4, - "Total Node": 4 + "logic element": 2, + "Longest Path": 3, + "Average Path": 3, + "Estimated LUTs": 2, + "Total Node": 2 }, "not/not_wire/no_arch": { "test_name": "not/not_wire/no_arch", @@ -23,11 +23,11 @@ "test_coverage(%)": 100, "Pi": 1, "Po": 1, - "logic element": 2, - "Longest Path": 4, - "Average Path": 4, - "Estimated LUTs": 2, - "Total Node": 2 + "logic element": 1, + "Longest Path": 3, + "Average Path": 3, + "Estimated LUTs": 1, + "Total Node": 1 }, "DEFAULT": { "test_name": "n/a", diff --git a/ODIN_II/regression_test/benchmark/task/keywords/or/simulation_result.json b/ODIN_II/regression_test/benchmark/task/keywords/or/simulation_result.json index 99d4f5e0c61..5b128de80ea 100644 --- a/ODIN_II/regression_test/benchmark/task/keywords/or/simulation_result.json +++ b/ODIN_II/regression_test/benchmark/task/keywords/or/simulation_result.json @@ -8,11 +8,11 @@ "test_coverage(%)": 100, "Pi": 4, "Po": 2, - "logic element": 4, - "Longest Path": 4, - "Average Path": 4, - "Estimated LUTs": 4, - "Total Node": 4 + "logic element": 2, + "Longest Path": 3, + "Average Path": 3, + "Estimated LUTs": 2, + "Total Node": 2 }, "or/or_wire/no_arch": { "test_name": "or/or_wire/no_arch", @@ -23,11 +23,11 @@ "test_coverage(%)": 100, "Pi": 2, "Po": 1, - "logic element": 2, - "Longest Path": 4, - "Average Path": 4, - "Estimated LUTs": 2, - "Total Node": 2 + "logic element": 1, + "Longest Path": 3, + "Average Path": 3, + "Estimated LUTs": 1, + "Total Node": 1 }, "DEFAULT": { "test_name": "n/a", diff --git a/ODIN_II/regression_test/benchmark/task/keywords/posedge/simulation_result.json b/ODIN_II/regression_test/benchmark/task/keywords/posedge/simulation_result.json index 8570b8688cd..585bfa88c7d 100644 --- a/ODIN_II/regression_test/benchmark/task/keywords/posedge/simulation_result.json +++ b/ODIN_II/regression_test/benchmark/task/keywords/posedge/simulation_result.json @@ -9,12 +9,10 @@ "Latch Drivers": 1, "Pi": 1, "Po": 1, - "logic element": 1, "latch": 1, - "Longest Path": 4, - "Average Path": 4, - "Estimated LUTs": 1, - "Total Node": 3 + "Longest Path": 3, + "Average Path": 3, + "Total Node": 2 }, "DEFAULT": { "test_name": "n/a", diff --git a/ODIN_II/regression_test/benchmark/task/keywords/specparam/simulation_result.json b/ODIN_II/regression_test/benchmark/task/keywords/specparam/simulation_result.json index 35662bd4c73..6148f062fb2 100644 --- a/ODIN_II/regression_test/benchmark/task/keywords/specparam/simulation_result.json +++ b/ODIN_II/regression_test/benchmark/task/keywords/specparam/simulation_result.json @@ -5,14 +5,14 @@ "max_rss(MiB)": 14.8, "exec_time(ms)": 2.9, "simulation_time(ms)": 0.2, - "test_coverage(%)": 66.7, + "test_coverage(%)": 75, "Pi": 2, "Po": 1, - "logic element": 2, - "Longest Path": 4, - "Average Path": 4, - "Estimated LUTs": 2, - "Total Node": 2 + "logic element": 1, + "Longest Path": 3, + "Average Path": 3, + "Estimated LUTs": 1, + "Total Node": 1 }, "DEFAULT": { "test_name": "n/a", diff --git a/ODIN_II/regression_test/benchmark/task/keywords/xnor/simulation_result.json b/ODIN_II/regression_test/benchmark/task/keywords/xnor/simulation_result.json index 8524accc33d..8063deb1586 100644 --- a/ODIN_II/regression_test/benchmark/task/keywords/xnor/simulation_result.json +++ b/ODIN_II/regression_test/benchmark/task/keywords/xnor/simulation_result.json @@ -8,11 +8,11 @@ "test_coverage(%)": 100, "Pi": 4, "Po": 2, - "logic element": 4, - "Longest Path": 4, - "Average Path": 4, - "Estimated LUTs": 4, - "Total Node": 4 + "logic element": 2, + "Longest Path": 3, + "Average Path": 3, + "Estimated LUTs": 2, + "Total Node": 2 }, "xnor/xnor_wire/no_arch": { "test_name": "xnor/xnor_wire/no_arch", @@ -23,11 +23,11 @@ "test_coverage(%)": 100, "Pi": 2, "Po": 1, - "logic element": 2, - "Longest Path": 4, - "Average Path": 4, - "Estimated LUTs": 2, - "Total Node": 2 + "logic element": 1, + "Longest Path": 3, + "Average Path": 3, + "Estimated LUTs": 1, + "Total Node": 1 }, "DEFAULT": { "test_name": "n/a", diff --git a/ODIN_II/regression_test/benchmark/task/keywords/xor/simulation_result.json b/ODIN_II/regression_test/benchmark/task/keywords/xor/simulation_result.json index ae7d8da2dbc..f2f9c1e573d 100644 --- a/ODIN_II/regression_test/benchmark/task/keywords/xor/simulation_result.json +++ b/ODIN_II/regression_test/benchmark/task/keywords/xor/simulation_result.json @@ -8,11 +8,11 @@ "test_coverage(%)": 100, "Pi": 4, "Po": 2, - "logic element": 4, - "Longest Path": 4, - "Average Path": 4, - "Estimated LUTs": 4, - "Total Node": 4 + "logic element": 2, + "Longest Path": 3, + "Average Path": 3, + "Estimated LUTs": 2, + "Total Node": 2 }, "xor/xor_wire/no_arch": { "test_name": "xor/xor_wire/no_arch", @@ -23,11 +23,11 @@ "test_coverage(%)": 100, "Pi": 2, "Po": 1, - "logic element": 2, - "Longest Path": 4, - "Average Path": 4, - "Estimated LUTs": 2, - "Total Node": 2 + "logic element": 1, + "Longest Path": 3, + "Average Path": 3, + "Estimated LUTs": 1, + "Total Node": 1 }, "DEFAULT": { "test_name": "n/a", diff --git a/ODIN_II/regression_test/benchmark/task/micro/simulation_result.json b/ODIN_II/regression_test/benchmark/task/micro/simulation_result.json index 7053cbf8aef..7f132169ae7 100644 --- a/ODIN_II/regression_test/benchmark/task/micro/simulation_result.json +++ b/ODIN_II/regression_test/benchmark/task/micro/simulation_result.json @@ -161,15 +161,15 @@ "Latch Drivers": 1, "Pi": 608, "Po": 144, - "logic element": 232, + "logic element": 88, "latch": 144, "Adder": 184, "Multiplier": 4, "generic logic size": 4, - "Longest Path": 37, - "Average Path": 5, - "Estimated LUTs": 232, - "Total Node": 565 + "Longest Path": 36, + "Average Path": 4, + "Estimated LUTs": 88, + "Total Node": 421 }, "micro/bm_arithmetic_unused_bits/k6_N10_40nm": { "test_name": "micro/bm_arithmetic_unused_bits/k6_N10_40nm", @@ -182,13 +182,13 @@ "Latch Drivers": 1, "Pi": 528, "Po": 144, - "logic element": 3880, + "logic element": 3736, "latch": 144, "generic logic size": 6, - "Longest Path": 66, - "Average Path": 5, - "Estimated LUTs": 3880, - "Total Node": 4025 + "Longest Path": 65, + "Average Path": 4, + "Estimated LUTs": 3736, + "Total Node": 3881 }, "micro/bm_arithmetic_unused_bits/k6_N10_mem32K_40nm": { "test_name": "micro/bm_arithmetic_unused_bits/k6_N10_mem32K_40nm", @@ -201,14 +201,14 @@ "Latch Drivers": 1, "Pi": 608, "Po": 144, - "logic element": 496, + "logic element": 352, "latch": 144, "Multiplier": 4, "generic logic size": 6, - "Longest Path": 37, - "Average Path": 5, - "Estimated LUTs": 496, - "Total Node": 645 + "Longest Path": 36, + "Average Path": 4, + "Estimated LUTs": 352, + "Total Node": 501 }, "micro/bm_arithmetic_unused_bits/no_arch": { "test_name": "micro/bm_arithmetic_unused_bits/no_arch", @@ -220,12 +220,12 @@ "Latch Drivers": 1, "Pi": 528, "Po": 144, - "logic element": 3880, + "logic element": 3736, "latch": 144, - "Longest Path": 66, - "Average Path": 5, - "Estimated LUTs": 3880, - "Total Node": 4025 + "Longest Path": 65, + "Average Path": 4, + "Estimated LUTs": 3736, + "Total Node": 3881 }, "micro/bm_base_multiply/k6_frac_N10_frac_chain_mem32K_40nm": { "test_name": "micro/bm_base_multiply/k6_frac_N10_frac_chain_mem32K_40nm", @@ -238,14 +238,14 @@ "Latch Drivers": 1, "Pi": 47, "Po": 78, - "logic element": 110, + "logic element": 63, "latch": 71, "Multiplier": 3, "generic logic size": 4, - "Longest Path": 9, + "Longest Path": 8, "Average Path": 4, - "Estimated LUTs": 110, - "Total Node": 185 + "Estimated LUTs": 63, + "Total Node": 138 }, "micro/bm_base_multiply/k6_N10_40nm": { "test_name": "micro/bm_base_multiply/k6_N10_40nm", @@ -258,13 +258,13 @@ "Latch Drivers": 1, "Pi": 47, "Po": 78, - "logic element": 795, + "logic element": 748, "latch": 71, "generic logic size": 6, - "Longest Path": 26, - "Average Path": 6, - "Estimated LUTs": 795, - "Total Node": 867 + "Longest Path": 25, + "Average Path": 5, + "Estimated LUTs": 748, + "Total Node": 820 }, "micro/bm_base_multiply/k6_N10_mem32K_40nm": { "test_name": "micro/bm_base_multiply/k6_N10_mem32K_40nm", @@ -277,14 +277,14 @@ "Latch Drivers": 1, "Pi": 47, "Po": 78, - "logic element": 110, + "logic element": 63, "latch": 71, "Multiplier": 3, "generic logic size": 6, - "Longest Path": 9, + "Longest Path": 8, "Average Path": 4, - "Estimated LUTs": 110, - "Total Node": 185 + "Estimated LUTs": 63, + "Total Node": 138 }, "micro/bm_base_multiply/no_arch": { "test_name": "micro/bm_base_multiply/no_arch", @@ -296,12 +296,12 @@ "Latch Drivers": 1, "Pi": 47, "Po": 78, - "logic element": 795, + "logic element": 748, "latch": 71, - "Longest Path": 26, - "Average Path": 6, - "Estimated LUTs": 795, - "Total Node": 867 + "Longest Path": 25, + "Average Path": 5, + "Estimated LUTs": 748, + "Total Node": 820 }, "micro/bm_dag1_log/k6_frac_N10_frac_chain_mem32K_40nm": { "test_name": "micro/bm_dag1_log/k6_frac_N10_frac_chain_mem32K_40nm", @@ -521,13 +521,13 @@ "Latch Drivers": 1, "Pi": 6, "Po": 3, - "logic element": 16, + "logic element": 13, "latch": 13, "generic logic size": 4, - "Longest Path": 9, - "Average Path": 5, - "Estimated LUTs": 16, - "Total Node": 30 + "Longest Path": 8, + "Average Path": 4, + "Estimated LUTs": 13, + "Total Node": 27 }, "micro/bm_dag1_mod/k6_N10_40nm": { "test_name": "micro/bm_dag1_mod/k6_N10_40nm", @@ -540,13 +540,13 @@ "Latch Drivers": 1, "Pi": 6, "Po": 3, - "logic element": 16, + "logic element": 13, "latch": 13, "generic logic size": 6, - "Longest Path": 9, - "Average Path": 5, - "Estimated LUTs": 16, - "Total Node": 30 + "Longest Path": 8, + "Average Path": 4, + "Estimated LUTs": 13, + "Total Node": 27 }, "micro/bm_dag1_mod/k6_N10_mem32K_40nm": { "test_name": "micro/bm_dag1_mod/k6_N10_mem32K_40nm", @@ -559,13 +559,13 @@ "Latch Drivers": 1, "Pi": 6, "Po": 3, - "logic element": 16, + "logic element": 13, "latch": 13, "generic logic size": 6, - "Longest Path": 9, - "Average Path": 5, - "Estimated LUTs": 16, - "Total Node": 30 + "Longest Path": 8, + "Average Path": 4, + "Estimated LUTs": 13, + "Total Node": 27 }, "micro/bm_dag1_mod/no_arch": { "test_name": "micro/bm_dag1_mod/no_arch", @@ -577,12 +577,12 @@ "Latch Drivers": 1, "Pi": 6, "Po": 3, - "logic element": 16, + "logic element": 13, "latch": 13, - "Longest Path": 9, - "Average Path": 5, - "Estimated LUTs": 16, - "Total Node": 30 + "Longest Path": 8, + "Average Path": 4, + "Estimated LUTs": 13, + "Total Node": 27 }, "micro/bm_dag2_log/k6_frac_N10_frac_chain_mem32K_40nm": { "test_name": "micro/bm_dag2_log/k6_frac_N10_frac_chain_mem32K_40nm", @@ -646,13 +646,13 @@ "Latch Drivers": 1, "Pi": 6, "Po": 3, - "logic element": 12, + "logic element": 9, "latch": 9, "generic logic size": 4, - "Longest Path": 9, - "Average Path": 5, - "Estimated LUTs": 12, - "Total Node": 22 + "Longest Path": 8, + "Average Path": 4, + "Estimated LUTs": 9, + "Total Node": 19 }, "micro/bm_dag2_log_mod/k6_N10_40nm": { "test_name": "micro/bm_dag2_log_mod/k6_N10_40nm", @@ -665,13 +665,13 @@ "Latch Drivers": 1, "Pi": 6, "Po": 3, - "logic element": 12, + "logic element": 9, "latch": 9, "generic logic size": 6, - "Longest Path": 9, - "Average Path": 5, - "Estimated LUTs": 12, - "Total Node": 22 + "Longest Path": 8, + "Average Path": 4, + "Estimated LUTs": 9, + "Total Node": 19 }, "micro/bm_dag2_log_mod/k6_N10_mem32K_40nm": { "test_name": "micro/bm_dag2_log_mod/k6_N10_mem32K_40nm", @@ -684,13 +684,13 @@ "Latch Drivers": 1, "Pi": 6, "Po": 3, - "logic element": 12, + "logic element": 9, "latch": 9, "generic logic size": 6, - "Longest Path": 9, - "Average Path": 5, - "Estimated LUTs": 12, - "Total Node": 22 + "Longest Path": 8, + "Average Path": 4, + "Estimated LUTs": 9, + "Total Node": 19 }, "micro/bm_dag2_log_mod/no_arch": { "test_name": "micro/bm_dag2_log_mod/no_arch", @@ -702,12 +702,12 @@ "Latch Drivers": 1, "Pi": 6, "Po": 3, - "logic element": 12, + "logic element": 9, "latch": 9, - "Longest Path": 9, - "Average Path": 5, - "Estimated LUTs": 12, - "Total Node": 22 + "Longest Path": 8, + "Average Path": 4, + "Estimated LUTs": 9, + "Total Node": 19 }, "micro/bm_dag2_log/no_arch": { "test_name": "micro/bm_dag2_log/no_arch", @@ -802,13 +802,13 @@ "Latch Drivers": 1, "Pi": 6, "Po": 3, - "logic element": 12, + "logic element": 9, "latch": 9, "generic logic size": 4, - "Longest Path": 9, - "Average Path": 5, - "Estimated LUTs": 12, - "Total Node": 22 + "Longest Path": 8, + "Average Path": 4, + "Estimated LUTs": 9, + "Total Node": 19 }, "micro/bm_dag2_mod/k6_N10_40nm": { "test_name": "micro/bm_dag2_mod/k6_N10_40nm", @@ -821,13 +821,13 @@ "Latch Drivers": 1, "Pi": 6, "Po": 3, - "logic element": 12, + "logic element": 9, "latch": 9, "generic logic size": 6, - "Longest Path": 9, - "Average Path": 5, - "Estimated LUTs": 12, - "Total Node": 22 + "Longest Path": 8, + "Average Path": 4, + "Estimated LUTs": 9, + "Total Node": 19 }, "micro/bm_dag2_mod/k6_N10_mem32K_40nm": { "test_name": "micro/bm_dag2_mod/k6_N10_mem32K_40nm", @@ -840,13 +840,13 @@ "Latch Drivers": 1, "Pi": 6, "Po": 3, - "logic element": 12, + "logic element": 9, "latch": 9, "generic logic size": 6, - "Longest Path": 9, - "Average Path": 5, - "Estimated LUTs": 12, - "Total Node": 22 + "Longest Path": 8, + "Average Path": 4, + "Estimated LUTs": 9, + "Total Node": 19 }, "micro/bm_dag2_mod/no_arch": { "test_name": "micro/bm_dag2_mod/no_arch", @@ -858,12 +858,12 @@ "Latch Drivers": 1, "Pi": 6, "Po": 3, - "logic element": 12, + "logic element": 9, "latch": 9, - "Longest Path": 9, - "Average Path": 5, - "Estimated LUTs": 12, - "Total Node": 22 + "Longest Path": 8, + "Average Path": 4, + "Estimated LUTs": 9, + "Total Node": 19 }, "micro/bm_dag3_log/k6_frac_N10_frac_chain_mem32K_40nm": { "test_name": "micro/bm_dag3_log/k6_frac_N10_frac_chain_mem32K_40nm", @@ -1300,13 +1300,13 @@ "Latch Drivers": 1, "Pi": 6, "Po": 3, - "logic element": 28, + "logic element": 25, "latch": 23, "generic logic size": 4, - "Longest Path": 18, - "Average Path": 5, - "Estimated LUTs": 28, - "Total Node": 52 + "Longest Path": 17, + "Average Path": 4, + "Estimated LUTs": 25, + "Total Node": 49 }, "micro/bm_dag3_mod/k6_N10_40nm": { "test_name": "micro/bm_dag3_mod/k6_N10_40nm", @@ -1319,13 +1319,13 @@ "Latch Drivers": 1, "Pi": 6, "Po": 3, - "logic element": 28, + "logic element": 25, "latch": 23, "generic logic size": 6, - "Longest Path": 18, - "Average Path": 5, - "Estimated LUTs": 28, - "Total Node": 52 + "Longest Path": 17, + "Average Path": 4, + "Estimated LUTs": 25, + "Total Node": 49 }, "micro/bm_dag3_mod/k6_N10_mem32K_40nm": { "test_name": "micro/bm_dag3_mod/k6_N10_mem32K_40nm", @@ -1338,13 +1338,13 @@ "Latch Drivers": 1, "Pi": 6, "Po": 3, - "logic element": 28, + "logic element": 25, "latch": 23, "generic logic size": 6, - "Longest Path": 18, - "Average Path": 5, - "Estimated LUTs": 28, - "Total Node": 52 + "Longest Path": 17, + "Average Path": 4, + "Estimated LUTs": 25, + "Total Node": 49 }, "micro/bm_dag3_mod/no_arch": { "test_name": "micro/bm_dag3_mod/no_arch", @@ -1356,12 +1356,12 @@ "Latch Drivers": 1, "Pi": 6, "Po": 3, - "logic element": 28, + "logic element": 25, "latch": 23, - "Longest Path": 18, - "Average Path": 5, - "Estimated LUTs": 28, - "Total Node": 52 + "Longest Path": 17, + "Average Path": 4, + "Estimated LUTs": 25, + "Total Node": 49 }, "micro/bm_dag4_mod/k6_frac_N10_frac_chain_mem32K_40nm": { "test_name": "micro/bm_dag4_mod/k6_frac_N10_frac_chain_mem32K_40nm", @@ -1374,13 +1374,13 @@ "Latch Drivers": 1, "Pi": 6, "Po": 3, - "logic element": 16, + "logic element": 13, "latch": 13, "generic logic size": 4, - "Longest Path": 9, - "Average Path": 5, - "Estimated LUTs": 16, - "Total Node": 30 + "Longest Path": 8, + "Average Path": 4, + "Estimated LUTs": 13, + "Total Node": 27 }, "micro/bm_dag4_mod/k6_N10_40nm": { "test_name": "micro/bm_dag4_mod/k6_N10_40nm", @@ -1393,13 +1393,13 @@ "Latch Drivers": 1, "Pi": 6, "Po": 3, - "logic element": 16, + "logic element": 13, "latch": 13, "generic logic size": 6, - "Longest Path": 9, - "Average Path": 5, - "Estimated LUTs": 16, - "Total Node": 30 + "Longest Path": 8, + "Average Path": 4, + "Estimated LUTs": 13, + "Total Node": 27 }, "micro/bm_dag4_mod/k6_N10_mem32K_40nm": { "test_name": "micro/bm_dag4_mod/k6_N10_mem32K_40nm", @@ -1412,13 +1412,13 @@ "Latch Drivers": 1, "Pi": 6, "Po": 3, - "logic element": 16, + "logic element": 13, "latch": 13, "generic logic size": 6, - "Longest Path": 9, - "Average Path": 5, - "Estimated LUTs": 16, - "Total Node": 30 + "Longest Path": 8, + "Average Path": 4, + "Estimated LUTs": 13, + "Total Node": 27 }, "micro/bm_dag4_mod/no_arch": { "test_name": "micro/bm_dag4_mod/no_arch", @@ -1430,12 +1430,12 @@ "Latch Drivers": 1, "Pi": 6, "Po": 3, - "logic element": 16, + "logic element": 13, "latch": 13, - "Longest Path": 9, - "Average Path": 5, - "Estimated LUTs": 16, - "Total Node": 30 + "Longest Path": 8, + "Average Path": 4, + "Estimated LUTs": 13, + "Total Node": 27 }, "micro/bm_DL_16_1_mux/k6_frac_N10_frac_chain_mem32K_40nm": { "test_name": "micro/bm_DL_16_1_mux/k6_frac_N10_frac_chain_mem32K_40nm", @@ -1646,13 +1646,13 @@ "Latch Drivers": 1, "Pi": 1, "Po": 2, - "logic element": 2, + "logic element": 1, "latch": 2, "generic logic size": 4, - "Longest Path": 5, + "Longest Path": 4, "Average Path": 4, - "Estimated LUTs": 2, - "Total Node": 5 + "Estimated LUTs": 1, + "Total Node": 4 }, "micro/bm_DL_2_cascaded_flip_flops/k6_N10_40nm": { "test_name": "micro/bm_DL_2_cascaded_flip_flops/k6_N10_40nm", @@ -1665,13 +1665,13 @@ "Latch Drivers": 1, "Pi": 1, "Po": 2, - "logic element": 2, + "logic element": 1, "latch": 2, "generic logic size": 6, - "Longest Path": 5, + "Longest Path": 4, "Average Path": 4, - "Estimated LUTs": 2, - "Total Node": 5 + "Estimated LUTs": 1, + "Total Node": 4 }, "micro/bm_DL_2_cascaded_flip_flops/k6_N10_mem32K_40nm": { "test_name": "micro/bm_DL_2_cascaded_flip_flops/k6_N10_mem32K_40nm", @@ -1684,13 +1684,13 @@ "Latch Drivers": 1, "Pi": 1, "Po": 2, - "logic element": 2, + "logic element": 1, "latch": 2, "generic logic size": 6, - "Longest Path": 5, + "Longest Path": 4, "Average Path": 4, - "Estimated LUTs": 2, - "Total Node": 5 + "Estimated LUTs": 1, + "Total Node": 4 }, "micro/bm_DL_2_cascaded_flip_flops/no_arch": { "test_name": "micro/bm_DL_2_cascaded_flip_flops/no_arch", @@ -1702,12 +1702,12 @@ "Latch Drivers": 1, "Pi": 1, "Po": 2, - "logic element": 2, + "logic element": 1, "latch": 2, - "Longest Path": 5, + "Longest Path": 4, "Average Path": 4, - "Estimated LUTs": 2, - "Total Node": 5 + "Estimated LUTs": 1, + "Total Node": 4 }, "micro/bm_DL_4_16_encoder/k6_frac_N10_frac_chain_mem32K_40nm": { "test_name": "micro/bm_DL_4_16_encoder/k6_frac_N10_frac_chain_mem32K_40nm", @@ -1918,13 +1918,13 @@ "Latch Drivers": 1, "Pi": 6, "Po": 4, - "logic element": 16, + "logic element": 15, "latch": 4, "generic logic size": 4, - "Longest Path": 13, + "Longest Path": 12, "Average Path": 5, - "Estimated LUTs": 16, - "Total Node": 21 + "Estimated LUTs": 15, + "Total Node": 20 }, "micro/bm_DL_4_bit_shift_register/k6_N10_40nm": { "test_name": "micro/bm_DL_4_bit_shift_register/k6_N10_40nm", @@ -1937,13 +1937,13 @@ "Latch Drivers": 1, "Pi": 6, "Po": 4, - "logic element": 16, + "logic element": 15, "latch": 4, "generic logic size": 6, - "Longest Path": 13, + "Longest Path": 12, "Average Path": 5, - "Estimated LUTs": 16, - "Total Node": 21 + "Estimated LUTs": 15, + "Total Node": 20 }, "micro/bm_DL_4_bit_shift_register/k6_N10_mem32K_40nm": { "test_name": "micro/bm_DL_4_bit_shift_register/k6_N10_mem32K_40nm", @@ -1956,13 +1956,13 @@ "Latch Drivers": 1, "Pi": 6, "Po": 4, - "logic element": 16, + "logic element": 15, "latch": 4, "generic logic size": 6, - "Longest Path": 13, + "Longest Path": 12, "Average Path": 5, - "Estimated LUTs": 16, - "Total Node": 21 + "Estimated LUTs": 15, + "Total Node": 20 }, "micro/bm_DL_4_bit_shift_register/no_arch": { "test_name": "micro/bm_DL_4_bit_shift_register/no_arch", @@ -1974,12 +1974,12 @@ "Latch Drivers": 1, "Pi": 6, "Po": 4, - "logic element": 16, + "logic element": 15, "latch": 4, - "Longest Path": 13, + "Longest Path": 12, "Average Path": 5, - "Estimated LUTs": 16, - "Total Node": 21 + "Estimated LUTs": 15, + "Total Node": 20 }, "micro/bm_DL_74381_ALU/k6_frac_N10_frac_chain_mem32K_40nm": { "test_name": "micro/bm_DL_74381_ALU/k6_frac_N10_frac_chain_mem32K_40nm", @@ -2259,13 +2259,13 @@ "Latch Drivers": 1, "Pi": 2, "Po": 1, - "logic element": 4, + "logic element": 3, "latch": 1, "generic logic size": 4, - "Longest Path": 7, - "Average Path": 5, - "Estimated LUTs": 4, - "Total Node": 6 + "Longest Path": 6, + "Average Path": 4, + "Estimated LUTs": 3, + "Total Node": 5 }, "micro/bm_DL_Dff_w_synch_reset/k6_N10_40nm": { "test_name": "micro/bm_DL_Dff_w_synch_reset/k6_N10_40nm", @@ -2278,13 +2278,13 @@ "Latch Drivers": 1, "Pi": 2, "Po": 1, - "logic element": 4, + "logic element": 3, "latch": 1, "generic logic size": 6, - "Longest Path": 7, - "Average Path": 5, - "Estimated LUTs": 4, - "Total Node": 6 + "Longest Path": 6, + "Average Path": 4, + "Estimated LUTs": 3, + "Total Node": 5 }, "micro/bm_DL_Dff_w_synch_reset/k6_N10_mem32K_40nm": { "test_name": "micro/bm_DL_Dff_w_synch_reset/k6_N10_mem32K_40nm", @@ -2297,13 +2297,13 @@ "Latch Drivers": 1, "Pi": 2, "Po": 1, - "logic element": 4, + "logic element": 3, "latch": 1, "generic logic size": 6, - "Longest Path": 7, - "Average Path": 5, - "Estimated LUTs": 4, - "Total Node": 6 + "Longest Path": 6, + "Average Path": 4, + "Estimated LUTs": 3, + "Total Node": 5 }, "micro/bm_DL_Dff_w_synch_reset/no_arch": { "test_name": "micro/bm_DL_Dff_w_synch_reset/no_arch", @@ -2315,12 +2315,12 @@ "Latch Drivers": 1, "Pi": 2, "Po": 1, - "logic element": 4, + "logic element": 3, "latch": 1, - "Longest Path": 7, - "Average Path": 5, - "Estimated LUTs": 4, - "Total Node": 6 + "Longest Path": 6, + "Average Path": 4, + "Estimated LUTs": 3, + "Total Node": 5 }, "micro/bm_DL_D_flipflop/k6_frac_N10_frac_chain_mem32K_40nm": { "test_name": "micro/bm_DL_D_flipflop/k6_frac_N10_frac_chain_mem32K_40nm", @@ -2333,13 +2333,11 @@ "Latch Drivers": 1, "Pi": 1, "Po": 1, - "logic element": 1, "latch": 1, "generic logic size": 4, - "Longest Path": 4, - "Average Path": 4, - "Estimated LUTs": 1, - "Total Node": 3 + "Longest Path": 3, + "Average Path": 3, + "Total Node": 2 }, "micro/bm_DL_D_flipflop/k6_N10_40nm": { "test_name": "micro/bm_DL_D_flipflop/k6_N10_40nm", @@ -2352,13 +2350,11 @@ "Latch Drivers": 1, "Pi": 1, "Po": 1, - "logic element": 1, "latch": 1, "generic logic size": 6, - "Longest Path": 4, - "Average Path": 4, - "Estimated LUTs": 1, - "Total Node": 3 + "Longest Path": 3, + "Average Path": 3, + "Total Node": 2 }, "micro/bm_DL_D_flipflop/k6_N10_mem32K_40nm": { "test_name": "micro/bm_DL_D_flipflop/k6_N10_mem32K_40nm", @@ -2371,13 +2367,11 @@ "Latch Drivers": 1, "Pi": 1, "Po": 1, - "logic element": 1, "latch": 1, "generic logic size": 6, - "Longest Path": 4, - "Average Path": 4, - "Estimated LUTs": 1, - "Total Node": 3 + "Longest Path": 3, + "Average Path": 3, + "Total Node": 2 }, "micro/bm_DL_D_flipflop/no_arch": { "test_name": "micro/bm_DL_D_flipflop/no_arch", @@ -2389,12 +2383,10 @@ "Latch Drivers": 1, "Pi": 1, "Po": 1, - "logic element": 1, "latch": 1, - "Longest Path": 4, - "Average Path": 4, - "Estimated LUTs": 1, - "Total Node": 3 + "Longest Path": 3, + "Average Path": 3, + "Total Node": 2 }, "micro/bm_DL_four_bit_adder_continuous_assign/k6_frac_N10_frac_chain_mem32K_40nm": { "test_name": "micro/bm_DL_four_bit_adder_continuous_assign/k6_frac_N10_frac_chain_mem32K_40nm", @@ -2473,13 +2465,13 @@ "Latch Drivers": 1, "Pi": 3, "Po": 2, - "logic element": 4, + "logic element": 3, "latch": 2, "generic logic size": 4, - "Longest Path": 7, - "Average Path": 5, - "Estimated LUTs": 4, - "Total Node": 7 + "Longest Path": 6, + "Average Path": 4, + "Estimated LUTs": 3, + "Total Node": 6 }, "micro/bm_DL_logic_w_Dff2/k6_N10_40nm": { "test_name": "micro/bm_DL_logic_w_Dff2/k6_N10_40nm", @@ -2492,13 +2484,13 @@ "Latch Drivers": 1, "Pi": 3, "Po": 2, - "logic element": 4, + "logic element": 3, "latch": 2, "generic logic size": 6, - "Longest Path": 7, - "Average Path": 5, - "Estimated LUTs": 4, - "Total Node": 7 + "Longest Path": 6, + "Average Path": 4, + "Estimated LUTs": 3, + "Total Node": 6 }, "micro/bm_DL_logic_w_Dff2/k6_N10_mem32K_40nm": { "test_name": "micro/bm_DL_logic_w_Dff2/k6_N10_mem32K_40nm", @@ -2511,13 +2503,13 @@ "Latch Drivers": 1, "Pi": 3, "Po": 2, - "logic element": 4, + "logic element": 3, "latch": 2, "generic logic size": 6, - "Longest Path": 7, - "Average Path": 5, - "Estimated LUTs": 4, - "Total Node": 7 + "Longest Path": 6, + "Average Path": 4, + "Estimated LUTs": 3, + "Total Node": 6 }, "micro/bm_DL_logic_w_Dff2/no_arch": { "test_name": "micro/bm_DL_logic_w_Dff2/no_arch", @@ -2529,12 +2521,12 @@ "Latch Drivers": 1, "Pi": 3, "Po": 2, - "logic element": 4, + "logic element": 3, "latch": 2, - "Longest Path": 7, - "Average Path": 5, - "Estimated LUTs": 4, - "Total Node": 7 + "Longest Path": 6, + "Average Path": 4, + "Estimated LUTs": 3, + "Total Node": 6 }, "micro/bm_DL_logic_w_Dff/k6_frac_N10_frac_chain_mem32K_40nm": { "test_name": "micro/bm_DL_logic_w_Dff/k6_frac_N10_frac_chain_mem32K_40nm", @@ -2547,13 +2539,13 @@ "Latch Drivers": 1, "Pi": 3, "Po": 2, - "logic element": 4, + "logic element": 3, "latch": 2, "generic logic size": 4, - "Longest Path": 7, - "Average Path": 5, - "Estimated LUTs": 4, - "Total Node": 7 + "Longest Path": 6, + "Average Path": 4, + "Estimated LUTs": 3, + "Total Node": 6 }, "micro/bm_DL_logic_w_Dff/k6_N10_40nm": { "test_name": "micro/bm_DL_logic_w_Dff/k6_N10_40nm", @@ -2566,13 +2558,13 @@ "Latch Drivers": 1, "Pi": 3, "Po": 2, - "logic element": 4, + "logic element": 3, "latch": 2, "generic logic size": 6, - "Longest Path": 7, - "Average Path": 5, - "Estimated LUTs": 4, - "Total Node": 7 + "Longest Path": 6, + "Average Path": 4, + "Estimated LUTs": 3, + "Total Node": 6 }, "micro/bm_DL_logic_w_Dff/k6_N10_mem32K_40nm": { "test_name": "micro/bm_DL_logic_w_Dff/k6_N10_mem32K_40nm", @@ -2585,13 +2577,13 @@ "Latch Drivers": 1, "Pi": 3, "Po": 2, - "logic element": 4, + "logic element": 3, "latch": 2, "generic logic size": 6, - "Longest Path": 7, - "Average Path": 5, - "Estimated LUTs": 4, - "Total Node": 7 + "Longest Path": 6, + "Average Path": 4, + "Estimated LUTs": 3, + "Total Node": 6 }, "micro/bm_DL_logic_w_Dff/no_arch": { "test_name": "micro/bm_DL_logic_w_Dff/no_arch", @@ -2603,12 +2595,12 @@ "Latch Drivers": 1, "Pi": 3, "Po": 2, - "logic element": 4, + "logic element": 3, "latch": 2, - "Longest Path": 7, - "Average Path": 5, - "Estimated LUTs": 4, - "Total Node": 7 + "Longest Path": 6, + "Average Path": 4, + "Estimated LUTs": 3, + "Total Node": 6 }, "micro/bm_DL_structural_logic2/k6_frac_N10_frac_chain_mem32K_40nm": { "test_name": "micro/bm_DL_structural_logic2/k6_frac_N10_frac_chain_mem32K_40nm", @@ -2620,12 +2612,12 @@ "test_coverage(%)": 100, "Pi": 4, "Po": 3, - "logic element": 12, + "logic element": 11, "generic logic size": 4, - "Longest Path": 7, - "Average Path": 6, - "Estimated LUTs": 12, - "Total Node": 12 + "Longest Path": 6, + "Average Path": 5, + "Estimated LUTs": 11, + "Total Node": 11 }, "micro/bm_DL_structural_logic2/k6_N10_40nm": { "test_name": "micro/bm_DL_structural_logic2/k6_N10_40nm", @@ -2637,12 +2629,12 @@ "test_coverage(%)": 100, "Pi": 4, "Po": 3, - "logic element": 12, + "logic element": 11, "generic logic size": 6, - "Longest Path": 7, - "Average Path": 6, - "Estimated LUTs": 12, - "Total Node": 12 + "Longest Path": 6, + "Average Path": 5, + "Estimated LUTs": 11, + "Total Node": 11 }, "micro/bm_DL_structural_logic2/k6_N10_mem32K_40nm": { "test_name": "micro/bm_DL_structural_logic2/k6_N10_mem32K_40nm", @@ -2654,12 +2646,12 @@ "test_coverage(%)": 100, "Pi": 4, "Po": 3, - "logic element": 12, + "logic element": 11, "generic logic size": 6, - "Longest Path": 7, - "Average Path": 6, - "Estimated LUTs": 12, - "Total Node": 12 + "Longest Path": 6, + "Average Path": 5, + "Estimated LUTs": 11, + "Total Node": 11 }, "micro/bm_DL_structural_logic2/no_arch": { "test_name": "micro/bm_DL_structural_logic2/no_arch", @@ -2670,11 +2662,11 @@ "test_coverage(%)": 100, "Pi": 4, "Po": 3, - "logic element": 12, - "Longest Path": 7, - "Average Path": 6, - "Estimated LUTs": 12, - "Total Node": 12 + "logic element": 11, + "Longest Path": 6, + "Average Path": 5, + "Estimated LUTs": 11, + "Total Node": 11 }, "micro/bm_DL_structural_logic/k6_frac_N10_frac_chain_mem32K_40nm": { "test_name": "micro/bm_DL_structural_logic/k6_frac_N10_frac_chain_mem32K_40nm", @@ -2686,12 +2678,12 @@ "test_coverage(%)": 100, "Pi": 3, "Po": 1, - "logic element": 5, + "logic element": 4, "generic logic size": 4, - "Longest Path": 6, - "Average Path": 5, - "Estimated LUTs": 5, - "Total Node": 5 + "Longest Path": 5, + "Average Path": 4, + "Estimated LUTs": 4, + "Total Node": 4 }, "micro/bm_DL_structural_logic/k6_N10_40nm": { "test_name": "micro/bm_DL_structural_logic/k6_N10_40nm", @@ -2703,12 +2695,12 @@ "test_coverage(%)": 100, "Pi": 3, "Po": 1, - "logic element": 5, + "logic element": 4, "generic logic size": 6, - "Longest Path": 6, - "Average Path": 5, - "Estimated LUTs": 5, - "Total Node": 5 + "Longest Path": 5, + "Average Path": 4, + "Estimated LUTs": 4, + "Total Node": 4 }, "micro/bm_DL_structural_logic/k6_N10_mem32K_40nm": { "test_name": "micro/bm_DL_structural_logic/k6_N10_mem32K_40nm", @@ -2720,12 +2712,12 @@ "test_coverage(%)": 100, "Pi": 3, "Po": 1, - "logic element": 5, + "logic element": 4, "generic logic size": 6, - "Longest Path": 6, - "Average Path": 5, - "Estimated LUTs": 5, - "Total Node": 5 + "Longest Path": 5, + "Average Path": 4, + "Estimated LUTs": 4, + "Total Node": 4 }, "micro/bm_DL_structural_logic/no_arch": { "test_name": "micro/bm_DL_structural_logic/no_arch", @@ -2736,11 +2728,11 @@ "test_coverage(%)": 100, "Pi": 3, "Po": 1, - "logic element": 5, - "Longest Path": 6, - "Average Path": 5, - "Estimated LUTs": 5, - "Total Node": 5 + "logic element": 4, + "Longest Path": 5, + "Average Path": 4, + "Estimated LUTs": 4, + "Total Node": 4 }, "micro/bm_expr_all_mod/k6_frac_N10_frac_chain_mem32K_40nm": { "test_name": "micro/bm_expr_all_mod/k6_frac_N10_frac_chain_mem32K_40nm", @@ -2753,14 +2745,14 @@ "Latch Drivers": 1, "Pi": 161, "Po": 555, - "logic element": 1826, + "logic element": 1271, "latch": 555, "Adder": 132, "generic logic size": 4, - "Longest Path": 42, - "Average Path": 5, - "Estimated LUTs": 1996, - "Total Node": 2514 + "Longest Path": 41, + "Average Path": 4, + "Estimated LUTs": 1441, + "Total Node": 1959 }, "micro/bm_expr_all_mod/k6_N10_40nm": { "test_name": "micro/bm_expr_all_mod/k6_N10_40nm", @@ -2773,13 +2765,13 @@ "Latch Drivers": 1, "Pi": 161, "Po": 555, - "logic element": 2141, + "logic element": 1586, "latch": 555, "generic logic size": 6, - "Longest Path": 42, - "Average Path": 4, - "Estimated LUTs": 2243, - "Total Node": 2697 + "Longest Path": 41, + "Average Path": 3, + "Estimated LUTs": 1688, + "Total Node": 2142 }, "micro/bm_expr_all_mod/k6_N10_mem32K_40nm": { "test_name": "micro/bm_expr_all_mod/k6_N10_mem32K_40nm", @@ -2792,13 +2784,13 @@ "Latch Drivers": 1, "Pi": 161, "Po": 555, - "logic element": 2141, + "logic element": 1586, "latch": 555, "generic logic size": 6, - "Longest Path": 42, - "Average Path": 4, - "Estimated LUTs": 2243, - "Total Node": 2697 + "Longest Path": 41, + "Average Path": 3, + "Estimated LUTs": 1688, + "Total Node": 2142 }, "micro/bm_expr_all_mod/no_arch": { "test_name": "micro/bm_expr_all_mod/no_arch", @@ -2810,12 +2802,12 @@ "Latch Drivers": 1, "Pi": 161, "Po": 555, - "logic element": 2141, + "logic element": 1586, "latch": 555, - "Longest Path": 42, - "Average Path": 4, - "Estimated LUTs": 2141, - "Total Node": 2697 + "Longest Path": 41, + "Average Path": 3, + "Estimated LUTs": 1586, + "Total Node": 2142 }, "micro/bm_functional_test/k6_frac_N10_frac_chain_mem32K_40nm": { "test_name": "micro/bm_functional_test/k6_frac_N10_frac_chain_mem32K_40nm", @@ -2828,15 +2820,15 @@ "Latch Drivers": 1, "Pi": 33, "Po": 40, - "logic element": 340, + "logic element": 308, "latch": 40, "Adder": 47, "Multiplier": 2, "generic logic size": 4, - "Longest Path": 30, - "Average Path": 5, - "Estimated LUTs": 503, - "Total Node": 430 + "Longest Path": 29, + "Average Path": 4, + "Estimated LUTs": 471, + "Total Node": 398 }, "micro/bm_functional_test/k6_N10_40nm": { "test_name": "micro/bm_functional_test/k6_N10_40nm", @@ -2849,13 +2841,13 @@ "Latch Drivers": 1, "Pi": 33, "Po": 40, - "logic element": 785, + "logic element": 753, "latch": 40, "generic logic size": 6, - "Longest Path": 53, - "Average Path": 5, - "Estimated LUTs": 882, - "Total Node": 826 + "Longest Path": 52, + "Average Path": 4, + "Estimated LUTs": 850, + "Total Node": 794 }, "micro/bm_functional_test/k6_N10_mem32K_40nm": { "test_name": "micro/bm_functional_test/k6_N10_mem32K_40nm", @@ -2868,14 +2860,14 @@ "Latch Drivers": 1, "Pi": 33, "Po": 40, - "logic element": 419, + "logic element": 387, "latch": 40, "Multiplier": 2, "generic logic size": 6, - "Longest Path": 53, - "Average Path": 5, - "Estimated LUTs": 516, - "Total Node": 462 + "Longest Path": 52, + "Average Path": 4, + "Estimated LUTs": 484, + "Total Node": 430 }, "micro/bm_functional_test/no_arch": { "test_name": "micro/bm_functional_test/no_arch", @@ -2887,12 +2879,12 @@ "Latch Drivers": 1, "Pi": 33, "Po": 40, - "logic element": 785, + "logic element": 753, "latch": 40, - "Longest Path": 53, - "Average Path": 5, - "Estimated LUTs": 785, - "Total Node": 826 + "Longest Path": 52, + "Average Path": 4, + "Estimated LUTs": 753, + "Total Node": 794 }, "micro/bm_if_collapse/k6_frac_N10_frac_chain_mem32K_40nm": { "test_name": "micro/bm_if_collapse/k6_frac_N10_frac_chain_mem32K_40nm", @@ -2905,13 +2897,13 @@ "Latch Drivers": 1, "Pi": 6, "Po": 5, - "logic element": 44, + "logic element": 42, "latch": 11, "generic logic size": 4, - "Longest Path": 12, + "Longest Path": 11, "Average Path": 5, - "Estimated LUTs": 52, - "Total Node": 56 + "Estimated LUTs": 50, + "Total Node": 54 }, "micro/bm_if_collapse/k6_N10_40nm": { "test_name": "micro/bm_if_collapse/k6_N10_40nm", @@ -2924,13 +2916,13 @@ "Latch Drivers": 1, "Pi": 6, "Po": 5, - "logic element": 44, + "logic element": 42, "latch": 11, "generic logic size": 6, - "Longest Path": 12, + "Longest Path": 11, "Average Path": 5, - "Estimated LUTs": 52, - "Total Node": 56 + "Estimated LUTs": 50, + "Total Node": 54 }, "micro/bm_if_collapse/k6_N10_mem32K_40nm": { "test_name": "micro/bm_if_collapse/k6_N10_mem32K_40nm", @@ -2943,13 +2935,13 @@ "Latch Drivers": 1, "Pi": 6, "Po": 5, - "logic element": 44, + "logic element": 42, "latch": 11, "generic logic size": 6, - "Longest Path": 12, + "Longest Path": 11, "Average Path": 5, - "Estimated LUTs": 52, - "Total Node": 56 + "Estimated LUTs": 50, + "Total Node": 54 }, "micro/bm_if_collapse/no_arch": { "test_name": "micro/bm_if_collapse/no_arch", @@ -2961,12 +2953,12 @@ "Latch Drivers": 1, "Pi": 6, "Po": 5, - "logic element": 44, + "logic element": 42, "latch": 11, - "Longest Path": 12, + "Longest Path": 11, "Average Path": 5, - "Estimated LUTs": 44, - "Total Node": 56 + "Estimated LUTs": 42, + "Total Node": 54 }, "micro/bm_if_common/k6_frac_N10_frac_chain_mem32K_40nm": { "test_name": "micro/bm_if_common/k6_frac_N10_frac_chain_mem32K_40nm", @@ -2979,13 +2971,13 @@ "Latch Drivers": 1, "Pi": 6, "Po": 5, - "logic element": 32, + "logic element": 27, "latch": 11, "generic logic size": 4, - "Longest Path": 10, - "Average Path": 5, - "Estimated LUTs": 40, - "Total Node": 44 + "Longest Path": 9, + "Average Path": 4, + "Estimated LUTs": 35, + "Total Node": 39 }, "micro/bm_if_common/k6_N10_40nm": { "test_name": "micro/bm_if_common/k6_N10_40nm", @@ -2998,13 +2990,13 @@ "Latch Drivers": 1, "Pi": 6, "Po": 5, - "logic element": 32, + "logic element": 27, "latch": 11, "generic logic size": 6, - "Longest Path": 10, - "Average Path": 5, - "Estimated LUTs": 40, - "Total Node": 44 + "Longest Path": 9, + "Average Path": 4, + "Estimated LUTs": 35, + "Total Node": 39 }, "micro/bm_if_common/k6_N10_mem32K_40nm": { "test_name": "micro/bm_if_common/k6_N10_mem32K_40nm", @@ -3017,13 +3009,13 @@ "Latch Drivers": 1, "Pi": 6, "Po": 5, - "logic element": 32, + "logic element": 27, "latch": 11, "generic logic size": 6, - "Longest Path": 10, - "Average Path": 5, - "Estimated LUTs": 40, - "Total Node": 44 + "Longest Path": 9, + "Average Path": 4, + "Estimated LUTs": 35, + "Total Node": 39 }, "micro/bm_if_common/no_arch": { "test_name": "micro/bm_if_common/no_arch", @@ -3035,12 +3027,12 @@ "Latch Drivers": 1, "Pi": 6, "Po": 5, - "logic element": 32, + "logic element": 27, "latch": 11, - "Longest Path": 10, - "Average Path": 5, - "Estimated LUTs": 32, - "Total Node": 44 + "Longest Path": 9, + "Average Path": 4, + "Estimated LUTs": 27, + "Total Node": 39 }, "micro/bm_if_reset/k6_frac_N10_frac_chain_mem32K_40nm": { "test_name": "micro/bm_if_reset/k6_frac_N10_frac_chain_mem32K_40nm", @@ -3053,13 +3045,13 @@ "Latch Drivers": 1, "Pi": 7, "Po": 3, - "logic element": 12, + "logic element": 9, "latch": 3, "generic logic size": 4, - "Longest Path": 8, - "Average Path": 5, - "Estimated LUTs": 12, - "Total Node": 16 + "Longest Path": 7, + "Average Path": 4, + "Estimated LUTs": 9, + "Total Node": 13 }, "micro/bm_if_reset/k6_N10_40nm": { "test_name": "micro/bm_if_reset/k6_N10_40nm", @@ -3072,13 +3064,13 @@ "Latch Drivers": 1, "Pi": 7, "Po": 3, - "logic element": 12, + "logic element": 9, "latch": 3, "generic logic size": 6, - "Longest Path": 8, - "Average Path": 5, - "Estimated LUTs": 12, - "Total Node": 16 + "Longest Path": 7, + "Average Path": 4, + "Estimated LUTs": 9, + "Total Node": 13 }, "micro/bm_if_reset/k6_N10_mem32K_40nm": { "test_name": "micro/bm_if_reset/k6_N10_mem32K_40nm", @@ -3091,13 +3083,13 @@ "Latch Drivers": 1, "Pi": 7, "Po": 3, - "logic element": 12, + "logic element": 9, "latch": 3, "generic logic size": 6, - "Longest Path": 8, - "Average Path": 5, - "Estimated LUTs": 12, - "Total Node": 16 + "Longest Path": 7, + "Average Path": 4, + "Estimated LUTs": 9, + "Total Node": 13 }, "micro/bm_if_reset/no_arch": { "test_name": "micro/bm_if_reset/no_arch", @@ -3109,12 +3101,12 @@ "Latch Drivers": 1, "Pi": 7, "Po": 3, - "logic element": 12, + "logic element": 9, "latch": 3, - "Longest Path": 8, - "Average Path": 5, - "Estimated LUTs": 12, - "Total Node": 16 + "Longest Path": 7, + "Average Path": 4, + "Estimated LUTs": 9, + "Total Node": 13 }, "micro/bm_lpm_all/k6_frac_N10_frac_chain_mem32K_40nm": { "test_name": "micro/bm_lpm_all/k6_frac_N10_frac_chain_mem32K_40nm", @@ -3260,14 +3252,14 @@ "Latch Drivers": 1, "Pi": 88, "Po": 144, - "logic element": 144, + "logic element": 72, "latch": 72, "Multiplier": 3, "generic logic size": 4, - "Longest Path": 5, + "Longest Path": 4, "Average Path": 4, - "Estimated LUTs": 144, - "Total Node": 220 + "Estimated LUTs": 72, + "Total Node": 148 }, "micro/bm_match1_str_arch/k6_N10_40nm": { "test_name": "micro/bm_match1_str_arch/k6_N10_40nm", @@ -3280,13 +3272,13 @@ "Latch Drivers": 1, "Pi": 88, "Po": 144, - "logic element": 3872, + "logic element": 3800, "latch": 72, "generic logic size": 6, - "Longest Path": 74, - "Average Path": 6, - "Estimated LUTs": 3872, - "Total Node": 3945 + "Longest Path": 73, + "Average Path": 5, + "Estimated LUTs": 3800, + "Total Node": 3873 }, "micro/bm_match1_str_arch/k6_N10_mem32K_40nm": { "test_name": "micro/bm_match1_str_arch/k6_N10_mem32K_40nm", @@ -3299,14 +3291,14 @@ "Latch Drivers": 1, "Pi": 88, "Po": 144, - "logic element": 144, + "logic element": 72, "latch": 72, "Multiplier": 3, "generic logic size": 6, - "Longest Path": 5, + "Longest Path": 4, "Average Path": 4, - "Estimated LUTs": 144, - "Total Node": 220 + "Estimated LUTs": 72, + "Total Node": 148 }, "micro/bm_match1_str_arch/no_arch": { "test_name": "micro/bm_match1_str_arch/no_arch", @@ -3318,12 +3310,12 @@ "Latch Drivers": 1, "Pi": 88, "Po": 144, - "logic element": 3872, + "logic element": 3800, "latch": 72, - "Longest Path": 74, - "Average Path": 6, - "Estimated LUTs": 3872, - "Total Node": 3945 + "Longest Path": 73, + "Average Path": 5, + "Estimated LUTs": 3800, + "Total Node": 3873 }, "micro/bm_match2_str_arch/k6_frac_N10_frac_chain_mem32K_40nm": { "test_name": "micro/bm_match2_str_arch/k6_frac_N10_frac_chain_mem32K_40nm", @@ -3336,15 +3328,15 @@ "Latch Drivers": 1, "Pi": 54, "Po": 99, - "logic element": 99, + "logic element": 45, "latch": 54, "Adder": 173, "Multiplier": 4, "generic logic size": 4, - "Longest Path": 25, + "Longest Path": 24, "Average Path": 5, - "Estimated LUTs": 99, - "Total Node": 331 + "Estimated LUTs": 45, + "Total Node": 277 }, "micro/bm_match2_str_arch/k6_N10_40nm": { "test_name": "micro/bm_match2_str_arch/k6_N10_40nm", @@ -3357,13 +3349,13 @@ "Latch Drivers": 1, "Pi": 54, "Po": 99, - "logic element": 3211, + "logic element": 3157, "latch": 54, "generic logic size": 6, - "Longest Path": 32, - "Average Path": 7, - "Estimated LUTs": 3211, - "Total Node": 3266 + "Longest Path": 31, + "Average Path": 6, + "Estimated LUTs": 3157, + "Total Node": 3212 }, "micro/bm_match2_str_arch/k6_N10_mem32K_40nm": { "test_name": "micro/bm_match2_str_arch/k6_N10_mem32K_40nm", @@ -3376,14 +3368,14 @@ "Latch Drivers": 1, "Pi": 54, "Po": 99, - "logic element": 415, + "logic element": 361, "latch": 54, "Multiplier": 4, "generic logic size": 6, - "Longest Path": 25, + "Longest Path": 24, "Average Path": 5, - "Estimated LUTs": 415, - "Total Node": 474 + "Estimated LUTs": 361, + "Total Node": 420 }, "micro/bm_match2_str_arch/no_arch": { "test_name": "micro/bm_match2_str_arch/no_arch", @@ -3395,12 +3387,12 @@ "Latch Drivers": 1, "Pi": 54, "Po": 99, - "logic element": 3211, + "logic element": 3157, "latch": 54, - "Longest Path": 32, - "Average Path": 7, - "Estimated LUTs": 3211, - "Total Node": 3266 + "Longest Path": 31, + "Average Path": 6, + "Estimated LUTs": 3157, + "Total Node": 3212 }, "micro/bm_match3_str_arch/k6_frac_N10_frac_chain_mem32K_40nm": { "test_name": "micro/bm_match3_str_arch/k6_frac_N10_frac_chain_mem32K_40nm", @@ -3413,15 +3405,15 @@ "Latch Drivers": 1, "Pi": 54, "Po": 54, - "logic element": 54, + "logic element": 18, "latch": 54, "Adder": 50, "Multiplier": 1, "generic logic size": 4, - "Longest Path": 24, - "Average Path": 5, - "Estimated LUTs": 54, - "Total Node": 160 + "Longest Path": 23, + "Average Path": 4, + "Estimated LUTs": 18, + "Total Node": 124 }, "micro/bm_match3_str_arch/k6_N10_40nm": { "test_name": "micro/bm_match3_str_arch/k6_N10_40nm", @@ -3434,13 +3426,13 @@ "Latch Drivers": 1, "Pi": 54, "Po": 54, - "logic element": 375, + "logic element": 339, "latch": 54, "generic logic size": 6, - "Longest Path": 58, - "Average Path": 5, - "Estimated LUTs": 375, - "Total Node": 430 + "Longest Path": 57, + "Average Path": 4, + "Estimated LUTs": 339, + "Total Node": 394 }, "micro/bm_match3_str_arch/k6_N10_mem32K_40nm": { "test_name": "micro/bm_match3_str_arch/k6_N10_mem32K_40nm", @@ -3453,14 +3445,14 @@ "Latch Drivers": 1, "Pi": 54, "Po": 54, - "logic element": 142, + "logic element": 106, "latch": 54, "Multiplier": 1, "generic logic size": 6, - "Longest Path": 58, - "Average Path": 5, - "Estimated LUTs": 142, - "Total Node": 198 + "Longest Path": 57, + "Average Path": 4, + "Estimated LUTs": 106, + "Total Node": 162 }, "micro/bm_match3_str_arch/no_arch": { "test_name": "micro/bm_match3_str_arch/no_arch", @@ -3472,12 +3464,12 @@ "Latch Drivers": 1, "Pi": 54, "Po": 54, - "logic element": 375, + "logic element": 339, "latch": 54, - "Longest Path": 58, - "Average Path": 5, - "Estimated LUTs": 375, - "Total Node": 430 + "Longest Path": 57, + "Average Path": 4, + "Estimated LUTs": 339, + "Total Node": 394 }, "micro/bm_match4_str_arch/k6_frac_N10_frac_chain_mem32K_40nm": { "test_name": "micro/bm_match4_str_arch/k6_frac_N10_frac_chain_mem32K_40nm", @@ -3490,15 +3482,15 @@ "Latch Drivers": 1, "Pi": 51, "Po": 216, - "logic element": 216, + "logic element": 108, "latch": 108, "Adder": 74, "Multiplier": 3, "generic logic size": 4, - "Longest Path": 42, + "Longest Path": 41, "Average Path": 4, - "Estimated LUTs": 216, - "Total Node": 402 + "Estimated LUTs": 108, + "Total Node": 294 }, "micro/bm_match4_str_arch/k6_N10_40nm": { "test_name": "micro/bm_match4_str_arch/k6_N10_40nm", @@ -3511,13 +3503,13 @@ "Latch Drivers": 1, "Pi": 51, "Po": 216, - "logic element": 1367, + "logic element": 1259, "latch": 108, "generic logic size": 6, - "Longest Path": 49, - "Average Path": 5, - "Estimated LUTs": 1367, - "Total Node": 1476 + "Longest Path": 48, + "Average Path": 4, + "Estimated LUTs": 1259, + "Total Node": 1368 }, "micro/bm_match4_str_arch/k6_N10_mem32K_40nm": { "test_name": "micro/bm_match4_str_arch/k6_N10_mem32K_40nm", @@ -3530,14 +3522,14 @@ "Latch Drivers": 1, "Pi": 51, "Po": 216, - "logic element": 358, + "logic element": 250, "latch": 108, "Multiplier": 3, "generic logic size": 6, - "Longest Path": 42, + "Longest Path": 41, "Average Path": 4, - "Estimated LUTs": 358, - "Total Node": 470 + "Estimated LUTs": 250, + "Total Node": 362 }, "micro/bm_match4_str_arch/no_arch": { "test_name": "micro/bm_match4_str_arch/no_arch", @@ -3549,12 +3541,12 @@ "Latch Drivers": 1, "Pi": 51, "Po": 216, - "logic element": 1367, + "logic element": 1259, "latch": 108, - "Longest Path": 49, - "Average Path": 5, - "Estimated LUTs": 1367, - "Total Node": 1476 + "Longest Path": 48, + "Average Path": 4, + "Estimated LUTs": 1259, + "Total Node": 1368 }, "micro/bm_match5_str_arch/k6_frac_N10_frac_chain_mem32K_40nm": { "test_name": "micro/bm_match5_str_arch/k6_frac_N10_frac_chain_mem32K_40nm", @@ -3567,15 +3559,13 @@ "Latch Drivers": 1, "Pi": 90, "Po": 54, - "logic element": 54, "latch": 54, "Adder": 125, "Multiplier": 6, "generic logic size": 4, - "Longest Path": 27, - "Average Path": 5, - "Estimated LUTs": 54, - "Total Node": 240 + "Longest Path": 26, + "Average Path": 4, + "Total Node": 186 }, "micro/bm_match5_str_arch/k6_N10_40nm": { "test_name": "micro/bm_match5_str_arch/k6_N10_40nm", @@ -3588,13 +3578,13 @@ "Latch Drivers": 1, "Pi": 90, "Po": 54, - "logic element": 2147, + "logic element": 2093, "latch": 54, "generic logic size": 6, - "Longest Path": 34, - "Average Path": 6, - "Estimated LUTs": 2147, - "Total Node": 2202 + "Longest Path": 33, + "Average Path": 5, + "Estimated LUTs": 2093, + "Total Node": 2148 }, "micro/bm_match5_str_arch/k6_N10_mem32K_40nm": { "test_name": "micro/bm_match5_str_arch/k6_N10_mem32K_40nm", @@ -3607,14 +3597,14 @@ "Latch Drivers": 1, "Pi": 90, "Po": 54, - "logic element": 283, + "logic element": 229, "latch": 54, "Multiplier": 6, "generic logic size": 6, - "Longest Path": 27, - "Average Path": 5, - "Estimated LUTs": 283, - "Total Node": 344 + "Longest Path": 26, + "Average Path": 4, + "Estimated LUTs": 229, + "Total Node": 290 }, "micro/bm_match5_str_arch/no_arch": { "test_name": "micro/bm_match5_str_arch/no_arch", @@ -3626,12 +3616,12 @@ "Latch Drivers": 1, "Pi": 90, "Po": 54, - "logic element": 2147, + "logic element": 2093, "latch": 54, - "Longest Path": 34, - "Average Path": 6, - "Estimated LUTs": 2147, - "Total Node": 2202 + "Longest Path": 33, + "Average Path": 5, + "Estimated LUTs": 2093, + "Total Node": 2148 }, "micro/bm_match6_str_arch/k6_frac_N10_frac_chain_mem32K_40nm": { "test_name": "micro/bm_match6_str_arch/k6_frac_N10_frac_chain_mem32K_40nm", @@ -3644,15 +3634,15 @@ "Latch Drivers": 1, "Pi": 54, "Po": 54, - "logic element": 54, + "logic element": 18, "latch": 36, "Adder": 49, "Multiplier": 2, "generic logic size": 4, - "Longest Path": 23, - "Average Path": 5, - "Estimated LUTs": 54, - "Total Node": 142 + "Longest Path": 22, + "Average Path": 4, + "Estimated LUTs": 18, + "Total Node": 106 }, "micro/bm_match6_str_arch/k6_N10_40nm": { "test_name": "micro/bm_match6_str_arch/k6_N10_40nm", @@ -3665,13 +3655,13 @@ "Latch Drivers": 1, "Pi": 54, "Po": 54, - "logic element": 609, + "logic element": 573, "latch": 36, "generic logic size": 6, - "Longest Path": 30, + "Longest Path": 29, "Average Path": 5, - "Estimated LUTs": 609, - "Total Node": 646 + "Estimated LUTs": 573, + "Total Node": 610 }, "micro/bm_match6_str_arch/k6_N10_mem32K_40nm": { "test_name": "micro/bm_match6_str_arch/k6_N10_mem32K_40nm", @@ -3684,14 +3674,14 @@ "Latch Drivers": 1, "Pi": 54, "Po": 54, - "logic element": 143, + "logic element": 107, "latch": 36, "Multiplier": 2, "generic logic size": 6, - "Longest Path": 23, - "Average Path": 5, - "Estimated LUTs": 143, - "Total Node": 182 + "Longest Path": 22, + "Average Path": 4, + "Estimated LUTs": 107, + "Total Node": 146 }, "micro/bm_match6_str_arch/no_arch": { "test_name": "micro/bm_match6_str_arch/no_arch", @@ -3703,12 +3693,12 @@ "Latch Drivers": 1, "Pi": 54, "Po": 54, - "logic element": 609, + "logic element": 573, "latch": 36, - "Longest Path": 30, + "Longest Path": 29, "Average Path": 5, - "Estimated LUTs": 609, - "Total Node": 646 + "Estimated LUTs": 573, + "Total Node": 610 }, "micro/bm_mod/k6_frac_N10_frac_chain_mem32K_40nm": { "test_name": "micro/bm_mod/k6_frac_N10_frac_chain_mem32K_40nm", @@ -3721,13 +3711,13 @@ "Latch Drivers": 1, "Pi": 66, "Po": 33, - "logic element": 66, + "logic element": 33, "latch": 33, "generic logic size": 4, - "Longest Path": 5, + "Longest Path": 4, "Average Path": 4, - "Estimated LUTs": 66, - "Total Node": 100 + "Estimated LUTs": 33, + "Total Node": 67 }, "micro/bm_mod/k6_N10_40nm": { "test_name": "micro/bm_mod/k6_N10_40nm", @@ -3740,13 +3730,13 @@ "Latch Drivers": 1, "Pi": 66, "Po": 33, - "logic element": 66, + "logic element": 33, "latch": 33, "generic logic size": 6, - "Longest Path": 5, + "Longest Path": 4, "Average Path": 4, - "Estimated LUTs": 66, - "Total Node": 100 + "Estimated LUTs": 33, + "Total Node": 67 }, "micro/bm_mod/k6_N10_mem32K_40nm": { "test_name": "micro/bm_mod/k6_N10_mem32K_40nm", @@ -3759,13 +3749,13 @@ "Latch Drivers": 1, "Pi": 66, "Po": 33, - "logic element": 66, + "logic element": 33, "latch": 33, "generic logic size": 6, - "Longest Path": 5, + "Longest Path": 4, "Average Path": 4, - "Estimated LUTs": 66, - "Total Node": 100 + "Estimated LUTs": 33, + "Total Node": 67 }, "micro/bm_mod/no_arch": { "test_name": "micro/bm_mod/no_arch", @@ -3777,12 +3767,12 @@ "Latch Drivers": 1, "Pi": 66, "Po": 33, - "logic element": 66, + "logic element": 33, "latch": 33, - "Longest Path": 5, + "Longest Path": 4, "Average Path": 4, - "Estimated LUTs": 66, - "Total Node": 100 + "Estimated LUTs": 33, + "Total Node": 67 }, "micro/bm_my_D_latch1/k6_frac_N10_frac_chain_mem32K_40nm": { "test_name": "micro/bm_my_D_latch1/k6_frac_N10_frac_chain_mem32K_40nm", @@ -3927,13 +3917,13 @@ "Latch Drivers": 1, "Pi": 5, "Po": 25, - "logic element": 153, + "logic element": 132, "latch": 25, "generic logic size": 4, - "Longest Path": 9, - "Average Path": 5, - "Estimated LUTs": 217, - "Total Node": 179 + "Longest Path": 8, + "Average Path": 4, + "Estimated LUTs": 196, + "Total Node": 158 }, "micro/bm_stmt_all_mod/k6_N10_40nm": { "test_name": "micro/bm_stmt_all_mod/k6_N10_40nm", @@ -3946,13 +3936,13 @@ "Latch Drivers": 1, "Pi": 5, "Po": 25, - "logic element": 153, + "logic element": 132, "latch": 25, "generic logic size": 6, - "Longest Path": 9, - "Average Path": 5, - "Estimated LUTs": 180, - "Total Node": 179 + "Longest Path": 8, + "Average Path": 4, + "Estimated LUTs": 159, + "Total Node": 158 }, "micro/bm_stmt_all_mod/k6_N10_mem32K_40nm": { "test_name": "micro/bm_stmt_all_mod/k6_N10_mem32K_40nm", @@ -3965,13 +3955,13 @@ "Latch Drivers": 1, "Pi": 5, "Po": 25, - "logic element": 153, + "logic element": 132, "latch": 25, "generic logic size": 6, - "Longest Path": 9, - "Average Path": 5, - "Estimated LUTs": 180, - "Total Node": 179 + "Longest Path": 8, + "Average Path": 4, + "Estimated LUTs": 159, + "Total Node": 158 }, "micro/bm_stmt_all_mod/no_arch": { "test_name": "micro/bm_stmt_all_mod/no_arch", @@ -3983,12 +3973,12 @@ "Latch Drivers": 1, "Pi": 5, "Po": 25, - "logic element": 153, + "logic element": 132, "latch": 25, - "Longest Path": 9, - "Average Path": 5, - "Estimated LUTs": 153, - "Total Node": 179 + "Longest Path": 8, + "Average Path": 4, + "Estimated LUTs": 132, + "Total Node": 158 }, "micro/bm_stmt_compare_padding/k6_frac_N10_frac_chain_mem32K_40nm": { "test_name": "micro/bm_stmt_compare_padding/k6_frac_N10_frac_chain_mem32K_40nm", @@ -4001,13 +3991,13 @@ "Latch Drivers": 1, "Pi": 5, "Po": 15, - "logic element": 96, + "logic element": 81, "latch": 15, "generic logic size": 4, - "Longest Path": 9, - "Average Path": 5, - "Estimated LUTs": 128, - "Total Node": 112 + "Longest Path": 8, + "Average Path": 4, + "Estimated LUTs": 113, + "Total Node": 97 }, "micro/bm_stmt_compare_padding/k6_N10_40nm": { "test_name": "micro/bm_stmt_compare_padding/k6_N10_40nm", @@ -4020,13 +4010,13 @@ "Latch Drivers": 1, "Pi": 5, "Po": 15, - "logic element": 96, + "logic element": 81, "latch": 15, "generic logic size": 6, - "Longest Path": 9, - "Average Path": 5, - "Estimated LUTs": 110, - "Total Node": 112 + "Longest Path": 8, + "Average Path": 4, + "Estimated LUTs": 95, + "Total Node": 97 }, "micro/bm_stmt_compare_padding/k6_N10_mem32K_40nm": { "test_name": "micro/bm_stmt_compare_padding/k6_N10_mem32K_40nm", @@ -4039,13 +4029,13 @@ "Latch Drivers": 1, "Pi": 5, "Po": 15, - "logic element": 96, + "logic element": 81, "latch": 15, "generic logic size": 6, - "Longest Path": 9, - "Average Path": 5, - "Estimated LUTs": 110, - "Total Node": 112 + "Longest Path": 8, + "Average Path": 4, + "Estimated LUTs": 95, + "Total Node": 97 }, "micro/bm_stmt_compare_padding/no_arch": { "test_name": "micro/bm_stmt_compare_padding/no_arch", @@ -4057,12 +4047,12 @@ "Latch Drivers": 1, "Pi": 5, "Po": 15, - "logic element": 96, + "logic element": 81, "latch": 15, - "Longest Path": 9, - "Average Path": 5, - "Estimated LUTs": 96, - "Total Node": 112 + "Longest Path": 8, + "Average Path": 4, + "Estimated LUTs": 81, + "Total Node": 97 }, "micro/bm_tester/k6_frac_N10_frac_chain_mem32K_40nm": { "test_name": "micro/bm_tester/k6_frac_N10_frac_chain_mem32K_40nm", @@ -4075,13 +4065,13 @@ "Latch Drivers": 1, "Pi": 4, "Po": 4, - "logic element": 89, + "logic element": 85, "latch": 4, "generic logic size": 4, - "Longest Path": 8, - "Average Path": 5, - "Estimated LUTs": 141, - "Total Node": 94 + "Longest Path": 7, + "Average Path": 4, + "Estimated LUTs": 137, + "Total Node": 90 }, "micro/bm_tester/k6_N10_40nm": { "test_name": "micro/bm_tester/k6_N10_40nm", @@ -4094,13 +4084,13 @@ "Latch Drivers": 1, "Pi": 4, "Po": 4, - "logic element": 89, + "logic element": 85, "latch": 4, "generic logic size": 6, - "Longest Path": 8, - "Average Path": 5, - "Estimated LUTs": 116, - "Total Node": 94 + "Longest Path": 7, + "Average Path": 4, + "Estimated LUTs": 112, + "Total Node": 90 }, "micro/bm_tester/k6_N10_mem32K_40nm": { "test_name": "micro/bm_tester/k6_N10_mem32K_40nm", @@ -4113,13 +4103,13 @@ "Latch Drivers": 1, "Pi": 4, "Po": 4, - "logic element": 89, + "logic element": 85, "latch": 4, "generic logic size": 6, - "Longest Path": 8, - "Average Path": 5, - "Estimated LUTs": 116, - "Total Node": 94 + "Longest Path": 7, + "Average Path": 4, + "Estimated LUTs": 112, + "Total Node": 90 }, "micro/bm_tester/no_arch": { "test_name": "micro/bm_tester/no_arch", @@ -4131,12 +4121,12 @@ "Latch Drivers": 1, "Pi": 4, "Po": 4, - "logic element": 89, + "logic element": 85, "latch": 4, - "Longest Path": 8, - "Average Path": 5, - "Estimated LUTs": 89, - "Total Node": 94 + "Longest Path": 7, + "Average Path": 4, + "Estimated LUTs": 85, + "Total Node": 90 }, "micro/case_generate/k6_frac_N10_frac_chain_mem32K_40nm": { "test_name": "micro/case_generate/k6_frac_N10_frac_chain_mem32K_40nm", @@ -4209,13 +4199,13 @@ "Latch Drivers": 1, "Pi": 2, "Po": 1, - "logic element": 4, + "logic element": 3, "latch": 1, "generic logic size": 4, - "Longest Path": 7, - "Average Path": 5, - "Estimated LUTs": 4, - "Total Node": 6 + "Longest Path": 6, + "Average Path": 4, + "Estimated LUTs": 3, + "Total Node": 5 }, "micro/ff/k6_N10_40nm": { "test_name": "micro/ff/k6_N10_40nm", @@ -4226,13 +4216,13 @@ "Latch Drivers": 1, "Pi": 2, "Po": 1, - "logic element": 4, + "logic element": 3, "latch": 1, "generic logic size": 6, - "Longest Path": 7, - "Average Path": 5, - "Estimated LUTs": 4, - "Total Node": 6 + "Longest Path": 6, + "Average Path": 4, + "Estimated LUTs": 3, + "Total Node": 5 }, "micro/ff/k6_N10_mem32K_40nm": { "test_name": "micro/ff/k6_N10_mem32K_40nm", @@ -4243,13 +4233,13 @@ "Latch Drivers": 1, "Pi": 2, "Po": 1, - "logic element": 4, + "logic element": 3, "latch": 1, "generic logic size": 6, - "Longest Path": 7, - "Average Path": 5, - "Estimated LUTs": 4, - "Total Node": 6 + "Longest Path": 6, + "Average Path": 4, + "Estimated LUTs": 3, + "Total Node": 5 }, "micro/ff/no_arch": { "test_name": "micro/ff/no_arch", @@ -4259,12 +4249,12 @@ "Latch Drivers": 1, "Pi": 2, "Po": 1, - "logic element": 4, + "logic element": 3, "latch": 1, - "Longest Path": 7, - "Average Path": 5, - "Estimated LUTs": 4, - "Total Node": 6 + "Longest Path": 6, + "Average Path": 4, + "Estimated LUTs": 3, + "Total Node": 5 }, "micro/generate/k6_frac_N10_frac_chain_mem32K_40nm": { "test_name": "micro/generate/k6_frac_N10_frac_chain_mem32K_40nm", diff --git a/ODIN_II/regression_test/benchmark/task/mixing_optimization/mults_auto_full/simulation_result.json b/ODIN_II/regression_test/benchmark/task/mixing_optimization/mults_auto_full/simulation_result.json index 2a0fc35c7f6..74070a60280 100644 --- a/ODIN_II/regression_test/benchmark/task/mixing_optimization/mults_auto_full/simulation_result.json +++ b/ODIN_II/regression_test/benchmark/task/mixing_optimization/mults_auto_full/simulation_result.json @@ -10,14 +10,14 @@ "Latch Drivers": 1, "Pi": 47, "Po": 78, - "logic element": 110, + "logic element": 63, "latch": 71, "Multiplier": 3, "generic logic size": 4, - "Longest Path": 9, + "Longest Path": 8, "Average Path": 4, - "Estimated LUTs": 110, - "Total Node": 185 + "Estimated LUTs": 63, + "Total Node": 138 }, "mults_auto_full/bm_base_multiply/k6_N10_40nm": { "test_name": "mults_auto_full/bm_base_multiply/k6_N10_40nm", @@ -30,13 +30,13 @@ "Latch Drivers": 1, "Pi": 47, "Po": 78, - "logic element": 795, + "logic element": 748, "latch": 71, "generic logic size": 6, - "Longest Path": 26, - "Average Path": 6, - "Estimated LUTs": 795, - "Total Node": 867 + "Longest Path": 25, + "Average Path": 5, + "Estimated LUTs": 748, + "Total Node": 820 }, "mults_auto_full/bm_match1_str_arch/k6_frac_N10_frac_chain_mem32K_40nm": { "test_name": "mults_auto_full/bm_match1_str_arch/k6_frac_N10_frac_chain_mem32K_40nm", @@ -49,14 +49,14 @@ "Latch Drivers": 1, "Pi": 88, "Po": 144, - "logic element": 144, + "logic element": 72, "latch": 72, "Multiplier": 3, "generic logic size": 4, - "Longest Path": 5, + "Longest Path": 4, "Average Path": 4, - "Estimated LUTs": 144, - "Total Node": 220 + "Estimated LUTs": 72, + "Total Node": 148 }, "mults_auto_full/bm_match1_str_arch/k6_N10_40nm": { "test_name": "mults_auto_full/bm_match1_str_arch/k6_N10_40nm", @@ -69,13 +69,13 @@ "Latch Drivers": 1, "Pi": 88, "Po": 144, - "logic element": 3872, + "logic element": 3800, "latch": 72, "generic logic size": 6, - "Longest Path": 74, - "Average Path": 6, - "Estimated LUTs": 3872, - "Total Node": 3945 + "Longest Path": 73, + "Average Path": 5, + "Estimated LUTs": 3800, + "Total Node": 3873 }, "mults_auto_full/bm_match2_str_arch/k6_frac_N10_frac_chain_mem32K_40nm": { "test_name": "mults_auto_full/bm_match2_str_arch/k6_frac_N10_frac_chain_mem32K_40nm", @@ -88,15 +88,15 @@ "Latch Drivers": 1, "Pi": 54, "Po": 99, - "logic element": 99, + "logic element": 45, "latch": 54, "Adder": 173, "Multiplier": 4, "generic logic size": 4, - "Longest Path": 25, + "Longest Path": 24, "Average Path": 5, - "Estimated LUTs": 99, - "Total Node": 331 + "Estimated LUTs": 45, + "Total Node": 277 }, "mults_auto_full/bm_match2_str_arch/k6_N10_40nm": { "test_name": "mults_auto_full/bm_match2_str_arch/k6_N10_40nm", @@ -109,13 +109,13 @@ "Latch Drivers": 1, "Pi": 54, "Po": 99, - "logic element": 3211, + "logic element": 3157, "latch": 54, "generic logic size": 6, - "Longest Path": 32, - "Average Path": 7, - "Estimated LUTs": 3211, - "Total Node": 3266 + "Longest Path": 31, + "Average Path": 6, + "Estimated LUTs": 3157, + "Total Node": 3212 }, "mults_auto_full/bm_match3_str_arch/k6_frac_N10_frac_chain_mem32K_40nm": { "test_name": "mults_auto_full/bm_match3_str_arch/k6_frac_N10_frac_chain_mem32K_40nm", @@ -128,15 +128,15 @@ "Latch Drivers": 1, "Pi": 54, "Po": 54, - "logic element": 54, + "logic element": 18, "latch": 54, "Adder": 50, "Multiplier": 1, "generic logic size": 4, - "Longest Path": 24, - "Average Path": 5, - "Estimated LUTs": 54, - "Total Node": 160 + "Longest Path": 23, + "Average Path": 4, + "Estimated LUTs": 18, + "Total Node": 124 }, "mults_auto_full/bm_match3_str_arch/k6_N10_40nm": { "test_name": "mults_auto_full/bm_match3_str_arch/k6_N10_40nm", @@ -149,13 +149,13 @@ "Latch Drivers": 1, "Pi": 54, "Po": 54, - "logic element": 375, + "logic element": 339, "latch": 54, "generic logic size": 6, - "Longest Path": 58, - "Average Path": 5, - "Estimated LUTs": 375, - "Total Node": 430 + "Longest Path": 57, + "Average Path": 4, + "Estimated LUTs": 339, + "Total Node": 394 }, "mults_auto_full/bm_match4_str_arch/k6_frac_N10_frac_chain_mem32K_40nm": { "test_name": "mults_auto_full/bm_match4_str_arch/k6_frac_N10_frac_chain_mem32K_40nm", @@ -168,15 +168,15 @@ "Latch Drivers": 1, "Pi": 51, "Po": 216, - "logic element": 216, + "logic element": 108, "latch": 108, "Adder": 74, "Multiplier": 3, "generic logic size": 4, - "Longest Path": 42, + "Longest Path": 41, "Average Path": 4, - "Estimated LUTs": 216, - "Total Node": 402 + "Estimated LUTs": 108, + "Total Node": 294 }, "mults_auto_full/bm_match4_str_arch/k6_N10_40nm": { "test_name": "mults_auto_full/bm_match4_str_arch/k6_N10_40nm", @@ -189,13 +189,13 @@ "Latch Drivers": 1, "Pi": 51, "Po": 216, - "logic element": 1367, + "logic element": 1259, "latch": 108, "generic logic size": 6, - "Longest Path": 49, - "Average Path": 5, - "Estimated LUTs": 1367, - "Total Node": 1476 + "Longest Path": 48, + "Average Path": 4, + "Estimated LUTs": 1259, + "Total Node": 1368 }, "mults_auto_full/bm_match5_str_arch/k6_frac_N10_frac_chain_mem32K_40nm": { "test_name": "mults_auto_full/bm_match5_str_arch/k6_frac_N10_frac_chain_mem32K_40nm", @@ -208,15 +208,13 @@ "Latch Drivers": 1, "Pi": 90, "Po": 54, - "logic element": 54, "latch": 54, "Adder": 125, "Multiplier": 6, "generic logic size": 4, - "Longest Path": 27, - "Average Path": 5, - "Estimated LUTs": 54, - "Total Node": 240 + "Longest Path": 26, + "Average Path": 4, + "Total Node": 186 }, "mults_auto_full/bm_match5_str_arch/k6_N10_40nm": { "test_name": "mults_auto_full/bm_match5_str_arch/k6_N10_40nm", @@ -229,13 +227,13 @@ "Latch Drivers": 1, "Pi": 90, "Po": 54, - "logic element": 2147, + "logic element": 2093, "latch": 54, "generic logic size": 6, - "Longest Path": 34, - "Average Path": 6, - "Estimated LUTs": 2147, - "Total Node": 2202 + "Longest Path": 33, + "Average Path": 5, + "Estimated LUTs": 2093, + "Total Node": 2148 }, "mults_auto_full/multiply_hard_block/k6_frac_N10_frac_chain_mem32K_40nm": { "test_name": "mults_auto_full/multiply_hard_block/k6_frac_N10_frac_chain_mem32K_40nm", @@ -266,14 +264,14 @@ "Latch Drivers": 1, "Pi": 5, "Po": 5, - "logic element": 12, + "logic element": 8, "latch": 4, "Multiplier": 1, "generic logic size": 4, - "Longest Path": 8, - "Average Path": 5, - "Estimated LUTs": 12, - "Total Node": 18 + "Longest Path": 7, + "Average Path": 4, + "Estimated LUTs": 8, + "Total Node": 14 }, "mults_auto_full/twobits_arithmetic_multiply/k6_N10_40nm": { "test_name": "mults_auto_full/twobits_arithmetic_multiply/k6_N10_40nm", @@ -286,13 +284,13 @@ "Latch Drivers": 1, "Pi": 5, "Po": 5, - "logic element": 21, + "logic element": 17, "latch": 4, "generic logic size": 6, - "Longest Path": 9, - "Average Path": 5, - "Estimated LUTs": 21, - "Total Node": 26 + "Longest Path": 8, + "Average Path": 4, + "Estimated LUTs": 17, + "Total Node": 22 }, "DEFAULT": { "test_name": "n/a", diff --git a/ODIN_II/regression_test/benchmark/task/mixing_optimization/mults_auto_half/simulation_result.json b/ODIN_II/regression_test/benchmark/task/mixing_optimization/mults_auto_half/simulation_result.json index 18a5f6cc018..bd30305dcde 100644 --- a/ODIN_II/regression_test/benchmark/task/mixing_optimization/mults_auto_half/simulation_result.json +++ b/ODIN_II/regression_test/benchmark/task/mixing_optimization/mults_auto_half/simulation_result.json @@ -10,14 +10,14 @@ "Latch Drivers": 1, "Pi": 47, "Po": 78, - "logic element": 454, + "logic element": 407, "latch": 71, "Multiplier": 1, "generic logic size": 4, "Longest Path": 25, "Average Path": 5, - "Estimated LUTs": 454, - "Total Node": 527 + "Estimated LUTs": 407, + "Total Node": 480 }, "mults_auto_half/bm_base_multiply/k6_N10_40nm": { "test_name": "mults_auto_half/bm_base_multiply/k6_N10_40nm", @@ -30,13 +30,13 @@ "Latch Drivers": 1, "Pi": 47, "Po": 78, - "logic element": 795, + "logic element": 748, "latch": 71, "generic logic size": 6, - "Longest Path": 26, - "Average Path": 6, - "Estimated LUTs": 795, - "Total Node": 867 + "Longest Path": 25, + "Average Path": 5, + "Estimated LUTs": 748, + "Total Node": 820 }, "mults_auto_half/bm_match1_str_arch/k6_frac_N10_frac_chain_mem32K_40nm": { "test_name": "mults_auto_half/bm_match1_str_arch/k6_frac_N10_frac_chain_mem32K_40nm", @@ -49,14 +49,14 @@ "Latch Drivers": 1, "Pi": 88, "Po": 144, - "logic element": 1775, + "logic element": 1703, "latch": 72, "Multiplier": 1, "generic logic size": 4, - "Longest Path": 74, + "Longest Path": 73, "Average Path": 5, - "Estimated LUTs": 1775, - "Total Node": 1849 + "Estimated LUTs": 1703, + "Total Node": 1777 }, "mults_auto_half/bm_match1_str_arch/k6_N10_40nm": { "test_name": "mults_auto_half/bm_match1_str_arch/k6_N10_40nm", @@ -69,13 +69,13 @@ "Latch Drivers": 1, "Pi": 88, "Po": 144, - "logic element": 3872, + "logic element": 3800, "latch": 72, "generic logic size": 6, - "Longest Path": 74, - "Average Path": 6, - "Estimated LUTs": 3872, - "Total Node": 3945 + "Longest Path": 73, + "Average Path": 5, + "Estimated LUTs": 3800, + "Total Node": 3873 }, "mults_auto_half/bm_match2_str_arch/k6_frac_N10_frac_chain_mem32K_40nm": { "test_name": "mults_auto_half/bm_match2_str_arch/k6_frac_N10_frac_chain_mem32K_40nm", @@ -88,15 +88,15 @@ "Latch Drivers": 1, "Pi": 54, "Po": 99, - "logic element": 565, + "logic element": 511, "latch": 54, "Adder": 173, "Multiplier": 2, "generic logic size": 4, - "Longest Path": 31, - "Average Path": 6, - "Estimated LUTs": 565, - "Total Node": 795 + "Longest Path": 30, + "Average Path": 5, + "Estimated LUTs": 511, + "Total Node": 741 }, "mults_auto_half/bm_match2_str_arch/k6_N10_40nm": { "test_name": "mults_auto_half/bm_match2_str_arch/k6_N10_40nm", @@ -109,13 +109,13 @@ "Latch Drivers": 1, "Pi": 54, "Po": 99, - "logic element": 3211, + "logic element": 3157, "latch": 54, "generic logic size": 6, - "Longest Path": 32, - "Average Path": 7, - "Estimated LUTs": 3211, - "Total Node": 3266 + "Longest Path": 31, + "Average Path": 6, + "Estimated LUTs": 3157, + "Total Node": 3212 }, "mults_auto_half/bm_match3_str_arch/k6_frac_N10_frac_chain_mem32K_40nm": { "test_name": "mults_auto_half/bm_match3_str_arch/k6_frac_N10_frac_chain_mem32K_40nm", @@ -128,14 +128,14 @@ "Latch Drivers": 1, "Pi": 54, "Po": 54, - "logic element": 287, + "logic element": 251, "latch": 54, "Adder": 50, "generic logic size": 4, - "Longest Path": 31, - "Average Path": 5, - "Estimated LUTs": 287, - "Total Node": 392 + "Longest Path": 30, + "Average Path": 4, + "Estimated LUTs": 251, + "Total Node": 356 }, "mults_auto_half/bm_match3_str_arch/k6_N10_40nm": { "test_name": "mults_auto_half/bm_match3_str_arch/k6_N10_40nm", @@ -148,13 +148,13 @@ "Latch Drivers": 1, "Pi": 54, "Po": 54, - "logic element": 375, + "logic element": 339, "latch": 54, "generic logic size": 6, - "Longest Path": 58, - "Average Path": 5, - "Estimated LUTs": 375, - "Total Node": 430 + "Longest Path": 57, + "Average Path": 4, + "Estimated LUTs": 339, + "Total Node": 394 }, "mults_auto_half/bm_match4_str_arch/k6_frac_N10_frac_chain_mem32K_40nm": { "test_name": "mults_auto_half/bm_match4_str_arch/k6_frac_N10_frac_chain_mem32K_40nm", @@ -167,15 +167,15 @@ "Latch Drivers": 1, "Pi": 51, "Po": 216, - "logic element": 604, + "logic element": 496, "latch": 108, "Adder": 74, "Multiplier": 1, "generic logic size": 4, - "Longest Path": 48, - "Average Path": 5, - "Estimated LUTs": 604, - "Total Node": 788 + "Longest Path": 47, + "Average Path": 4, + "Estimated LUTs": 496, + "Total Node": 680 }, "mults_auto_half/bm_match4_str_arch/k6_N10_40nm": { "test_name": "mults_auto_half/bm_match4_str_arch/k6_N10_40nm", @@ -188,13 +188,13 @@ "Latch Drivers": 1, "Pi": 51, "Po": 216, - "logic element": 1367, + "logic element": 1259, "latch": 108, "generic logic size": 6, - "Longest Path": 49, - "Average Path": 5, - "Estimated LUTs": 1367, - "Total Node": 1476 + "Longest Path": 48, + "Average Path": 4, + "Estimated LUTs": 1259, + "Total Node": 1368 }, "mults_auto_half/bm_match5_str_arch/k6_frac_N10_frac_chain_mem32K_40nm": { "test_name": "mults_auto_half/bm_match5_str_arch/k6_frac_N10_frac_chain_mem32K_40nm", @@ -207,15 +207,15 @@ "Latch Drivers": 1, "Pi": 90, "Po": 54, - "logic element": 753, + "logic element": 699, "latch": 54, "Adder": 125, "Multiplier": 3, "generic logic size": 4, - "Longest Path": 32, - "Average Path": 5, - "Estimated LUTs": 753, - "Total Node": 936 + "Longest Path": 31, + "Average Path": 4, + "Estimated LUTs": 699, + "Total Node": 882 }, "mults_auto_half/bm_match5_str_arch/k6_N10_40nm": { "test_name": "mults_auto_half/bm_match5_str_arch/k6_N10_40nm", @@ -228,13 +228,13 @@ "Latch Drivers": 1, "Pi": 90, "Po": 54, - "logic element": 2147, + "logic element": 2093, "latch": 54, "generic logic size": 6, - "Longest Path": 34, - "Average Path": 6, - "Estimated LUTs": 2147, - "Total Node": 2202 + "Longest Path": 33, + "Average Path": 5, + "Estimated LUTs": 2093, + "Total Node": 2148 }, "mults_auto_half/multiply_hard_block/k6_frac_N10_frac_chain_mem32K_40nm": { "test_name": "mults_auto_half/multiply_hard_block/k6_frac_N10_frac_chain_mem32K_40nm", @@ -265,13 +265,13 @@ "Latch Drivers": 1, "Pi": 5, "Po": 5, - "logic element": 21, + "logic element": 17, "latch": 4, "generic logic size": 4, - "Longest Path": 9, - "Average Path": 5, - "Estimated LUTs": 21, - "Total Node": 26 + "Longest Path": 8, + "Average Path": 4, + "Estimated LUTs": 17, + "Total Node": 22 }, "mults_auto_half/twobits_arithmetic_multiply/k6_N10_40nm": { "test_name": "mults_auto_half/twobits_arithmetic_multiply/k6_N10_40nm", @@ -284,13 +284,13 @@ "Latch Drivers": 1, "Pi": 5, "Po": 5, - "logic element": 21, + "logic element": 17, "latch": 4, "generic logic size": 6, - "Longest Path": 9, - "Average Path": 5, - "Estimated LUTs": 21, - "Total Node": 26 + "Longest Path": 8, + "Average Path": 4, + "Estimated LUTs": 17, + "Total Node": 22 }, "DEFAULT": { "test_name": "n/a", diff --git a/ODIN_II/regression_test/benchmark/task/mixing_optimization/mults_auto_none/simulation_result.json b/ODIN_II/regression_test/benchmark/task/mixing_optimization/mults_auto_none/simulation_result.json index 83e9e9c2fd8..73f64ef71db 100644 --- a/ODIN_II/regression_test/benchmark/task/mixing_optimization/mults_auto_none/simulation_result.json +++ b/ODIN_II/regression_test/benchmark/task/mixing_optimization/mults_auto_none/simulation_result.json @@ -10,13 +10,13 @@ "Latch Drivers": 1, "Pi": 47, "Po": 78, - "logic element": 637, + "logic element": 590, "latch": 71, "generic logic size": 4, - "Longest Path": 26, - "Average Path": 6, - "Estimated LUTs": 637, - "Total Node": 709 + "Longest Path": 25, + "Average Path": 5, + "Estimated LUTs": 590, + "Total Node": 662 }, "mults_auto_none/bm_base_multiply/k6_N10_40nm": { "test_name": "mults_auto_none/bm_base_multiply/k6_N10_40nm", @@ -29,13 +29,13 @@ "Latch Drivers": 1, "Pi": 47, "Po": 78, - "logic element": 795, + "logic element": 748, "latch": 71, "generic logic size": 6, - "Longest Path": 26, - "Average Path": 6, - "Estimated LUTs": 795, - "Total Node": 867 + "Longest Path": 25, + "Average Path": 5, + "Estimated LUTs": 748, + "Total Node": 820 }, "mults_auto_none/bm_match1_str_arch/k6_frac_N10_frac_chain_mem32K_40nm": { "test_name": "mults_auto_none/bm_match1_str_arch/k6_frac_N10_frac_chain_mem32K_40nm", @@ -48,13 +48,13 @@ "Latch Drivers": 1, "Pi": 88, "Po": 144, - "logic element": 2008, + "logic element": 1936, "latch": 72, "generic logic size": 4, - "Longest Path": 74, - "Average Path": 6, - "Estimated LUTs": 2008, - "Total Node": 2081 + "Longest Path": 73, + "Average Path": 5, + "Estimated LUTs": 1936, + "Total Node": 2009 }, "mults_auto_none/bm_match1_str_arch/k6_N10_40nm": { "test_name": "mults_auto_none/bm_match1_str_arch/k6_N10_40nm", @@ -67,13 +67,13 @@ "Latch Drivers": 1, "Pi": 88, "Po": 144, - "logic element": 3872, + "logic element": 3800, "latch": 72, "generic logic size": 6, - "Longest Path": 74, - "Average Path": 6, - "Estimated LUTs": 3872, - "Total Node": 3945 + "Longest Path": 73, + "Average Path": 5, + "Estimated LUTs": 3800, + "Total Node": 3873 }, "mults_auto_none/bm_match2_str_arch/k6_frac_N10_frac_chain_mem32K_40nm": { "test_name": "mults_auto_none/bm_match2_str_arch/k6_frac_N10_frac_chain_mem32K_40nm", @@ -86,14 +86,14 @@ "Latch Drivers": 1, "Pi": 54, "Po": 99, - "logic element": 1031, + "logic element": 977, "latch": 54, "Adder": 173, "generic logic size": 4, - "Longest Path": 32, - "Average Path": 7, - "Estimated LUTs": 1031, - "Total Node": 1259 + "Longest Path": 31, + "Average Path": 6, + "Estimated LUTs": 977, + "Total Node": 1205 }, "mults_auto_none/bm_match2_str_arch/k6_N10_40nm": { "test_name": "mults_auto_none/bm_match2_str_arch/k6_N10_40nm", @@ -106,13 +106,13 @@ "Latch Drivers": 1, "Pi": 54, "Po": 99, - "logic element": 3211, + "logic element": 3157, "latch": 54, "generic logic size": 6, - "Longest Path": 32, - "Average Path": 7, - "Estimated LUTs": 3211, - "Total Node": 3266 + "Longest Path": 31, + "Average Path": 6, + "Estimated LUTs": 3157, + "Total Node": 3212 }, "mults_auto_none/bm_match3_str_arch/k6_frac_N10_frac_chain_mem32K_40nm": { "test_name": "mults_auto_none/bm_match3_str_arch/k6_frac_N10_frac_chain_mem32K_40nm", @@ -125,14 +125,14 @@ "Latch Drivers": 1, "Pi": 54, "Po": 54, - "logic element": 287, + "logic element": 251, "latch": 54, "Adder": 50, "generic logic size": 4, - "Longest Path": 31, - "Average Path": 5, - "Estimated LUTs": 287, - "Total Node": 392 + "Longest Path": 30, + "Average Path": 4, + "Estimated LUTs": 251, + "Total Node": 356 }, "mults_auto_none/bm_match3_str_arch/k6_N10_40nm": { "test_name": "mults_auto_none/bm_match3_str_arch/k6_N10_40nm", @@ -145,13 +145,13 @@ "Latch Drivers": 1, "Pi": 54, "Po": 54, - "logic element": 375, + "logic element": 339, "latch": 54, "generic logic size": 6, - "Longest Path": 58, - "Average Path": 5, - "Estimated LUTs": 375, - "Total Node": 430 + "Longest Path": 57, + "Average Path": 4, + "Estimated LUTs": 339, + "Total Node": 394 }, "mults_auto_none/bm_match4_str_arch/k6_frac_N10_frac_chain_mem32K_40nm": { "test_name": "mults_auto_none/bm_match4_str_arch/k6_frac_N10_frac_chain_mem32K_40nm", @@ -164,14 +164,14 @@ "Latch Drivers": 1, "Pi": 51, "Po": 216, - "logic element": 837, + "logic element": 729, "latch": 108, "Adder": 74, "generic logic size": 4, - "Longest Path": 49, - "Average Path": 5, - "Estimated LUTs": 837, - "Total Node": 1020 + "Longest Path": 48, + "Average Path": 4, + "Estimated LUTs": 729, + "Total Node": 912 }, "mults_auto_none/bm_match4_str_arch/k6_N10_40nm": { "test_name": "mults_auto_none/bm_match4_str_arch/k6_N10_40nm", @@ -184,13 +184,13 @@ "Latch Drivers": 1, "Pi": 51, "Po": 216, - "logic element": 1367, + "logic element": 1259, "latch": 108, "generic logic size": 6, - "Longest Path": 49, - "Average Path": 5, - "Estimated LUTs": 1367, - "Total Node": 1476 + "Longest Path": 48, + "Average Path": 4, + "Estimated LUTs": 1259, + "Total Node": 1368 }, "mults_auto_none/bm_match5_str_arch/k6_frac_N10_frac_chain_mem32K_40nm": { "test_name": "mults_auto_none/bm_match5_str_arch/k6_frac_N10_frac_chain_mem32K_40nm", @@ -203,14 +203,14 @@ "Latch Drivers": 1, "Pi": 90, "Po": 54, - "logic element": 1452, + "logic element": 1398, "latch": 54, "Adder": 125, "generic logic size": 4, - "Longest Path": 34, - "Average Path": 6, - "Estimated LUTs": 1452, - "Total Node": 1632 + "Longest Path": 33, + "Average Path": 5, + "Estimated LUTs": 1398, + "Total Node": 1578 }, "mults_auto_none/bm_match5_str_arch/k6_N10_40nm": { "test_name": "mults_auto_none/bm_match5_str_arch/k6_N10_40nm", @@ -223,13 +223,13 @@ "Latch Drivers": 1, "Pi": 90, "Po": 54, - "logic element": 2147, + "logic element": 2093, "latch": 54, "generic logic size": 6, - "Longest Path": 34, - "Average Path": 6, - "Estimated LUTs": 2147, - "Total Node": 2202 + "Longest Path": 33, + "Average Path": 5, + "Estimated LUTs": 2093, + "Total Node": 2148 }, "mults_auto_none/multiply_hard_block/k6_frac_N10_frac_chain_mem32K_40nm": { "test_name": "mults_auto_none/multiply_hard_block/k6_frac_N10_frac_chain_mem32K_40nm", @@ -259,13 +259,13 @@ "Latch Drivers": 1, "Pi": 5, "Po": 5, - "logic element": 21, + "logic element": 17, "latch": 4, "generic logic size": 4, - "Longest Path": 9, - "Average Path": 5, - "Estimated LUTs": 21, - "Total Node": 26 + "Longest Path": 8, + "Average Path": 4, + "Estimated LUTs": 17, + "Total Node": 22 }, "mults_auto_none/twobits_arithmetic_multiply/k6_N10_40nm": { "test_name": "mults_auto_none/twobits_arithmetic_multiply/k6_N10_40nm", @@ -278,13 +278,13 @@ "Latch Drivers": 1, "Pi": 5, "Po": 5, - "logic element": 21, + "logic element": 17, "latch": 4, "generic logic size": 6, - "Longest Path": 9, - "Average Path": 5, - "Estimated LUTs": 21, - "Total Node": 26 + "Longest Path": 8, + "Average Path": 4, + "Estimated LUTs": 17, + "Total Node": 22 }, "DEFAULT": { "test_name": "n/a", diff --git a/ODIN_II/regression_test/benchmark/task/operators/simulation_result.json b/ODIN_II/regression_test/benchmark/task/operators/simulation_result.json index d72c403ddcb..d71684e1382 100644 --- a/ODIN_II/regression_test/benchmark/task/operators/simulation_result.json +++ b/ODIN_II/regression_test/benchmark/task/operators/simulation_result.json @@ -10,13 +10,13 @@ "Latch Drivers": 1, "Pi": 10, "Po": 16, - "logic element": 36, + "logic element": 20, "latch": 16, "generic logic size": 4, - "Longest Path": 7, - "Average Path": 5, - "Estimated LUTs": 36, - "Total Node": 53 + "Longest Path": 6, + "Average Path": 4, + "Estimated LUTs": 20, + "Total Node": 37 }, "operators/asr_16_7/k6_N10_40nm": { "test_name": "operators/asr_16_7/k6_N10_40nm", @@ -29,13 +29,13 @@ "Latch Drivers": 1, "Pi": 10, "Po": 16, - "logic element": 36, + "logic element": 20, "latch": 16, "generic logic size": 6, - "Longest Path": 7, - "Average Path": 5, - "Estimated LUTs": 36, - "Total Node": 53 + "Longest Path": 6, + "Average Path": 4, + "Estimated LUTs": 20, + "Total Node": 37 }, "operators/asr_16_7/k6_N10_mem32K_40nm": { "test_name": "operators/asr_16_7/k6_N10_mem32K_40nm", @@ -48,13 +48,13 @@ "Latch Drivers": 1, "Pi": 10, "Po": 16, - "logic element": 36, + "logic element": 20, "latch": 16, "generic logic size": 6, - "Longest Path": 7, - "Average Path": 5, - "Estimated LUTs": 36, - "Total Node": 53 + "Longest Path": 6, + "Average Path": 4, + "Estimated LUTs": 20, + "Total Node": 37 }, "operators/asr_16_7/no_arch": { "test_name": "operators/asr_16_7/no_arch", @@ -66,12 +66,12 @@ "Latch Drivers": 1, "Pi": 10, "Po": 16, - "logic element": 36, + "logic element": 20, "latch": 16, - "Longest Path": 7, - "Average Path": 5, - "Estimated LUTs": 36, - "Total Node": 53 + "Longest Path": 6, + "Average Path": 4, + "Estimated LUTs": 20, + "Total Node": 37 }, "operators/asr_8_1/k6_frac_N10_frac_chain_mem32K_40nm": { "test_name": "operators/asr_8_1/k6_frac_N10_frac_chain_mem32K_40nm", @@ -84,13 +84,13 @@ "Latch Drivers": 1, "Pi": 8, "Po": 8, - "logic element": 20, + "logic element": 12, "latch": 8, "generic logic size": 4, - "Longest Path": 7, - "Average Path": 5, - "Estimated LUTs": 20, - "Total Node": 29 + "Longest Path": 6, + "Average Path": 4, + "Estimated LUTs": 12, + "Total Node": 21 }, "operators/asr_8_1/k6_N10_40nm": { "test_name": "operators/asr_8_1/k6_N10_40nm", @@ -103,13 +103,13 @@ "Latch Drivers": 1, "Pi": 8, "Po": 8, - "logic element": 20, + "logic element": 12, "latch": 8, "generic logic size": 6, - "Longest Path": 7, - "Average Path": 5, - "Estimated LUTs": 20, - "Total Node": 29 + "Longest Path": 6, + "Average Path": 4, + "Estimated LUTs": 12, + "Total Node": 21 }, "operators/asr_8_1/k6_N10_mem32K_40nm": { "test_name": "operators/asr_8_1/k6_N10_mem32K_40nm", @@ -122,13 +122,13 @@ "Latch Drivers": 1, "Pi": 8, "Po": 8, - "logic element": 20, + "logic element": 12, "latch": 8, "generic logic size": 6, - "Longest Path": 7, - "Average Path": 5, - "Estimated LUTs": 20, - "Total Node": 29 + "Longest Path": 6, + "Average Path": 4, + "Estimated LUTs": 12, + "Total Node": 21 }, "operators/asr_8_1/no_arch": { "test_name": "operators/asr_8_1/no_arch", @@ -140,12 +140,12 @@ "Latch Drivers": 1, "Pi": 8, "Po": 8, - "logic element": 20, + "logic element": 12, "latch": 8, - "Longest Path": 7, - "Average Path": 5, - "Estimated LUTs": 20, - "Total Node": 29 + "Longest Path": 6, + "Average Path": 4, + "Estimated LUTs": 12, + "Total Node": 21 }, "operators/asr_8_2/k6_frac_N10_frac_chain_mem32K_40nm": { "test_name": "operators/asr_8_2/k6_frac_N10_frac_chain_mem32K_40nm", @@ -158,13 +158,13 @@ "Latch Drivers": 1, "Pi": 7, "Po": 8, - "logic element": 20, + "logic element": 12, "latch": 8, "generic logic size": 4, - "Longest Path": 7, - "Average Path": 5, - "Estimated LUTs": 20, - "Total Node": 29 + "Longest Path": 6, + "Average Path": 4, + "Estimated LUTs": 12, + "Total Node": 21 }, "operators/asr_8_2/k6_N10_40nm": { "test_name": "operators/asr_8_2/k6_N10_40nm", @@ -177,13 +177,13 @@ "Latch Drivers": 1, "Pi": 7, "Po": 8, - "logic element": 20, + "logic element": 12, "latch": 8, "generic logic size": 6, - "Longest Path": 7, - "Average Path": 5, - "Estimated LUTs": 20, - "Total Node": 29 + "Longest Path": 6, + "Average Path": 4, + "Estimated LUTs": 12, + "Total Node": 21 }, "operators/asr_8_2/k6_N10_mem32K_40nm": { "test_name": "operators/asr_8_2/k6_N10_mem32K_40nm", @@ -196,13 +196,13 @@ "Latch Drivers": 1, "Pi": 7, "Po": 8, - "logic element": 20, + "logic element": 12, "latch": 8, "generic logic size": 6, - "Longest Path": 7, - "Average Path": 5, - "Estimated LUTs": 20, - "Total Node": 29 + "Longest Path": 6, + "Average Path": 4, + "Estimated LUTs": 12, + "Total Node": 21 }, "operators/asr_8_2/no_arch": { "test_name": "operators/asr_8_2/no_arch", @@ -214,12 +214,12 @@ "Latch Drivers": 1, "Pi": 7, "Po": 8, - "logic element": 20, + "logic element": 12, "latch": 8, - "Longest Path": 7, - "Average Path": 5, - "Estimated LUTs": 20, - "Total Node": 29 + "Longest Path": 6, + "Average Path": 4, + "Estimated LUTs": 12, + "Total Node": 21 }, "operators/asr_8_3/k6_frac_N10_frac_chain_mem32K_40nm": { "test_name": "operators/asr_8_3/k6_frac_N10_frac_chain_mem32K_40nm", @@ -232,13 +232,13 @@ "Latch Drivers": 1, "Pi": 6, "Po": 8, - "logic element": 20, + "logic element": 12, "latch": 8, "generic logic size": 4, - "Longest Path": 7, - "Average Path": 5, - "Estimated LUTs": 20, - "Total Node": 29 + "Longest Path": 6, + "Average Path": 4, + "Estimated LUTs": 12, + "Total Node": 21 }, "operators/asr_8_3/k6_N10_40nm": { "test_name": "operators/asr_8_3/k6_N10_40nm", @@ -251,13 +251,13 @@ "Latch Drivers": 1, "Pi": 6, "Po": 8, - "logic element": 20, + "logic element": 12, "latch": 8, "generic logic size": 6, - "Longest Path": 7, - "Average Path": 5, - "Estimated LUTs": 20, - "Total Node": 29 + "Longest Path": 6, + "Average Path": 4, + "Estimated LUTs": 12, + "Total Node": 21 }, "operators/asr_8_3/k6_N10_mem32K_40nm": { "test_name": "operators/asr_8_3/k6_N10_mem32K_40nm", @@ -270,13 +270,13 @@ "Latch Drivers": 1, "Pi": 6, "Po": 8, - "logic element": 20, + "logic element": 12, "latch": 8, "generic logic size": 6, - "Longest Path": 7, - "Average Path": 5, - "Estimated LUTs": 20, - "Total Node": 29 + "Longest Path": 6, + "Average Path": 4, + "Estimated LUTs": 12, + "Total Node": 21 }, "operators/asr_8_3/no_arch": { "test_name": "operators/asr_8_3/no_arch", @@ -288,12 +288,12 @@ "Latch Drivers": 1, "Pi": 6, "Po": 8, - "logic element": 20, + "logic element": 12, "latch": 8, - "Longest Path": 7, - "Average Path": 5, - "Estimated LUTs": 20, - "Total Node": 29 + "Longest Path": 6, + "Average Path": 4, + "Estimated LUTs": 12, + "Total Node": 21 }, "operators/asr_8_4/k6_frac_N10_frac_chain_mem32K_40nm": { "test_name": "operators/asr_8_4/k6_frac_N10_frac_chain_mem32K_40nm", @@ -306,13 +306,13 @@ "Latch Drivers": 1, "Pi": 5, "Po": 8, - "logic element": 20, + "logic element": 12, "latch": 8, "generic logic size": 4, - "Longest Path": 7, - "Average Path": 5, - "Estimated LUTs": 20, - "Total Node": 29 + "Longest Path": 6, + "Average Path": 4, + "Estimated LUTs": 12, + "Total Node": 21 }, "operators/asr_8_4/k6_N10_40nm": { "test_name": "operators/asr_8_4/k6_N10_40nm", @@ -325,13 +325,13 @@ "Latch Drivers": 1, "Pi": 5, "Po": 8, - "logic element": 20, + "logic element": 12, "latch": 8, "generic logic size": 6, - "Longest Path": 7, - "Average Path": 5, - "Estimated LUTs": 20, - "Total Node": 29 + "Longest Path": 6, + "Average Path": 4, + "Estimated LUTs": 12, + "Total Node": 21 }, "operators/asr_8_4/k6_N10_mem32K_40nm": { "test_name": "operators/asr_8_4/k6_N10_mem32K_40nm", @@ -344,13 +344,13 @@ "Latch Drivers": 1, "Pi": 5, "Po": 8, - "logic element": 20, + "logic element": 12, "latch": 8, "generic logic size": 6, - "Longest Path": 7, - "Average Path": 5, - "Estimated LUTs": 20, - "Total Node": 29 + "Longest Path": 6, + "Average Path": 4, + "Estimated LUTs": 12, + "Total Node": 21 }, "operators/asr_8_4/no_arch": { "test_name": "operators/asr_8_4/no_arch", @@ -362,12 +362,12 @@ "Latch Drivers": 1, "Pi": 5, "Po": 8, - "logic element": 20, + "logic element": 12, "latch": 8, - "Longest Path": 7, - "Average Path": 5, - "Estimated LUTs": 20, - "Total Node": 29 + "Longest Path": 6, + "Average Path": 4, + "Estimated LUTs": 12, + "Total Node": 21 }, "operators/asr_8_5/k6_frac_N10_frac_chain_mem32K_40nm": { "test_name": "operators/asr_8_5/k6_frac_N10_frac_chain_mem32K_40nm", @@ -380,13 +380,13 @@ "Latch Drivers": 1, "Pi": 4, "Po": 8, - "logic element": 20, + "logic element": 12, "latch": 8, "generic logic size": 4, - "Longest Path": 7, - "Average Path": 5, - "Estimated LUTs": 20, - "Total Node": 29 + "Longest Path": 6, + "Average Path": 4, + "Estimated LUTs": 12, + "Total Node": 21 }, "operators/asr_8_5/k6_N10_40nm": { "test_name": "operators/asr_8_5/k6_N10_40nm", @@ -399,13 +399,13 @@ "Latch Drivers": 1, "Pi": 4, "Po": 8, - "logic element": 20, + "logic element": 12, "latch": 8, "generic logic size": 6, - "Longest Path": 7, - "Average Path": 5, - "Estimated LUTs": 20, - "Total Node": 29 + "Longest Path": 6, + "Average Path": 4, + "Estimated LUTs": 12, + "Total Node": 21 }, "operators/asr_8_5/k6_N10_mem32K_40nm": { "test_name": "operators/asr_8_5/k6_N10_mem32K_40nm", @@ -418,13 +418,13 @@ "Latch Drivers": 1, "Pi": 4, "Po": 8, - "logic element": 20, + "logic element": 12, "latch": 8, "generic logic size": 6, - "Longest Path": 7, - "Average Path": 5, - "Estimated LUTs": 20, - "Total Node": 29 + "Longest Path": 6, + "Average Path": 4, + "Estimated LUTs": 12, + "Total Node": 21 }, "operators/asr_8_5/no_arch": { "test_name": "operators/asr_8_5/no_arch", @@ -436,12 +436,12 @@ "Latch Drivers": 1, "Pi": 4, "Po": 8, - "logic element": 20, + "logic element": 12, "latch": 8, - "Longest Path": 7, - "Average Path": 5, - "Estimated LUTs": 20, - "Total Node": 29 + "Longest Path": 6, + "Average Path": 4, + "Estimated LUTs": 12, + "Total Node": 21 }, "operators/asr_8_6/k6_frac_N10_frac_chain_mem32K_40nm": { "test_name": "operators/asr_8_6/k6_frac_N10_frac_chain_mem32K_40nm", @@ -454,13 +454,13 @@ "Latch Drivers": 1, "Pi": 3, "Po": 8, - "logic element": 20, + "logic element": 12, "latch": 8, "generic logic size": 4, - "Longest Path": 7, - "Average Path": 5, - "Estimated LUTs": 20, - "Total Node": 29 + "Longest Path": 6, + "Average Path": 4, + "Estimated LUTs": 12, + "Total Node": 21 }, "operators/asr_8_6/k6_N10_40nm": { "test_name": "operators/asr_8_6/k6_N10_40nm", @@ -473,13 +473,13 @@ "Latch Drivers": 1, "Pi": 3, "Po": 8, - "logic element": 20, + "logic element": 12, "latch": 8, "generic logic size": 6, - "Longest Path": 7, - "Average Path": 5, - "Estimated LUTs": 20, - "Total Node": 29 + "Longest Path": 6, + "Average Path": 4, + "Estimated LUTs": 12, + "Total Node": 21 }, "operators/asr_8_6/k6_N10_mem32K_40nm": { "test_name": "operators/asr_8_6/k6_N10_mem32K_40nm", @@ -492,13 +492,13 @@ "Latch Drivers": 1, "Pi": 3, "Po": 8, - "logic element": 20, + "logic element": 12, "latch": 8, "generic logic size": 6, - "Longest Path": 7, - "Average Path": 5, - "Estimated LUTs": 20, - "Total Node": 29 + "Longest Path": 6, + "Average Path": 4, + "Estimated LUTs": 12, + "Total Node": 21 }, "operators/asr_8_6/no_arch": { "test_name": "operators/asr_8_6/no_arch", @@ -510,12 +510,12 @@ "Latch Drivers": 1, "Pi": 3, "Po": 8, - "logic element": 20, + "logic element": 12, "latch": 8, - "Longest Path": 7, - "Average Path": 5, - "Estimated LUTs": 20, - "Total Node": 29 + "Longest Path": 6, + "Average Path": 4, + "Estimated LUTs": 12, + "Total Node": 21 }, "operators/asr_8_7/k6_frac_N10_frac_chain_mem32K_40nm": { "test_name": "operators/asr_8_7/k6_frac_N10_frac_chain_mem32K_40nm", @@ -528,13 +528,13 @@ "Latch Drivers": 1, "Pi": 2, "Po": 8, - "logic element": 20, + "logic element": 12, "latch": 8, "generic logic size": 4, - "Longest Path": 7, - "Average Path": 5, - "Estimated LUTs": 20, - "Total Node": 29 + "Longest Path": 6, + "Average Path": 4, + "Estimated LUTs": 12, + "Total Node": 21 }, "operators/asr_8_7/k6_N10_40nm": { "test_name": "operators/asr_8_7/k6_N10_40nm", @@ -547,13 +547,13 @@ "Latch Drivers": 1, "Pi": 2, "Po": 8, - "logic element": 20, + "logic element": 12, "latch": 8, "generic logic size": 6, - "Longest Path": 7, - "Average Path": 5, - "Estimated LUTs": 20, - "Total Node": 29 + "Longest Path": 6, + "Average Path": 4, + "Estimated LUTs": 12, + "Total Node": 21 }, "operators/asr_8_7/k6_N10_mem32K_40nm": { "test_name": "operators/asr_8_7/k6_N10_mem32K_40nm", @@ -566,13 +566,13 @@ "Latch Drivers": 1, "Pi": 2, "Po": 8, - "logic element": 20, + "logic element": 12, "latch": 8, "generic logic size": 6, - "Longest Path": 7, - "Average Path": 5, - "Estimated LUTs": 20, - "Total Node": 29 + "Longest Path": 6, + "Average Path": 4, + "Estimated LUTs": 12, + "Total Node": 21 }, "operators/asr_8_7/no_arch": { "test_name": "operators/asr_8_7/no_arch", @@ -584,12 +584,12 @@ "Latch Drivers": 1, "Pi": 2, "Po": 8, - "logic element": 20, + "logic element": 12, "latch": 8, - "Longest Path": 7, - "Average Path": 5, - "Estimated LUTs": 20, - "Total Node": 29 + "Longest Path": 6, + "Average Path": 4, + "Estimated LUTs": 12, + "Total Node": 21 }, "operators/binary_and/k6_frac_N10_frac_chain_mem32K_40nm": { "test_name": "operators/binary_and/k6_frac_N10_frac_chain_mem32K_40nm", @@ -602,13 +602,13 @@ "Latch Drivers": 1, "Pi": 3, "Po": 2, - "logic element": 7, + "logic element": 6, "latch": 1, "generic logic size": 4, - "Longest Path": 8, + "Longest Path": 7, "Average Path": 4, - "Estimated LUTs": 7, - "Total Node": 9 + "Estimated LUTs": 6, + "Total Node": 8 }, "operators/binary_and/k6_N10_40nm": { "test_name": "operators/binary_and/k6_N10_40nm", @@ -621,13 +621,13 @@ "Latch Drivers": 1, "Pi": 3, "Po": 2, - "logic element": 7, + "logic element": 6, "latch": 1, "generic logic size": 6, - "Longest Path": 8, + "Longest Path": 7, "Average Path": 4, - "Estimated LUTs": 7, - "Total Node": 9 + "Estimated LUTs": 6, + "Total Node": 8 }, "operators/binary_and/k6_N10_mem32K_40nm": { "test_name": "operators/binary_and/k6_N10_mem32K_40nm", @@ -640,13 +640,13 @@ "Latch Drivers": 1, "Pi": 3, "Po": 2, - "logic element": 7, + "logic element": 6, "latch": 1, "generic logic size": 6, - "Longest Path": 8, + "Longest Path": 7, "Average Path": 4, - "Estimated LUTs": 7, - "Total Node": 9 + "Estimated LUTs": 6, + "Total Node": 8 }, "operators/binary_and/no_arch": { "test_name": "operators/binary_and/no_arch", @@ -658,12 +658,12 @@ "Latch Drivers": 1, "Pi": 3, "Po": 2, - "logic element": 7, + "logic element": 6, "latch": 1, - "Longest Path": 8, + "Longest Path": 7, "Average Path": 4, - "Estimated LUTs": 7, - "Total Node": 9 + "Estimated LUTs": 6, + "Total Node": 8 }, "operators/binary_logical_and/k6_frac_N10_frac_chain_mem32K_40nm": { "test_name": "operators/binary_logical_and/k6_frac_N10_frac_chain_mem32K_40nm", @@ -676,13 +676,13 @@ "Latch Drivers": 1, "Pi": 3, "Po": 2, - "logic element": 9, + "logic element": 8, "latch": 1, "generic logic size": 4, - "Longest Path": 8, + "Longest Path": 7, "Average Path": 4, - "Estimated LUTs": 9, - "Total Node": 11 + "Estimated LUTs": 8, + "Total Node": 10 }, "operators/binary_logical_and/k6_N10_40nm": { "test_name": "operators/binary_logical_and/k6_N10_40nm", @@ -695,13 +695,13 @@ "Latch Drivers": 1, "Pi": 3, "Po": 2, - "logic element": 9, + "logic element": 8, "latch": 1, "generic logic size": 6, - "Longest Path": 8, + "Longest Path": 7, "Average Path": 4, - "Estimated LUTs": 9, - "Total Node": 11 + "Estimated LUTs": 8, + "Total Node": 10 }, "operators/binary_logical_and/k6_N10_mem32K_40nm": { "test_name": "operators/binary_logical_and/k6_N10_mem32K_40nm", @@ -714,13 +714,13 @@ "Latch Drivers": 1, "Pi": 3, "Po": 2, - "logic element": 9, + "logic element": 8, "latch": 1, "generic logic size": 6, - "Longest Path": 8, + "Longest Path": 7, "Average Path": 4, - "Estimated LUTs": 9, - "Total Node": 11 + "Estimated LUTs": 8, + "Total Node": 10 }, "operators/binary_logical_and/no_arch": { "test_name": "operators/binary_logical_and/no_arch", @@ -732,12 +732,12 @@ "Latch Drivers": 1, "Pi": 3, "Po": 2, - "logic element": 9, + "logic element": 8, "latch": 1, - "Longest Path": 8, + "Longest Path": 7, "Average Path": 4, - "Estimated LUTs": 9, - "Total Node": 11 + "Estimated LUTs": 8, + "Total Node": 10 }, "operators/binary_logical_equal/k6_frac_N10_frac_chain_mem32K_40nm": { "test_name": "operators/binary_logical_equal/k6_frac_N10_frac_chain_mem32K_40nm", @@ -750,13 +750,13 @@ "Latch Drivers": 1, "Pi": 3, "Po": 2, - "logic element": 8, + "logic element": 7, "latch": 1, "generic logic size": 4, - "Longest Path": 8, + "Longest Path": 7, "Average Path": 4, - "Estimated LUTs": 8, - "Total Node": 10 + "Estimated LUTs": 7, + "Total Node": 9 }, "operators/binary_logical_equal/k6_N10_40nm": { "test_name": "operators/binary_logical_equal/k6_N10_40nm", @@ -769,13 +769,13 @@ "Latch Drivers": 1, "Pi": 3, "Po": 2, - "logic element": 8, + "logic element": 7, "latch": 1, "generic logic size": 6, - "Longest Path": 8, + "Longest Path": 7, "Average Path": 4, - "Estimated LUTs": 8, - "Total Node": 10 + "Estimated LUTs": 7, + "Total Node": 9 }, "operators/binary_logical_equal/k6_N10_mem32K_40nm": { "test_name": "operators/binary_logical_equal/k6_N10_mem32K_40nm", @@ -788,13 +788,13 @@ "Latch Drivers": 1, "Pi": 3, "Po": 2, - "logic element": 8, + "logic element": 7, "latch": 1, "generic logic size": 6, - "Longest Path": 8, + "Longest Path": 7, "Average Path": 4, - "Estimated LUTs": 8, - "Total Node": 10 + "Estimated LUTs": 7, + "Total Node": 9 }, "operators/binary_logical_equal/no_arch": { "test_name": "operators/binary_logical_equal/no_arch", @@ -806,12 +806,12 @@ "Latch Drivers": 1, "Pi": 3, "Po": 2, - "logic element": 8, + "logic element": 7, "latch": 1, - "Longest Path": 8, + "Longest Path": 7, "Average Path": 4, - "Estimated LUTs": 8, - "Total Node": 10 + "Estimated LUTs": 7, + "Total Node": 9 }, "operators/binary_logical_greater_equal_than/k6_frac_N10_frac_chain_mem32K_40nm": { "test_name": "operators/binary_logical_greater_equal_than/k6_frac_N10_frac_chain_mem32K_40nm", @@ -824,13 +824,13 @@ "Latch Drivers": 1, "Pi": 3, "Po": 2, - "logic element": 11, + "logic element": 10, "latch": 1, "generic logic size": 4, - "Longest Path": 8, + "Longest Path": 7, "Average Path": 4, - "Estimated LUTs": 11, - "Total Node": 13 + "Estimated LUTs": 10, + "Total Node": 12 }, "operators/binary_logical_greater_equal_than/k6_N10_40nm": { "test_name": "operators/binary_logical_greater_equal_than/k6_N10_40nm", @@ -843,13 +843,13 @@ "Latch Drivers": 1, "Pi": 3, "Po": 2, - "logic element": 11, + "logic element": 10, "latch": 1, "generic logic size": 6, - "Longest Path": 8, + "Longest Path": 7, "Average Path": 4, - "Estimated LUTs": 11, - "Total Node": 13 + "Estimated LUTs": 10, + "Total Node": 12 }, "operators/binary_logical_greater_equal_than/k6_N10_mem32K_40nm": { "test_name": "operators/binary_logical_greater_equal_than/k6_N10_mem32K_40nm", @@ -862,13 +862,13 @@ "Latch Drivers": 1, "Pi": 3, "Po": 2, - "logic element": 11, + "logic element": 10, "latch": 1, "generic logic size": 6, - "Longest Path": 8, + "Longest Path": 7, "Average Path": 4, - "Estimated LUTs": 11, - "Total Node": 13 + "Estimated LUTs": 10, + "Total Node": 12 }, "operators/binary_logical_greater_equal_than/no_arch": { "test_name": "operators/binary_logical_greater_equal_than/no_arch", @@ -880,12 +880,12 @@ "Latch Drivers": 1, "Pi": 3, "Po": 2, - "logic element": 11, + "logic element": 10, "latch": 1, - "Longest Path": 8, + "Longest Path": 7, "Average Path": 4, - "Estimated LUTs": 11, - "Total Node": 13 + "Estimated LUTs": 10, + "Total Node": 12 }, "operators/binary_logical_greater_than/k6_frac_N10_frac_chain_mem32K_40nm": { "test_name": "operators/binary_logical_greater_than/k6_frac_N10_frac_chain_mem32K_40nm", @@ -898,13 +898,13 @@ "Latch Drivers": 1, "Pi": 3, "Po": 2, - "logic element": 8, + "logic element": 7, "latch": 1, "generic logic size": 4, - "Longest Path": 8, + "Longest Path": 7, "Average Path": 4, - "Estimated LUTs": 8, - "Total Node": 10 + "Estimated LUTs": 7, + "Total Node": 9 }, "operators/binary_logical_greater_than/k6_N10_40nm": { "test_name": "operators/binary_logical_greater_than/k6_N10_40nm", @@ -917,13 +917,13 @@ "Latch Drivers": 1, "Pi": 3, "Po": 2, - "logic element": 8, + "logic element": 7, "latch": 1, "generic logic size": 6, - "Longest Path": 8, + "Longest Path": 7, "Average Path": 4, - "Estimated LUTs": 8, - "Total Node": 10 + "Estimated LUTs": 7, + "Total Node": 9 }, "operators/binary_logical_greater_than/k6_N10_mem32K_40nm": { "test_name": "operators/binary_logical_greater_than/k6_N10_mem32K_40nm", @@ -936,13 +936,13 @@ "Latch Drivers": 1, "Pi": 3, "Po": 2, - "logic element": 8, + "logic element": 7, "latch": 1, "generic logic size": 6, - "Longest Path": 8, + "Longest Path": 7, "Average Path": 4, - "Estimated LUTs": 8, - "Total Node": 10 + "Estimated LUTs": 7, + "Total Node": 9 }, "operators/binary_logical_greater_than/no_arch": { "test_name": "operators/binary_logical_greater_than/no_arch", @@ -954,12 +954,12 @@ "Latch Drivers": 1, "Pi": 3, "Po": 2, - "logic element": 8, + "logic element": 7, "latch": 1, - "Longest Path": 8, + "Longest Path": 7, "Average Path": 4, - "Estimated LUTs": 8, - "Total Node": 10 + "Estimated LUTs": 7, + "Total Node": 9 }, "operators/binary_logical_less_equal_than/k6_frac_N10_frac_chain_mem32K_40nm": { "test_name": "operators/binary_logical_less_equal_than/k6_frac_N10_frac_chain_mem32K_40nm", @@ -972,13 +972,13 @@ "Latch Drivers": 1, "Pi": 3, "Po": 2, - "logic element": 11, + "logic element": 10, "latch": 1, "generic logic size": 4, - "Longest Path": 8, + "Longest Path": 7, "Average Path": 4, - "Estimated LUTs": 11, - "Total Node": 13 + "Estimated LUTs": 10, + "Total Node": 12 }, "operators/binary_logical_less_equal_than/k6_N10_40nm": { "test_name": "operators/binary_logical_less_equal_than/k6_N10_40nm", @@ -991,13 +991,13 @@ "Latch Drivers": 1, "Pi": 3, "Po": 2, - "logic element": 11, + "logic element": 10, "latch": 1, "generic logic size": 6, - "Longest Path": 8, + "Longest Path": 7, "Average Path": 4, - "Estimated LUTs": 11, - "Total Node": 13 + "Estimated LUTs": 10, + "Total Node": 12 }, "operators/binary_logical_less_equal_than/k6_N10_mem32K_40nm": { "test_name": "operators/binary_logical_less_equal_than/k6_N10_mem32K_40nm", @@ -1010,13 +1010,13 @@ "Latch Drivers": 1, "Pi": 3, "Po": 2, - "logic element": 11, + "logic element": 10, "latch": 1, "generic logic size": 6, - "Longest Path": 8, + "Longest Path": 7, "Average Path": 4, - "Estimated LUTs": 11, - "Total Node": 13 + "Estimated LUTs": 10, + "Total Node": 12 }, "operators/binary_logical_less_equal_than/no_arch": { "test_name": "operators/binary_logical_less_equal_than/no_arch", @@ -1028,12 +1028,12 @@ "Latch Drivers": 1, "Pi": 3, "Po": 2, - "logic element": 11, + "logic element": 10, "latch": 1, - "Longest Path": 8, + "Longest Path": 7, "Average Path": 4, - "Estimated LUTs": 11, - "Total Node": 13 + "Estimated LUTs": 10, + "Total Node": 12 }, "operators/binary_logical_less_than/k6_frac_N10_frac_chain_mem32K_40nm": { "test_name": "operators/binary_logical_less_than/k6_frac_N10_frac_chain_mem32K_40nm", @@ -1046,13 +1046,13 @@ "Latch Drivers": 1, "Pi": 3, "Po": 2, - "logic element": 8, + "logic element": 7, "latch": 1, "generic logic size": 4, - "Longest Path": 8, + "Longest Path": 7, "Average Path": 4, - "Estimated LUTs": 8, - "Total Node": 10 + "Estimated LUTs": 7, + "Total Node": 9 }, "operators/binary_logical_less_than/k6_N10_40nm": { "test_name": "operators/binary_logical_less_than/k6_N10_40nm", @@ -1065,13 +1065,13 @@ "Latch Drivers": 1, "Pi": 3, "Po": 2, - "logic element": 8, + "logic element": 7, "latch": 1, "generic logic size": 6, - "Longest Path": 8, + "Longest Path": 7, "Average Path": 4, - "Estimated LUTs": 8, - "Total Node": 10 + "Estimated LUTs": 7, + "Total Node": 9 }, "operators/binary_logical_less_than/k6_N10_mem32K_40nm": { "test_name": "operators/binary_logical_less_than/k6_N10_mem32K_40nm", @@ -1084,13 +1084,13 @@ "Latch Drivers": 1, "Pi": 3, "Po": 2, - "logic element": 8, + "logic element": 7, "latch": 1, "generic logic size": 6, - "Longest Path": 8, + "Longest Path": 7, "Average Path": 4, - "Estimated LUTs": 8, - "Total Node": 10 + "Estimated LUTs": 7, + "Total Node": 9 }, "operators/binary_logical_less_than/no_arch": { "test_name": "operators/binary_logical_less_than/no_arch", @@ -1102,12 +1102,12 @@ "Latch Drivers": 1, "Pi": 3, "Po": 2, - "logic element": 8, + "logic element": 7, "latch": 1, - "Longest Path": 8, + "Longest Path": 7, "Average Path": 4, - "Estimated LUTs": 8, - "Total Node": 10 + "Estimated LUTs": 7, + "Total Node": 9 }, "operators/binary_logical_not_equal/k6_frac_N10_frac_chain_mem32K_40nm": { "test_name": "operators/binary_logical_not_equal/k6_frac_N10_frac_chain_mem32K_40nm", @@ -1120,13 +1120,13 @@ "Latch Drivers": 1, "Pi": 3, "Po": 2, - "logic element": 8, + "logic element": 7, "latch": 1, "generic logic size": 4, - "Longest Path": 8, + "Longest Path": 7, "Average Path": 4, - "Estimated LUTs": 8, - "Total Node": 10 + "Estimated LUTs": 7, + "Total Node": 9 }, "operators/binary_logical_not_equal/k6_N10_40nm": { "test_name": "operators/binary_logical_not_equal/k6_N10_40nm", @@ -1139,13 +1139,13 @@ "Latch Drivers": 1, "Pi": 3, "Po": 2, - "logic element": 8, + "logic element": 7, "latch": 1, "generic logic size": 6, - "Longest Path": 8, + "Longest Path": 7, "Average Path": 4, - "Estimated LUTs": 8, - "Total Node": 10 + "Estimated LUTs": 7, + "Total Node": 9 }, "operators/binary_logical_not_equal/k6_N10_mem32K_40nm": { "test_name": "operators/binary_logical_not_equal/k6_N10_mem32K_40nm", @@ -1158,13 +1158,13 @@ "Latch Drivers": 1, "Pi": 3, "Po": 2, - "logic element": 8, + "logic element": 7, "latch": 1, "generic logic size": 6, - "Longest Path": 8, + "Longest Path": 7, "Average Path": 4, - "Estimated LUTs": 8, - "Total Node": 10 + "Estimated LUTs": 7, + "Total Node": 9 }, "operators/binary_logical_not_equal/no_arch": { "test_name": "operators/binary_logical_not_equal/no_arch", @@ -1176,12 +1176,12 @@ "Latch Drivers": 1, "Pi": 3, "Po": 2, - "logic element": 8, + "logic element": 7, "latch": 1, - "Longest Path": 8, + "Longest Path": 7, "Average Path": 4, - "Estimated LUTs": 8, - "Total Node": 10 + "Estimated LUTs": 7, + "Total Node": 9 }, "operators/binary_logical_or/k6_frac_N10_frac_chain_mem32K_40nm": { "test_name": "operators/binary_logical_or/k6_frac_N10_frac_chain_mem32K_40nm", @@ -1194,13 +1194,13 @@ "Latch Drivers": 1, "Pi": 3, "Po": 2, - "logic element": 9, + "logic element": 8, "latch": 1, "generic logic size": 4, - "Longest Path": 8, + "Longest Path": 7, "Average Path": 4, - "Estimated LUTs": 9, - "Total Node": 11 + "Estimated LUTs": 8, + "Total Node": 10 }, "operators/binary_logical_or/k6_N10_40nm": { "test_name": "operators/binary_logical_or/k6_N10_40nm", @@ -1213,13 +1213,13 @@ "Latch Drivers": 1, "Pi": 3, "Po": 2, - "logic element": 9, + "logic element": 8, "latch": 1, "generic logic size": 6, - "Longest Path": 8, + "Longest Path": 7, "Average Path": 4, - "Estimated LUTs": 9, - "Total Node": 11 + "Estimated LUTs": 8, + "Total Node": 10 }, "operators/binary_logical_or/k6_N10_mem32K_40nm": { "test_name": "operators/binary_logical_or/k6_N10_mem32K_40nm", @@ -1232,13 +1232,13 @@ "Latch Drivers": 1, "Pi": 3, "Po": 2, - "logic element": 9, + "logic element": 8, "latch": 1, "generic logic size": 6, - "Longest Path": 8, + "Longest Path": 7, "Average Path": 4, - "Estimated LUTs": 9, - "Total Node": 11 + "Estimated LUTs": 8, + "Total Node": 10 }, "operators/binary_logical_or/no_arch": { "test_name": "operators/binary_logical_or/no_arch", @@ -1250,12 +1250,12 @@ "Latch Drivers": 1, "Pi": 3, "Po": 2, - "logic element": 9, + "logic element": 8, "latch": 1, - "Longest Path": 8, + "Longest Path": 7, "Average Path": 4, - "Estimated LUTs": 9, - "Total Node": 11 + "Estimated LUTs": 8, + "Total Node": 10 }, "operators/binary_nand/k6_frac_N10_frac_chain_mem32K_40nm": { "test_name": "operators/binary_nand/k6_frac_N10_frac_chain_mem32K_40nm", @@ -1268,13 +1268,13 @@ "Latch Drivers": 1, "Pi": 3, "Po": 2, - "logic element": 7, + "logic element": 6, "latch": 1, "generic logic size": 4, - "Longest Path": 8, + "Longest Path": 7, "Average Path": 4, - "Estimated LUTs": 7, - "Total Node": 9 + "Estimated LUTs": 6, + "Total Node": 8 }, "operators/binary_nand/k6_N10_40nm": { "test_name": "operators/binary_nand/k6_N10_40nm", @@ -1287,13 +1287,13 @@ "Latch Drivers": 1, "Pi": 3, "Po": 2, - "logic element": 7, + "logic element": 6, "latch": 1, "generic logic size": 6, - "Longest Path": 8, + "Longest Path": 7, "Average Path": 4, - "Estimated LUTs": 7, - "Total Node": 9 + "Estimated LUTs": 6, + "Total Node": 8 }, "operators/binary_nand/k6_N10_mem32K_40nm": { "test_name": "operators/binary_nand/k6_N10_mem32K_40nm", @@ -1306,13 +1306,13 @@ "Latch Drivers": 1, "Pi": 3, "Po": 2, - "logic element": 7, + "logic element": 6, "latch": 1, "generic logic size": 6, - "Longest Path": 8, + "Longest Path": 7, "Average Path": 4, - "Estimated LUTs": 7, - "Total Node": 9 + "Estimated LUTs": 6, + "Total Node": 8 }, "operators/binary_nand/no_arch": { "test_name": "operators/binary_nand/no_arch", @@ -1324,12 +1324,12 @@ "Latch Drivers": 1, "Pi": 3, "Po": 2, - "logic element": 7, + "logic element": 6, "latch": 1, - "Longest Path": 8, + "Longest Path": 7, "Average Path": 4, - "Estimated LUTs": 7, - "Total Node": 9 + "Estimated LUTs": 6, + "Total Node": 8 }, "operators/binary_nor/k6_frac_N10_frac_chain_mem32K_40nm": { "test_name": "operators/binary_nor/k6_frac_N10_frac_chain_mem32K_40nm", @@ -1342,13 +1342,13 @@ "Latch Drivers": 1, "Pi": 3, "Po": 2, - "logic element": 7, + "logic element": 6, "latch": 1, "generic logic size": 4, - "Longest Path": 8, + "Longest Path": 7, "Average Path": 4, - "Estimated LUTs": 7, - "Total Node": 9 + "Estimated LUTs": 6, + "Total Node": 8 }, "operators/binary_nor/k6_N10_40nm": { "test_name": "operators/binary_nor/k6_N10_40nm", @@ -1361,13 +1361,13 @@ "Latch Drivers": 1, "Pi": 3, "Po": 2, - "logic element": 7, + "logic element": 6, "latch": 1, "generic logic size": 6, - "Longest Path": 8, + "Longest Path": 7, "Average Path": 4, - "Estimated LUTs": 7, - "Total Node": 9 + "Estimated LUTs": 6, + "Total Node": 8 }, "operators/binary_nor/k6_N10_mem32K_40nm": { "test_name": "operators/binary_nor/k6_N10_mem32K_40nm", @@ -1380,13 +1380,13 @@ "Latch Drivers": 1, "Pi": 3, "Po": 2, - "logic element": 7, + "logic element": 6, "latch": 1, "generic logic size": 6, - "Longest Path": 8, + "Longest Path": 7, "Average Path": 4, - "Estimated LUTs": 7, - "Total Node": 9 + "Estimated LUTs": 6, + "Total Node": 8 }, "operators/binary_nor/no_arch": { "test_name": "operators/binary_nor/no_arch", @@ -1398,12 +1398,12 @@ "Latch Drivers": 1, "Pi": 3, "Po": 2, - "logic element": 7, + "logic element": 6, "latch": 1, - "Longest Path": 8, - "Average Path": 4, - "Estimated LUTs": 7, - "Total Node": 9 + "Longest Path": 7, + "Average Path": 4, + "Estimated LUTs": 6, + "Total Node": 8 }, "operators/binary_or/k6_frac_N10_frac_chain_mem32K_40nm": { "test_name": "operators/binary_or/k6_frac_N10_frac_chain_mem32K_40nm", @@ -1416,13 +1416,13 @@ "Latch Drivers": 1, "Pi": 3, "Po": 2, - "logic element": 7, + "logic element": 6, "latch": 1, "generic logic size": 4, - "Longest Path": 8, + "Longest Path": 7, "Average Path": 4, - "Estimated LUTs": 7, - "Total Node": 9 + "Estimated LUTs": 6, + "Total Node": 8 }, "operators/binary_or/k6_N10_40nm": { "test_name": "operators/binary_or/k6_N10_40nm", @@ -1435,13 +1435,13 @@ "Latch Drivers": 1, "Pi": 3, "Po": 2, - "logic element": 7, + "logic element": 6, "latch": 1, "generic logic size": 6, - "Longest Path": 8, + "Longest Path": 7, "Average Path": 4, - "Estimated LUTs": 7, - "Total Node": 9 + "Estimated LUTs": 6, + "Total Node": 8 }, "operators/binary_or/k6_N10_mem32K_40nm": { "test_name": "operators/binary_or/k6_N10_mem32K_40nm", @@ -1454,13 +1454,13 @@ "Latch Drivers": 1, "Pi": 3, "Po": 2, - "logic element": 7, + "logic element": 6, "latch": 1, "generic logic size": 6, - "Longest Path": 8, + "Longest Path": 7, "Average Path": 4, - "Estimated LUTs": 7, - "Total Node": 9 + "Estimated LUTs": 6, + "Total Node": 8 }, "operators/binary_or/no_arch": { "test_name": "operators/binary_or/no_arch", @@ -1472,12 +1472,12 @@ "Latch Drivers": 1, "Pi": 3, "Po": 2, - "logic element": 7, + "logic element": 6, "latch": 1, - "Longest Path": 8, + "Longest Path": 7, "Average Path": 4, - "Estimated LUTs": 7, - "Total Node": 9 + "Estimated LUTs": 6, + "Total Node": 8 }, "operators/binary_shift_left/k6_frac_N10_frac_chain_mem32K_40nm": { "test_name": "operators/binary_shift_left/k6_frac_N10_frac_chain_mem32K_40nm", @@ -1490,13 +1490,13 @@ "Latch Drivers": 1, "Pi": 2, "Po": 3, - "logic element": 8, + "logic element": 6, "latch": 2, "generic logic size": 4, - "Longest Path": 8, + "Longest Path": 7, "Average Path": 4, - "Estimated LUTs": 8, - "Total Node": 11 + "Estimated LUTs": 6, + "Total Node": 9 }, "operators/binary_shift_left/k6_N10_40nm": { "test_name": "operators/binary_shift_left/k6_N10_40nm", @@ -1509,13 +1509,13 @@ "Latch Drivers": 1, "Pi": 2, "Po": 3, - "logic element": 8, + "logic element": 6, "latch": 2, "generic logic size": 6, - "Longest Path": 8, + "Longest Path": 7, "Average Path": 4, - "Estimated LUTs": 8, - "Total Node": 11 + "Estimated LUTs": 6, + "Total Node": 9 }, "operators/binary_shift_left/k6_N10_mem32K_40nm": { "test_name": "operators/binary_shift_left/k6_N10_mem32K_40nm", @@ -1528,13 +1528,13 @@ "Latch Drivers": 1, "Pi": 2, "Po": 3, - "logic element": 8, + "logic element": 6, "latch": 2, "generic logic size": 6, - "Longest Path": 8, + "Longest Path": 7, "Average Path": 4, - "Estimated LUTs": 8, - "Total Node": 11 + "Estimated LUTs": 6, + "Total Node": 9 }, "operators/binary_shift_left/no_arch": { "test_name": "operators/binary_shift_left/no_arch", @@ -1546,12 +1546,12 @@ "Latch Drivers": 1, "Pi": 2, "Po": 3, - "logic element": 8, + "logic element": 6, "latch": 2, - "Longest Path": 8, + "Longest Path": 7, "Average Path": 4, - "Estimated LUTs": 8, - "Total Node": 11 + "Estimated LUTs": 6, + "Total Node": 9 }, "operators/binary_shift_right/k6_frac_N10_frac_chain_mem32K_40nm": { "test_name": "operators/binary_shift_right/k6_frac_N10_frac_chain_mem32K_40nm", @@ -1564,13 +1564,13 @@ "Latch Drivers": 1, "Pi": 2, "Po": 3, - "logic element": 8, + "logic element": 6, "latch": 2, "generic logic size": 4, - "Longest Path": 8, + "Longest Path": 7, "Average Path": 4, - "Estimated LUTs": 8, - "Total Node": 11 + "Estimated LUTs": 6, + "Total Node": 9 }, "operators/binary_shift_right/k6_N10_40nm": { "test_name": "operators/binary_shift_right/k6_N10_40nm", @@ -1583,13 +1583,13 @@ "Latch Drivers": 1, "Pi": 2, "Po": 3, - "logic element": 8, + "logic element": 6, "latch": 2, "generic logic size": 6, - "Longest Path": 8, + "Longest Path": 7, "Average Path": 4, - "Estimated LUTs": 8, - "Total Node": 11 + "Estimated LUTs": 6, + "Total Node": 9 }, "operators/binary_shift_right/k6_N10_mem32K_40nm": { "test_name": "operators/binary_shift_right/k6_N10_mem32K_40nm", @@ -1602,13 +1602,13 @@ "Latch Drivers": 1, "Pi": 2, "Po": 3, - "logic element": 8, + "logic element": 6, "latch": 2, "generic logic size": 6, - "Longest Path": 8, + "Longest Path": 7, "Average Path": 4, - "Estimated LUTs": 8, - "Total Node": 11 + "Estimated LUTs": 6, + "Total Node": 9 }, "operators/binary_shift_right/no_arch": { "test_name": "operators/binary_shift_right/no_arch", @@ -1620,12 +1620,12 @@ "Latch Drivers": 1, "Pi": 2, "Po": 3, - "logic element": 8, + "logic element": 6, "latch": 2, - "Longest Path": 8, + "Longest Path": 7, "Average Path": 4, - "Estimated LUTs": 8, - "Total Node": 11 + "Estimated LUTs": 6, + "Total Node": 9 }, "operators/binary_signed_shift_left/k6_frac_N10_frac_chain_mem32K_40nm": { "test_name": "operators/binary_signed_shift_left/k6_frac_N10_frac_chain_mem32K_40nm", @@ -1638,13 +1638,13 @@ "Latch Drivers": 1, "Pi": 2, "Po": 3, - "logic element": 8, + "logic element": 6, "latch": 2, "generic logic size": 4, - "Longest Path": 8, + "Longest Path": 7, "Average Path": 4, - "Estimated LUTs": 8, - "Total Node": 11 + "Estimated LUTs": 6, + "Total Node": 9 }, "operators/binary_signed_shift_left/k6_N10_40nm": { "test_name": "operators/binary_signed_shift_left/k6_N10_40nm", @@ -1657,13 +1657,13 @@ "Latch Drivers": 1, "Pi": 2, "Po": 3, - "logic element": 8, + "logic element": 6, "latch": 2, "generic logic size": 6, - "Longest Path": 8, + "Longest Path": 7, "Average Path": 4, - "Estimated LUTs": 8, - "Total Node": 11 + "Estimated LUTs": 6, + "Total Node": 9 }, "operators/binary_signed_shift_left/k6_N10_mem32K_40nm": { "test_name": "operators/binary_signed_shift_left/k6_N10_mem32K_40nm", @@ -1676,13 +1676,13 @@ "Latch Drivers": 1, "Pi": 2, "Po": 3, - "logic element": 8, + "logic element": 6, "latch": 2, "generic logic size": 6, - "Longest Path": 8, + "Longest Path": 7, "Average Path": 4, - "Estimated LUTs": 8, - "Total Node": 11 + "Estimated LUTs": 6, + "Total Node": 9 }, "operators/binary_signed_shift_left/no_arch": { "test_name": "operators/binary_signed_shift_left/no_arch", @@ -1694,12 +1694,12 @@ "Latch Drivers": 1, "Pi": 2, "Po": 3, - "logic element": 8, + "logic element": 6, "latch": 2, - "Longest Path": 8, + "Longest Path": 7, "Average Path": 4, - "Estimated LUTs": 8, - "Total Node": 11 + "Estimated LUTs": 6, + "Total Node": 9 }, "operators/binary_signed_shift_right/k6_frac_N10_frac_chain_mem32K_40nm": { "test_name": "operators/binary_signed_shift_right/k6_frac_N10_frac_chain_mem32K_40nm", @@ -1712,13 +1712,13 @@ "Latch Drivers": 1, "Pi": 2, "Po": 3, - "logic element": 8, + "logic element": 6, "latch": 2, "generic logic size": 4, - "Longest Path": 8, + "Longest Path": 7, "Average Path": 4, - "Estimated LUTs": 8, - "Total Node": 11 + "Estimated LUTs": 6, + "Total Node": 9 }, "operators/binary_signed_shift_right/k6_N10_40nm": { "test_name": "operators/binary_signed_shift_right/k6_N10_40nm", @@ -1731,13 +1731,13 @@ "Latch Drivers": 1, "Pi": 2, "Po": 3, - "logic element": 8, + "logic element": 6, "latch": 2, "generic logic size": 6, - "Longest Path": 8, + "Longest Path": 7, "Average Path": 4, - "Estimated LUTs": 8, - "Total Node": 11 + "Estimated LUTs": 6, + "Total Node": 9 }, "operators/binary_signed_shift_right/k6_N10_mem32K_40nm": { "test_name": "operators/binary_signed_shift_right/k6_N10_mem32K_40nm", @@ -1750,13 +1750,13 @@ "Latch Drivers": 1, "Pi": 2, "Po": 3, - "logic element": 8, + "logic element": 6, "latch": 2, "generic logic size": 6, - "Longest Path": 8, + "Longest Path": 7, "Average Path": 4, - "Estimated LUTs": 8, - "Total Node": 11 + "Estimated LUTs": 6, + "Total Node": 9 }, "operators/binary_signed_shift_right/no_arch": { "test_name": "operators/binary_signed_shift_right/no_arch", @@ -1768,12 +1768,12 @@ "Latch Drivers": 1, "Pi": 2, "Po": 3, - "logic element": 8, + "logic element": 6, "latch": 2, - "Longest Path": 8, + "Longest Path": 7, "Average Path": 4, - "Estimated LUTs": 8, - "Total Node": 11 + "Estimated LUTs": 6, + "Total Node": 9 }, "operators/binary_xnor/k6_frac_N10_frac_chain_mem32K_40nm": { "test_name": "operators/binary_xnor/k6_frac_N10_frac_chain_mem32K_40nm", @@ -1786,13 +1786,13 @@ "Latch Drivers": 1, "Pi": 3, "Po": 2, - "logic element": 7, + "logic element": 6, "latch": 1, "generic logic size": 4, - "Longest Path": 8, + "Longest Path": 7, "Average Path": 4, - "Estimated LUTs": 7, - "Total Node": 9 + "Estimated LUTs": 6, + "Total Node": 8 }, "operators/binary_xnor/k6_N10_40nm": { "test_name": "operators/binary_xnor/k6_N10_40nm", @@ -1805,13 +1805,13 @@ "Latch Drivers": 1, "Pi": 3, "Po": 2, - "logic element": 7, + "logic element": 6, "latch": 1, "generic logic size": 6, - "Longest Path": 8, + "Longest Path": 7, "Average Path": 4, - "Estimated LUTs": 7, - "Total Node": 9 + "Estimated LUTs": 6, + "Total Node": 8 }, "operators/binary_xnor/k6_N10_mem32K_40nm": { "test_name": "operators/binary_xnor/k6_N10_mem32K_40nm", @@ -1824,13 +1824,13 @@ "Latch Drivers": 1, "Pi": 3, "Po": 2, - "logic element": 7, + "logic element": 6, "latch": 1, "generic logic size": 6, - "Longest Path": 8, + "Longest Path": 7, "Average Path": 4, - "Estimated LUTs": 7, - "Total Node": 9 + "Estimated LUTs": 6, + "Total Node": 8 }, "operators/binary_xnor/no_arch": { "test_name": "operators/binary_xnor/no_arch", @@ -1842,12 +1842,12 @@ "Latch Drivers": 1, "Pi": 3, "Po": 2, - "logic element": 7, + "logic element": 6, "latch": 1, - "Longest Path": 8, + "Longest Path": 7, "Average Path": 4, - "Estimated LUTs": 7, - "Total Node": 9 + "Estimated LUTs": 6, + "Total Node": 8 }, "operators/binary_xor/k6_frac_N10_frac_chain_mem32K_40nm": { "test_name": "operators/binary_xor/k6_frac_N10_frac_chain_mem32K_40nm", @@ -1860,13 +1860,13 @@ "Latch Drivers": 1, "Pi": 3, "Po": 2, - "logic element": 7, + "logic element": 6, "latch": 1, "generic logic size": 4, - "Longest Path": 8, + "Longest Path": 7, "Average Path": 4, - "Estimated LUTs": 7, - "Total Node": 9 + "Estimated LUTs": 6, + "Total Node": 8 }, "operators/binary_xor/k6_N10_40nm": { "test_name": "operators/binary_xor/k6_N10_40nm", @@ -1879,13 +1879,13 @@ "Latch Drivers": 1, "Pi": 3, "Po": 2, - "logic element": 7, + "logic element": 6, "latch": 1, "generic logic size": 6, - "Longest Path": 8, + "Longest Path": 7, "Average Path": 4, - "Estimated LUTs": 7, - "Total Node": 9 + "Estimated LUTs": 6, + "Total Node": 8 }, "operators/binary_xor/k6_N10_mem32K_40nm": { "test_name": "operators/binary_xor/k6_N10_mem32K_40nm", @@ -1898,13 +1898,13 @@ "Latch Drivers": 1, "Pi": 3, "Po": 2, - "logic element": 7, + "logic element": 6, "latch": 1, "generic logic size": 6, - "Longest Path": 8, + "Longest Path": 7, "Average Path": 4, - "Estimated LUTs": 7, - "Total Node": 9 + "Estimated LUTs": 6, + "Total Node": 8 }, "operators/binary_xor/no_arch": { "test_name": "operators/binary_xor/no_arch", @@ -1916,12 +1916,12 @@ "Latch Drivers": 1, "Pi": 3, "Po": 2, - "logic element": 7, + "logic element": 6, "latch": 1, - "Longest Path": 8, + "Longest Path": 7, "Average Path": 4, - "Estimated LUTs": 7, - "Total Node": 9 + "Estimated LUTs": 6, + "Total Node": 8 }, "operators/clog2/k6_frac_N10_frac_chain_mem32K_40nm": { "test_name": "operators/clog2/k6_frac_N10_frac_chain_mem32K_40nm", @@ -1934,13 +1934,13 @@ "Latch Drivers": 1, "Pi": 2, "Po": 2, - "logic element": 7, + "logic element": 6, "latch": 1, "generic logic size": 4, - "Longest Path": 8, + "Longest Path": 7, "Average Path": 4, - "Estimated LUTs": 7, - "Total Node": 9 + "Estimated LUTs": 6, + "Total Node": 8 }, "operators/clog2/k6_N10_40nm": { "test_name": "operators/clog2/k6_N10_40nm", @@ -1953,13 +1953,13 @@ "Latch Drivers": 1, "Pi": 2, "Po": 2, - "logic element": 7, + "logic element": 6, "latch": 1, "generic logic size": 6, - "Longest Path": 8, + "Longest Path": 7, "Average Path": 4, - "Estimated LUTs": 7, - "Total Node": 9 + "Estimated LUTs": 6, + "Total Node": 8 }, "operators/clog2/k6_N10_mem32K_40nm": { "test_name": "operators/clog2/k6_N10_mem32K_40nm", @@ -1972,13 +1972,13 @@ "Latch Drivers": 1, "Pi": 2, "Po": 2, - "logic element": 7, + "logic element": 6, "latch": 1, "generic logic size": 6, - "Longest Path": 8, + "Longest Path": 7, "Average Path": 4, - "Estimated LUTs": 7, - "Total Node": 9 + "Estimated LUTs": 6, + "Total Node": 8 }, "operators/clog2/no_arch": { "test_name": "operators/clog2/no_arch", @@ -1990,12 +1990,12 @@ "Latch Drivers": 1, "Pi": 2, "Po": 2, - "logic element": 7, + "logic element": 6, "latch": 1, - "Longest Path": 8, + "Longest Path": 7, "Average Path": 4, - "Estimated LUTs": 7, - "Total Node": 9 + "Estimated LUTs": 6, + "Total Node": 8 }, "operators/concat/k6_frac_N10_frac_chain_mem32K_40nm": { "test_name": "operators/concat/k6_frac_N10_frac_chain_mem32K_40nm", @@ -2008,13 +2008,13 @@ "Latch Drivers": 1, "Pi": 24, "Po": 72, - "logic element": 201, + "logic element": 177, "latch": 24, "generic logic size": 4, - "Longest Path": 10, + "Longest Path": 9, "Average Path": 5, - "Estimated LUTs": 221, - "Total Node": 226 + "Estimated LUTs": 197, + "Total Node": 202 }, "operators/concat/k6_N10_40nm": { "test_name": "operators/concat/k6_N10_40nm", @@ -2027,13 +2027,13 @@ "Latch Drivers": 1, "Pi": 24, "Po": 72, - "logic element": 201, + "logic element": 177, "latch": 24, "generic logic size": 6, - "Longest Path": 10, + "Longest Path": 9, "Average Path": 5, - "Estimated LUTs": 215, - "Total Node": 226 + "Estimated LUTs": 191, + "Total Node": 202 }, "operators/concat/k6_N10_mem32K_40nm": { "test_name": "operators/concat/k6_N10_mem32K_40nm", @@ -2046,13 +2046,13 @@ "Latch Drivers": 1, "Pi": 24, "Po": 72, - "logic element": 201, + "logic element": 177, "latch": 24, "generic logic size": 6, - "Longest Path": 10, + "Longest Path": 9, "Average Path": 5, - "Estimated LUTs": 215, - "Total Node": 226 + "Estimated LUTs": 191, + "Total Node": 202 }, "operators/concat/no_arch": { "test_name": "operators/concat/no_arch", @@ -2064,12 +2064,12 @@ "Latch Drivers": 1, "Pi": 24, "Po": 72, - "logic element": 201, + "logic element": 177, "latch": 24, - "Longest Path": 10, + "Longest Path": 9, "Average Path": 5, - "Estimated LUTs": 201, - "Total Node": 226 + "Estimated LUTs": 177, + "Total Node": 202 }, "operators/eightbit_arithmetic_power/k6_frac_N10_frac_chain_mem32K_40nm": { "test_name": "operators/eightbit_arithmetic_power/k6_frac_N10_frac_chain_mem32K_40nm", @@ -2082,14 +2082,14 @@ "Latch Drivers": 1, "Pi": 9, "Po": 8, - "logic element": 19, + "logic element": 11, "latch": 8, "Multiplier": 1, "generic logic size": 4, - "Longest Path": 8, - "Average Path": 5, - "Estimated LUTs": 19, - "Total Node": 29 + "Longest Path": 7, + "Average Path": 4, + "Estimated LUTs": 11, + "Total Node": 21 }, "operators/eightbit_arithmetic_power/k6_N10_40nm": { "test_name": "operators/eightbit_arithmetic_power/k6_N10_40nm", @@ -2102,13 +2102,13 @@ "Latch Drivers": 1, "Pi": 9, "Po": 8, - "logic element": 104, + "logic element": 96, "latch": 8, "generic logic size": 6, - "Longest Path": 19, - "Average Path": 5, - "Estimated LUTs": 104, - "Total Node": 113 + "Longest Path": 18, + "Average Path": 4, + "Estimated LUTs": 96, + "Total Node": 105 }, "operators/eightbit_arithmetic_power/k6_N10_mem32K_40nm": { "test_name": "operators/eightbit_arithmetic_power/k6_N10_mem32K_40nm", @@ -2121,14 +2121,14 @@ "Latch Drivers": 1, "Pi": 9, "Po": 8, - "logic element": 19, + "logic element": 11, "latch": 8, "Multiplier": 1, "generic logic size": 6, - "Longest Path": 8, - "Average Path": 5, - "Estimated LUTs": 19, - "Total Node": 29 + "Longest Path": 7, + "Average Path": 4, + "Estimated LUTs": 11, + "Total Node": 21 }, "operators/eightbit_arithmetic_power/no_arch": { "test_name": "operators/eightbit_arithmetic_power/no_arch", @@ -2140,12 +2140,12 @@ "Latch Drivers": 1, "Pi": 9, "Po": 8, - "logic element": 104, + "logic element": 96, "latch": 8, - "Longest Path": 19, - "Average Path": 5, - "Estimated LUTs": 104, - "Total Node": 113 + "Longest Path": 18, + "Average Path": 4, + "Estimated LUTs": 96, + "Total Node": 105 }, "operators/macromudule_test/k6_frac_N10_frac_chain_mem32K_40nm": { "test_name": "operators/macromudule_test/k6_frac_N10_frac_chain_mem32K_40nm", @@ -2414,13 +2414,11 @@ "test_coverage(%)": 100, "Latch Drivers": 1, "Po": 128, - "logic element": 128, "latch": 128, "generic logic size": 4, - "Longest Path": 4, - "Average Path": 4, - "Estimated LUTs": 128, - "Total Node": 257 + "Longest Path": 3, + "Average Path": 3, + "Total Node": 129 }, "operators/signed_to_unsigned/k6_N10_40nm": { "test_name": "operators/signed_to_unsigned/k6_N10_40nm", @@ -2432,13 +2430,11 @@ "test_coverage(%)": 100, "Latch Drivers": 1, "Po": 128, - "logic element": 128, "latch": 128, "generic logic size": 6, - "Longest Path": 4, - "Average Path": 4, - "Estimated LUTs": 128, - "Total Node": 257 + "Longest Path": 3, + "Average Path": 3, + "Total Node": 129 }, "operators/signed_to_unsigned/k6_N10_mem32K_40nm": { "test_name": "operators/signed_to_unsigned/k6_N10_mem32K_40nm", @@ -2450,13 +2446,11 @@ "test_coverage(%)": 100, "Latch Drivers": 1, "Po": 128, - "logic element": 128, "latch": 128, "generic logic size": 6, - "Longest Path": 4, - "Average Path": 4, - "Estimated LUTs": 128, - "Total Node": 257 + "Longest Path": 3, + "Average Path": 3, + "Total Node": 129 }, "operators/signed_to_unsigned/no_arch": { "test_name": "operators/signed_to_unsigned/no_arch", @@ -2467,12 +2461,10 @@ "test_coverage(%)": 100, "Latch Drivers": 1, "Po": 128, - "logic element": 128, "latch": 128, - "Longest Path": 4, - "Average Path": 4, - "Estimated LUTs": 128, - "Total Node": 257 + "Longest Path": 3, + "Average Path": 3, + "Total Node": 129 }, "operators/specifyBlock/k6_frac_N10_frac_chain_mem32K_40nm": { "test_name": "operators/specifyBlock/k6_frac_N10_frac_chain_mem32K_40nm", @@ -2548,12 +2540,12 @@ "exec_time(ms)": 40.8, "Pi": 2, "Po": 1, - "logic element": 2, + "logic element": 1, "generic logic size": 4, - "Longest Path": 4, - "Average Path": 4, - "Estimated LUTs": 2, - "Total Node": 2 + "Longest Path": 3, + "Average Path": 3, + "Estimated LUTs": 1, + "Total Node": 1 }, "operators/specparam/k6_N10_40nm": { "test_name": "operators/specparam/k6_N10_40nm", @@ -2563,12 +2555,12 @@ "exec_time(ms)": 7.6, "Pi": 2, "Po": 1, - "logic element": 2, + "logic element": 1, "generic logic size": 6, - "Longest Path": 4, - "Average Path": 4, - "Estimated LUTs": 2, - "Total Node": 2 + "Longest Path": 3, + "Average Path": 3, + "Estimated LUTs": 1, + "Total Node": 1 }, "operators/specparam/k6_N10_mem32K_40nm": { "test_name": "operators/specparam/k6_N10_mem32K_40nm", @@ -2578,12 +2570,12 @@ "exec_time(ms)": 34, "Pi": 2, "Po": 1, - "logic element": 2, + "logic element": 1, "generic logic size": 6, - "Longest Path": 4, - "Average Path": 4, - "Estimated LUTs": 2, - "Total Node": 2 + "Longest Path": 3, + "Average Path": 3, + "Estimated LUTs": 1, + "Total Node": 1 }, "operators/specparam/no_arch": { "test_name": "operators/specparam/no_arch", @@ -2592,11 +2584,11 @@ "exec_time(ms)": 2.6, "Pi": 2, "Po": 1, - "logic element": 2, - "Longest Path": 4, - "Average Path": 4, - "Estimated LUTs": 2, - "Total Node": 2 + "logic element": 1, + "Longest Path": 3, + "Average Path": 3, + "Estimated LUTs": 1, + "Total Node": 1 }, "operators/string_test_concat/k6_frac_N10_frac_chain_mem32K_40nm": { "test_name": "operators/string_test_concat/k6_frac_N10_frac_chain_mem32K_40nm", @@ -2608,13 +2600,11 @@ "test_coverage(%)": 100, "Latch Drivers": 1, "Po": 241, - "logic element": 241, "latch": 241, "generic logic size": 4, - "Longest Path": 4, - "Average Path": 4, - "Estimated LUTs": 241, - "Total Node": 483 + "Longest Path": 3, + "Average Path": 3, + "Total Node": 242 }, "operators/string_test_concat/k6_N10_40nm": { "test_name": "operators/string_test_concat/k6_N10_40nm", @@ -2626,13 +2616,11 @@ "test_coverage(%)": 100, "Latch Drivers": 1, "Po": 241, - "logic element": 241, "latch": 241, "generic logic size": 6, - "Longest Path": 4, - "Average Path": 4, - "Estimated LUTs": 241, - "Total Node": 483 + "Longest Path": 3, + "Average Path": 3, + "Total Node": 242 }, "operators/string_test_concat/k6_N10_mem32K_40nm": { "test_name": "operators/string_test_concat/k6_N10_mem32K_40nm", @@ -2644,13 +2632,11 @@ "test_coverage(%)": 100, "Latch Drivers": 1, "Po": 241, - "logic element": 241, "latch": 241, "generic logic size": 6, - "Longest Path": 4, - "Average Path": 4, - "Estimated LUTs": 241, - "Total Node": 483 + "Longest Path": 3, + "Average Path": 3, + "Total Node": 242 }, "operators/string_test_concat/no_arch": { "test_name": "operators/string_test_concat/no_arch", @@ -2661,12 +2647,10 @@ "test_coverage(%)": 100, "Latch Drivers": 1, "Po": 241, - "logic element": 241, "latch": 241, - "Longest Path": 4, - "Average Path": 4, - "Estimated LUTs": 241, - "Total Node": 483 + "Longest Path": 3, + "Average Path": 3, + "Total Node": 242 }, "operators/string_test_concat_replicate/k6_frac_N10_frac_chain_mem32K_40nm": { "test_name": "operators/string_test_concat_replicate/k6_frac_N10_frac_chain_mem32K_40nm", @@ -2678,13 +2662,11 @@ "test_coverage(%)": 100, "Latch Drivers": 1, "Po": 241, - "logic element": 241, "latch": 241, "generic logic size": 4, - "Longest Path": 4, - "Average Path": 4, - "Estimated LUTs": 241, - "Total Node": 483 + "Longest Path": 3, + "Average Path": 3, + "Total Node": 242 }, "operators/string_test_concat_replicate/k6_N10_40nm": { "test_name": "operators/string_test_concat_replicate/k6_N10_40nm", @@ -2696,13 +2678,11 @@ "test_coverage(%)": 100, "Latch Drivers": 1, "Po": 241, - "logic element": 241, "latch": 241, "generic logic size": 6, - "Longest Path": 4, - "Average Path": 4, - "Estimated LUTs": 241, - "Total Node": 483 + "Longest Path": 3, + "Average Path": 3, + "Total Node": 242 }, "operators/string_test_concat_replicate/k6_N10_mem32K_40nm": { "test_name": "operators/string_test_concat_replicate/k6_N10_mem32K_40nm", @@ -2714,13 +2694,11 @@ "test_coverage(%)": 100, "Latch Drivers": 1, "Po": 241, - "logic element": 241, "latch": 241, "generic logic size": 6, - "Longest Path": 4, - "Average Path": 4, - "Estimated LUTs": 241, - "Total Node": 483 + "Longest Path": 3, + "Average Path": 3, + "Total Node": 242 }, "operators/string_test_concat_replicate/no_arch": { "test_name": "operators/string_test_concat_replicate/no_arch", @@ -2731,12 +2709,10 @@ "test_coverage(%)": 100, "Latch Drivers": 1, "Po": 241, - "logic element": 241, "latch": 241, - "Longest Path": 4, - "Average Path": 4, - "Estimated LUTs": 241, - "Total Node": 483 + "Longest Path": 3, + "Average Path": 3, + "Total Node": 242 }, "operators/string_test/k6_frac_N10_frac_chain_mem32K_40nm": { "test_name": "operators/string_test/k6_frac_N10_frac_chain_mem32K_40nm", @@ -2748,13 +2724,11 @@ "test_coverage(%)": 100, "Latch Drivers": 1, "Po": 241, - "logic element": 241, "latch": 241, "generic logic size": 4, - "Longest Path": 4, - "Average Path": 4, - "Estimated LUTs": 241, - "Total Node": 483 + "Longest Path": 3, + "Average Path": 3, + "Total Node": 242 }, "operators/string_test/k6_N10_40nm": { "test_name": "operators/string_test/k6_N10_40nm", @@ -2766,13 +2740,11 @@ "test_coverage(%)": 100, "Latch Drivers": 1, "Po": 241, - "logic element": 241, "latch": 241, "generic logic size": 6, - "Longest Path": 4, - "Average Path": 4, - "Estimated LUTs": 241, - "Total Node": 483 + "Longest Path": 3, + "Average Path": 3, + "Total Node": 242 }, "operators/string_test/k6_N10_mem32K_40nm": { "test_name": "operators/string_test/k6_N10_mem32K_40nm", @@ -2784,13 +2756,11 @@ "test_coverage(%)": 100, "Latch Drivers": 1, "Po": 241, - "logic element": 241, "latch": 241, "generic logic size": 6, - "Longest Path": 4, - "Average Path": 4, - "Estimated LUTs": 241, - "Total Node": 483 + "Longest Path": 3, + "Average Path": 3, + "Total Node": 242 }, "operators/string_test/no_arch": { "test_name": "operators/string_test/no_arch", @@ -2801,12 +2771,10 @@ "test_coverage(%)": 100, "Latch Drivers": 1, "Po": 241, - "logic element": 241, "latch": 241, - "Longest Path": 4, - "Average Path": 4, - "Estimated LUTs": 241, - "Total Node": 483 + "Longest Path": 3, + "Average Path": 3, + "Total Node": 242 }, "operators/twobits_arithmetic_minus/k6_frac_N10_frac_chain_mem32K_40nm": { "test_name": "operators/twobits_arithmetic_minus/k6_frac_N10_frac_chain_mem32K_40nm", @@ -2819,14 +2787,14 @@ "Latch Drivers": 1, "Pi": 5, "Po": 4, - "logic element": 12, + "logic element": 9, "latch": 3, "Adder": 3, "generic logic size": 4, - "Longest Path": 8, - "Average Path": 5, - "Estimated LUTs": 12, - "Total Node": 19 + "Longest Path": 7, + "Average Path": 4, + "Estimated LUTs": 9, + "Total Node": 16 }, "operators/twobits_arithmetic_minus/k6_N10_40nm": { "test_name": "operators/twobits_arithmetic_minus/k6_N10_40nm", @@ -2839,13 +2807,13 @@ "Latch Drivers": 1, "Pi": 5, "Po": 4, - "logic element": 15, + "logic element": 12, "latch": 3, "generic logic size": 6, - "Longest Path": 8, - "Average Path": 5, - "Estimated LUTs": 15, - "Total Node": 19 + "Longest Path": 7, + "Average Path": 4, + "Estimated LUTs": 12, + "Total Node": 16 }, "operators/twobits_arithmetic_minus/k6_N10_mem32K_40nm": { "test_name": "operators/twobits_arithmetic_minus/k6_N10_mem32K_40nm", @@ -2858,13 +2826,13 @@ "Latch Drivers": 1, "Pi": 5, "Po": 4, - "logic element": 15, + "logic element": 12, "latch": 3, "generic logic size": 6, - "Longest Path": 8, - "Average Path": 5, - "Estimated LUTs": 15, - "Total Node": 19 + "Longest Path": 7, + "Average Path": 4, + "Estimated LUTs": 12, + "Total Node": 16 }, "operators/twobits_arithmetic_minus/no_arch": { "test_name": "operators/twobits_arithmetic_minus/no_arch", @@ -2876,12 +2844,12 @@ "Latch Drivers": 1, "Pi": 5, "Po": 4, - "logic element": 15, + "logic element": 12, "latch": 3, - "Longest Path": 8, - "Average Path": 5, - "Estimated LUTs": 15, - "Total Node": 19 + "Longest Path": 7, + "Average Path": 4, + "Estimated LUTs": 12, + "Total Node": 16 }, "operators/twobits_arithmetic_multiply/k6_frac_N10_frac_chain_mem32K_40nm": { "test_name": "operators/twobits_arithmetic_multiply/k6_frac_N10_frac_chain_mem32K_40nm", @@ -2894,14 +2862,14 @@ "Latch Drivers": 1, "Pi": 5, "Po": 5, - "logic element": 12, + "logic element": 8, "latch": 4, "Multiplier": 1, "generic logic size": 4, - "Longest Path": 8, - "Average Path": 5, - "Estimated LUTs": 12, - "Total Node": 18 + "Longest Path": 7, + "Average Path": 4, + "Estimated LUTs": 8, + "Total Node": 14 }, "operators/twobits_arithmetic_multiply/k6_N10_40nm": { "test_name": "operators/twobits_arithmetic_multiply/k6_N10_40nm", @@ -2914,13 +2882,13 @@ "Latch Drivers": 1, "Pi": 5, "Po": 5, - "logic element": 21, + "logic element": 17, "latch": 4, "generic logic size": 6, - "Longest Path": 9, - "Average Path": 5, - "Estimated LUTs": 21, - "Total Node": 26 + "Longest Path": 8, + "Average Path": 4, + "Estimated LUTs": 17, + "Total Node": 22 }, "operators/twobits_arithmetic_multiply/k6_N10_mem32K_40nm": { "test_name": "operators/twobits_arithmetic_multiply/k6_N10_mem32K_40nm", @@ -2933,14 +2901,14 @@ "Latch Drivers": 1, "Pi": 5, "Po": 5, - "logic element": 12, + "logic element": 8, "latch": 4, "Multiplier": 1, "generic logic size": 6, - "Longest Path": 8, - "Average Path": 5, - "Estimated LUTs": 12, - "Total Node": 18 + "Longest Path": 7, + "Average Path": 4, + "Estimated LUTs": 8, + "Total Node": 14 }, "operators/twobits_arithmetic_multiply/no_arch": { "test_name": "operators/twobits_arithmetic_multiply/no_arch", @@ -2952,12 +2920,12 @@ "Latch Drivers": 1, "Pi": 5, "Po": 5, - "logic element": 21, + "logic element": 17, "latch": 4, - "Longest Path": 9, - "Average Path": 5, - "Estimated LUTs": 21, - "Total Node": 26 + "Longest Path": 8, + "Average Path": 4, + "Estimated LUTs": 17, + "Total Node": 22 }, "operators/twobits_arithmetic_plus/k6_frac_N10_frac_chain_mem32K_40nm": { "test_name": "operators/twobits_arithmetic_plus/k6_frac_N10_frac_chain_mem32K_40nm", @@ -2970,14 +2938,14 @@ "Latch Drivers": 1, "Pi": 5, "Po": 4, - "logic element": 10, + "logic element": 7, "latch": 3, "Adder": 4, "generic logic size": 4, - "Longest Path": 9, - "Average Path": 5, - "Estimated LUTs": 10, - "Total Node": 18 + "Longest Path": 8, + "Average Path": 4, + "Estimated LUTs": 7, + "Total Node": 15 }, "operators/twobits_arithmetic_plus/k6_N10_40nm": { "test_name": "operators/twobits_arithmetic_plus/k6_N10_40nm", @@ -2990,13 +2958,13 @@ "Latch Drivers": 1, "Pi": 5, "Po": 4, - "logic element": 15, + "logic element": 12, "latch": 3, "generic logic size": 6, - "Longest Path": 8, - "Average Path": 5, - "Estimated LUTs": 15, - "Total Node": 19 + "Longest Path": 7, + "Average Path": 4, + "Estimated LUTs": 12, + "Total Node": 16 }, "operators/twobits_arithmetic_plus/k6_N10_mem32K_40nm": { "test_name": "operators/twobits_arithmetic_plus/k6_N10_mem32K_40nm", @@ -3009,13 +2977,13 @@ "Latch Drivers": 1, "Pi": 5, "Po": 4, - "logic element": 15, + "logic element": 12, "latch": 3, "generic logic size": 6, - "Longest Path": 8, - "Average Path": 5, - "Estimated LUTs": 15, - "Total Node": 19 + "Longest Path": 7, + "Average Path": 4, + "Estimated LUTs": 12, + "Total Node": 16 }, "operators/twobits_arithmetic_plus/no_arch": { "test_name": "operators/twobits_arithmetic_plus/no_arch", @@ -3027,12 +2995,12 @@ "Latch Drivers": 1, "Pi": 5, "Po": 4, - "logic element": 15, + "logic element": 12, "latch": 3, - "Longest Path": 8, - "Average Path": 5, - "Estimated LUTs": 15, - "Total Node": 19 + "Longest Path": 7, + "Average Path": 4, + "Estimated LUTs": 12, + "Total Node": 16 }, "operators/twobits_logical_greater_equal_than/k6_frac_N10_frac_chain_mem32K_40nm": { "test_name": "operators/twobits_logical_greater_equal_than/k6_frac_N10_frac_chain_mem32K_40nm", @@ -3045,13 +3013,13 @@ "Latch Drivers": 1, "Pi": 5, "Po": 2, - "logic element": 15, + "logic element": 14, "latch": 1, "generic logic size": 4, - "Longest Path": 10, + "Longest Path": 9, "Average Path": 4, - "Estimated LUTs": 15, - "Total Node": 17 + "Estimated LUTs": 14, + "Total Node": 16 }, "operators/twobits_logical_greater_equal_than/k6_N10_40nm": { "test_name": "operators/twobits_logical_greater_equal_than/k6_N10_40nm", @@ -3064,13 +3032,13 @@ "Latch Drivers": 1, "Pi": 5, "Po": 2, - "logic element": 15, + "logic element": 14, "latch": 1, "generic logic size": 6, - "Longest Path": 10, + "Longest Path": 9, "Average Path": 4, - "Estimated LUTs": 15, - "Total Node": 17 + "Estimated LUTs": 14, + "Total Node": 16 }, "operators/twobits_logical_greater_equal_than/k6_N10_mem32K_40nm": { "test_name": "operators/twobits_logical_greater_equal_than/k6_N10_mem32K_40nm", @@ -3083,13 +3051,13 @@ "Latch Drivers": 1, "Pi": 5, "Po": 2, - "logic element": 15, + "logic element": 14, "latch": 1, "generic logic size": 6, - "Longest Path": 10, + "Longest Path": 9, "Average Path": 4, - "Estimated LUTs": 15, - "Total Node": 17 + "Estimated LUTs": 14, + "Total Node": 16 }, "operators/twobits_logical_greater_equal_than/no_arch": { "test_name": "operators/twobits_logical_greater_equal_than/no_arch", @@ -3101,12 +3069,12 @@ "Latch Drivers": 1, "Pi": 5, "Po": 2, - "logic element": 15, + "logic element": 14, "latch": 1, - "Longest Path": 10, + "Longest Path": 9, "Average Path": 4, - "Estimated LUTs": 15, - "Total Node": 17 + "Estimated LUTs": 14, + "Total Node": 16 }, "operators/twobits_logical_greater_than/k6_frac_N10_frac_chain_mem32K_40nm": { "test_name": "operators/twobits_logical_greater_than/k6_frac_N10_frac_chain_mem32K_40nm", @@ -3119,13 +3087,13 @@ "Latch Drivers": 1, "Pi": 5, "Po": 2, - "logic element": 11, + "logic element": 10, "latch": 1, "generic logic size": 4, - "Longest Path": 9, + "Longest Path": 8, "Average Path": 4, - "Estimated LUTs": 11, - "Total Node": 13 + "Estimated LUTs": 10, + "Total Node": 12 }, "operators/twobits_logical_greater_than/k6_N10_40nm": { "test_name": "operators/twobits_logical_greater_than/k6_N10_40nm", @@ -3138,13 +3106,13 @@ "Latch Drivers": 1, "Pi": 5, "Po": 2, - "logic element": 11, + "logic element": 10, "latch": 1, "generic logic size": 6, - "Longest Path": 9, + "Longest Path": 8, "Average Path": 4, - "Estimated LUTs": 11, - "Total Node": 13 + "Estimated LUTs": 10, + "Total Node": 12 }, "operators/twobits_logical_greater_than/k6_N10_mem32K_40nm": { "test_name": "operators/twobits_logical_greater_than/k6_N10_mem32K_40nm", @@ -3157,13 +3125,13 @@ "Latch Drivers": 1, "Pi": 5, "Po": 2, - "logic element": 11, + "logic element": 10, "latch": 1, "generic logic size": 6, - "Longest Path": 9, + "Longest Path": 8, "Average Path": 4, - "Estimated LUTs": 11, - "Total Node": 13 + "Estimated LUTs": 10, + "Total Node": 12 }, "operators/twobits_logical_greater_than/no_arch": { "test_name": "operators/twobits_logical_greater_than/no_arch", @@ -3175,12 +3143,12 @@ "Latch Drivers": 1, "Pi": 5, "Po": 2, - "logic element": 11, + "logic element": 10, "latch": 1, - "Longest Path": 9, + "Longest Path": 8, "Average Path": 4, - "Estimated LUTs": 11, - "Total Node": 13 + "Estimated LUTs": 10, + "Total Node": 12 }, "operators/twobits_logical_less_equal_than/k6_frac_N10_frac_chain_mem32K_40nm": { "test_name": "operators/twobits_logical_less_equal_than/k6_frac_N10_frac_chain_mem32K_40nm", @@ -3193,13 +3161,13 @@ "Latch Drivers": 1, "Pi": 5, "Po": 2, - "logic element": 15, + "logic element": 14, "latch": 1, "generic logic size": 4, - "Longest Path": 10, + "Longest Path": 9, "Average Path": 4, - "Estimated LUTs": 15, - "Total Node": 17 + "Estimated LUTs": 14, + "Total Node": 16 }, "operators/twobits_logical_less_equal_than/k6_N10_40nm": { "test_name": "operators/twobits_logical_less_equal_than/k6_N10_40nm", @@ -3212,13 +3180,13 @@ "Latch Drivers": 1, "Pi": 5, "Po": 2, - "logic element": 15, + "logic element": 14, "latch": 1, "generic logic size": 6, - "Longest Path": 10, + "Longest Path": 9, "Average Path": 4, - "Estimated LUTs": 15, - "Total Node": 17 + "Estimated LUTs": 14, + "Total Node": 16 }, "operators/twobits_logical_less_equal_than/k6_N10_mem32K_40nm": { "test_name": "operators/twobits_logical_less_equal_than/k6_N10_mem32K_40nm", @@ -3231,13 +3199,13 @@ "Latch Drivers": 1, "Pi": 5, "Po": 2, - "logic element": 15, + "logic element": 14, "latch": 1, "generic logic size": 6, - "Longest Path": 10, + "Longest Path": 9, "Average Path": 4, - "Estimated LUTs": 15, - "Total Node": 17 + "Estimated LUTs": 14, + "Total Node": 16 }, "operators/twobits_logical_less_equal_than/no_arch": { "test_name": "operators/twobits_logical_less_equal_than/no_arch", @@ -3249,12 +3217,12 @@ "Latch Drivers": 1, "Pi": 5, "Po": 2, - "logic element": 15, + "logic element": 14, "latch": 1, - "Longest Path": 10, + "Longest Path": 9, "Average Path": 4, - "Estimated LUTs": 15, - "Total Node": 17 + "Estimated LUTs": 14, + "Total Node": 16 }, "operators/twobits_logical_less_than/k6_frac_N10_frac_chain_mem32K_40nm": { "test_name": "operators/twobits_logical_less_than/k6_frac_N10_frac_chain_mem32K_40nm", @@ -3267,13 +3235,13 @@ "Latch Drivers": 1, "Pi": 5, "Po": 2, - "logic element": 11, + "logic element": 10, "latch": 1, "generic logic size": 4, - "Longest Path": 9, + "Longest Path": 8, "Average Path": 4, - "Estimated LUTs": 11, - "Total Node": 13 + "Estimated LUTs": 10, + "Total Node": 12 }, "operators/twobits_logical_less_than/k6_N10_40nm": { "test_name": "operators/twobits_logical_less_than/k6_N10_40nm", @@ -3286,13 +3254,13 @@ "Latch Drivers": 1, "Pi": 5, "Po": 2, - "logic element": 11, + "logic element": 10, "latch": 1, "generic logic size": 6, - "Longest Path": 9, + "Longest Path": 8, "Average Path": 4, - "Estimated LUTs": 11, - "Total Node": 13 + "Estimated LUTs": 10, + "Total Node": 12 }, "operators/twobits_logical_less_than/k6_N10_mem32K_40nm": { "test_name": "operators/twobits_logical_less_than/k6_N10_mem32K_40nm", @@ -3305,13 +3273,13 @@ "Latch Drivers": 1, "Pi": 5, "Po": 2, - "logic element": 11, + "logic element": 10, "latch": 1, "generic logic size": 6, - "Longest Path": 9, + "Longest Path": 8, "Average Path": 4, - "Estimated LUTs": 11, - "Total Node": 13 + "Estimated LUTs": 10, + "Total Node": 12 }, "operators/twobits_logical_less_than/no_arch": { "test_name": "operators/twobits_logical_less_than/no_arch", @@ -3323,12 +3291,12 @@ "Latch Drivers": 1, "Pi": 5, "Po": 2, - "logic element": 11, + "logic element": 10, "latch": 1, - "Longest Path": 9, + "Longest Path": 8, "Average Path": 4, - "Estimated LUTs": 11, - "Total Node": 13 + "Estimated LUTs": 10, + "Total Node": 12 }, "operators/unary_bitwise_bufnode/k6_frac_N10_frac_chain_mem32K_40nm": { "test_name": "operators/unary_bitwise_bufnode/k6_frac_N10_frac_chain_mem32K_40nm", @@ -3407,13 +3375,13 @@ "Latch Drivers": 1, "Pi": 2, "Po": 2, - "logic element": 7, + "logic element": 6, "latch": 1, "generic logic size": 4, - "Longest Path": 8, + "Longest Path": 7, "Average Path": 4, - "Estimated LUTs": 7, - "Total Node": 9 + "Estimated LUTs": 6, + "Total Node": 8 }, "operators/unary_bitwise_not/k6_N10_40nm": { "test_name": "operators/unary_bitwise_not/k6_N10_40nm", @@ -3426,13 +3394,13 @@ "Latch Drivers": 1, "Pi": 2, "Po": 2, - "logic element": 7, + "logic element": 6, "latch": 1, "generic logic size": 6, - "Longest Path": 8, + "Longest Path": 7, "Average Path": 4, - "Estimated LUTs": 7, - "Total Node": 9 + "Estimated LUTs": 6, + "Total Node": 8 }, "operators/unary_bitwise_not/k6_N10_mem32K_40nm": { "test_name": "operators/unary_bitwise_not/k6_N10_mem32K_40nm", @@ -3445,13 +3413,13 @@ "Latch Drivers": 1, "Pi": 2, "Po": 2, - "logic element": 7, + "logic element": 6, "latch": 1, "generic logic size": 6, - "Longest Path": 8, + "Longest Path": 7, "Average Path": 4, - "Estimated LUTs": 7, - "Total Node": 9 + "Estimated LUTs": 6, + "Total Node": 8 }, "operators/unary_bitwise_not/no_arch": { "test_name": "operators/unary_bitwise_not/no_arch", @@ -3463,12 +3431,12 @@ "Latch Drivers": 1, "Pi": 2, "Po": 2, - "logic element": 7, + "logic element": 6, "latch": 1, - "Longest Path": 8, + "Longest Path": 7, "Average Path": 4, - "Estimated LUTs": 7, - "Total Node": 9 + "Estimated LUTs": 6, + "Total Node": 8 }, "operators/twobits_arithmetic_uminus/k6_N10_40nm": { "test_name": "operators/twobits_arithmetic_uminus/k6_N10_40nm", @@ -3481,13 +3449,13 @@ "Latch Drivers": 1, "Pi": 3, "Po": 4, - "logic element": 15, + "logic element": 12, "latch": 3, "generic logic size": 6, - "Longest Path": 8, - "Average Path": 5, - "Estimated LUTs": 15, - "Total Node": 19 + "Longest Path": 7, + "Average Path": 4, + "Estimated LUTs": 12, + "Total Node": 16 }, "operators/twobits_arithmetic_uminus/k6_N10_mem32K_40nm": { "test_name": "operators/twobits_arithmetic_uminus/k6_N10_mem32K_40nm", @@ -3500,13 +3468,13 @@ "Latch Drivers": 1, "Pi": 3, "Po": 4, - "logic element": 15, + "logic element": 12, "latch": 3, "generic logic size": 6, - "Longest Path": 8, - "Average Path": 5, - "Estimated LUTs": 15, - "Total Node": 19 + "Longest Path": 7, + "Average Path": 4, + "Estimated LUTs": 12, + "Total Node": 16 }, "operators/twobits_arithmetic_uminus/k6_frac_N10_frac_chain_mem32K_40nm": { "test_name": "operators/twobits_arithmetic_uminus/k6_frac_N10_frac_chain_mem32K_40nm", @@ -3519,14 +3487,14 @@ "Latch Drivers": 1, "Pi": 3, "Po": 4, - "logic element": 12, + "logic element": 9, "latch": 3, "Adder": 3, "generic logic size": 4, - "Longest Path": 8, - "Average Path": 5, - "Estimated LUTs": 12, - "Total Node": 19 + "Longest Path": 7, + "Average Path": 4, + "Estimated LUTs": 9, + "Total Node": 16 }, "operators/twobits_arithmetic_uminus/no_arch": { "test_name": "operators/twobits_arithmetic_uminus/no_arch", @@ -3538,12 +3506,12 @@ "Latch Drivers": 1, "Pi": 3, "Po": 4, - "logic element": 15, + "logic element": 12, "latch": 3, - "Longest Path": 8, - "Average Path": 5, - "Estimated LUTs": 15, - "Total Node": 19 + "Longest Path": 7, + "Average Path": 4, + "Estimated LUTs": 12, + "Total Node": 16 }, "DEFAULT": { "test_name": "n/a", diff --git a/ODIN_II/regression_test/benchmark/task/preprocessor/simulation_result.json b/ODIN_II/regression_test/benchmark/task/preprocessor/simulation_result.json index a13157f6ebf..9c950dd13ed 100644 --- a/ODIN_II/regression_test/benchmark/task/preprocessor/simulation_result.json +++ b/ODIN_II/regression_test/benchmark/task/preprocessor/simulation_result.json @@ -155,14 +155,14 @@ "max_rss(MiB)": 14.5, "exec_time(ms)": 3.2, "simulation_time(ms)": 0.1, - "test_coverage(%)": 62.5, + "test_coverage(%)": 71.4, "Pi": 1, "Po": 1, - "logic element": 2, - "Longest Path": 4, - "Average Path": 4, - "Estimated LUTs": 2, - "Total Node": 2 + "logic element": 1, + "Longest Path": 3, + "Average Path": 3, + "Estimated LUTs": 1, + "Total Node": 1 }, "preprocessor/ifdef_undefined/no_arch": { "test_name": "preprocessor/ifdef_undefined/no_arch", @@ -210,11 +210,11 @@ "test_coverage(%)": 100, "Pi": 2, "Po": 1, - "logic element": 4, - "Longest Path": 4, - "Average Path": 4, - "Estimated LUTs": 4, - "Total Node": 4 + "logic element": 2, + "Longest Path": 3, + "Average Path": 3, + "Estimated LUTs": 2, + "Total Node": 2 }, "preprocessor/nested_ifdef_alldef/no_arch": { "test_name": "preprocessor/nested_ifdef_alldef/no_arch", @@ -250,11 +250,11 @@ "simulation_time(ms)": 0.6, "test_coverage(%)": 100, "Po": 3, - "logic element": 24, - "Longest Path": 4, - "Average Path": 4, - "Estimated LUTs": 24, - "Total Node": 24 + "logic element": 12, + "Longest Path": 3, + "Average Path": 3, + "Estimated LUTs": 12, + "Total Node": 12 }, "preprocessor/nested_ifdef_outsidedef/no_arch": { "test_name": "preprocessor/nested_ifdef_outsidedef/no_arch", diff --git a/ODIN_II/regression_test/benchmark/task/syntax/simulation_result.json b/ODIN_II/regression_test/benchmark/task/syntax/simulation_result.json index 911cd897068..f1d96ba9bdc 100644 --- a/ODIN_II/regression_test/benchmark/task/syntax/simulation_result.json +++ b/ODIN_II/regression_test/benchmark/task/syntax/simulation_result.json @@ -10,13 +10,13 @@ "Latch Drivers": 1, "Pi": 9, "Po": 8, - "logic element": 20, + "logic element": 12, "latch": 8, "generic logic size": 4, - "Longest Path": 7, - "Average Path": 5, - "Estimated LUTs": 20, - "Total Node": 29 + "Longest Path": 6, + "Average Path": 4, + "Estimated LUTs": 12, + "Total Node": 21 }, "syntax/8_bit_for_pass_through_module/k6_frac_N10_frac_chain_mem32K_40nm": { "test_name": "syntax/8_bit_for_pass_through_module/k6_frac_N10_frac_chain_mem32K_40nm", @@ -29,13 +29,13 @@ "Latch Drivers": 1, "Pi": 9, "Po": 8, - "logic element": 48, + "logic element": 40, "latch": 8, "generic logic size": 4, - "Longest Path": 7, - "Average Path": 5, - "Estimated LUTs": 48, - "Total Node": 57 + "Longest Path": 6, + "Average Path": 4, + "Estimated LUTs": 40, + "Total Node": 49 }, "syntax/8_bit_for_pass_through_module/no_arch": { "test_name": "syntax/8_bit_for_pass_through_module/no_arch", @@ -47,12 +47,12 @@ "Latch Drivers": 1, "Pi": 9, "Po": 8, - "logic element": 48, + "logic element": 40, "latch": 8, - "Longest Path": 7, - "Average Path": 5, - "Estimated LUTs": 48, - "Total Node": 57 + "Longest Path": 6, + "Average Path": 4, + "Estimated LUTs": 40, + "Total Node": 49 }, "syntax/8_bit_for_pass_through/no_arch": { "test_name": "syntax/8_bit_for_pass_through/no_arch", @@ -64,12 +64,12 @@ "Latch Drivers": 1, "Pi": 9, "Po": 8, - "logic element": 20, + "logic element": 12, "latch": 8, - "Longest Path": 7, - "Average Path": 5, - "Estimated LUTs": 20, - "Total Node": 29 + "Longest Path": 6, + "Average Path": 4, + "Estimated LUTs": 12, + "Total Node": 21 }, "syntax/8_bit_for_pass_through_off_by_1/k6_frac_N10_frac_chain_mem32K_40nm": { "test_name": "syntax/8_bit_for_pass_through_off_by_1/k6_frac_N10_frac_chain_mem32K_40nm", @@ -82,13 +82,13 @@ "Latch Drivers": 1, "Pi": 9, "Po": 8, - "logic element": 20, + "logic element": 12, "latch": 8, "generic logic size": 4, - "Longest Path": 7, - "Average Path": 5, - "Estimated LUTs": 20, - "Total Node": 29 + "Longest Path": 6, + "Average Path": 4, + "Estimated LUTs": 12, + "Total Node": 21 }, "syntax/8_bit_for_pass_through_off_by_1/no_arch": { "test_name": "syntax/8_bit_for_pass_through_off_by_1/no_arch", @@ -100,12 +100,12 @@ "Latch Drivers": 1, "Pi": 9, "Po": 8, - "logic element": 20, + "logic element": 12, "latch": 8, - "Longest Path": 7, - "Average Path": 5, - "Estimated LUTs": 20, - "Total Node": 29 + "Longest Path": 6, + "Average Path": 4, + "Estimated LUTs": 12, + "Total Node": 21 }, "syntax/8_bit_pass_through_module/k6_frac_N10_frac_chain_mem32K_40nm": { "test_name": "syntax/8_bit_pass_through_module/k6_frac_N10_frac_chain_mem32K_40nm", @@ -118,13 +118,13 @@ "Latch Drivers": 1, "Pi": 9, "Po": 8, - "logic element": 48, + "logic element": 40, "latch": 8, "generic logic size": 4, - "Longest Path": 7, - "Average Path": 5, - "Estimated LUTs": 48, - "Total Node": 57 + "Longest Path": 6, + "Average Path": 4, + "Estimated LUTs": 40, + "Total Node": 49 }, "syntax/8_bit_pass_through_module/no_arch": { "test_name": "syntax/8_bit_pass_through_module/no_arch", @@ -136,12 +136,12 @@ "Latch Drivers": 1, "Pi": 9, "Po": 8, - "logic element": 48, + "logic element": 40, "latch": 8, - "Longest Path": 7, - "Average Path": 5, - "Estimated LUTs": 48, - "Total Node": 57 + "Longest Path": 6, + "Average Path": 4, + "Estimated LUTs": 40, + "Total Node": 49 }, "syntax/and_primitive/k6_frac_N10_frac_chain_mem32K_40nm": { "test_name": "syntax/and_primitive/k6_frac_N10_frac_chain_mem32K_40nm", @@ -185,12 +185,12 @@ "test_coverage(%)": 71.4, "Pi": 6, "Po": 3, - "logic element": 6, + "logic element": 3, "generic logic size": 4, - "Longest Path": 4, - "Average Path": 4, - "Estimated LUTs": 6, - "Total Node": 6 + "Longest Path": 3, + "Average Path": 3, + "Estimated LUTs": 3, + "Total Node": 3 }, "syntax/bm_dag7_mod_log/no_arch": { "test_name": "syntax/bm_dag7_mod_log/no_arch", @@ -201,11 +201,11 @@ "test_coverage(%)": 71.4, "Pi": 6, "Po": 3, - "logic element": 6, - "Longest Path": 4, - "Average Path": 4, - "Estimated LUTs": 6, - "Total Node": 6 + "logic element": 3, + "Longest Path": 3, + "Average Path": 3, + "Estimated LUTs": 3, + "Total Node": 3 }, "syntax/bm_DL_4_bit_updown_counter/k6_frac_N10_frac_chain_mem32K_40nm": { "test_name": "syntax/bm_DL_4_bit_updown_counter/k6_frac_N10_frac_chain_mem32K_40nm", @@ -516,13 +516,13 @@ "Latch Drivers": 1, "Pi": 9, "Po": 8, - "logic element": 20, + "logic element": 12, "latch": 8, "generic logic size": 4, - "Longest Path": 7, - "Average Path": 5, - "Estimated LUTs": 20, - "Total Node": 29 + "Longest Path": 6, + "Average Path": 4, + "Estimated LUTs": 12, + "Total Node": 21 }, "syntax/complex_post_for_loop/no_arch": { "test_name": "syntax/complex_post_for_loop/no_arch", @@ -534,12 +534,12 @@ "Latch Drivers": 1, "Pi": 9, "Po": 8, - "logic element": 20, + "logic element": 12, "latch": 8, - "Longest Path": 7, - "Average Path": 5, - "Estimated LUTs": 20, - "Total Node": 29 + "Longest Path": 6, + "Average Path": 4, + "Estimated LUTs": 12, + "Total Node": 21 }, "syntax/constant_module_inst/k6_frac_N10_frac_chain_mem32K_40nm": { "test_name": "syntax/constant_module_inst/k6_frac_N10_frac_chain_mem32K_40nm", @@ -735,13 +735,13 @@ "Latch Drivers": 1, "Pi": 5, "Po": 8, - "logic element": 20, + "logic element": 16, "latch": 8, "generic logic size": 4, "Longest Path": 7, - "Average Path": 5, - "Estimated LUTs": 20, - "Total Node": 29 + "Average Path": 4, + "Estimated LUTs": 16, + "Total Node": 25 }, "syntax/for_loop_adv_post/no_arch": { "test_name": "syntax/for_loop_adv_post/no_arch", @@ -753,12 +753,12 @@ "Latch Drivers": 1, "Pi": 5, "Po": 8, - "logic element": 20, + "logic element": 16, "latch": 8, "Longest Path": 7, - "Average Path": 5, - "Estimated LUTs": 20, - "Total Node": 29 + "Average Path": 4, + "Estimated LUTs": 16, + "Total Node": 25 }, "syntax/for_loop_adv_pre/k6_frac_N10_frac_chain_mem32K_40nm": { "test_name": "syntax/for_loop_adv_pre/k6_frac_N10_frac_chain_mem32K_40nm", @@ -771,13 +771,13 @@ "Latch Drivers": 1, "Pi": 9, "Po": 8, - "logic element": 20, + "logic element": 12, "latch": 8, "generic logic size": 4, - "Longest Path": 7, - "Average Path": 5, - "Estimated LUTs": 20, - "Total Node": 29 + "Longest Path": 6, + "Average Path": 4, + "Estimated LUTs": 12, + "Total Node": 21 }, "syntax/for_loop_adv_pre/no_arch": { "test_name": "syntax/for_loop_adv_pre/no_arch", @@ -789,12 +789,12 @@ "Latch Drivers": 1, "Pi": 9, "Po": 8, - "logic element": 20, + "logic element": 12, "latch": 8, - "Longest Path": 7, - "Average Path": 5, - "Estimated LUTs": 20, - "Total Node": 29 + "Longest Path": 6, + "Average Path": 4, + "Estimated LUTs": 12, + "Total Node": 21 }, "syntax/freq_division/k6_frac_N10_frac_chain_mem32K_40nm": { "test_name": "syntax/freq_division/k6_frac_N10_frac_chain_mem32K_40nm", @@ -843,14 +843,14 @@ "Latch Drivers": 1, "Pi": 5, "Po": 4, - "logic element": 10, + "logic element": 7, "latch": 3, "Adder": 4, "generic logic size": 4, - "Longest Path": 9, - "Average Path": 5, - "Estimated LUTs": 10, - "Total Node": 18 + "Longest Path": 8, + "Average Path": 4, + "Estimated LUTs": 7, + "Total Node": 15 }, "syntax/function_automatic/no_arch": { "test_name": "syntax/function_automatic/no_arch", @@ -862,12 +862,12 @@ "Latch Drivers": 1, "Pi": 5, "Po": 4, - "logic element": 15, + "logic element": 12, "latch": 3, - "Longest Path": 8, - "Average Path": 5, - "Estimated LUTs": 15, - "Total Node": 19 + "Longest Path": 7, + "Average Path": 4, + "Estimated LUTs": 12, + "Total Node": 16 }, "syntax/function_syntax/k6_frac_N10_frac_chain_mem32K_40nm": { "test_name": "syntax/function_syntax/k6_frac_N10_frac_chain_mem32K_40nm", @@ -912,13 +912,13 @@ "Latch Drivers": 1, "Pi": 8, "Po": 8, - "logic element": 20, + "logic element": 13, "latch": 8, "generic logic size": 4, "Longest Path": 7, - "Average Path": 5, - "Estimated LUTs": 20, - "Total Node": 29 + "Average Path": 4, + "Estimated LUTs": 13, + "Total Node": 22 }, "syntax/h7_of_8_bit_for_pass_through/no_arch": { "test_name": "syntax/h7_of_8_bit_for_pass_through/no_arch", @@ -930,12 +930,12 @@ "Latch Drivers": 1, "Pi": 8, "Po": 8, - "logic element": 20, + "logic element": 13, "latch": 8, "Longest Path": 7, - "Average Path": 5, - "Estimated LUTs": 20, - "Total Node": 29 + "Average Path": 4, + "Estimated LUTs": 13, + "Total Node": 22 }, "syntax/ifdef-else-syntax/k6_frac_N10_frac_chain_mem32K_40nm": { "test_name": "syntax/ifdef-else-syntax/k6_frac_N10_frac_chain_mem32K_40nm", @@ -948,14 +948,14 @@ "Latch Drivers": 1, "Pi": 47, "Po": 78, - "logic element": 110, + "logic element": 63, "latch": 71, "Multiplier": 3, "generic logic size": 4, - "Longest Path": 9, + "Longest Path": 8, "Average Path": 4, - "Estimated LUTs": 110, - "Total Node": 185 + "Estimated LUTs": 63, + "Total Node": 138 }, "syntax/ifdef-else-syntax/no_arch": { "test_name": "syntax/ifdef-else-syntax/no_arch", @@ -967,12 +967,12 @@ "Latch Drivers": 1, "Pi": 47, "Po": 78, - "logic element": 795, + "logic element": 748, "latch": 71, - "Longest Path": 26, - "Average Path": 6, - "Estimated LUTs": 795, - "Total Node": 867 + "Longest Path": 25, + "Average Path": 5, + "Estimated LUTs": 748, + "Total Node": 820 }, "syntax/ifndef-else-syntax/k6_frac_N10_frac_chain_mem32K_40nm": { "test_name": "syntax/ifndef-else-syntax/k6_frac_N10_frac_chain_mem32K_40nm", @@ -985,14 +985,14 @@ "Latch Drivers": 1, "Pi": 47, "Po": 78, - "logic element": 110, + "logic element": 63, "latch": 71, "Multiplier": 3, "generic logic size": 4, - "Longest Path": 9, + "Longest Path": 8, "Average Path": 4, - "Estimated LUTs": 110, - "Total Node": 185 + "Estimated LUTs": 63, + "Total Node": 138 }, "syntax/ifndef-else-syntax/no_arch": { "test_name": "syntax/ifndef-else-syntax/no_arch", @@ -1004,12 +1004,12 @@ "Latch Drivers": 1, "Pi": 47, "Po": 78, - "logic element": 795, + "logic element": 748, "latch": 71, - "Longest Path": 26, - "Average Path": 6, - "Estimated LUTs": 795, - "Total Node": 867 + "Longest Path": 25, + "Average Path": 5, + "Estimated LUTs": 748, + "Total Node": 820 }, "syntax/include-syntax/k6_frac_N10_frac_chain_mem32K_40nm": { "test_name": "syntax/include-syntax/k6_frac_N10_frac_chain_mem32K_40nm", @@ -1022,14 +1022,14 @@ "Latch Drivers": 1, "Pi": 47, "Po": 78, - "logic element": 110, + "logic element": 63, "latch": 71, "Multiplier": 3, "generic logic size": 4, - "Longest Path": 9, + "Longest Path": 8, "Average Path": 4, - "Estimated LUTs": 110, - "Total Node": 185 + "Estimated LUTs": 63, + "Total Node": 138 }, "syntax/include-syntax/no_arch": { "test_name": "syntax/include-syntax/no_arch", @@ -1041,12 +1041,12 @@ "Latch Drivers": 1, "Pi": 47, "Po": 78, - "logic element": 795, + "logic element": 748, "latch": 71, - "Longest Path": 26, - "Average Path": 6, - "Estimated LUTs": 795, - "Total Node": 867 + "Longest Path": 25, + "Average Path": 5, + "Estimated LUTs": 748, + "Total Node": 820 }, "syntax/inferred_DPram/k6_frac_N10_frac_chain_mem32K_40nm": { "test_name": "syntax/inferred_DPram/k6_frac_N10_frac_chain_mem32K_40nm", @@ -1059,14 +1059,12 @@ "Latch Drivers": 1, "Pi": 35, "Po": 32, - "logic element": 32, "latch": 32, "Memory": 32, "generic logic size": 4, - "Longest Path": 5, + "Longest Path": 4, "Average Path": 4, - "Estimated LUTs": 32, - "Total Node": 97 + "Total Node": 65 }, "syntax/inferred_DPram/no_arch": { "test_name": "syntax/inferred_DPram/no_arch", @@ -1078,12 +1076,12 @@ "Latch Drivers": 1, "Pi": 35, "Po": 32, - "logic element": 878, + "logic element": 846, "latch": 288, - "Longest Path": 12, - "Average Path": 5, - "Estimated LUTs": 878, - "Total Node": 1167 + "Longest Path": 11, + "Average Path": 4, + "Estimated LUTs": 846, + "Total Node": 1135 }, "syntax/inferred_ram_w_clog2/k6_frac_N10_frac_chain_mem32K_40nm": { "test_name": "syntax/inferred_ram_w_clog2/k6_frac_N10_frac_chain_mem32K_40nm", @@ -1096,14 +1094,14 @@ "Latch Drivers": 1, "Pi": 37, "Po": 160, - "logic element": 160, + "logic element": 32, "latch": 128, "Memory": 96, "generic logic size": 4, - "Longest Path": 5, - "Average Path": 4, - "Estimated LUTs": 160, - "Total Node": 385 + "Longest Path": 4, + "Average Path": 3, + "Estimated LUTs": 32, + "Total Node": 257 }, "syntax/inferred_ram_w_clog2/no_arch": { "test_name": "syntax/inferred_ram_w_clog2/no_arch", @@ -1115,12 +1113,12 @@ "Latch Drivers": 1, "Pi": 37, "Po": 160, - "logic element": 9982, + "logic element": 9854, "latch": 3200, - "Longest Path": 12, - "Average Path": 5, - "Estimated LUTs": 9982, - "Total Node": 13183 + "Longest Path": 11, + "Average Path": 4, + "Estimated LUTs": 9854, + "Total Node": 13055 }, "syntax/inferred_SPram/k6_frac_N10_frac_chain_mem32K_40nm": { "test_name": "syntax/inferred_SPram/k6_frac_N10_frac_chain_mem32K_40nm", @@ -1133,13 +1131,11 @@ "Latch Drivers": 1, "Pi": 32, "Po": 32, - "logic element": 32, "latch": 32, "generic logic size": 4, - "Longest Path": 4, - "Average Path": 4, - "Estimated LUTs": 32, - "Total Node": 65 + "Longest Path": 3, + "Average Path": 3, + "Total Node": 33 }, "syntax/inferred_SPram/no_arch": { "test_name": "syntax/inferred_SPram/no_arch", @@ -1151,12 +1147,10 @@ "Latch Drivers": 1, "Pi": 32, "Po": 32, - "logic element": 32, "latch": 32, - "Longest Path": 4, - "Average Path": 4, - "Estimated LUTs": 32, - "Total Node": 65 + "Longest Path": 3, + "Average Path": 3, + "Total Node": 33 }, "syntax/instantiated_by_name_function_valid/k6_frac_N10_frac_chain_mem32K_40nm": { "test_name": "syntax/instantiated_by_name_function_valid/k6_frac_N10_frac_chain_mem32K_40nm", @@ -1169,14 +1163,14 @@ "Latch Drivers": 1, "Pi": 5, "Po": 4, - "logic element": 10, + "logic element": 7, "latch": 3, "Adder": 4, "generic logic size": 4, - "Longest Path": 9, - "Average Path": 5, - "Estimated LUTs": 10, - "Total Node": 18 + "Longest Path": 8, + "Average Path": 4, + "Estimated LUTs": 7, + "Total Node": 15 }, "syntax/instantiated_by_name_function_valid/no_arch": { "test_name": "syntax/instantiated_by_name_function_valid/no_arch", @@ -1188,12 +1182,12 @@ "Latch Drivers": 1, "Pi": 5, "Po": 4, - "logic element": 15, + "logic element": 12, "latch": 3, - "Longest Path": 8, - "Average Path": 5, - "Estimated LUTs": 15, - "Total Node": 19 + "Longest Path": 7, + "Average Path": 4, + "Estimated LUTs": 12, + "Total Node": 16 }, "syntax/instantiated_by_name_task_valid/k6_frac_N10_frac_chain_mem32K_40nm": { "test_name": "syntax/instantiated_by_name_task_valid/k6_frac_N10_frac_chain_mem32K_40nm", @@ -1206,14 +1200,14 @@ "Latch Drivers": 1, "Pi": 5, "Po": 4, - "logic element": 10, + "logic element": 7, "latch": 3, "Adder": 4, "generic logic size": 4, - "Longest Path": 9, - "Average Path": 5, - "Estimated LUTs": 10, - "Total Node": 18 + "Longest Path": 8, + "Average Path": 4, + "Estimated LUTs": 7, + "Total Node": 15 }, "syntax/instantiated_by_name_task_valid/no_arch": { "test_name": "syntax/instantiated_by_name_task_valid/no_arch", @@ -1225,12 +1219,12 @@ "Latch Drivers": 1, "Pi": 5, "Po": 4, - "logic element": 15, + "logic element": 12, "latch": 3, - "Longest Path": 8, - "Average Path": 5, - "Estimated LUTs": 15, - "Total Node": 19 + "Longest Path": 7, + "Average Path": 4, + "Estimated LUTs": 12, + "Total Node": 16 }, "syntax/instantiating_by_name_valid/k6_frac_N10_frac_chain_mem32K_40nm": { "test_name": "syntax/instantiating_by_name_valid/k6_frac_N10_frac_chain_mem32K_40nm", @@ -1275,13 +1269,13 @@ "Latch Drivers": 1, "Pi": 5, "Po": 8, - "logic element": 20, + "logic element": 16, "latch": 8, "generic logic size": 4, "Longest Path": 7, - "Average Path": 5, - "Estimated LUTs": 20, - "Total Node": 29 + "Average Path": 4, + "Estimated LUTs": 16, + "Total Node": 25 }, "syntax/l2_and_h2_of_8_bit_for_pass_through/no_arch": { "test_name": "syntax/l2_and_h2_of_8_bit_for_pass_through/no_arch", @@ -1293,12 +1287,12 @@ "Latch Drivers": 1, "Pi": 5, "Po": 8, - "logic element": 20, + "logic element": 16, "latch": 8, "Longest Path": 7, - "Average Path": 5, - "Estimated LUTs": 20, - "Total Node": 29 + "Average Path": 4, + "Estimated LUTs": 16, + "Total Node": 25 }, "syntax/macro_in_module_declaration/k6_frac_N10_frac_chain_mem32K_40nm": { "test_name": "syntax/macro_in_module_declaration/k6_frac_N10_frac_chain_mem32K_40nm", @@ -1311,13 +1305,11 @@ "Latch Drivers": 1, "Pi": 32, "Po": 32, - "logic element": 32, "latch": 32, "generic logic size": 4, - "Longest Path": 4, - "Average Path": 4, - "Estimated LUTs": 32, - "Total Node": 65 + "Longest Path": 3, + "Average Path": 3, + "Total Node": 33 }, "syntax/macro_in_module_declaration/no_arch": { "test_name": "syntax/macro_in_module_declaration/no_arch", @@ -1329,12 +1321,10 @@ "Latch Drivers": 1, "Pi": 32, "Po": 32, - "logic element": 32, "latch": 32, - "Longest Path": 4, - "Average Path": 4, - "Estimated LUTs": 32, - "Total Node": 65 + "Longest Path": 3, + "Average Path": 3, + "Total Node": 33 }, "syntax/memlooptesting/k6_frac_N10_frac_chain_mem32K_40nm": { "test_name": "syntax/memlooptesting/k6_frac_N10_frac_chain_mem32K_40nm", @@ -1347,14 +1337,14 @@ "Latch Drivers": 1, "Pi": 38, "Po": 32, - "logic element": 100, + "logic element": 68, "latch": 32, "Memory": 32, "generic logic size": 4, - "Longest Path": 7, - "Average Path": 5, - "Estimated LUTs": 100, - "Total Node": 165 + "Longest Path": 6, + "Average Path": 4, + "Estimated LUTs": 68, + "Total Node": 133 }, "syntax/memlooptesting/no_arch": { "test_name": "syntax/memlooptesting/no_arch", @@ -1366,12 +1356,12 @@ "Latch Drivers": 1, "Pi": 38, "Po": 32, - "logic element": 1192, + "logic element": 1160, "latch": 544, - "Longest Path": 13, - "Average Path": 6, - "Estimated LUTs": 1192, - "Total Node": 1737 + "Longest Path": 12, + "Average Path": 5, + "Estimated LUTs": 1160, + "Total Node": 1705 }, "syntax/multi_clock_reader_writer/k6_frac_N10_frac_chain_mem32K_40nm": { "test_name": "syntax/multi_clock_reader_writer/k6_frac_N10_frac_chain_mem32K_40nm", @@ -1384,13 +1374,13 @@ "Latch Drivers": 2, "Pi": 4, "Po": 4, - "logic element": 144, + "logic element": 140, "latch": 34, "generic logic size": 4, - "Longest Path": 27, - "Average Path": 5, - "Estimated LUTs": 386, - "Total Node": 180 + "Longest Path": 26, + "Average Path": 4, + "Estimated LUTs": 382, + "Total Node": 176 }, "syntax/multi_clock_reader_writer/no_arch": { "test_name": "syntax/multi_clock_reader_writer/no_arch", @@ -1402,12 +1392,12 @@ "Latch Drivers": 2, "Pi": 4, "Po": 4, - "logic element": 144, + "logic element": 140, "latch": 34, - "Longest Path": 27, - "Average Path": 5, - "Estimated LUTs": 144, - "Total Node": 180 + "Longest Path": 26, + "Average Path": 4, + "Estimated LUTs": 140, + "Total Node": 176 }, "syntax/multi_edge_reader_writer/k6_frac_N10_frac_chain_mem32K_40nm": { "test_name": "syntax/multi_edge_reader_writer/k6_frac_N10_frac_chain_mem32K_40nm", @@ -1420,14 +1410,12 @@ "Latch Drivers": 1, "Pi": 8, "Po": 4, - "logic element": 4, "latch": 4, "Memory": 4, "generic logic size": 4, - "Longest Path": 5, + "Longest Path": 4, "Average Path": 4, - "Estimated LUTs": 4, - "Total Node": 13 + "Total Node": 9 }, "syntax/multi_edge_reader_writer/no_arch": { "test_name": "syntax/multi_edge_reader_writer/no_arch", @@ -1439,12 +1427,12 @@ "Latch Drivers": 1, "Pi": 8, "Po": 4, - "logic element": 80, + "logic element": 76, "latch": 20, - "Longest Path": 12, - "Average Path": 5, - "Estimated LUTs": 80, - "Total Node": 101 + "Longest Path": 11, + "Average Path": 4, + "Estimated LUTs": 76, + "Total Node": 97 }, "syntax/multi_module_io_data_types/k6_frac_N10_frac_chain_mem32K_40nm": { "test_name": "syntax/multi_module_io_data_types/k6_frac_N10_frac_chain_mem32K_40nm", @@ -1521,14 +1509,14 @@ "Latch Drivers": 1, "Pi": 47, "Po": 78, - "logic element": 110, + "logic element": 63, "latch": 71, "Multiplier": 3, "generic logic size": 4, - "Longest Path": 9, + "Longest Path": 8, "Average Path": 4, - "Estimated LUTs": 110, - "Total Node": 185 + "Estimated LUTs": 63, + "Total Node": 138 }, "syntax/nested-ifdef-syntax/no_arch": { "test_name": "syntax/nested-ifdef-syntax/no_arch", @@ -1540,12 +1528,12 @@ "Latch Drivers": 1, "Pi": 47, "Po": 78, - "logic element": 795, + "logic element": 748, "latch": 71, - "Longest Path": 26, - "Average Path": 6, - "Estimated LUTs": 795, - "Total Node": 867 + "Longest Path": 25, + "Average Path": 5, + "Estimated LUTs": 748, + "Total Node": 820 }, "syntax/no_input/k6_frac_N10_frac_chain_mem32K_40nm": { "test_name": "syntax/no_input/k6_frac_N10_frac_chain_mem32K_40nm", @@ -1553,7 +1541,7 @@ "blif": "no_input.blif", "exit": 134, "errors": [ - "[PARSE_BLIF] Error: Could not hook up the pin and_primitive^BUF~1: not available." + "[PARSE_BLIF] Error: Could not hook up the pin and_primitive^out: not available." ] }, "syntax/no_input/no_arch": { @@ -1561,7 +1549,7 @@ "blif": "no_input.blif", "exit": 134, "errors": [ - "[PARSE_BLIF] Error: Could not hook up the pin and_primitive^BUF~1: not available." + "[PARSE_BLIF] Error: Could not hook up the pin and_primitive^out: not available." ] }, "syntax/no_output/k6_frac_N10_frac_chain_mem32K_40nm": { @@ -1661,14 +1649,14 @@ "Latch Drivers": 1, "Pi": 5, "Po": 4, - "logic element": 10, + "logic element": 7, "latch": 3, "Adder": 8, "generic logic size": 4, - "Longest Path": 10, - "Average Path": 5, - "Estimated LUTs": 10, - "Total Node": 22 + "Longest Path": 9, + "Average Path": 4, + "Estimated LUTs": 7, + "Total Node": 19 }, "syntax/preprocessor_complex_define/no_arch": { "test_name": "syntax/preprocessor_complex_define/no_arch", @@ -1680,12 +1668,12 @@ "Latch Drivers": 1, "Pi": 5, "Po": 4, - "logic element": 20, + "logic element": 17, "latch": 3, - "Longest Path": 9, - "Average Path": 5, - "Estimated LUTs": 20, - "Total Node": 24 + "Longest Path": 8, + "Average Path": 4, + "Estimated LUTs": 17, + "Total Node": 21 }, "syntax/preprocessor_define/k6_frac_N10_frac_chain_mem32K_40nm": { "test_name": "syntax/preprocessor_define/k6_frac_N10_frac_chain_mem32K_40nm", @@ -1698,14 +1686,14 @@ "Latch Drivers": 1, "Pi": 5, "Po": 4, - "logic element": 10, + "logic element": 7, "latch": 3, "Adder": 8, "generic logic size": 4, - "Longest Path": 10, - "Average Path": 5, - "Estimated LUTs": 10, - "Total Node": 22 + "Longest Path": 9, + "Average Path": 4, + "Estimated LUTs": 7, + "Total Node": 19 }, "syntax/preprocessor_define/no_arch": { "test_name": "syntax/preprocessor_define/no_arch", @@ -1717,12 +1705,12 @@ "Latch Drivers": 1, "Pi": 5, "Po": 4, - "logic element": 20, + "logic element": 17, "latch": 3, - "Longest Path": 9, - "Average Path": 5, - "Estimated LUTs": 20, - "Total Node": 24 + "Longest Path": 8, + "Average Path": 4, + "Estimated LUTs": 17, + "Total Node": 21 }, "syntax/preprocessor_define_with_comment/k6_frac_N10_frac_chain_mem32K_40nm": { "test_name": "syntax/preprocessor_define_with_comment/k6_frac_N10_frac_chain_mem32K_40nm", @@ -1735,14 +1723,14 @@ "Latch Drivers": 1, "Pi": 5, "Po": 4, - "logic element": 10, + "logic element": 7, "latch": 3, "Adder": 8, "generic logic size": 4, - "Longest Path": 10, - "Average Path": 5, - "Estimated LUTs": 10, - "Total Node": 22 + "Longest Path": 9, + "Average Path": 4, + "Estimated LUTs": 7, + "Total Node": 19 }, "syntax/preprocessor_define_with_comment/no_arch": { "test_name": "syntax/preprocessor_define_with_comment/no_arch", @@ -1754,12 +1742,12 @@ "Latch Drivers": 1, "Pi": 5, "Po": 4, - "logic element": 20, + "logic element": 17, "latch": 3, - "Longest Path": 9, - "Average Path": 5, - "Estimated LUTs": 20, - "Total Node": 24 + "Longest Path": 8, + "Average Path": 4, + "Estimated LUTs": 17, + "Total Node": 21 }, "syntax/rs_decoder_1/k6_frac_N10_frac_chain_mem32K_40nm": { "test_name": "syntax/rs_decoder_1/k6_frac_N10_frac_chain_mem32K_40nm", @@ -1884,14 +1872,14 @@ "Latch Drivers": 1, "Pi": 5, "Po": 4, - "logic element": 10, + "logic element": 7, "latch": 3, "Adder": 4, "generic logic size": 4, - "Longest Path": 9, - "Average Path": 5, - "Estimated LUTs": 10, - "Total Node": 18 + "Longest Path": 8, + "Average Path": 4, + "Estimated LUTs": 7, + "Total Node": 15 }, "syntax/simple_function/no_arch": { "test_name": "syntax/simple_function/no_arch", @@ -1903,12 +1891,12 @@ "Latch Drivers": 1, "Pi": 5, "Po": 4, - "logic element": 15, + "logic element": 12, "latch": 3, - "Longest Path": 8, - "Average Path": 5, - "Estimated LUTs": 15, - "Total Node": 19 + "Longest Path": 7, + "Average Path": 4, + "Estimated LUTs": 12, + "Total Node": 16 }, "syntax/simple_module/k6_frac_N10_frac_chain_mem32K_40nm": { "test_name": "syntax/simple_module/k6_frac_N10_frac_chain_mem32K_40nm", @@ -1921,14 +1909,14 @@ "Latch Drivers": 1, "Pi": 5, "Po": 4, - "logic element": 10, + "logic element": 7, "latch": 3, "Adder": 4, "generic logic size": 4, - "Longest Path": 9, - "Average Path": 5, - "Estimated LUTs": 10, - "Total Node": 18 + "Longest Path": 8, + "Average Path": 4, + "Estimated LUTs": 7, + "Total Node": 15 }, "syntax/simple_module/no_arch": { "test_name": "syntax/simple_module/no_arch", @@ -1940,12 +1928,12 @@ "Latch Drivers": 1, "Pi": 5, "Po": 4, - "logic element": 15, + "logic element": 12, "latch": 3, - "Longest Path": 8, - "Average Path": 5, - "Estimated LUTs": 15, - "Total Node": 19 + "Longest Path": 7, + "Average Path": 4, + "Estimated LUTs": 12, + "Total Node": 16 }, "syntax/simple_task/k6_frac_N10_frac_chain_mem32K_40nm": { "test_name": "syntax/simple_task/k6_frac_N10_frac_chain_mem32K_40nm", @@ -1958,14 +1946,14 @@ "Latch Drivers": 1, "Pi": 5, "Po": 4, - "logic element": 10, + "logic element": 7, "latch": 3, "Adder": 4, "generic logic size": 4, - "Longest Path": 9, - "Average Path": 5, - "Estimated LUTs": 10, - "Total Node": 18 + "Longest Path": 8, + "Average Path": 4, + "Estimated LUTs": 7, + "Total Node": 15 }, "syntax/simple_task/no_arch": { "test_name": "syntax/simple_task/no_arch", @@ -1977,12 +1965,12 @@ "Latch Drivers": 1, "Pi": 5, "Po": 4, - "logic element": 15, + "logic element": 12, "latch": 3, - "Longest Path": 8, - "Average Path": 5, - "Estimated LUTs": 15, - "Total Node": 19 + "Longest Path": 7, + "Average Path": 4, + "Estimated LUTs": 12, + "Total Node": 16 }, "syntax/spram_big/k6_frac_N10_frac_chain_mem32K_40nm": { "test_name": "syntax/spram_big/k6_frac_N10_frac_chain_mem32K_40nm", @@ -2033,14 +2021,14 @@ "Latch Drivers": 1, "Pi": 5, "Po": 4, - "logic element": 10, + "logic element": 7, "latch": 3, "Adder": 4, "generic logic size": 4, - "Longest Path": 9, - "Average Path": 5, - "Estimated LUTs": 10, - "Total Node": 18 + "Longest Path": 8, + "Average Path": 4, + "Estimated LUTs": 7, + "Total Node": 15 }, "syntax/task_automatic/no_arch": { "test_name": "syntax/task_automatic/no_arch", @@ -2052,12 +2040,12 @@ "Latch Drivers": 1, "Pi": 5, "Po": 4, - "logic element": 15, + "logic element": 12, "latch": 3, - "Longest Path": 8, - "Average Path": 5, - "Estimated LUTs": 15, - "Total Node": 19 + "Longest Path": 7, + "Average Path": 4, + "Estimated LUTs": 12, + "Total Node": 16 }, "syntax/task_multiple_instances/k6_frac_N10_frac_chain_mem32K_40nm": { "test_name": "syntax/task_multiple_instances/k6_frac_N10_frac_chain_mem32K_40nm", @@ -2070,14 +2058,14 @@ "Latch Drivers": 1, "Pi": 9, "Po": 7, - "logic element": 19, + "logic element": 13, "latch": 6, "Adder": 8, "generic logic size": 4, - "Longest Path": 9, - "Average Path": 5, - "Estimated LUTs": 19, - "Total Node": 34 + "Longest Path": 8, + "Average Path": 4, + "Estimated LUTs": 13, + "Total Node": 28 }, "syntax/task_multiple_instances/no_arch": { "test_name": "syntax/task_multiple_instances/no_arch", @@ -2089,12 +2077,12 @@ "Latch Drivers": 1, "Pi": 9, "Po": 7, - "logic element": 29, + "logic element": 23, "latch": 6, - "Longest Path": 8, - "Average Path": 5, - "Estimated LUTs": 29, - "Total Node": 36 + "Longest Path": 7, + "Average Path": 4, + "Estimated LUTs": 23, + "Total Node": 30 }, "syntax/timescale_syntax/k6_frac_N10_frac_chain_mem32K_40nm": { "test_name": "syntax/timescale_syntax/k6_frac_N10_frac_chain_mem32K_40nm", @@ -2188,12 +2176,12 @@ "test_coverage(%)": 100, "Pi": 4, "Po": 2, - "logic element": 4, + "logic element": 2, "generic logic size": 4, - "Longest Path": 4, - "Average Path": 4, - "Estimated LUTs": 4, - "Total Node": 4 + "Longest Path": 3, + "Average Path": 3, + "Estimated LUTs": 2, + "Total Node": 2 }, "syntax/vector_and/no_arch": { "test_name": "syntax/vector_and/no_arch", @@ -2204,11 +2192,11 @@ "test_coverage(%)": 100, "Pi": 4, "Po": 2, - "logic element": 4, - "Longest Path": 4, - "Average Path": 4, - "Estimated LUTs": 4, - "Total Node": 4 + "logic element": 2, + "Longest Path": 3, + "Average Path": 3, + "Estimated LUTs": 2, + "Total Node": 2 }, "syntax/vector_buf/k6_frac_N10_frac_chain_mem32K_40nm": { "test_name": "syntax/vector_buf/k6_frac_N10_frac_chain_mem32K_40nm", diff --git a/ODIN_II/regression_test/benchmark/task/syntax/synthesis_result.json b/ODIN_II/regression_test/benchmark/task/syntax/synthesis_result.json index 0fcc77a14a9..a06be1f973d 100644 --- a/ODIN_II/regression_test/benchmark/task/syntax/synthesis_result.json +++ b/ODIN_II/regression_test/benchmark/task/syntax/synthesis_result.json @@ -1702,9 +1702,9 @@ "matrix_multiplication.v:132:1 [NETLIST] Assignment (matrix_multiplication^tmp7~0) is missing driver", "matrix_multiplication.v:69:8 [NETLIST] This output is undriven (matrix_multiplication^data_out~16) and will be removed", "matrix_multiplication.v:69:8 [NETLIST] This output is undriven (matrix_multiplication^data_out~17) and will be removed", - "matrix_multiplication.v:166:16 [NETLIST] Net (null) driving node matrix_multiplication^nMUX~49^MUX_2~380 is itself undriven.", "matrix_multiplication.v:69:8 [NETLIST] Net matrix_multiplication^data_out~16 driving node matrix_multiplication^data_out~16 is itself undriven.", - "matrix_multiplication.v:69:8 [NETLIST] Net matrix_multiplication^data_out~17 driving node matrix_multiplication^data_out~17 is itself undriven." + "matrix_multiplication.v:69:8 [NETLIST] Net matrix_multiplication^data_out~17 driving node matrix_multiplication^data_out~17 is itself undriven.", + "matrix_multiplication.v:166:16 [NETLIST] Net (null) driving node matrix_multiplication^nMUX~49^MUX_2~380 is itself undriven." ], "Latch Drivers": 1, "Pi": 2, @@ -1735,9 +1735,9 @@ "matrix_multiplication.v:132:1 [NETLIST] Assignment (matrix_multiplication^tmp7~0) is missing driver", "matrix_multiplication.v:69:8 [NETLIST] This output is undriven (matrix_multiplication^data_out~16) and will be removed", "matrix_multiplication.v:69:8 [NETLIST] This output is undriven (matrix_multiplication^data_out~17) and will be removed", - "matrix_multiplication.v:166:16 [NETLIST] Net (null) driving node matrix_multiplication^nMUX~49^MUX_2~8012 is itself undriven.", "matrix_multiplication.v:69:8 [NETLIST] Net matrix_multiplication^data_out~16 driving node matrix_multiplication^data_out~16 is itself undriven.", - "matrix_multiplication.v:69:8 [NETLIST] Net matrix_multiplication^data_out~17 driving node matrix_multiplication^data_out~17 is itself undriven." + "matrix_multiplication.v:69:8 [NETLIST] Net matrix_multiplication^data_out~17 driving node matrix_multiplication^data_out~17 is itself undriven.", + "matrix_multiplication.v:166:16 [NETLIST] Net (null) driving node matrix_multiplication^nMUX~49^MUX_2~8012 is itself undriven." ], "Latch Drivers": 1, "Pi": 2, diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_basic/basic_no_timing/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_basic/basic_no_timing/config/golden_results.txt index 41ca614758d..354a6509642 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_basic/basic_no_timing/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_basic/basic_no_timing/config/golden_results.txt @@ -1,5 +1,5 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time -k4_N10_memSize16384_memData64.xml ch_intrinsics.v common 3.08 0.14 116128 4 0.19 -1 -1 33812 -1 -1 72 99 1 0 success v8.0.0-2123-g41cf93464-dirty release VTR_ASSERT_LEVEL=3 gprof GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-27T05:01:03 betzgrp-wintermute.eecg.utoronto.ca /home/hubingra/master/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_basic/basic_no_timing/run027/k4_N10_memSize16384_memData64.xml/ch_intrinsics.v/common 76844 99 130 378 508 1 260 302 13 13 169 clb auto 0.06 638 0.59 0.00 34 1605 10 3.33e+06 2.28e+06 450788. 2667.39 0.68 -k4_N10_memSize16384_memData64.xml diffeq1.v common 8.00 0.10 102712 23 0.23 -1 -1 34256 -1 -1 72 162 0 5 success v8.0.0-2123-g41cf93464-dirty release VTR_ASSERT_LEVEL=3 gprof GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-27T05:01:03 betzgrp-wintermute.eecg.utoronto.ca /home/hubingra/master/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_basic/basic_no_timing/run027/k4_N10_memSize16384_memData64.xml/diffeq1.v/common 80952 162 96 1214 1147 1 676 335 13 13 169 clb auto 0.21 4324 1.76 0.01 50 10008 26 3.33e+06 2.61e+06 641417. 3795.37 3.79 -k4_N10_memSize16384_memData64.xml single_wire.v common 0.54 0.06 82948 1 0.00 -1 -1 29628 -1 -1 0 1 0 0 success v8.0.0-2123-g41cf93464-dirty release VTR_ASSERT_LEVEL=3 gprof GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-27T05:01:03 betzgrp-wintermute.eecg.utoronto.ca /home/hubingra/master/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_basic/basic_no_timing/run027/k4_N10_memSize16384_memData64.xml/single_wire.v/common 67096 1 1 1 2 0 1 2 3 3 9 -1 auto 0.00 2 0.00 0.00 6 4 1 30000 0 1761.23 195.692 0.01 -k4_N10_memSize16384_memData64.xml single_ff.v common 0.57 0.06 83024 1 0.00 -1 -1 29516 -1 -1 1 2 0 0 success v8.0.0-2123-g41cf93464-dirty release VTR_ASSERT_LEVEL=3 gprof GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-27T05:01:03 betzgrp-wintermute.eecg.utoronto.ca /home/hubingra/master/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_basic/basic_no_timing/run027/k4_N10_memSize16384_memData64.xml/single_ff.v/common 67756 2 1 3 4 1 3 4 3 3 9 -1 auto 0.00 4 0.00 0.00 18 4 1 30000 30000 3112.78 345.864 0.01 +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time +k4_N10_memSize16384_memData64.xml ch_intrinsics.v common 11.75 0.03 8932 4 0.21 -1 -1 40008 -1 -1 72 99 1 0 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_basic/basic_no_timing/run014/k4_N10_memSize16384_memData64.xml/ch_intrinsics.v/common 26652 99 130 378 508 1 260 302 13 13 169 clb auto 0.05 638 0.28 0.00 38 1530 9 3.33e+06 2.28e+06 504671. 2986.22 0.35 +k4_N10_memSize16384_memData64.xml diffeq1.v common 14.27 0.02 8644 23 0.28 -1 -1 38212 -1 -1 72 162 0 5 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_basic/basic_no_timing/run014/k4_N10_memSize16384_memData64.xml/diffeq1.v/common 31148 162 96 1214 1147 1 676 335 13 13 169 clb auto 0.16 4324 0.62 0.00 50 10008 26 3.33e+06 2.61e+06 641417. 3795.37 2.02 +k4_N10_memSize16384_memData64.xml single_wire.v common 10.67 0.01 5380 1 0.01 -1 -1 33052 -1 -1 0 1 0 0 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_basic/basic_no_timing/run014/k4_N10_memSize16384_memData64.xml/single_wire.v/common 21184 1 1 1 2 0 1 2 3 3 9 -1 auto 0.00 2 0.00 0.00 2 1 1 30000 0 1489.46 165.495 0.00 +k4_N10_memSize16384_memData64.xml single_ff.v common 10.66 0.01 5344 1 0.00 -1 -1 33384 -1 -1 1 2 0 0 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_basic/basic_no_timing/run014/k4_N10_memSize16384_memData64.xml/single_ff.v/common 21308 2 1 3 4 1 3 4 3 3 9 -1 auto 0.00 4 0.00 0.00 16 9 1 30000 30000 2550.78 283.420 0.00 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_basic/basic_timing/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_basic/basic_timing/config/golden_results.txt index b762f10f37f..51f744d3bc5 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_basic/basic_timing/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_basic/basic_timing/config/golden_results.txt @@ -1,9 +1,9 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6_N10_mem32K_40nm.xml ch_intrinsics.v common 1.83 0.02 7444 3 0.19 -1 -1 34440 -1 -1 70 99 1 0 success v8.0.0-2354-gf49343db5-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.2.0 on Linux-5.4.43 x86_64 1969-12-31T16:00:01 hank /home/dusty/src/symbiflow/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_basic/basic_timing/run029/k6_N10_mem32K_40nm.xml/ch_intrinsics.v/common 66680 99 130 363 493 1 255 300 12 12 144 clb auto 0.05 655 0.43 0.00 2.18412 -208.426 -2.18412 2.18412 0.000427165 0.000363408 0.0535736 0.0463846 38 1213 28 5.66058e+06 4.32058e+06 306247. 2126.71 0.39 0.14468 0.127742 1113 18 739 1031 114104 39086 2.6714 2.6714 -228.621 -2.6714 0 0 388532. 2698.14 0.03 0.0166286 0.0150891 -k6_N10_mem32K_40nm.xml ch_intrinsics.v common_--reorder_rr_graph_nodes_algorithm_random_shuffle 2.22 0.02 7460 3 0.19 -1 -1 34380 -1 -1 70 99 1 0 success v8.0.0-2354-gf49343db5-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.2.0 on Linux-5.4.43 x86_64 1969-12-31T16:00:01 hank /home/dusty/src/symbiflow/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_basic/basic_timing/run029/k6_N10_mem32K_40nm.xml/ch_intrinsics.v/common_--reorder_rr_graph_nodes_algorithm_random_shuffle 65692 99 130 363 493 1 255 300 12 12 144 clb auto 0.05 655 0.43 0.00 2.18412 -208.426 -2.18412 2.18412 0.000374397 0.0003229 0.0502852 0.0430231 38 1213 28 5.66058e+06 4.32058e+06 306247. 2126.71 0.78 0.202994 0.178545 1113 18 739 1031 114104 39086 2.6714 2.6714 -228.621 -2.6714 0 0 388531. 2698.14 0.03 0.0165891 0.015059 -k6_N10_mem32K_40nm.xml diffeq1.v common 4.73 0.02 7276 15 0.30 -1 -1 32972 -1 -1 52 162 0 5 success v8.0.0-2354-gf49343db5-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.2.0 on Linux-5.4.43 x86_64 1969-12-31T16:00:01 hank /home/dusty/src/symbiflow/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_basic/basic_timing/run029/k6_N10_mem32K_40nm.xml/diffeq1.v/common 73840 162 96 999 932 1 707 315 16 16 256 mult_36 auto 0.16 5392 0.88 0.00 19.8556 -1716.78 -19.8556 19.8556 0.00110493 0.000971807 0.148517 0.128122 44 11950 42 1.21132e+07 4.78249e+06 665287. 2598.78 1.97 0.467331 0.412122 9499 24 4032 8541 2355345 561334 21.9068 21.9068 -1883.87 -21.9068 0 0 864808. 3378.16 0.28 0.0714563 0.0652019 -k6_N10_mem32K_40nm.xml diffeq1.v common_--reorder_rr_graph_nodes_algorithm_random_shuffle 6.35 0.02 7232 15 0.29 -1 -1 33008 -1 -1 52 162 0 5 success v8.0.0-2354-gf49343db5-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.2.0 on Linux-5.4.43 x86_64 1969-12-31T16:00:01 hank /home/dusty/src/symbiflow/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_basic/basic_timing/run029/k6_N10_mem32K_40nm.xml/diffeq1.v/common_--reorder_rr_graph_nodes_algorithm_random_shuffle 73852 162 96 999 932 1 707 315 16 16 256 mult_36 auto 0.16 5392 0.89 0.00 19.8556 -1716.78 -19.8556 19.8556 0.00114118 0.001008 0.149456 0.129224 44 11950 42 1.21132e+07 4.78249e+06 665287. 2598.78 3.54 0.606688 0.536175 9499 24 4032 8541 2355345 561334 21.9068 21.9068 -1883.87 -21.9068 0 0 864809. 3378.16 0.29 0.0715942 0.0654077 -k6_N10_mem32K_40nm.xml single_wire.v common 0.31 0.01 4160 1 0.00 -1 -1 28288 -1 -1 0 1 0 0 success v8.0.0-2354-gf49343db5-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.2.0 on Linux-5.4.43 x86_64 1969-12-31T16:00:01 hank /home/dusty/src/symbiflow/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_basic/basic_timing/run029/k6_N10_mem32K_40nm.xml/single_wire.v/common 57788 1 1 1 2 0 1 2 3 3 9 -1 auto 0.00 2 0.00 0.00 0.205011 -0.205011 -0.205011 nan 2.7111e-05 2.2017e-05 6.5433e-05 4.4914e-05 14 5 1 53894 0 3251.56 361.284 0.00 0.000147999 9.2142e-05 5 1 1 1 23 21 0.515002 nan -0.515002 -0.515002 0 0 4350.07 483.341 0.00 5.5223e-05 3.292e-05 -k6_N10_mem32K_40nm.xml single_wire.v common_--reorder_rr_graph_nodes_algorithm_random_shuffle 0.31 0.01 4164 1 0.00 -1 -1 28320 -1 -1 0 1 0 0 success v8.0.0-2354-gf49343db5-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.2.0 on Linux-5.4.43 x86_64 1969-12-31T16:00:01 hank /home/dusty/src/symbiflow/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_basic/basic_timing/run029/k6_N10_mem32K_40nm.xml/single_wire.v/common_--reorder_rr_graph_nodes_algorithm_random_shuffle 57952 1 1 1 2 0 1 2 3 3 9 -1 auto 0.00 2 0.00 0.00 0.205011 -0.205011 -0.205011 nan 1.1584e-05 5.193e-06 5.228e-05 2.9222e-05 14 5 1 53894 0 3251.56 361.284 0.01 0.000198123 0.000110877 5 1 1 1 23 21 0.515002 nan -0.515002 -0.515002 0 0 4350.07 483.341 0.00 5.7877e-05 3.4616e-05 -k6_N10_mem32K_40nm.xml single_ff.v common 0.31 0.01 4088 1 0.00 -1 -1 28348 -1 -1 1 2 0 0 success v8.0.0-2354-gf49343db5-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.2.0 on Linux-5.4.43 x86_64 1969-12-31T16:00:01 hank /home/dusty/src/symbiflow/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_basic/basic_timing/run029/k6_N10_mem32K_40nm.xml/single_ff.v/common 57812 2 1 3 4 1 3 4 3 3 9 -1 auto 0.00 4 0.00 0.00 0.570641 -0.944653 -0.570641 0.570641 2.8245e-05 2.4065e-05 9.7529e-05 6.1764e-05 2 2 2 53894 53894 1165.58 129.509 0.00 0.000248445 0.000151363 2 2 3 3 70 44 0.576831 0.576831 -0.957916 -0.576831 0 0 1165.58 129.509 0.00 0.000113926 7.8571e-05 -k6_N10_mem32K_40nm.xml single_ff.v common_--reorder_rr_graph_nodes_algorithm_random_shuffle 0.32 0.01 4128 1 0.00 -1 -1 28336 -1 -1 1 2 0 0 success v8.0.0-2354-gf49343db5-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.2.0 on Linux-5.4.43 x86_64 1969-12-31T16:00:01 hank /home/dusty/src/symbiflow/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_basic/basic_timing/run029/k6_N10_mem32K_40nm.xml/single_ff.v/common_--reorder_rr_graph_nodes_algorithm_random_shuffle 58260 2 1 3 4 1 3 4 3 3 9 -1 auto 0.00 4 0.00 0.00 0.570641 -0.944653 -0.570641 0.570641 1.3689e-05 8.253e-06 7.0161e-05 4.5517e-05 2 2 2 53894 53894 1165.58 129.509 0.01 0.000523227 0.000318569 2 2 3 3 70 44 0.576831 0.576831 -0.957916 -0.576831 0 0 1165.58 129.509 0.00 0.000104793 6.9493e-05 +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_mem32K_40nm.xml ch_intrinsics.v common 12.36 0.03 8924 3 0.20 -1 -1 37620 -1 -1 70 99 1 0 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_basic/basic_timing/run014/k6_N10_mem32K_40nm.xml/ch_intrinsics.v/common 27492 99 130 363 493 1 255 300 12 12 144 clb auto 0.06 655 0.58 0.00 2.18412 -208.426 -2.18412 2.18412 0.000376964 0.000327403 0.0511594 0.0446628 38 1213 28 5.66058e+06 4.32058e+06 306247. 2126.71 0.49 0.153124 0.137605 1113 18 739 1031 114104 39086 2.6714 2.6714 -228.621 -2.6714 0 0 388532. 2698.14 0.04 0.0192211 0.0178366 +k6_N10_mem32K_40nm.xml ch_intrinsics.v common_--reorder_rr_graph_nodes_algorithm_random_shuffle 12.42 0.03 9032 3 0.22 -1 -1 37716 -1 -1 70 99 1 0 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_basic/basic_timing/run014/k6_N10_mem32K_40nm.xml/ch_intrinsics.v/common_--reorder_rr_graph_nodes_algorithm_random_shuffle 27484 99 130 363 493 1 255 300 12 12 144 clb auto 0.06 655 0.59 0.00 2.18412 -208.426 -2.18412 2.18412 0.000377588 0.000328425 0.0513139 0.0448317 38 1213 28 5.66058e+06 4.32058e+06 306247. 2126.71 0.52 0.154502 0.139036 1113 18 739 1031 114104 39086 2.6714 2.6714 -228.621 -2.6714 0 0 388531. 2698.14 0.04 0.0201455 0.0186962 +k6_N10_mem32K_40nm.xml diffeq1.v common 8.16 0.02 8736 15 0.32 -1 -1 38500 -1 -1 52 162 0 5 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_basic/basic_timing/run014/k6_N10_mem32K_40nm.xml/diffeq1.v/common 36836 162 96 999 932 1 707 315 16 16 256 mult_36 auto 0.18 5392 1.42 0.01 19.8556 -1716.78 -19.8556 19.8556 0.00144721 0.00129594 0.189577 0.169104 44 11950 42 1.21132e+07 4.78249e+06 665287. 2598.78 2.67 0.616492 0.559872 9499 24 4032 8541 2355345 561334 21.9068 21.9068 -1883.87 -21.9068 0 0 864808. 3378.16 0.37 0.092734 0.0864435 +k6_N10_mem32K_40nm.xml diffeq1.v common_--reorder_rr_graph_nodes_algorithm_random_shuffle 8.38 0.02 8812 15 0.34 -1 -1 38708 -1 -1 52 162 0 5 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_basic/basic_timing/run014/k6_N10_mem32K_40nm.xml/diffeq1.v/common_--reorder_rr_graph_nodes_algorithm_random_shuffle 36556 162 96 999 932 1 707 315 16 16 256 mult_36 auto 0.18 5392 1.46 0.01 19.8556 -1716.78 -19.8556 19.8556 0.00145743 0.00130116 0.189871 0.169168 44 11950 42 1.21132e+07 4.78249e+06 665287. 2598.78 2.83 0.618692 0.56202 9499 24 4032 8541 2355345 561334 21.9068 21.9068 -1883.87 -21.9068 0 0 864809. 3378.16 0.40 0.0919174 0.0856796 +k6_N10_mem32K_40nm.xml single_wire.v common 2.12 0.01 5572 1 0.01 -1 -1 33244 -1 -1 0 1 0 0 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_basic/basic_timing/run014/k6_N10_mem32K_40nm.xml/single_wire.v/common 22136 1 1 1 2 0 1 2 3 3 9 -1 auto 0.00 2 0.00 0.00 0.205011 -0.205011 -0.205011 nan 6.485e-06 2.816e-06 3.3493e-05 1.8151e-05 14 5 1 53894 0 3251.56 361.284 0.00 9.7468e-05 5.7524e-05 5 1 1 1 23 21 0.515002 nan -0.515002 -0.515002 0 0 4350.07 483.341 0.00 4.093e-05 2.5868e-05 +k6_N10_mem32K_40nm.xml single_wire.v common_--reorder_rr_graph_nodes_algorithm_random_shuffle 2.10 0.01 5584 1 0.01 -1 -1 33148 -1 -1 0 1 0 0 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_basic/basic_timing/run014/k6_N10_mem32K_40nm.xml/single_wire.v/common_--reorder_rr_graph_nodes_algorithm_random_shuffle 22128 1 1 1 2 0 1 2 3 3 9 -1 auto 0.00 2 0.00 0.00 0.205011 -0.205011 -0.205011 nan 6.645e-06 2.926e-06 3.0696e-05 1.6398e-05 14 5 1 53894 0 3251.56 361.284 0.00 8.8271e-05 5.0964e-05 5 1 1 1 23 21 0.515002 nan -0.515002 -0.515002 0 0 4350.07 483.341 0.00 3.8013e-05 2.3763e-05 +k6_N10_mem32K_40nm.xml single_ff.v common 2.07 0.01 5504 1 0.01 -1 -1 33232 -1 -1 1 2 0 0 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_basic/basic_timing/run014/k6_N10_mem32K_40nm.xml/single_ff.v/common 22104 2 1 3 4 1 3 4 3 3 9 -1 auto 0.00 4 0.00 0.00 0.570641 -0.944653 -0.570641 0.570641 6.53e-06 3.637e-06 4.0986e-05 2.5532e-05 2 2 2 53894 53894 1165.58 129.509 0.00 0.00012441 8.3048e-05 2 2 3 3 70 44 0.576831 0.576831 -0.957916 -0.576831 0 0 1165.58 129.509 0.00 7.2524e-05 5.2262e-05 +k6_N10_mem32K_40nm.xml single_ff.v common_--reorder_rr_graph_nodes_algorithm_random_shuffle 2.06 0.01 5568 1 0.01 -1 -1 33420 -1 -1 1 2 0 0 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_basic/basic_timing/run014/k6_N10_mem32K_40nm.xml/single_ff.v/common_--reorder_rr_graph_nodes_algorithm_random_shuffle 22288 2 1 3 4 1 3 4 3 3 9 -1 auto 0.00 4 0.00 0.00 0.570641 -0.944653 -0.570641 0.570641 2.0207e-05 2.869e-06 7.9215e-05 2.6633e-05 2 2 2 53894 53894 1165.58 129.509 0.00 0.000163351 8.5527e-05 2 2 3 3 70 44 0.576831 0.576831 -0.957916 -0.576831 0 0 1165.58 129.509 0.00 6.9453e-05 4.9332e-05 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_basic/basic_timing_no_sdc/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_basic/basic_timing_no_sdc/config/golden_results.txt index ce996e281b0..e592c6446e2 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_basic/basic_timing_no_sdc/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_basic/basic_timing_no_sdc/config/golden_results.txt @@ -1,2 +1,2 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time -k6_N10_mem32K_40nm.xml mkPktMerge.v common 15.87 0.09 16088 2 0.08 -1 -1 33472 -1 -1 32 311 15 0 v8.0.0-1603-g6c2a712a0 success betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr3/vtr_flow/tasks/regression_tests/vtr_reg_basic/basic_timing_no_sdc/run005/k6_N10_mem32K_40nm.xml/mkPktMerge.v/common 69012 311 156 972 1128 1 953 514 28 28 784 memory auto 0.32 7654 2.39 3.70719 -4074.07 -3.70719 40 13686 25 4.25198e+07 9.94461e+06 2.03169e+06 2591.44 9.47 12833 16 3145 3741 4670273 1395801 4.01588 4.01588 -4944.07 -4.01588 -12.0212 -0.299894 2.55406e+06 3257.73 0.62 +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_mem32K_40nm.xml mkPktMerge.v common 13.24 0.09 16364 2 0.08 -1 -1 37328 -1 -1 32 311 15 0 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_basic/basic_timing_no_sdc/run014/k6_N10_mem32K_40nm.xml/mkPktMerge.v/common 55908 311 156 972 1128 1 953 514 28 28 784 memory auto 0.34 7654 2.84 0.01 3.70719 -4074.07 -3.70719 3.70719 0.00228702 0.00190099 0.331075 0.274934 40 13686 25 4.25198e+07 9.94461e+06 2.03169e+06 2591.44 4.42 0.926894 0.804038 12833 16 3145 3741 4670273 1395801 4.01588 4.01588 -4944.07 -4.01588 -12.0212 -0.299894 2.55406e+06 3257.73 0.69 0.108231 0.0985157 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly/complex_switch/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly/complex_switch/config/golden_results.txt index 5509098a40c..80dabef4e5b 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly/complex_switch/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly/complex_switch/config/golden_results.txt @@ -1,15 +1,15 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_route_time -k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml bgm.v common 788.42 24.61 390728 33 448.38 -1 -1 151176 -1 -1 5544 257 0 11 v8.0.0-1603-g6c2a712a0 success betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr3/vtr_flow/tasks/regression_tests/vtr_reg_nightly/complex_switch/run003/k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml/bgm.v/common 802716 257 32 44425 43940 1 42719 5844 81 81 6561 clb auto 9.08 395786 184.81 13.0914 -18105.2 -13.0914 625515 223329 769392 123367166 25825057 3.71927e+07 2.29284e+07 7.46633e+07 11379.9 21 14.5012 14.5012 -20812.6 -14.5012 0 0 28.71 -k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml blob_merge.v common 114.40 0.39 55676 29 69.72 -1 -1 58652 -1 -1 1320 36 0 0 v8.0.0-1603-g6c2a712a0 success betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr3/vtr_flow/tasks/regression_tests/vtr_reg_nightly/complex_switch/run003/k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml/blob_merge.v/common 226548 36 100 10431 10531 1 9865 1456 41 41 1681 clb auto 1.38 87002 17.44 8.47251 -2140.67 -8.47251 133097 31457 114567 16548713 3316868 8.95136e+06 5.148e+06 1.84779e+07 10992.2 19 9.62033 9.62033 -2566.3 -9.62033 0 0 4.42 -k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml boundtop.v common 3.42 0.60 44352 3 0.35 -1 -1 37852 -1 -1 95 114 0 0 v8.0.0-1603-g6c2a712a0 success betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr3/vtr_flow/tasks/regression_tests/vtr_reg_nightly/complex_switch/run003/k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml/boundtop.v/common 36052 114 192 467 659 1 374 401 13 13 169 clb auto 0.05 897 0.45 0.992068 -138.658 -0.992068 1402 639 1641 182883 51928 666600 370500 1.59550e+06 9440.85 8 1.32554 1.32554 -165.62 -1.32554 0 0 0.04 -k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml LU8PEEng.v common 564.92 15.15 227776 206 230.92 -1 -1 99036 -1 -1 4462 114 83 8 v8.0.0-1603-g6c2a712a0 success betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr3/vtr_flow/tasks/regression_tests/vtr_reg_nightly/complex_switch/run003/k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml/LU8PEEng.v/common 828808 114 102 39002 38728 1 36304 4769 86 86 7396 memory auto 8.24 353696 161.85 65.0798 -40943.9 -65.0798 504667 122060 420830 142157515 52147695 4.18276e+07 2.52203e+07 8.44414e+07 11417.2 22 72.2886 72.2886 -68688.3 -72.2886 -122.681 -0.36083 44.31 -k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml LU32PEEng.v common 3056.50 162.60 795572 205 1293.87 -1 -1 349016 -1 -1 15728 114 299 32 v8.0.0-1603-g6c2a712a0 success betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr3/vtr_flow/tasks/regression_tests/vtr_reg_nightly/complex_switch/run003/k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml/LU32PEEng.v/common 2840152 114 102 136869 135467 1 128734 16275 169 169 28561 memory auto 33.30 1597267 1004.23 63.4675 -228562 -63.4675 2131079 391254 1376325 500048428 178681891 1.64515e+08 8.99058e+07 3.31299e+08 11599.7 22 71.949 71.949 -468512 -71.949 -122.967 -0.303936 145.99 -k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml mcml.v common 8677.71 27.27 900676 124 7532.52 -1 -1 450260 -1 -1 12829 36 318 27 v8.0.0-1603-g6c2a712a0 success betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr3/vtr_flow/tasks/regression_tests/vtr_reg_nightly/complex_switch/run003/k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml/mcml.v/common 2709936 36 33 149067 147525 1 102631 13243 169 169 28561 memory auto 27.83 7231692 621.28 55.0557 -219978 -55.0557 1301051 389609 1559007 296166383 77252107 1.64515e+08 7.95673e+07 3.31299e+08 11599.7 21 59.3356 59.3356 -382055 -59.3356 -1.60521 -0.151201 81.87 -k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml mkDelayWorker32B.v common 99.79 0.81 77064 6 6.29 -1 -1 52584 -1 -1 574 506 80 0 v8.0.0-1603-g6c2a712a0 success betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr3/vtr_flow/tasks/regression_tests/vtr_reg_nightly/complex_switch/run003/k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml/mkDelayWorker32B.v/common 411084 506 553 3459 4012 1 3453 1713 82 82 6724 memory auto 1.17 18680 5.90 6.25369 -1200.18 -6.25369 20282 3082 3452 9708304 3817079 3.85878e+07 8.85844e+06 7.66484e+07 11399.2 12 6.56906 6.56906 -1632.51 -6.56906 -5.18119 -0.36083 2.69 -k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml mkSMAdapter4B.v common 21.01 0.24 30700 11 2.49 -1 -1 37708 -1 -1 290 193 10 0 v8.0.0-1603-g6c2a712a0 success betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr3/vtr_flow/tasks/regression_tests/vtr_reg_nightly/complex_switch/run003/k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml/mkSMAdapter4B.v/common 115336 193 205 2764 2969 1 2139 698 37 37 1369 memory auto 0.38 15840 2.79 3.96195 -2306.85 -3.96195 23987 7590 24522 4723774 1304361 7.45627e+06 1.95848e+06 1.49196e+07 10898.2 17 4.30614 4.30614 -2638.65 -4.30614 -19.0711 -0.362934 1.04 -k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml or1200.v common 24.36 0.39 41276 45 4.40 -1 -1 42868 -1 -1 531 385 4 1 v8.0.0-1603-g6c2a712a0 success betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr3/vtr_flow/tasks/regression_tests/vtr_reg_nightly/complex_switch/run003/k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml/or1200.v/common 118024 385 394 5227 5558 1 4558 1315 27 27 729 io clb auto 0.78 43591 8.34 12.604 -9016.1 -12.604 62713 15250 56834 9094092 2217442 4.06709e+06 2.52069e+06 7.75339e+06 10635.7 18 13.5337 13.5337 -10571.8 -13.5337 0 0 2.18 -k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml raygentop.v common 12.21 0.28 31412 12 1.38 -1 -1 40772 -1 -1 237 214 0 9 v8.0.0-1603-g6c2a712a0 success betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr3/vtr_flow/tasks/regression_tests/vtr_reg_nightly/complex_switch/run003/k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml/raygentop.v/common 80804 214 305 2938 3054 1 2192 765 26 26 676 mult_36 auto 0.40 15830 2.37 3.79643 -1875.96 -3.79643 23924 7211 23901 8898703 2538084 3.88769e+06 1.9935e+06 7.17610e+06 10615.5 15 4.06389 4.06389 -2239.91 -4.06389 0 0 1.53 -k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml sha.v common 475.41 0.72 36288 31 460.57 -1 -1 94324 -1 -1 415 38 0 0 v8.0.0-1603-g6c2a712a0 success betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr3/vtr_flow/tasks/regression_tests/vtr_reg_nightly/complex_switch/run003/k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml/sha.v/common 91664 38 36 4183 4219 1 3300 489 24 24 576 clb auto 0.54 24119 3.39 9.76184 -3261.27 -9.76184 41263 12799 52053 6505810 1515418 2.72374e+06 1.6185e+06 6.03346e+06 10474.8 20 11.484 11.484 -3914.71 -11.484 0 0 1.41 -k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml stereovision0.v common 164.72 1.34 117908 7 98.42 -1 -1 73932 -1 -1 1792 157 0 0 v8.0.0-1603-g6c2a712a0 success betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr3/vtr_flow/tasks/regression_tests/vtr_reg_nightly/complex_switch/run003/k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml/stereovision0.v/common 319872 157 197 22236 22433 1 13745 2146 47 47 2209 clb auto 2.17 79577 30.15 2.32783 -8845.53 -2.32783 117877 40246 120359 14885223 3515430 1.16296e+07 6.9888e+06 2.45588e+07 11117.6 17 2.58709 2.58709 -11278 -2.58709 0 0 4.27 -k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml stereovision1.v common 146.38 1.82 99972 10 57.30 -1 -1 78948 -1 -1 1724 113 0 44 v8.0.0-1603-g6c2a712a0 success betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr3/vtr_flow/tasks/regression_tests/vtr_reg_nightly/complex_switch/run003/k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml/stereovision1.v/common 419584 113 145 23291 21156 1 16143 2026 62 62 3844 mult_36 auto 2.56 128667 26.94 4.07751 -17058.2 -4.07751 178264 52898 144813 49829119 13522418 2.17057e+07 1.19508e+07 4.33614e+07 11280.3 19 4.59872 4.59872 -20597.4 -4.59872 0 0 9.80 -k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml stereovision2.v common 1051.79 2.18 161984 26 362.22 -1 -1 189052 -1 -1 5847 149 0 324 v8.0.0-1603-g6c2a712a0 success betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr3/vtr_flow/tasks/regression_tests/vtr_reg_nightly/complex_switch/run003/k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml/stereovision2.v/common 2067048 149 182 65520 55100 1 55662 6502 166 166 27556 mult_36 auto 11.19 722632 235.92 13.8773 -51753.7 -13.8773 887366 228455 600564 162733153 45498914 1.58074e+08 6.12945e+07 3.19849e+08 11607.2 19 15.2039 15.2039 -66588.5 -15.2039 0 0 43.91 +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS 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0.791756 0.695437 +k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml sha.v common 905.10 0.76 36692 31 877.48 -1 -1 99928 -1 -1 415 38 0 0 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_nightly/complex_switch/run003/k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml/sha.v/common 80368 38 36 4183 4219 1 3300 489 24 24 576 clb auto 0.69 25277 9.55 0.07 9.76184 -3261.27 -9.76184 9.76184 0.00696895 0.00553381 0.777251 0.617915 41263 12799 52053 6505810 1515418 2.72374e+06 1.6185e+06 6.03346e+06 10474.8 20 11.484 11.484 -3914.71 -11.484 0 0 2.27 1.14923 0.944263 +k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml stereovision0.v common 287.95 1.52 118116 7 154.64 -1 -1 79824 -1 -1 1804 157 0 0 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_nightly/complex_switch/run003/k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml/stereovision0.v/common 276948 157 197 22240 22437 1 13748 2158 47 47 2209 clb auto 3.09 84492 86.01 0.64 2.32222 -9049.57 -2.32222 2.32222 0.0342273 0.0285629 3.78823 3.07113 116250 39503 116668 14395060 3418838 1.16296e+07 7.0356e+06 2.45588e+07 11117.6 15 2.58333 2.58333 -11590 -2.58333 0 0 6.24 5.10644 4.21648 +k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml stereovision1.v common 254.45 1.86 103480 10 86.26 -1 -1 82272 -1 -1 1728 113 0 44 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_nightly/complex_switch/run003/k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml/stereovision1.v/common 358716 113 145 23282 21147 1 16134 2030 62 62 3844 mult_36 auto 3.44 135967 85.43 0.66 4.11199 -16819.2 -4.11199 4.11199 0.0303499 0.0255553 4.20557 3.45463 179160 51317 146560 53572873 14297270 2.17057e+07 1.19664e+07 4.33614e+07 11280.3 13 4.39031 4.39031 -21197.9 -4.39031 0 0 15.89 5.50184 4.58784 +k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml stereovision2.v common 1313.45 2.23 158868 26 392.76 -1 -1 191152 -1 -1 5847 149 0 324 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_nightly/complex_switch/run003/k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml/stereovision2.v/common 1761392 149 182 65520 55100 1 55662 6502 166 166 27556 mult_36 auto 14.16 758277 446.48 3.65 13.8606 -51737.6 -13.8606 13.8606 0.115386 0.0944863 15.0389 12.8115 889806 236402 621440 166828090 46581412 1.58074e+08 6.12945e+07 3.19849e+08 11607.2 21 15.1278 15.1278 -63570.9 -15.1278 0 0 45.26 20.9689 18.1069 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly/titan_other/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly/titan_other/config/golden_results.txt index ade96bed0ce..a88b7ec7f70 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly/titan_other/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly/titan_other/config/golden_results.txt @@ -1,24 +1,24 @@ -arch circuit script_params vtr_flow_elapsed_time error num_io num_LAB num_DSP num_M9K num_M144K num_PLL vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks 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2020-06-02T09:59:48 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_nightly/titan_other/run006/stratixiv_arch.timing.xml/MMM_stratixiv_arch_timing.blif/common 1775924 202 276 35125 30509 3 21597 2026 106 79 8374 M9K auto 54.72 271809 88.55 0.36 9.34216 -43943.7 -8.34216 0.0823835 0.0577709 12.1217 8.2959 407668 54498 148298 191018714 33489506 0 0 1.63945e+08 19577.8 14 9.69222 3.54343 -58569.4 -8.69222 0 0 25.75 16.2191 11.7019 -stratixiv_arch.timing.xml radar20_stratixiv_arch_timing.blif common 182.90 5 335 31 105 0 2 success v8.0.0-1870-gb04b8b68d release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T09:59:48 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_nightly/titan_other/run006/stratixiv_arch.timing.xml/radar20_stratixiv_arch_timing.blif/common 1422288 3 2 14862 10304 26 7545 478 89 66 5874 DSP auto 28.55 113036 36.32 0.07 5.98651 -36166.6 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/mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_nightly/titan_other/run003/stratixiv_arch.timing.xml/CH_DFSIN_stratixiv_arch_timing.blif/common 1296636 3 33 48977 39238 1 25960 1639 54 40 2160 LAB auto 73.67 313697 314.35 1.88 78.1141 -91342.2 -77.1141 78.1141 0.101581 0.0796362 14.8058 11.8606 404280 81150 213721 212899211 30619107 0 0 4.19467e+07 19419.8 21 71.8793 71.8793 -127775 -70.8793 0 0 30.23 20.6486 16.927 +stratixiv_arch.timing.xml CHERI_stratixiv_arch_timing.blif common 786.50 211 2256 3 210 0 0 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_nightly/titan_other/run003/stratixiv_arch.timing.xml/CHERI_stratixiv_arch_timing.blif/common 1783976 38 173 62892 59064 3 36122 2680 86 64 5504 M9K auto 161.48 658363 451.14 3.77 13.0094 -348427 -12.0094 7.25521 0.209617 0.169449 26.6551 20.7507 872304 138831 482466 381936244 52315467 0 0 1.07263e+08 19488.2 20 13.5825 7.43717 -393006 -12.5825 0 0 57.25 37.9091 30.3762 +stratixiv_arch.timing.xml EKF-SLAM_Jacobians_stratixiv_arch_timing.blif common 873.21 574 2805 16 0 0 0 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_nightly/titan_other/run003/stratixiv_arch.timing.xml/EKF-SLAM_Jacobians_stratixiv_arch_timing.blif/common 1867964 4 570 66175 54803 2 39637 3395 91 67 6097 io auto 136.48 683175 470.78 3.58 28.272 -109937 -27.272 7.24493 0.224491 0.177331 27.8178 22.4999 954462 226668 908727 1000484779 161171256 0 0 1.18864e+08 19495.5 22 29.2958 7.66167 -122816 -28.2958 0 0 140.87 39.082 32.3537 +stratixiv_arch.timing.xml fir_cascade_stratixiv_arch_timing.blif common 1086.77 40 3678 172 1 0 0 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_nightly/titan_other/run003/stratixiv_arch.timing.xml/fir_cascade_stratixiv_arch_timing.blif/common 4153528 19 21 171111 96274 1 72623 3891 194 144 27936 DSP auto 97.86 717944 439.35 2.49 5.71261 -136483 -4.71261 3.69506 0.362396 0.323268 49.7215 43.838 820533 142207 171038 272204886 61250598 0 0 5.45821e+08 19538.3 12 7.10717 3.9555 -208318 -6.10717 0 0 49.43 63.7147 56.901 +stratixiv_arch.timing.xml jacobi_stratixiv_arch_timing.blif common 570.52 536 1972 7 4 0 0 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_nightly/titan_other/run003/stratixiv_arch.timing.xml/jacobi_stratixiv_arch_timing.blif/common 1578720 227 309 49176 40422 1 28183 2519 85 63 5355 io auto 95.89 314421 336.07 2.03 198.847 -126590 -197.847 198.847 0.104979 0.0832463 16.7541 13.4696 399782 86109 271857 214690493 24232179 0 0 1.04230e+08 19464.1 19 189.538 189.538 -144463 -188.538 0 0 26.50 22.8233 18.7869 +stratixiv_arch.timing.xml JPEG_stratixiv_arch_timing.blif common 414.08 36 1332 8 149 2 0 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_nightly/titan_other/run003/stratixiv_arch.timing.xml/JPEG_stratixiv_arch_timing.blif/common 1455648 3 33 52402 39411 1 28117 1527 73 54 3942 M9K auto 76.35 333731 218.54 1.97 16.8571 -315426 -15.8571 16.8571 0.107399 0.0894608 14.4849 11.5052 446522 82925 205213 213167850 33260253 0 0 7.68757e+07 19501.7 18 17.6082 17.6082 -335363 -16.6082 0 0 29.68 20.1764 16.4852 +stratixiv_arch.timing.xml leon2_stratixiv_arch_timing.blif common 155.50 251 951 1 17 0 0 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_nightly/titan_other/run003/stratixiv_arch.timing.xml/leon2_stratixiv_arch_timing.blif/common 1034720 55 196 20131 19956 1 8395 1220 44 33 1452 io auto 44.59 123508 61.51 0.43 7.80776 -84161.3 -6.80776 7.80776 0.0424159 0.0324636 5.79069 4.46629 173442 26533 111263 90994801 10350184 0 0 2.80180e+07 19296.2 13 7.97265 7.97265 -90136 -6.97265 0 0 10.51 7.82176 6.25012 +stratixiv_arch.timing.xml leon3mp_stratixiv_arch_timing.blif common 336.93 255 2095 1 28 0 0 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_nightly/titan_other/run003/stratixiv_arch.timing.xml/leon3mp_stratixiv_arch_timing.blif/common 1336212 84 171 36458 36247 3 20591 2379 62 46 2852 LAB auto 88.45 299485 167.98 1.34 12.2312 -84057.7 -11.2312 4.1469 0.104269 0.0809203 11.9026 9.39658 387645 54857 189436 119409681 13931573 0 0 5.55332e+07 19471.7 12 13.469 4.51114 -95678.2 -12.469 0 0 17.38 16.0385 12.9992 +stratixiv_arch.timing.xml MCML_stratixiv_arch_timing.blif common 493.21 69 2106 10 295 16 0 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_nightly/titan_other/run003/stratixiv_arch.timing.xml/MCML_stratixiv_arch_timing.blif/common 1853176 36 33 57796 49182 1 20383 2496 105 78 8190 M9K auto 80.27 263815 220.91 1.29 9.65456 -96867.1 -8.65456 9.65456 0.111354 0.0901365 18.0282 14.2262 403371 61335 173118 214203305 42166745 0 0 1.60337e+08 19577.1 15 9.88699 9.88699 -185844 -8.88699 0 0 41.76 23.5579 19.145 +stratixiv_arch.timing.xml MMM_stratixiv_arch_timing.blif common 426.54 478 1243 1 300 4 0 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_nightly/titan_other/run003/stratixiv_arch.timing.xml/MMM_stratixiv_arch_timing.blif/common 1687036 202 276 35125 30509 3 21597 2026 106 79 8374 M9K auto 67.70 268290 167.55 1.01 9.61641 -43421.7 -8.61641 3.2225 0.102583 0.076419 13.9723 10.9332 400814 54282 148271 193929640 34411060 0 0 1.63929e+08 19576.0 15 10.1311 3.59809 -58181.2 -9.13114 0 0 30.86 18.61 15.0181 +stratixiv_arch.timing.xml radar20_stratixiv_arch_timing.blif common 210.11 5 335 31 105 0 2 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_nightly/titan_other/run003/stratixiv_arch.timing.xml/radar20_stratixiv_arch_timing.blif/common 1341752 3 2 14862 10304 26 7545 478 89 66 5874 DSP auto 38.76 115438 49.22 0.16 5.69753 -35401.8 -4.69753 3.98639 0.0417616 0.0351174 6.0704 5.0195 168915 17348 37310 49304357 9618656 0 0 1.14496e+08 19491.9 15 5.99393 4.10529 -47208.1 -4.99393 0 0 8.57 8.12909 6.88781 +stratixiv_arch.timing.xml random_stratixiv_arch_timing.blif common 575.38 693 1772 25 16 0 0 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_nightly/titan_other/run003/stratixiv_arch.timing.xml/random_stratixiv_arch_timing.blif/common 1817564 35 658 51416 37539 1 27838 2506 108 80 8640 io auto 73.43 273923 306.92 1.46 40.0047 -60899.9 -39.0047 40.0047 0.108148 0.0954133 22.7092 19.0439 367093 73282 213103 227868109 36745001 0 0 1.69281e+08 19592.7 18 40.084 40.084 -66381.9 -39.084 0 0 30.27 28.8356 24.5508 +stratixiv_arch.timing.xml Reed_Solomon_stratixiv_arch_timing.blif common 381.36 753 1134 5 32 0 0 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_nightly/titan_other/run003/stratixiv_arch.timing.xml/Reed_Solomon_stratixiv_arch_timing.blif/common 1708236 13 740 25173 25306 1 12841 1924 117 87 10179 io auto 54.55 163872 128.63 0.69 9.15497 -34302.5 -8.15497 8.09384 0.06256 0.0492745 8.17271 6.52022 202645 30008 107333 77167436 8993295 0 0 1.99743e+08 19623.1 10 9.94298 8.35343 -39700.5 -8.94298 0 0 9.72 10.7136 8.80397 +stratixiv_arch.timing.xml smithwaterman_stratixiv_arch_timing.blif common 486.98 117 2162 0 0 0 0 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_nightly/titan_other/run003/stratixiv_arch.timing.xml/smithwaterman_stratixiv_arch_timing.blif/common 1479248 79 38 66795 54922 1 35874 2279 62 46 2852 LAB auto 79.61 259552 320.38 2.04 9.67265 -176614 -8.67265 9.67265 0.125494 0.0984952 16.4318 13.1833 334981 99551 209738 156040315 18616928 0 0 5.55332e+07 19471.7 17 10.5013 10.5013 -201976 -9.50128 0 0 19.48 22.7132 18.709 +stratixiv_arch.timing.xml stap_steering_stratixiv_arch_timing.blif common 321.25 213 1566 26 4 0 0 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_nightly/titan_other/run003/stratixiv_arch.timing.xml/stap_steering_stratixiv_arch_timing.blif/common 1521408 139 74 57121 41054 1 24187 1809 75 56 4200 DSP auto 63.17 165167 152.46 1.01 5.6808 -27863.8 -4.6808 5.18621 0.111794 0.0934951 16.8628 14.0913 220914 53925 95436 111897254 21882175 0 0 8.19523e+07 19512.5 13 5.93959 5.57581 -42510.8 -4.93959 0 0 16.27 21.4665 18.282 +stratixiv_arch.timing.xml sudoku_check_stratixiv_arch_timing.blif common 139.10 54 671 0 40 0 1 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_nightly/titan_other/run003/stratixiv_arch.timing.xml/sudoku_check_stratixiv_arch_timing.blif/common 1015204 2 52 16673 16662 2 12020 766 38 28 1064 LAB auto 37.81 177997 53.99 0.38 5.91051 -22320.6 -4.91051 4.82757 0.0512772 0.0387108 6.47727 4.95923 232822 47336 146618 140826246 18790810 0 0 2.04775e+07 19245.7 15 6.04977 5.19305 -26959.5 -5.04977 0 0 16.35 9.00697 7.13785 +stratixiv_arch.timing.xml SURF_desc_stratixiv_arch_timing.blif common 535.22 445 2166 19 51 0 0 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_nightly/titan_other/run003/stratixiv_arch.timing.xml/SURF_desc_stratixiv_arch_timing.blif/common 1610092 131 314 57881 45152 1 32966 2681 73 54 3942 io auto 85.28 325925 332.35 2.60 197.956 -71278.7 -196.956 197.956 0.171344 0.140961 20.2214 16.7617 425782 91978 273342 232056364 28532249 0 0 7.68757e+07 19501.7 17 186.537 186.537 -82847.5 -185.537 0 0 30.12 28.3454 24.0067 +stratixiv_arch.timing.xml ucsb_152_tap_fir_stratixiv_arch_timing.blif common 99.43 42 750 0 0 0 0 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_nightly/titan_other/run003/stratixiv_arch.timing.xml/ucsb_152_tap_fir_stratixiv_arch_timing.blif/common 966092 13 29 26295 20086 1 12417 792 39 29 1131 LAB auto 12.08 76598 54.29 0.32 5.12079 -4836.29 -4.12079 2.70704 0.0251636 0.020905 3.66108 2.99456 80209 28118 37672 29749453 3289834 0 0 2.17613e+07 19240.8 15 5.32359 2.74868 -5384.88 -4.32359 0 0 3.40 4.77289 3.9885 +stratixiv_arch.timing.xml uoft_raytracer_stratixiv_arch_timing.blif common 658.77 964 982 19 34 0 0 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_nightly/titan_other/run003/stratixiv_arch.timing.xml/uoft_raytracer_stratixiv_arch_timing.blif/common 2218488 542 422 37277 26038 1 20655 1999 147 109 16023 io auto 51.77 264252 290.80 1.94 9.37886 -39232.4 -8.37886 7.87006 0.0793446 0.0636085 12.0276 9.79755 342120 63517 140930 178387822 34995705 0 0 3.15224e+08 19673.2 19 9.83117 7.7229 -43856.7 -8.83117 0 0 24.32 16.0695 13.4479 +stratixiv_arch.timing.xml wb_conmax_stratixiv_arch_timing.blif common 575.42 1107 724 0 0 0 0 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_nightly/titan_other/run003/stratixiv_arch.timing.xml/wb_conmax_stratixiv_arch_timing.blif/common 2675556 403 704 15490 16194 1 8415 1831 167 124 20708 io auto 43.73 196192 156.24 0.42 11.5434 -23243.5 -10.5434 4.69945 0.0455293 0.0370973 6.19152 5.07561 239184 24258 93974 60084224 6802068 0 0 4.07637e+08 19685.0 13 12.0352 4.77336 -29077.4 -11.0352 0 0 8.11 8.09259 6.79959 +stratixiv_arch.timing.xml picosoc_stratixiv_arch_timing.blif common 112.06 35 730 0 6 0 0 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_nightly/titan_other/run003/stratixiv_arch.timing.xml/picosoc_stratixiv_arch_timing.blif/common 972904 18 17 16969 16357 1 6291 771 39 29 1131 LAB auto 46.50 85462 30.99 0.23 6.99606 -44851.1 -5.99606 6.99606 0.0272209 0.0222113 3.37322 2.62673 113305 18749 83383 60733936 6528173 0 0 2.17613e+07 19240.8 13 7.16443 7.16443 -48512.4 -6.16443 0 0 6.81 4.8246 3.92182 +stratixiv_arch.timing.xml murax_stratixiv_arch_timing.blif common 17.35 35 76 0 8 0 0 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_nightly/titan_other/run003/stratixiv_arch.timing.xml/murax_stratixiv_arch_timing.blif/common 782256 18 17 2291 2142 1 1504 119 16 12 192 LAB M9K auto 4.88 10424 2.22 0.02 4.965 -3545.67 -3.965 3.875 0.00368836 0.00294373 0.537211 0.411434 14116 3621 8306 7325933 995004 0 0 3.52194e+06 18343.4 12 5.05408 4.0797 -3793.6 -4.05408 0 0 0.79 0.744016 0.599798 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly/titan_quick_qor/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly/titan_quick_qor/config/golden_results.txt index ed91774ddaa..62e8a723b96 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly/titan_quick_qor/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly/titan_quick_qor/config/golden_results.txt @@ -1,23 +1,23 @@ -arch circuit script_params vtr_flow_elapsed_time error num_io num_LAB num_DSP num_M9K num_M144K num_PLL vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time -stratixiv_arch.timing.xml directrf_stratixiv_arch_timing.blif common 15559.10 319 61450 240 2535 0 0 success v8.0.0-1870-gb04b8b68d release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T09:59:48 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_nightly/titan_quick_qor/run003/stratixiv_arch.timing.xml/directrf_stratixiv_arch_timing.blif/common 17908116 62 257 1374456 930989 2 679981 64544 317 235 74495 M9K auto 991.97 12281902 12065.54 52.64 11.4825 -1.70874e+06 -10.4825 2.10005 1.51306 422.484 299.597 13972300 1885244 3370262 5345688217 877716856 0 0 1.42890e+09 19181.1 15 11.866 11.0436 -2.5887e+06 -10.866 0 0 877.28 524.199 384.368 -stratixiv_arch.timing.xml bitcoin_miner_stratixiv_arch_timing.blif common 14456.28 385 32503 0 1331 0 1 success v8.0.0-1870-gb04b8b68d release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T09:59:48 betzgrp-wintermute.eecg.utoronto.ca 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67.0409 48.9399 2171516 287940 886247 962543168 174799830 0 0 4.27406e+08 19680.7 16 12.0281 12.0281 -908132 -11.0281 0 0 149.60 91.5259 69.7213 +arch circuit script_params vtr_flow_elapsed_time error num_io num_LAB num_DSP num_M9K num_M144K num_PLL vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time +stratixiv_arch.timing.xml directrf_stratixiv_arch_timing.blif common 27114.45 319 61450 240 2535 0 0 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_nightly/titan_quick_qor/run002/stratixiv_arch.timing.xml/directrf_stratixiv_arch_timing.blif/common 17133400 62 257 1374456 930989 2 679981 64544 317 235 74495 M9K auto 1469.22 12490881 22037.28 110.46 12.7415 -1.70403e+06 -11.7415 10.028 3.14492 2.56688 532.955 428.554 13158207 1769579 3102075 3999342046 632554133 0 0 1.42888e+09 19180.9 14 13.5386 10.8207 -2.53421e+06 -12.5386 0 0 1819.59 658.019 539.379 +stratixiv_arch.timing.xml bitcoin_miner_stratixiv_arch_timing.blif common 26460.16 385 32503 0 1331 0 1 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_nightly/titan_quick_qor/run002/stratixiv_arch.timing.xml/bitcoin_miner_stratixiv_arch_timing.blif/common 13365056 353 32 1446409 1087537 2 848902 34220 225 167 37575 LAB auto 978.13 9957243 24022.75 147.13 7.13955 -849804 -6.13955 7.13955 2.61284 2.10559 379.281 310.396 11170159 2526441 3697186 3695152979 523450109 0 0 7.28427e+08 19385.9 20 9.43789 9.43789 -1.40988e+06 -8.43789 0 0 564.08 508.256 421.985 +stratixiv_arch.timing.xml LU230_stratixiv_arch_timing.blif common 12035.60 373 16571 116 5040 16 0 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_nightly/titan_quick_qor/run002/stratixiv_arch.timing.xml/LU230_stratixiv_arch_timing.blif/common 17901196 178 195 663067 568001 2 413013 22116 430 319 137170 M9K auto 1249.31 16652524 7287.89 41.59 23.819 -3.14544e+06 -22.819 9.36285 2.3237 1.87961 400.301 324.444 17720945 1231174 2456597 3528484437 649808735 0 0 2.85686e+09 20827.1 16 24.1995 10.9518 -6.21914e+06 -23.1995 0 0 911.26 504.805 416.261 +stratixiv_arch.timing.xml sparcT1_chip2_stratixiv_arch_timing.blif common 15722.62 1891 33629 3 506 0 0 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_nightly/titan_quick_qor/run002/stratixiv_arch.timing.xml/sparcT1_chip2_stratixiv_arch_timing.blif/common 12530408 815 1076 764693 760412 1423 416439 36029 280 207 57960 io auto 1900.11 7244370 12110.45 81.82 17.6981 -4.14406e+06 -16.6981 5.52342 2.3612 1.82935 319.39 252.614 8177346 1211859 3993469 2635471449 329737758 0 0 1.11555e+09 19246.8 18 18.3537 5.83932 -5.06622e+06 -17.3537 0 0 485.27 427.415 345.558 +stratixiv_arch.timing.xml LU_Network_stratixiv_arch_timing.blif common 11439.15 399 31006 112 1175 0 2 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_nightly/titan_quick_qor/run002/stratixiv_arch.timing.xml/LU_Network_stratixiv_arch_timing.blif/common 11238056 85 185 721554 630079 28 403716 32694 220 163 35860 LAB auto 981.42 4699152 9340.44 51.84 6.21149 -546190 -5.21149 4.42725 2.21733 1.75228 362.321 283.858 5717675 893277 1886018 1672592809 281691352 0 0 6.95741e+08 19401.6 17 7.11927 4.78608 -837373 -6.11927 0 0 309.79 462.969 370.897 +stratixiv_arch.timing.xml neuron_stratixiv_arch_timing.blif common 772.12 77 3123 89 136 0 0 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_nightly/titan_quick_qor/run002/stratixiv_arch.timing.xml/neuron_stratixiv_arch_timing.blif/common 2740996 42 35 119888 86875 1 51283 3425 129 96 12384 DSP auto 108.43 624011 354.80 2.26 7.38807 -78421.5 -6.38807 5.18703 0.296923 0.247129 40.2537 33.6795 784410 111971 189656 270679483 57900121 0 0 2.43094e+08 19629.7 12 7.64301 5.79722 -122714 -6.64301 0 0 51.01 51.7685 44.171 +stratixiv_arch.timing.xml sparcT1_core_stratixiv_arch_timing.blif common 1285.58 310 4000 1 128 0 0 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_nightly/titan_quick_qor/run002/stratixiv_arch.timing.xml/sparcT1_core_stratixiv_arch_timing.blif/common 2165312 173 137 92814 91975 1 60944 4439 82 61 5002 LAB auto 293.83 928184 782.75 5.38 8.52276 -530618 -7.52276 8.52276 0.318362 0.242508 41.5197 31.7536 1225985 232453 797691 614295520 80092150 0 0 9.73922e+07 19470.6 21 9.0175 9.0175 -644606 -8.0175 0 0 86.35 58.7266 46.3146 +stratixiv_arch.timing.xml stereo_vision_stratixiv_arch_timing.blif common 696.64 506 3246 76 113 0 0 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_nightly/titan_quick_qor/run002/stratixiv_arch.timing.xml/stereo_vision_stratixiv_arch_timing.blif/common 2555048 172 334 127090 94090 3 61732 3941 129 96 12384 DSP auto 84.63 562899 340.99 2.28 7.89299 -56989.2 -6.89299 3.23635 0.220359 0.180863 29.3572 23.9212 635674 134127 201911 189819266 27561583 0 0 2.43094e+08 19629.7 14 7.92007 3.33907 -79809.8 -6.92007 0 0 28.46 38.5198 32.0267 +stratixiv_arch.timing.xml cholesky_mc_stratixiv_arch_timing.blif common 1134.27 262 4765 59 444 16 0 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_nightly/titan_quick_qor/run002/stratixiv_arch.timing.xml/cholesky_mc_stratixiv_arch_timing.blif/common 3033436 111 151 140214 108592 1 66751 5546 125 93 11625 M9K auto 139.41 856294 625.70 4.05 6.61962 -212371 -5.61962 6.61962 0.373008 0.298087 53.2177 43.1928 1188872 161466 364822 653310116 151461903 0 0 2.28048e+08 19617.0 18 7.35884 7.35884 -342959 -6.35884 0 0 137.97 71.1019 59.0781 +stratixiv_arch.timing.xml gsm_switch_stratixiv_arch_timing.blif common 6715.97 136 21492 0 1848 0 1 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_nightly/titan_quick_qor/run002/stratixiv_arch.timing.xml/gsm_switch_stratixiv_arch_timing.blif/common 9785776 100 36 504627 490068 5 200916 23477 255 189 48195 M9K auto 862.19 4546030 4644.83 25.68 8.18644 -1.54828e+06 -7.18644 6.19203 1.24019 0.954782 205.221 157.211 5361841 507245 1549763 1203957187 194001358 0 0 9.29950e+08 19295.6 12 9.14032 6.85182 -2.22832e+06 -8.14032 0 0 271.34 255.761 201.21 +stratixiv_arch.timing.xml mes_noc_stratixiv_arch_timing.blif common 11338.32 5 23760 0 800 0 8 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_nightly/titan_quick_qor/run002/stratixiv_arch.timing.xml/mes_noc_stratixiv_arch_timing.blif/common 8976636 3 2 577696 547568 17 345674 24573 193 143 27599 LAB auto 1698.96 4147460 8378.50 58.13 12.8537 -3.14083e+06 -11.8537 8.24406 2.0135 1.54932 255.183 198.217 5041168 853385 2495785 1969491924 241212820 0 0 5.39284e+08 19540.0 20 14.2141 8.7034 -3.83722e+06 -13.2141 0 0 632.25 353.694 282.541 +stratixiv_arch.timing.xml dart_stratixiv_arch_timing.blif common 2497.78 69 6862 0 530 0 0 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_nightly/titan_quick_qor/run002/stratixiv_arch.timing.xml/dart_stratixiv_arch_timing.blif/common 4149648 23 46 223304 202401 1 131203 7461 138 102 14076 M9K auto 466.39 2148316 1544.30 11.64 14.4761 -1.54757e+06 -13.4761 14.4761 0.764432 0.573331 97.1517 73.9376 2478514 414724 1089892 1005032915 138609823 0 0 2.76626e+08 19652.3 19 15.3002 15.3002 -2.02492e+06 -14.3002 0 0 215.51 133.604 104.935 +stratixiv_arch.timing.xml denoise_stratixiv_arch_timing.blif common 7595.67 852 14030 24 359 0 0 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_nightly/titan_quick_qor/run002/stratixiv_arch.timing.xml/denoise_stratixiv_arch_timing.blif/common 5730356 264 588 355537 274786 1 218574 15265 150 111 16650 LAB auto 460.09 2725722 6480.33 40.81 897.192 -938284 -896.192 897.192 1.05785 0.867026 140.699 116.779 3249712 753117 2432885 2037464482 242099859 0 0 3.27518e+08 19670.7 24 886.403 886.403 -1.19306e+06 -885.403 0 0 269.32 198.795 167.06 +stratixiv_arch.timing.xml sparcT2_core_stratixiv_arch_timing.blif common 6508.69 451 14725 0 260 0 0 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_nightly/titan_quick_qor/run002/stratixiv_arch.timing.xml/sparcT2_core_stratixiv_arch_timing.blif/common 5258560 239 212 302755 300220 1 184812 15436 153 113 17289 LAB auto 870.99 3761906 4987.25 35.49 10.882 -757045 -9.88197 10.882 1.06783 0.810081 133.049 101.118 4628535 644304 2476499 1850415845 227883917 0 0 3.40229e+08 19678.9 17 11.2614 11.2614 -1.07489e+06 -10.2614 0 0 268.99 179.269 140.266 +stratixiv_arch.timing.xml cholesky_bdti_stratixiv_arch_timing.blif common 2870.43 162 9680 132 600 0 0 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_nightly/titan_quick_qor/run002/stratixiv_arch.timing.xml/cholesky_bdti_stratixiv_arch_timing.blif/common 5411520 94 68 331744 255478 1 156536 10574 169 125 21125 DSP auto 366.43 1957997 1723.41 11.39 8.43278 -535028 -7.43278 8.43278 0.803165 0.665794 112.428 92.9166 2528750 384542 840112 1406271355 300695707 0 0 4.15889e+08 19687.0 19 9.20202 9.20202 -825079 -8.20202 0 0 332.83 151.84 127.756 +stratixiv_arch.timing.xml minres_stratixiv_arch_timing.blif common 2986.96 229 7818 78 1459 0 1 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_nightly/titan_quick_qor/run002/stratixiv_arch.timing.xml/minres_stratixiv_arch_timing.blif/common 6668424 129 100 316623 257480 3 183470 9585 225 167 37575 M9K auto 444.28 2291907 1644.47 11.79 6.52043 -357450 -5.52043 4.60288 0.898408 0.73974 119.24 99.0706 2935697 416406 829032 945471094 172777169 0 0 7.28427e+08 19385.9 16 9.82157 6.19556 -569390 -8.82157 0 0 172.85 157.667 133.478 +stratixiv_arch.timing.xml stap_qrd_stratixiv_arch_timing.blif common 4103.14 150 15899 75 553 0 0 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_nightly/titan_quick_qor/run002/stratixiv_arch.timing.xml/stap_qrd_stratixiv_arch_timing.blif/common 4740072 68 82 284051 234177 1 144423 16677 158 117 18486 LAB auto 326.25 2219653 3189.01 15.06 6.79714 -388510 -5.79714 6.79714 0.639211 0.52988 126.57 102.673 2659061 335990 827912 1009666529 182595553 0 0 3.63991e+08 19690.1 15 7.5363 7.5363 -600141 -6.53631 0 0 227.04 155.787 128.233 +stratixiv_arch.timing.xml openCV_stratixiv_arch_timing.blif common 2781.47 208 7145 213 785 40 0 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_nightly/titan_quick_qor/run002/stratixiv_arch.timing.xml/openCV_stratixiv_arch_timing.blif/common 5945324 106 102 279132 212552 1 168784 8391 209 155 32395 DSP auto 402.12 2608443 1526.28 11.23 10.0792 -640688 -9.07916 10.0792 0.832084 0.705574 109.117 91.4389 3256682 467289 1060868 1280232998 239367192 0 0 6.29744e+08 19439.5 14 10.9677 10.9677 -928107 -9.96769 0 0 237.95 143.97 122.629 +stratixiv_arch.timing.xml bitonic_mesh_stratixiv_arch_timing.blif common 3903.05 119 7239 85 1664 0 0 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_nightly/titan_quick_qor/run002/stratixiv_arch.timing.xml/bitonic_mesh_stratixiv_arch_timing.blif/common 6981652 87 32 233978 190746 1 146198 9107 242 179 43318 M9K auto 598.74 3624476 2138.97 16.15 12.1912 -1.52088e+06 -11.1912 12.1912 1.02345 0.822015 133.542 108.014 4629145 505615 1634722 1798263323 329584032 0 0 8.37652e+08 19337.3 15 12.8801 12.8801 -1.92566e+06 -11.8801 0 0 340.89 181.023 150.171 +stratixiv_arch.timing.xml segmentation_stratixiv_arch_timing.blif common 2693.72 441 6937 15 481 0 0 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_nightly/titan_quick_qor/run002/stratixiv_arch.timing.xml/segmentation_stratixiv_arch_timing.blif/common 3553452 72 369 178312 137832 1 108345 7874 136 101 13736 M9K auto 224.05 1321319 2054.62 14.20 870.616 -420887 -869.616 870.616 0.445876 0.364647 63.6551 52.4386 1687418 374304 1125305 984342265 121506108 0 0 2.69860e+08 19646.2 23 852.474 852.474 -552671 -851.474 0 0 130.23 90.0459 75.415 +stratixiv_arch.timing.xml SLAM_spheric_stratixiv_arch_timing.blif common 1702.10 479 5366 37 0 0 0 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_nightly/titan_quick_qor/run002/stratixiv_arch.timing.xml/SLAM_spheric_stratixiv_arch_timing.blif/common 2653848 323 156 140638 111354 1 78004 5882 95 70 6650 LAB auto 223.55 1374386 1176.59 7.85 87.569 -388477 -86.569 87.569 0.390002 0.33934 54.556 44.9362 1729218 297300 1013784 1082735154 166362065 0 0 1.29880e+08 19530.8 17 86.5799 86.5799 -437976 -85.5799 0 0 158.71 73.8259 61.8996 +stratixiv_arch.timing.xml des90_stratixiv_arch_timing.blif common 1975.47 117 4233 44 860 0 0 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_nightly/titan_quick_qor/run002/stratixiv_arch.timing.xml/des90_stratixiv_arch_timing.blif/common 4070272 85 32 138853 110549 1 87969 5254 171 127 21717 M9K auto 339.64 1641191 1049.13 7.86 11.5765 -770122 -10.5765 11.5765 0.578652 0.472559 74.1361 60.1258 2265343 294723 906545 977626022 177456470 0 0 4.27392e+08 19680.0 16 12.313 12.313 -926605 -11.313 0 0 171.77 100.937 83.8938 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vpr_reg_mcnc/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vpr_reg_mcnc/config/golden_results.txt index 49548007c75..b3cedc7295d 100755 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vpr_reg_mcnc/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vpr_reg_mcnc/config/golden_results.txt @@ -1,21 +1,21 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6_frac_N10_40nm.xml alu4.pre-vpr.blif common 3.15 -1 -1 -1 -1 -1 -1 -1 -1 -1 78 14 -1 -1 success v8.0.0-2035-g8d89fa817 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-04T09:52:13 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vpr_reg_mcnc/run010/k6_frac_N10_40nm.xml/alu4.pre-vpr.blif/common 35216 14 8 926 934 0 489 100 11 11 121 clb auto 0.57 4545 0.49 0.00 4.13095 -29.4096 -4.13095 nan 0.000998014 0.000733417 0.106191 0.0812653 50 7158 28 4.36541e+06 4.20373e+06 367716. 3038.97 1.19 0.382191 0.307566 6588 19 3147 13875 404780 78580 4.82558 nan -33.8986 -4.82558 0 0 488301. 4035.55 0.15 0.0752746 0.0665839 -k6_frac_N10_40nm.xml apex2.pre-vpr.blif common 4.98 -1 -1 -1 -1 -1 -1 -1 -1 -1 100 38 -1 -1 success v8.0.0-2035-g8d89fa817 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-04T09:52:13 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vpr_reg_mcnc/run010/k6_frac_N10_40nm.xml/apex2.pre-vpr.blif/common 37140 38 3 1113 1116 0 660 141 12 12 144 clb auto 1.02 7294 0.72 0.01 4.93262 -14.2396 -4.93262 nan 0.00122455 0.000890487 0.131515 0.0999061 68 12356 42 5.3894e+06 5.3894e+06 607821. 4220.98 2.14 0.547118 0.440498 11351 17 4674 22716 793324 139303 5.59168 nan -16.129 -5.59168 0 0 752446. 5225.32 0.20 0.0870064 0.0780969 -k6_frac_N10_40nm.xml apex4.pre-vpr.blif common 3.74 -1 -1 -1 -1 -1 -1 -1 -1 -1 81 9 -1 -1 success v8.0.0-2035-g8d89fa817 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-04T09:52:13 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vpr_reg_mcnc/run010/k6_frac_N10_40nm.xml/apex4.pre-vpr.blif/common 36476 9 19 897 916 0 559 109 11 11 121 clb auto 0.80 6009 0.56 0.00 4.29596 -69.3669 -4.29596 nan 0.000999628 0.000739645 0.110225 0.0847747 70 9868 32 4.36541e+06 4.36541e+06 511363. 4226.14 1.41 0.394619 0.319183 8989 18 4206 22184 728600 129373 4.91069 nan -79.5225 -4.91069 0 0 640906. 5296.74 0.18 0.0738126 0.0655693 -k6_frac_N10_40nm.xml bigkey.pre-vpr.blif common 5.11 -1 -1 -1 -1 -1 -1 -1 -1 -1 71 229 -1 -1 success v8.0.0-2035-g8d89fa817 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-04T09:52:13 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vpr_reg_mcnc/run010/k6_frac_N10_40nm.xml/bigkey.pre-vpr.blif/common 40928 229 197 1364 1561 1 539 497 16 16 256 io auto 0.63 4369 1.26 0.01 2.52649 -602.604 -2.52649 2.52649 0.00150375 0.00130652 0.217357 0.182905 36 8296 28 1.05632e+07 3.82647e+06 638738. 2495.07 2.03 0.662877 0.579021 7174 13 1844 4823 244728 56441 2.94081 2.94081 -725.784 -2.94081 0 0 786978. 3074.13 0.12 0.0728988 0.067624 -k6_frac_N10_40nm.xml clma.pre-vpr.blif common 22.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 306 62 -1 -1 success v8.0.0-2035-g8d89fa817 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-04T09:52:13 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vpr_reg_mcnc/run010/k6_frac_N10_40nm.xml/clma.pre-vpr.blif/common 78668 62 82 3672 3754 1 2349 450 20 20 400 clb auto 2.66 28271 4.53 0.03 7.3873 -313.176 -7.3873 7.3873 0.00646821 0.0042712 0.957019 0.637457 90 46920 32 1.74617e+07 1.64916e+07 2.33441e+06 5836.01 11.61 2.91813 2.18454 42001 17 13632 57828 2166827 341987 8.20346 8.20346 -355.143 -8.20346 0 0 2.96194e+06 7404.86 0.76 0.346531 0.304618 -k6_frac_N10_40nm.xml des.pre-vpr.blif common 4.66 -1 -1 -1 -1 -1 -1 -1 -1 -1 51 256 -1 -1 success v8.0.0-2035-g8d89fa817 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-04T09:52:13 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vpr_reg_mcnc/run010/k6_frac_N10_40nm.xml/des.pre-vpr.blif/common 40936 256 245 954 1199 0 581 552 18 18 324 io auto 0.26 5313 1.28 0.01 3.36026 -639.053 -3.36026 nan 0.00158637 0.00141153 0.174995 0.154841 38 9362 23 1.37969e+07 2.74859e+06 861717. 2659.62 1.74 0.556794 0.507691 8380 12 2176 4871 267585 61494 4.2211 nan -794.859 -4.2211 0 0 1.08879e+06 3360.46 0.11 0.0587017 0.055182 -k6_frac_N10_40nm.xml diffeq.pre-vpr.blif common 2.77 -1 -1 -1 -1 -1 -1 -1 -1 -1 66 64 -1 -1 success v8.0.0-2035-g8d89fa817 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-04T09:52:13 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vpr_reg_mcnc/run010/k6_frac_N10_40nm.xml/diffeq.pre-vpr.blif/common 34624 64 39 1371 1410 1 542 169 11 11 121 clb auto 0.38 3268 0.54 0.00 4.58914 -911.456 -4.58914 4.58914 0.000991973 0.000816039 0.127843 0.10027 46 5534 17 4.36541e+06 3.557e+06 343362. 2837.71 0.95 0.384278 0.315664 4962 16 1951 5468 157862 33420 5.51488 5.51488 -1054.96 -5.51488 0 0 440296. 3638.81 0.12 0.0931907 0.0853721 -k6_frac_N10_40nm.xml dsip.pre-vpr.blif common 4.60 -1 -1 -1 -1 -1 -1 -1 -1 -1 71 229 -1 -1 success v8.0.0-2035-g8d89fa817 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-04T09:52:13 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vpr_reg_mcnc/run010/k6_frac_N10_40nm.xml/dsip.pre-vpr.blif/common 41468 229 197 1362 1559 1 566 497 16 16 256 io auto 0.66 4510 1.20 0.01 2.55156 -608.544 -2.55156 2.55156 0.00148707 0.00129047 0.194361 0.163899 38 8089 17 1.05632e+07 3.82647e+06 667532. 2607.55 1.50 0.573396 0.501974 7449 13 1840 4626 263524 60697 3.19804 3.19804 -734.438 -3.19804 0 0 843755. 3295.92 0.12 0.0740256 0.0688325 -k6_frac_N10_40nm.xml elliptic.pre-vpr.blif common 8.59 -1 -1 -1 -1 -1 -1 -1 -1 -1 166 131 -1 -1 success v8.0.0-2035-g8d89fa817 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-04T09:52:13 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vpr_reg_mcnc/run010/k6_frac_N10_40nm.xml/elliptic.pre-vpr.blif/common 55764 131 114 3421 3535 1 1164 411 15 15 225 clb auto 2.03 10092 1.83 0.01 6.9234 -3791.81 -6.9234 6.9234 0.00307006 0.00215855 0.424898 0.308843 62 17253 33 9.10809e+06 8.9464e+06 909814. 4043.62 2.94 1.26782 1.01179 15036 15 4684 19448 684653 116466 8.18287 8.18287 -4401.55 -8.18287 0 0 1.12687e+06 5008.33 0.29 0.186743 0.168855 -k6_frac_N10_40nm.xml ex1010.pre-vpr.blif common 17.10 -1 -1 -1 -1 -1 -1 -1 -1 -1 288 10 -1 -1 success v8.0.0-2035-g8d89fa817 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-04T09:52:13 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vpr_reg_mcnc/run010/k6_frac_N10_40nm.xml/ex1010.pre-vpr.blif/common 72544 10 10 2659 2669 0 1393 308 19 19 361 clb auto 2.92 25429 2.58 0.02 5.89909 -56.9473 -5.89909 nan 0.00397568 0.00269342 0.452056 0.317157 92 43387 36 1.55754e+07 1.55215e+07 2.13123e+06 5903.67 8.41 1.68101 1.27936 39115 17 9407 57312 2541251 334629 6.59987 nan -63.4666 -6.59987 0 0 2.70169e+06 7483.90 0.74 0.259631 0.226338 -k6_frac_N10_40nm.xml ex5p.pre-vpr.blif common 2.83 -1 -1 -1 -1 -1 -1 -1 -1 -1 62 8 -1 -1 success v8.0.0-2035-g8d89fa817 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-04T09:52:13 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vpr_reg_mcnc/run010/k6_frac_N10_40nm.xml/ex5p.pre-vpr.blif/common 32808 8 63 761 824 0 435 133 10 10 100 clb auto 0.52 3968 0.47 0.00 3.66777 -160.387 -3.66777 nan 0.000825922 0.000612476 0.0947581 0.072467 62 6651 25 3.44922e+06 3.34143e+06 366588. 3665.88 1.13 0.317422 0.25703 5940 16 2785 12079 392057 74806 4.32321 nan -189.055 -4.32321 0 0 454102. 4541.02 0.12 0.0568005 0.0514564 -k6_frac_N10_40nm.xml frisc.pre-vpr.blif common 10.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 169 20 -1 -1 success v8.0.0-2035-g8d89fa817 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-04T09:52:13 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vpr_reg_mcnc/run010/k6_frac_N10_40nm.xml/frisc.pre-vpr.blif/common 57324 20 116 3175 3291 1 1278 305 15 15 225 clb auto 1.71 13776 1.78 0.01 7.33361 -3878.59 -7.33361 7.33361 0.00262678 0.00216718 0.399983 0.299902 78 22267 27 9.10809e+06 9.10809e+06 1.10266e+06 4900.72 5.01 1.40799 1.13421 19830 17 5943 24319 976851 163809 8.54663 8.54663 -4537.52 -8.54663 0 0 1.39226e+06 6187.84 0.38 0.21695 0.194625 -k6_frac_N10_40nm.xml misex3.pre-vpr.blif common 3.20 -1 -1 -1 -1 -1 -1 -1 -1 -1 72 14 -1 -1 success v8.0.0-2035-g8d89fa817 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-04T09:52:13 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vpr_reg_mcnc/run010/k6_frac_N10_40nm.xml/misex3.pre-vpr.blif/common 34936 14 14 828 842 0 472 100 11 11 121 clb auto 0.65 4402 0.49 0.00 4.00896 -51.4978 -4.00896 nan 0.000897245 0.0006606 0.0978567 0.0750892 52 7377 34 4.36541e+06 3.88037e+06 379421. 3135.71 1.23 0.35845 0.289091 6759 17 3331 16743 583124 107453 4.68262 nan -60.789 -4.68262 0 0 499620. 4129.09 0.14 0.0640339 0.0575458 -k6_frac_N10_40nm.xml pdc.pre-vpr.blif common 18.24 -1 -1 -1 -1 -1 -1 -1 -1 -1 271 16 -1 -1 success v8.0.0-2035-g8d89fa817 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-04T09:52:13 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vpr_reg_mcnc/run010/k6_frac_N10_40nm.xml/pdc.pre-vpr.blif/common 72172 16 40 2839 2879 0 1511 327 19 19 361 clb auto 2.27 22864 2.68 0.02 5.9551 -223.297 -5.9551 nan 0.00425367 0.00288446 0.493563 0.34657 86 37986 35 1.55754e+07 1.46053e+07 2.00874e+06 5564.38 10.12 2.18166 1.67393 34874 18 9516 52700 2080242 302015 6.73274 nan -250.704 -6.73274 0 0 2.53507e+06 7022.34 0.71 0.281899 0.247557 -k6_frac_N10_40nm.xml s298.pre-vpr.blif common 2.74 -1 -1 -1 -1 -1 -1 -1 -1 -1 64 4 -1 -1 success v8.0.0-2035-g8d89fa817 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-04T09:52:13 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vpr_reg_mcnc/run010/k6_frac_N10_40nm.xml/s298.pre-vpr.blif/common 32188 4 6 726 732 1 380 74 10 10 100 clb auto 0.50 3586 0.39 0.00 5.42762 -43.69 -5.42762 5.42762 0.000836842 0.000632203 0.091282 0.0709818 50 5628 48 3.44922e+06 3.44922e+06 295697. 2956.97 1.05 0.353591 0.291579 5059 17 2144 9196 281030 51848 6.29751 6.29751 -51.9034 -6.29751 0 0 392659. 3926.59 0.10 0.0576842 0.0523943 -k6_frac_N10_40nm.xml s38417.pre-vpr.blif common 9.69 -1 -1 -1 -1 -1 -1 -1 -1 -1 250 29 -1 -1 success v8.0.0-2035-g8d89fa817 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-04T09:52:13 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vpr_reg_mcnc/run010/k6_frac_N10_40nm.xml/s38417.pre-vpr.blif/common 70684 29 106 4782 4888 1 2018 385 18 18 324 clb auto 1.81 12887 2.48 0.01 4.47861 -3196.34 -4.47861 4.47861 0.00380394 0.00268688 0.575461 0.409692 52 21065 25 1.37969e+07 1.34735e+07 1.12378e+06 3468.47 2.97 1.49333 1.16305 19079 14 6146 16531 562747 114792 5.52326 5.52326 -3663.87 -5.52326 0 0 1.48031e+06 4568.86 0.37 0.261999 0.236328 -k6_frac_N10_40nm.xml s38584.1.pre-vpr.blif common 10.51 -1 -1 -1 -1 -1 -1 -1 -1 -1 227 38 -1 -1 success v8.0.0-2035-g8d89fa817 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-04T09:52:13 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vpr_reg_mcnc/run010/k6_frac_N10_40nm.xml/s38584.1.pre-vpr.blif/common 69488 38 304 4422 4726 1 2038 569 18 18 324 clb auto 1.79 13238 2.65 0.02 4.11061 -2659.2 -4.11061 4.11061 0.00362505 0.00294396 0.5475 0.400074 58 23896 30 1.37969e+07 1.22339e+07 1.26150e+06 3893.53 3.57 1.53558 1.21756 20485 14 6607 17571 631189 131756 5.07914 5.07914 -3062.61 -5.07914 0 0 1.60510e+06 4954.00 0.38 0.269618 0.244879 -k6_frac_N10_40nm.xml seq.pre-vpr.blif common 4.22 -1 -1 -1 -1 -1 -1 -1 -1 -1 85 41 -1 -1 success v8.0.0-2035-g8d89fa817 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-04T09:52:13 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vpr_reg_mcnc/run010/k6_frac_N10_40nm.xml/seq.pre-vpr.blif/common 37800 41 35 1006 1041 0 599 161 12 12 144 clb auto 0.81 6256 0.69 0.00 4.11328 -118.565 -4.11328 nan 0.00110678 0.000823028 0.124495 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0.000800426 0.106699 0.0876993 50 5628 48 3.44922e+06 3.44922e+06 295697. 2956.97 1.42 0.418496 0.351724 5078 16 2234 9327 290769 54293 6.17453 6.17453 -52.7272 -6.17453 0 0 379824. 3798.24 0.14 0.068519 0.0628446 +k6_frac_N10_40nm.xml s38417.pre-vpr.blif common 13.03 -1 -1 -1 -1 -1 -1 -1 -1 -1 250 29 -1 -1 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vpr_reg_mcnc/run009/k6_frac_N10_40nm.xml/s38417.pre-vpr.blif/common 63856 29 106 4782 4888 1 2018 385 18 18 324 clb auto 2.28 12987 4.49 0.03 4.47861 -3196.34 -4.47861 4.47861 0.00480433 0.00370757 0.644954 0.508377 52 21065 25 1.37969e+07 1.34735e+07 1.12378e+06 3468.47 3.56 1.71339 1.41289 19079 14 6146 16531 562747 114792 5.52326 5.52326 -3663.87 -5.52326 0 0 1.48031e+06 4568.86 0.41 0.286461 0.262104 +k6_frac_N10_40nm.xml s38584.1.pre-vpr.blif common 14.24 -1 -1 -1 -1 -1 -1 -1 -1 -1 227 38 -1 -1 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vpr_reg_mcnc/run009/k6_frac_N10_40nm.xml/s38584.1.pre-vpr.blif/common 62936 38 304 4422 4726 1 2038 569 18 18 324 clb auto 2.24 13304 5.08 0.03 4.11061 -2659.2 -4.11061 4.11061 0.00467603 0.00386135 0.673352 0.539597 58 23896 30 1.37969e+07 1.22339e+07 1.26150e+06 3893.53 4.16 1.79261 1.49436 20485 14 6607 17571 631189 131756 5.07914 5.07914 -3062.61 -5.07914 0 0 1.60510e+06 4954.00 0.40 0.27994 0.255617 +k6_frac_N10_40nm.xml seq.pre-vpr.blif common 5.79 -1 -1 -1 -1 -1 -1 -1 -1 -1 85 41 -1 -1 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vpr_reg_mcnc/run009/k6_frac_N10_40nm.xml/seq.pre-vpr.blif/common 33824 41 35 1006 1041 0 599 161 12 12 144 clb auto 1.02 6256 1.29 0.01 4.11328 -118.565 -4.11328 nan 0.00140492 0.0011045 0.160104 0.129974 66 10954 28 5.3894e+06 4.58099e+06 593979. 4124.86 2.32 0.557976 0.462782 9922 17 4124 20782 729375 131122 4.7977 nan -138.898 -4.7977 0 0 735425. 5107.12 0.26 0.0964902 0.0871891 +k6_frac_N10_40nm.xml spla.pre-vpr.blif common 15.85 -1 -1 -1 -1 -1 -1 -1 -1 -1 213 16 -1 -1 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vpr_reg_mcnc/run009/k6_frac_N10_40nm.xml/spla.pre-vpr.blif/common 52320 16 46 2232 2278 0 1178 275 17 17 289 clb auto 2.18 15674 3.67 0.03 5.56011 -180.807 -5.56011 nan 0.00359813 0.00273732 0.420605 0.332003 72 26775 31 1.21262e+07 1.14794e+07 1.37091e+06 4743.65 7.16 1.77086 1.4411 23620 17 6841 37281 1466749 227622 6.51898 nan -213.676 -6.51898 0 0 1.71058e+06 5918.98 0.76 0.27306 0.244833 +k6_frac_N10_40nm.xml tseng.pre-vpr.blif common 2.94 -1 -1 -1 -1 -1 -1 -1 -1 -1 63 52 -1 -1 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vpr_reg_mcnc/run009/k6_frac_N10_40nm.xml/tseng.pre-vpr.blif/common 31000 52 122 1461 1583 1 476 237 10 10 100 clb auto 0.49 2380 0.83 0.01 4.22428 -1029.87 -4.22428 4.22428 0.00112555 0.000920685 0.139283 0.113333 46 4781 25 3.44922e+06 3.39532e+06 276332. 2763.32 0.87 0.379636 0.317213 4262 14 1550 3871 141397 34032 4.73687 4.73687 -1241.89 -4.73687 0 0 354105. 3541.05 0.10 0.0715144 0.0654175 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vpr_verify_rr_graph/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vpr_verify_rr_graph/config/golden_results.txt index 3333dfafeab..7970313f5fa 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vpr_verify_rr_graph/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vpr_verify_rr_graph/config/golden_results.txt @@ -1,6 +1,6 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_route_time -k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml raygentop.v common 13.24 0.27 30560 3 1.07 -1 -1 40436 -1 -1 100 214 0 8 v8.0.0-1603-g6c2a712a0 success betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr3/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vpr_verify_rr_graph/run003/k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml/raygentop.v/common 69284 214 305 2964 2870 1 1451 627 19 19 361 io auto 1.27 10465 1.84 4.309 -2465.69 -4.309 19171 4546 11197 2578546 581722 1.72706e+07 8.5574e+06 2.90560e+06 8048.76 15 4.84698 4.84698 -2859.35 -4.84698 0 0 0.56 -k6_frac_N10_frac_chain_mem32K_40nm.xml raygentop.v common 14.34 0.27 30380 3 1.02 -1 -1 40388 -1 -1 107 214 0 8 v8.0.0-1603-g6c2a712a0 success betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr3/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vpr_verify_rr_graph/run003/k6_frac_N10_frac_chain_mem32K_40nm.xml/raygentop.v/common 67516 214 305 2964 2870 1 1438 634 19 19 361 io auto 2.17 10699 1.77 4.29461 -2428.67 -4.29461 17562 3816 8573 1845564 412898 1.72706e+07 8.93466e+06 2.71656e+06 7525.11 12 4.72319 4.72319 -2774.87 -4.72319 0 0 0.44 -k6_frac_N10_mem32K_40nm.xml raygentop.v common 14.16 0.29 31512 8 1.43 -1 -1 37124 -1 -1 106 214 0 9 v8.0.0-1603-g6c2a712a0 success betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr3/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vpr_verify_rr_graph/run003/k6_frac_N10_mem32K_40nm.xml/raygentop.v/common 67224 214 305 2617 2733 1 1407 634 22 22 484 mult_36 auto 1.47 11693 1.63 4.17001 -2370.43 -4.17001 18465 3646 8733 2438262 505749 2.50602e+07 9.27676e+06 3.71564e+06 7676.94 11 4.872 4.872 -2824.27 -4.872 0 0 0.47 -k6_N10_mem32K_40nm.xml raygentop.v common 14.11 0.31 31528 8 1.44 -1 -1 37048 -1 -1 161 214 0 9 v8.0.0-1603-g6c2a712a0 success betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr3/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vpr_verify_rr_graph/run003/k6_N10_mem32K_40nm.xml/raygentop.v/common 68380 214 305 2617 2733 1 1470 689 22 22 484 mult_36 auto 0.61 12056 1.98 4.46928 -2395.54 -4.46928 17594 6535 15216 6003306 1200223 2.50602e+07 1.22409e+07 3.52243e+06 7277.74 24 4.90132 4.90132 -2822.05 -4.90132 0 0 0.97 -hard_fpu_arch_timing.xml raygentop.v common 163.20 0.49 62108 37 96.73 -1 -1 67884 -1 -1 2288 211 -1 -1 v8.0.0-1603-g6c2a712a0 success betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr3/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vpr_verify_rr_graph/run003/hard_fpu_arch_timing.xml/raygentop.v/common 202428 211 305 9804 10109 1 7252 2804 53 53 2809 clb auto 1.57 77422 15.62 21.5689 -5865.79 -21.5689 118461 68308 174469 19262947 1964467 5.87942e+06 5.24453e+06 1.13971e+07 4057.33 30 23.1326 23.1326 -6660.15 -23.1326 -0.0851 -0.0851 4.31 +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml raygentop.v common 21.90 0.28 30792 3 1.26 -1 -1 44536 -1 -1 100 214 0 8 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vpr_verify_rr_graph/run003/k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml/raygentop.v/common 60312 214 305 2963 2869 1 1462 627 19 19 361 io auto 1.73 11150 3.86 0.02 4.38178 -2447.34 -4.38178 4.38178 0.00444291 0.00389586 0.69491 0.607387 19764 5023 12645 3110830 676299 1.72706e+07 8.5574e+06 2.90560e+06 8048.76 18 4.75418 4.75418 -2914.87 -4.75418 0 0 0.81 0.978303 0.869577 +k6_frac_N10_frac_chain_mem32K_40nm.xml raygentop.v common 23.01 0.29 30668 3 1.27 -1 -1 44560 -1 -1 111 214 0 8 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vpr_verify_rr_graph/run003/k6_frac_N10_frac_chain_mem32K_40nm.xml/raygentop.v/common 58484 214 305 2963 2869 1 1440 638 19 19 361 io auto 2.98 10840 3.59 0.02 4.24405 -2504.45 -4.24405 4.24405 0.00438709 0.00386471 0.674195 0.58947 17834 3853 8845 2030233 440229 1.72706e+07 9.15023e+06 2.71656e+06 7525.11 12 4.71655 4.71655 -2851.82 -4.71655 0 0 0.54 0.897195 0.79803 +k6_frac_N10_mem32K_40nm.xml raygentop.v common 22.88 0.31 31664 8 1.95 -1 -1 44568 -1 -1 104 214 0 9 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vpr_verify_rr_graph/run003/k6_frac_N10_mem32K_40nm.xml/raygentop.v/common 60388 214 305 2625 2741 1 1440 632 22 22 484 mult_36 auto 2.12 11598 3.55 0.02 4.45213 -2339.09 -4.45213 4.45213 0.00455045 0.00397957 0.668606 0.583323 18691 3749 8623 2001032 422822 2.50602e+07 9.16898e+06 3.71564e+06 7676.94 13 4.97872 4.97872 -2780.31 -4.97872 0 0 0.55 0.889442 0.787488 +k6_N10_mem32K_40nm.xml raygentop.v common 22.50 0.31 31804 8 1.95 -1 -1 44200 -1 -1 164 214 0 9 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vpr_verify_rr_graph/run003/k6_N10_mem32K_40nm.xml/raygentop.v/common 59476 214 305 2625 2741 1 1482 692 22 22 484 mult_36 auto 0.82 12228 3.86 0.03 4.46596 -2351.27 -4.46596 4.46596 0.00451956 0.00394865 0.601256 0.521127 17611 6615 15185 6956194 1412993 2.50602e+07 1.24026e+07 3.52243e+06 7277.74 35 4.99249 4.99249 -2806.04 -4.99249 0 0 1.55 1.00135 0.883414 +hard_fpu_arch_timing.xml raygentop.v common 241.36 0.52 63944 38 121.48 -1 -1 70304 -1 -1 2217 211 -1 -1 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vpr_verify_rr_graph/run003/hard_fpu_arch_timing.xml/raygentop.v/common 196048 211 305 9491 9796 1 6956 2733 53 53 2809 clb auto 1.89 70714 40.90 0.29 21.018 -5650.98 -21.018 21.018 0.0148842 0.0127338 1.82616 1.46297 109967 68260 174045 18832733 1921895 5.87942e+06 5.0818e+06 1.13971e+07 4057.33 35 22.7127 22.7127 -6315.58 -22.7127 -0.0851 -0.0851 4.91 3.03601 2.49009 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vpr_verify_rr_graph_bidir/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vpr_verify_rr_graph_bidir/config/golden_results.txt index fd9da35b20d..d9f1ad4a362 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vpr_verify_rr_graph_bidir/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vpr_verify_rr_graph_bidir/config/golden_results.txt @@ -1,3 +1,3 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_route_time -k4_n4_v7_bidir.xml dsip.blif common 23.67 -1 -1 -1 -1 -1 -1 -1 -1 -1 390 229 -1 -1 v8.0.0-1603-g6c2a712a0 success betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr3/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vpr_verify_rr_graph_bidir/run003/k4_n4_v7_bidir.xml/dsip.blif/common 94280 229 197 1815 2012 1 1190 816 29 29 841 io auto 0.26 10800 2.22 8.34612 -1903.74 -8.34612 15398 5944 18568 6066939 402099 2.187e+07 1.17e+07 -1 -1 14 9.65079 9.65079 -2410.03 -9.65079 0 0 0.67 -k4_n4_v7_bidir.xml elliptic.blif common 38.63 -1 -1 -1 -1 -1 -1 -1 -1 -1 996 131 -1 -1 v8.0.0-1603-g6c2a712a0 success betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr3/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vpr_verify_rr_graph_bidir/run003/k4_n4_v7_bidir.xml/elliptic.blif/common 143056 131 114 4855 4969 1 2150 1241 34 34 1156 clb auto 0.61 31676 4.57 22.7414 -11960.6 -22.7414 41772 10211 46481 9432724 587952 3.072e+07 2.988e+07 -1 -1 18 28.8701 28.8701 -15382.5 -28.8701 0 0 1.41 +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k4_n4_v7_bidir.xml dsip.blif common 35.18 -1 -1 -1 -1 -1 -1 -1 -1 -1 390 229 -1 -1 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vpr_verify_rr_graph_bidir/run003/k4_n4_v7_bidir.xml/dsip.blif/common 90432 229 197 1815 2012 1 1190 816 29 29 841 io auto 0.30 11403 5.41 0.03 8.34612 -1903.74 -8.34612 8.34612 0.00301294 0.0025095 0.395856 0.333624 15398 5944 18568 6066939 402099 2.187e+07 1.17e+07 -1 -1 14 9.65079 9.65079 -2410.03 -9.65079 0 0 0.90 0.523308 0.447105 +k4_n4_v7_bidir.xml elliptic.blif common 59.87 -1 -1 -1 -1 -1 -1 -1 -1 -1 996 131 -1 -1 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vpr_verify_rr_graph_bidir/run003/k4_n4_v7_bidir.xml/elliptic.blif/common 126244 131 114 4855 4969 1 2150 1241 34 34 1156 clb auto 0.74 32791 10.12 0.07 22.7414 -11960.6 -22.7414 22.7414 0.0067515 0.00569571 0.842137 0.652761 41772 10211 46481 9432724 587952 3.072e+07 2.988e+07 -1 -1 18 28.8701 28.8701 -15382.5 -28.8701 0 0 1.94 1.21763 0.974991 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vpr_verify_rr_graph_complex_switch/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vpr_verify_rr_graph_complex_switch/config/golden_results.txt index a8b6a6bf6c6..9bd2e3d19cc 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vpr_verify_rr_graph_complex_switch/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vpr_verify_rr_graph_complex_switch/config/golden_results.txt @@ -1,2 +1,2 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_route_time -complex_switch/k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml raygentop.v common 25.78 0.31 31396 12 1.43 -1 -1 40708 -1 -1 237 214 0 9 v8.0.0-1603-g6c2a712a0 success betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr3/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vpr_verify_rr_graph_complex_switch/run003/complex_switch/k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml/raygentop.v/common 80812 214 305 2938 3054 1 2192 765 26 26 676 mult_36 auto 0.40 15830 2.38 3.79643 -1875.96 -3.79643 23924 7211 23901 8898703 2538084 3.88769e+06 1.9935e+06 7.17610e+06 10615.5 15 4.06389 4.06389 -2239.91 -4.06389 0 0 1.56 +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time +complex_switch/k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml raygentop.v common 33.90 0.27 31608 12 1.61 -1 -1 44200 -1 -1 238 214 0 9 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vpr_verify_rr_graph_complex_switch/run003/complex_switch/k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml/raygentop.v/common 70692 214 305 2927 3043 1 2181 766 26 26 676 mult_36 auto 0.48 17577 4.94 0.04 3.98034 -1919.91 -3.98034 3.98034 0.00403367 0.00352678 0.506808 0.439147 25522 6489 21870 5246349 1478242 3.88769e+06 1.9974e+06 7.17610e+06 10615.5 14 4.12981 4.12981 -2356.83 -4.12981 0 0 1.23 0.695426 0.612034 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vpr_verify_rr_graph_error_check/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vpr_verify_rr_graph_error_check/config/golden_results.txt index b1c5a6b3d37..7bfb9f84d95 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vpr_verify_rr_graph_error_check/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vpr_verify_rr_graph_error_check/config/golden_results.txt @@ -1,2 +1,2 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_route_time -complex_switch/k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml raygentop.v common 9.47 0.29 31400 12 1.37 -1 -1 40760 -1 -1 237 214 0 9 v8.0.0-1603-g6c2a712a0 success betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr3/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vpr_verify_rr_graph_error_check/run003/complex_switch/k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml/raygentop.v/common 71488 214 305 2938 3054 1 2192 765 26 26 676 mult_36 auto 0.40 15841 2.32 3.96927 -1924.78 -3.96927 24718 8681 28369 7186763 2222298 3.88769e+06 1.9935e+06 3.89335e+06 5759.39 18 4.59938 4.59938 -2333.32 -4.59938 0 0 1.22 +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time +complex_switch/k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml raygentop.v common 15.79 0.29 31604 12 1.55 -1 -1 44496 -1 -1 238 214 0 9 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vpr_verify_rr_graph_error_check/run003/complex_switch/k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml/raygentop.v/common 60400 214 305 2927 3043 1 2181 766 26 26 676 mult_36 auto 0.49 16349 5.24 0.04 3.87995 -1944.58 -3.87995 3.87995 0.00393338 0.00340579 0.52449 0.456474 25185 8664 28508 7577689 2337669 3.88769e+06 1.9974e+06 3.89335e+06 5759.39 17 4.21778 4.21778 -2425.24 -4.21778 0 0 1.81 0.771226 0.679554 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vpr_verify_rr_graph_titan/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vpr_verify_rr_graph_titan/config/golden_results.txt index d0eb25205e4..8cbdbd1947d 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vpr_verify_rr_graph_titan/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vpr_verify_rr_graph_titan/config/golden_results.txt @@ -1,2 +1,2 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_route_time -stratixiv_arch.timing.xml neuron_stratixiv_arch_timing.blif common 1218.67 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 42 -1 -1 v8.0.0-1603-g6c2a712a0 success betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr3/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vpr_verify_rr_graph_titan/run003/stratixiv_arch.timing.xml/neuron_stratixiv_arch_timing.blif/common 3418396 42 35 119888 86875 1 51266 3427 129 96 12384 DSP auto 86.89 569613 209.90 8.03881 -217062 -8.03881 743236 106623 180308 249743317 52164267 0 0 2.43110e+08 19631.0 12 8.40431 8.40431 -274265 -8.40431 0 0 38.65 +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time +stratixiv_arch.timing.xml neuron_stratixiv_arch_timing.blif common 1619.43 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 42 -1 -1 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vpr_verify_rr_graph_titan/run003/stratixiv_arch.timing.xml/neuron_stratixiv_arch_timing.blif/common 2744068 42 35 119888 86875 1 51143 3418 129 96 12384 DSP auto 112.51 588507 373.16 2.19 8.10444 -219398 -8.10444 8.10444 0.264115 0.226856 40.2722 34.1174 744601 106732 181925 249748927 51990281 0 0 2.43094e+08 19629.7 11 8.88207 8.88207 -280470 -8.88207 0 0 44.97 50.8616 43.7937 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vtr_func_formal/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vtr_func_formal/config/golden_results.txt index 445232d8914..e415c75600f 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vtr_func_formal/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vtr_func_formal/config/golden_results.txt @@ -1,3 +1,3 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time -k6_frac_N10_40nm.xml sha.v common 1929.91 0.63 35892 20 527.40 -1 -1 94296 -1 -1 208 38 -1 -1 v8.0.0-1603-g6c2a712a0 success betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr3/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vtr_func_formal/run003/k6_frac_N10_40nm.xml/sha.v/common 74616 38 36 3404 3440 1 1290 282 17 17 289 clb auto 1.67 11961 1.55 11.2442 -3838.09 -11.2442 -1 16788 12 1.21262e+07 1.121e+07 3.33009e+06 11522.8 0.34 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6_frac_N10_40nm.xml stereovision3.v common 1.37 0.05 8720 4 0.11 -1 -1 32996 -1 -1 13 11 -1 -1 v8.0.0-1603-g6c2a712a0 success betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr3/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vtr_func_formal/run003/k6_frac_N10_40nm.xml/stereovision3.v/common 24992 23 30 262 304 2 110 66 6 6 36 clb auto 0.09 360 0.09 2.24318 -154.938 -2.24318 -1 417 9 862304 700622 300248. 8340.23 0.02 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_40nm.xml sha.v common 2534.97 0.73 36496 20 775.90 -1 -1 100396 -1 -1 208 38 -1 -1 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vtr_func_formal/run006/k6_frac_N10_40nm.xml/sha.v/common 66868 38 36 3404 3440 1 1290 282 17 17 289 clb auto 2.06 12055 3.26 0.03 11.2442 -3838.09 -11.2442 11.2442 0.00501589 0.0041315 0.630325 0.503396 -1 16788 12 1.21262e+07 1.121e+07 3.33009e+06 11522.8 0.41 0.901693 0.750424 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml stereovision3.v common 3.21 0.04 8716 4 0.14 -1 -1 37268 -1 -1 13 11 -1 -1 exited with return code 2 v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vtr_func_formal/run006/k6_frac_N10_40nm.xml/stereovision3.v/common 22000 23 29 257 298 2 106 65 6 6 36 clb auto 0.10 341 0.12 0.00 2.33979 -154.184 -2.33979 2.13015 0.000244479 0.000185707 0.036509 0.0284924 -1 380 12 862304 700622 300248. 8340.23 0.02 0.0519872 0.042557 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vtr_reg_netlist_writer/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vtr_reg_netlist_writer/config/golden_results.txt index 135e9986743..6724d7f8d77 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vtr_reg_netlist_writer/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vtr_reg_netlist_writer/config/golden_results.txt @@ -1,5 +1,5 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time -k6_frac_N10_frac_chain_mem32K_40nm.xml or1200.v common 39.94 0.36 40752 8 4.38 -1 -1 43724 -1 -1 252 385 2 1 v8.0.0-1603-g6c2a712a0 success betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr3/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vtr_reg_netlist_writer/run003/k6_frac_N10_frac_chain_mem32K_40nm.xml/or1200.v/common 122648 385 394 4676 4540 1 2422 1034 27 27 729 io auto 6.75 30721 6.89 8.14334 -9286.61 -8.14334 96 47243 43 3.93038e+07 1.50733e+07 4.41327e+06 6053.86 13.88 44156 17 9748 33997 3450207 672662 8.71082 8.71082 -10901.8 -8.71082 0 0 5.51931e+06 7571.08 1.05 -k6_frac_N10_frac_chain_mem32K_40nm.xml sha.v common 259.08 0.64 36328 3 242.24 -1 -1 91616 -1 -1 156 38 0 0 v8.0.0-1603-g6c2a712a0 success betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr3/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vtr_reg_netlist_writer/run003/k6_frac_N10_frac_chain_mem32K_40nm.xml/sha.v/common 76796 38 36 2995 2744 1 1210 230 17 17 289 clb auto 1.85 11128 1.92 8.63389 -2451.33 -8.63389 74 16247 24 1.34605e+07 8.40746e+06 1.29327e+06 4475.00 6.68 15777 23 4883 12799 483157 82370 10.176 10.176 -2919.88 -10.176 0 0 1.62379e+06 5618.64 0.40 -k6_frac_N10_frac_chain_mem32K_40nm.xml boundtop.v common 5.94 0.44 42672 3 0.40 -1 -1 37800 -1 -1 92 142 0 0 v8.0.0-1603-g6c2a712a0 success betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr3/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vtr_reg_netlist_writer/run003/k6_frac_N10_frac_chain_mem32K_40nm.xml/boundtop.v/common 44924 142 192 1071 1141 1 560 426 14 14 196 clb auto 0.63 1696 0.88 2.91391 -445.169 -2.91391 34 3981 14 9.20055e+06 4.95825e+06 429196. 2189.78 1.51 3444 14 1284 2018 93022 25079 3.39108 3.39108 -545.825 -3.39108 0 0 527839. 2693.05 0.08 -k6_frac_N10_frac_chain_mem32K_40nm.xml raygentop.v common 16.09 0.26 30368 3 1.04 -1 -1 40320 -1 -1 107 214 0 8 v8.0.0-1603-g6c2a712a0 success betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr3/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vtr_reg_netlist_writer/run003/k6_frac_N10_frac_chain_mem32K_40nm.xml/raygentop.v/common 75396 214 305 2964 2870 1 1438 634 19 19 361 io auto 2.20 11432 2.33 4.31218 -2475.36 -4.31218 58 24848 40 1.72706e+07 8.93466e+06 1.32779e+06 3678.09 6.46 20523 18 6049 13718 3496664 806645 4.78735 4.78735 -2995.2 -4.78735 0 0 1.69263e+06 4688.74 0.65 +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_frac_chain_mem32K_40nm.xml or1200.v common 50.67 0.38 38884 8 5.06 -1 -1 47308 -1 -1 251 385 2 1 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vtr_reg_netlist_writer/run006/k6_frac_N10_frac_chain_mem32K_40nm.xml/or1200.v/common 93984 385 394 4649 4513 1 2401 1033 27 27 729 io auto 8.93 31026 12.73 0.08 8.30614 -9504.48 -8.30614 8.30614 0.00957184 0.00845055 1.39777 1.20682 92 45002 23 3.93038e+07 1.50194e+07 4.24291e+06 5820.18 13.46 4.32375 3.84483 43089 14 9948 34006 3507858 708010 9.0496 9.0496 -10607.5 -9.0496 0 0 5.38988e+06 7393.52 1.22 0.483442 0.449718 +k6_frac_N10_frac_chain_mem32K_40nm.xml sha.v common 311.25 0.75 36664 3 287.86 -1 -1 95608 -1 -1 156 38 0 0 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vtr_reg_netlist_writer/run006/k6_frac_N10_frac_chain_mem32K_40nm.xml/sha.v/common 62592 38 36 2995 2744 1 1210 230 17 17 289 clb auto 2.42 11166 3.73 0.02 8.63389 -2451.33 -8.63389 8.63389 0.00378499 0.00311613 0.586797 0.466926 64 17062 39 1.34605e+07 8.40746e+06 1.14637e+06 3966.67 8.00 2.59347 2.16111 15901 25 4840 12871 475408 82527 10.2849 10.2849 -3106.96 -10.2849 0 0 1.43435e+06 4963.14 0.49 0.320061 0.284097 +k6_frac_N10_frac_chain_mem32K_40nm.xml boundtop.v common 9.48 0.44 43372 3 0.50 -1 -1 41632 -1 -1 93 142 0 0 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vtr_reg_netlist_writer/run006/k6_frac_N10_frac_chain_mem32K_40nm.xml/boundtop.v/common 38040 142 192 1069 1139 1 566 427 14 14 196 clb auto 0.81 1652 1.39 0.01 2.89629 -433.273 -2.89629 2.89629 0.00156449 0.00140477 0.199527 0.175763 36 4155 27 9.20055e+06 5.01214e+06 447080. 2281.02 2.09 0.653228 0.585223 3316 11 1255 1880 94628 27074 3.53989 3.53989 -536.392 -3.53989 0 0 553089. 2821.88 0.08 0.0591472 0.0557834 +k6_frac_N10_frac_chain_mem32K_40nm.xml raygentop.v common 25.41 0.27 30688 3 1.12 -1 -1 44776 -1 -1 111 214 0 8 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vtr_reg_netlist_writer/run006/k6_frac_N10_frac_chain_mem32K_40nm.xml/raygentop.v/common 64000 214 305 2963 2869 1 1440 638 19 19 361 io auto 2.86 10831 4.23 0.02 4.45643 -2463.21 -4.45643 4.45643 0.00440239 0.00388427 0.670597 0.588254 60 22353 36 1.72706e+07 9.15023e+06 1.37250e+06 3801.94 10.79 2.39222 2.13018 18864 18 5390 12315 2356278 554331 4.68083 4.68083 -2868.47 -4.68083 0 0 1.72840e+06 4787.81 0.62 0.263432 0.244395 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vtr_reg_qor_chain/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vtr_reg_qor_chain/config/golden_results.txt index 400421d96b1..6f5fa226a61 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vtr_reg_qor_chain/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vtr_reg_qor_chain/config/golden_results.txt @@ -1,22 +1,22 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_revision vpr_status hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time -k6_frac_N10_frac_chain_mem32K_40nm.xml arm_core.v common 363.95 1.32 135168 18 71.49 -1 -1 68952 -1 -1 1035 133 40 0 v8.0.0-1603-g6c2a712a0 success betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr3/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vtr_reg_qor_chain/run004/k6_frac_N10_frac_chain_mem32K_40nm.xml/arm_core.v/common 350524 133 179 18548 18330 1 9251 1387 44 44 1936 memory auto 22.10 152121 29.28 17.4482 -251432 -17.4482 104 222897 49 1.12988e+08 7.77019e+07 1.29301e+07 6678.75 174.28 203296 17 36967 135373 71046115 18534152 19.2499 19.2499 -284831 -19.2499 0 0 1.64104e+07 8476.43 21.14 -k6_frac_N10_frac_chain_mem32K_40nm.xml bgm.v common 596.02 11.04 382300 14 241.01 -1 -1 143248 -1 -1 2735 257 0 11 v8.0.0-1603-g6c2a712a0 success betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr3/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vtr_reg_qor_chain/run004/k6_frac_N10_frac_chain_mem32K_40nm.xml/bgm.v/common 687000 257 32 36582 33970 1 19817 3035 63 63 3969 clb auto 56.87 262986 127.20 18.9887 -24255.7 -18.9887 76 404946 29 2.36641e+08 1.51758e+08 2.05973e+07 5189.55 104.41 382686 21 92597 414874 25552838 4184948 21.2902 21.2902 -26763.6 -21.2902 0 0 2.57532e+07 6488.59 12.04 -k6_frac_N10_frac_chain_mem32K_40nm.xml blob_merge.v common 101.85 0.41 51960 5 38.83 -1 -1 59376 -1 -1 620 36 0 0 v8.0.0-1603-g6c2a712a0 success betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr3/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vtr_reg_qor_chain/run004/k6_frac_N10_frac_chain_mem32K_40nm.xml/blob_merge.v/common 181308 36 100 14037 11284 1 3208 756 31 31 961 clb auto 13.60 44352 9.85 13.3005 -2456.24 -13.3005 60 73963 41 5.14688e+07 3.34143e+07 3.85800e+06 4014.56 27.88 64078 15 12267 59048 2389421 313662 14.9619 14.9619 -2799.82 -14.9619 0 0 4.86014e+06 5057.38 1.72 -k6_frac_N10_frac_chain_mem32K_40nm.xml boundtop.v common 6.00 0.47 42644 3 0.40 -1 -1 37880 -1 -1 92 142 0 0 v8.0.0-1603-g6c2a712a0 success betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr3/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vtr_reg_qor_chain/run004/k6_frac_N10_frac_chain_mem32K_40nm.xml/boundtop.v/common 43584 142 192 1071 1141 1 560 426 14 14 196 clb auto 0.67 1696 0.89 2.91391 -445.169 -2.91391 34 3981 14 9.20055e+06 4.95825e+06 429196. 2189.78 1.57 3444 14 1284 2018 93022 25079 3.39108 3.39108 -545.825 -3.39108 0 0 527839. 2693.05 0.08 -k6_frac_N10_frac_chain_mem32K_40nm.xml ch_intrinsics.v common 2.17 0.04 8924 3 0.19 -1 -1 36352 -1 -1 65 99 1 0 v8.0.0-1603-g6c2a712a0 success betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr3/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vtr_reg_qor_chain/run004/k6_frac_N10_frac_chain_mem32K_40nm.xml/ch_intrinsics.v/common 36300 99 130 363 493 1 251 295 12 12 144 clb auto 0.14 635 0.44 1.86439 -198.325 -1.86439 48 1372 10 5.66058e+06 4.05111e+06 394078. 2736.65 0.46 1259 8 580 750 46400 15459 2.4004 2.4004 -228.324 -2.4004 0 0 503203. 3494.47 0.02 -k6_frac_N10_frac_chain_mem32K_40nm.xml diffeq1.v common 8.49 0.03 8516 6 0.15 -1 -1 33728 -1 -1 32 162 0 5 v8.0.0-1603-g6c2a712a0 success betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr3/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vtr_reg_qor_chain/run004/k6_frac_N10_frac_chain_mem32K_40nm.xml/diffeq1.v/common 52800 162 96 1075 884 1 667 295 16 16 256 mult_36 auto 0.34 4712 1.00 15.5225 -1169.15 -15.5225 58 10285 36 1.21132e+07 3.70461e+06 904541. 3533.36 5.21 8556 20 3284 5544 2043129 554084 17.2136 17.2136 -1394.48 -17.2136 0 0 1.15318e+06 4504.63 0.34 -k6_frac_N10_frac_chain_mem32K_40nm.xml diffeq2.v common 11.31 0.03 7776 6 0.09 -1 -1 33336 -1 -1 21 66 0 7 v8.0.0-1603-g6c2a712a0 success betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr3/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vtr_reg_qor_chain/run004/k6_frac_N10_frac_chain_mem32K_40nm.xml/diffeq2.v/common 57756 66 96 866 607 1 547 190 18 18 324 mult_36 auto 0.40 4587 1.07 12.1504 -713.843 -12.1504 58 9945 17 1.57076e+07 3.90377e+06 1.18151e+06 3646.63 7.75 9228 16 3038 6716 2931176 713747 13.3052 13.3052 -828.362 -13.3052 0 0 1.50617e+06 4648.66 0.39 -k6_frac_N10_frac_chain_mem32K_40nm.xml LU8PEEng.v common 543.37 6.78 219884 101 88.05 -1 -1 104192 -1 -1 2196 114 44 8 v8.0.0-1603-g6c2a712a0 success betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr3/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vtr_reg_qor_chain/run004/k6_frac_N10_frac_chain_mem32K_40nm.xml/LU8PEEng.v/common 659328 114 102 38222 33863 1 17915 2464 57 57 3249 clb auto 68.35 230605 100.97 67.8974 -50466.8 -67.8974 98 337087 24 1.92089e+08 1.45633e+08 2.09305e+07 6442.12 223.79 315345 23 67456 257973 38614328 8845452 76.6465 76.6465 -64432.7 -76.6465 0 0 2.65396e+07 8168.55 16.85 -k6_frac_N10_frac_chain_mem32K_40nm.xml LU32PEEng.v common 3305.03 78.24 774576 97 779.73 -1 -1 319220 -1 -1 7491 114 167 32 v8.0.0-1603-g6c2a712a0 success betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr3/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vtr_reg_qor_chain/run004/k6_frac_N10_frac_chain_mem32K_40nm.xml/LU32PEEng.v/common 2147992 114 102 124854 111149 1 59091 7906 102 102 10404 clb auto 221.83 1021773 763.74 68.7353 -327692 -68.7353 124 1400339 42 6.36957e+08 5.07872e+08 8.44220e+07 8114.38 1230.04 1323028 22 213582 894393 215512368 52740904 78.3285 78.3285 -462946 -78.3285 0 0 1.06940e+08 10278.8 83.47 -k6_frac_N10_frac_chain_mem32K_40nm.xml mcml.v common 5396.14 25.40 873988 24 3279.16 -1 -1 372968 -1 -1 7103 36 159 27 v8.0.0-1603-g6c2a712a0 success betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr3/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vtr_reg_qor_chain/run004/k6_frac_N10_frac_chain_mem32K_40nm.xml/mcml.v/common 2363260 36 33 190959 166678 1 61855 7358 100 100 10000 clb auto 207.14 720967 894.93 40.562 -267244 -40.562 144 973829 23 6.13558e+08 4.80599e+08 9.27426e+07 9274.26 791.59 952625 19 224457 572557 97599831 22248863 42.7818 42.7818 -325949 -42.7818 0 0 1.17701e+08 11770.1 41.30 -k6_frac_N10_frac_chain_mem32K_40nm.xml mkDelayWorker32B.v common 56.43 0.71 77248 5 5.82 -1 -1 53112 -1 -1 461 506 44 0 v8.0.0-1603-g6c2a712a0 success betzgrp-wintermute.eecg.utoronto.ca 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102 38265 33906 1 18033 2457 57 57 3249 clb auto 94.93 235242 276.79 1.59 66.1419 -50129 -66.1419 66.1419 0.0869482 0.0742378 12.9005 10.2096 90 351631 30 1.92089e+08 1.45256e+08 1.94366e+07 5982.34 425.92 42.4442 34.0191 323705 21 70572 266553 43895643 9874508 76.0414 76.0414 -65040.3 -76.0414 0 0 2.43249e+07 7486.90 15.46 4.94906 4.28806 +k6_frac_N10_frac_chain_mem32K_40nm.xml LU32PEEng.v common 4768.86 51.34 722808 98 981.33 -1 -1 316020 -1 -1 7515 114 167 32 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vtr_reg_qor_chain/run006/k6_frac_N10_frac_chain_mem32K_40nm.xml/LU32PEEng.v/common 2169316 114 102 124808 111103 1 59282 7930 103 103 10609 clb auto 289.54 1051869 1782.19 10.36 67.6851 -321864 -67.6851 67.6851 0.360413 0.28165 51.2481 40.2567 126 1387159 39 6.46441e+08 5.09165e+08 8.73307e+07 8231.76 1383.05 196.232 158.282 1331628 22 211817 882444 226479177 59572254 77.6696 77.6696 -479560 -77.6696 0 0 1.10400e+08 10406.3 109.75 21.0961 18.1055 +k6_frac_N10_frac_chain_mem32K_40nm.xml mcml.v common 6850.71 28.86 893328 25 3937.74 -1 -1 377780 -1 -1 7054 36 159 27 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vtr_reg_qor_chain/run006/k6_frac_N10_frac_chain_mem32K_40nm.xml/mcml.v/common 2060676 36 33 190611 166330 1 61304 7309 99 99 9801 clb auto 294.79 739446 1989.53 9.52 40.1263 -267398 -40.1263 40.1263 0.292279 0.227166 49.4106 38.6462 144 962044 32 6.00857e+08 4.77959e+08 9.11403e+07 9299.09 395.48 142.586 115.73 942252 21 218273 560443 81668170 15655027 42.9113 42.9113 -330822 -42.9113 0 0 1.15652e+08 11800.0 35.21 15.8022 13.9252 +k6_frac_N10_frac_chain_mem32K_40nm.xml mkDelayWorker32B.v common 98.38 0.76 76404 5 12.17 -1 -1 57068 -1 -1 456 506 45 0 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vtr_reg_qor_chain/run006/k6_frac_N10_frac_chain_mem32K_40nm.xml/mkDelayWorker32B.v/common 271252 506 553 3519 4017 1 3099 1560 50 50 2500 memory auto 5.74 14899 27.27 0.04 6.74817 -1845.46 -6.74817 6.74817 0.013426 0.0118968 2.04496 1.79389 40 23268 17 1.47946e+08 4.92362e+07 7.18436e+06 2873.75 34.97 7.37062 6.65451 22187 15 3766 4900 3558603 899673 7.49548 7.49548 -2222.54 -7.49548 0 0 8.97548e+06 3590.19 1.18 0.634317 0.59348 +k6_frac_N10_frac_chain_mem32K_40nm.xml mkPktMerge.v common 16.34 0.11 16668 2 0.09 -1 -1 38240 -1 -1 29 311 15 0 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vtr_reg_qor_chain/run006/k6_frac_N10_frac_chain_mem32K_40nm.xml/mkPktMerge.v/common 58948 311 156 1019 1160 1 965 511 28 28 784 memory auto 0.63 8153 3.73 0.01 4.22002 -4093.01 -4.22002 4.22002 0.0033575 0.00275479 0.465014 0.383743 36 15206 16 4.25198e+07 9.78293e+06 1.94918e+06 2486.20 5.20 1.23586 1.05423 13885 15 3136 3505 2473167 714186 4.30394 4.30394 -4829.14 -4.30394 0 0 2.40571e+06 3068.51 0.58 0.156611 0.142407 +k6_frac_N10_frac_chain_mem32K_40nm.xml mkSMAdapter4B.v common 29.71 0.25 30608 4 2.14 -1 -1 42000 -1 -1 193 193 5 0 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vtr_reg_qor_chain/run006/k6_frac_N10_frac_chain_mem32K_40nm.xml/mkSMAdapter4B.v/common 61660 193 205 2926 2852 1 1458 596 20 20 400 memory auto 3.57 11221 5.47 0.03 4.8329 -2483.31 -4.8329 4.8329 0.00441457 0.00371156 0.792891 0.656406 50 21365 32 2.07112e+07 1.31415e+07 1.26946e+06 3173.65 12.25 2.36376 2.01426 18013 15 5224 13396 1118810 255533 5.3128 5.3128 -2920.48 -5.3128 0 0 1.63222e+06 4080.54 0.49 0.267965 0.245903 +k6_frac_N10_frac_chain_mem32K_40nm.xml or1200.v common 53.86 0.41 38968 8 6.02 -1 -1 47412 -1 -1 251 385 2 1 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vtr_reg_qor_chain/run006/k6_frac_N10_frac_chain_mem32K_40nm.xml/or1200.v/common 93404 385 394 4649 4513 1 2401 1033 27 27 729 io auto 9.33 31026 13.60 0.08 8.30614 -9504.48 -8.30614 8.30614 0.0142318 0.0132648 1.57823 1.36237 92 45002 23 3.93038e+07 1.50194e+07 4.24291e+06 5820.18 14.39 4.68511 4.15706 43089 14 9948 34006 3507858 708010 9.0496 9.0496 -10607.5 -9.0496 0 0 5.38988e+06 7393.52 1.28 0.497688 0.460864 +k6_frac_N10_frac_chain_mem32K_40nm.xml raygentop.v common 25.58 0.28 30536 3 1.15 -1 -1 44756 -1 -1 111 214 0 8 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vtr_reg_qor_chain/run006/k6_frac_N10_frac_chain_mem32K_40nm.xml/raygentop.v/common 62644 214 305 2963 2869 1 1440 638 19 19 361 io auto 2.85 10831 4.27 0.02 4.45643 -2463.21 -4.45643 4.45643 0.00481418 0.0041691 0.669822 0.586816 60 22353 36 1.72706e+07 9.15023e+06 1.37250e+06 3801.94 10.99 2.41394 2.14441 18864 18 5390 12315 2356278 554331 4.68083 4.68083 -2868.47 -4.68083 0 0 1.72840e+06 4787.81 0.63 0.269293 0.249313 +k6_frac_N10_frac_chain_mem32K_40nm.xml sha.v common 328.42 0.76 36776 3 305.31 -1 -1 95580 -1 -1 156 38 0 0 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vtr_reg_qor_chain/run006/k6_frac_N10_frac_chain_mem32K_40nm.xml/sha.v/common 58164 38 36 2995 2744 1 1210 230 17 17 289 clb auto 2.43 11166 3.76 0.02 8.63389 -2451.33 -8.63389 8.63389 0.00403473 0.0032868 0.597233 0.478882 64 17062 39 1.34605e+07 8.40746e+06 1.14637e+06 3966.67 8.11 2.6512 2.2109 15901 25 4840 12871 475408 82527 10.2849 10.2849 -3106.96 -10.2849 0 0 1.43435e+06 4963.14 0.52 0.338136 0.299708 +k6_frac_N10_frac_chain_mem32K_40nm.xml spree.v common 14.38 0.15 20372 15 0.73 -1 -1 39204 -1 -1 65 45 3 1 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vtr_reg_qor_chain/run006/k6_frac_N10_frac_chain_mem32K_40nm.xml/spree.v/common 42900 45 32 1275 1232 1 827 146 14 14 196 memory auto 2.87 6841 1.81 0.01 9.76234 -6177.51 -9.76234 9.76234 0.00216371 0.00176569 0.348914 0.277349 64 12667 32 9.20055e+06 5.54311e+06 762053. 3888.03 4.32 1.04543 0.857953 11560 17 3499 9467 1909306 471069 11.7144 11.7144 -7378.36 -11.7144 0 0 953435. 4864.47 0.46 0.144686 0.12992 +k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision0.v common 87.17 1.37 114856 5 12.03 -1 -1 74940 -1 -1 704 157 0 0 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vtr_reg_qor_chain/run006/k6_frac_N10_frac_chain_mem32K_40nm.xml/stereovision0.v/common 217956 157 197 23846 21799 1 6676 1058 33 33 1089 clb auto 9.82 41998 23.80 0.14 2.95438 -13454.7 -2.95438 2.95438 0.0275761 0.0209064 3.97924 3.15979 54 66814 43 6.0475e+07 3.79415e+07 3.92475e+06 3604.00 22.04 13.1621 10.6407 58421 14 16522 26572 1054438 205495 3.59416 3.59416 -15755.9 -3.59416 0 0 5.09631e+06 4679.81 1.65 1.44999 1.28633 +k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision1.v common 211.19 1.27 99384 3 66.63 -1 -1 88584 -1 -1 678 115 0 40 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vtr_reg_qor_chain/run006/k6_frac_N10_frac_chain_mem32K_40nm.xml/stereovision1.v/common 250512 115 145 23131 19544 1 9729 978 40 40 1600 mult_36 auto 10.62 77437 34.31 0.18 4.87165 -21699.1 -4.87165 4.87165 0.0256304 0.0212997 4.50413 3.66874 80 131306 49 9.16046e+07 5.23808e+07 8.41679e+06 5260.49 72.90 13.0973 10.7313 114546 17 34319 51727 18662926 3877778 5.17184 5.17184 -24663.9 -5.17184 0 0 1.06125e+07 6632.80 4.48 1.51476 1.34528 +k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision2.v common 779.75 1.60 143880 3 9.13 -1 -1 206168 -1 -1 1653 149 0 324 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vtr_reg_qor_chain/run006/k6_frac_N10_frac_chain_mem32K_40nm.xml/stereovision2.v/common 1250952 149 182 65737 42630 1 35961 2308 104 104 10816 mult_36 auto 34.51 355062 261.76 1.23 15.2766 -65075.8 -15.2766 15.2766 0.0956141 0.0817942 14.3528 12.1557 78 482413 43 6.67561e+08 2.17385e+08 5.81687e+07 5378.03 366.86 50.0813 43.0819 462216 17 118704 138766 36905553 7395549 16.945 16.945 -75211.5 -16.945 0 0 7.36102e+07 6805.68 12.70 4.95282 4.44468 +k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 3.91 0.04 9460 5 0.13 -1 -1 36600 -1 -1 13 11 0 0 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vtr_reg_qor_chain/run006/k6_frac_N10_frac_chain_mem32K_40nm.xml/stereovision3.v/common 26988 11 29 301 308 2 120 53 7 7 49 clb auto 0.33 394 0.16 0.00 2.29162 -154.44 -2.29162 2.05093 0.000276151 0.000210651 0.0387655 0.030311 30 1092 24 1.07788e+06 700622 77114.5 1573.76 0.39 0.132936 0.10824 734 14 475 749 30750 10264 2.73285 2.34233 -177.508 -2.73285 0 0 95414.1 1947.23 0.03 0.0194671 0.017764 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vtr_timing_update_diff/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vtr_timing_update_diff/config/golden_results.txt index d7c783e26db..978877c2b3d 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vtr_timing_update_diff/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vtr_timing_update_diff/config/golden_results.txt @@ -1,2 +1,2 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6_frac_N10_frac_chain_mem32K_40nm.xml LU8PEEng.v common 520.20 4.48 221420 101 63.11 -1 -1 103832 -1 -1 2196 114 44 8 success v8.0.0-2062-g497427a4c release IPO VTR_ASSERT_LEVEL=2 gprof GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-10T16:04:07 betzgrp-wintermute.eecg.utoronto.ca /home/hubingra/master/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vtr_timing_update_diff/run006/k6_frac_N10_frac_chain_mem32K_40nm.xml/LU8PEEng.v/common 491376 114 102 38222 33863 1 17915 2464 57 57 3249 clb auto 82.02 236833 100.23 0.66 70.3072 -52452.5 -70.3072 70.3072 0.124767 0.0898768 17.1378 12.3269 -1 342720 22 1.92089e+08 1.45633e+08 2.12617e+07 6544.09 18.85 24.7182 18.4663 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_frac_chain_mem32K_40nm.xml LU8PEEng.v common 846.03 6.17 212124 101 101.33 -1 -1 108004 -1 -1 2189 114 44 8 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vtr_timing_update_diff/run003/k6_frac_N10_frac_chain_mem32K_40nm.xml/LU8PEEng.v/common 487868 114 102 38265 33906 1 18033 2457 57 57 3249 clb auto 98.66 238440 242.26 1.42 71.2342 -55171.9 -71.2342 71.2342 0.0829218 0.0638184 11.8586 9.39716 -1 343535 23 1.92089e+08 1.45256e+08 2.12617e+07 6544.09 21.73 17.2625 14.0728 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vtr_timing_update_diff_titan/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vtr_timing_update_diff_titan/config/golden_results.txt index 764fd6cfbfb..5f2e0072fb4 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vtr_timing_update_diff_titan/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vtr_timing_update_diff_titan/config/golden_results.txt @@ -1,2 +1,2 @@ -arch circuit script_params vtr_flow_elapsed_time error num_io num_LAB num_DSP num_M9K num_M144K num_PLL vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time -stratixiv_arch.timing.xml neuron_stratixiv_arch_timing.blif common 1207.06 77 3123 89 136 0 0 success v8.0.0-2062-g497427a4c release IPO VTR_ASSERT_LEVEL=2 gprof GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-10T16:04:07 betzgrp-wintermute.eecg.utoronto.ca /home/hubingra/master/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vtr_timing_update_diff_titan/run001/stratixiv_arch.timing.xml/neuron_stratixiv_arch_timing.blif/common 2835708 42 35 119888 86875 1 51283 3425 129 96 12384 DSP auto 95.48 594721 230.50 1.33 7.4259 -77210.5 -6.4259 4.93706 0.53072 0.442149 67.642 55.4784 769712 112462 189175 279340533 60063017 0 0 2.43110e+08 19631.0 13 7.9864 5.61903 -123476 -6.9864 0 0 64.36 87.4876 73.1599 +arch circuit script_params vtr_flow_elapsed_time error num_io num_LAB num_DSP num_M9K num_M144K num_PLL vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time +stratixiv_arch.timing.xml neuron_stratixiv_arch_timing.blif common 1457.47 77 3123 89 136 0 0 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_nightly/vtr_timing_update_diff_titan/run003/stratixiv_arch.timing.xml/neuron_stratixiv_arch_timing.blif/common 2744368 42 35 119888 86875 1 51283 3425 129 96 12384 DSP auto 109.15 617148 352.46 2.32 7.24598 -75907.3 -6.24598 5.78904 0.306291 0.254599 39.4981 32.9766 776820 111898 188031 276475290 58908159 0 0 2.43094e+08 19629.7 13 7.52683 6.29364 -128625 -6.52683 0 0 50.63 51.3691 43.7736 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_absorb_buffers/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_absorb_buffers/config/golden_results.txt index 230b3258bab..a7f0d5c897c 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_absorb_buffers/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_absorb_buffers/config/golden_results.txt @@ -1,3 +1,3 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6_frac_N10_40nm.xml riscv_core_lut6.blif common_--absorb_buffer_luts_on 1.21 -1 -1 -1 -1 -1 -1 -1 -1 -1 84 130 -1 -1 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_absorb_buffers/run011/k6_frac_N10_40nm.xml/riscv_core_lut6.blif/common_--absorb_buffer_luts_on 35720 130 150 1169 1319 1 888 364 12 12 144 clb auto 0.90 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.00185239 0.00152993 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6_frac_N10_40nm.xml riscv_core_lut6.blif common_--absorb_buffer_luts_off 1.15 -1 -1 -1 -1 -1 -1 -1 -1 -1 89 130 -1 -1 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_absorb_buffers/run011/k6_frac_N10_40nm.xml/riscv_core_lut6.blif/common_--absorb_buffer_luts_off 35512 130 150 1216 1366 1 925 369 12 12 144 clb auto 0.79 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.00186601 0.00153509 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_40nm.xml riscv_core_lut6.blif common_--absorb_buffer_luts_on 1.18 -1 -1 -1 -1 -1 -1 -1 -1 -1 84 130 -1 -1 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_absorb_buffers/run008/k6_frac_N10_40nm.xml/riscv_core_lut6.blif/common_--absorb_buffer_luts_on 32664 130 150 1169 1319 1 888 364 12 12 144 clb auto 0.86 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.00250625 0.00218639 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml riscv_core_lut6.blif common_--absorb_buffer_luts_off 1.17 -1 -1 -1 -1 -1 -1 -1 -1 -1 89 130 -1 -1 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_absorb_buffers/run008/k6_frac_N10_40nm.xml/riscv_core_lut6.blif/common_--absorb_buffer_luts_off 32500 130 150 1216 1366 1 925 369 12 12 144 clb auto 0.87 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.00240775 0.00208747 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_analysis_only/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_analysis_only/config/golden_results.txt index 1cf703179b4..a6a8c6394d2 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_analysis_only/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_analysis_only/config/golden_results.txt @@ -1,3 +1,3 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6_N10_mem32K_40nm.xml stereovision3.v common 1.25 0.05 9176 4 0.12 -1 -1 33076 -1 -1 19 11 0 0 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_analysis_only/run014/k6_N10_mem32K_40nm.xml/stereovision3.v/common 28876 11 30 262 292 2 104 60 7 7 49 clb auto 0.08 411 0.09 0.00 2.21827 -167.491 -2.21827 2.12157 0.000337004 0.000269811 0.0361555 0.0278073 476 706 1762 86557 15062 1.07788e+06 1.02399e+06 207176. 4228.08 21 2.37477 2.25251 -178.461 -2.37477 0 0 0.06 0.0536857 0.0427473 -k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 1.41 0.05 9636 5 0.11 -1 -1 33320 -1 -1 14 11 0 0 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_analysis_only/run014/k6_frac_N10_frac_chain_mem32K_40nm.xml/stereovision3.v/common 31048 11 30 313 321 2 117 55 7 7 49 clb auto 0.28 389 0.09 0.00 2.27833 -153.323 -2.27833 2.06764 0.000326252 0.000262622 0.0476506 0.0376635 524 235 443 11245 3448 1.07788e+06 754516 219490. 4479.39 8 2.4554 2.27846 -166.763 -2.4554 0 0 0.02 0.0630713 0.0518124 +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_mem32K_40nm.xml stereovision3.v common 2.79 0.04 9228 4 0.14 -1 -1 37112 -1 -1 18 11 0 0 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_analysis_only/run013/k6_N10_mem32K_40nm.xml/stereovision3.v/common 24576 11 29 257 286 2 102 58 7 7 49 clb auto 0.06 370 0.09 0.00 2.20099 -163.509 -2.20099 2.10428 0.000237748 0.000178884 0.0266272 0.0202162 429 861 1916 96733 17314 1.07788e+06 970092 207176. 4228.08 20 2.22326 2.17156 -175.185 -2.22326 0 0 0.03 0.0437887 0.0351754 +k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 3.06 0.04 9300 5 0.12 -1 -1 36460 -1 -1 13 11 0 0 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_analysis_only/run013/k6_frac_N10_frac_chain_mem32K_40nm.xml/stereovision3.v/common 26388 11 29 301 308 2 120 53 7 7 49 clb auto 0.31 409 0.11 0.00 2.29324 -153.859 -2.29324 2.05363 0.000244051 0.000183444 0.0353832 0.0271441 620 251 401 16466 5063 1.07788e+06 700622 219490. 4479.39 11 2.71041 2.4269 -177.871 -2.71041 0 0 0.02 0.0517563 0.0422036 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_binary/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_binary/config/golden_results.txt index 400056c259e..ec9c2c05b98 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_binary/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_binary/config/golden_results.txt @@ -1,3 +1,3 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6_N10_mem32K_40nm.xml stereovision3.v common_--verify_binary_search_off 1.33 0.05 9464 4 0.14 -1 -1 33008 -1 -1 19 11 0 0 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_binary/run011/k6_N10_mem32K_40nm.xml/stereovision3.v/common_--verify_binary_search_off 29572 11 30 262 292 2 104 60 7 7 49 clb auto 0.08 395 0.12 0.00 2.22041 -166.454 -2.22041 2.11404 0.000290214 0.000229793 0.0333367 0.0257718 22 602 35 1.07788e+06 1.02399e+06 54623.3 1114.76 0.13 0.0858249 0.0689766 598 29 933 2291 84683 24243 2.72583 2.49701 -190.532 -2.72583 0 0 69322.2 1414.74 0.04 0.0207673 0.0175407 -k6_N10_mem32K_40nm.xml stereovision3.v common_--verify_binary_search_on 1.46 0.03 9356 4 0.13 -1 -1 33124 -1 -1 19 11 0 0 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_binary/run011/k6_N10_mem32K_40nm.xml/stereovision3.v/common_--verify_binary_search_on 29508 11 30 262 292 2 104 60 7 7 49 clb auto 0.06 395 0.11 0.00 2.22041 -166.454 -2.22041 2.11404 0.00028622 0.000226844 0.0320311 0.0245901 22 602 35 1.07788e+06 1.02399e+06 54623.3 1114.76 0.26 0.132887 0.106021 598 29 933 2291 84683 24243 2.72583 2.49701 -190.532 -2.72583 0 0 69322.2 1414.74 0.04 0.0205748 0.0173417 +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_mem32K_40nm.xml stereovision3.v common_--verify_binary_search_off 3.13 0.04 9232 4 0.12 -1 -1 37112 -1 -1 18 11 0 0 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_binary/run013/k6_N10_mem32K_40nm.xml/stereovision3.v/common_--verify_binary_search_off 24616 11 29 257 286 2 102 58 7 7 49 clb auto 0.06 364 0.14 0.00 2.20202 -161.339 -2.20202 2.10527 0.000227557 0.00017071 0.027115 0.0206194 18 697 48 1.07788e+06 970092 45686.6 932.380 0.20 0.0802975 0.0643501 502 25 932 2323 76645 24178 2.57826 2.43094 -180.635 -2.57826 0 0 59124.6 1206.62 0.04 0.018272 0.0158041 +k6_N10_mem32K_40nm.xml stereovision3.v common_--verify_binary_search_on 3.40 0.04 9244 4 0.13 -1 -1 37316 -1 -1 18 11 0 0 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_binary/run013/k6_N10_mem32K_40nm.xml/stereovision3.v/common_--verify_binary_search_on 24672 11 29 257 286 2 102 58 7 7 49 clb auto 0.06 364 0.14 0.00 2.20202 -161.339 -2.20202 2.10527 0.000249969 0.000190452 0.0285324 0.0217409 18 697 48 1.07788e+06 970092 45686.6 932.380 0.46 0.131316 0.105122 502 25 932 2323 76645 24178 2.57826 2.43094 -180.635 -2.57826 0 0 59124.6 1206.62 0.04 0.0179541 0.0154687 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_blocks_with_no_inputs/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_blocks_with_no_inputs/config/golden_results.txt index 5cf59b02251..04760044bf5 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_blocks_with_no_inputs/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_blocks_with_no_inputs/config/golden_results.txt @@ -1,9 +1,9 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6_N10_mem32K_40nm.xml ch_intrinsics.v common 11.31 0.10 9044 3 0.41 -1 -1 39980 -1 -1 70 99 1 0 success v8.0.0-2197-g9f118f7a2 release IPO VTR_ASSERT_LEVEL=3 GNU 6.5.0 on Linux-5.6.14-2rodete2-amd64 x86_64 2020-07-17T16:08:52 keithrothman2.svl.corp.google.com /usr/local/google/home/keithrothman/cat_x/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_blocks_with_no_inputs/run001/k6_N10_mem32K_40nm.xml/ch_intrinsics.v/common 71344 99 130 363 493 1 255 300 12 12 144 clb auto 0.23 655 3.49 0.02 2.18412 -208.426 -2.18412 2.18412 0.0168429 0.0156467 1.38585 1.22025 38 1213 28 5.66058e+06 4.32058e+06 306247. 2126.71 3.39 2.94623 2.47815 1113 18 739 1031 114104 39086 2.6714 2.6714 -228.621 -2.6714 0 0 388532. 2698.14 0.28 0.233271 0.0961667 -k6_N10_mem32K_40nm.xml diffeq1.v common 30.65 0.13 8656 15 0.62 -1 -1 38360 -1 -1 52 162 0 5 success v8.0.0-2197-g9f118f7a2 release IPO VTR_ASSERT_LEVEL=3 GNU 6.5.0 on Linux-5.6.14-2rodete2-amd64 x86_64 2020-07-17T16:08:52 keithrothman2.svl.corp.google.com /usr/local/google/home/keithrothman/cat_x/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_blocks_with_no_inputs/run001/k6_N10_mem32K_40nm.xml/diffeq1.v/common 76816 162 96 999 932 1 707 315 16 16 256 mult_36 auto 0.64 5392 6.41 0.02 19.8556 -1716.78 -19.8556 19.8556 0.00777612 0.00755412 2.92766 2.74303 44 11950 42 1.21132e+07 4.78249e+06 665287. 2598.78 16.33 8.30359 7.63854 9499 24 4032 8541 2355345 561334 21.9068 21.9068 -1883.87 -21.9068 0 0 864808. 3378.16 1.16 0.279793 0.248573 -k6_N10_mem32K_40nm.xml single_wire.v common 1.22 0.03 5588 1 0.01 -1 -1 33172 -1 -1 0 1 0 0 success v8.0.0-2197-g9f118f7a2 release IPO VTR_ASSERT_LEVEL=3 GNU 6.5.0 on Linux-5.6.14-2rodete2-amd64 x86_64 2020-07-17T16:08:52 keithrothman2.svl.corp.google.com /usr/local/google/home/keithrothman/cat_x/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_blocks_with_no_inputs/run001/k6_N10_mem32K_40nm.xml/single_wire.v/common 62204 1 1 1 2 0 1 2 3 3 9 -1 auto 0.00 2 0.01 0.00 0.205011 -0.205011 -0.205011 nan 0.00203777 0.00175101 0.00363454 0.00267006 14 5 1 53894 0 3251.56 361.284 0.06 0.0202002 0.00525638 5 1 1 1 23 21 0.515002 nan -0.515002 -0.515002 0 0 4350.07 483.341 0.00 0.000284556 0.000229007 -k6_N10_mem32K_40nm.xml single_ff.v common 1.34 0.01 5556 1 0.01 -1 -1 33340 -1 -1 1 2 0 0 success v8.0.0-2197-g9f118f7a2 release IPO VTR_ASSERT_LEVEL=3 GNU 6.5.0 on Linux-5.6.14-2rodete2-amd64 x86_64 2020-07-17T16:08:52 keithrothman2.svl.corp.google.com /usr/local/google/home/keithrothman/cat_x/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_blocks_with_no_inputs/run001/k6_N10_mem32K_40nm.xml/single_ff.v/common 62660 2 1 3 4 1 3 4 3 3 9 -1 auto 0.00 4 0.01 0.00 0.570641 -0.944653 -0.570641 0.570641 0.00123048 0.000945615 0.0049211 0.0038887 2 3 2 53894 53894 1165.58 129.509 0.04 0.0209083 0.0137863 3 2 4 4 86 48 0.577715 0.577715 -1.04204 -0.577715 0 0 1165.58 129.509 0.00 0.000519317 0.000337559 -k6_N10_mem32K_40nm_i_or_o.xml ch_intrinsics.v common 166.64 0.20 8972 3 0.42 -1 -1 39820 -1 -1 70 99 1 0 success v8.0.0-2197-g9f118f7a2 release IPO VTR_ASSERT_LEVEL=3 GNU 6.5.0 on Linux-5.6.14-2rodete2-amd64 x86_64 2020-07-17T16:08:52 keithrothman2.svl.corp.google.com /usr/local/google/home/keithrothman/cat_x/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_blocks_with_no_inputs/run001/k6_N10_mem32K_40nm_i_or_o.xml/ch_intrinsics.v/common 68196 99 130 363 493 1 255 300 19 19 361 o auto 0.30 792 156.14 0.01 2.14848 -226.623 -2.14848 2.14848 0.00126129 0.00115112 0.827134 0.709591 32 1591 15 1.92828e+07 4.32058e+06 754825. 2090.93 4.59 2.01089 1.65332 1311 14 852 1223 127641 39958 2.48928 2.48928 -252.191 -2.48928 0 0 935064. 2590.20 0.13 0.0733341 0.0635439 -k6_N10_mem32K_40nm_i_or_o.xml diffeq1.v common 41.18 0.13 8776 15 0.55 -1 -1 38532 -1 -1 52 162 0 5 success v8.0.0-2197-g9f118f7a2 release IPO VTR_ASSERT_LEVEL=3 GNU 6.5.0 on Linux-5.6.14-2rodete2-amd64 x86_64 2020-07-17T16:08:52 keithrothman2.svl.corp.google.com /usr/local/google/home/keithrothman/cat_x/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_blocks_with_no_inputs/run001/k6_N10_mem32K_40nm_i_or_o.xml/diffeq1.v/common 84740 162 96 999 932 1 707 315 24 24 576 i auto 0.58 7164 12.84 0.02 20.2809 -1846.99 -20.2809 20.2809 0.0104701 0.0057697 2.88408 2.70228 40 11806 30 3.2214e+07 4.78249e+06 1.47109e+06 2553.97 18.85 7.79402 7.19715 10980 25 4173 9005 3355783 783837 22.0003 22.0003 -2005.62 -22.0003 0 0 1.84580e+06 3204.51 1.77 0.76645 0.692156 -k6_N10_mem32K_40nm_i_or_o.xml single_wire.v common 1.43 0.04 5584 1 0.01 -1 -1 33176 -1 -1 0 1 0 0 success v8.0.0-2197-g9f118f7a2 release IPO VTR_ASSERT_LEVEL=3 GNU 6.5.0 on Linux-5.6.14-2rodete2-amd64 x86_64 2020-07-17T16:08:52 keithrothman2.svl.corp.google.com /usr/local/google/home/keithrothman/cat_x/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_blocks_with_no_inputs/run001/k6_N10_mem32K_40nm_i_or_o.xml/single_wire.v/common 63028 1 1 1 2 0 1 2 4 4 16 i auto 0.02 4 0.02 0.00 0.310441 -0.310441 -0.310441 nan 4.7286e-05 2.42e-05 0.000137975 7.4338e-05 4 5 1 323364 0 1970.29 123.143 0.13 0.00861919 0.00267743 6 1 1 1 32 25 0.484024 nan -0.484024 -0.484024 0 0 3039.08 189.942 0.00 0.000303122 0.000238994 -k6_N10_mem32K_40nm_i_or_o.xml single_ff.v common 1.44 0.02 5548 1 0.01 -1 -1 33176 -1 -1 1 2 0 0 success v8.0.0-2197-g9f118f7a2 release IPO VTR_ASSERT_LEVEL=3 GNU 6.5.0 on Linux-5.6.14-2rodete2-amd64 x86_64 2020-07-17T16:08:52 keithrothman2.svl.corp.google.com /usr/local/google/home/keithrothman/cat_x/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_blocks_with_no_inputs/run001/k6_N10_mem32K_40nm_i_or_o.xml/single_ff.v/common 62508 2 1 3 4 1 3 4 4 4 16 i auto 0.00 6 0.12 0.00 0.59309 -1.03934 -0.59309 0.59309 2.5118e-05 1.1253e-05 0.0854558 0.0370764 8 5 2 323364 53894 4250.52 265.658 0.09 0.0933332 0.0443832 5 2 3 3 89 46 0.594048 0.594048 -1.06808 -0.594048 0 0 5124.99 320.312 0.00 0.00041458 0.000325376 +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_mem32K_40nm.xml ch_intrinsics.v common 4.17 0.03 9024 3 0.21 -1 -1 38004 -1 -1 70 99 1 0 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_blocks_with_no_inputs/run013/k6_N10_mem32K_40nm.xml/ch_intrinsics.v/common 27640 99 130 363 493 1 255 300 12 12 144 clb auto 0.06 655 0.60 0.00 2.18412 -208.426 -2.18412 2.18412 0.000408516 0.000355192 0.052976 0.0463164 38 1213 28 5.66058e+06 4.32058e+06 306247. 2126.71 0.50 0.155481 0.139712 1113 18 739 1031 114104 39086 2.6714 2.6714 -228.621 -2.6714 0 0 388532. 2698.14 0.04 0.0202317 0.0187536 +k6_N10_mem32K_40nm.xml diffeq1.v common 8.60 0.02 8708 15 0.35 -1 -1 38864 -1 -1 52 162 0 5 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_blocks_with_no_inputs/run013/k6_N10_mem32K_40nm.xml/diffeq1.v/common 36960 162 96 999 932 1 707 315 16 16 256 mult_36 auto 0.19 5392 1.49 0.01 19.8556 -1716.78 -19.8556 19.8556 0.00153368 0.00137455 0.199647 0.178477 44 11950 42 1.21132e+07 4.78249e+06 665287. 2598.78 2.91 0.668756 0.608205 9499 24 4032 8541 2355345 561334 21.9068 21.9068 -1883.87 -21.9068 0 0 864808. 3378.16 0.42 0.104557 0.0974134 +k6_N10_mem32K_40nm.xml single_wire.v common 2.18 0.01 5616 1 0.00 -1 -1 32960 -1 -1 0 1 0 0 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_blocks_with_no_inputs/run013/k6_N10_mem32K_40nm.xml/single_wire.v/common 22244 1 1 1 2 0 1 2 3 3 9 -1 auto 0.00 2 0.00 0.00 0.205011 -0.205011 -0.205011 nan 6.841e-06 3.01e-06 3.3404e-05 1.8064e-05 14 5 1 53894 0 3251.56 361.284 0.00 9.9008e-05 5.8441e-05 5 1 1 1 23 21 0.515002 nan -0.515002 -0.515002 0 0 4350.07 483.341 0.00 3.9483e-05 2.4752e-05 +k6_N10_mem32K_40nm.xml single_ff.v common 2.30 0.01 5592 1 0.00 -1 -1 33692 -1 -1 1 2 0 0 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_blocks_with_no_inputs/run013/k6_N10_mem32K_40nm.xml/single_ff.v/common 22304 2 1 3 4 1 3 4 3 3 9 -1 auto 0.00 4 0.00 0.00 0.570641 -0.944653 -0.570641 0.570641 7.041e-06 4.049e-06 4.6684e-05 3.0213e-05 2 2 2 53894 53894 1165.58 129.509 0.00 0.000146492 0.000102563 2 2 3 3 70 44 0.576831 0.576831 -0.957916 -0.576831 0 0 1165.58 129.509 0.00 9.7422e-05 7.2971e-05 +k6_N10_mem32K_40nm_i_or_o.xml ch_intrinsics.v common 55.36 0.03 8988 3 0.20 -1 -1 37636 -1 -1 70 99 1 0 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_blocks_with_no_inputs/run013/k6_N10_mem32K_40nm_i_or_o.xml/ch_intrinsics.v/common 45176 99 130 363 493 1 255 300 19 19 361 o auto 0.07 792 51.15 0.00 2.14848 -226.623 -2.14848 2.14848 0.000415936 0.000367264 0.0513575 0.0451057 32 1591 15 1.92828e+07 4.32058e+06 754825. 2090.93 0.60 0.102839 0.0921833 1311 14 852 1223 127641 39958 2.48928 2.48928 -252.191 -2.48928 0 0 935064. 2590.20 0.03 0.0153321 0.0142596 +k6_N10_mem32K_40nm_i_or_o.xml diffeq1.v common 12.90 0.02 8856 15 0.33 -1 -1 38824 -1 -1 52 162 0 5 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_blocks_with_no_inputs/run013/k6_N10_mem32K_40nm_i_or_o.xml/diffeq1.v/common 64988 162 96 999 932 1 707 315 24 24 576 i auto 0.20 7164 3.68 0.01 20.2809 -1846.99 -20.2809 20.2809 0.00151997 0.00135492 0.217948 0.194528 40 11806 30 3.2214e+07 4.78249e+06 1.47109e+06 2553.97 3.84 0.641504 0.583381 10980 25 4173 9005 3355783 783837 22.0003 22.0003 -2005.62 -22.0003 0 0 1.84580e+06 3204.51 0.56 0.104864 0.097682 +k6_N10_mem32K_40nm_i_or_o.xml single_wire.v common 2.20 0.01 5484 1 0.00 -1 -1 33448 -1 -1 0 1 0 0 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_blocks_with_no_inputs/run013/k6_N10_mem32K_40nm_i_or_o.xml/single_wire.v/common 22176 1 1 1 2 0 1 2 4 4 16 i auto 0.00 4 0.00 0.00 0.310441 -0.310441 -0.310441 nan 5.683e-06 2.962e-06 3.3421e-05 1.7644e-05 4 5 1 323364 0 1970.29 123.143 0.00 0.000107848 6.1272e-05 6 1 1 1 32 25 0.484024 nan -0.484024 -0.484024 0 0 3039.08 189.942 0.00 4.124e-05 2.6204e-05 +k6_N10_mem32K_40nm_i_or_o.xml single_ff.v common 2.25 0.01 5576 1 0.01 -1 -1 33224 -1 -1 1 2 0 0 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_blocks_with_no_inputs/run013/k6_N10_mem32K_40nm_i_or_o.xml/single_ff.v/common 22320 2 1 3 4 1 3 4 4 4 16 i auto 0.00 6 0.00 0.00 0.59309 -1.03934 -0.59309 0.59309 4.27e-06 1.862e-06 0.000288368 0.00013361 8 5 2 323364 53894 4250.52 265.658 0.00 0.000403238 0.000212929 5 2 3 3 89 46 0.594048 0.594048 -1.06808 -0.594048 0 0 5124.99 320.312 0.00 7.7481e-05 5.6804e-05 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_bounding_box/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_bounding_box/config/golden_results.txt index 9bd589c3255..c03c123b88d 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_bounding_box/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_bounding_box/config/golden_results.txt @@ -1,2 +1,2 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6_N10_mem32K_40nm.xml stereovision3.v common 1.28 0.05 9248 4 0.12 -1 -1 33124 -1 -1 19 11 0 0 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_bounding_box/run015/k6_N10_mem32K_40nm.xml/stereovision3.v/common 28704 11 30 262 292 2 104 60 7 7 49 clb auto 0.08 395 0.03 0.00 -1 -1 -1 -1 0 0 0 0 20 695 50 1.07788e+06 1.02399e+06 49980.0 1020.00 0.16 0.0645011 0.0526037 571 26 1026 2494 78614 23220 2.58874 2.37064 -190.862 -2.58874 0 0 65453.8 1335.79 0.04 0.0204325 0.0174085 +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_mem32K_40nm.xml stereovision3.v common 2.94 0.04 9096 4 0.13 -1 -1 36696 -1 -1 18 11 0 0 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_bounding_box/run013/k6_N10_mem32K_40nm.xml/stereovision3.v/common 24340 11 29 257 286 2 102 58 7 7 49 clb auto 0.06 364 0.03 0.00 -1 -1 -1 -1 0 0 0 0 20 601 24 1.07788e+06 970092 49980.0 1020.00 0.13 0.0402147 0.0333605 478 25 861 2087 64587 19191 2.46009 2.33451 -181.614 -2.46009 0 0 65453.8 1335.79 0.03 0.0179701 0.0155259 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_breadth_first/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_breadth_first/config/golden_results.txt index ae2d48a1500..9a974e93f0e 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_breadth_first/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_breadth_first/config/golden_results.txt @@ -1,2 +1,2 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6_N10_mem32K_40nm.xml stereovision3.v common 1.05 0.05 9352 4 0.12 -1 -1 33140 -1 -1 19 11 0 0 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_breadth_first/run015/k6_N10_mem32K_40nm.xml/stereovision3.v/common 28652 11 30 262 292 2 104 60 7 7 49 clb auto 0.09 402 0.09 0.00 2.23968 -167.49 -2.23968 2.12269 0.0003376 0.000271184 0.0410785 0.0318842 519 -1 -1 -1 -1 1.07788e+06 1.02399e+06 207176. 4228.08 9 2.603 2.54078 -189.078 -2.603 0 0 0.03 0.0448481 0.0353861 +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_mem32K_40nm.xml stereovision3.v common 2.75 0.04 9212 4 0.12 -1 -1 36768 -1 -1 18 11 0 0 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_breadth_first/run013/k6_N10_mem32K_40nm.xml/stereovision3.v/common 24292 11 29 257 286 2 102 58 7 7 49 clb auto 0.06 370 0.10 0.00 2.22343 -160.091 -2.22343 2.11498 0.000236187 0.000178362 0.0282376 0.0214795 484 -1 -1 -1 -1 1.07788e+06 970092 207176. 4228.08 9 2.43545 2.33629 -178.533 -2.43545 0 0 0.03 0.0319636 0.0250354 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_check_route_options/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_check_route_options/config/golden_results.txt index 70592e308f9..4db137ff329 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_check_route_options/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_check_route_options/config/golden_results.txt @@ -1,4 +1,4 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time -sub_tiles.xml sub_tiles.blif common_--check_route_full 1.80 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 6 -1 -1 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_check_route_options/run004/sub_tiles.xml/sub_tiles.blif/common_--check_route_full 46088 6 7 19 26 0 19 26 3 3 9 -1 auto 0.00 38 1.37 0.00 3.87729 -27.141 -3.87729 nan 3.5931e-05 2.6291e-05 0.000126829 9.2438e-05 6 19 4 14813.4 192574 -1 -1 0.04 0.000697701 0.000494867 19 2 32 34 5402 2849 3.87729 nan -27.141 -3.87729 0 0 -1 -1 0.00 0.000609721 0.000425509 -sub_tiles.xml sub_tiles.blif common_--check_route_quick 1.80 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 6 -1 -1 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_check_route_options/run004/sub_tiles.xml/sub_tiles.blif/common_--check_route_quick 46144 6 7 19 26 0 19 26 3 3 9 -1 auto 0.00 38 1.40 0.00 3.87729 -27.141 -3.87729 nan 3.4256e-05 2.4869e-05 0.000122996 9.0043e-05 6 19 4 14813.4 192574 -1 -1 0.04 0.00060591 0.00042679 19 2 32 34 5402 2849 3.87729 nan -27.141 -3.87729 0 0 -1 -1 0.00 0.00030006 0.000214753 -sub_tiles.xml sub_tiles.blif common_--check_route_off 1.75 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 6 -1 -1 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_check_route_options/run004/sub_tiles.xml/sub_tiles.blif/common_--check_route_off 46172 6 7 19 26 0 19 26 3 3 9 -1 auto 0.00 38 1.37 0.00 3.87729 -27.141 -3.87729 nan 3.4104e-05 2.4533e-05 0.000123891 8.9864e-05 6 19 4 14813.4 192574 -1 -1 0.04 0.000640294 0.00044823 19 2 32 34 5402 2849 3.87729 nan -27.141 -3.87729 0 0 -1 -1 0.00 0.000243534 0.000170302 +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time +sub_tiles.xml sub_tiles.blif common_--check_route_full 2.41 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 6 -1 -1 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_check_route_options/run008/sub_tiles.xml/sub_tiles.blif/common_--check_route_full 37412 6 7 19 26 0 19 26 3 3 9 -1 auto 0.00 38 2.04 0.00 3.87729 -27.141 -3.87729 nan 1.3236e-05 8.809e-06 7.0803e-05 4.9161e-05 6 19 3 14813.4 192574 -1 -1 0.04 0.00032469 0.000242913 19 3 34 37 5960 3302 3.87729 nan -27.141 -3.87729 0 0 -1 -1 0.00 0.000161598 0.000124822 +sub_tiles.xml sub_tiles.blif common_--check_route_quick 2.41 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 6 -1 -1 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_check_route_options/run008/sub_tiles.xml/sub_tiles.blif/common_--check_route_quick 37216 6 7 19 26 0 19 26 3 3 9 -1 auto 0.00 38 2.04 0.00 3.87729 -27.141 -3.87729 nan 1.3223e-05 8.715e-06 6.8988e-05 4.8165e-05 6 19 3 14813.4 192574 -1 -1 0.04 0.000312642 0.000232614 19 3 34 37 5960 3302 3.87729 nan -27.141 -3.87729 0 0 -1 -1 0.00 0.000155107 0.000119333 +sub_tiles.xml sub_tiles.blif common_--check_route_off 2.41 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 6 -1 -1 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_check_route_options/run008/sub_tiles.xml/sub_tiles.blif/common_--check_route_off 37128 6 7 19 26 0 19 26 3 3 9 -1 auto 0.00 38 2.04 0.00 3.87729 -27.141 -3.87729 nan 1.3045e-05 8.805e-06 7.0537e-05 4.9282e-05 6 19 3 14813.4 192574 -1 -1 0.04 0.000326492 0.000242765 19 3 34 37 5960 3302 3.87729 nan -27.141 -3.87729 0 0 -1 -1 0.00 0.000160309 0.000123893 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_cin_tie_off/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_cin_tie_off/config/golden_results.txt index 21222b332bc..a86082a8cbf 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_cin_tie_off/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_cin_tie_off/config/golden_results.txt @@ -1,3 +1,3 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length -k6_frac_N10_4add_2chains_tie_off_depop50_mem20K_22nm.xml mult_4x4.v common 1.03 0.01 5816 1 0.02 -1 -1 29900 -1 -1 3 9 0 -1 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_cin_tie_off/run015/k6_frac_N10_4add_2chains_tie_off_depop50_mem20K_22nm.xml/mult_4x4.v/common 26016 9 8 71 66 1 37 20 5 5 25 clb auto 0.47 85 0.06 0.00 2.22275 -22.7102 -2.22275 2.22275 0.000143941 0.000119207 0.019139 0.0157608 26 199 19 151211 75605.7 37105.9 1484.24 0.04 0.0304893 0.0250386 166 14 147 195 5055 2690 3.84065 3.84065 -36.0874 -3.84065 0 0 45067.1 1802.68 0.01 0.00348874 0.00302937 14 16 16 6 0 0 -k6_frac_N10_4add_2chains_tie_off_depop50_mem20K_22nm.xml mult_9x9.v common 2.92 0.02 5952 1 0.02 -1 -1 30440 -1 -1 8 19 0 -1 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_cin_tie_off/run015/k6_frac_N10_4add_2chains_tie_off_depop50_mem20K_22nm.xml/mult_9x9.v/common 28404 19 18 299 240 1 150 45 6 6 36 clb auto 1.94 498 0.11 0.00 3.67246 -67.9518 -3.67246 3.67246 0.00027031 0.000219413 0.0391563 0.03287 52 1244 30 403230 201615 110337. 3064.92 0.27 0.118437 0.100608 980 19 973 1386 60799 23055 5.39047 5.39047 -120.052 -5.39047 0 0 143382. 3982.83 0.03 0.0163773 0.0147932 62 81 85 13 0 0 +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length +k6_frac_N10_4add_2chains_tie_off_depop50_mem20K_22nm.xml mult_4x4.v common 2.91 0.01 5612 1 0.01 -1 -1 33656 -1 -1 3 9 0 -1 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_cin_tie_off/run015/k6_frac_N10_4add_2chains_tie_off_depop50_mem20K_22nm.xml/mult_4x4.v/common 23496 9 8 71 66 1 37 20 5 5 25 clb auto 0.52 85 0.03 0.00 2.22275 -22.7102 -2.22275 2.22275 3.7929e-05 2.8209e-05 0.00528182 0.00404792 26 199 19 151211 75605.7 37105.9 1484.24 0.03 0.0124548 0.0101173 166 14 147 195 5055 2690 3.84065 3.84065 -36.0874 -3.84065 0 0 45067.1 1802.68 0.01 0.00288792 0.00263694 14 16 16 6 0 0 +k6_frac_N10_4add_2chains_tie_off_depop50_mem20K_22nm.xml mult_9x9.v common 5.00 0.01 5764 1 0.02 -1 -1 34076 -1 -1 8 19 0 -1 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_cin_tie_off/run015/k6_frac_N10_4add_2chains_tie_off_depop50_mem20K_22nm.xml/mult_9x9.v/common 25560 19 18 299 240 1 150 45 6 6 36 clb auto 2.19 498 0.13 0.00 3.67246 -67.9518 -3.67246 3.67246 0.000158275 0.000118853 0.0236918 0.018718 52 1244 30 403230 201615 110337. 3064.92 0.21 0.0704906 0.0584212 980 19 973 1386 60799 23055 5.39047 5.39047 -120.052 -5.39047 0 0 143382. 3982.83 0.03 0.013568 0.0124424 62 81 85 13 0 0 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_aliases/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_aliases/config/golden_results.txt index 6f371323b68..27ba09d84c0 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_aliases/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_aliases/config/golden_results.txt @@ -1,4 +1,4 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time -timing/k6_N10_40nm.xml clock_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/clk.sdc 0.24 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 1 -1 -1 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_aliases/run009/timing/k6_N10_40nm.xml/clock_aliases.blif/common_-sdc_file_sdc/samples/clock_aliases/clk.sdc 19548 1 4 28 32 2 10 9 4 4 16 clb auto 0.01 20 0.03 0.00 2.18276 0 0 2.18276 6.7283e-05 5.2326e-05 0.00815367 0.00626288 8 20 5 215576 215576 5503.53 343.971 0.03 0.0157619 0.0120416 18 4 19 19 532 233 2.20321 2.20321 0 0 0 0 6317.10 394.819 0.00 0.000982231 0.000821075 -timing/k6_N10_40nm.xml clock_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/clk_assign.sdc 0.19 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 1 -1 -1 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_aliases/run009/timing/k6_N10_40nm.xml/clock_aliases.blif/common_-sdc_file_sdc/samples/clock_aliases/clk_assign.sdc 19656 1 4 28 32 2 10 9 4 4 16 clb auto 0.00 20 0.02 0.00 2.18276 0 0 2.18276 4.6786e-05 3.6598e-05 0.00472127 0.00352975 8 20 5 215576 215576 5503.53 343.971 0.02 0.00917158 0.00685601 18 4 19 19 532 233 2.20321 2.20321 0 0 0 0 6317.10 394.819 0.00 0.00126981 0.00106383 -timing/k6_N10_40nm.xml clock_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/counter_clk.sdc 0.20 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 1 -1 -1 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_aliases/run009/timing/k6_N10_40nm.xml/clock_aliases.blif/common_-sdc_file_sdc/samples/clock_aliases/counter_clk.sdc 19500 1 4 28 32 2 10 9 4 4 16 clb auto 0.01 20 0.02 0.00 2.18276 0 0 2.18276 6.3783e-05 4.9035e-05 0.00495275 0.00373809 8 20 5 215576 215576 5503.53 343.971 0.02 0.00973133 0.00733373 18 4 19 19 532 233 2.20321 2.20321 0 0 0 0 6317.10 394.819 0.00 0.000838713 0.000702013 +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time +timing/k6_N10_40nm.xml clock_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/clk.sdc 0.16 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 1 -1 -1 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_aliases/run008/timing/k6_N10_40nm.xml/clock_aliases.blif/common_-sdc_file_sdc/samples/clock_aliases/clk.sdc 18124 1 4 28 32 2 10 9 4 4 16 clb auto 0.00 20 0.01 0.00 2.18276 0 0 2.18276 1.6717e-05 1.1363e-05 0.00176891 0.00120854 8 20 5 215576 215576 5503.53 343.971 0.01 0.00399922 0.0029634 18 4 19 19 532 233 2.20321 2.20321 0 0 0 0 6317.10 394.819 0.00 0.000614944 0.00055416 +timing/k6_N10_40nm.xml clock_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/clk_assign.sdc 0.14 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 1 -1 -1 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_aliases/run008/timing/k6_N10_40nm.xml/clock_aliases.blif/common_-sdc_file_sdc/samples/clock_aliases/clk_assign.sdc 18032 1 4 28 32 2 10 9 4 4 16 clb auto 0.00 20 0.01 0.00 2.18276 0 0 2.18276 1.6645e-05 1.1352e-05 0.00176576 0.00121679 8 20 5 215576 215576 5503.53 343.971 0.01 0.00397789 0.00296083 18 4 19 19 532 233 2.20321 2.20321 0 0 0 0 6317.10 394.819 0.00 0.00062457 0.000562172 +timing/k6_N10_40nm.xml clock_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/counter_clk.sdc 0.14 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 1 -1 -1 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_aliases/run008/timing/k6_N10_40nm.xml/clock_aliases.blif/common_-sdc_file_sdc/samples/clock_aliases/counter_clk.sdc 18288 1 4 28 32 2 10 9 4 4 16 clb auto 0.00 20 0.01 0.00 2.18276 0 0 2.18276 1.6599e-05 1.1184e-05 0.00175924 0.00119942 8 20 5 215576 215576 5503.53 343.971 0.01 0.00398773 0.00294998 18 4 19 19 532 233 2.20321 2.20321 0 0 0 0 6317.10 394.819 0.00 0.000612632 0.000551937 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_aliases_set_delay/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_aliases_set_delay/config/golden_results.txt index b1454517013..b04e3ad0022 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_aliases_set_delay/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_aliases_set_delay/config/golden_results.txt @@ -1,2 +1,2 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time -timing/k6_N10_40nm.xml clock_set_delay_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/set_delay.sdc 0.13 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 2 -1 -1 success v8.0.0-2368-g3c56542c2-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-111-generic x86_64 2020-08-07T14:08:33 goeders-ssh0 /home/shadtorrie/git/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_aliases_set_delay/run116/timing/k6_N10_40nm.xml/clock_set_delay_aliases.blif/common_-sdc_file_sdc/samples/clock_aliases/set_delay.sdc 8512 2 2 22 24 2 4 6 4 4 16 clb auto 0.01 4 0.01 0.00 1.293 0 0 1.293 1.181e-05 8.064e-06 0.000109995 9.1012e-05 6 20 2 215576 107788 3924.73 245.296 0.01 0.000804665 0.000648399 7 2 3 3 135 78 1.293 1.293 0 0 0 0 5503.53 343.971 0.00 0.000288477 0.000259906 +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time +timing/k6_N10_40nm.xml clock_set_delay_aliases.blif common_-sdc_file_sdc/samples/clock_aliases/set_delay.sdc 0.13 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 2 -1 -1 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_aliases_set_delay/run008/timing/k6_N10_40nm.xml/clock_set_delay_aliases.blif/common_-sdc_file_sdc/samples/clock_aliases/set_delay.sdc 18212 2 2 22 24 2 4 6 4 4 16 clb auto 0.00 4 0.01 0.00 1.293 0 0 1.293 1.7588e-05 1.1678e-05 0.000152727 0.000124357 6 20 2 215576 107788 3924.73 245.296 0.00 0.00056973 0.000485717 7 2 3 3 135 78 1.293 1.293 0 0 0 0 5503.53 343.971 0.00 0.000363957 0.000323264 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_modeling/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_modeling/config/golden_results.txt index 9acd474a6e5..5ae3d962551 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_modeling/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_modeling/config/golden_results.txt @@ -1,9 +1,9 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_global_nets num_routed_nets -timing/k6_N10_40nm.xml microbenchmarks/d_flip_flop.v common_--clock_modeling_ideal_--route_chan_width_60 0.23 0.00 5132 1 0.01 -1 -1 29836 -1 -1 1 2 -1 -1 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_modeling/run014/timing/k6_N10_40nm.xml/microbenchmarks/d_flip_flop.v/common_--clock_modeling_ideal_--route_chan_width_60 18736 2 1 3 4 1 3 4 3 3 9 -1 auto 0.00 4 0.00 0.00 0.571526 -0.946421 -0.571526 0.571526 1.7441e-05 1.149e-05 7.1145e-05 4.8641e-05 -1 2 3 53894 53894 12370.0 1374.45 0.00 0.000254072 0.000169134 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 2 -timing/k6_N10_40nm.xml microbenchmarks/d_flip_flop.v common_--clock_modeling_route_--route_chan_width_60 0.22 0.00 5088 1 0.00 -1 -1 29712 -1 -1 1 2 -1 -1 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_modeling/run014/timing/k6_N10_40nm.xml/microbenchmarks/d_flip_flop.v/common_--clock_modeling_route_--route_chan_width_60 18828 2 1 3 4 1 3 4 3 3 9 -1 auto 0.00 6 0.00 0.00 0.526189 -0.94819 -0.526189 0.526189 2.6654e-05 1.7791e-05 0.000101225 7.076e-05 -1 5 2 53894 53894 14028.3 1558.70 0.00 0.000323996 0.00021954 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 3 -timing/k6_N10_40nm.xml verilog/mkPktMerge.v common_--clock_modeling_ideal_--route_chan_width_60 3.22 0.25 52116 2 0.91 -1 -1 50852 -1 -1 155 5 -1 -1 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_modeling/run014/timing/k6_N10_40nm.xml/verilog/mkPktMerge.v/common_--clock_modeling_ideal_--route_chan_width_60 26512 5 156 191 347 1 163 316 15 15 225 clb auto 0.04 22 0.16 0.00 1.10064 -11.4028 -1.10064 1.10064 0.00018189 0.000157805 0.0168641 0.0144931 -1 38 4 9.10809e+06 8.35357e+06 828754. 3683.35 0.00 0.0200693 0.0173657 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 154 9 -timing/k6_N10_40nm.xml verilog/mkPktMerge.v common_--clock_modeling_route_--route_chan_width_60 3.20 0.32 52072 2 0.99 -1 -1 50968 -1 -1 155 5 -1 -1 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_modeling/run014/timing/k6_N10_40nm.xml/verilog/mkPktMerge.v/common_--clock_modeling_route_--route_chan_width_60 26700 5 156 191 347 1 163 316 15 15 225 clb auto 0.05 25 0.11 0.00 1.08173 -11.7171 -1.08173 1.08173 0.000168376 0.000145799 0.0118848 0.0101721 -1 53 5 9.10809e+06 8.35357e+06 858153. 3814.01 0.01 0.0153738 0.0132187 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 153 10 -timing/k6_N10_mem32K_40nm.xml microbenchmarks/d_flip_flop.v common_--clock_modeling_ideal_--route_chan_width_60 0.29 0.02 5524 1 0.01 -1 -1 29668 -1 -1 1 2 0 0 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_modeling/run014/timing/k6_N10_mem32K_40nm.xml/microbenchmarks/d_flip_flop.v/common_--clock_modeling_ideal_--route_chan_width_60 24540 2 1 3 4 1 3 4 3 3 9 -1 auto 0.00 4 0.00 0.00 0.571526 -0.946421 -0.571526 0.571526 2.2399e-05 1.4995e-05 0.000108559 7.325e-05 -1 2 3 53894 53894 12370.0 1374.45 0.00 0.000326066 0.00021689 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 2 -timing/k6_N10_mem32K_40nm.xml microbenchmarks/d_flip_flop.v common_--clock_modeling_route_--route_chan_width_60 0.27 0.01 5604 1 0.01 -1 -1 29632 -1 -1 1 2 0 0 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_modeling/run014/timing/k6_N10_mem32K_40nm.xml/microbenchmarks/d_flip_flop.v/common_--clock_modeling_route_--route_chan_width_60 24584 2 1 3 4 1 3 4 3 3 9 -1 auto 0.00 6 0.00 0.00 0.526189 -0.94819 -0.526189 0.526189 1.666e-05 1.0936e-05 6.8312e-05 4.7081e-05 -1 5 2 53894 53894 14028.3 1558.70 0.00 0.000220808 0.000149648 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 3 -timing/k6_N10_mem32K_40nm.xml verilog/mkPktMerge.v common_--clock_modeling_ideal_--route_chan_width_60 4.05 0.13 16332 2 0.08 -1 -1 33604 -1 -1 32 311 15 0 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_modeling/run014/timing/k6_N10_mem32K_40nm.xml/verilog/mkPktMerge.v/common_--clock_modeling_ideal_--route_chan_width_60 52004 311 156 972 1128 1 953 514 28 28 784 memory auto 0.32 8018 1.16 0.01 3.83829 -4111.97 -3.83829 3.83829 0.00233626 0.00199214 0.349669 0.293018 -1 12414 17 4.25198e+07 9.94461e+06 2.96205e+06 3778.13 0.81 0.474833 0.406689 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 15 938 -timing/k6_N10_mem32K_40nm.xml verilog/mkPktMerge.v common_--clock_modeling_route_--route_chan_width_60 4.59 0.12 16324 2 0.09 -1 -1 33564 -1 -1 32 311 15 0 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_modeling/run014/timing/k6_N10_mem32K_40nm.xml/verilog/mkPktMerge.v/common_--clock_modeling_route_--route_chan_width_60 52228 311 156 972 1128 1 953 514 28 28 784 memory auto 0.33 8012 1.39 0.01 4.15843 -3579.44 -4.15843 4.15843 0.00258934 0.00213737 0.40798 0.337577 -1 12768 17 4.25198e+07 9.94461e+06 3.02951e+06 3864.17 1.00 0.53661 0.454871 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 14 939 +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_global_nets num_routed_nets +timing/k6_N10_40nm.xml microbenchmarks/d_flip_flop.v common_--clock_modeling_ideal_--route_chan_width_60 2.17 0.00 5056 1 0.00 -1 -1 33344 -1 -1 1 2 -1 -1 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_modeling/run013/timing/k6_N10_40nm.xml/microbenchmarks/d_flip_flop.v/common_--clock_modeling_ideal_--route_chan_width_60 17736 2 1 3 4 1 3 4 3 3 9 -1 auto 0.00 4 0.00 0.00 0.571526 -0.946421 -0.571526 0.571526 6.529e-06 3.651e-06 4.4168e-05 2.8785e-05 -1 2 3 53894 53894 12370.0 1374.45 0.00 0.000133798 8.9656e-05 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 2 +timing/k6_N10_40nm.xml microbenchmarks/d_flip_flop.v common_--clock_modeling_route_--route_chan_width_60 2.17 0.00 5016 1 0.01 -1 -1 33540 -1 -1 1 2 -1 -1 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_modeling/run013/timing/k6_N10_40nm.xml/microbenchmarks/d_flip_flop.v/common_--clock_modeling_route_--route_chan_width_60 17628 2 1 3 4 1 3 4 3 3 9 -1 auto 0.00 6 0.00 0.00 0.526189 -0.94819 -0.526189 0.526189 6.697e-06 3.806e-06 4.6154e-05 3.01e-05 -1 4 2 53894 53894 14028.3 1558.70 0.00 0.00031213 0.000268575 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 3 +timing/k6_N10_40nm.xml verilog/mkPktMerge.v common_--clock_modeling_ideal_--route_chan_width_60 4.92 0.21 54128 2 1.02 -1 -1 54128 -1 -1 155 5 -1 -1 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_modeling/run013/timing/k6_N10_40nm.xml/verilog/mkPktMerge.v/common_--clock_modeling_ideal_--route_chan_width_60 22580 5 156 191 347 1 163 316 15 15 225 clb auto 0.03 22 0.10 0.00 1.10064 -11.4028 -1.10064 1.10064 0.000164142 0.000143902 0.00873563 0.0076383 -1 38 4 9.10809e+06 8.35357e+06 828754. 3683.35 0.00 0.0117656 0.0104674 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 154 9 +timing/k6_N10_40nm.xml verilog/mkPktMerge.v common_--clock_modeling_route_--route_chan_width_60 4.88 0.21 54128 2 1.03 -1 -1 53872 -1 -1 155 5 -1 -1 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_modeling/run013/timing/k6_N10_40nm.xml/verilog/mkPktMerge.v/common_--clock_modeling_route_--route_chan_width_60 22592 5 156 191 347 1 163 316 15 15 225 clb auto 0.03 25 0.12 0.00 1.08173 -11.7171 -1.08173 1.08173 0.000151742 0.000132747 0.0105557 0.00919997 -1 53 5 9.10809e+06 8.35357e+06 858153. 3814.01 0.01 0.0138526 0.0122684 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 153 10 +timing/k6_N10_mem32K_40nm.xml microbenchmarks/d_flip_flop.v common_--clock_modeling_ideal_--route_chan_width_60 2.16 0.01 5480 1 0.00 -1 -1 33056 -1 -1 1 2 0 0 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_modeling/run013/timing/k6_N10_mem32K_40nm.xml/microbenchmarks/d_flip_flop.v/common_--clock_modeling_ideal_--route_chan_width_60 21820 2 1 3 4 1 3 4 3 3 9 -1 auto 0.00 4 0.00 0.00 0.571526 -0.946421 -0.571526 0.571526 5.359e-06 2.777e-06 4.3366e-05 2.8297e-05 -1 2 3 53894 53894 12370.0 1374.45 0.00 0.000133538 9.0261e-05 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 2 +timing/k6_N10_mem32K_40nm.xml microbenchmarks/d_flip_flop.v common_--clock_modeling_route_--route_chan_width_60 2.12 0.01 5640 1 0.01 -1 -1 33532 -1 -1 1 2 0 0 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_modeling/run013/timing/k6_N10_mem32K_40nm.xml/microbenchmarks/d_flip_flop.v/common_--clock_modeling_route_--route_chan_width_60 21816 2 1 3 4 1 3 4 3 3 9 -1 auto 0.00 6 0.00 0.00 0.526189 -0.94819 -0.526189 0.526189 6.632e-06 3.782e-06 5.3476e-05 3.6471e-05 -1 4 2 53894 53894 14028.3 1558.70 0.00 0.00014541 0.000100282 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 3 +timing/k6_N10_mem32K_40nm.xml verilog/mkPktMerge.v common_--clock_modeling_ideal_--route_chan_width_60 6.68 0.09 16596 2 0.09 -1 -1 37576 -1 -1 32 311 15 0 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_modeling/run013/timing/k6_N10_mem32K_40nm.xml/verilog/mkPktMerge.v/common_--clock_modeling_ideal_--route_chan_width_60 46500 311 156 972 1128 1 953 514 28 28 784 memory auto 0.37 8018 1.81 0.01 3.83829 -4111.97 -3.83829 3.83829 0.00268208 0.00224874 0.401769 0.336002 -1 12414 17 4.25198e+07 9.94461e+06 2.96205e+06 3778.13 0.81 0.535741 0.457522 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 15 938 +timing/k6_N10_mem32K_40nm.xml verilog/mkPktMerge.v common_--clock_modeling_route_--route_chan_width_60 6.74 0.09 16496 2 0.07 -1 -1 37260 -1 -1 32 311 15 0 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_modeling/run013/timing/k6_N10_mem32K_40nm.xml/verilog/mkPktMerge.v/common_--clock_modeling_route_--route_chan_width_60 46668 311 156 972 1128 1 953 514 28 28 784 memory auto 0.38 8012 1.76 0.01 4.15843 -3579.44 -4.15843 4.15843 0.00267 0.00223568 0.391158 0.328634 -1 12768 17 4.25198e+07 9.94461e+06 3.02951e+06 3864.17 0.91 0.52447 0.449532 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 14 939 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_pll/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_pll/config/golden_results.txt index d983f4b783d..79d24bd232d 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_pll/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_pll/config/golden_results.txt @@ -1,3 +1,3 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6_frac_N10_mem32K_40nm_clk_pll_valid.xml multiclock_buf.blif common 0.43 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 8 0 0 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_pll/run004/k6_frac_N10_mem32K_40nm_clk_pll_valid.xml/multiclock_buf.blif/common 25580 8 4 25 28 5 19 19 6 6 36 clb auto 0.28 33 0.02 0.00 1.2518 -5.38119 -1.2518 0.545 3.9051e-05 2.9422e-05 0.00485776 0.00345104 88 18 18 1374 518 431152 215576 56755.0 1576.53 2 1.72803 0.545 -7.04473 -1.72803 -0.669015 -0.398071 0.00 0.00545285 0.00391538 -k6_frac_N10_mem32K_40nm_clk_pll_invalid.xml multiclock_buf.blif common 0.05 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 exited with return code 1 v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_pll/run004/k6_frac_N10_mem32K_40nm_clk_pll_invalid.xml/multiclock_buf.blif/common 17160 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_mem32K_40nm_clk_pll_valid.xml multiclock_buf.blif common 0.44 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 8 0 0 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_pll/run008/k6_frac_N10_mem32K_40nm_clk_pll_valid.xml/multiclock_buf.blif/common 22796 8 4 25 28 5 19 19 6 6 36 clb auto 0.32 33 0.01 0.00 1.2518 -5.38119 -1.2518 0.545 1.6516e-05 1.1232e-05 0.00215042 0.0013604 88 18 18 1374 518 431152 215576 56755.0 1576.53 2 1.72803 0.545 -7.04473 -1.72803 -0.669015 -0.398071 0.00 0.0025917 0.00172845 +k6_frac_N10_mem32K_40nm_clk_pll_invalid.xml multiclock_buf.blif common 0.03 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 exited with return code 1 v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_clock_pll/run008/k6_frac_N10_mem32K_40nm_clk_pll_invalid.xml/multiclock_buf.blif/common 16556 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_constant_outputs/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_constant_outputs/config/golden_results.txt index 47a59b4a85f..13eb11d7d5d 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_constant_outputs/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_constant_outputs/config/golden_results.txt @@ -1,2 +1,2 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6_N10_mem32K_40nm.xml constant_outputs_only.blif common 0.24 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 0 0 0 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_constant_outputs/run015/k6_N10_mem32K_40nm.xml/constant_outputs_only.blif/common 25076 -1 2 2 4 0 2 4 4 4 16 clb auto 0.00 0 0.01 0.00 nan 0 0 nan 1.3744e-05 8.231e-06 6.572e-05 4.2352e-05 2 0 1 107788 107788 1342.00 83.8749 0.01 0.000188746 0.000121875 0 1 0 0 0 0 nan nan 0 0 0 0 1342.00 83.8749 0.00 0.000109803 7.5671e-05 +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_mem32K_40nm.xml constant_outputs_only.blif common 0.17 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 0 0 0 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_constant_outputs/run008/k6_N10_mem32K_40nm.xml/constant_outputs_only.blif/common 22252 -1 2 2 4 0 2 4 4 4 16 clb auto 0.00 0 0.01 0.00 nan 0 0 nan 5.451e-06 2.399e-06 3.7219e-05 2.2226e-05 2 0 1 107788 107788 1342.00 83.8749 0.00 0.000104788 6.8398e-05 0 1 0 0 0 0 nan nan 0 0 0 0 1342.00 83.8749 0.00 4.6498e-05 3.1739e-05 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_grid/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_grid/config/golden_results.txt index b68393c4b96..08c6ac552d7 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_grid/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_grid/config/golden_results.txt @@ -1,9 +1,9 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time -fixed_grid.xml raygentop.v common 32.14 0.34 30692 3 1.15 -1 -1 40444 -1 -1 107 214 0 8 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_grid/run015/fixed_grid.xml/raygentop.v/common 79440 214 305 2964 2870 1 1438 634 25 25 625 -1 25x25 2.14 12433 2.85 0.01 4.27896 -2529.83 -4.27896 4.27896 0.00310914 0.00268943 0.473982 0.4021 50 27096 39 3.19446e+07 8.93466e+06 2.03477e+06 3255.63 20.78 2.07927 1.82354 22100 20 7309 16834 4662790 1022693 4.87864 4.87864 -2997.81 -4.87864 0 0 2.70140e+06 4322.25 0.81 0.210053 0.19299 -column_io.xml raygentop.v common 16.28 0.31 30576 3 1.08 -1 -1 40404 -1 -1 107 214 0 8 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_grid/run015/column_io.xml/raygentop.v/common 73260 214 305 2964 2870 1 1438 634 25 25 625 io auto 2.11 11453 2.49 0.01 4.49554 -2526.95 -4.49554 4.49554 0.00304143 0.00264159 0.409192 0.34743 52 25238 32 2.82259e+07 8.93466e+06 1.94438e+06 3111.01 5.87 1.3259 1.16988 21443 16 5916 12766 3066686 667810 4.88861 4.88861 -3042.94 -4.88861 0 0 2.55773e+06 4092.38 0.53 0.178769 0.166464 -multiwidth_blocks.xml raygentop.v common 15.70 0.38 30632 3 1.26 -1 -1 40500 -1 -1 107 214 0 8 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_grid/run015/multiwidth_blocks.xml/raygentop.v/common 67544 214 305 2964 2870 1 1438 634 19 19 361 io clb auto 2.19 10759 2.30 0.01 4.33368 -2452.19 -4.33368 4.33368 0.00304881 0.00265461 0.458839 0.391485 66 22580 50 1.65001e+07 8.93466e+06 1.25644e+06 3480.44 5.85 1.47914 1.30527 19187 14 5762 12949 4054788 991646 4.85255 4.85255 -2921.26 -4.85255 0 0 1.57029e+06 4349.83 0.70 0.175554 0.164092 -non_column.xml raygentop.v common 34.36 0.34 30864 3 1.04 -1 -1 40524 -1 -1 107 214 0 8 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_grid/run015/non_column.xml/raygentop.v/common 98700 214 305 2964 2870 1 1438 634 33 33 1089 io auto 2.12 13674 3.76 0.01 4.4409 -2597.8 -4.4409 4.4409 0.00286403 0.00250291 0.422186 0.358431 42 32841 48 5.44432e+07 8.93466e+06 2.65355e+06 2436.68 21.40 1.92776 1.68935 25196 24 8281 18643 4750391 1157127 5.14301 5.14301 -3217.38 -5.14301 0 0 3.33682e+06 3064.11 0.84 0.228471 0.210195 -non_column_tall_aspect_ratio.xml raygentop.v common 22.75 0.34 30836 3 1.14 -1 -1 40524 -1 -1 107 214 0 8 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_grid/run015/non_column_tall_aspect_ratio.xml/raygentop.v/common 99468 214 305 2964 2870 1 1438 634 23 46 1058 io auto 2.07 13161 3.74 0.01 4.53129 -2590.45 -4.53129 4.53129 0.00293991 0.00255505 0.426191 0.361146 48 28227 43 5.05849e+07 8.93466e+06 3.02110e+06 2855.48 9.68 1.52391 1.34245 22800 16 6240 14099 3206151 774400 5.24897 5.24897 -3134.25 -5.24897 0 0 3.85688e+06 3645.44 0.60 0.191899 0.177672 -non_column_wide_aspect_ratio.xml raygentop.v common 24.94 0.39 30912 3 1.10 -1 -1 40428 -1 -1 107 214 0 8 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_grid/run015/non_column_wide_aspect_ratio.xml/raygentop.v/common 94324 214 305 2964 2870 1 1438 634 43 22 946 io auto 2.32 13891 3.53 0.01 4.43985 -2787.05 -4.43985 4.43985 0.00311606 0.00270965 0.42392 0.359652 46 29178 37 4.55909e+07 8.93466e+06 2.54300e+06 2688.17 11.87 1.37639 1.20633 23948 19 6853 15830 3958847 942808 5.14016 5.14016 -3266.42 -5.14016 0 0 3.26968e+06 3456.32 0.77 0.204084 0.188245 -custom_sbloc.xml raygentop.v common 14.51 0.37 30684 3 1.14 -1 -1 40424 -1 -1 107 214 0 8 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_grid/run015/custom_sbloc.xml/raygentop.v/common 67116 214 305 2964 2870 1 1438 634 19 19 361 io clb auto 2.09 10923 2.20 0.01 4.37821 -2527.54 -4.37821 4.37821 0.00299357 0.00255811 0.448137 0.379618 64 23396 48 1.65001e+07 8.93466e+06 1.19565e+06 3312.06 4.89 1.25479 1.09924 19687 17 5978 13180 3973491 953556 4.82034 4.82034 -3060.92 -4.82034 0 0 1.50465e+06 4168.01 0.64 0.1864 0.17368 -multiple_io_types.xml raygentop.v common 168.17 0.35 30676 3 1.03 -1 -1 40524 -1 -1 107 214 0 8 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_grid/run015/multiple_io_types.xml/raygentop.v/common 418024 214 305 2964 2870 1 1438 634 67 67 4489 io_left auto 2.64 38230 28.16 0.01 6.79184 -4560.73 -6.79184 6.79184 0.00289183 0.00248393 0.470717 0.396242 54 52339 48 2.48753e+08 8.93466e+06 1.32429e+07 2950.07 119.61 1.90407 1.67449 47802 13 6253 13980 6759458 1620836 7.06436 7.06436 -4977.72 -7.06436 0 0 1.71824e+07 3827.68 1.01 0.151637 0.141993 +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time +fixed_grid.xml raygentop.v common 24.12 0.25 30576 3 1.05 -1 -1 44724 -1 -1 111 214 0 8 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_grid/run015/fixed_grid.xml/raygentop.v/common 67968 214 305 2963 2869 1 1440 638 25 25 625 -1 25x25 2.79 11823 4.43 0.02 4.20109 -2559.97 -4.20109 4.20109 0.00398059 0.0035058 0.594507 0.521336 48 26472 48 3.19446e+07 9.15023e+06 1.97188e+06 3155.02 9.01 1.79476 1.60686 21639 17 6323 13963 4257751 943131 4.74865 4.74865 -3075.57 -4.74865 0 0 2.52596e+06 4041.53 0.78 0.22069 0.206301 +column_io.xml raygentop.v common 21.68 0.26 30644 3 1.00 -1 -1 44696 -1 -1 111 214 0 8 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_grid/run015/column_io.xml/raygentop.v/common 67044 214 305 2963 2869 1 1440 638 25 25 625 io auto 2.75 11086 3.86 0.02 4.46209 -2486.32 -4.46209 4.46209 0.00366679 0.00321121 0.489202 0.428073 52 25265 32 2.82259e+07 9.15023e+06 1.94438e+06 3111.01 7.52 1.56962 1.40422 20771 18 5648 12575 3186979 695927 4.99978 4.99978 -2922.86 -4.99978 0 0 2.55773e+06 4092.38 0.64 0.231509 0.216002 +multiwidth_blocks.xml raygentop.v common 18.46 0.25 30684 3 0.98 -1 -1 44564 -1 -1 111 214 0 8 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_grid/run015/multiwidth_blocks.xml/raygentop.v/common 59592 214 305 2963 2869 1 1440 638 19 19 361 io clb auto 2.71 10875 3.91 0.02 4.39313 -2533.87 -4.39313 4.39313 0.00367743 0.00321717 0.561156 0.490533 66 23605 41 1.65001e+07 9.15023e+06 1.25644e+06 3480.44 5.23 1.51923 1.35563 19962 21 6378 14747 3762504 951115 4.7137 4.7137 -2945.67 -4.7137 0 0 1.57029e+06 4349.83 0.75 0.254223 0.236253 +non_column.xml raygentop.v common 25.79 0.34 30800 3 0.97 -1 -1 44464 -1 -1 111 214 0 8 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_grid/run015/non_column.xml/raygentop.v/common 91168 214 305 2963 2869 1 1440 638 33 33 1089 io auto 2.73 12646 5.13 0.02 4.42704 -2538.33 -4.42704 4.42704 0.00371305 0.0032465 0.509852 0.446772 48 27237 45 5.44432e+07 9.15023e+06 3.01743e+06 2770.83 8.77 1.68926 1.51314 22375 22 6700 15214 4036701 971565 5.12134 5.12134 -3015.32 -5.12134 0 0 3.86350e+06 3547.75 0.81 0.25476 0.236536 +non_column_tall_aspect_ratio.xml raygentop.v common 24.30 0.34 30832 3 0.97 -1 -1 44600 -1 -1 111 214 0 8 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_grid/run015/non_column_tall_aspect_ratio.xml/raygentop.v/common 89836 214 305 2963 2869 1 1440 638 23 46 1058 io auto 2.70 12635 4.99 0.02 4.30105 -2686.97 -4.30105 4.30105 0.003695 0.00322027 0.50315 0.439932 52 24502 44 5.05849e+07 9.15023e+06 3.21889e+06 3042.43 7.45 1.66713 1.49333 22103 20 6939 16379 4736093 1180899 4.85803 4.85803 -3245.26 -4.85803 0 0 4.23218e+06 4000.17 0.88 0.246313 0.22945 +non_column_wide_aspect_ratio.xml raygentop.v common 24.06 0.35 30752 3 0.98 -1 -1 44952 -1 -1 111 214 0 8 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_grid/run015/non_column_wide_aspect_ratio.xml/raygentop.v/common 86364 214 305 2963 2869 1 1440 638 43 22 946 io auto 2.76 13910 4.95 0.02 4.56584 -2789.95 -4.56584 4.56584 0.0038809 0.00339034 0.54709 0.478769 48 27844 42 4.55909e+07 9.15023e+06 2.64263e+06 2793.48 7.40 1.75229 1.56384 22980 17 6298 14412 3304256 805641 4.98866 4.98866 -3262.59 -4.98866 0 0 3.38205e+06 3575.11 0.78 0.253463 0.235965 +custom_sbloc.xml raygentop.v common 19.82 0.25 30548 3 0.97 -1 -1 44664 -1 -1 111 214 0 8 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_grid/run015/custom_sbloc.xml/raygentop.v/common 58980 214 305 2963 2869 1 1440 638 19 19 361 io clb auto 2.70 10997 3.80 0.02 4.46787 -2561.46 -4.46787 4.46787 0.00380839 0.00333763 0.566167 0.495531 64 23072 46 1.65001e+07 9.15023e+06 1.19565e+06 3312.06 6.62 1.59436 1.42189 19905 15 6126 13862 5176138 1212334 4.84148 4.84148 -3047.38 -4.84148 0 0 1.50465e+06 4168.01 0.87 0.205506 0.192626 +multiple_io_types.xml raygentop.v common 134.41 0.25 30604 3 0.97 -1 -1 44892 -1 -1 111 214 0 8 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_grid/run015/multiple_io_types.xml/raygentop.v/common 410104 214 305 2963 2869 1 1440 638 67 67 4489 io_left auto 3.25 37050 30.78 0.01 5.38629 -4371.06 -5.38629 5.38629 0.00358075 0.00312624 0.54769 0.478222 46 53400 36 2.48753e+08 9.15023e+06 1.14498e+07 2550.63 81.06 1.61465 1.44048 47679 17 7366 16415 7588008 1735768 5.91175 5.91175 -4814.2 -5.91175 0 0 1.47872e+07 3294.09 1.17 0.198447 0.185403 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_pin_locs/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_pin_locs/config/golden_results.txt index 3166a11066d..563a4e8fdd4 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_pin_locs/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_pin_locs/config/golden_results.txt @@ -1,2 +1,2 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6_frac_N10_mem32K_40nm_custom_pins.xml ch_intrinsics.v common 2.39 0.04 8916 3 0.27 -1 -1 36220 -1 -1 65 99 1 0 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_pin_locs/run015/k6_frac_N10_mem32K_40nm_custom_pins.xml/ch_intrinsics.v/common 36108 99 130 363 493 1 251 295 12 12 144 clb auto 0.12 633 0.48 0.00 2.00656 -201.062 -2.00656 2.00656 0.000405159 0.000350221 0.0537882 0.0463387 50 1406 15 5.66058e+06 4.05111e+06 423042. 2937.80 0.50 0.144363 0.127655 1316 10 578 760 65734 22502 2.47507 2.47507 -237.488 -2.47507 0 0 561550. 3899.65 0.04 0.0217154 0.0199903 +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_mem32K_40nm_custom_pins.xml ch_intrinsics.v common 4.15 0.03 8944 3 0.21 -1 -1 37888 -1 -1 65 99 1 0 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_pin_locs/run015/k6_frac_N10_mem32K_40nm_custom_pins.xml/ch_intrinsics.v/common 29664 99 130 363 493 1 251 295 12 12 144 clb auto 0.10 633 0.56 0.00 2.00656 -201.062 -2.00656 2.00656 0.000380692 0.000331016 0.0504683 0.0441059 50 1406 15 5.66058e+06 4.05111e+06 423042. 2937.80 0.54 0.143131 0.12883 1299 10 586 744 54420 19218 2.45758 2.45758 -238.141 -2.45758 0 0 542351. 3766.33 0.03 0.0149402 0.0140997 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_switch_block/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_switch_block/config/golden_results.txt index 33d40f9ef9b..e7e52e00e3e 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_switch_block/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_switch_block/config/golden_results.txt @@ -1,2 +1,2 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml ch_intrinsics.v common 2.28 0.04 8840 4 0.19 -1 -1 33940 -1 -1 75 99 1 0 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_switch_block/run015/k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml/ch_intrinsics.v/common 36036 99 130 378 508 1 307 305 15 15 225 memory auto 0.04 805 0.38 0.00 1.48585 -153.891 -1.48585 1.48585 0.000417369 0.000361723 0.0624584 0.0535332 1265 695 1705 233724 60603 1.16234e+06 375248 2.18283e+06 9701.45 18 1.86698 1.86698 -178.287 -1.86698 -0.0308982 -0.0308982 0.05 0.0803599 0.0696521 +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml ch_intrinsics.v common 4.56 0.03 8792 4 0.22 -1 -1 39936 -1 -1 75 99 1 0 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_custom_switch_block/run015/k4_N8_topology-0.85sL2-0.15gL4-on-cb-off-sb_22nm_22nm.xml/ch_intrinsics.v/common 31036 99 130 378 508 1 307 305 15 15 225 memory auto 0.04 805 0.50 0.00 1.48585 -153.891 -1.48585 1.48585 0.000427673 0.000372982 0.055545 0.0486032 1265 695 1705 233724 60603 1.16234e+06 375248 2.18283e+06 9701.45 18 1.86698 1.86698 -178.287 -1.86698 -0.0308982 -0.0308982 0.06 0.0755467 0.0669975 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_dedicated_clock/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_dedicated_clock/config/golden_results.txt index 50eef810267..5f99f108602 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_dedicated_clock/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_dedicated_clock/config/golden_results.txt @@ -1,4 +1,4 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_global_nets num_routed_nets -timing/k6_frac_N10_frac_chain_mem32K_htree0_40nm.xml verilog/mkPktMerge.v common_--clock_modeling_dedicated_network 14.17 0.12 16360 2 0.10 -1 -1 34244 -1 -1 29 311 15 0 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_dedicated_clock/run015/timing/k6_frac_N10_frac_chain_mem32K_htree0_40nm.xml/verilog/mkPktMerge.v/common_--clock_modeling_dedicated_network 71668 311 156 1019 1160 1 965 511 28 28 784 memory auto 0.49 8249 2.68 0.01 4.06259 -3369.31 -4.06259 4.06259 0.00239796 0.002034 0.342229 0.283615 36 15880 24 4.25198e+07 9.78293e+06 1.97160e+06 2514.80 5.63 0.95166 0.824493 13986 16 3061 3486 4980323 2134077 4.66801 4.66801 -4358.27 -4.66801 -426.967 -1.41574 2.42825e+06 3097.26 1.74 0.113561 0.10334 15 950 -timing/k6_frac_N10_frac_chain_mem32K_htree0_routedCLK_40nm.xml verilog/mkPktMerge.v common_--clock_modeling_dedicated_network 13.97 0.09 16356 2 0.12 -1 -1 34376 -1 -1 29 311 15 0 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_dedicated_clock/run015/timing/k6_frac_N10_frac_chain_mem32K_htree0_routedCLK_40nm.xml/verilog/mkPktMerge.v/common_--clock_modeling_dedicated_network 73024 311 156 1019 1160 1 965 511 28 28 784 memory auto 0.49 8216 2.73 0.01 3.87435 -3448.99 -3.87435 3.87435 0.00259015 0.00209923 0.369649 0.306293 36 15614 20 4.25198e+07 9.78293e+06 2.00618e+06 2558.90 5.74 0.994123 0.859995 13962 15 3531 4036 3370681 961715 4.1019 4.1019 -4151.44 -4.1019 -238.207 -1.50963 2.47848e+06 3161.33 1.34 0.108281 0.0984048 15 950 -timing/k6_frac_N10_frac_chain_mem32K_htree0short_40nm.xml verilog/mkPktMerge.v common_--clock_modeling_dedicated_network 14.52 0.09 16428 2 0.12 -1 -1 34384 -1 -1 29 311 15 0 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_dedicated_clock/run015/timing/k6_frac_N10_frac_chain_mem32K_htree0short_40nm.xml/verilog/mkPktMerge.v/common_--clock_modeling_dedicated_network 73400 311 156 1019 1160 1 965 511 28 28 784 memory auto 0.56 8117 2.44 0.01 3.8524 -3651.42 -3.8524 3.8524 0.00221509 0.0018317 0.324477 0.268193 40 16634 25 4.25198e+07 9.78293e+06 2.15085e+06 2743.43 5.93 0.926307 0.801747 15345 15 2987 3412 5488063 2593602 5.42665 5.42665 -4393.57 -5.42665 -1602.53 -3.37364 2.68809e+06 3428.68 1.98 0.105948 0.0966677 15 950 +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_global_nets num_routed_nets +timing/k6_frac_N10_frac_chain_mem32K_htree0_40nm.xml verilog/mkPktMerge.v common_--clock_modeling_dedicated_network 17.62 0.09 16568 2 0.08 -1 -1 38292 -1 -1 29 311 15 0 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_dedicated_clock/run015/timing/k6_frac_N10_frac_chain_mem32K_htree0_40nm.xml/verilog/mkPktMerge.v/common_--clock_modeling_dedicated_network 69428 311 156 1019 1160 1 965 511 28 28 784 memory auto 0.58 8249 3.33 0.01 4.06259 -3369.31 -4.06259 4.06259 0.0028288 0.00236554 0.401509 0.337946 36 15776 35 4.25198e+07 9.78293e+06 1.97160e+06 2514.80 6.34 1.15795 1.00967 14077 14 3084 3570 5047247 2142504 4.66801 4.66801 -4353.93 -4.66801 -429.499 -1.41574 2.42825e+06 3097.26 1.85 0.117758 0.10788 15 950 +timing/k6_frac_N10_frac_chain_mem32K_htree0_routedCLK_40nm.xml verilog/mkPktMerge.v common_--clock_modeling_dedicated_network 17.27 0.09 16800 2 0.09 -1 -1 38216 -1 -1 29 311 15 0 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_dedicated_clock/run015/timing/k6_frac_N10_frac_chain_mem32K_htree0_routedCLK_40nm.xml/verilog/mkPktMerge.v/common_--clock_modeling_dedicated_network 68552 311 156 1019 1160 1 965 511 28 28 784 memory auto 0.63 8216 3.33 0.01 3.87435 -3448.99 -3.87435 3.87435 0.002742 0.00222378 0.387634 0.325732 36 15587 36 4.25198e+07 9.78293e+06 2.00618e+06 2558.90 6.33 1.17357 1.02192 13959 16 3545 4023 3238570 921164 4.1019 4.1019 -4162.17 -4.1019 -244.739 -1.50963 2.47848e+06 3161.33 1.41 0.129699 0.119008 15 950 +timing/k6_frac_N10_frac_chain_mem32K_htree0short_40nm.xml verilog/mkPktMerge.v common_--clock_modeling_dedicated_network 18.21 0.10 16668 2 0.07 -1 -1 38044 -1 -1 29 311 15 0 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_dedicated_clock/run015/timing/k6_frac_N10_frac_chain_mem32K_htree0short_40nm.xml/verilog/mkPktMerge.v/common_--clock_modeling_dedicated_network 70980 311 156 1019 1160 1 965 511 28 28 784 memory auto 0.61 8117 3.34 0.01 3.8524 -3651.42 -3.8524 3.8524 0.00302465 0.00261879 0.448138 0.383998 40 16606 30 4.25198e+07 9.78293e+06 2.15085e+06 2743.43 6.67 1.29329 1.14439 15331 15 3121 3561 5541998 2613243 5.30904 5.30904 -4325.58 -5.30904 -1548.28 -3.23864 2.68809e+06 3428.68 2.04 0.123977 0.113676 15 950 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_default_fc_pinlocs/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_default_fc_pinlocs/config/golden_results.txt index b331eaebf71..208d05417d8 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_default_fc_pinlocs/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_default_fc_pinlocs/config/golden_results.txt @@ -1,2 +1,2 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k4_N4_90nm_default_fc_pinloc.xml diffeq.blif common 7.35 -1 -1 -1 -1 -1 -1 -1 -1 -1 417 64 -1 -1 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_default_fc_pinlocs/run014/k4_N4_90nm_default_fc_pinloc.xml/diffeq.blif/common 52868 64 39 1935 1974 1 1104 520 23 23 529 clb auto 0.26 10194 1.93 0.01 6.5862 -1367.76 -6.5862 6.5862 0.0017261 0.00134038 0.240938 0.175852 24 12158 27 983127 929624 797780. 1508.09 3.02 0.561167 0.43501 11171 19 7079 24040 1692224 422101 6.8984 6.8984 -1482.36 -6.8984 0 0 1.04508e+06 1975.57 0.46 0.112933 0.095172 +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k4_N4_90nm_default_fc_pinloc.xml diffeq.blif common 9.02 -1 -1 -1 -1 -1 -1 -1 -1 -1 417 64 -1 -1 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_default_fc_pinlocs/run008/k4_N4_90nm_default_fc_pinloc.xml/diffeq.blif/common 44572 64 39 1935 1974 1 1104 520 23 23 529 clb auto 0.29 10329 3.02 0.02 6.5862 -1367.76 -6.5862 6.5862 0.00197152 0.00158666 0.229382 0.182333 24 12158 27 983127 929624 797780. 1508.09 3.50 0.569584 0.466288 11171 19 7079 24040 1692224 422101 6.8984 6.8984 -1482.36 -6.8984 0 0 1.04508e+06 1975.57 0.57 0.116412 0.101007 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_depop/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_depop/config/golden_results.txt index b7312a7c8bc..7d8d59aa706 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_depop/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_depop/config/golden_results.txt @@ -1,2 +1,2 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml mkSMAdapter4B.v common 21.85 0.36 30924 4 1.78 -1 -1 39832 -1 -1 167 193 5 0 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_depop/run015/k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml/mkSMAdapter4B.v/common 72028 193 205 2926 2852 1 1371 570 20 20 400 memory auto 1.43 10454 2.79 0.01 4.17962 -2464.62 -4.17962 4.17962 0.00387448 0.00316113 0.547803 0.442993 80 20576 38 2.07112e+07 1.17403e+07 2.10510e+06 5262.74 11.79 1.91781 1.6406 18693 16 5010 14283 1459244 324974 4.84767 4.84767 -2845.86 -4.84767 -12.6591 -0.360359 2.64606e+06 6615.15 0.35 0.182318 0.167841 +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml mkSMAdapter4B.v common 20.94 0.22 30568 4 1.79 -1 -1 41884 -1 -1 167 193 5 0 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_depop/run014/k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml/mkSMAdapter4B.v/common 65308 193 205 2926 2852 1 1371 570 20 20 400 memory auto 1.58 10767 4.68 0.03 4.38764 -2424.87 -4.38764 4.38764 0.00382762 0.00319792 0.58895 0.488599 76 21689 42 2.07112e+07 1.17403e+07 2.02110e+06 5052.76 6.91 1.7197 1.47734 20197 17 5498 15422 1697659 365914 4.80242 4.80242 -2890.94 -4.80242 -6.70715 -0.340786 2.51807e+06 6295.18 0.53 0.247678 0.228541 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_detailed_timing/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_detailed_timing/config/golden_results.txt index 93b763f1be2..ab1b17d3a25 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_detailed_timing/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_detailed_timing/config/golden_results.txt @@ -1,2 +1,2 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common 2.24 0.05 8984 3 0.20 -1 -1 36332 -1 -1 65 99 1 0 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_detailed_timing/run014/k6_frac_N10_mem32K_40nm.xml/ch_intrinsics.v/common 35616 99 130 363 493 1 251 295 12 12 144 clb auto 0.12 624 0.46 0.00 1.94344 -198.852 -1.94344 1.94344 0.000400353 0.00034645 0.0554696 0.0477651 50 1398 19 5.66058e+06 4.05111e+06 406292. 2821.48 0.49 0.148872 0.131874 1368 9 565 725 73444 24903 2.56877 2.56877 -239.947 -2.56877 0 0 539112. 3743.83 0.03 0.0133877 0.0124567 +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common 4.33 0.03 9016 3 0.21 -1 -1 37848 -1 -1 65 99 1 0 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_detailed_timing/run013/k6_frac_N10_mem32K_40nm.xml/ch_intrinsics.v/common 29376 99 130 363 493 1 251 295 12 12 144 clb auto 0.10 624 0.60 0.00 1.94344 -198.852 -1.94344 1.94344 0.000417352 0.000363387 0.0549382 0.0481283 50 1398 19 5.66058e+06 4.05111e+06 406292. 2821.48 0.58 0.154971 0.139643 1334 9 570 753 58756 20655 2.42731 2.42731 -236.701 -2.42731 0 0 520805. 3616.70 0.03 0.014708 0.0138978 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_eblif_vpr/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_eblif_vpr/config/golden_results.txt index 7f1f4a26028..1cf5db3985d 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_eblif_vpr/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_eblif_vpr/config/golden_results.txt @@ -1,3 +1,3 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6_frac_N10_40nm.xml test_eblif.eblif common 0.12 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 3 -1 -1 success v8.0.0-2368-g3c56542c2-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-111-generic x86_64 2020-08-07T14:08:33 goeders-ssh0 /home/shadtorrie/git/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_eblif_vpr/run119/k6_frac_N10_40nm.xml/test_eblif.eblif/common 8832 3 1 5 6 1 4 5 3 3 9 -1 auto 0.00 6 0.00 0.00 0.544641 -0.918653 -0.544641 0.544641 4.815e-06 2.731e-06 3.8107e-05 2.655e-05 20 10 1 53894 53894 4880.82 542.314 0.00 0.000144243 0.000104436 14 2 4 4 76 62 1.21985 1.21985 -1.76449 -1.21985 0 0 6579.40 731.044 0.00 6.8754e-05 5.3143e-05 -k6_frac_N10_40nm.xml conn_order.eblif common 0.12 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 2 -1 -1 success v8.0.0-2368-g3c56542c2-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-111-generic x86_64 2020-08-07T14:08:33 goeders-ssh0 /home/shadtorrie/git/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_eblif_vpr/run119/k6_frac_N10_40nm.xml/conn_order.eblif/common 8752 2 1 4 5 1 3 4 3 3 9 -1 auto 0.00 4 0.00 0.00 0.709011 -1.25365 -0.709011 0.709011 4.339e-06 2.328e-06 3.3398e-05 2.2701e-05 20 11 1 53894 53894 4880.82 542.314 0.00 0.000128923 9.2203e-05 19 1 2 2 66 59 2.01453 2.01453 -2.56006 -2.01453 0 0 6579.40 731.044 0.00 5.915e-05 4.6654e-05 +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_40nm.xml test_eblif.eblif common 0.13 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 3 -1 -1 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_eblif_vpr/run008/k6_frac_N10_40nm.xml/test_eblif.eblif/common 18312 3 1 5 6 1 4 5 3 3 9 -1 auto 0.00 6 0.00 0.00 0.544641 -0.918653 -0.544641 0.544641 7.614e-06 4.616e-06 5.2436e-05 3.5691e-05 20 10 1 53894 53894 4880.82 542.314 0.00 0.000162724 0.000117791 14 2 4 4 76 62 1.21985 1.21985 -1.76449 -1.21985 0 0 6579.40 731.044 0.00 9.2266e-05 7.1433e-05 +k6_frac_N10_40nm.xml conn_order.eblif common 0.11 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 2 -1 -1 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_eblif_vpr/run008/k6_frac_N10_40nm.xml/conn_order.eblif/common 18252 2 1 4 5 1 3 4 3 3 9 -1 auto 0.00 4 0.00 0.00 0.709011 -1.25365 -0.709011 0.709011 7.126e-06 4.129e-06 5.2231e-05 3.589e-05 20 11 1 53894 53894 4880.82 542.314 0.00 0.000157934 0.000115443 19 1 2 2 66 59 2.01453 2.01453 -2.56006 -2.01453 0 0 6579.40 731.044 0.00 8.6793e-05 6.9073e-05 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_eblif_vpr_write/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_eblif_vpr_write/config/golden_results.txt index fe9e0078589..6f6ea4fe44b 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_eblif_vpr_write/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_eblif_vpr_write/config/golden_results.txt @@ -1,2 +1,2 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time -arch.xml eblif_write.eblif common 0.17 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 -1 -1 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_eblif_vpr_write/run014/arch.xml/eblif_write.eblif/common 18544 3 2 5 7 1 5 7 4 4 16 ff_tile io_tile auto 0.00 8 0.01 0.00 0.188362 -0.633245 -0.188362 0.188362 6.543e-05 5.807e-05 0.00141955 0.000897781 2 8 3 59253.6 29626.8 -1 -1 0.01 0.00285527 0.00183743 8 3 6 6 122 69 0.249819 0.249819 -0.756538 -0.249819 0 0 -1 -1 0.00 0.000215509 0.000140858 +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time +arch.xml eblif_write.eblif common 0.12 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 -1 -1 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_eblif_vpr_write/run008/arch.xml/eblif_write.eblif/common 17368 3 2 5 7 1 5 7 4 4 16 ff_tile io_tile auto 0.00 8 0.00 0.00 0.188362 -0.633245 -0.188362 0.188362 7.251e-06 3.512e-06 0.000575021 0.00029175 2 8 3 59253.6 29626.8 -1 -1 0.01 0.00117828 0.000682408 8 3 6 6 122 69 0.249819 0.249819 -0.756538 -0.249819 0 0 -1 -1 0.00 9.5894e-05 6.8673e-05 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_echo_files/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_echo_files/config/golden_results.txt index 1e91e93e525..a9bf70cf5ea 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_echo_files/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_echo_files/config/golden_results.txt @@ -1,2 +1,2 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6_N10_mem32K_40nm.xml stereovision3.v common 1.13 0.05 9256 4 0.13 -1 -1 33092 -1 -1 19 11 0 0 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_echo_files/run015/k6_N10_mem32K_40nm.xml/stereovision3.v/common 27508 11 30 262 292 2 104 60 7 7 49 clb auto 0.09 393 0.13 0.00 2.23968 -171.108 -2.23968 2.13287 0.000286003 0.000229733 0.0321467 0.0249497 -1 476 25 1.07788e+06 1.02399e+06 90369.8 1844.28 0.03 0.0513387 0.04117 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_mem32K_40nm.xml stereovision3.v common 2.78 0.04 9276 4 0.12 -1 -1 36876 -1 -1 18 11 0 0 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_echo_files/run013/k6_N10_mem32K_40nm.xml/stereovision3.v/common 24108 11 29 257 286 2 102 58 7 7 49 clb auto 0.07 375 0.11 0.00 2.23968 -165.863 -2.23968 2.13179 0.000227004 0.000170696 0.0238564 0.0181583 -1 436 21 1.07788e+06 970092 90369.8 1844.28 0.03 0.0404787 0.0325966 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_equivalent_sites/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_equivalent_sites/config/golden_results.txt index 7574a18e313..ab33f90e870 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_equivalent_sites/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_equivalent_sites/config/golden_results.txt @@ -1,2 +1,2 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time -equivalent.xml equivalent.blif common 0.21 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 -1 -1 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_equivalent_sites/run011/equivalent.xml/equivalent.blif/common 18484 1 1 3 4 0 3 4 4 4 16 io_site_1 auto 0.00 7 0.01 0.00 3.6909 -3.6909 -3.6909 nan 1.7662e-05 1.2102e-05 0.00129277 0.000882898 1 3 1 59253.6 29626.8 -1 -1 0.00 0.00155496 0.00105635 3 1 3 3 50 17 3.69193 nan -3.69193 -3.69193 0 0 -1 -1 0.00 0.000152151 9.921e-05 +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time +equivalent.xml equivalent.blif common 0.13 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 -1 -1 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_equivalent_sites/run008/equivalent.xml/equivalent.blif/common 17424 1 1 3 4 0 3 4 4 4 16 io_site_1 auto 0.00 7 0.00 0.00 3.6909 -3.6909 -3.6909 nan 4.804e-06 2.342e-06 0.000343251 0.000167423 1 3 1 59253.6 29626.8 -1 -1 0.00 0.000421899 0.000216757 3 1 3 3 50 17 3.69193 nan -3.69193 -3.69193 0 0 -1 -1 0.00 4.9487e-05 3.2854e-05 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fc_abs/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fc_abs/config/golden_results.txt index 927861bdd9e..61a80ec1fbe 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fc_abs/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fc_abs/config/golden_results.txt @@ -1,2 +1,2 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6_N10_mem32K_40nm_fc_abs.xml stereovision3.v common 1.30 0.05 9176 4 0.12 -1 -1 33040 -1 -1 19 11 0 0 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fc_abs/run014/k6_N10_mem32K_40nm_fc_abs.xml/stereovision3.v/common 30384 11 30 262 292 2 104 60 7 7 49 clb auto 0.07 401 0.12 0.00 2.2283 -166.679 -2.2283 2.11876 0.000334435 0.000269344 0.0328891 0.0254814 16 574 25 1.07788e+06 1.02399e+06 88828.2 1812.82 0.14 0.0818614 0.0655978 502 28 978 2119 97696 25382 2.88672 2.66584 -203.092 -2.88672 0 0 104221. 2126.97 0.04 0.020146 0.0170636 +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_mem32K_40nm_fc_abs.xml stereovision3.v common 3.12 0.04 9116 4 0.13 -1 -1 37260 -1 -1 18 11 0 0 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fc_abs/run013/k6_N10_mem32K_40nm_fc_abs.xml/stereovision3.v/common 24676 11 29 257 286 2 102 58 7 7 49 clb auto 0.06 372 0.14 0.00 2.2057 -160.345 -2.2057 2.108 0.000227541 0.000171909 0.024997 0.01905 16 535 48 1.07788e+06 970092 88828.2 1812.82 0.18 0.0777035 0.0623766 587 48 1091 2555 117821 30316 2.84283 2.5335 -205.172 -2.84283 0 0 104221. 2126.97 0.06 0.0280158 0.0237119 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fix_clusters/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fix_clusters/config/golden_results.txt index 51ab7473e23..cd6fcf881da 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fix_clusters/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fix_clusters/config/golden_results.txt @@ -1,2 +1,2 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time -fix_clusters_test_arch.xml apex2.blif common 7.84 -1 -1 -1 -1 -1 -1 -1 -1 -1 141 38 -1 -1 success v8.0.0-2202-g8f11883e3-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-07-27T19:24:47 betzgrp-wintermute.eecg.utoronto.ca /home/khalid88/Documents/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fix_clusters/run037/fix_clusters_test_arch.xml/apex2.blif/common 53244 38 3 1916 1919 0 1062 182 7 7 49 clb auto 2.08 5387 0.18 0.03 4.66816 -13.91 -4.66816 nan 0.00147967 0.0012157 0.0240095 0.0229321 164 7659 37 1.34735e+06 7.59905e+06 957298. 19536.7 4.36 0.824295 0.669083 6946 18 6057 24435 1152150 355904 5.7306 nan -16.8488 -5.7306 0 0 1.19720e+06 24432.6 0.25 0.119777 0.107901 +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time +fix_clusters_test_arch.xml apex2.blif common 8.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 141 38 -1 -1 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fix_clusters/run008/fix_clusters_test_arch.xml/apex2.blif/common 42016 38 3 1916 1919 0 1062 182 7 7 49 clb auto 2.74 5387 0.26 0.03 4.66816 -13.91 -4.66816 nan 0.00219948 0.00184454 0.0342576 0.0324845 164 7659 37 1.34735e+06 7.59905e+06 957298. 19536.7 4.01 0.916341 0.756747 6946 18 6057 24435 1152150 355904 5.7306 nan -16.8488 -5.7306 0 0 1.19720e+06 24432.6 0.38 0.158382 0.142529 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fix_pins_random/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fix_pins_random/config/golden_results.txt index 9a134895485..0e04c676ecb 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fix_pins_random/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fix_pins_random/config/golden_results.txt @@ -1,2 +1,2 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6_N10_mem32K_40nm.xml stereovision3.v common 1.42 0.05 9352 4 0.13 -1 -1 33132 -1 -1 19 11 0 0 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fix_pins_random/run014/k6_N10_mem32K_40nm.xml/stereovision3.v/common 29336 11 30 262 292 2 104 60 7 7 49 clb auto 0.08 478 0.14 0.00 2.23968 -173.325 -2.23968 2.1232 0.000376852 0.000231273 0.031811 0.02419 22 792 25 1.07788e+06 1.02399e+06 54623.3 1114.76 0.13 0.0808549 0.0645732 719 45 1163 2902 121680 33636 2.65665 2.40886 -195.159 -2.65665 0 0 69322.2 1414.74 0.06 0.0323268 0.0268877 +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_mem32K_40nm.xml stereovision3.v common 3.11 0.04 9216 4 0.11 -1 -1 37304 -1 -1 18 11 0 0 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fix_pins_random/run013/k6_N10_mem32K_40nm.xml/stereovision3.v/common 24572 11 29 257 286 2 102 58 7 7 49 clb auto 0.06 436 0.20 0.00 2.20202 -171.201 -2.20202 2.10527 0.000252616 0.000195883 0.0243677 0.0187971 20 692 30 1.07788e+06 970092 49980.0 1020.00 0.13 0.0676798 0.0545153 551 23 656 1660 53453 15719 2.56951 2.37638 -185.594 -2.56951 0 0 65453.8 1335.79 0.03 0.0169896 0.0146771 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_flyover_wires/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_flyover_wires/config/golden_results.txt index 6f85a06583d..63a5314e068 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_flyover_wires/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_flyover_wires/config/golden_results.txt @@ -1,3 +1,3 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time -shorted_flyover_wires.xml raygentop.v common 16.33 0.28 30652 3 1.40 -1 -1 40476 -1 -1 107 214 0 8 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_flyover_wires/run015/shorted_flyover_wires.xml/raygentop.v/common 66264 214 305 2964 2870 1 1438 634 19 19 361 io clb auto 2.18 10856 2.36 0.01 4.39652 -2498.48 -4.39652 4.39652 0.00296434 0.00257976 0.462061 0.393261 66 27866 32 1.65001e+07 8.93466e+06 1.15238e+06 3192.19 5.76 1.36556 1.1895 22609 23 6564 15129 5362840 1300782 5.32517 5.32517 -2957.12 -5.32517 0 0 1.43513e+06 3975.42 1.02 0.265233 0.244978 -buffered_flyover_wires.xml raygentop.v common 15.93 0.30 30588 3 1.35 -1 -1 40448 -1 -1 107 214 0 8 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_flyover_wires/run015/buffered_flyover_wires.xml/raygentop.v/common 66324 214 305 2964 2870 1 1438 634 19 19 361 io clb auto 2.21 10890 2.30 0.01 4.35951 -2423.98 -4.35951 4.35951 0.00301783 0.00259087 0.467389 0.396939 68 26177 38 1.65001e+07 8.93466e+06 1.22105e+06 3382.40 5.50 1.41939 1.24455 21304 16 6126 14336 5421684 1304674 4.95972 4.95972 -3001.08 -4.95972 0 0 1.52022e+06 4211.15 0.84 0.181002 0.168567 +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time +shorted_flyover_wires.xml raygentop.v common 19.70 0.25 30668 3 0.97 -1 -1 44760 -1 -1 111 214 0 8 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_flyover_wires/run015/shorted_flyover_wires.xml/raygentop.v/common 59956 214 305 2963 2869 1 1440 638 19 19 361 io clb auto 2.65 11244 3.79 0.02 4.44813 -2545.22 -4.44813 4.44813 0.00387612 0.00339778 0.545368 0.477066 64 28714 29 1.65001e+07 9.15023e+06 1.11360e+06 3084.77 5.89 1.43728 1.28492 24056 17 6849 16137 5536449 1373813 5.20342 5.20342 -3060.64 -5.20342 0 0 1.39747e+06 3871.11 1.06 0.223873 0.208699 +buffered_flyover_wires.xml raygentop.v common 20.20 0.25 30520 3 0.94 -1 -1 44960 -1 -1 111 214 0 8 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_flyover_wires/run015/buffered_flyover_wires.xml/raygentop.v/common 59940 214 305 2963 2869 1 1440 638 19 19 361 io clb auto 2.64 10916 3.98 0.02 4.16668 -2495.77 -4.16668 4.16668 0.00379379 0.00332457 0.569567 0.498905 66 27236 36 1.65001e+07 9.15023e+06 1.19176e+06 3301.28 6.37 1.52766 1.36457 21694 17 6170 13640 4822807 1205088 4.71202 4.71202 -2922.68 -4.71202 0 0 1.48698e+06 4119.07 0.95 0.224701 0.209865 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fpu_hard_block_arch/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fpu_hard_block_arch/config/golden_results.txt index 3447c779d7b..17ae818fa9b 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fpu_hard_block_arch/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fpu_hard_block_arch/config/golden_results.txt @@ -1,2 +1,2 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time -hard_fpu_arch_timing.xml mm3.v common 2.21 0.02 6364 1 0.02 -1 -1 30536 -1 -1 0 193 -1 -1 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fpu_hard_block_arch/run015/hard_fpu_arch_timing.xml/mm3.v/common 34840 193 32 545 422 1 289 227 21 21 441 io auto 0.97 3073 0.30 0.00 2.985 -793.195 -2.985 2.985 0.000763196 0.00068747 0.100217 0.0904177 4204 388 388 1639031 600440 809148 68766.3 979092. 2220.16 4 2.985 2.985 -803.223 -2.985 -21.8252 -0.0851 0.21 0.115939 0.10529 +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time +hard_fpu_arch_timing.xml mm3.v common 4.54 0.02 6284 1 0.01 -1 -1 33948 -1 -1 0 193 -1 -1 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fpu_hard_block_arch/run014/hard_fpu_arch_timing.xml/mm3.v/common 30184 193 32 545 422 1 289 227 21 21 441 io auto 1.18 3073 0.39 0.00 2.985 -793.196 -2.985 2.985 0.00086814 0.000786499 0.111156 0.101186 4240 416 416 1611893 581721 809148 68766.3 979092. 2220.16 5 2.985 2.985 -803.995 -2.985 -21.7856 -0.0851 0.23 0.132332 0.121489 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fracturable_luts/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fracturable_luts/config/golden_results.txt index 52371aa301c..238d6155dd6 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fracturable_luts/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fracturable_luts/config/golden_results.txt @@ -1,2 +1,2 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time -k6_N8_I80_fleI10_fleO2_ff2_nmodes_2.xml ch_intrinsics.v common 2.27 0.04 8984 3 0.24 -1 -1 36260 -1 -1 67 99 1 0 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fracturable_luts/run015/k6_N8_I80_fleI10_fleO2_ff2_nmodes_2.xml/ch_intrinsics.v/common 36352 99 130 363 493 1 249 297 13 13 169 clb auto 0.39 558 0.22 0.00 36 1334 10 0 0 481804. 2850.91 0.46 +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time +k6_N8_I80_fleI10_fleO2_ff2_nmodes_2.xml ch_intrinsics.v common 4.27 0.03 8912 3 0.23 -1 -1 40184 -1 -1 67 99 1 0 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_fracturable_luts/run014/k6_N8_I80_fleI10_fleO2_ff2_nmodes_2.xml/ch_intrinsics.v/common 29644 99 130 363 493 1 249 297 13 13 169 clb auto 0.44 558 0.30 0.00 36 1334 10 0 0 481804. 2850.91 0.54 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_full_stats/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_full_stats/config/golden_results.txt index 615a5a37d4d..0d0a8742664 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_full_stats/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_full_stats/config/golden_results.txt @@ -1,2 +1,2 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6_N10_mem32K_40nm.xml stereovision3.v common 1.02 0.05 9228 4 0.11 -1 -1 33080 -1 -1 19 11 0 0 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_full_stats/run011/k6_N10_mem32K_40nm.xml/stereovision3.v/common 27716 11 30 262 292 2 104 60 7 7 49 clb auto 0.08 393 0.08 0.00 2.23968 -171.108 -2.23968 2.13287 0.000286094 0.000228816 0.0332272 0.0258492 -1 476 25 1.07788e+06 1.02399e+06 90369.8 1844.28 0.04 0.0540432 0.0433436 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_mem32K_40nm.xml stereovision3.v common 2.76 0.04 9184 4 0.13 -1 -1 37212 -1 -1 18 11 0 0 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_full_stats/run013/k6_N10_mem32K_40nm.xml/stereovision3.v/common 24340 11 29 257 286 2 102 58 7 7 49 clb auto 0.06 375 0.08 0.00 2.23968 -165.863 -2.23968 2.13179 0.000233906 0.000178572 0.0236176 0.0180422 -1 436 21 1.07788e+06 970092 90369.8 1844.28 0.03 0.0410697 0.0332331 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_func_formal_flow/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_func_formal_flow/config/golden_results.txt index 27ad7a55e6c..9aacbde1a57 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_func_formal_flow/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_func_formal_flow/config/golden_results.txt @@ -1,21 +1,21 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6_frac_N10_40nm.xml const_true.blif common 0.26 -1 -1 0 0.00 -1 -1 29572 -1 -1 1 0 -1 -1 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_func_formal_flow/run015/k6_frac_N10_40nm.xml/const_true.blif/common 19384 -1 1 1 2 0 1 2 3 3 9 -1 auto 0.00 0 0.00 0.00 nan 0 0 nan 1.2237e-05 7.343e-06 4.9024e-05 3.1558e-05 -1 0 1 53894 53894 38783.3 4309.26 0.00 0.000143025 8.9268e-05 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6_frac_N10_40nm.xml const_false.blif common 0.22 -1 -1 0 0.01 -1 -1 29700 -1 -1 1 0 -1 -1 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_func_formal_flow/run015/k6_frac_N10_40nm.xml/const_false.blif/common 19200 -1 1 1 2 0 1 2 3 3 9 -1 auto 0.00 0 0.00 0.00 nan 0 0 nan 1.7399e-05 1.0487e-05 6.6503e-05 4.2005e-05 -1 0 1 53894 53894 38783.3 4309.26 0.00 0.000182915 0.000113721 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6_frac_N10_40nm.xml always_true.blif common 0.26 -1 -1 0 0.01 -1 -1 29552 -1 -1 1 0 -1 -1 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_func_formal_flow/run015/k6_frac_N10_40nm.xml/always_true.blif/common 19464 6 1 1 8 0 1 8 3 3 9 -1 auto 0.00 0 0.00 0.00 nan 0 0 nan 1.808e-05 1.0968e-05 0.000133261 0.00010355 -1 0 1 53894 53894 38783.3 4309.26 0.00 0.000254706 0.0001785 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6_frac_N10_40nm.xml always_false.blif common 0.27 -1 -1 0 0.01 -1 -1 29552 -1 -1 1 0 -1 -1 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_func_formal_flow/run015/k6_frac_N10_40nm.xml/always_false.blif/common 19452 6 1 1 8 0 1 8 3 3 9 -1 auto 0.00 0 0.00 0.00 nan 0 0 nan 2.04e-05 1.2416e-05 7.7454e-05 4.8358e-05 -1 0 1 53894 53894 38783.3 4309.26 0.00 0.000176112 0.000110121 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6_frac_N10_40nm.xml and.blif common 0.28 -1 -1 1 0.01 -1 -1 29748 -1 -1 1 2 -1 -1 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_func_formal_flow/run015/k6_frac_N10_40nm.xml/and.blif/common 19516 2 1 3 4 0 3 4 3 3 9 -1 auto 0.00 6 0.00 0.00 0.708653 -0.708653 -0.708653 nan 1.6238e-05 1.0869e-05 7.2239e-05 5.1555e-05 -1 5 1 53894 53894 38783.3 4309.26 0.00 0.000227119 0.000154138 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6_frac_N10_40nm.xml multiconnected_lut.blif common 0.28 -1 -1 1 0.01 -1 -1 31356 -1 -1 1 5 -1 -1 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_func_formal_flow/run015/k6_frac_N10_40nm.xml/multiconnected_lut.blif/common 19588 5 1 6 7 0 6 7 3 3 9 -1 auto 0.00 12 0.00 0.00 0.708653 -0.708653 -0.708653 nan 2.468e-05 1.6355e-05 0.000123199 9.0276e-05 -1 7 11 53894 53894 38783.3 4309.26 0.00 0.000589018 0.000404164 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6_frac_N10_40nm.xml multiconnected_lut2.blif common 0.35 -1 -1 1 0.01 -1 -1 31900 -1 -1 1 5 -1 -1 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_func_formal_flow/run015/k6_frac_N10_40nm.xml/multiconnected_lut2.blif/common 19464 5 1 6 7 0 6 7 3 3 9 -1 auto 0.00 12 0.00 0.00 0.708653 -0.708653 -0.708653 nan 4.3225e-05 2.9362e-05 0.000188999 0.000137384 -1 7 11 53894 53894 38783.3 4309.26 0.00 0.000984289 0.000673754 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6_frac_N10_40nm.xml and_latch.blif common 0.29 -1 -1 1 0.00 -1 -1 29752 -1 -1 1 3 -1 -1 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_func_formal_flow/run015/k6_frac_N10_40nm.xml/and_latch.blif/common 19532 3 1 5 6 1 4 5 3 3 9 -1 auto 0.00 6 0.00 0.00 0.544641 -0.918653 -0.544641 0.544641 2.8947e-05 1.9271e-05 0.000119926 8.6346e-05 -1 5 1 53894 53894 38783.3 4309.26 0.00 0.00033709 0.000238526 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6_frac_N10_40nm.xml false_path_mux.blif common 0.35 -1 -1 1 0.03 -1 -1 31440 -1 -1 1 3 -1 -1 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_func_formal_flow/run015/k6_frac_N10_40nm.xml/false_path_mux.blif/common 19300 4 1 4 6 0 4 6 3 3 9 -1 auto 0.00 8 0.00 0.00 0.708653 -0.708653 -0.708653 nan 6.0538e-05 5.3447e-05 0.00012305 9.8145e-05 -1 4 11 53894 53894 38783.3 4309.26 0.00 0.000446167 0.000308255 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6_frac_N10_40nm.xml mult_2x2.blif common 0.35 -1 -1 1 0.03 -1 -1 31584 -1 -1 1 4 -1 -1 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca 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/mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_func_formal_flow/run008/k6_frac_N10_40nm.xml/mult_3x4.blif/common 18820 7 8 22 30 0 15 18 4 4 16 clb auto 0.01 34 0.01 0.00 1.09565 -6.57093 -1.09565 nan 2.2126e-05 1.5998e-05 0.00259909 0.00188803 -1 44 12 215576 161682 99039.1 6189.95 0.00 0.00384098 0.00299527 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml mult_4x4.blif common 1.00 -1 -1 4 0.04 -1 -1 35620 -1 -1 2 8 -1 -1 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_func_formal_flow/run008/k6_frac_N10_40nm.xml/mult_4x4.blif/common 18784 8 8 29 37 0 21 18 4 4 16 clb auto 0.01 54 0.01 0.00 1.79165 -10.3186 -1.79165 nan 2.9944e-05 2.2575e-05 0.00317544 0.00240077 -1 59 17 215576 107788 99039.1 6189.95 0.00 0.00529933 0.00430369 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml mult_5x5.blif common 1.06 -1 -1 4 0.05 -1 -1 35564 -1 -1 4 10 -1 -1 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_func_formal_flow/run008/k6_frac_N10_40nm.xml/mult_5x5.blif/common 19016 10 10 47 57 0 39 24 4 4 16 clb auto 0.02 126 0.02 0.00 2.32358 -16.2013 -2.32358 nan 4.7696e-05 3.6738e-05 0.00516125 0.003992 -1 140 18 215576 215576 99039.1 6189.95 0.01 0.00872959 0.00721365 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml mult_5x6.blif common 1.16 -1 -1 5 0.07 -1 -1 36520 -1 -1 5 11 -1 -1 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_func_formal_flow/run008/k6_frac_N10_40nm.xml/mult_5x6.blif/common 19428 11 11 61 72 0 51 27 5 5 25 clb auto 0.03 175 0.03 0.00 2.94997 -19.4089 -2.94997 nan 6.5286e-05 4.9432e-05 0.00625271 0.00493327 -1 200 13 485046 269470 186194. 7447.77 0.01 0.010742 0.00906837 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml rca_1bit.blif common 0.94 -1 -1 1 0.02 -1 -1 34608 -1 -1 1 3 -1 -1 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_func_formal_flow/run008/k6_frac_N10_40nm.xml/rca_1bit.blif/common 18480 3 2 5 7 0 5 6 3 3 9 -1 auto 0.00 10 0.00 0.00 0.708653 -1.41731 -0.708653 nan 7.027e-06 4.1e-06 6.1605e-05 4.5217e-05 -1 8 11 53894 53894 38783.3 4309.26 0.00 0.00026883 0.000194274 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml rca_2bit.blif common 0.93 -1 -1 1 0.02 -1 -1 35696 -1 -1 1 5 -1 -1 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_func_formal_flow/run008/k6_frac_N10_40nm.xml/rca_2bit.blif/common 18524 5 3 8 11 0 8 9 3 3 9 -1 auto 0.00 16 0.00 0.00 0.708653 -2.12596 -0.708653 nan 1.0442e-05 6.795e-06 9.487e-05 7.5795e-05 -1 13 11 53894 53894 38783.3 4309.26 0.00 0.000444376 0.000353731 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml rca_3bit.blif common 0.93 -1 -1 2 0.03 -1 -1 35804 -1 -1 1 7 -1 -1 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_func_formal_flow/run008/k6_frac_N10_40nm.xml/rca_3bit.blif/common 18628 7 4 12 16 0 11 12 3 3 9 -1 auto 0.00 22 0.00 0.00 1.04365 -3.83961 -1.04365 nan 1.2522e-05 8.523e-06 0.000130561 0.000109275 -1 18 11 53894 53894 38783.3 4309.26 0.00 0.00061002 0.000510525 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml rca_4bit.blif common 0.94 -1 -1 2 0.02 -1 -1 35856 -1 -1 1 9 -1 -1 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_func_formal_flow/run008/k6_frac_N10_40nm.xml/rca_4bit.blif/common 18560 9 5 15 20 0 14 15 3 3 9 -1 auto 0.00 28 0.00 0.00 1.04365 -4.54826 -1.04365 nan 1.4965e-05 1.061e-05 0.000159242 0.000137005 -1 18 12 53894 53894 38783.3 4309.26 0.00 0.000780232 0.000667063 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml rca_5bit.blif common 0.95 -1 -1 3 0.02 -1 -1 35668 -1 -1 1 11 -1 -1 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_func_formal_flow/run008/k6_frac_N10_40nm.xml/rca_5bit.blif/common 18500 11 6 19 25 0 17 18 3 3 9 -1 auto 0.00 34 0.00 0.00 1.37865 -6.93192 -1.37865 nan 1.7555e-05 1.2587e-05 0.000206891 0.000181246 -1 22 6 53894 53894 38783.3 4309.26 0.00 0.000832487 0.000740359 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_func_formal_vpr/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_func_formal_vpr/config/golden_results.txt index 7611c909a58..627227a02a1 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_func_formal_vpr/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_func_formal_vpr/config/golden_results.txt @@ -1,7 +1,7 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6_frac_N10_40nm.xml const_true.blif common 0.16 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 0 -1 -1 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_func_formal_vpr/run015/k6_frac_N10_40nm.xml/const_true.blif/common 19160 -1 1 1 2 0 1 2 3 3 9 -1 auto 0.00 0 0.00 0.00 nan 0 0 nan 1.2116e-05 7.148e-06 4.9436e-05 3.1401e-05 -1 0 1 53894 53894 20487.3 2276.37 0.00 0.000137672 8.6389e-05 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6_frac_N10_40nm.xml const_false.blif common 0.17 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 0 -1 -1 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_func_formal_vpr/run015/k6_frac_N10_40nm.xml/const_false.blif/common 19108 -1 1 1 2 0 1 2 3 3 9 -1 auto 0.00 0 0.00 0.00 nan 0 0 nan 1.6666e-05 1.0142e-05 7.5238e-05 4.8097e-05 -1 0 1 53894 53894 20487.3 2276.37 0.00 0.000199786 0.000128102 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6_frac_N10_40nm.xml always_true.blif common 0.15 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 6 -1 -1 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_func_formal_vpr/run015/k6_frac_N10_40nm.xml/always_true.blif/common 20012 6 1 7 8 0 7 8 3 3 9 -1 auto 0.00 14 0.00 0.00 0.736421 -0.736421 -0.736421 nan 2.2031e-05 1.5121e-05 9.6391e-05 7.1506e-05 -1 9 13 53894 53894 20487.3 2276.37 0.00 0.000645406 0.000461608 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6_frac_N10_40nm.xml always_false.blif common 0.18 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 6 -1 -1 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_func_formal_vpr/run015/k6_frac_N10_40nm.xml/always_false.blif/common 20108 6 1 7 8 0 7 8 3 3 9 -1 auto 0.00 14 0.00 0.00 0.736421 -0.736421 -0.736421 nan 2.2199e-05 1.515e-05 0.000102961 7.5062e-05 -1 9 13 53894 53894 20487.3 2276.37 0.00 0.000582954 0.000398915 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6_frac_N10_40nm.xml multiconnected_lut.blif common 0.21 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 5 -1 -1 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_func_formal_vpr/run015/k6_frac_N10_40nm.xml/multiconnected_lut.blif/common 19164 5 1 6 7 0 6 7 3 3 9 -1 auto 0.00 12 0.00 0.00 0.736421 -0.736421 -0.736421 nan 2.403e-05 1.5916e-05 0.000108273 7.5908e-05 -1 7 1 53894 53894 20487.3 2276.37 0.00 0.000338817 0.000242869 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6_frac_N10_40nm.xml multiconnected_lut2.blif common 0.19 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 5 -1 -1 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_func_formal_vpr/run015/k6_frac_N10_40nm.xml/multiconnected_lut2.blif/common 19080 5 1 6 7 0 6 7 3 3 9 -1 auto 0.00 12 0.00 0.00 0.736421 -0.736421 -0.736421 nan 3.2406e-05 2.2919e-05 0.000149203 0.000107347 -1 7 1 53894 53894 20487.3 2276.37 0.00 0.00042548 0.000308476 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_40nm.xml const_true.blif common 0.10 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 0 -1 -1 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_func_formal_vpr/run008/k6_frac_N10_40nm.xml/const_true.blif/common 18164 -1 1 1 2 0 1 2 3 3 9 -1 auto 0.00 0 0.00 0.00 nan 0 0 nan 5.906e-06 2.702e-06 3.508e-05 1.9947e-05 -1 0 1 53894 53894 20487.3 2276.37 0.00 7.8373e-05 4.6212e-05 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml const_false.blif common 0.10 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 0 -1 -1 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_func_formal_vpr/run008/k6_frac_N10_40nm.xml/const_false.blif/common 18216 -1 1 1 2 0 1 2 3 3 9 -1 auto 0.00 0 0.00 0.00 nan 0 0 nan 5.462e-06 2.343e-06 3.3193e-05 1.8523e-05 -1 0 1 53894 53894 20487.3 2276.37 0.00 7.7035e-05 4.5411e-05 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml always_true.blif common 0.10 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 6 -1 -1 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_func_formal_vpr/run008/k6_frac_N10_40nm.xml/always_true.blif/common 18340 6 1 7 8 0 7 8 3 3 9 -1 auto 0.00 14 0.00 0.00 0.736421 -0.736421 -0.736421 nan 8.06e-06 5.016e-06 6.02e-05 4.4119e-05 -1 8 2 53894 53894 20487.3 2276.37 0.00 0.000179643 0.000137051 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml always_false.blif common 0.10 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 6 -1 -1 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_func_formal_vpr/run008/k6_frac_N10_40nm.xml/always_false.blif/common 18344 6 1 7 8 0 7 8 3 3 9 -1 auto 0.00 14 0.00 0.00 0.736421 -0.736421 -0.736421 nan 7.937e-06 4.846e-06 5.8989e-05 4.2781e-05 -1 8 2 53894 53894 20487.3 2276.37 0.00 0.000178337 0.000135601 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml multiconnected_lut.blif common 0.13 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 5 -1 -1 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_func_formal_vpr/run008/k6_frac_N10_40nm.xml/multiconnected_lut.blif/common 18240 5 1 6 7 0 6 7 3 3 9 -1 auto 0.00 12 0.00 0.00 0.736421 -0.736421 -0.736421 nan 7.616e-06 4.599e-06 5.9776e-05 4.3e-05 -1 7 12 53894 53894 20487.3 2276.37 0.00 0.000277861 0.000199136 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_frac_N10_40nm.xml multiconnected_lut2.blif common 0.13 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 5 -1 -1 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_func_formal_vpr/run008/k6_frac_N10_40nm.xml/multiconnected_lut2.blif/common 18372 5 1 6 7 0 6 7 3 3 9 -1 auto 0.00 12 0.00 0.00 0.736421 -0.736421 -0.736421 nan 7.66e-06 4.667e-06 5.8877e-05 4.2503e-05 -1 7 12 53894 53894 20487.3 2276.37 0.00 0.000274921 0.00019703 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_global_nonuniform/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_global_nonuniform/config/golden_results.txt index 64894c055ba..5745444a9ad 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_global_nonuniform/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_global_nonuniform/config/golden_results.txt @@ -1,7 +1,7 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time -x_gaussian_y_uniform.xml stereovision3.v common 1.33 0.05 9276 4 0.11 -1 -1 33060 -1 -1 13 11 0 0 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_global_nonuniform/run011/x_gaussian_y_uniform.xml/stereovision3.v/common 27700 11 30 262 292 2 110 54 7 7 49 clb auto 0.12 367 0.10 0.00 1.91988 -135.359 -1.91988 1.85222 0.000283933 0.000230209 0.0483647 0.0398743 12 301 4 1.07788e+06 700622 -1 -1 0.12 0.0955425 0.0802346 288 2 145 219 14754 5946 1.91988 1.85222 -135.359 -1.91988 0 0 -1 -1 0.01 0.00863779 0.00815694 -x_uniform_y_gaussian.xml stereovision3.v common 1.34 0.05 9180 4 0.14 -1 -1 33096 -1 -1 13 11 0 0 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_global_nonuniform/run011/x_uniform_y_gaussian.xml/stereovision3.v/common 28048 11 30 262 292 2 110 54 7 7 49 clb auto 0.10 344 0.08 0.00 1.91988 -135.359 -1.91988 1.85222 0.0004883 0.000403134 0.033427 0.0274684 10 314 19 1.07788e+06 700622 -1 -1 0.15 0.0756226 0.0632296 259 3 169 256 15612 6426 1.91988 1.85222 -135.359 -1.91988 0 0 -1 -1 0.02 0.0147541 0.0138339 -x_gaussian_y_gaussian.xml stereovision3.v common 1.29 0.05 9328 4 0.10 -1 -1 33056 -1 -1 13 11 0 0 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_global_nonuniform/run011/x_gaussian_y_gaussian.xml/stereovision3.v/common 27792 11 30 262 292 2 110 54 7 7 49 clb auto 0.10 349 0.09 0.00 1.91988 -135.359 -1.91988 1.85222 0.000489259 0.00040451 0.0384295 0.0316628 12 288 8 1.07788e+06 700622 -1 -1 0.16 0.0825146 0.0694766 272 3 159 237 14357 5895 1.91988 1.85222 -135.359 -1.91988 0 0 -1 -1 0.01 0.00969215 0.00913209 -x_delta_y_uniform.xml stereovision3.v common 1.27 0.06 9324 4 0.11 -1 -1 33136 -1 -1 13 11 0 0 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_global_nonuniform/run011/x_delta_y_uniform.xml/stereovision3.v/common 27940 11 30 262 292 2 110 54 7 7 49 clb auto 0.09 370 0.09 0.00 1.91988 -135.359 -1.91988 1.85222 0.000289699 0.000233697 0.0407541 0.0330296 48 299 3 1.07788e+06 700622 -1 -1 0.13 0.103302 0.0855557 300 2 154 228 16498 6675 1.91988 1.85222 -135.359 -1.91988 0 0 -1 -1 0.02 0.0130216 0.0123026 -x_delta_y_delta.xml stereovision3.v common 1.55 0.05 9256 4 0.15 -1 -1 33080 -1 -1 13 11 0 0 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_global_nonuniform/run011/x_delta_y_delta.xml/stereovision3.v/common 27756 11 30 262 292 2 110 54 7 7 49 clb auto 0.14 365 0.14 0.00 1.91988 -135.359 -1.91988 1.85222 0.000479438 0.000397034 0.0652252 0.0543857 48 295 15 1.07788e+06 700622 -1 -1 0.22 0.162305 0.137058 283 11 204 319 22292 8966 1.91988 1.85222 -135.359 -1.91988 0 0 -1 -1 0.03 0.0209343 0.0190146 -x_uniform_y_delta.xml stereovision3.v common 1.44 0.05 9256 4 0.12 -1 -1 33080 -1 -1 13 11 0 0 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_global_nonuniform/run011/x_uniform_y_delta.xml/stereovision3.v/common 27928 11 30 262 292 2 110 54 7 7 49 clb auto 0.14 365 0.09 0.00 1.91988 -135.359 -1.91988 1.85222 0.000285296 0.00023051 0.0411397 0.0336476 38 284 2 1.07788e+06 700622 -1 -1 0.19 0.126387 0.106109 287 15 174 293 17775 6988 1.91988 1.85222 -135.359 -1.91988 0 0 -1 -1 0.03 0.0230303 0.0205393 +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time +x_gaussian_y_uniform.xml stereovision3.v common 3.01 0.04 9220 4 0.13 -1 -1 37168 -1 -1 13 11 0 0 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_global_nonuniform/run013/x_gaussian_y_uniform.xml/stereovision3.v/common 24616 11 29 257 286 2 106 53 7 7 49 clb auto 0.10 360 0.08 0.00 1.99788 -133.626 -1.99788 1.88947 0.000221336 0.000167533 0.0257731 0.020057 12 277 5 1.07788e+06 700622 -1 -1 0.11 0.0613876 0.0504397 281 3 159 228 15368 6286 1.99788 1.88947 -133.626 -1.99788 0 0 -1 -1 0.01 0.0100317 0.00955307 +x_uniform_y_gaussian.xml stereovision3.v common 3.04 0.04 9232 4 0.12 -1 -1 37140 -1 -1 13 11 0 0 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_global_nonuniform/run013/x_uniform_y_gaussian.xml/stereovision3.v/common 24780 11 29 257 286 2 106 53 7 7 49 clb auto 0.10 318 0.10 0.00 1.99788 -133.626 -1.99788 1.88947 0.00022203 0.000166893 0.0303489 0.0235551 10 243 5 1.07788e+06 700622 -1 -1 0.15 0.0655939 0.053717 242 2 149 216 12095 5003 1.99788 1.88947 -133.626 -1.99788 0 0 -1 -1 0.01 0.00960016 0.00921376 +x_gaussian_y_gaussian.xml stereovision3.v common 2.95 0.04 9292 4 0.12 -1 -1 37180 -1 -1 13 11 0 0 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_global_nonuniform/run013/x_gaussian_y_gaussian.xml/stereovision3.v/common 24708 11 29 257 286 2 106 53 7 7 49 clb auto 0.10 353 0.08 0.00 1.99788 -133.626 -1.99788 1.88947 0.000249977 0.000191253 0.0252307 0.0198827 14 283 11 1.07788e+06 700622 -1 -1 0.09 0.0615774 0.0507442 285 2 142 209 13898 5668 1.99788 1.88947 -133.626 -1.99788 0 0 -1 -1 0.01 0.00949246 0.00909221 +x_delta_y_uniform.xml stereovision3.v common 3.08 0.04 9276 4 0.15 -1 -1 36844 -1 -1 13 11 0 0 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_global_nonuniform/run013/x_delta_y_uniform.xml/stereovision3.v/common 24800 11 29 257 286 2 106 53 7 7 49 clb auto 0.10 383 0.11 0.00 1.99788 -133.626 -1.99788 1.88947 0.000225335 0.000170281 0.0324928 0.0252056 44 318 14 1.07788e+06 700622 -1 -1 0.16 0.0931864 0.0758055 314 14 196 309 22831 9430 1.99788 1.88947 -133.626 -1.99788 0 0 -1 -1 0.02 0.0152393 0.0138105 +x_delta_y_delta.xml stereovision3.v common 3.07 0.04 9236 4 0.13 -1 -1 37200 -1 -1 13 11 0 0 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_global_nonuniform/run013/x_delta_y_delta.xml/stereovision3.v/common 24676 11 29 257 286 2 106 53 7 7 49 clb auto 0.11 342 0.10 0.00 1.99788 -133.626 -1.99788 1.88947 0.000220109 0.000166406 0.0300643 0.0234906 44 277 14 1.07788e+06 700622 -1 -1 0.16 0.0932797 0.0765619 268 16 185 285 19115 7834 1.99788 1.88947 -133.626 -1.99788 0 0 -1 -1 0.02 0.0158876 0.0143724 +x_uniform_y_delta.xml stereovision3.v common 2.97 0.04 9324 4 0.12 -1 -1 37240 -1 -1 13 11 0 0 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_global_nonuniform/run013/x_uniform_y_delta.xml/stereovision3.v/common 24780 11 29 257 286 2 106 53 7 7 49 clb auto 0.10 343 0.09 0.00 1.99788 -133.626 -1.99788 1.88947 0.000223483 0.000169025 0.027487 0.0213607 48 291 3 1.07788e+06 700622 -1 -1 0.12 0.0821758 0.0671647 289 2 149 209 14083 6019 1.99788 1.88947 -133.626 -1.99788 0 0 -1 -1 0.01 0.00931726 0.0089396 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_global_routing/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_global_routing/config/golden_results.txt index 324955d5572..17beba06662 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_global_routing/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_global_routing/config/golden_results.txt @@ -1,4 +1,4 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time -timing/k6_N10_mem32K_40nm.xml stereovision3.v common 1.32 0.03 9256 4 0.12 -1 -1 33032 -1 -1 19 11 0 0 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_global_routing/run014/timing/k6_N10_mem32K_40nm.xml/stereovision3.v/common 27316 11 30 262 292 2 104 60 7 7 49 clb auto 0.07 393 0.07 0.00 1.93141 -141.327 -1.93141 1.88461 0.000334722 0.000270475 0.0287483 0.0235286 10 332 24 1.07788e+06 1.02399e+06 -1 -1 0.20 0.0949287 0.0786353 322 23 620 1331 105337 41161 1.93141 1.88461 -141.327 -1.93141 0 0 -1 -1 0.07 0.028243 0.0242568 -nonuniform_chan_width/k6_N10_mem32K_40nm_nonuniform.xml stereovision3.v common 1.24 0.05 9324 4 0.13 -1 -1 33156 -1 -1 19 11 0 0 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_global_routing/run014/nonuniform_chan_width/k6_N10_mem32K_40nm_nonuniform.xml/stereovision3.v/common 27144 11 30 262 292 2 104 60 7 7 49 clb auto 0.10 397 0.07 0.00 1.93141 -141.327 -1.93141 1.88461 0.000284883 0.000230777 0.0279787 0.022886 14 351 23 1.07788e+06 1.02399e+06 -1 -1 0.11 0.0703105 0.0585028 324 23 680 1240 112202 45973 1.93141 1.88461 -141.327 -1.93141 0 0 -1 -1 0.04 0.0194268 0.0171311 -nonuniform_chan_width/k6_N10_mem32K_40nm_pulse.xml stereovision3.v common 1.38 0.06 9248 4 0.10 -1 -1 33032 -1 -1 19 11 0 0 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_global_routing/run014/nonuniform_chan_width/k6_N10_mem32K_40nm_pulse.xml/stereovision3.v/common 27188 11 30 262 292 2 104 60 7 7 49 clb auto 0.06 426 0.11 0.00 1.93141 -141.327 -1.93141 1.88461 0.000933193 0.000749405 0.0426975 0.0353334 14 354 48 1.07788e+06 1.02399e+06 -1 -1 0.27 0.140665 0.116929 353 22 633 1263 104916 43343 1.93141 1.88461 -141.327 -1.93141 0 0 -1 -1 0.04 0.0167794 0.0145753 +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time +timing/k6_N10_mem32K_40nm.xml stereovision3.v common 2.94 0.04 9096 4 0.13 -1 -1 37136 -1 -1 18 11 0 0 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_global_routing/run013/timing/k6_N10_mem32K_40nm.xml/stereovision3.v/common 24164 11 29 257 286 2 102 58 7 7 49 clb auto 0.06 368 0.08 0.00 1.93141 -139.635 -1.93141 1.88461 0.000232092 0.000176284 0.0226726 0.0176913 10 299 25 1.07788e+06 970092 -1 -1 0.12 0.0626496 0.0512462 292 22 675 1080 98847 41515 1.93141 1.88461 -139.635 -1.93141 0 0 -1 -1 0.04 0.016707 0.0147014 +nonuniform_chan_width/k6_N10_mem32K_40nm_nonuniform.xml stereovision3.v common 3.02 0.04 9160 4 0.12 -1 -1 36808 -1 -1 18 11 0 0 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_global_routing/run013/nonuniform_chan_width/k6_N10_mem32K_40nm_nonuniform.xml/stereovision3.v/common 24196 11 29 257 286 2 102 58 7 7 49 clb auto 0.06 365 0.09 0.00 1.93141 -139.635 -1.93141 1.88461 0.000228777 0.000172668 0.0249083 0.0192365 16 309 24 1.07788e+06 970092 -1 -1 0.12 0.066519 0.0541297 310 24 797 1411 124651 51700 1.93141 1.88461 -139.635 -1.93141 0 0 -1 -1 0.04 0.0178468 0.0156001 +nonuniform_chan_width/k6_N10_mem32K_40nm_pulse.xml stereovision3.v common 2.92 0.04 9204 4 0.13 -1 -1 37188 -1 -1 18 11 0 0 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_global_routing/run013/nonuniform_chan_width/k6_N10_mem32K_40nm_pulse.xml/stereovision3.v/common 24256 11 29 257 286 2 102 58 7 7 49 clb auto 0.06 372 0.09 0.00 1.93141 -139.635 -1.93141 1.88461 0.000230803 0.000172667 0.0242561 0.0186407 16 301 23 1.07788e+06 970092 -1 -1 0.11 0.0646663 0.0524111 299 23 611 1138 89912 36137 1.93141 1.88461 -139.635 -1.93141 0 0 -1 -1 0.04 0.0168005 0.0147144 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_graphics_commands/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_graphics_commands/config/golden_results.txt index 5611ffbb3f0..6a5d43840ee 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_graphics_commands/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_graphics_commands/config/golden_results.txt @@ -1,2 +1,2 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6_N10_mem32K_40nm.xml stereovision3.v common 3.48 0.05 9180 4 0.11 -1 -1 33036 -1 -1 19 11 0 0 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_graphics_commands/run004/k6_N10_mem32K_40nm.xml/stereovision3.v/common 49184 11 30 262 292 2 104 60 7 7 49 clb auto 0.08 411 1.39 0.00 2.21827 -167.491 -2.21827 2.12157 0.000291008 0.000232527 0.0346588 0.0269316 -1 476 21 1.07788e+06 1.02399e+06 207176. 4228.08 0.61 0.0523586 0.0418939 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_mem32K_40nm.xml stereovision3.v common 5.29 0.04 9300 4 0.12 -1 -1 36788 -1 -1 18 11 0 0 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_graphics_commands/run013/k6_N10_mem32K_40nm.xml/stereovision3.v/common 58528 11 29 257 286 2 102 58 7 7 49 clb auto 0.06 370 1.37 0.00 2.20099 -163.509 -2.20099 2.10428 0.000254004 0.000195022 0.0278476 0.0213452 -1 429 20 1.07788e+06 970092 207176. 4228.08 0.64 0.044166 0.0355682 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_manual_annealing/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_manual_annealing/config/golden_results.txt index f2e559d3624..39e77b82a90 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_manual_annealing/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_manual_annealing/config/golden_results.txt @@ -1,2 +1,2 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6_frac_N10_40nm.xml stereovision3.v common 1.30 0.06 8840 4 0.11 -1 -1 33040 -1 -1 13 11 -1 -1 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_manual_annealing/run014/k6_frac_N10_40nm.xml/stereovision3.v/common 23524 11 30 262 292 2 110 54 6 6 36 clb auto 0.10 390 0.05 0.00 2.26562 -157.479 -2.26562 2.11716 0.000297036 0.000226766 0.0155239 0.0121872 36 724 21 862304 700622 64877.6 1802.15 0.20 0.089481 0.0723913 545 12 323 532 14269 5196 2.50329 2.28128 -182.979 -2.50329 0 0 80896.3 2247.12 0.02 0.0135541 0.0121761 +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_40nm.xml stereovision3.v common 2.94 0.03 8748 4 0.12 -1 -1 37176 -1 -1 13 11 -1 -1 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_manual_annealing/run013/k6_frac_N10_40nm.xml/stereovision3.v/common 20984 11 29 257 286 2 106 53 6 6 36 clb auto 0.10 371 0.06 0.00 2.34083 -156.088 -2.34083 2.13062 0.000238038 0.000178623 0.0126977 0.00998501 32 762 29 862304 700622 60095.3 1669.31 0.13 0.0581389 0.0478841 646 12 378 538 27021 10480 2.64089 2.28911 -183.229 -2.64089 0 0 72928.5 2025.79 0.02 0.0142602 0.0129528 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_mcnc/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_mcnc/config/golden_results.txt index 2044f6c488d..79bf815b105 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_mcnc/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_mcnc/config/golden_results.txt @@ -1,4 +1,4 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k4_N4_90nm.xml diffeq.blif common 7.56 -1 -1 -1 -1 -1 -1 -1 -1 -1 417 64 -1 -1 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_mcnc/run015/k4_N4_90nm.xml/diffeq.blif/common 52456 64 39 1935 1974 1 1104 520 23 23 529 clb auto 0.38 10194 1.98 0.02 6.5862 -1367.76 -6.5862 6.5862 0.00278317 0.00219727 0.260315 0.199008 24 12158 27 983127 929624 797780. 1508.09 3.05 0.571302 0.450593 11171 19 7079 24040 1692224 422101 6.8984 6.8984 -1482.36 -6.8984 0 0 1.04508e+06 1975.57 0.39 0.0930463 0.0792965 -k4_N4_90nm.xml ex5p.blif common 17.66 -1 -1 -1 -1 -1 -1 -1 -1 -1 346 8 -1 -1 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_mcnc/run015/k4_N4_90nm.xml/ex5p.blif/common 44252 8 63 1072 1135 0 909 417 21 21 441 clb auto 0.20 11469 1.36 0.01 6.00224 -269.468 -6.00224 nan 0.00114423 0.000849497 0.129256 0.0972554 36 15772 36 804782 771343 957936. 2172.19 13.74 0.444201 0.346706 13567 23 9150 30844 4172449 1193561 6.73044 nan -286.327 -6.73044 0 0 1.20592e+06 2734.52 0.71 0.0707398 0.0601922 -k4_N4_90nm.xml s298.blif common 11.42 -1 -1 -1 -1 -1 -1 -1 -1 -1 571 4 -1 -1 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_mcnc/run015/k4_N4_90nm.xml/s298.blif/common 57704 4 6 1942 1948 1 1193 581 26 26 676 clb auto 0.40 13020 2.39 0.01 11.1117 -88.2322 -11.1117 11.1117 0.0019518 0.00135616 0.262064 0.183421 26 18430 38 1.28409e+06 1.27294e+06 1.12979e+06 1671.28 5.48 0.616792 0.455222 17192 20 9138 46892 4593534 908726 11.2577 11.2577 -91.3533 -11.2577 0 0 1.43821e+06 2127.53 0.90 0.115793 0.0986491 +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k4_N4_90nm.xml diffeq.blif common 8.82 -1 -1 -1 -1 -1 -1 -1 -1 -1 417 64 -1 -1 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_mcnc/run010/k4_N4_90nm.xml/diffeq.blif/common 44364 64 39 1935 1974 1 1104 520 23 23 529 clb auto 0.28 10329 2.97 0.02 6.5862 -1367.76 -6.5862 6.5862 0.00193574 0.00154226 0.224129 0.17769 24 12158 27 983127 929624 797780. 1508.09 3.40 0.552154 0.450358 11171 19 7079 24040 1692224 422101 6.8984 6.8984 -1482.36 -6.8984 0 0 1.04508e+06 1975.57 0.54 0.109803 0.0950502 +k4_N4_90nm.xml ex5p.blif common 19.88 -1 -1 -1 -1 -1 -1 -1 -1 -1 346 8 -1 -1 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_mcnc/run010/k4_N4_90nm.xml/ex5p.blif/common 38500 8 63 1072 1135 0 909 417 21 21 441 clb auto 0.20 11549 2.40 0.02 6.00224 -269.468 -6.00224 nan 0.00124664 0.000973452 0.143338 0.114337 36 15772 36 804782 771343 957936. 2172.19 14.83 0.48701 0.396872 13567 23 9150 30844 4172449 1193561 6.73044 nan -286.327 -6.73044 0 0 1.20592e+06 2734.52 0.91 0.0869853 0.0756346 +k4_N4_90nm.xml s298.blif common 15.27 -1 -1 -1 -1 -1 -1 -1 -1 -1 571 4 -1 -1 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_mcnc/run010/k4_N4_90nm.xml/s298.blif/common 52644 4 6 1942 1948 1 1193 581 26 26 676 clb auto 0.28 13962 3.94 0.03 11.1117 -88.2322 -11.1117 11.1117 0.00213405 0.00167882 0.256206 0.205602 26 18430 38 1.28409e+06 1.27294e+06 1.12979e+06 1671.28 7.22 0.6292 0.517381 17192 20 9138 46892 4593534 908726 11.2577 11.2577 -91.3533 -11.2577 0 0 1.43821e+06 2127.53 1.59 0.136553 0.120005 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_minimax_budgets/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_minimax_budgets/config/golden_results.txt index 0c1086f138f..ed30e8fb7f9 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_minimax_budgets/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_minimax_budgets/config/golden_results.txt @@ -1,2 +1,2 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 1.29 0.06 9444 5 0.14 -1 -1 33316 -1 -1 15 11 0 0 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_minimax_budgets/run014/k6_frac_N10_frac_chain_mem32K_40nm.xml/stereovision3.v/common 31620 11 30 313 321 2 114 56 7 7 49 clb auto 0.23 382 0.09 0.00 4.29791 0 0 4.13033 0.00027049 0.0002255 0.0394027 0.0322835 587 171 321 11871 3447 1.07788e+06 808410 219490. 4479.39 6 4.57733 4.27235 0 0 -164.701 -1.707 0.06 0.0913421 0.0823425 +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 3.12 0.04 9500 5 0.11 -1 -1 36504 -1 -1 13 11 0 0 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_minimax_budgets/run013/k6_frac_N10_frac_chain_mem32K_40nm.xml/stereovision3.v/common 26316 11 29 301 308 2 121 53 7 7 49 clb auto 0.31 388 0.11 0.00 4.29236 0 0 4.08002 0.000203459 0.000150986 0.0298909 0.0233308 596 208 347 13523 3976 1.07788e+06 700622 219490. 4479.39 5 4.59615 4.30169 0 0 -164.305 -1.707 0.06 0.0841582 0.0763007 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_no_timing/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_no_timing/config/golden_results.txt index ef3ea7e2c38..ffaa8072a89 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_no_timing/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_no_timing/config/golden_results.txt @@ -1,2 +1,2 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time -k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml ch_intrinsics.v common 1.74 0.04 9052 3 0.21 -1 -1 36248 -1 -1 64 99 1 0 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_no_timing/run015/k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml/ch_intrinsics.v/common 36072 99 130 363 493 1 251 294 12 12 144 clb auto 0.12 631 0.22 0.00 40 1720 12 5.66058e+06 3.99722e+06 360333. 2502.31 0.38 +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time +k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml ch_intrinsics.v common 3.64 0.03 8976 3 0.22 -1 -1 37628 -1 -1 64 99 1 0 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_no_timing/run015/k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml/ch_intrinsics.v/common 29344 99 130 363 493 1 251 294 12 12 144 clb auto 0.12 631 0.27 0.00 40 1720 12 5.66058e+06 3.99722e+06 360333. 2502.31 0.41 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_pack/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_pack/config/golden_results.txt index 3bcd8702b9b..943d0d07244 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_pack/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_pack/config/golden_results.txt @@ -1,2 +1,2 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6_N10_mem32K_40nm.xml stereovision3.v common 0.78 0.04 9352 4 0.11 -1 -1 33068 -1 -1 19 11 0 0 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_pack/run014/k6_N10_mem32K_40nm.xml/stereovision3.v/common 27252 11 30 262 292 2 104 60 7 7 49 clb auto 0.06 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.000398583 0.000303303 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_mem32K_40nm.xml stereovision3.v common 2.61 0.04 9288 4 0.13 -1 -1 37008 -1 -1 18 11 0 0 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_pack/run013/k6_N10_mem32K_40nm.xml/stereovision3.v/common 23756 11 29 257 286 2 102 58 7 7 49 clb auto 0.06 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.000334924 0.000256792 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_pack_and_place/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_pack_and_place/config/golden_results.txt index 815f7cf0806..4be9119cd3d 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_pack_and_place/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_pack_and_place/config/golden_results.txt @@ -1,2 +1,2 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6_N10_mem32K_40nm.xml stereovision3.v common 0.98 0.05 9284 4 0.12 -1 -1 33040 -1 -1 19 11 0 0 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_pack_and_place/run014/k6_N10_mem32K_40nm.xml/stereovision3.v/common 28084 11 30 262 292 2 104 60 7 7 49 clb auto 0.07 395 0.12 0.00 2.22041 -166.454 -2.22041 2.11404 0.000341291 0.000270976 0.0326007 0.0252046 -1 -1 -1 -1 -1 -1 -1 -1 0.0330103 0.0255164 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_mem32K_40nm.xml stereovision3.v common 2.76 0.04 9296 4 0.14 -1 -1 37108 -1 -1 18 11 0 0 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_pack_and_place/run013/k6_N10_mem32K_40nm.xml/stereovision3.v/common 23788 11 29 257 286 2 102 58 7 7 49 clb auto 0.06 364 0.14 0.00 2.20202 -161.339 -2.20202 2.10527 0.000227565 0.000171411 0.0276284 0.0210855 -1 -1 -1 -1 -1 -1 -1 -1 0.027964 0.021346 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_pack_disable/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_pack_disable/config/golden_results.txt index 26e1a3ba7e2..cb5d64e8449 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_pack_disable/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_pack_disable/config/golden_results.txt @@ -1,3 +1,3 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time -k6_frac_N10_40nm.xml mult_5x6.blif common 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 11 -1 -1 success v8.0.0-1769-gb0af4b978-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1062.9.1.el7.x86_64 x86_64 2020-05-21T12:42:01 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_pack_disable/run001/k6_frac_N10_40nm.xml/mult_5x6.blif/common 12024 11 11 59 70 0 48 26 4 4 16 clb auto 0.04 155 0.04 2.26753 -18.3823 -2.26753 30 250 46 215576 215576 18771.3 1173.21 0.12 215 14 228 489 11159 6264 2.8603 nan -23.4652 -2.8603 0 0 22855.5 1428.47 0.01 -k6_frac_N10_40nm_disable_packing.xml mult_5x6.blif common 0.09 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 exited with return code 1 v8.0.0-1769-gb0af4b978-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 8.4.0 on Linux-3.10.0-1062.9.1.el7.x86_64 x86_64 2020-05-21T12:42:01 lnissrv4.eng.utah.edu /research/ece/lnis/USERS/tang/github/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_pack_disable/run001/k6_frac_N10_40nm_disable_packing.xml/mult_5x6.blif/common 10368 11 11 59 70 0 -1 -1 -1 -1 -1 -1 -1 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_40nm.xml mult_5x6.blif common 0.25 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 11 -1 -1 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_pack_disable/run008/k6_frac_N10_40nm.xml/mult_5x6.blif/common 19240 11 11 59 70 0 48 26 4 4 16 clb auto 0.02 155 0.04 0.00 2.26753 -18.3823 -2.26753 nan 6.0061e-05 4.4781e-05 0.00709431 0.00556291 30 250 46 215576 215576 18771.3 1173.21 0.05 0.0205867 0.0170411 215 14 228 489 11159 6264 2.8603 nan -23.4652 -2.8603 0 0 22855.5 1428.47 0.01 0.00410298 0.00376333 +k6_frac_N10_40nm_disable_packing.xml mult_5x6.blif common 0.02 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 exited with return code 1 v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_pack_disable/run008/k6_frac_N10_40nm_disable_packing.xml/mult_5x6.blif/common 18200 11 11 59 70 0 -1 -1 -1 -1 -1 -1 -1 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_delay_calc_method/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_delay_calc_method/config/golden_results.txt index 4b4fbdbad73..031e23c4bc6 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_delay_calc_method/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_delay_calc_method/config/golden_results.txt @@ -1,5 +1,5 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time -stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta_--place_delta_delay_matrix_calculation_method_astar 19.43 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-2157-g60090c4a9 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-08-18T05:21:02 betzgrp-wintermute.eecg.utoronto.ca /home/daixiao4/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_delay_calc_method/run002/stratixiv_arch.timing.xml/styr.blif/common_--place_delay_model_delta_--place_delta_delay_matrix_calculation_method_astar 785600 10 10 168 178 1 62 30 11 8 88 io auto 0.33 338 1.50 0.00 6.42475 -70.0057 -6.42475 6.42475 0.000210069 0.000170001 0.0206966 0.016419 18 790 16 0 0 88905.3 1010.29 0.40 0.0538882 0.0445886 639 12 269 1020 106260 54300 6.98692 6.98692 -75.0776 -6.98692 0 0 114811. 1304.67 0.04 0.0125945 0.0115189 -stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta_override_--place_delta_delay_matrix_calculation_method_astar 20.14 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-2157-g60090c4a9 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-08-18T05:21:02 betzgrp-wintermute.eecg.utoronto.ca /home/daixiao4/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_delay_calc_method/run002/stratixiv_arch.timing.xml/styr.blif/common_--place_delay_model_delta_override_--place_delta_delay_matrix_calculation_method_astar 785616 10 10 168 178 1 62 30 11 8 88 io auto 0.33 332 1.50 0.00 6.5579 -69.9738 -6.5579 6.5579 0.000295816 0.000220692 0.0229095 0.01789 16 871 17 0 0 80336.7 912.917 1.10 0.084033 0.0679953 718 14 322 1131 133881 69813 7.11693 7.11693 -77.5537 -7.11693 0 0 100211. 1138.76 0.04 0.0132427 0.0120206 -stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta_--place_delta_delay_matrix_calculation_method_dijkstra 20.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-2157-g60090c4a9 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-08-18T05:21:02 betzgrp-wintermute.eecg.utoronto.ca /home/daixiao4/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_delay_calc_method/run002/stratixiv_arch.timing.xml/styr.blif/common_--place_delay_model_delta_--place_delta_delay_matrix_calculation_method_dijkstra 785404 10 10 168 178 1 62 30 11 8 88 io auto 0.33 347 1.97 0.00 6.26392 -68.7055 -6.26392 6.26392 0.000228263 0.000173269 0.0213126 0.0166803 16 889 21 0 0 80336.7 912.917 0.47 0.0574665 0.0469206 727 14 387 1575 164654 85947 6.94009 6.94009 -77.0502 -6.94009 0 0 100211. 1138.76 0.04 0.0132417 0.0119827 -stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta_override_--place_delta_delay_matrix_calculation_method_dijkstra 20.34 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-2157-g60090c4a9 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-08-18T05:21:02 betzgrp-wintermute.eecg.utoronto.ca /home/daixiao4/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_delay_calc_method/run002/stratixiv_arch.timing.xml/styr.blif/common_--place_delay_model_delta_override_--place_delta_delay_matrix_calculation_method_dijkstra 788772 10 10 168 178 1 62 30 11 8 88 io auto 0.34 349 1.98 0.00 6.58215 -68.9146 -6.58215 6.58215 0.00020901 0.000173343 0.0206752 0.0164291 28 680 15 0 0 134307. 1526.22 0.74 0.0839271 0.0692388 555 12 233 818 105815 48725 6.96661 6.96661 -73.0028 -6.96661 0 0 173484. 1971.41 0.04 0.0123703 0.0113118 +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time +stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta_--place_delta_delay_matrix_calculation_method_astar 20.70 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_delay_calc_method/run010/stratixiv_arch.timing.xml/styr.blif/common_--place_delay_model_delta_--place_delta_delay_matrix_calculation_method_astar 768472 10 10 168 178 1 62 30 11 8 88 io auto 0.43 338 2.04 0.00 6.42475 -70.0057 -6.42475 6.42475 0.000200496 0.000160581 0.0188988 0.0153899 18 790 16 0 0 88905.3 1010.29 0.43 0.0561867 0.0480067 639 12 269 1020 106260 54300 6.98692 6.98692 -75.0776 -6.98692 0 0 114811. 1304.67 0.04 0.0151667 0.0141682 +stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta_override_--place_delta_delay_matrix_calculation_method_astar 20.14 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_delay_calc_method/run010/stratixiv_arch.timing.xml/styr.blif/common_--place_delay_model_delta_override_--place_delta_delay_matrix_calculation_method_astar 768672 10 10 168 178 1 62 30 11 8 88 io auto 0.47 332 2.02 0.00 6.5579 -69.9738 -6.5579 6.5579 0.000200406 0.000153964 0.0193001 0.0156624 16 871 17 0 0 80336.7 912.917 0.53 0.0590304 0.0503817 718 14 322 1131 133881 69813 7.11693 7.11693 -77.5537 -7.11693 0 0 100211. 1138.76 0.05 0.0156472 0.0145533 +stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta_--place_delta_delay_matrix_calculation_method_dijkstra 19.88 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_delay_calc_method/run010/stratixiv_arch.timing.xml/styr.blif/common_--place_delay_model_delta_--place_delta_delay_matrix_calculation_method_dijkstra 768544 10 10 168 178 1 62 30 11 8 88 io auto 0.41 347 2.41 0.00 6.26392 -68.7055 -6.26392 6.26392 0.000183855 0.000141006 0.0183151 0.01484 16 889 21 0 0 80336.7 912.917 0.51 0.0582436 0.0496632 727 14 387 1575 164654 85947 6.94009 6.94009 -77.0502 -6.94009 0 0 100211. 1138.76 0.04 0.0135522 0.0125777 +stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta_override_--place_delta_delay_matrix_calculation_method_dijkstra 20.31 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_delay_calc_method/run010/stratixiv_arch.timing.xml/styr.blif/common_--place_delay_model_delta_override_--place_delta_delay_matrix_calculation_method_dijkstra 768584 10 10 168 178 1 62 30 11 8 88 io auto 0.43 349 2.53 0.00 6.58215 -68.9146 -6.58215 6.58215 0.000175394 0.000139893 0.0171825 0.013961 28 680 15 0 0 134307. 1526.22 0.38 0.0540425 0.0463507 555 12 233 818 105815 48725 6.96661 6.96661 -73.0028 -6.96661 0 0 173484. 1971.41 0.03 0.0133279 0.0124768 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_delay_model/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_delay_model/config/golden_results.txt index 286a94df90c..bb2dc3e1977 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_delay_model/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_delay_model/config/golden_results.txt @@ -1,3 +1,3 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time -stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta 19.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-2157-g60090c4a9 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-08-18T05:21:02 betzgrp-wintermute.eecg.utoronto.ca /home/daixiao4/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_delay_model/run002/stratixiv_arch.timing.xml/styr.blif/common_--place_delay_model_delta 786656 10 10 168 178 1 62 30 11 8 88 io auto 0.33 338 1.50 0.00 6.42475 -70.0057 -6.42475 6.42475 0.000213653 0.000172023 0.0208692 0.0165288 18 790 16 0 0 88905.3 1010.29 0.40 0.0546836 0.0452492 639 12 269 1020 106260 54300 6.98692 6.98692 -75.0776 -6.98692 0 0 114811. 1304.67 0.04 0.0124049 0.0113595 -stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta_override 20.10 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-2157-g60090c4a9 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-08-18T05:21:02 betzgrp-wintermute.eecg.utoronto.ca /home/daixiao4/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_delay_model/run002/stratixiv_arch.timing.xml/styr.blif/common_--place_delay_model_delta_override 785496 10 10 168 178 1 62 30 11 8 88 io auto 0.33 332 1.51 0.00 6.5579 -69.9738 -6.5579 6.5579 0.000246646 0.000189851 0.0210186 0.0164993 16 871 17 0 0 80336.7 912.917 1.08 0.0817692 0.0662263 718 14 322 1131 133881 69813 7.11693 7.11693 -77.5537 -7.11693 0 0 100211. 1138.76 0.04 0.0130732 0.0118572 +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time +stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta 19.62 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_delay_model/run010/stratixiv_arch.timing.xml/styr.blif/common_--place_delay_model_delta 768672 10 10 168 178 1 62 30 11 8 88 io auto 0.39 338 1.80 0.00 6.42475 -70.0057 -6.42475 6.42475 0.000174474 0.000138268 0.017206 0.0139288 18 790 16 0 0 88905.3 1010.29 0.40 0.051539 0.0439088 639 12 269 1020 106260 54300 6.98692 6.98692 -75.0776 -6.98692 0 0 114811. 1304.67 0.04 0.0140411 0.0131447 +stratixiv_arch.timing.xml styr.blif common_--place_delay_model_delta_override 20.08 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10 -1 -1 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_delay_model/run010/stratixiv_arch.timing.xml/styr.blif/common_--place_delay_model_delta_override 768568 10 10 168 178 1 62 30 11 8 88 io auto 0.41 332 1.85 0.00 6.5579 -69.9738 -6.5579 6.5579 0.000185242 0.000140302 0.0178184 0.0143209 16 871 17 0 0 80336.7 912.917 0.48 0.0525002 0.0444245 718 14 322 1131 133881 69813 7.11693 7.11693 -77.5537 -7.11693 0 0 100211. 1138.76 0.04 0.0147666 0.013719 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_effort_scaling/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_effort_scaling/config/golden_results.txt index f7b6c3bc5c0..4e8c724f3e2 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_effort_scaling/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_effort_scaling/config/golden_results.txt @@ -1,5 +1,5 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time -EArch.xml ex5p.blif common_--place_effort_scaling_circuit 2.15 -1 -1 -1 -1 -1 -1 -1 -1 -1 59 8 0 0 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_effort_scaling/run004/EArch.xml/ex5p.blif/common_--place_effort_scaling_circuit 40432 8 63 1072 1135 0 632 130 11 11 121 clb auto 1.09 5949 0.65 0.00 4.5988 -192.739 -4.5988 nan 0.00102661 0.000765209 0.134072 0.102888 -1 -1 -1 -1 -1 -1 -1 -1 0.13539 0.103905 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -EArch.xml ex5p.blif common_--place_effort_scaling_device_circuit 2.35 -1 -1 -1 -1 -1 -1 -1 -1 -1 59 8 0 0 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_effort_scaling/run004/EArch.xml/ex5p.blif/common_--place_effort_scaling_device_circuit 40308 8 63 1072 1135 0 632 130 11 11 121 clb auto 1.23 5986 0.69 0.00 4.55938 -193.607 -4.55938 nan 0.000997948 0.000748922 0.142982 0.109904 -1 -1 -1 -1 -1 -1 -1 -1 0.145309 0.111707 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -EArch.xml ex5p.blif common_--place_effort_scaling_circuit_--target_utilization_0.1 4.89 -1 -1 -1 -1 -1 -1 -1 -1 -1 59 8 0 0 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_effort_scaling/run004/EArch.xml/ex5p.blif/common_--place_effort_scaling_circuit_--target_utilization_0.1 65408 8 63 1072 1135 0 632 130 27 27 729 -1 auto 1.11 6736 1.94 0.00 5.04695 -230.507 -5.04695 nan 0.000998492 0.000738891 0.141988 0.108922 -1 -1 -1 -1 -1 -1 -1 -1 0.14332 0.109944 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -EArch.xml ex5p.blif common_--place_effort_scaling_device_circuit_--target_utilization_0.1 5.44 -1 -1 -1 -1 -1 -1 -1 -1 -1 59 8 0 0 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_effort_scaling/run004/EArch.xml/ex5p.blif/common_--place_effort_scaling_device_circuit_--target_utilization_0.1 65296 8 63 1072 1135 0 632 130 27 27 729 -1 auto 1.10 6023 2.55 0.01 4.57207 -199.792 -4.57207 nan 0.000994746 0.000736193 0.146404 0.112325 -1 -1 -1 -1 -1 -1 -1 -1 0.14773 0.113354 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time +EArch.xml ex5p.blif common_--place_effort_scaling_circuit 3.03 -1 -1 -1 -1 -1 -1 -1 -1 -1 59 8 0 0 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_effort_scaling/run008/EArch.xml/ex5p.blif/common_--place_effort_scaling_circuit 35624 8 63 1072 1135 0 632 130 11 11 121 clb auto 1.38 5950 1.21 0.01 4.5988 -192.739 -4.5988 nan 0.00127896 0.00101799 0.160962 0.131211 -1 -1 -1 -1 -1 -1 -1 -1 0.162658 0.132603 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +EArch.xml ex5p.blif common_--place_effort_scaling_device_circuit 3.01 -1 -1 -1 -1 -1 -1 -1 -1 -1 59 8 0 0 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_effort_scaling/run008/EArch.xml/ex5p.blif/common_--place_effort_scaling_device_circuit 35640 8 63 1072 1135 0 632 130 11 11 121 clb auto 1.38 5987 1.21 0.01 4.55938 -193.607 -4.55938 nan 0.00128836 0.00104402 0.165915 0.135483 -1 -1 -1 -1 -1 -1 -1 -1 0.167634 0.136894 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +EArch.xml ex5p.blif common_--place_effort_scaling_circuit_--target_utilization_0.1 5.86 -1 -1 -1 -1 -1 -1 -1 -1 -1 59 8 0 0 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_effort_scaling/run008/EArch.xml/ex5p.blif/common_--place_effort_scaling_circuit_--target_utilization_0.1 59668 8 63 1072 1135 0 632 130 27 27 729 -1 auto 1.37 6738 2.62 0.01 5.04695 -230.507 -5.04695 nan 0.00127997 0.000999272 0.176541 0.143379 -1 -1 -1 -1 -1 -1 -1 -1 0.178464 0.144963 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +EArch.xml ex5p.blif common_--place_effort_scaling_device_circuit_--target_utilization_0.1 7.34 -1 -1 -1 -1 -1 -1 -1 -1 -1 59 8 0 0 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_place_effort_scaling/run008/EArch.xml/ex5p.blif/common_--place_effort_scaling_device_circuit_--target_utilization_0.1 59720 8 63 1072 1135 0 632 130 27 27 729 -1 auto 1.35 6024 4.12 0.02 4.57207 -199.792 -4.57207 nan 0.00122883 0.000981444 0.182028 0.148445 -1 -1 -1 -1 -1 -1 -1 -1 0.183827 0.149932 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_power/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_power/config/golden_results.txt index 5ace834bbc0..2cc56b34fcb 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_power/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_power/config/golden_results.txt @@ -1,3 +1,3 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time total_power routing_power_perc clock_power_perc tile_power_perc -k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common 3.03 0.04 9032 3 0.23 -1 -1 36184 -1 52324 65 99 1 0 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_power/run015/k6_frac_N10_mem32K_40nm.xml/ch_intrinsics.v/common 38012 99 130 363 493 1 251 295 12 12 144 clb auto 0.14 649 0.50 0.00 1.83922 -196.437 -1.83922 1.83922 0.000405138 0.000348938 0.0569279 0.0489824 52 1344 14 5.66058e+06 4.05111e+06 419432. 2912.72 0.61 0.160688 0.142471 1268 10 547 697 50558 16348 2.26669 2.26669 -234.063 -2.26669 0 0 551878. 3832.49 0.03 0.0141372 0.013132 0.009993 0.2128 0.07602 0.7112 -k6_frac_N10_mem32K_40nm.xml diffeq1.v common 8.15 0.02 8788 15 0.30 -1 -1 34660 -1 54084 36 162 0 5 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_power/run015/k6_frac_N10_mem32K_40nm.xml/diffeq1.v/common 48288 162 96 999 932 1 693 299 16 16 256 mult_36 auto 0.27 5309 1.03 0.00 19.796 -1786.28 -19.796 19.796 0.00136819 0.00121722 0.201032 0.176641 48 12568 47 1.21132e+07 3.92018e+06 756778. 2956.16 3.39 0.64297 0.577124 10180 19 3169 6154 2037599 497337 22.4129 22.4129 -2167.74 -22.4129 0 0 968034. 3781.38 0.30 0.0770259 0.0717386 0.007913 0.3536 0.01655 0.6298 +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time total_power routing_power_perc clock_power_perc tile_power_perc +k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common 7.97 0.03 9024 3 0.22 -1 -1 37824 -1 54028 65 99 1 0 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_power/run013/k6_frac_N10_mem32K_40nm.xml/ch_intrinsics.v/common 29880 99 130 363 493 1 251 295 12 12 144 clb auto 0.09 649 0.60 0.00 1.83922 -196.437 -1.83922 1.83922 0.000409344 0.000356977 0.0536299 0.0469513 52 1344 14 5.66058e+06 4.05111e+06 419432. 2912.72 0.56 0.146733 0.131888 1268 10 547 697 50558 16348 2.26669 2.26669 -234.063 -2.26669 0 0 551878. 3832.49 0.03 0.014958 0.0140973 0.009993 0.2128 0.07602 0.7112 +k6_frac_N10_mem32K_40nm.xml diffeq1.v common 14.03 0.02 8780 15 0.32 -1 -1 38692 -1 55900 36 162 0 5 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_power/run013/k6_frac_N10_mem32K_40nm.xml/diffeq1.v/common 39780 162 96 999 932 1 693 299 16 16 256 mult_36 auto 0.29 5309 1.48 0.01 19.796 -1786.28 -19.796 19.796 0.00151913 0.00135746 0.220899 0.197441 48 12568 47 1.21132e+07 3.92018e+06 756778. 2956.16 3.81 0.697207 0.633889 10180 19 3169 6154 2037599 497337 22.4129 22.4129 -2167.74 -22.4129 0 0 968034. 3781.38 0.36 0.0924262 0.0866667 0.007913 0.3536 0.01655 0.6298 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_route_only/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_route_only/config/golden_results.txt index f8aa36ac962..3ca3df50ce4 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_route_only/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_route_only/config/golden_results.txt @@ -1,3 +1,3 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6_N10_mem32K_40nm.xml stereovision3.v common 1.24 0.04 9252 4 0.13 -1 -1 33012 -1 -1 19 11 0 0 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_route_only/run014/k6_N10_mem32K_40nm.xml/stereovision3.v/common 28796 11 30 262 292 2 104 60 7 7 49 clb auto 0.09 411 0.08 0.00 2.21827 -167.491 -2.21827 2.12157 0.000286099 0.000229625 0.0335546 0.0259543 476 706 1762 86557 15062 1.07788e+06 1.02399e+06 207176. 4228.08 21 2.37477 2.25251 -178.461 -2.37477 0 0 0.03 0.0516532 0.0413056 -k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 1.50 0.06 9556 5 0.10 -1 -1 33256 -1 -1 14 11 0 0 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_route_only/run014/k6_frac_N10_frac_chain_mem32K_40nm.xml/stereovision3.v/common 31232 11 30 313 321 2 117 55 7 7 49 clb auto 0.27 389 0.11 0.00 2.27833 -153.323 -2.27833 2.06764 0.000549577 0.000448282 0.0538636 0.0429385 524 235 443 11245 3448 1.07788e+06 754516 219490. 4479.39 8 2.4554 2.27846 -166.763 -2.4554 0 0 0.03 0.0765967 0.0638709 +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_mem32K_40nm.xml stereovision3.v common 2.75 0.04 9308 4 0.11 -1 -1 37120 -1 -1 18 11 0 0 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_route_only/run013/k6_N10_mem32K_40nm.xml/stereovision3.v/common 24416 11 29 257 286 2 102 58 7 7 49 clb auto 0.06 370 0.09 0.00 2.20099 -163.509 -2.20099 2.10428 0.000239831 0.000182466 0.0266923 0.0202772 429 861 1916 96733 17314 1.07788e+06 970092 207176. 4228.08 20 2.22326 2.17156 -175.185 -2.22326 0 0 0.03 0.0426791 0.0341686 +k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 3.06 0.04 9348 5 0.10 -1 -1 36832 -1 -1 13 11 0 0 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_route_only/run013/k6_frac_N10_frac_chain_mem32K_40nm.xml/stereovision3.v/common 26452 11 29 301 308 2 120 53 7 7 49 clb auto 0.32 409 0.11 0.00 2.29324 -153.859 -2.29324 2.05363 0.000245713 0.000185094 0.0352054 0.0270199 620 251 401 16466 5063 1.07788e+06 700622 219490. 4479.39 11 2.71041 2.4269 -177.871 -2.71041 0 0 0.02 0.0512182 0.0417726 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_route_reconverge/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_route_reconverge/config/golden_results.txt index 2081e02fbbc..741a190a8a4 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_route_reconverge/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_route_reconverge/config/golden_results.txt @@ -1,2 +1,2 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml mkSMAdapter4B.v common 20.02 0.26 30784 4 1.81 -1 -1 39784 -1 -1 167 193 5 0 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_route_reconverge/run011/k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml/mkSMAdapter4B.v/common 71568 193 205 2926 2852 1 1371 570 20 20 400 memory auto 1.33 10454 2.60 0.01 4.17962 -2464.62 -4.17962 4.17962 0.00299973 0.00239168 0.46302 0.37433 80 20576 39 2.07112e+07 1.17403e+07 2.10510e+06 5262.74 10.51 1.74356 1.49433 18693 17 5010 14283 1459244 324974 4.84767 4.84767 -2845.86 -4.84767 -12.6591 -0.360359 2.64606e+06 6615.15 0.36 0.189262 0.17394 +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml mkSMAdapter4B.v common 21.28 0.22 30532 4 1.82 -1 -1 41668 -1 -1 167 193 5 0 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_route_reconverge/run013/k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml/mkSMAdapter4B.v/common 65600 193 205 2926 2852 1 1371 570 20 20 400 memory auto 1.60 10767 4.73 0.03 4.38764 -2424.87 -4.38764 4.38764 0.00381377 0.00318619 0.597844 0.494515 76 21689 43 2.07112e+07 1.17403e+07 2.02110e+06 5052.76 7.08 1.76351 1.51391 20197 18 5498 15422 1697659 365914 4.80242 4.80242 -2890.94 -4.80242 -6.70715 -0.340786 2.51807e+06 6295.18 0.54 0.250606 0.230155 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_router_init_timing/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_router_init_timing/config/golden_results.txt index 44d1d2087d9..a30b5a71e10 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_router_init_timing/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_router_init_timing/config/golden_results.txt @@ -1,3 +1,3 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6_N10_mem32K_40nm.xml ex5p.blif common_--router_initial_timing_all_critical 1.34 -1 -1 -1 -1 -1 -1 -1 -1 -1 80 8 0 0 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_router_init_timing/run011/k6_N10_mem32K_40nm.xml/ex5p.blif/common_--router_initial_timing_all_critical 38260 8 63 748 811 0 474 151 13 13 169 clb auto 0.28 4625 0.44 0.00 3.81146 -161.595 -3.81146 nan 0.00150047 0.00109178 0.127492 0.0990043 6362 3946 14540 677760 102374 6.63067e+06 4.31152e+06 714925. 4230.32 23 4.24514 nan -182.157 -4.24514 0 0 0.19 0.208624 0.170839 -k6_N10_mem32K_40nm.xml ex5p.blif common_--router_initial_timing_lookahead 1.32 -1 -1 -1 -1 -1 -1 -1 -1 -1 80 8 0 0 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_router_init_timing/run011/k6_N10_mem32K_40nm.xml/ex5p.blif/common_--router_initial_timing_lookahead 38368 8 63 748 811 0 474 151 13 13 169 clb auto 0.29 4625 0.40 0.00 3.81146 -161.595 -3.81146 nan 0.000965051 0.000715673 0.110265 0.084314 6509 4453 16911 764005 114794 6.63067e+06 4.31152e+06 714925. 4230.32 32 4.15613 nan -185.233 -4.15613 0 0 0.22 0.20245 0.164438 +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_mem32K_40nm.xml ex5p.blif common_--router_initial_timing_all_critical 1.82 -1 -1 -1 -1 -1 -1 -1 -1 -1 80 8 0 0 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_router_init_timing/run009/k6_N10_mem32K_40nm.xml/ex5p.blif/common_--router_initial_timing_all_critical 34656 8 63 748 811 0 474 151 13 13 169 clb auto 0.30 4625 0.79 0.01 3.81146 -161.595 -3.81146 nan 0.0012323 0.000970735 0.132069 0.108005 6362 3946 14540 677760 102374 6.63067e+06 4.31152e+06 714925. 4230.32 23 4.24514 nan -182.157 -4.24514 0 0 0.24 0.222905 0.188988 +k6_N10_mem32K_40nm.xml ex5p.blif common_--router_initial_timing_lookahead 1.75 -1 -1 -1 -1 -1 -1 -1 -1 -1 80 8 0 0 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_router_init_timing/run009/k6_N10_mem32K_40nm.xml/ex5p.blif/common_--router_initial_timing_lookahead 34560 8 63 748 811 0 474 151 13 13 169 clb auto 0.30 4625 0.77 0.01 3.81146 -161.595 -3.81146 nan 0.00109387 0.000852047 0.1279 0.104409 6509 4453 16911 764005 114794 6.63067e+06 4.31152e+06 714925. 4230.32 32 4.15613 nan -185.233 -4.15613 0 0 0.28 0.23067 0.195527 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_router_lookahead/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_router_lookahead/config/golden_results.txt index 1e62b8fda48..9e5e0ebc006 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_router_lookahead/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_router_lookahead/config/golden_results.txt @@ -1,3 +1,3 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6_N10_mem32K_40nm.xml ex5p.blif common_--router_lookahead_classic 1.39 -1 -1 -1 -1 -1 -1 -1 -1 -1 80 8 0 0 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_router_lookahead/run014/k6_N10_mem32K_40nm.xml/ex5p.blif/common_--router_lookahead_classic 38504 8 63 748 811 0 474 151 13 13 169 clb auto 0.29 4714 0.52 0.00 3.70871 -159.069 -3.70871 nan 0.000962558 0.000710169 0.147775 0.113669 6802 4803 18126 1410663 241971 6.63067e+06 4.31152e+06 558096. 3302.35 31 4.15097 nan -183.347 -4.15097 0 0 0.29 0.246723 0.200214 -k6_N10_mem32K_40nm.xml ex5p.blif common_--router_lookahead_map 1.28 -1 -1 -1 -1 -1 -1 -1 -1 -1 80 8 0 0 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_router_lookahead/run014/k6_N10_mem32K_40nm.xml/ex5p.blif/common_--router_lookahead_map 37744 8 63 748 811 0 474 151 13 13 169 clb auto 0.27 4774 0.45 0.00 3.68749 -162.239 -3.68749 nan 0.000979309 0.000718807 0.123995 0.094656 6885 4550 17546 783482 128874 6.63067e+06 4.31152e+06 558096. 3302.35 25 4.28104 nan -189.84 -4.28104 0 0 0.21 0.206307 0.167057 +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_mem32K_40nm.xml ex5p.blif common_--router_lookahead_classic 1.69 -1 -1 -1 -1 -1 -1 -1 -1 -1 80 8 0 0 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_router_lookahead/run008/k6_N10_mem32K_40nm.xml/ex5p.blif/common_--router_lookahead_classic 34240 8 63 748 811 0 474 151 13 13 169 clb auto 0.29 4714 0.80 0.01 3.70871 -159.069 -3.70871 nan 0.00123665 0.000987506 0.134885 0.111148 6802 4803 18126 1410663 241971 6.63067e+06 4.31152e+06 558096. 3302.35 31 4.15097 nan -183.347 -4.15097 0 0 0.35 0.246382 0.210321 +k6_N10_mem32K_40nm.xml ex5p.blif common_--router_lookahead_map 1.76 -1 -1 -1 -1 -1 -1 -1 -1 -1 80 8 0 0 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_router_lookahead/run008/k6_N10_mem32K_40nm.xml/ex5p.blif/common_--router_lookahead_map 34336 8 63 748 811 0 474 151 13 13 169 clb auto 0.31 4774 0.80 0.01 3.68749 -162.239 -3.68749 nan 0.00126444 0.00100491 0.137521 0.112941 6885 4550 17546 783482 128874 6.63067e+06 4.31152e+06 558096. 3302.35 25 4.28104 nan -189.84 -4.28104 0 0 0.28 0.234119 0.198792 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_router_update_lb_delays/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_router_update_lb_delays/config/golden_results.txt index 3e4fba874e8..183b8f6149e 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_router_update_lb_delays/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_router_update_lb_delays/config/golden_results.txt @@ -1,3 +1,3 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6_N10_mem32K_40nm.xml ex5p.blif common_--router_update_lower_bound_delays_off 1.34 -1 -1 -1 -1 -1 -1 -1 -1 -1 80 8 0 0 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_router_update_lb_delays/run011/k6_N10_mem32K_40nm.xml/ex5p.blif/common_--router_update_lower_bound_delays_off 38780 8 63 748 811 0 474 151 13 13 169 clb auto 0.26 4637 0.51 0.00 3.90481 -171.483 -3.90481 nan 0.000949892 0.000701354 0.141238 0.107461 6533 3905 14523 665599 104616 6.63067e+06 4.31152e+06 648366. 3836.48 22 4.19585 nan -190.835 -4.19585 0 0 0.18 0.214983 0.172742 -k6_N10_mem32K_40nm.xml ex5p.blif common_--router_update_lower_bound_delays_on 1.26 -1 -1 -1 -1 -1 -1 -1 -1 -1 80 8 0 0 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_router_update_lb_delays/run011/k6_N10_mem32K_40nm.xml/ex5p.blif/common_--router_update_lower_bound_delays_on 38900 8 63 748 811 0 474 151 13 13 169 clb auto 0.29 4637 0.40 0.00 3.90481 -171.483 -3.90481 nan 0.000937804 0.00069632 0.107439 0.0822581 6549 3830 14383 660219 104384 6.63067e+06 4.31152e+06 648366. 3836.48 19 4.19585 nan -192.564 -4.19585 0 0 0.17 0.17892 0.145456 +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_mem32K_40nm.xml ex5p.blif common_--router_update_lower_bound_delays_off 1.65 -1 -1 -1 -1 -1 -1 -1 -1 -1 80 8 0 0 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_router_update_lb_delays/run009/k6_N10_mem32K_40nm.xml/ex5p.blif/common_--router_update_lower_bound_delays_off 34416 8 63 748 811 0 474 151 13 13 169 clb auto 0.29 4637 0.76 0.01 3.90481 -171.483 -3.90481 nan 0.00114557 0.00090854 0.130241 0.107469 6533 3905 14523 665599 104616 6.63067e+06 4.31152e+06 648366. 3836.48 22 4.19585 nan -190.835 -4.19585 0 0 0.22 0.214463 0.18305 +k6_N10_mem32K_40nm.xml ex5p.blif common_--router_update_lower_bound_delays_on 1.65 -1 -1 -1 -1 -1 -1 -1 -1 -1 80 8 0 0 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_router_update_lb_delays/run009/k6_N10_mem32K_40nm.xml/ex5p.blif/common_--router_update_lower_bound_delays_on 34476 8 63 748 811 0 474 151 13 13 169 clb auto 0.28 4637 0.78 0.01 3.90481 -171.483 -3.90481 nan 0.00128434 0.00102998 0.130394 0.107241 6549 3830 14383 660219 104384 6.63067e+06 4.31152e+06 648366. 3836.48 19 4.19585 nan -192.564 -4.19585 0 0 0.22 0.210697 0.179788 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_routing_differing_modes/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_routing_differing_modes/config/golden_results.txt index a6a943d254b..12c20b42316 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_routing_differing_modes/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_routing_differing_modes/config/golden_results.txt @@ -1,2 +1,2 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time -slicem.xml carry_chain.blif common 0.47 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 -1 -1 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_routing_differing_modes/run014/slicem.xml/carry_chain.blif/common 19572 1 -1 48 34 1 32 5 4 4 16 BLK_IG-SLICEM auto 0.16 65 0.02 0.00 0.55434 -5.54475 -0.55434 0.55434 8.727e-05 7.1791e-05 0.0100323 0.00811205 27 213 21 59253.6 59253.6 -1 -1 0.09 0.0302786 0.02379 164 12 95 95 20812 11936 1.25215 1.25215 -10.6324 -1.25215 0 0 -1 -1 0.01 0.0022928 0.00191969 +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time +slicem.xml carry_chain.blif common 0.37 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 1 -1 -1 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_routing_differing_modes/run008/slicem.xml/carry_chain.blif/common 18200 1 -1 48 34 1 32 5 4 4 16 BLK_IG-SLICEM auto 0.10 65 0.01 0.00 0.55434 -5.54475 -0.55434 0.55434 2.803e-05 2.0093e-05 0.00279824 0.00205896 25 166 19 59253.6 59253.6 -1 -1 0.12 0.0155611 0.0121182 202 17 135 135 27745 16606 1.45253 1.45253 -14.0154 -1.45253 0 0 -1 -1 0.01 0.00177609 0.00153799 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_routing_modes/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_routing_modes/config/golden_results.txt index 5ec06ab0857..3c858f81932 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_routing_modes/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_routing_modes/config/golden_results.txt @@ -1,2 +1,2 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time -arch.xml ndff.blif common 0.18 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 -1 -1 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_routing_modes/run014/arch.xml/ndff.blif/common 18512 4 4 10 14 1 10 11 4 4 16 ff_tile io_tile auto 0.00 23 0.01 0.00 0.198362 -1.99999 -0.198362 0.198362 2.588e-05 1.7338e-05 0.00289752 0.00192378 4 25 13 59253.6 44440.2 -1 -1 0.02 0.00547603 0.00363759 26 2 15 20 897 403 0.260484 0.260484 -2.61426 -0.260484 0 0 -1 -1 0.00 0.000397896 0.000295969 +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time +arch.xml ndff.blif common 0.13 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 4 -1 -1 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_routing_modes/run008/arch.xml/ndff.blif/common 17524 4 4 10 14 1 10 11 4 4 16 ff_tile io_tile auto 0.00 23 0.01 0.00 0.198362 -1.99999 -0.198362 0.198362 1.0012e-05 5.912e-06 0.00113169 0.00065181 4 25 13 59253.6 44440.2 -1 -1 0.01 0.00239454 0.00153253 26 2 15 20 897 403 0.260484 0.260484 -2.61426 -0.260484 0 0 -1 -1 0.00 0.00017686 0.00014693 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_scale_delay_budgets/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_scale_delay_budgets/config/golden_results.txt index a786cc3dac8..ac016188391 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_scale_delay_budgets/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_scale_delay_budgets/config/golden_results.txt @@ -1,2 +1,2 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 1.23 0.06 9472 5 0.10 -1 -1 33224 -1 -1 15 11 0 0 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_scale_delay_budgets/run014/k6_frac_N10_frac_chain_mem32K_40nm.xml/stereovision3.v/common 30972 11 30 313 321 2 114 56 7 7 49 clb auto 0.23 382 0.09 0.00 4.29791 0 0 4.13033 0.000325202 0.000271371 0.0433681 0.0355896 581 172 326 11476 3370 1.07788e+06 808410 219490. 4479.39 6 4.57733 4.27235 0 0 -164.701 -1.707 0.02 0.0558825 0.0472557 +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 3.04 0.04 9268 5 0.12 -1 -1 36776 -1 -1 13 11 0 0 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_scale_delay_budgets/run013/k6_frac_N10_frac_chain_mem32K_40nm.xml/stereovision3.v/common 26612 11 29 301 308 2 121 53 7 7 49 clb auto 0.31 388 0.11 0.00 4.29236 0 0 4.08002 0.000202666 0.000149019 0.0294518 0.022931 592 209 349 13288 3942 1.07788e+06 700622 219490. 4479.39 5 4.59615 4.30169 0 0 -164.305 -1.707 0.02 0.0417011 0.0345837 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sdc/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sdc/config/golden_results.txt index a5deaa77e2e..3128c3a2e08 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sdc/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sdc/config/golden_results.txt @@ -1,7 +1,7 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/A.sdc 0.23 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sdc/run011/k6_N10_mem32K_40nm.xml/multiclock.blif/common_-sdc_file_sdc/samples/A.sdc 25288 5 3 11 14 2 9 10 4 4 16 clb auto 0.00 16 0.02 0.00 0.738757 -2.61951 -0.738757 0.571 3.4936e-05 2.4423e-05 0.00314375 0.00224221 8 24 8 107788 107788 4794.78 299.674 0.01 0.00370959 0.00264217 33 4 14 14 686 498 0.739641 0.571 -2.62128 -0.739641 0 0 5401.54 337.596 0.00 0.000422038 0.000330531 -k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/B.sdc 0.22 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sdc/run011/k6_N10_mem32K_40nm.xml/multiclock.blif/common_-sdc_file_sdc/samples/B.sdc 25336 5 3 11 14 2 9 10 4 4 16 clb auto 0.00 19 0.01 0.00 0.571 0 0 0.571 3.1349e-05 2.1849e-05 0.000127889 9.4626e-05 8 29 7 107788 107788 4794.78 299.674 0.01 0.000630239 0.000451601 23 4 13 13 297 127 0.571 0.571 0 0 0 0 5401.54 337.596 0.00 0.000307493 0.000226879 -k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/C.sdc 0.26 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sdc/run011/k6_N10_mem32K_40nm.xml/multiclock.blif/common_-sdc_file_sdc/samples/C.sdc 25280 5 3 11 14 2 9 10 4 4 16 clb auto 0.00 16 0.03 0.00 0.569757 -1.88754 -0.569757 0.571 4.0079e-05 2.5518e-05 0.00606995 0.00392157 8 26 4 107788 107788 4794.78 299.674 0.01 0.00672637 0.00438372 19 8 26 26 674 363 0.717991 0.571 -2.35413 -0.717991 0 0 5401.54 337.596 0.00 0.000496463 0.000348304 -k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/D.sdc 0.25 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sdc/run011/k6_N10_mem32K_40nm.xml/multiclock.blif/common_-sdc_file_sdc/samples/D.sdc 25376 5 3 11 14 2 9 10 4 4 16 clb auto 0.00 16 0.02 0.00 1.56976 -4.87541 -1.56976 0.571 2.958e-05 1.7961e-05 0.00414537 0.00265591 8 26 10 107788 107788 4794.78 299.674 0.01 0.00490451 0.00315553 17 4 11 11 265 121 1.57153 0.571 -4.90021 -1.57153 0 0 5401.54 337.596 0.00 0.000378573 0.000269939 -k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/E.sdc 0.23 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sdc/run011/k6_N10_mem32K_40nm.xml/multiclock.blif/common_-sdc_file_sdc/samples/E.sdc 25100 5 3 11 14 2 9 10 4 4 16 clb auto 0.00 16 0.02 0.00 1.37313 -2.68253 -1.37313 0.571 2.8867e-05 1.8372e-05 0.00546779 0.00367434 6 24 28 107788 107788 3417.33 213.583 0.01 0.00696488 0.00471235 18 2 10 10 262 131 1.39454 0.571 -2.70748 -1.39454 0 0 4794.78 299.674 0.00 0.000298742 0.000219104 -k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/F.sdc 0.21 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sdc/run011/k6_N10_mem32K_40nm.xml/multiclock.blif/common_-sdc_file_sdc/samples/F.sdc 25468 5 3 11 14 2 9 10 4 4 16 clb auto 0.00 16 0.02 0.00 0.0697572 0 0 0.571 2.5355e-05 1.8235e-05 0.00407125 0.00280983 8 23 3 107788 107788 4794.78 299.674 0.01 0.00451409 0.00313548 27 3 14 14 519 336 0.0724097 0.571 0 0 0 0 5401.54 337.596 0.00 0.000401233 0.000319461 +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/A.sdc 0.19 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sdc/run008/k6_N10_mem32K_40nm.xml/multiclock.blif/common_-sdc_file_sdc/samples/A.sdc 22412 5 3 11 14 2 9 10 4 4 16 clb auto 0.00 16 0.01 0.00 0.738757 -2.61951 -0.738757 0.571 8.62e-06 4.855e-06 0.00105798 0.00061654 8 24 8 107788 107788 4794.78 299.674 0.01 0.00138862 0.000854589 33 4 14 14 686 498 0.739641 0.571 -2.62128 -0.739641 0 0 5401.54 337.596 0.00 0.000199774 0.000151341 +k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/B.sdc 0.15 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sdc/run008/k6_N10_mem32K_40nm.xml/multiclock.blif/common_-sdc_file_sdc/samples/B.sdc 22360 5 3 11 14 2 9 10 4 4 16 clb auto 0.00 18 0.01 0.00 0.571 0 0 0.571 1.0487e-05 6.572e-06 7.605e-05 5.4971e-05 8 22 5 107788 107788 4794.78 299.674 0.01 0.000311505 0.000233862 21 4 14 14 413 215 0.571 0.571 0 0 0 0 5401.54 337.596 0.00 0.000185589 0.000145461 +k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/C.sdc 0.16 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sdc/run008/k6_N10_mem32K_40nm.xml/multiclock.blif/common_-sdc_file_sdc/samples/C.sdc 22364 5 3 11 14 2 9 10 4 4 16 clb auto 0.00 16 0.01 0.00 0.569757 -1.88754 -0.569757 0.571 1.1865e-05 6.099e-06 0.00173724 0.000920786 8 26 4 107788 107788 4794.78 299.674 0.01 0.00203764 0.00113607 19 8 26 26 674 363 0.717991 0.571 -2.35413 -0.717991 0 0 5401.54 337.596 0.00 0.000307209 0.000224552 +k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/D.sdc 0.16 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sdc/run008/k6_N10_mem32K_40nm.xml/multiclock.blif/common_-sdc_file_sdc/samples/D.sdc 22408 5 3 11 14 2 9 10 4 4 16 clb auto 0.00 16 0.01 0.00 1.56976 -4.87541 -1.56976 0.571 1.3184e-05 6.413e-06 0.0018425 0.000975143 8 26 10 107788 107788 4794.78 299.674 0.01 0.00232156 0.00129433 17 4 11 11 265 121 1.57153 0.571 -4.90021 -1.57153 0 0 5401.54 337.596 0.00 0.000244076 0.000178355 +k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/E.sdc 0.16 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sdc/run008/k6_N10_mem32K_40nm.xml/multiclock.blif/common_-sdc_file_sdc/samples/E.sdc 22416 5 3 11 14 2 9 10 4 4 16 clb auto 0.00 16 0.01 0.00 1.37313 -2.68253 -1.37313 0.571 1.2943e-05 6.857e-06 0.00182033 0.0010336 6 24 28 107788 107788 3417.33 213.583 0.01 0.00265571 0.00159994 18 2 10 10 262 131 1.39454 0.571 -2.70748 -1.39454 0 0 4794.78 299.674 0.00 0.000201699 0.000152859 +k6_N10_mem32K_40nm.xml multiclock.blif common_-sdc_file_sdc/samples/F.sdc 0.16 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sdc/run008/k6_N10_mem32K_40nm.xml/multiclock.blif/common_-sdc_file_sdc/samples/F.sdc 22488 5 3 11 14 2 9 10 4 4 16 clb auto 0.00 16 0.01 0.00 0.0697572 0 0 0.571 9.44e-06 5.86e-06 0.00157376 0.000949111 8 23 3 107788 107788 4794.78 299.674 0.01 0.00185249 0.00116396 27 3 14 14 519 336 0.0724097 0.571 0 0 0 0 5401.54 337.596 0.00 0.000207357 0.000164218 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_soft_multipliers/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_soft_multipliers/config/golden_results.txt index d0b1d6e9f3a..2585cab57ff 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_soft_multipliers/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_soft_multipliers/config/golden_results.txt @@ -1,7 +1,7 @@ -+arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length -+k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_4x4.v common 0.83 0.01 5960 1 0.01 -1 -1 33540 -1 -1 3 9 0 -1 success v8.0.0-1788-gcbe613f03 Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-5.3.0-51-generic x86_64 2020-06-02T11:57:19 casa51 /home/casauser/Desktop/Most-Updated-VTR/Casa/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_soft_multipliers/run004/k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml/mult_4x4.v/common 24292 9 8 75 70 1 34 20 5 5 25 clb auto 0.48 72 0.02 2.25879 -23.5139 -2.25879 20 195 16 151211 75605.7 29112.5 1164.50 0.02 169 10 90 101 5752 3198 2.41865 2.41865 -34.9802 -2.41865 0 0 37105.9 1484.24 0.00 13 16 19 7 0 0 -+k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_5x5.v common 4.92 0.01 5952 1 0.00 -1 -1 33624 -1 -1 2 11 0 -1 success v8.0.0-1788-gcbe613f03 Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-5.3.0-51-generic x86_64 2020-06-02T11:57:19 casa51 /home/casauser/Desktop/Most-Updated-VTR/Casa/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_soft_multipliers/run004/k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml/mult_5x5.v/common 24492 11 10 108 97 1 44 23 4 4 16 clb auto 4.58 94 0.02 2.96669 -32.8172 -2.96669 34 213 25 50403.8 50403.8 21558.4 1347.40 0.05 156 7 110 135 4945 3112 3.64419 3.64419 -46.6251 -3.64419 0 0 26343.3 1646.46 0.00 14 25 29 8 0 0 -+k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_6x6.v common 3.60 0.01 6068 1 0.01 -1 -1 33888 -1 -1 6 13 0 -1 success v8.0.0-1788-gcbe613f03 Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-5.3.0-51-generic x86_64 2020-06-02T11:57:19 casa51 /home/casauser/Desktop/Most-Updated-VTR/Casa/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_soft_multipliers/run004/k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml/mult_6x6.v/common 25360 13 12 149 129 1 72 31 5 5 25 clb auto 3.09 180 0.04 3.03389 -41.8702 -3.03389 60 324 25 151211 151211 73020.3 2920.81 0.14 254 12 247 302 11201 5196 3.38467 3.38467 -55.0874 -3.38467 0 0 90821.2 3632.85 0.01 25 36 42 9 0 0 -+k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_7x7.v common 2.03 0.01 6152 1 0.01 -1 -1 33832 -1 -1 6 15 0 -1 success v8.0.0-1788-gcbe613f03 Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-5.3.0-51-generic x86_64 2020-06-02T11:57:19 casa51 /home/casauser/Desktop/Most-Updated-VTR/Casa/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_soft_multipliers/run004/k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml/mult_7x7.v/common 25616 15 14 196 165 1 95 35 5 5 25 clb auto 1.49 287 0.05 3.1163 -51.6955 -3.1163 46 525 19 151211 151211 57775.2 2311.01 0.17 395 18 375 525 17847 7934 3.85568 3.85568 -71.6886 -3.85568 0 0 73020.3 2920.81 0.01 38 49 57 11 0 0 -+k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_8x8.v common 2.24 0.01 6144 1 0.01 -1 -1 33504 -1 -1 6 17 0 -1 success v8.0.0-1788-gcbe613f03 Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-5.3.0-51-generic x86_64 2020-06-02T11:57:19 casa51 /home/casauser/Desktop/Most-Updated-VTR/Casa/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_soft_multipliers/run004/k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml/mult_8x8.v/common 26020 17 16 251 206 1 116 39 5 5 25 clb auto 1.71 377 0.06 3.26291 -60.9398 -3.26291 52 611 28 151211 151211 63348.9 2533.96 0.12 505 16 515 759 25843 11622 5.22085 5.22085 -95.6248 -5.22085 0 0 82390.3 3295.61 0.01 51 64 75 13 0 0 -+k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_9x9.v common 4.70 0.01 6236 1 0.02 -1 -1 34160 -1 -1 7 19 0 -1 success v8.0.0-1788-gcbe613f03 Release VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-5.3.0-51-generic x86_64 2020-06-02T11:57:19 casa51 /home/casauser/Desktop/Most-Updated-VTR/Casa/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_soft_multipliers/run004/k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml/mult_9x9.v/common 26564 19 18 308 249 1 141 44 6 6 36 clb auto 4.06 461 0.07 3.86024 -71.5388 -3.86024 54 1031 48 403230 176413 113905. 3164.04 0.17 755 18 655 1081 41335 16174 5.26704 5.26704 -107.994 -5.26704 0 0 146644. 4073.44 0.02 58 81 93 14 0 0 \ No newline at end of file +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length +k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_4x4.v common 2.87 0.01 5516 1 0.01 -1 -1 33488 -1 -1 3 9 0 -1 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_soft_multipliers/run015/k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml/mult_4x4.v/common 23888 9 8 75 70 1 34 20 5 5 25 clb auto 0.50 72 0.03 0.00 2.25879 -23.5139 -2.25879 2.25879 3.8863e-05 2.8943e-05 0.00502415 0.00388444 20 195 16 151211 75605.7 29112.5 1164.50 0.02 0.00832979 0.00686554 169 10 90 101 5752 3198 2.41865 2.41865 -34.9802 -2.41865 0 0 37105.9 1484.24 0.00 0.00258835 0.00239773 13 16 19 7 0 0 +k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_5x5.v common 7.81 0.02 5552 1 0.01 -1 -1 33416 -1 -1 2 11 0 -1 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_soft_multipliers/run015/k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml/mult_5x5.v/common 23824 11 10 108 97 1 44 23 4 4 16 clb auto 5.39 94 0.03 0.00 2.96669 -32.8172 -2.96669 2.96669 5.502e-05 4.2086e-05 0.00821095 0.00644633 34 213 25 50403.8 50403.8 21558.4 1347.40 0.06 0.0249456 0.0203718 156 7 110 135 4945 3112 3.64419 3.64419 -46.6251 -3.64419 0 0 26343.3 1646.46 0.01 0.00344265 0.00324154 14 25 29 8 0 0 +k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_6x6.v common 6.59 0.01 5784 1 0.01 -1 -1 33784 -1 -1 6 13 0 -1 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_soft_multipliers/run015/k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml/mult_6x6.v/common 23980 13 12 149 129 1 72 31 5 5 25 clb auto 4.10 180 0.06 0.00 3.03389 -41.8702 -3.03389 3.03389 7.5396e-05 5.803e-05 0.0107635 0.00852917 60 324 25 151211 151211 73020.3 2920.81 0.09 0.0336521 0.0277525 254 12 247 302 11201 5196 3.38467 3.38467 -55.0874 -3.38467 0 0 90821.2 3632.85 0.01 0.00548564 0.00510352 25 36 42 9 0 0 +k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_7x7.v common 4.46 0.02 5912 1 0.01 -1 -1 33236 -1 -1 6 15 0 -1 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_soft_multipliers/run015/k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml/mult_7x7.v/common 24448 15 14 196 165 1 95 35 5 5 25 clb auto 1.89 287 0.08 0.00 3.1163 -51.6955 -3.1163 3.1163 9.7683e-05 7.5895e-05 0.0140242 0.0111335 46 525 19 151211 151211 57775.2 2311.01 0.11 0.0423412 0.0350833 395 18 375 525 17847 7934 3.85568 3.85568 -71.6886 -3.85568 0 0 73020.3 2920.81 0.01 0.0085281 0.00782893 38 49 57 11 0 0 +k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_8x8.v common 4.69 0.01 5940 1 0.00 -1 -1 33552 -1 -1 6 17 0 -1 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_soft_multipliers/run015/k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml/mult_8x8.v/common 24936 17 16 251 206 1 116 39 5 5 25 clb auto 2.20 377 0.09 0.00 3.26291 -60.9398 -3.26291 3.26291 0.000127232 9.9478e-05 0.0182695 0.0146137 52 611 28 151211 151211 63348.9 2533.96 0.13 0.056883 0.0471944 505 16 515 759 25843 11622 5.22085 5.22085 -95.6248 -5.22085 0 0 82390.3 3295.61 0.02 0.0102647 0.0094651 51 64 75 13 0 0 +k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml mult_9x9.v common 7.59 0.01 6028 1 0.01 -1 -1 33908 -1 -1 7 19 0 -1 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_soft_multipliers/run015/k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml/mult_9x9.v/common 25652 19 18 308 249 1 141 44 6 6 36 clb auto 4.97 461 0.11 0.00 3.86024 -71.5388 -3.86024 3.86024 0.000152121 0.00011949 0.0215118 0.0171028 54 1031 48 403230 176413 113905. 3164.04 0.20 0.0754836 0.0629888 755 18 655 1081 41335 16174 5.26704 5.26704 -107.994 -5.26704 0 0 146644. 4073.44 0.02 0.0139787 0.0128909 58 81 93 14 0 0 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sub_tiles/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sub_tiles/config/golden_results.txt index db7914c9efb..64c130e292f 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sub_tiles/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sub_tiles/config/golden_results.txt @@ -1,2 +1,2 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time -sub_tiles.xml sub_tiles.blif common 1.81 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 6 -1 -1 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sub_tiles/run004/sub_tiles.xml/sub_tiles.blif/common 46184 6 7 19 26 0 19 26 3 3 9 -1 auto 0.01 38 1.38 0.00 3.87729 -27.141 -3.87729 nan 3.7606e-05 2.7467e-05 0.00012843 9.409e-05 6 19 4 14813.4 192574 -1 -1 0.08 0.00121158 0.000839129 19 2 32 34 5402 2849 3.87729 nan -27.141 -3.87729 0 0 -1 -1 0.00 0.000235428 0.000165429 +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time +sub_tiles.xml sub_tiles.blif common 2.49 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 6 -1 -1 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sub_tiles/run008/sub_tiles.xml/sub_tiles.blif/common 37132 6 7 19 26 0 19 26 3 3 9 -1 auto 0.00 38 2.05 0.00 3.87729 -27.141 -3.87729 nan 1.3368e-05 9.09e-06 7.1838e-05 5.0096e-05 6 19 3 14813.4 192574 -1 -1 0.04 0.000314794 0.000233672 19 3 34 37 5960 3302 3.87729 nan -27.141 -3.87729 0 0 -1 -1 0.00 0.000166989 0.000129444 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sweep_constant_outputs/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sweep_constant_outputs/config/golden_results.txt index 45196067b96..8113fa6bc77 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sweep_constant_outputs/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sweep_constant_outputs/config/golden_results.txt @@ -1,2 +1,2 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6_N10_mem32K_40nm.xml ch_intrinsics.v common 1.59 0.04 8984 3 0.23 -1 -1 36160 -1 -1 14 99 1 0 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sweep_constant_outputs/run015/k6_N10_mem32K_40nm.xml/ch_intrinsics.v/common 30424 99 74 307 381 1 199 188 8 8 64 io memory auto 0.05 665 0.28 0.00 1.91417 -195.15 -1.91417 1.91417 0.000326354 0.000276592 0.0514491 0.0432667 42 1220 14 2.23746e+06 1.30252e+06 130676. 2041.82 0.35 0.146871 0.126644 1097 15 753 1100 113456 36999 2.1112 2.1112 -216.052 -2.1112 0 0 165046. 2578.84 0.03 0.0147062 0.0131667 +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_mem32K_40nm.xml ch_intrinsics.v common 3.41 0.03 8896 3 0.22 -1 -1 37972 -1 -1 14 99 1 0 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_sweep_constant_outputs/run013/k6_N10_mem32K_40nm.xml/ch_intrinsics.v/common 25784 99 74 307 381 1 199 188 8 8 64 io memory auto 0.05 665 0.33 0.00 1.91417 -195.15 -1.91417 1.91417 0.000302506 0.000255418 0.0392211 0.0333282 42 1220 14 2.23746e+06 1.30252e+06 130676. 2041.82 0.29 0.108715 0.095232 1097 15 753 1100 113456 36999 2.1112 2.1112 -216.052 -2.1112 0 0 165046. 2578.84 0.04 0.0147094 0.0134955 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_target_pin_util/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_target_pin_util/config/golden_results.txt index 935b2db1a4b..6238cb3a178 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_target_pin_util/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_target_pin_util/config/golden_results.txt @@ -1,14 +1,14 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time -EArch.xml styr.blif common_--target_ext_pin_util_1 0.72 -1 -1 -1 -1 -1 -1 -1 -1 -1 11 10 0 0 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_target_pin_util/run014/EArch.xml/styr.blif/common_--target_ext_pin_util_1 30508 10 10 168 178 1 74 31 6 6 36 clb auto 0.13 382 0.07 0.00 2.15459 -25.1942 -2.15459 2.15459 0.000221005 0.000177753 0.0254642 0.0199756 38 800 17 646728 592834 65452.3 1818.12 0.18 0.0814708 0.0665146 688 20 456 1668 64688 24156 2.66364 2.66364 -31.6709 -2.66364 0 0 83521.2 2320.03 0.03 0.0163916 0.0146049 -EArch.xml styr.blif common_--target_ext_pin_util_0.7 0.85 -1 -1 -1 -1 -1 -1 -1 -1 -1 11 10 0 0 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_target_pin_util/run014/EArch.xml/styr.blif/common_--target_ext_pin_util_0.7 30452 10 10 168 178 1 74 31 6 6 36 clb auto 0.21 382 0.08 0.00 2.15459 -25.1942 -2.15459 2.15459 0.000253731 0.000204724 0.0290702 0.0227229 38 800 17 646728 592834 65452.3 1818.12 0.18 0.0849551 0.0690739 688 20 456 1668 64688 24156 2.66364 2.66364 -31.6709 -2.66364 0 0 83521.2 2320.03 0.03 0.016151 0.0144691 -EArch.xml styr.blif common_--target_ext_pin_util_0.1,0.5 2.30 -1 -1 -1 -1 -1 -1 -1 -1 -1 90 10 0 0 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_target_pin_util/run014/EArch.xml/styr.blif/common_--target_ext_pin_util_0.1,0.5 36796 10 10 168 178 1 162 110 14 14 196 clb auto 0.58 1387 0.42 0.00 2.51884 -31.4654 -2.51884 2.51884 0.000236837 0.000178212 0.0236971 0.018329 26 2837 16 9.20055e+06 4.85046e+06 387483. 1976.95 0.40 0.062511 0.050505 2742 14 650 2789 168625 37686 3.58224 3.58224 -42.6087 -3.58224 0 0 467681. 2386.13 0.06 0.0190385 0.0168887 -EArch.xml styr.blif common_--target_ext_pin_util_0.5,0.3 0.87 -1 -1 -1 -1 -1 -1 -1 -1 -1 13 10 0 0 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_target_pin_util/run014/EArch.xml/styr.blif/common_--target_ext_pin_util_0.5,0.3 31864 10 10 168 178 1 73 33 7 7 49 clb auto 0.16 360 0.10 0.00 2.15444 -25.01 -2.15444 2.15444 0.00021268 0.000176334 0.0253541 0.0198352 28 1248 38 1.07788e+06 700622 79600.7 1624.51 0.18 0.0684005 0.055929 928 18 558 2136 96280 33898 2.79653 2.79653 -35.1311 -2.79653 0 0 95067.4 1940.15 0.05 0.0297294 0.0270798 -EArch.xml styr.blif common_--target_ext_pin_util_0.0 2.30 -1 -1 -1 -1 -1 -1 -1 -1 -1 101 10 0 0 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_target_pin_util/run014/EArch.xml/styr.blif/common_--target_ext_pin_util_0.0 37244 10 10 168 178 1 163 121 14 14 196 clb auto 0.52 1410 0.52 0.00 2.77278 -32.4085 -2.77278 2.77278 0.000238357 0.000182325 0.0268028 0.0208842 26 2807 12 9.20055e+06 5.44329e+06 387483. 1976.95 0.39 0.0597298 0.0481853 2754 17 663 2477 151760 33519 3.70229 3.70229 -44.61 -3.70229 0 0 467681. 2386.13 0.04 0.0120313 0.010564 -EArch.xml styr.blif common_--target_ext_pin_util_clb:0.7 0.85 -1 -1 -1 -1 -1 -1 -1 -1 -1 11 10 0 0 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_target_pin_util/run014/EArch.xml/styr.blif/common_--target_ext_pin_util_clb:0.7 30320 10 10 168 178 1 74 31 6 6 36 clb auto 0.17 382 0.08 0.00 2.15459 -25.1942 -2.15459 2.15459 0.000218217 0.000176576 0.0276365 0.0219964 38 800 17 646728 592834 65452.3 1818.12 0.18 0.0830532 0.06813 688 20 456 1668 64688 24156 2.66364 2.66364 -31.6709 -2.66364 0 0 83521.2 2320.03 0.04 0.0250439 0.0221544 -EArch.xml styr.blif common_--target_ext_pin_util_clb:0.7_0.8 0.71 -1 -1 -1 -1 -1 -1 -1 -1 -1 11 10 0 0 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_target_pin_util/run014/EArch.xml/styr.blif/common_--target_ext_pin_util_clb:0.7_0.8 30388 10 10 168 178 1 74 31 6 6 36 clb auto 0.13 382 0.07 0.00 2.15459 -25.1942 -2.15459 2.15459 0.000217263 0.000174673 0.0254039 0.0198319 38 800 17 646728 592834 65452.3 1818.12 0.17 0.0796192 0.0647946 688 20 456 1668 64688 24156 2.66364 2.66364 -31.6709 -2.66364 0 0 83521.2 2320.03 0.03 0.017595 0.0156692 -EArch.xml styr.blif common_--target_ext_pin_util_clb:0.1_0.8 2.22 -1 -1 -1 -1 -1 -1 -1 -1 -1 90 10 0 0 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_target_pin_util/run014/EArch.xml/styr.blif/common_--target_ext_pin_util_clb:0.1_0.8 36568 10 10 168 178 1 162 110 14 14 196 clb auto 0.48 1387 0.50 0.00 2.51884 -31.4654 -2.51884 2.51884 0.000234864 0.000177166 0.0261234 0.0204132 26 2837 16 9.20055e+06 4.85046e+06 387483. 1976.95 0.41 0.060792 0.0493305 2742 14 650 2789 168625 37686 3.58224 3.58224 -42.6087 -3.58224 0 0 467681. 2386.13 0.04 0.0118605 0.0105076 -EArch.xml styr.blif common_--target_ext_pin_util_io:0.1,0.1_clb:0.7_0.8,1.0 0.84 -1 -1 -1 -1 -1 -1 -1 -1 -1 11 10 0 0 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_target_pin_util/run014/EArch.xml/styr.blif/common_--target_ext_pin_util_io:0.1,0.1_clb:0.7_0.8,1.0 30416 10 10 168 178 1 74 31 6 6 36 clb auto 0.15 382 0.08 0.00 2.15459 -25.1942 -2.15459 2.15459 0.000217183 0.00017539 0.0256727 0.0202203 38 800 17 646728 592834 65452.3 1818.12 0.19 0.0843206 0.0685009 688 20 456 1668 64688 24156 2.66364 2.66364 -31.6709 -2.66364 0 0 83521.2 2320.03 0.05 0.0277123 0.0244696 -EArch.xml styr.blif common_--target_ext_pin_util_-0.1 0.11 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 exited with return code 1 v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_target_pin_util/run014/EArch.xml/styr.blif/common_--target_ext_pin_util_-0.1 25760 10 10 168 178 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -EArch.xml styr.blif common_--target_ext_pin_util_1.1 0.10 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 exited with return code 1 v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_target_pin_util/run014/EArch.xml/styr.blif/common_--target_ext_pin_util_1.1 25824 10 10 168 178 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -EArch.xml styr.blif common_--target_ext_pin_util_io:0.1,0.1_clb:0.7_0.8,1.0_1.0 0.11 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 exited with return code 1 v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_target_pin_util/run014/EArch.xml/styr.blif/common_--target_ext_pin_util_io:0.1,0.1_clb:0.7_0.8,1.0_1.0 25672 10 10 168 178 1 -1 -1 -1 -1 -1 -1 -1 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -EArch.xml styr.blif common_--target_ext_pin_util_io:0.1,0.1_clb:0.7_0.8,1.0_clb:1.0 0.09 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 exited with return code 1 v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_target_pin_util/run014/EArch.xml/styr.blif/common_--target_ext_pin_util_io:0.1,0.1_clb:0.7_0.8,1.0_clb:1.0 25812 10 10 168 178 1 -1 -1 -1 -1 -1 -1 -1 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time +EArch.xml styr.blif common_--target_ext_pin_util_1 0.77 -1 -1 -1 -1 -1 -1 -1 -1 -1 11 10 0 0 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_target_pin_util/run008/EArch.xml/styr.blif/common_--target_ext_pin_util_1 26076 10 10 168 178 1 74 31 6 6 36 clb auto 0.15 382 0.10 0.00 2.15459 -25.1942 -2.15459 2.15459 0.000185711 0.000147247 0.0217871 0.0175896 38 800 17 646728 592834 65452.3 1818.12 0.20 0.0745402 0.0627398 688 20 456 1668 64688 24156 2.66364 2.66364 -31.6709 -2.66364 0 0 83521.2 2320.03 0.03 0.0165573 0.0152039 +EArch.xml styr.blif common_--target_ext_pin_util_0.7 0.74 -1 -1 -1 -1 -1 -1 -1 -1 -1 11 10 0 0 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_target_pin_util/run008/EArch.xml/styr.blif/common_--target_ext_pin_util_0.7 26012 10 10 168 178 1 74 31 6 6 36 clb auto 0.15 382 0.10 0.00 2.15459 -25.1942 -2.15459 2.15459 0.000181072 0.000143198 0.0212676 0.0171573 38 800 17 646728 592834 65452.3 1818.12 0.21 0.0744256 0.062579 688 20 456 1668 64688 24156 2.66364 2.66364 -31.6709 -2.66364 0 0 83521.2 2320.03 0.03 0.0170128 0.0155951 +EArch.xml styr.blif common_--target_ext_pin_util_0.1,0.5 2.40 -1 -1 -1 -1 -1 -1 -1 -1 -1 90 10 0 0 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_target_pin_util/run008/EArch.xml/styr.blif/common_--target_ext_pin_util_0.1,0.5 30828 10 10 168 178 1 162 110 14 14 196 clb auto 0.58 1387 0.56 0.00 2.51884 -31.4654 -2.51884 2.51884 0.000209515 0.000163832 0.0211425 0.017262 26 2837 16 9.20055e+06 4.85046e+06 387483. 1976.95 0.47 0.0542665 0.0459641 2742 14 650 2789 168625 37686 3.58224 3.58224 -42.6087 -3.58224 0 0 467681. 2386.13 0.05 0.0122613 0.0112192 +EArch.xml styr.blif common_--target_ext_pin_util_0.5,0.3 0.83 -1 -1 -1 -1 -1 -1 -1 -1 -1 13 10 0 0 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_target_pin_util/run008/EArch.xml/styr.blif/common_--target_ext_pin_util_0.5,0.3 26396 10 10 168 178 1 73 33 7 7 49 clb auto 0.17 360 0.12 0.00 2.15444 -25.01 -2.15444 2.15444 0.000177104 0.000141126 0.0210897 0.0169854 28 1248 38 1.07788e+06 700622 79600.7 1624.51 0.22 0.0645703 0.0546932 928 18 558 2136 96280 33898 2.79653 2.79653 -35.1311 -2.79653 0 0 95067.4 1940.15 0.04 0.016232 0.0149343 +EArch.xml styr.blif common_--target_ext_pin_util_0.0 2.50 -1 -1 -1 -1 -1 -1 -1 -1 -1 101 10 0 0 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_target_pin_util/run008/EArch.xml/styr.blif/common_--target_ext_pin_util_0.0 30728 10 10 168 178 1 163 121 14 14 196 clb auto 0.65 1410 0.59 0.00 2.77278 -32.4085 -2.77278 2.77278 0.000218557 0.000172293 0.021337 0.0172806 26 2807 12 9.20055e+06 5.44329e+06 387483. 1976.95 0.46 0.0525069 0.0442033 2754 17 663 2477 151760 33519 3.70229 3.70229 -44.61 -3.70229 0 0 467681. 2386.13 0.06 0.0131354 0.0118976 +EArch.xml styr.blif common_--target_ext_pin_util_clb:0.7 0.74 -1 -1 -1 -1 -1 -1 -1 -1 -1 11 10 0 0 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_target_pin_util/run008/EArch.xml/styr.blif/common_--target_ext_pin_util_clb:0.7 26052 10 10 168 178 1 74 31 6 6 36 clb auto 0.14 382 0.10 0.00 2.15459 -25.1942 -2.15459 2.15459 0.000183425 0.000146014 0.0214809 0.0174174 38 800 17 646728 592834 65452.3 1818.12 0.20 0.0741188 0.0626112 688 20 456 1668 64688 24156 2.66364 2.66364 -31.6709 -2.66364 0 0 83521.2 2320.03 0.03 0.0170442 0.0156701 +EArch.xml styr.blif common_--target_ext_pin_util_clb:0.7_0.8 0.74 -1 -1 -1 -1 -1 -1 -1 -1 -1 11 10 0 0 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_target_pin_util/run008/EArch.xml/styr.blif/common_--target_ext_pin_util_clb:0.7_0.8 26256 10 10 168 178 1 74 31 6 6 36 clb auto 0.15 382 0.10 0.00 2.15459 -25.1942 -2.15459 2.15459 0.000181346 0.000143335 0.0209123 0.0168071 38 800 17 646728 592834 65452.3 1818.12 0.20 0.0738868 0.0623966 688 20 456 1668 64688 24156 2.66364 2.66364 -31.6709 -2.66364 0 0 83521.2 2320.03 0.03 0.0168141 0.0154263 +EArch.xml styr.blif common_--target_ext_pin_util_clb:0.1_0.8 2.44 -1 -1 -1 -1 -1 -1 -1 -1 -1 90 10 0 0 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_target_pin_util/run008/EArch.xml/styr.blif/common_--target_ext_pin_util_clb:0.1_0.8 30804 10 10 168 178 1 162 110 14 14 196 clb auto 0.59 1387 0.56 0.00 2.51884 -31.4654 -2.51884 2.51884 0.000249311 0.000198365 0.0212012 0.017209 26 2837 16 9.20055e+06 4.85046e+06 387483. 1976.95 0.47 0.0546223 0.0461511 2742 14 650 2789 168625 37686 3.58224 3.58224 -42.6087 -3.58224 0 0 467681. 2386.13 0.05 0.0126376 0.011535 +EArch.xml styr.blif common_--target_ext_pin_util_io:0.1,0.1_clb:0.7_0.8,1.0 0.75 -1 -1 -1 -1 -1 -1 -1 -1 -1 11 10 0 0 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_target_pin_util/run008/EArch.xml/styr.blif/common_--target_ext_pin_util_io:0.1,0.1_clb:0.7_0.8,1.0 26188 10 10 168 178 1 74 31 6 6 36 clb auto 0.15 382 0.10 0.00 2.15459 -25.1942 -2.15459 2.15459 0.000189076 0.000150579 0.0212666 0.0171364 38 800 17 646728 592834 65452.3 1818.12 0.21 0.0761332 0.0641867 688 20 456 1668 64688 24156 2.66364 2.66364 -31.6709 -2.66364 0 0 83521.2 2320.03 0.03 0.0177538 0.0163217 +EArch.xml styr.blif common_--target_ext_pin_util_-0.1 0.08 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 exited with return code 1 v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_target_pin_util/run008/EArch.xml/styr.blif/common_--target_ext_pin_util_-0.1 23412 10 10 168 178 1 -1 -1 -1 -1 -1 -1 -1 0.03 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +EArch.xml styr.blif common_--target_ext_pin_util_1.1 0.05 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 exited with return code 1 v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_target_pin_util/run008/EArch.xml/styr.blif/common_--target_ext_pin_util_1.1 23356 10 10 168 178 1 -1 -1 -1 -1 -1 -1 -1 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +EArch.xml styr.blif common_--target_ext_pin_util_io:0.1,0.1_clb:0.7_0.8,1.0_1.0 0.05 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 exited with return code 1 v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_target_pin_util/run008/EArch.xml/styr.blif/common_--target_ext_pin_util_io:0.1,0.1_clb:0.7_0.8,1.0_1.0 23384 10 10 168 178 1 -1 -1 -1 -1 -1 -1 -1 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +EArch.xml styr.blif common_--target_ext_pin_util_io:0.1,0.1_clb:0.7_0.8,1.0_clb:1.0 0.05 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 exited with return code 1 v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_target_pin_util/run008/EArch.xml/styr.blif/common_--target_ext_pin_util_io:0.1,0.1_clb:0.7_0.8,1.0_clb:1.0 23452 10 10 168 178 1 -1 -1 -1 -1 -1 -1 -1 0.00 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing/config/golden_results.txt index 6345820010d..9452d9d1e09 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing/config/golden_results.txt @@ -1,2 +1,2 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common 2.40 0.05 8924 3 0.22 -1 -1 36244 -1 -1 65 99 1 0 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing/run015/k6_frac_N10_mem32K_40nm.xml/ch_intrinsics.v/common 35428 99 130 363 493 1 251 295 12 12 144 clb auto 0.09 624 0.47 0.00 1.94344 -198.852 -1.94344 1.94344 0.000653392 0.000563955 0.0573088 0.0494635 50 1398 19 5.66058e+06 4.05111e+06 406292. 2821.48 0.59 0.168467 0.149351 1368 9 565 725 73444 24903 2.56877 2.56877 -239.947 -2.56877 0 0 539112. 3743.83 0.03 0.0132233 0.0122888 +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_mem32K_40nm.xml ch_intrinsics.v common 4.26 0.03 8952 3 0.23 -1 -1 37920 -1 -1 65 99 1 0 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing/run014/k6_frac_N10_mem32K_40nm.xml/ch_intrinsics.v/common 29412 99 130 363 493 1 251 295 12 12 144 clb auto 0.10 624 0.58 0.00 1.94344 -198.852 -1.94344 1.94344 0.000380451 0.00033018 0.0533974 0.0467482 50 1398 19 5.66058e+06 4.05111e+06 406292. 2821.48 0.56 0.157198 0.141968 1334 9 570 753 58756 20655 2.42731 2.42731 -236.701 -2.42731 0 0 520805. 3616.70 0.03 0.014999 0.0141699 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_report_detail/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_report_detail/config/golden_results.txt index 6118c31ad79..1b788c5e979 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_report_detail/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_report_detail/config/golden_results.txt @@ -1,4 +1,4 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6_frac_N10_frac_chain_mem32K_40nm.xml multiclock.blif common_--timing_report_detail_netlist 0.29 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_report_detail/run011/k6_frac_N10_frac_chain_mem32K_40nm.xml/multiclock.blif/common_--timing_report_detail_netlist 27132 5 3 11 14 2 9 10 4 4 16 clb auto 0.01 16 0.02 0.00 0.545 -3.13055 -0.545 0.545 2.6504e-05 1.7223e-05 0.00364423 0.0024041 20 26 8 107788 107788 10441.3 652.579 0.01 0.00430123 0.00287257 20 1 7 7 139 86 0.721454 0.545 -3.67021 -0.721454 0 0 13752.8 859.551 0.00 0.000569671 0.000433281 -k6_frac_N10_frac_chain_mem32K_40nm.xml multiclock.blif common_--timing_report_detail_aggregated 0.26 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_report_detail/run011/k6_frac_N10_frac_chain_mem32K_40nm.xml/multiclock.blif/common_--timing_report_detail_aggregated 27176 5 3 11 14 2 9 10 4 4 16 clb auto 0.01 16 0.02 0.00 0.545 -3.13055 -0.545 0.545 2.635e-05 1.6953e-05 0.00367386 0.00239662 20 26 8 107788 107788 10441.3 652.579 0.01 0.00433019 0.00286887 20 1 7 7 139 86 0.721454 0.545 -3.67021 -0.721454 0 0 13752.8 859.551 0.00 0.000263548 0.000200567 -k6_frac_N10_frac_chain_mem32K_40nm.xml multiclock.blif common_--timing_report_detail_detailed 0.31 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_report_detail/run011/k6_frac_N10_frac_chain_mem32K_40nm.xml/multiclock.blif/common_--timing_report_detail_detailed 27184 5 3 11 14 2 9 10 4 4 16 clb auto 0.00 16 0.02 0.00 0.545 -3.13055 -0.545 0.545 2.6258e-05 1.7131e-05 0.00392208 0.00261425 20 26 8 107788 107788 10441.3 652.579 0.01 0.00459771 0.00309595 20 1 7 7 139 86 0.721454 0.545 -3.67021 -0.721454 0 0 13752.8 859.551 0.00 0.000377741 0.000291052 +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_frac_chain_mem32K_40nm.xml multiclock.blif common_--timing_report_detail_netlist 0.20 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_report_detail/run008/k6_frac_N10_frac_chain_mem32K_40nm.xml/multiclock.blif/common_--timing_report_detail_netlist 23876 5 3 11 14 2 9 10 4 4 16 clb auto 0.01 16 0.01 0.00 0.545 -3.13055 -0.545 0.545 1.2358e-05 6.277e-06 0.00163203 0.000890123 20 26 8 107788 107788 10441.3 652.579 0.01 0.00204339 0.00119644 20 1 7 7 139 86 0.721454 0.545 -3.67021 -0.721454 0 0 13752.8 859.551 0.00 0.000194018 0.00016017 +k6_frac_N10_frac_chain_mem32K_40nm.xml multiclock.blif common_--timing_report_detail_aggregated 0.21 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_report_detail/run008/k6_frac_N10_frac_chain_mem32K_40nm.xml/multiclock.blif/common_--timing_report_detail_aggregated 23956 5 3 11 14 2 9 10 4 4 16 clb auto 0.01 16 0.01 0.00 0.545 -3.13055 -0.545 0.545 1.094e-05 5.509e-06 0.00155504 0.000820215 20 26 8 107788 107788 10441.3 652.579 0.01 0.00198059 0.0011409 20 1 7 7 139 86 0.721454 0.545 -3.67021 -0.721454 0 0 13752.8 859.551 0.00 0.000210614 0.000176096 +k6_frac_N10_frac_chain_mem32K_40nm.xml multiclock.blif common_--timing_report_detail_detailed 0.20 -1 -1 -1 -1 -1 -1 -1 -1 -1 2 5 0 0 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_report_detail/run008/k6_frac_N10_frac_chain_mem32K_40nm.xml/multiclock.blif/common_--timing_report_detail_detailed 23816 5 3 11 14 2 9 10 4 4 16 clb auto 0.01 16 0.01 0.00 0.545 -3.13055 -0.545 0.545 1.2075e-05 6.221e-06 0.00165135 0.000903713 20 26 8 107788 107788 10441.3 652.579 0.01 0.00207844 0.00122381 20 1 7 7 139 86 0.721454 0.545 -3.67021 -0.721454 0 0 13752.8 859.551 0.00 0.000200501 0.000165646 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_update_diff/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_update_diff/config/golden_results.txt index ad1f6cc64f1..f57597cb007 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_update_diff/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_update_diff/config/golden_results.txt @@ -1,2 +1,2 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 2.37 0.06 10600 5 0.08 -1 -1 33012 -1 -1 14 11 0 0 success v8.0.0-2062-g497427a4c release IPO VTR_ASSERT_LEVEL=2 gprof GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-10T16:04:07 betzgrp-wintermute.eecg.utoronto.ca /home/hubingra/master/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_update_diff/run016/k6_frac_N10_frac_chain_mem32K_40nm.xml/stereovision3.v/common 34320 11 30 313 321 2 117 55 7 7 49 clb auto 0.28 389 0.18 0.00 2.27833 -153.323 -2.27833 2.06764 0.000746185 0.00060234 0.103989 0.0830486 -1 524 8 1.07788e+06 754516 219490. 4479.39 0.03 0.129028 0.105458 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_frac_N10_frac_chain_mem32K_40nm.xml stereovision3.v common 3.73 0.04 9456 5 0.10 -1 -1 36604 -1 -1 13 11 0 0 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_update_diff/run013/k6_frac_N10_frac_chain_mem32K_40nm.xml/stereovision3.v/common 26620 11 29 301 308 2 120 53 7 7 49 clb auto 0.31 409 0.12 0.00 2.29324 -153.859 -2.29324 2.05363 0.000253907 0.000192883 0.0367332 0.0283983 -1 620 11 1.07788e+06 700622 219490. 4479.39 0.02 0.053217 0.04359 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_update_type/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_update_type/config/golden_results.txt index c252f9475c5..c586563ed5c 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_update_type/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_update_type/config/golden_results.txt @@ -1,5 +1,5 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_auto 0.95 0.05 9252 4 0.14 -1 -1 33036 -1 -1 19 11 0 0 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_update_type/run001/k6_N10_mem32K_40nm.xml/stereovision3.v/common_--timing_update_type_auto 28864 11 30 262 292 2 104 60 7 7 49 clb auto 0.06 411 0.08 0.00 2.21827 -167.491 -2.21827 2.12157 0.000292249 0.000234575 0.0337405 0.02608 -1 476 21 1.07788e+06 1.02399e+06 207176. 4228.08 0.03 0.0509136 0.0405874 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_full 0.99 0.05 9348 4 0.14 -1 -1 33080 -1 -1 19 11 0 0 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_update_type/run001/k6_N10_mem32K_40nm.xml/stereovision3.v/common_--timing_update_type_full 28948 11 30 262 292 2 104 60 7 7 49 clb auto 0.06 411 0.08 0.00 2.21827 -167.491 -2.21827 2.12157 0.000286383 0.000229729 0.0339332 0.0262336 -1 476 21 1.07788e+06 1.02399e+06 207176. 4228.08 0.03 0.0511426 0.0408293 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_incremental 0.88 0.05 9332 4 0.13 -1 -1 33064 -1 -1 19 11 0 0 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_update_type/run001/k6_N10_mem32K_40nm.xml/stereovision3.v/common_--timing_update_type_incremental 28856 11 30 262 292 2 104 60 7 7 49 clb auto 0.06 411 0.07 0.00 2.21827 -167.491 -2.21827 2.12157 3.6119e-05 2.0841e-05 0.0209833 0.0145752 -1 476 21 1.07788e+06 1.02399e+06 207176. 4228.08 0.02 0.0325579 0.0238664 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_incremental_--quench_recompute_divider_999999999 0.89 0.03 9328 4 0.11 -1 -1 33028 -1 -1 19 11 0 0 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_update_type/run001/k6_N10_mem32K_40nm.xml/stereovision3.v/common_--timing_update_type_incremental_--quench_recompute_divider_999999999 28992 11 30 262 292 2 104 60 7 7 49 clb auto 0.08 411 0.07 0.00 2.21827 -167.491 -2.21827 2.12157 0.000766939 0.000184216 0.0219317 0.0149481 -1 476 21 1.07788e+06 1.02399e+06 207176. 4228.08 0.02 0.0335243 0.0242639 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_auto 2.78 0.04 9328 4 0.13 -1 -1 36848 -1 -1 18 11 0 0 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_update_type/run013/k6_N10_mem32K_40nm.xml/stereovision3.v/common_--timing_update_type_auto 24668 11 29 257 286 2 102 58 7 7 49 clb auto 0.06 370 0.09 0.00 2.20099 -163.509 -2.20099 2.10428 0.000231474 0.00017371 0.0269249 0.0205426 -1 429 20 1.07788e+06 970092 207176. 4228.08 0.03 0.0430604 0.0345984 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_full 2.81 0.04 9308 4 0.12 -1 -1 36884 -1 -1 18 11 0 0 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_update_type/run013/k6_N10_mem32K_40nm.xml/stereovision3.v/common_--timing_update_type_full 24560 11 29 257 286 2 102 58 7 7 49 clb auto 0.06 370 0.09 0.00 2.20099 -163.509 -2.20099 2.10428 0.00023374 0.00017568 0.0261162 0.0198127 -1 429 20 1.07788e+06 970092 207176. 4228.08 0.03 0.0425315 0.0341371 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_incremental 2.76 0.04 9288 4 0.12 -1 -1 37340 -1 -1 18 11 0 0 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_update_type/run013/k6_N10_mem32K_40nm.xml/stereovision3.v/common_--timing_update_type_incremental 24692 11 29 257 286 2 102 58 7 7 49 clb auto 0.06 370 0.09 0.00 2.20099 -163.509 -2.20099 2.10428 5.8204e-05 4.3442e-05 0.0227884 0.0171697 -1 429 20 1.07788e+06 970092 207176. 4228.08 0.03 0.0353913 0.0278686 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +k6_N10_mem32K_40nm.xml stereovision3.v common_--timing_update_type_incremental_--quench_recompute_divider_999999999 2.76 0.04 9164 4 0.12 -1 -1 37136 -1 -1 18 11 0 0 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_timing_update_type/run013/k6_N10_mem32K_40nm.xml/stereovision3.v/common_--timing_update_type_incremental_--quench_recompute_divider_999999999 24720 11 29 257 286 2 102 58 7 7 49 clb auto 0.06 370 0.09 0.00 2.20099 -163.509 -2.20099 2.10428 0.000706697 0.000206204 0.0224299 0.0165627 -1 429 20 1.07788e+06 970092 207176. 4228.08 0.03 0.0346928 0.0269701 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_titan/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_titan/config/golden_results.txt index c028d04eb74..fc786cbf8d6 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_titan/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_titan/config/golden_results.txt @@ -1,2 +1,2 @@ -arch circuit script_params vtr_flow_elapsed_time error num_io num_LAB num_DSP num_M9K num_M144K num_PLL vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time -stratixiv_arch.timing.xml ucsb_152_tap_fir_stratixiv_arch_timing.blif common 58.38 42 750 0 0 0 0 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_titan/run015/stratixiv_arch.timing.xml/ucsb_152_tap_fir_stratixiv_arch_timing.blif/common 997336 13 29 26295 20086 1 12417 792 39 29 1131 LAB auto 9.81 77912 17.33 0.10 5.12079 -4876.18 -4.12079 2.74162 0.0139895 0.010985 2.50669 1.70375 82153 28190 37696 29527083 3283224 0 0 2.17765e+07 19254.2 14 5.31542 2.74311 -5419.85 -4.31542 0 0 2.78 3.37429 2.44936 +arch circuit script_params vtr_flow_elapsed_time error num_io num_LAB num_DSP num_M9K num_M144K num_PLL vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time +stratixiv_arch.timing.xml ucsb_152_tap_fir_stratixiv_arch_timing.blif common 91.84 42 750 0 0 0 0 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_titan/run010/stratixiv_arch.timing.xml/ucsb_152_tap_fir_stratixiv_arch_timing.blif/common 965876 13 29 26295 20086 1 12417 792 39 29 1131 LAB auto 11.32 76598 50.52 0.35 5.12079 -4836.29 -4.12079 2.70704 0.0278641 0.0228553 3.54314 2.87621 80209 28118 37672 29749453 3289834 0 0 2.17613e+07 19240.8 15 5.32359 2.74868 -5384.88 -4.32359 0 0 3.63 4.73003 3.93384 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_two_chains/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_two_chains/config/golden_results.txt index 6cace066b32..e965af16b81 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_two_chains/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_two_chains/config/golden_results.txt @@ -1,2 +1,2 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length -k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml diffeq2.v common 16.50 0.03 8884 6 0.15 -1 -1 34056 -1 -1 15 66 0 -1 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_two_chains/run015/k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml/diffeq2.v/common 51964 66 96 1000 687 1 576 192 18 18 324 mult_27 auto 1.09 4949 1.15 0.00 15.0088 -833.523 -15.0088 15.0088 0.0011633 0.00105857 0.172945 0.154747 60 12307 48 6.4517e+06 1.13409e+06 1.66893e+06 5151.03 11.70 0.84001 0.762799 10840 24 3207 7121 2485336 618188 17.4691 17.4691 -1077.83 -17.4691 0 0 2.06264e+06 6366.18 0.47 0.122432 0.114905 135 200 146 33 66 33 +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time num_le num_luts num_add_blocks max_add_chain_length num_sub_blocks max_sub_chain_length +k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml diffeq2.v common 19.80 0.02 8844 6 0.10 -1 -1 37724 -1 -1 15 66 0 -1 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_two_chains/run015/k6_frac_N10_4add_2chains_depop50_mem20K_22nm.xml/diffeq2.v/common 42996 66 96 1000 687 1 576 192 18 18 324 mult_27 auto 1.43 4941 1.74 0.01 15.4335 -866.905 -15.4335 15.4335 0.00128398 0.00115361 0.194197 0.17403 56 12595 29 6.4517e+06 1.13409e+06 1.55150e+06 4788.57 11.93 0.76117 0.692569 11480 40 3900 9056 4382145 1312294 16.9636 16.9636 -1106.96 -16.9636 0 0 1.95585e+06 6036.58 0.76 0.126213 0.117586 133 200 146 33 66 33 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_unroute_analysis/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_unroute_analysis/config/golden_results.txt index eb1eda4b91a..49d13c1761d 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_unroute_analysis/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_unroute_analysis/config/golden_results.txt @@ -1,5 +1,5 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6_N10_mem32K_40nm.xml traffic.blif common_--route_chan_width_20 0.14 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 6 0 0 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_unroute_analysis/run014/k6_N10_mem32K_40nm.xml/traffic.blif/common_--route_chan_width_20 25096 6 8 39 47 1 20 17 5 5 25 clb auto 0.01 51 0.02 0.00 1.10382 -14.1235 -1.10382 1.10382 7.102e-05 5.5257e-05 0.00769392 0.0058538 59 132 190 6966 3181 323364 161682 20103.2 804.128 23 1.30883 1.30883 -16.0731 -1.30883 0 0 0.01 0.0115487 0.00901437 -k6_N10_mem32K_40nm.xml traffic.blif common_--route_chan_width_20_--analysis 0.16 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 6 0 0 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_unroute_analysis/run014/k6_N10_mem32K_40nm.xml/traffic.blif/common_--route_chan_width_20_--analysis 25104 6 8 39 47 1 20 17 5 5 25 clb auto 0.01 51 0.02 0.00 1.10382 -14.1235 -1.10382 1.10382 7.024e-05 5.4449e-05 0.00771493 0.00591894 59 132 190 6966 3181 323364 161682 20103.2 804.128 23 1.30883 1.30883 -16.0731 -1.30883 0 0 0.01 0.0115629 0.00905474 -k6_N10_mem32K_40nm.xml traffic.blif common_--route_chan_width_8 0.16 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 6 0 0 exited with return code 2 v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_unroute_analysis/run014/k6_N10_mem32K_40nm.xml/traffic.blif/common_--route_chan_width_8 24948 6 8 39 47 1 20 17 5 5 25 clb auto 0.01 51 0.02 0.00 1.10205 -14.0594 -1.10205 1.10205 7.086e-05 5.5008e-05 0.00806438 0.00621324 -1 791 1058 67582 46410 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.03 -1 -1 -k6_N10_mem32K_40nm.xml traffic.blif common_--route_chan_width_8_--analysis 0.19 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 6 0 0 exited with return code 2 v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_unroute_analysis/run014/k6_N10_mem32K_40nm.xml/traffic.blif/common_--route_chan_width_8_--analysis 24912 6 8 39 47 1 20 17 5 5 25 clb auto 0.02 51 0.02 0.00 1.10205 -14.0594 -1.10205 1.10205 7.1272e-05 5.5589e-05 0.00799577 0.00615493 133 791 1058 67582 46410 323364 161682 9037.03 361.481 -1 1.58422 1.58422 -20.6732 -1.58422 0 0 0.03 -1 -1 +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k6_N10_mem32K_40nm.xml traffic.blif common_--route_chan_width_20 0.23 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 6 0 0 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_unroute_analysis/run008/k6_N10_mem32K_40nm.xml/traffic.blif/common_--route_chan_width_20 22228 6 8 39 47 1 20 17 5 5 25 clb auto 0.01 51 0.01 0.00 1.10382 -14.1235 -1.10382 1.10382 3.6414e-05 2.697e-05 0.00407625 0.00305922 59 132 190 6966 3181 323364 161682 20103.2 804.128 23 1.30883 1.30883 -16.0731 -1.30883 0 0 0.01 0.00694031 0.00555139 +k6_N10_mem32K_40nm.xml traffic.blif common_--route_chan_width_20_--analysis 0.20 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 6 0 0 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_unroute_analysis/run008/k6_N10_mem32K_40nm.xml/traffic.blif/common_--route_chan_width_20_--analysis 22092 6 8 39 47 1 20 17 5 5 25 clb auto 0.01 51 0.01 0.00 1.10382 -14.1235 -1.10382 1.10382 3.6866e-05 2.7306e-05 0.00413992 0.00310937 59 132 190 6966 3181 323364 161682 20103.2 804.128 23 1.30883 1.30883 -16.0731 -1.30883 0 0 0.01 0.00701039 0.00561232 +k6_N10_mem32K_40nm.xml traffic.blif common_--route_chan_width_8 0.16 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 6 0 0 exited with return code 2 v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_unroute_analysis/run008/k6_N10_mem32K_40nm.xml/traffic.blif/common_--route_chan_width_8 22056 6 8 39 47 1 20 17 5 5 25 clb auto 0.01 51 0.02 0.00 1.10205 -14.0594 -1.10205 1.10205 3.6581e-05 2.7082e-05 0.00427498 0.00320609 -1 2316 3067 209578 145898 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0.06 -1 -1 +k6_N10_mem32K_40nm.xml traffic.blif common_--route_chan_width_8_--analysis 0.16 -1 -1 -1 -1 -1 -1 -1 -1 -1 3 6 0 0 exited with return code 2 v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_unroute_analysis/run008/k6_N10_mem32K_40nm.xml/traffic.blif/common_--route_chan_width_8_--analysis 22120 6 8 39 47 1 20 17 5 5 25 clb auto 0.01 51 0.01 0.00 1.10205 -14.0594 -1.10205 1.10205 3.6543e-05 2.7175e-05 0.00423035 0.00317678 121 2316 3067 209578 145898 323364 161682 9037.03 361.481 -1 1.6143 1.6143 -19.9972 -1.6143 0 0 0.06 -1 -1 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_verify_rr_graph/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_verify_rr_graph/config/golden_results.txt index 7bb27bd19a1..51a7fa4d649 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_verify_rr_graph/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_verify_rr_graph/config/golden_results.txt @@ -1,3 +1,3 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k4_N4_90nm.xml stereovision3.v common 1.86 0.03 8768 6 0.12 -1 -1 33068 -1 -1 66 11 -1 -1 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_verify_rr_graph/run014/k4_N4_90nm.xml/stereovision3.v/common 25664 11 30 336 366 2 186 107 11 11 121 clb auto 0.05 1075 0.13 0.00 3.34892 -239.501 -3.34892 3.03185 0.000358116 0.000274374 0.036725 0.0279494 1041 911 2575 182253 35690 180575 147135 597941. 4941.66 14 3.34892 3.06614 -250.482 -3.34892 -0.21991 -0.0734 0.04 0.050806 0.0400998 -k6_frac_N10_40nm.xml stereovision3.v common 1.43 0.05 8872 4 0.13 -1 -1 33040 -1 -1 13 11 -1 -1 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_verify_rr_graph/run014/k6_frac_N10_40nm.xml/stereovision3.v/common 22672 11 30 262 292 2 110 54 6 6 36 clb auto 0.08 357 0.08 0.00 2.2451 -160.339 -2.2451 2.08659 0.000289048 0.000232304 0.0373107 0.0293951 483 216 348 12809 4438 862304 700622 161034. 4473.17 7 2.54203 2.24422 -180.244 -2.54203 0 0 0.02 0.0490499 0.0400724 +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k4_N4_90nm.xml stereovision3.v common 3.52 0.03 8656 6 0.14 -1 -1 36996 -1 -1 56 11 -1 -1 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_verify_rr_graph/run013/k4_N4_90nm.xml/stereovision3.v/common 21756 11 29 304 333 2 158 96 10 10 100 clb auto 0.04 803 0.16 0.00 3.04826 -213.434 -3.04826 2.70634 0.000289024 0.000218347 0.0279726 0.0210308 722 743 1951 131057 24360 142676 124842 477174. 4771.74 14 3.04826 2.74128 -217.929 -3.04826 -0.21991 -0.0734 0.04 0.0412003 0.0326469 +k6_frac_N10_40nm.xml stereovision3.v common 3.17 0.03 8708 4 0.11 -1 -1 37200 -1 -1 13 11 -1 -1 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_verify_rr_graph/run013/k6_frac_N10_40nm.xml/stereovision3.v/common 20884 11 29 257 286 2 106 53 6 6 36 clb auto 0.10 325 0.11 0.00 2.34363 -153.628 -2.34363 2.13189 0.000222948 0.000168565 0.0338601 0.0259718 442 210 295 14145 4959 862304 700622 161034. 4473.17 10 2.62755 2.33538 -171.977 -2.62755 0 0 0.02 0.0468982 0.0378824 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_verify_rr_graph_bin/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_verify_rr_graph_bin/config/golden_results.txt index fa4adbd43a2..ba1e2db74ec 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_verify_rr_graph_bin/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_verify_rr_graph_bin/config/golden_results.txt @@ -1,3 +1,3 @@ -arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k4_N4_90nm.xml stereovision3.v common 1.71 0.03 8784 6 0.18 -1 -1 33068 -1 -1 66 11 -1 -1 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_verify_rr_graph_bin/run011/k4_N4_90nm.xml/stereovision3.v/common 27416 11 30 336 366 2 186 107 11 11 121 clb auto 0.04 1075 0.13 0.00 3.34892 -239.501 -3.34892 3.03185 0.000354345 0.0002719 0.0362337 0.0276948 1041 911 2575 182253 35690 180575 147135 597941. 4941.66 14 3.34892 3.06614 -250.482 -3.34892 -0.21991 -0.0734 0.04 0.0529663 0.0421552 -k6_frac_N10_40nm.xml stereovision3.v common 1.47 0.04 8820 4 0.14 -1 -1 33116 -1 -1 13 11 -1 -1 success v8.0.0-1877-g77d3b9ae4 release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-06-02T18:06:14 betzgrp-wintermute.eecg.utoronto.ca /home/kmurray/trees/vtr/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_verify_rr_graph_bin/run011/k6_frac_N10_40nm.xml/stereovision3.v/common 23336 11 30 262 292 2 110 54 6 6 36 clb auto 0.09 357 0.07 0.00 2.2451 -160.339 -2.2451 2.08659 0.000306875 0.00024976 0.034639 0.0269934 483 216 348 12809 4438 862304 700622 161034. 4473.17 7 2.54203 2.24422 -180.244 -2.54203 0 0 0.02 0.0464467 0.0377276 +arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time +k4_N4_90nm.xml stereovision3.v common 3.29 0.03 8720 6 0.13 -1 -1 36924 -1 -1 56 11 -1 -1 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_verify_rr_graph_bin/run013/k4_N4_90nm.xml/stereovision3.v/common 22260 11 29 304 333 2 158 96 10 10 100 clb auto 0.04 803 0.16 0.00 3.04826 -213.434 -3.04826 2.70634 0.000277112 0.000207236 0.0277894 0.0209872 722 743 1951 131057 24360 142676 124842 477174. 4771.74 14 3.04826 2.74128 -217.929 -3.04826 -0.21991 -0.0734 0.04 0.0409386 0.0325138 +k6_frac_N10_40nm.xml stereovision3.v common 3.11 0.03 8824 4 0.11 -1 -1 36972 -1 -1 13 11 -1 -1 success v8.0.0-2557-g58d57ce48 release IPO VTR_ASSERT_LEVEL=3 GNU 7.5.0 on Linux-4.15.0-112-generic x86_64 2020-09-03T01:11:22 119-201-1 /mnt/comparison_results/vtr-verilog-to-routing/vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_verify_rr_graph_bin/run013/k6_frac_N10_40nm.xml/stereovision3.v/common 21152 11 29 257 286 2 106 53 6 6 36 clb auto 0.10 325 0.11 0.00 2.34363 -153.628 -2.34363 2.13189 0.000231401 0.000176562 0.0334837 0.0256583 442 210 295 14145 4959 862304 700622 161034. 4473.17 10 2.62755 2.33538 -171.977 -2.62755 0 0 0.02 0.0468271 0.0378647