+ 
@@ -55,7 +55,7 @@
-->
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| " + "TraceTable" + " | "; + tracetable += "|||||||||||||
| " + "PC" + " | "; + tracetable += "" + "Cycle" + " | "; + tracetable += "" + "RegDst" + " | "; + tracetable += "" + "Branch" + " | "; + tracetable += "" + "MemRead" + " | "; + tracetable += "" + "MemtoReg" + " | "; + tracetable += "" + "MemWrite" + " | "; + tracetable += "" + "ALUSrc" + " | "; + tracetable += "" + "RegWrite" + " | "; + tracetable += "" + "Immediate" + " | "; + tracetable += "" + "LoadType" + " | "; + tracetable += "" + "Jump" + " | "; + tracetable += "" + "Unsigned" + " | "; + tracetable += "" + "Shift" + " | "; + tracetable += "
| " + "Steps" + " | "; + tablecontents += "
| " + line[y] + " | "; + } + tablecontents += "
| " + "Default View" + " | "; + tablecontents += "
| " + "Registers" + " | "; + tablecontents += "|||
| " + registerNames[i] + " | "; + tablecontents += "" + registers[i] + " | "; + tablecontents += "" + registers[i].toString(16).toUpperCase() + " | "; + tablecontents += "" + createBinaryString(registers[i]) + " | "; + tablecontents += "
| " + "Memory" + " | "; + tablecontents += "||||
| " + counter + " | "; + counter++; + tablecontents += "" + i + " | "; + tablecontents += "" + tempOne + " | "; + tablecontents += "" + tempOne.toString(16).toUpperCase() + " | "; + tablecontents += "" + one + " | "; + tablecontents += "
| " + counter + " | "; + counter++; + tablecontents += ""+ " | "; + tablecontents += "" + tempTwo+ " " + " | "; + tablecontents += "" + tempTwo.toString(16).toUpperCase() + " | "; + tablecontents += "" + two + " | "; + tablecontents += "
| " + counter + " | "; + counter++; + tablecontents += ""+ " | "; + tablecontents += "" + tempThree + " | "; + tablecontents += "" + tempThree.toString(16).toUpperCase() + " | "; + tablecontents += "" + three + " | "; + tablecontents += "
| " + counter + " | "; + counter++; + tablecontents += ""+ " | "; + tablecontents += "" + tempFour + " | "; + tablecontents += "" + tempFour.toString(16).toUpperCase() + " | "; + tablecontents += "" + four + " | "; + tablecontents += "
+ Type the code you want to execute and click simulate.
+
It will simlate the code instruction by instruction and show the trace table, registers and memory spaces.
+ To view the trace, click on the steps section on the left pane.
NOTE: Use space between register variables. Spaces before instruction will make the instruction invalid.
+
| 0 | +rs | +rt | +rd | +shamt | +funct | +
| 31:26 | +25:21 | +20:16 | +15:11 | +10:6 | +5:0 | +
INSTRUCTIONS SUPPORTED- add, sub, and, or, etc
Eg. add $a1 $a1 $a2
| 35 or 43 | +rs | +rt | +address | +
| 31:26 | +25:21 | +20:16 | +15:0 | +
INSTRUCTIONS SUPPORTED- addi, subi, andi, ori, etc
Eg. addi $a1 $a1 72
| 4 | +rs | +rt | +address | +
| 31:26 | +25:21 | +20:16 | +15:0 | +
INSTRUCTIONS SUPPORTED- j
Eg. j 73
| add | +sub | +and | +or | +beq | +
| addi | +andi | +ori | +nor | +bne | +
| lw | +lh | +lhu | +lb | +lbu | +
| sw | +sh | +sb | +lui | +sll | +
| srl | +j | +jal | +jr | +slt | +
| t |