From 26d3f42afa0cddc55a4ae7546c9625880ae2d864 Mon Sep 17 00:00:00 2001 From: mrudhvika940 Date: Mon, 11 May 2020 15:08:30 +0530 Subject: [PATCH 01/17] Updated CSS in lab landing pages and exp1 --- src/lab/Courses Aligned.html | 358 ++++----- src/lab/Feedback.html | 369 ++++----- src/lab/Introduction.html | 399 +++++----- src/lab/List of experiments.html | 705 +++++++++--------- src/lab/Prerequisites.html | 383 +++++----- src/lab/Target Audience.html | 357 ++++----- src/lab/documents/flash-plugin.pdf | Bin 0 -> 32104 bytes .../EXP_1sep2010/exp1/Feedback.html | 426 ++++++----- .../EXP_1sep2010/exp1/Introduction.html | 460 ++++++------ .../final-build/EXP_1sep2010/exp1/Manual.html | 403 +++++----- .../EXP_1sep2010/exp1/Objective.html | 421 ++++++----- .../EXP_1sep2010/exp1/Procedure.html | 404 +++++----- .../final-build/EXP_1sep2010/exp1/Quiz.html | 594 ++++++++------- .../EXP_1sep2010/exp1/References.html | 423 ++++++----- .../EXP_1sep2010/exp1/Simulator.html | 409 +++++----- .../final-build/EXP_1sep2010/exp1/Theory.html | 591 ++++++++------- .../EXP_1sep2010/exp2/Introduction.html | 5 +- .../EXP_1sep2010/exp2/Objective.html | 3 +- .../EXP_1sep2010/exp2/Procedure.html | 5 +- .../final-build/EXP_1sep2010/exp2/Quiz.html | 5 +- .../EXP_1sep2010/exp2/References.html | 5 +- .../EXP_1sep2010/exp2/Simulator.html | 5 +- .../EXP_1sep2010/exp3/Introduction.html | 5 +- .../final-build/EXP_1sep2010/exp3/Manual.html | 5 +- .../EXP_1sep2010/exp3/Objective.html | 5 +- .../EXP_1sep2010/exp3/Procedure.html | 5 +- .../final-build/EXP_1sep2010/exp3/Quiz.html | 5 +- .../EXP_1sep2010/exp3/References.html | 5 +- .../EXP_1sep2010/exp3/Simulator.html | 5 +- .../final-build/EXP_1sep2010/exp3/Theory.html | 5 +- .../EXP_1sep2010/exp4/Feedback.html | 5 +- .../EXP_1sep2010/exp4/Introduction.html | 9 +- .../final-build/EXP_1sep2010/exp4/Manual.html | 5 +- .../EXP_1sep2010/exp4/Objective.html | 5 +- .../EXP_1sep2010/exp4/Procedure.html | 5 +- .../final-build/EXP_1sep2010/exp4/Quiz.html | 5 +- .../EXP_1sep2010/exp4/References.html | 5 +- .../EXP_1sep2010/exp4/Simulator.html | 5 +- .../final-build/EXP_1sep2010/exp4/Theory.html | 5 +- .../EXP_1sep2010/exp5/Feedback.html | 5 +- .../EXP_1sep2010/exp5/Introduction.html | 5 +- .../final-build/EXP_1sep2010/exp5/Manual.html | 5 +- .../EXP_1sep2010/exp5/Objective.html | 5 +- .../EXP_1sep2010/exp5/Procedure.html | 5 +- .../final-build/EXP_1sep2010/exp5/Quiz.html | 5 +- .../EXP_1sep2010/exp5/References.html | 5 +- .../EXP_1sep2010/exp5/Simulator.html | 5 +- .../final-build/EXP_1sep2010/exp5/Theory.html | 5 +- .../EXP_1sep2010/exp6/Feedback.html | 5 +- .../EXP_1sep2010/exp6/Introduction.html | 5 +- .../final-build/EXP_1sep2010/exp6/Manual.html | 8 +- .../EXP_1sep2010/exp6/Objective.html | 5 +- .../EXP_1sep2010/exp6/Procedure.html | 5 +- .../final-build/EXP_1sep2010/exp6/Quiz.html | 5 +- .../EXP_1sep2010/exp6/References.html | 5 +- .../EXP_1sep2010/exp6/Simulator.html | 5 +- .../final-build/EXP_1sep2010/exp6/Theory.html | 5 +- src/lab/index.html | 391 +++++----- src/themes/green-icon/css/style.css | 49 +- 59 files changed, 3871 insertions(+), 3481 deletions(-) create mode 100644 src/lab/documents/flash-plugin.pdf diff --git a/src/lab/Courses Aligned.html b/src/lab/Courses Aligned.html index ae59c480..1c58533d 100644 --- a/src/lab/Courses Aligned.html +++ b/src/lab/Courses Aligned.html @@ -1,176 +1,186 @@ - - - - - - - - - Welcome to Virtual Labs - A MHRD Govt of india Initiative - - - - - - - - - - - - - - - - - - -
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Computer Science & Engineering

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Introduction

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List of experiments

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Target Audience

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Courses Aligned

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Prerequisites

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Feedback

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+ +

Very Large Scale Integration Lab

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+ The present lab is aligned with VLSI course structure. The experiments touch on most topics covered in such courses in most curricula. +

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+ + + + + + + + + + + \ No newline at end of file diff --git a/src/lab/Feedback.html b/src/lab/Feedback.html index c2e6a62f..6d0deca0 100644 --- a/src/lab/Feedback.html +++ b/src/lab/Feedback.html @@ -1,172 +1,203 @@ - - - - - - - - - Welcome to Virtual Labs - A MHRD Govt of india Initiative - - - - - - - - - - - - - - - + + + + + + + + + + + + Welcome to Virtual Labs - A MHRD Govt of india Initiative + + + + + + + + + + + + + + -
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Computer Science & Engineering

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Introduction

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List of experiments

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Courses Aligned

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Prerequisites

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Feedback

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Data Structures

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Dear User,

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+ Thanks for using Virtual Labs. Your opinion is valuable to us. To help us improve, we'd like to ask you a few questions about your experience. It will only take 3 minutes and your answers will help us + make Virtual Labs better for you and other users. +

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+ + + + +
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+ +

+ Thanks for your time ! +
+ The Virtual Labs Team +

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+ + \ No newline at end of file diff --git a/src/lab/Introduction.html b/src/lab/Introduction.html index efe718a6..cfa0439b 100644 --- a/src/lab/Introduction.html +++ b/src/lab/Introduction.html @@ -1,210 +1,235 @@ - + + + + - - - - - + + + + + - - Welcome to Virtual Labs - A MHRD Govt of india Initiative - - - - - - + Welcome to Virtual Labs - A MHRD Govt of india Initiative + - - - - - + - - - - - - + - + + + - - -
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Computer Science & Engineering

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Introduction

List of experiments

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Very Large Scale Integration Lab

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A single chip sized of few millimeters may have Millions of transistors in it for example a microprocessor is a VLSI device. - Very Large Scale Integration (VLSI) is the process of creating integrated circuits by combining large numbers of transistors into a single chip.

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This lab provides good understanding and learning opportunity of VLSI designing for users. - There are ten experiments in this lab, which covers following aspects of VLSI designing.

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  • First six experiments provide GUI interface of schematic design and simulation results of various circuits.


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  • Seventh experiment provides WEB based Spice code simulation platform. User can learn circuit design using Spice coding.


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  • Eighth and ninth experiments provide digital circuit designing using Verilog code for which a web based Verilog simulation - platform is provided. User can test any level of Verilog code in ninth experiment.


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  • Tenth experiment provides GUI interface of physical (layout) design of various circuits. By this experiment user can learn design rules - (DRCs) for layout design and can test design rules of their designs.


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    Introduction

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    Courses Aligned

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    Prerequisites

     +

    Feedback

     +
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    + +

    Very Large Scale Integration Lab

    +
    +

    + A single chip sized of few millimeters may have Millions of transistors in it for example a microprocessor is a VLSI device. Very Large Scale Integration (VLSI) is the process of creating integrated + circuits by combining large numbers of transistors into a single chip.
    +

    +

    +
    +

    +
    +

    This lab provides good understanding and learning opportunity of VLSI designing for users. There are ten experiments in this lab, which covers following aspects of VLSI designing.

    +
    +

    +
      +

    • First six experiments provide GUI interface of schematic design and simulation results of various circuits.

      • +
      +

    • Seventh experiment provides WEB based Spice code simulation platform. User can learn circuit design using Spice coding.

      • +
      +
    • +

      + Eighth and ninth experiments provide digital circuit designing using Verilog code for which a web based Verilog simulation platform is provided. User can test any level of Verilog code in ninth + experiment. +

      +
      • +
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      + Tenth experiment provides GUI interface of physical (layout) design of various circuits. By this experiment user can learn design rules (DRCs) for layout design and can test design rules of their + designs. +

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      + + - - + - - + - - - - + + + + \ No newline at end of file diff --git a/src/lab/List of experiments.html b/src/lab/List of experiments.html index c37e8f27..19b8ef0c 100644 --- a/src/lab/List of experiments.html +++ b/src/lab/List of experiments.html @@ -1,341 +1,371 @@ - - - - - - - - - Welcome to Virtual Labs - A MHRD Govt of india Initiative - - - - - - - - - - - - - - - - - - - - - - - - - - -
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      Computer Science & Engineering

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      Introduction

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      List of experiments

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      Courses Aligned

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      Prerequisites

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      Feedback

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      Very Large Scale Integration Lab

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      • + + + + Schematic Design Of Transistor Level Inverter +
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        Click here to see Description

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        + In this experiment we will learn the basic design of an inverter. Inverter is the most basic component which we can make out using one NMOS and one PMOS transistor. Here you will learn about the + basics how inverter works internally, how the transistor are placed inside inverter and how we get the inverted output corresponding to the inputs we provide. We will learn the layout designing and + effects of capacitance and effects of width and length of transistor on the output of an inverter. +
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      • + Schematic Design Of Transistor Level NAND & NOR Gate. +
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        Click here to see Description

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        + In this experiment, we will learn about the series and parallel combination of n-switches and p-switches. Then we will proceed to the transistor level designing of NAND and NOR gate using NMOS and + PMOS and also layout designing of the same. +
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      • + Schematic Design Of Transistor Level XOR & XNOR Gate. +
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        Click here to see Description

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        + In this experiment, we will first learn how to deduce parallel and series combination of n and p-switches given a combinational logic and hence design them, specifically XOR and XNOR. +
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      • + Schematic Design Of Pass Transistor Logic & Multiplexer.
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        +

        Click here to see Description

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        + Transmission gates are used in digital circuits to pass or block particular signal from the components. In transmission gates, NMOS and PMOS are parallel connected to each other. Schematic + representation of transmission gate and its circuit symbol are shown below. +
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      • + Delay Estimation In Chain Of Inverters. +
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        Click here to see Description

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        + The method of logical effort is one of the methods used to estimate delay in a CMOS circuit. The model describes delay caused by the capacitive load that the logic gate drives and by the topology of + the logic gate. As the gate increases delay also increases, but delay depends on the logic function of the gate also. +
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      • + Schematic Design Of D-Latch and D-Flip Flop. +
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        Click here to see Description

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        + Latch is an electronic device that can be used to store one bit of information. The D latch is used to capture, or latch the logic level which is present on the Data line when the clock input is high. + If the data on the D line changes state while the clock pulse is high, then the output, Q, follows the input, D. When the CLK input falls to logic 0, the last state of the D input is trapped and held + in the latch. +
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      • + Spice Code Platform. +
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        Click here to see Description

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        + In the experiments we have done till now we have designed gates by arranging transistors in various fashions .The simulation of these designs gave graphs of output voltages and we analyzed how these + graph changes with varying different parameters of the transistor. Now when you place a transistor on screen there is a back end code which tells a simulator what are the points to which the + transistor's substrate,gate,drain,source are connected. The language in which this information is conveyed is spice. +
        + +
      • + Design Of D-Flip Flop Using Verilog. +
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        Click here to see Description

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        + Till now we have dealt with transistor level issues involved in designing a gate and studied the effects on the waveforms on changing various parameters of transistor(length and width) .The graphs we + have seen till now will gives the corresponding analog output voltages. In the earlier experiments, when a transistor was placed and connections were made a spice code was written in the back end. We + learned spice in the previous experiment . Now we proceed towards digital level designing of circuits for example lets take an or gate in the second experiment was we arranged pmos and nmos in a + particular fashion and simulated to obtain a graph , changing the parameters we analyzed how the rise time ,fall time ,delay etc. changes. If you observe the graph you will find that the input changes + from low value near 0 V to high value near 5V ,the rise is not steep one but gradual . In digital designing we will bother only about two levels 0 and 1(a threshold is determined i.e. voltages below + threshold will be 0 and those above will be 1 )As we move towards digital designing we shift our concerns from how does the analog voltage changes to how to generate a desired output from a given + sequence of inputs. For instance now we will visualize gate as an entity which will gives the desired truth table. +
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      • + Design Of Digital Circuits Using Verilog. +
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        Click here to see Description

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        + Verilog is language commonly used in designing digital systems. It is a hardware description language, which means that it is substantially different from any other language you might have encountered + so far. Even though it does have control flow statements and variables, it relies primarily on logic functions.It is a textual format for describing electronic circuits and systems. +
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      • + Layout Design. +
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      Computer Science & Engineering

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      Introduction

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      Prerequisites

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      Feedback

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      Very Large Scale Integration Lab

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      + The current version of the Virtual Lab applets pages requires a web browser and the Java plug-in (version 1.5.0_11 or later is recommended). The Java plug-in is part of the + Java Runtime Environment (JRE) . You may check whether Java is installed correctly by visiting the + Test Your Java Version page on the Sun web site. In addition to testing the Java installation, you will obtain information on the installed version + of Java. +
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      • Java allows you to play online virtual labs.
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      • Adobe Flash (formerly Macromedia Flash) is a multimedia platform used to add animation, video, and interactivity to web pages.
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      + Install Java plugin run the simulation +

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      Introduction

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      Prerequisites

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      Feedback

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      Very Large Scale Integration Lab

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      + For the students of UG-ECE and PG-ECE. +

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      Schematic Design Of Transistor Level Inverter

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      Inverter is a logic gate, with one input and one output. Its symbol is shown below:-

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      The output of inverter is complement of the input i.e. if the input is 0, the output will be 1 and vice-versa . The truth table for inverter is shown below:-

      -
      - - - - - - - - - - - - - -
      InputOutput
      01
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      The transistor level schematic of inverter can be designed in many logics,following two logics will be used for designing in the experiment

              * Complementary CMOS logic
              * Pseudo NMOS logic

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      Schematic Design Of Transistor Level Inverter.

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      (a) To design transistor level schematic of an Inverter using

              * Complementary CMOS logic
              * Pseudo NMOS logic


      -

      (b) To find the effect of load capacitance on the rise time and fall time and hence delay of output waveform.


      -

      (c) To find the effect of W/L of transistors on the output waveform.


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      Pre_Quiz

       -
        -
      • What do you mean by rise time and fall time ?
        • -
      • What are the three regions of operation of an inverter ?
        • -
      • What is the expression for gain factor ?
        • -
      • Name the IC used for inverter.
        • -
      -
      - -

      Post_Quiz

       - -
      -
        -
      1. The number of inputs in an inverter is ____.
        - 1
        - 2
        - 3
        - 4

        -
        2. - -
      2. Inverter gate is same as __________.
        - AND gate
        - NOT gate
        - NOR gate
        - NAND gate

        -
        3. - -
      3. Which is the most suitable representation for a NOT gate?
        -

        -

        -

        -


        -
        4. - -
      4. Identify which statement is true for inverter?
        - Any difference in inputs gurantees a high output
        - Any difference in inputs gurantees a low output
        - A high input gives a high output
        - A low input gives a high output

        -
        5. - -
      5. What is the traditional symbol for inverter?
        -
        -
        -
        -

        -
        6. - -
      6. Choose the electrical analogue of an inverter.
        -
        -
        -
        - none of these

        -
        7. - -
      7. What is the correct input voltage range for region D?
        - Vdd/2 < Vin ≤ Vdd-Vtp
        - Vin = Vdd/2
        - 0 ≤ Vin ≤ Vtn
        - Vin ≥ Vdd-Vtp

        -
        8. - -
      8. What are the operation states of n-device and p-device respectively in region B?
        - linear & unsaturated
        - cut-off & linear
        - linear & saturated
        - saturated & linear

        -
        9. - -
      9. What is delay?
        - maximum of rise time and fall time
        - product of rise time and fall time
        - average of rise time and fall time
        - addition of rise time and fall time

        -
        10. - -
      10. What is desirable βn/βp ratio for an inverter?
        - 0
        - 1
        - 0.5
        - ∞

        -
        11. - -
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      1. "Principles of cmos vlsi design"by Weste-Eshraghian

        2. - -
      2. CMOS: Circuit Design, Layout, and Simulation, Third Edition by Bacor, R. Jacob. Wiley-IEEE. pp. 1174.Chen, Wai-Kai (ed) (2006).

        3. -
      3. The VLSI Handbook, Second Edition (Electrical Engineering Handbook) by Boca Raton: CRC. ISBN 0-8493-4199-X.

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      4. http://jas.eng.buffalo.edu/education/fab/NMOS/nmos.html

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      - - -

      Schematic Design Of Transistor Level Inverter

      -

      - -

      CMOS INVERTER


      - -

      In the transistor level design of CMOS inverter consists of nmos and pmos transistor in series.The PMOS transistor is connected between Vdd and output node,whereas the NMOS is connected betweeen the output node and gnd.


      - -

      WORKING OF CMOS INVERTER


      - -

      Before knowing the working of CMOS inverter we will see the regions of operation of transistor so that we can understand what is actually happening inside the inverter. MOS transistors have three regions of operations :
      -     1) cut-off region
      -     2) linear region
      -     3) saturation region
      -

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      The transistor is said to be in cut-off region when Vgs < Vt. Vgs is the voltage applied at gate with respect to source and Vt is the threshhold voltage below which the transistor does not work. So for transistor to work Vgs - Vt should be greater than zero always.


      - -

      The transistor is in linear region when Vgs - Vt > Vds where Vds is the voltage at drain with respect to source.


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      The transistor is said to be in saturation region when vgs - Vt < Vds


      - -

      The transfer characteristic(i.e. the output voltage vs input voltage) is shown in the figure below. The operation is divided into 5 region depending on the range of input voltage(Move your mouse over the region to know about the region).The output voltage in every region is obtained by equating drain to source current of pmos and nmos.


      - -
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      -

      - -

      EFFECT OF W/L RATIO ON OUTPUT WAVEFORM


      - -

      Before proceeding to the study of effect please read the definition of β (gain factor).


      - -

      W/L ratio is directly proportional to β.The ratio βn/βp is crucial in determinig the transfer characteristic of the inverter.When the ratio is increased the transition shifts from left to right,but the output voltage transition remains sharp.For CMOS the ratio is desired to be 1 so that it requires equal time to charge and discharge.


      - -

      EFFECT OF CAPACITANCE ON THE RISE AND FALL TIME


      - -

      The rise time is defined as the time required to charge the capacitor from 10% to 90% and fall time is defined as the time required for the capacitor to discharge from 90% to 10%. - How the rise time and the fall time is calculated is shown in the figure below :


      - - - -

      Greater value of capacitor implies larger rise and fall time,which furthur implies large delay. The rise time and fall time are directly proportional to the capacitance, therefore, greater the value of capacitance, greater will be the time taken for rising and falling.


      - -

      PSEUDO NMOS


      - -

      The gate of p-device is permanently grounded which is equivalent to use of NMOS in depletion mode


      - - -

      SOME BASIC DEFINITIONS AND THEORY


      -

      TRANSISTOR


      - -

      Basically transistor consistes of three parts - GATE, SOURCE and DRAIN as shown in figure below:


      - - - -

      The gate is a control input which determines the flow of electric current between source and drain. Physically drain and source are equivalent and the two types of transistor i.e. n-transistor and p-transistor differ only in the way electric current flows between source and drain according to the different values applied at the controlling gate input. In n-transistor when logic 1 is aplied to gate, the current flows bwetween source and drain while no current flows when logic 0 is applied. The p-transistor works just the opposite way - the current flows between source and drain when logic 0 is applied and no current on logic 1.


      - -

      β - GAIN FACTOR


      - -

      β is the MOS transistor gain factor which depends both on process parameters and geometry parameters.


      - -
      β = k(W/L)
      where K is the factor which shows process dependency
      and W & L shows geometry dependency

      - -

      For NMOS, gain factor is denoted by βn and for PMOS, gain factor is denoted by βp.


      - -

      DELAY


      - -

      Delay time is the time taken for the input transistion (50% level) into output (50% level). The single gate delay is given by the average of rise time and fall time, so delay also is directly proportional to the capacitance value


      - -

      DEPLETION MODE


      - -

      Using NMOS in depletion region means increasing negative voltage on the gate to reduce current flow or we can say to deplete the channel of free carriers which are electrons in n-channel.


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      This lab provides good understanding and learning opportunity of VLSI designing for users. - There are ten experiments in this lab, which covers following aspects of VLSI designing.

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        • -

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        • -


          -





        -
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        Very Large Scale Integration Lab

        +
        +

        + A single chip sized of few millimeters may have millions of transistors in it for example a microprocessor is a VLSI device. Very Large Scale Integration (VLSI) is the process of creating integrated + circuits by combining large numbers of transistors into a single chip.
        +

        +

        +
        +

        +
        +

        This lab provides good understanding and learning opportunity of VLSI designing for users. There are ten experiments in this lab, which covers following aspects of VLSI designing.

        +
        +

        +
          +

        • First six experiments provide GUI interface of schematic design and simulation results of various circuits.

          • +
          +

        • Seventh experiment provides WEB based Spice code simulation platform. User can learn circuit design using Spice coding.

          • +
          +
        • +

          + Eighth and ninth experiments provide digital circuit designing using Verilog code for which a web based Verilog simulation platform is provided. User can test any level of Verilog code in ninth + experiment. +

          +
          • +
          +
        • +

          + Tenth experiment provides GUI interface of physical (layout) design of various circuits. By this experiment user can learn design rules (DRCs) for layout design and can test design rules of their + designs. +

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          DEFINITION OF NAND GATE

          -NAND gate has 1 output and 2 or more input
          -The output of the NAND gate is low only when all the inputs are high else it is low.
          -A NAND gate could be veiwed as an AND gate with inverter at the output

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          SCHEMATIC OF NAND GATE



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          DEFINITION OF NOR GATE

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          NOR gate has 1 output and 2 or more input
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          SCHEMATIC OF NOR GATE



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          Schematic Design Of Transistor Level NAND & NOR Gate

          Experiment Manual is under construction @@ -163,15 +163,15 @@

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          2. Identify the symbol for NOR gate.
            -
            -
            -
            -
            -
            3. -
            - -
          3. How do we represent with n-devices?
            - series connection of n-devices with input A and input B
            - parallel connection of p-devices with input A and input B
            - combination of series and parallel connecton of n-devices
            - none
            -
            4. -
            - -
          4. What is the correct representation (in terms of switches) for two n-devices connected in series having inputs 0 & 1?
            -
            -
            -
            -
            -
            5. -
            - -
          5. What is the correct representation (in terms of switches) for two p-devices connected in series having both inputs as 1?
            -
            - NMOS in parallel and PMOS in series
            - Both NMOS and PMOS in parallel
            - Both NMOS and PMOS in series
            -
            6. -
            - -
          6. Which of the following Boolean expression is represented by the given karnaugh map?

            - B
            - A
            - A+B
            - AB
            -
            7. -
            - -
          7. Which of the following Boolean expression is represented by the given karnaugh map?

            - AB
            - BC
            - AC
            - ABC
            -
            8. -
            - -
          8. Which combination of logic gates is correct for the expression ABCD?
            -
            -


            - Both a & b


            - None
            -
            9. -
            - -
          9. Which combination of logic gates is correct for the following expression?

            -
            -


            - none of the above


            - both a & b
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          2. CMOS: Circuit Design, Layout, and Simulation, Third Edition by Bacor, R. Jacob. Wiley-IEEE. pp. 1174.Chen, Wai-Kai (ed) (2006).

            3. -
          3. The VLSI Handbook, Second Edition (Electrical Engineering Handbook) by Boca Raton: CRC. ISBN 0-8493-4199-X.

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          SWITCHING BEHAVIOUR OF TRANSISTOR

          - -

          The gate of the MOS transistor controls the passage of the current between the drain and source.If the voltage at the gate is Vdd ,no current flows between the drain and source of PMOS and same is the case with NMOS if its gate is grounded.This characteristic of MOS transistors,enables it to be viewed as a switch.The switching behaviour of nmos and pmos device is shown in the figure below.Here the input 0 indicates that the gate is grounded and input 1 indicates that Vdd is applied to the gate:


          - -

          - -

          SERIES AND PARALLEL CONNECTION

          - -

          The transistor level schematic of any combinational logic can be obtained by placing two or more n/p-switches in series or parallel.

          - -

          If switches are connected in series then the composite switch hence constructed is closed when both the switches are closed.The series connection is shown in the figure below.The table indicates the states of the switch contructed by series connection depending on the inputs A and B


          - -

          -

          - Series connection of NMOS devices
          - - - - - - - - - - - - - - -
            B
          A           		0   1
          0
          1          		OFFOFF
          OFFON
          -
          -
          -
          - Series connection of PMOS devices
          - - - - - - - - - - - - - - -
            B
          A           		0   1
          0
          1          		ONOFF
          OFFOFF
          -
          -

          - -

          If the switches are connected in parallel then the composite switch hence constructed is closed when either or both of the switches are closed.The parallel connection is shown in the figure below.The table indicates the states of the switch obtained by parallel connection depending on the inputs A and B

          - - -
          - Parallel connection of NMOS devices
          - - - - - - - - - - - - - - -
            B
          A           		0   1
          0
          1          		OFFON
          ONON
          -
          -
          - -
          - Parallel connection of PMOS devices
          - - - - - - - - - - - - - - -
            B
          A           		0   1
          0
          1          		ONON
          ONOFF
          -
          -
          -
          - -

          By using any combinations of the above constructions,CMOS combinational gates can be obtained.In the following section ,Karnaugh maps for NAND and NOR have been used to determine the required combination


          -

          K-MAP FOR NAND


          -

          -

          Thus for NAND gate PMOS devices are connected in parallel between Vdd and output node,whereas the NMOS devices are in series between output node and ground.


          -

          K-MAP FOR NOR


          - -

          -

          Thus for NOR gate PMOS devices are connected in series between Vdd and output node,whereas the NMOS devices are in parallel between output node and ground.


          - -

          -
          -
          -
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          - - - - - - + + + + + + + - - - - - - - - - - \ No newline at end of file From 87b89bfcf33f1995a5bb2d505fa2571c9a94e0ae Mon Sep 17 00:00:00 2001 From: mrudhvika940 Date: Wed, 13 May 2020 10:14:19 +0530 Subject: [PATCH 03/17] Updated new CSS in exp3 --- .../EXP_1sep2010/exp2/Feedback.html | 3 +- .../EXP_1sep2010/exp2/Objective.html | 3 +- .../EXP_1sep2010/exp2/Procedure.html | 3 +- .../final-build/EXP_1sep2010/exp2/Quiz.html | 3 +- .../EXP_1sep2010/exp2/References.html | 3 +- .../EXP_1sep2010/exp2/Simulator.html | 9 +- .../final-build/EXP_1sep2010/exp2/Theory.html | 3 +- .../EXP_1sep2010/exp3/Feedback.html | 414 ++++++------ .../EXP_1sep2010/exp3/Introduction.html | 563 ++++++++-------- .../final-build/EXP_1sep2010/exp3/Manual.html | 22 +- .../EXP_1sep2010/exp3/Objective.html | 414 ++++++------ .../EXP_1sep2010/exp3/Procedure.html | 410 ++++++------ .../final-build/EXP_1sep2010/exp3/Quiz.html | 615 +++++++++--------- .../EXP_1sep2010/exp3/References.html | 424 ++++++------ .../EXP_1sep2010/exp3/Simulator.html | 406 ++++++------ .../final-build/EXP_1sep2010/exp3/Theory.html | 486 +++++++------- 16 files changed, 1930 insertions(+), 1851 deletions(-) diff --git a/src/lab/final-build/EXP_1sep2010/exp2/Feedback.html b/src/lab/final-build/EXP_1sep2010/exp2/Feedback.html index b9011b3d..606c467a 100755 --- a/src/lab/final-build/EXP_1sep2010/exp2/Feedback.html +++ b/src/lab/final-build/EXP_1sep2010/exp2/Feedback.html @@ -113,7 +113,7 @@

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          XOR(exclusive OR)
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          - The schematic and truth table for 2 input A and B for XOR gate :- -

          SCHEMATIC OF XOR GATE


          - -
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          Input AInput BOutput
          000
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          -


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          XNOR(exclusive OR)
          - For a 2 input XNOR,the output of the gate is high when both the inputs are same(either both low or both high).The output is low if one and only one of the inputs is high.

          - - The schematic and truth table for 2 input A and B for XOR gate :- -

          SCHEMATIC OF XNOR GATE



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          • Draw the truth table for XNOR gate.
            • -
          • Implement A+B using PMOS transistors.
            • -
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            • -
          • How do you convert XOR gate into buffer.
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          Post_Quiz

           - -
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          1. Can you distinguish between AND and XNOR gate when both the inputs are 1?
            - NO
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            - none of the above

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          9. Reduce the expression xy(z+w)+y(xz+xz)+zw and tell the min number of transistor required for the design.
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          1. "Principles of cmos vlsi design"by Weste-Eshraghian
            2. - -
          2. CMOS: Circuit Design, Layout, and Simulation, Third Edition by Bacor, R. Jacob. Wiley-IEEE. pp. 1174. Chen, Wai-Kai (ed) (2006).

            3. -
          3. The VLSI Handbook, Second Edition (Electrical Engineering Handbook) by Boca Raton: CRC. ISBN 0-8493-4199-X.

            4. -
          4. http://jas.eng.buffalo.edu/education/fab/NMOS/nmos.html

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          Schematic Design Of Transistor Level XOR & XNOR Gate.

          -

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          Having gained sufficient knowledge about series and parallel connection, we now move towards desining transistor level schematic for any given combinational logic. This is done by analysing the kmap of the given combination for p- and n-switches and then deducing the required series or parallel combination.The following example will give you an idea about how to go for designing a combinational logic using transistors.we want to design transistor level schematic of (AB+CD)


          - -

          K-MAP


          - - -

          IMPLEMENTATION FOR N-SWITCHES

          - - The series combination of A and B is in parallel with the series combination of C and D. -

          IMPLEMENTATION FOR P-SWITCHES

          - - The parallel combination of A and B is in series with the parallel combination of C and D. -

          The complete design will be as shown in the figure below


          - - - -

          XOR

          - - A ⊕ B = AB + AB
          - - A is analogous to C and B is analogous to D. - If implementation is done according to the example described above we would require 5 NMOS and 5 PMOS.
          4 NMOS and PMOS for implementation of complement of AB+AB
          and 1 pair for the inverter.
          .Now,think of a method to reduce the number of transistor. 1 pair needed for inverting can be reduced if XOR is implemented as the complement of XNOR.

          - -

          XNOR

          - A ⊕ B - - in the similar way xnor if implemented as complement of A ⊕ B rather than AB+A B would require 4 NMOS and PMOS.In that case B would be analougos to B in the above example,A to C and B to D. - -

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          Schematic Design Of Pass Transistor Logic & Multiplexer.

          -

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          Transmission gates are used in digital circuits to pass or block particular signal from the components. In transmission gates, NMOS and PMOS are parallel connected to each other. Schematic representation of transmission gate and its circuit symbol are shown below.

          -
          -

          -

          -

          In the transmission gates the input to the gate acts as the controlling input and depending on the value of control variable, the input at the source end of transistor appears at the drain end or in other words the control variable controls a transmission gate to which pass variables are applied. In figure shown above A is the control signal.

          - -



          - Pass transistor logic is an efficient alternative to Complementary CMOS logic design because of following reasons:

          -         1. Decreased node capacitance .

          -         2. Reduced transistor count required to implement a logic function.

          -         3. Due to the low voltage swing pass transistors require lower switching energy to charge up the node.

          -         4. Better speed .

          -         5. Low power design.

          -         6. No static power consumption .

          -


          - -

          - Applications of Transmission Gate:

          -         1. Transmission gates are typically used as building blocks for logic circuitry, such as a D Latch or D Flip-Flop.

          -         2. Transmission gates are basic building block for multiplexer.

                  3. Transmission gates can be used for blocking particular component from live signal.

          -



          - -

          Multiplexer


          - -

          Multiplexer or MUX, which is also known as data selector, is a combinational circuit with multiple input and single output. At a time a single input is selected and given as output based on select signal. -



          - -

          - A multiplexer selects binary information present on any one on the input line, depending upon logic status of the selection inputs and routes to the output line. If there are n selection line then number of possible routes input lines is 2n and then multiplexer is referred as a 2n x 1 multiplexer. -



          - -

          - Advantages of Multiplexer based on pass transistor:

          -         1. Pass transistor multiplexer uses fewer transistors as compared to fully complementary gates.

          -         2. Pass transistor is somewhat faster than complementary switch.

          -

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          - -
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          • To design positive level pass transistor logic .

            • -
          • To design a 2 input multiplexer using pass transistor logic for following logical expression :
            In1*CLK' + In2*CLK

            • -
          • To design negative level pass transistor logic

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          Schematic Design Of Pass Transistor Logic & Multiplexer.

          - - - -
          -
            -
          1. Identify which of the following can behave as pass transistors.
            -
            -
            -
            - All of the above
            -
            2. -
            - -
          2. Identify the correct statement from the following.
            - PMOS passes from source to drain when logic 1 is applied to gate.
            - NMOS passes from source to drain when logic 1 is applied to gate
            - PMOS always passes from source to drain whatever be the gate input
            - NMOS always passes from source to drain whatever be the gate input

            -
            3. -
            - -
          3. What can be designed using pass transistors?
            - Any combinational logic
            - Multiplexer
            - Both
            - None

            -
            4. -
            - -
          4. Which gate is designed in the following picture using pass transistor?

            - NOR gate
            - NAND gate
            - OR gate
            - AND gate

            -
            5. -
            -
          5. Which gate is designed in the following picture using pass transistor?

            - NOR gate
            - NAND gate
            - OR gate
            - AND gate

            -
            6. -
            - -
          6. Will n pass transistor and complementary pass transistor behave similarly for passing one?
            - No
            - Yes
            - May be in some situations
            - can not say
            -
            7. -
            - -
          7. Are the two circits shown below same?
            -
            - Yes
            - No
            - Cannot be said
            -
            8. -
            - -
          8. What is the correct expression corresponding to above circuits?
            - A+B
            - AS0 + B
            - A + BS0
            - AS0' + BS0

            -
            9. -
            - -
          9. _______ input mux can be formed using n select lines.
            - n
            - 2*n
            - 2n
            - None of the above

            -
            10. -
            - -
          10. Which gives good zero
            - Nmos Pass transistor
            - Both pmos and complementary pass transistor
            - Pmos pass transistor
            - None of the above
            -
            11. -
            - -
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            2. -
          2. "System integration:from transistor design to large scale integration" by Kurt Hoffman

            3. -
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          Schematic Design Of Pass Transistor Logic & Multiplexer.

          -

          - Pre-Quiz Questions:

          -

          - -

          - Test your Understanding Pass Transistor and Multiplexer , by going through the following quiz:
          -   

          -



          - -

          - Virtual Experiment:
          - Please make sure that you are going to perform experiment only after going through the following sections:

          - 1. Manual
          - 2. Procedure
          - 3. Objectives
          -

          - -
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          -   

          • Start the Experiment On Positive Level Pass Transistor and Multiplexer
          -

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          -   

          • Start the Experiment On Negative Level Pass Transistor
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          Schematic Design Of Pass Transistor Logic & Multiplexer.

          -

          - -

          Transmission gate is the parallel combination of NMOS and PMOS. When control signal (signal A) is high then transmission gate passes signal from input to output. NMOS passes good zero and PMOS passes good one, putting NMOS and PMOS in parallel produces a transmission gate that passes both logic levels good.



          -

          -

          PASS TRANSISTOR LOGIC THROUGH NMOS


          -

          As we already know NMOS permits flow of current from source to drain when the input to the gate is 1 therefore when control variable is equal to 1 the input at the source end appears on the drain.


          - - - - - - - - - - - - - - - - - - - - - - - - - - -
          INCONTROLOUT
          00X
          10X
          010
          111

          - -

          PASS TRANSISTOR LOGIC THROUGH PMOS


          -

          As we already know PMOS permits flow of current from source to drain when the input to the gate is 0 therefore when control variable is equal to 0 the input at the source end appears on the drain.


          - - - - - - - - - - - - - - - - - - - - - - - - - - - -
          INCONTROLOUT
          000
          101
          01X
          11X


          - - Click on the following image to see the steps in making of complementary pass transistor - -

          - -

          The above shown pass transistor will now be able to give a good one as well as good zero. At the time when S=1, both will be able to pass so whether the input signal is zero or one it will be passed almost as it is. -



          - -

          MULTIPLEXER


          - -

          The multiplexer selects one of many analog or digital input. A multiplexer with 2n input lines have n select lines. The select lines can either be 0 or 1. Depending on the binary number(formed by combination of 1s and 0s) at the select lines. One of the input is selected and it is passed on to the output.

          - - The block diagram and truth table of the 2 input multiplexer is given below: - - - -

          The logical expression for output can be AS'+BS . If we implement this logic using nands and nors then no. of transistor required would be 5.We can use the knowledge of pass transistors,control variables an pass variables.

          - -

          -



            -
          • Choice of control variable and pass variable??

            Select input should be the control variable and data inputs can act as pass variables

            • -
          • Whether to use nmos/pmos pass transistor ??

            Since nmos is preferable in passing logic 0 and pmos is preffered in passing logic 1. We use a combination of both with complementing control variables. This ensures that both are on simultaneously and any value applied at the input appears at the output
            • -
          - - - - The upper combination of nmos and pmos is switched on and hence B is passed .Similarily if select variable is 0 A is passed. -

          - - -

          - -
          -
          -
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          - -

          - Common challenges that chip designers face is that how large should be the transistors and how many stages of logic can give least delay. In other words how to optimize gate size to minimize the delay of a logic path. -


          - -

          - The method of logical effort is one of the methods used to estimate delay in a CMOS circuit. The model describes delay caused by the capacitive load that the logic gate drives and by the topology of the logic gate. As the gate increases delay also increases, but delay depends on the logic function of the gate also. -


          - -

          Delay in a Logic Circuit


          - -

          - Gate delay can be estimated from following formula.

          - D= p + h

          - Where, p is an intrinsic delay
          -                h is an effort delay

          - Effort delay is a product of logical effort and electrical effort.

          - h= g x f

          - where, g is logical effort which is a ratio of gate input’s capacitance to the inverter capacitance when sized to deliver the same current and f is an electrical effort (f= Cout/Cin) which is a function of load/gate size. Logical effort of an inverter is 1 which is shown below. -

          -
          - -

          - -

          In this experiment, it will be learnt how a delay can be reduced by changing the gate size of an inverter. The following figure shows what actually is meant by delay here


          - -

          - -

          In theory we will be proceeding further with reducing the shown delay, i.e., reducing the time between giving an input and getting the output.

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          • To study the effect of gate sizing in chain of inverters on its output delay.

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          Delay Estimation In Chain Of Inverters.

          - - -
          -
            -
          1. -Can we reduce delay to zero? -
            - Yes
            - No
            - Yes in most of the cases
            - Yes in very few cases

            -
            2. - -
          2. What you mean by delay?
            - time to correctly access the input
            - time to correctly access the output
            - average rise time and fall time
            - time taken for the output to come after the input has been captured

            -
            3. - -
          3. -The optimum size of each inverter is ________ of its neighbours
            - geometric mean
            - arithmetic mean
            - geometric or arithmetic mean
            - none of the above

            -
            4. - -
          4. -What does Cg1 corresponds to in the following formula?
            -
            - input gate capacitance of the last inverter driving capacitative load
            - sum of input capacitances of all the inverter in series
            - input gate capacitance of first inverter in series
            - None of the above

            -
            5. - -
          5. If the gate size is increased by n then what will be the effect on its resistance?
            - increases by n
            - decreases by n
            - decreases by n2
            - remains constant

            -
            6. - - -
          6. If the gate size is increased by n then what will be the effect on its capacitance?
            - increases by n2
            - increases by n
            - decreases by n
            - remains constant

            -
            7. - -
          7. -Choose the correct statement from the following.
             - All the inveters in series are kept to be of same size for minimum delay
            - The inverter size does not matter as long as the inverter driving the load has very big size
            - The inverter size does not matter as long as the inverter driving the load has very small size
            - The size of the inverter driving the load is maximum of all and is some multiple of size of the previous inverters
            -
            8. - -
          8. -For minimm delay, what is the no of inverters in the chain connected in series?
            - 4
            - 5
            - 6
            - need to calculate according to the situation given, it is not fixed.

            -
            9. - -
          9. -Let a be the stage ratio of an inverter chain. What is its optimum value to drive a load capacitor with minimum delay?
            - 4
            - 1/e
            - 2
            - e

            -
            10. - -
          10. -In the above question, if parasitic capacitances are taken into consideration then what is the optimum value of a?
            - 4
            - e
            - 1/e
            - 2

            -
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          1. "Principles of cmos vlsi design" by Weste-Eshraghian

            2. -
          2. "Logical effort: designing fast CMOS circuits" by Ivan Edward Sutherland, Robert F. Sproull, David F. Harris

            3. -
          3. "Practical low power digital VLSI design" by Gary K. Yeap

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          -Test your Understanding Gate Sizing , by going through the following quiz:
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          -Virtual Experiment:
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          Delay Estimation In Chain Of Inverters.

          -

          - -

          In this experiment, our goal is to calculate the propagation delay when some load is driven by a chain of inverters. To start with, let us consider simple case of a single inverter driving a capacitative load CL as shown in the following figure


          -

          -

          Now we want to optimize size of the inverter, x, when driven by a source resistance -Rs -and driving a load of -CL -.


          - -

          To drive CL fastly, we can make inverter size very large but then Rs will become very slow while driving such large size inverter as its input capacitance will be very large on increasing size by large amount.


          -

          If we reduce the size of an inverter and make it very small such that Rs drive it very quickly, then the delay to drive load capacitance will increase. So there is an optimal point in between these two conditions and we will see that optimal point further in this section


          -

          One thing that should be remebered is the effect of scaling of size of an inverter on its resistance and capacitance value. Suppose the size of an inverter has been scaled by a factor x, then its resistance will get reduced by the same factor while its capacitance will be increased by the same factor.


          -

          For getting optimum size of inverter, we differentiate the delay with respect to size. And when we put that value of size in the expressions of delay at the input of an inverter and delay in output, we get the same expressions. So we can summarize the optimal result for the above figure as below:


          -

          An inverter is scaled for optimium delay when the RC product of its input capacitance and the external resistance driving it, equals the RC product of its output resistance and the external load that it drives.


          -

          Now we will extend this concept for a chain of inverters as shown below


          -

          -

          -As we have seen earlier that to minimize delay, the RC product at input and output of an inverter should be same. Similar is the case with chain of inverters. Therefor the optimum size of each inverter is the geometric mean of its neighbors - meaning that if each inverter is sized up by the same factor x with respect to the preceding inverter, it will have the same effective RC product and hence the same delay. -


          -

          The following figure shows the relationship in sizes of a chain of five inverters


          -

          -

          Now we just have to see what is the value of x. The value of x derived by differentiating delay expression is nth root of CL/Cg1 where


          -     -n is equal to the number of inverters in the chain
          -     -CL is equal to the load capacitance
          -     -Cg1 is equal to the input gate capacitance of the first inverter
          -

          So expression for x is shown below


          -

          -           - -

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          D-LATCH


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          Latch is an electronic device that can be used to store one bit of information. The D latch is used to capture, or 'latch' the logic level which is present on the Data line when the clock input is high. If the data on the D line changes state while the clock pulse is high, then the output, Q, follows the input, D. When the CLK input falls to logic 0, the last state of the D input is trapped and held in the latch.

          -

          Timing diagram

          - - -

          -From the timing diagram it is clear that the output Q's waveform resembles that of input D's waveform when the clock is high whereas when the clock is low Q retains the previous value of D (the value before clock dropped down to 0)

          -
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          D FLIP FLOP


          -

          The working of D flip flop is similar to the D latch except that the output of D Flip Flop takes the state of the D input at the moment of a positive edge at the clock pin (or negative edge if the clock input is active low) and delays it by one clock cycle. That's why, it is commonly known as a delay flip flop. The D FlipFlop can be interpreted as a delay line or zero order hold. The advantage of the D flip-flop over the D-type "transparent latch" is that the signal on the D input pin is captured the moment the flip-flop is clocked, and subsequent changes on the D input will be ignored until the next clock event.


          -

          Timing diagram

          - - -

          -From the timing diagram it is clear that the output Q changes only at the positive edge.At each positive edge the output Q becomes equal to the input D at that instant and this value of Q is held untill the next positive edge

          -

          -
          -Characteristics and applications of D latch and D Flip Flop :

          -        1. D-latch is a level Triggering device while D Flip Flop is an Edge triggering device.

          -        2. The disadvantage of the D FF is its circuit size, which is about twice as large as that of a D latch. That's why, delay and power consumption in Flip flop is more as compared to D latch.

          -        3. Latches are used as temporary buffers whereas flip flops are used as registers.

          -        4. Flip flop can be considered as a basic memory cell because it stores the value on the data line with the advantage of the output being synchronized to a clock.

          -        5. Many logic synthesis tool use only D flip flop or D latch.

          -        6. FPGA contains edge triggered flip flops.

          -        7. D flip flops are also used in finite state machines.

          -
          -Edge Triggering vs. Level Clocking

          -        1. When a circuit is edge triggered the output can change only on the rrising or falling edge of the clock. But in the case of level-clocked, the output can change when the clock is high (or low).

          -        2. In edge triggering output can change only at one instant during the lock cycle; with level clocking output can change during an entire half cycle of the clock.

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          1. -What frequency clock source will produce clock waveforms having a period equal to 5 us (5 microseconds)? -
            - 5 MHz
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            - 2 MHz
            - 10 MHz

            -
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          2. On what parameters do the output of D flip flop depend?
            - independent of both previous state and input
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            - only on input D

            -
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            - positive edge triggered D flip flop
            - negative edge triggered D flip flop
            - none of them

            -
            4. -
            -
          4. -The timing diagram corresponds to
            - D latch
            - negative edge triggered flip flop
            - positive edge triggered
            - None of them

            -
            5. -
            -
          5. Which statement is false about D latch
             - the output follows the input everytime
            - the output follows the input when clock is high
            - the output follows the input when the clock is low
            - the output never follows the input

            -
            6. -
            - -
          6. Which latch has the property of either retaining or toggling the previous value
            - D-Latch
            - T-Latch
            - SR-Latch
            - None of the above

            -
            7. -
            -
          7. -Which statement below is the apt definition of flip flop
             - latch
            - coupled latch
            - de-coupled latch

            - clocked latch
            -
            8. -
            -
          8. -The above figure is the gate level implementation of:
            - SR-Latch
            - D-Latch
            - T-Latch
            - none of the above

            -
            9. -
            -
          9. - What kind of flip flop is generally preffered for constructing counters?
             - JK-flip flop
            - T flip flop
            -D flip flop
            - none of the above

            -
            10. -
            -
          10. - What is meant by the problem of metastability in flip flop
            - The data and the control input changes at the instant of clock pulse
            - The data and the control input does not change at all
            - - The clock input does not change at all
            - None of the above
            -
          -
          - - -
          - -
          - - - -
          -
          -
          - - - - - -
          - -
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          Schematic Design Of D-Latch and D-Flip Flop.

          - - -
            -
          1. "Principles of cmos vlsi design"by Weste-Eshraghian

            2. -
          2. "Digital design and computer architecture" by David Money Harris.Sarah L. Harris

            3. -
          3. "System integration:from transistor design to large scale integration" by Kurt Hoffman
            4. -
          - -
          -
          -
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          Schematic Design Of D-Latch and D-Flip Flop.

          - -

          - -Pre-Quiz Questions:

          -

          -Test your Understanding D-Latch and D-FlipFlop , by going through the following quiz:
          -  

          -



          -

          -Virtual Experiment:
          -Please make sure that you are going to perform experiment only after going through the following sections:

          -1. Manual
          -2. Procedure
          -3. Objectives
          -

          -
          -

          -   

          • Start the Positive Level D-Latch and D-FlipFlop Experiment
          -

          -
          -

          -   

          • Start the Negative Edge D-FlipFlop Experiment
          -

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          Schematic Design Of D-Latch and D-Flip Flop.

          -

          -With the definition of D latch and D flip-flop(given in the introduction) and the background knowledge of pass transistor(accquired in the fourth experiment) let us design the transistor level diagram of D latch in this experiment. -As mentioned earlier, when the clock is high the input D propogates to the output Q as it is and when the clock is low the output is held(irrespective of the changes in input D).This definition indicates that D latch can be implemented as a multiplexer with clock signal as the select input of multiplexer. Applying analogy , we realise that when clock=1 the input to the CMOS pass transistor should be D and when clock=0 the input to the pass transistor should be value of D just before the transition of clock from 1 to 0.To obtain the value of D just before transition a buffer is needed.The final design is given below: - -

          Working of the latch when clock is 1.

          - -

          When clock is 1 the pass transistor in red is on (the input to the gate of nmos is 1 and to the gate of pmos is 0) therefore the output is D as D changes the output changes accordingly.The two inverters act as a buffer.

          - -

          Working of the latch when clock is 0.

          - -

          When clock is 0 the pass transistor in red is on and the one connected to the input D is off thus any changes in D does not affect the circuit.If we observe the transistor in red is connected to the buffer at the output which loops back to its input thus the same value occurs at Q' again and again till this pass transistor is on.

          - - - -
          -
          -

          POSITIVE EDGE TRIGGERED FLIP FLOP

          - -

          From the introduction it is clear that for a positive edge triggered flip flop the changes in output occurs at the transition level.This is done by configuring two D latches in master slave configuration.A master slave D flip-flop is created by connecting two gated D latches in series, and inverting the clock input to one of them. It is called master slave because the second latch in the series only changes in response to a change in the first (master) latch. -To understand the transistor level design of positive edge triggered flip flop study the two diagrams below - -

          Positive edge triggered flip flop when clock=0

          - - - -

          -As evident from the figure when clk is 0 the input D passes through the first level of pass transistor logic and held there because the second level does not pass on the value of D

          - - -

          Positive edge triggered flip flop when clock=1

          - - -

          -When the clock input becomes 1, D(at that instant) is transferred to the output. Thereafter output Q does not change when D changes because D is not passed through the first level of pass transistor logic (as seen in the diagram). Now when the clock changes back to 1, Q still remains unaffected by the changes in D because it is now hindered by the second level of pass transistor. Thus we observe that Q remains unchanged for the entire clock cycle and changes only at the positive edge. Hence the above transistor level diagram implements positive edge triggerd flip flop.

          - - -
          -
          -

          APPLICATION AND ADVANTAGES OF D- FLIP FLOP

          -

          -D flip flop can be considered as a basic memory cell because it stores the value on the data line with the advantage of the output being synchronised to a clock. D flip flops form the basis of shift registers that are used in many electronic device. Many logic synthesis tool use only D flip flop or D latch. FPGA contains edge triggered flip flops. D flip flops are also used in finite state machines.

          - -

          -
          -
          -
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          - - - - - - - - - - - - - - - - - - + + + + + + + \ No newline at end of file From 855697bbcffa5674f026357c95498e2edf304799 Mon Sep 17 00:00:00 2001 From: mrudhvika940 Date: Thu, 14 May 2020 15:38:59 +0530 Subject: [PATCH 07/17] Updated new CSS in exp7 --- .../EXP_1sep2010/exp7/Feedback.html | 417 +++++------ .../EXP_1sep2010/exp7/Introduction.html | 463 ++++++------- .../final-build/EXP_1sep2010/exp7/Manual.html | 408 +++++------ .../EXP_1sep2010/exp7/Objective.html | 438 ++++++------ .../EXP_1sep2010/exp7/Procedure.html | 408 +++++------ .../final-build/EXP_1sep2010/exp7/Quiz.html | 594 ++++++++-------- .../EXP_1sep2010/exp7/References.html | 437 ++++++------ .../EXP_1sep2010/exp7/Simulator.html | 409 +++++------ .../final-build/EXP_1sep2010/exp7/Theory.html | 647 +++++++++--------- 9 files changed, 2158 insertions(+), 2063 deletions(-) diff --git a/src/lab/final-build/EXP_1sep2010/exp7/Feedback.html b/src/lab/final-build/EXP_1sep2010/exp7/Feedback.html index f44f0b9d..d44c17af 100755 --- a/src/lab/final-build/EXP_1sep2010/exp7/Feedback.html +++ b/src/lab/final-build/EXP_1sep2010/exp7/Feedback.html @@ -1,212 +1,235 @@ - - + + - Welcome to Virtual Labs - A MHRD Govt of india Initiative - - - - + - - - - - - - + + + + - - - - -
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          Spice Code Platform.

          -

          - - -

          In the experiments we have done till now we have designed gates by arranging transistors in various fashions .The simulation of these designs gave graphs of output voltages and we analyzed how these graph changes with varying different parameters of the transistor. Now when you place a transistor on screen there is a back end code which tells a simulator what are the points to which the transistor's substrate,gate,drain,source are connected. The language in which this information is conveyed is spice.


          -

          INTRODUCTION TO SPICE


          -

          -SPICE (Simulation Program with Integrated Circuit Emphasis) is a powerful program that is used in integrated circuit and board-level design to check the integrity of circuit designs and to predict circuit behavior. SPICE was originally developed at the Electronics Research Laboratory of the University of California, Berkeley (1975).Simulating the circuit with SPICE is the industry-standard way to verify circuit operation at the transistor level before committing to manufacturing an integrated circuit. In spice program, circuit elements (transistors, resistors, capacitors, etc) and their connections being translated into a text netlist. -


          -

          -

          -Several types of circuit analyses can be done using SPICE program. Here are the most important ones-

          -

            -
          • DC analysis: calculates the DC transfer curve.
            • -
          • Transient analysis: calculates the voltage and current as a function of time when a large signal is applied.
            • - -
          • AC Analysis: calculates the output as a function of frequency. A bode plot is generated.
            • - -
          • Noise analysis.
            • - -
          • Sensitivity analysis.
            • - -
          • Distortion analysis.
            • - -
          • Fourier analysis: calculates and plots the frequency spectrum.
            • - -
          • Monte Carlo Analysis
            • -

              - -All analyses can be done at different temperatures. The default temperature is 300K - -

              - - -

              -
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          - Click Here For Experiment Manual -

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          - - -1. To write and simulate spice codes for:

          - -       i. Simple Inverter

          - -       ii. Two input NAND gate

          - -       iii. Two input NOR gate


          - -2. To write spice code for any transistor level schematic.

          - -
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          -
          - - - - - -
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          - -

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          Pre_Quiz


          -
            -
          • What are various possible circuit analysis that can be implemented in SPICE?

            • -
          • In declarartion of MOSFET other than the essential parameters of length and breadth, what are the other parameters supported by SPICE?

            • -
          • A pulse voltage source is defined from 0 to VDD with 100ps delay, 100ps rise time, 100ps fall time, 2n pulse width, and 4ns repetition period.Write the declaration for such a source in SPICE?

            • -
          • What is the basic unit in Spice coding?
            • -

          -

          Post_Quiz


          -
          -
            -
          1. Identify the correct order in which the nodes are specified in SPICE for a mosfet
            - Gate Source Drain Bulkterminal
            - Drain Gate Source Bulkterminal
            - Bulkterinal Source Gate Drain
            - None of the above

            -
            2. - -
          2. Which of the following is not a part of the SPICE input file?
            - Data statement
            - Control statement
            - Output statement
            - Behavourial statement

            -
            3. - -
          3. What does this indicate .DC Vds 0 5 0.5 Vgs 0 5 1?
            - the voltage Vds will be swept from 0 to 5V in steps of 1V for every value of Vgs.
            - he voltage Vgs will be swept from 0 to 5V in steps of 1V for every value of Vds. ()
            - he voltage Vds will be swept from 0 to 1V in steps of 5V for every value of Vgs.
            - none of them

            -
            4. -
          4. What are the analysis done to obtain the graphs for the experiments done so far?
            - DC analysis
            - transient
            - both of them
            - None of them

            -
            5. - -
          5. Which statement is false about declaration of capacitor in SPICE
             - the positive node is followed by the negative node in declsration
            - there is no way to specify intial condition
            - both of the above
            - none of the above

            -
            6. - -
          6. Among the following which of the analysis can neither be printed nor plotted
            - .DC
            - .NOISE
            - .TRAN
            - .AC

            -
            7. - -
          7. The file extension which is not generated by spice?
             - .tr0
            - .st0
            - .ic

            - none of the above
            -
            8. - -
          8. What analysis should be performed to study variation of voltage over time?
            - .op
            - .tran

            - .dc
            - .sens

            -
            9. - -
          9. Which of the following statement is false?
            - First statement of a spice code is a comment
            - Comments in spice begin with *
            - Comments in spice begin with #
            - None of the above

            -
            10. - -
          10. What is the PC version of spice called?
            - HSPICE
            - PSPICE
            - TSPICE
            - NSPICE

            -
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          - -
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          1. The Spice Book, Andrei Vladimirescu, John Wiley & Sons, Inc.
            2. -       -
          2. http://www.brunel.ac.uk/~eestmba/usergS.html
            3.  -       -
          3. http://www.seas.upenn.edu/~jan/spice/spice.overview.html
            4.  -       -
          4. http://users.ece.utexas.edu/~adnan/vlsi-05-backup/lec7Spice.ppt
            5.  -       -
          5. A Guide to Circuit Simulation and Analysis Using PSpice, Paul Tuinenga, 3rd Edition, Prentice-Hall.
            6. -
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          -A spice input file, also called source file, consists -of three parts:
          -1. Data statements: These statements are -description of the components and their I -nterconnections.

          -2. Control statements: These statements are -responsible to tell SPICE simulator what type of -analysis to perform on the circuit.

          -3. Output statements: These statements specify -what outputs are to be printed or plotted.


          -Although these statements may appear in any order, -it is recommended that they be given in the above -sequence. Two other statements are required: the -title statement and the end statement. The title -statement is the first line and can contain any -information, while the end statement is always -.END. The title statement must be a line or word. -In addition, you can insert comment statements, -which must begin with an asterisk (*) and are -ignored by SPICE Simulator. - -



          - -

          1. Data Statements



          -(A).Independent DC Sources -

          -N1 is the positive terminal node. -N2 is the negative terminal node. -Type can be DC, AC or TRAN, depending on the -type of analysis. -Value gives the value of the source. -The name of a voltage and current source must start -with V and I, respectively.
          - -

          -The positive current direction through the current -or voltage source is from the positive (N1) node to -the negative (N2) node:

          -(B) Elements: for example MOSFETS
          - -

          -The MOS transistor name (Mname) has to start -with a M; ND, NG, NS and NB are the node -numbers of the Drain, Gate, Source and Bulk -terminals, respectively. ModName is the name of -the transistor model (NMOS or PMOS). L and W -are the length and width of the gate (in m).

          -

          2. Commands or Control Statements:



          -.TRAN Statement
          - -

          - -This statement specifies the time interval over -which the transient analysis takes place, and the -time increments. The format is as follows: -TSTEP is the printing increment. -TSTOP is the final time -TSTART is the starting time (if omitted, TSTART -is assumed to be zero) -TMAX is the maximum step size. -UIC stands for Use Initial Conditions. If UIC is -specified then simulator will use the initial -conditions specified in the element statements.

          -

          3.Output Statements



          -These statements will instruct Simulator what -
          - -

          - -output to generate. If you do not specify an output -statement, Simulator will always calculate the DC -operating points. The two types of outputs are the -prints and plots. A print is a table of data points and -a plot is a graphical representation. The format is as -follows:

          -In above format TYPE specifies the type of -analysis to be printed or plotted and can be: -
          - -

          - -The output variables are Y1, Y2 and can be voltage -or currents in voltage sources. Node voltages and -device currents can be specified as magnitude (M), -phase (P), real (R) or imaginary (I) parts by adding -the suffix to V or I as follows:


          -M: Magnitude.

          -DB: Magnitude in dB (decibels).

          -P: Phase.

          -R: Real part.

          -I: Imaginary part.

          - - -

          - -Complete example (Inverter-Netlist): - -

          -

          - -

          -In introduction of this experiment we have seen what is spice actually. In first experiment we have designed inverter, so as we have read in introduction that whenever you place anyting like transistor or capacitor etc., there is a code which is written at back end corresponding to the element placed on screen. So in this experiment we are going to learn what is taht code which is written in the back end, that is, we learn how to write that code directly, that is, we will learn basic inverter designing using spice coding. -


          -

          The following is the code for inverter in spice along with some of the explaination.



          -

          -

          Now we will be learning actually what parameters are specified by each of the element in every line in detail


          -

          FIRST LINE


          -

          First line of spice code is always a comment. So this line is always ignored by spice. Spice does not do any kind of processing on this line


          - -

          .INCLUDE LINE


          -

          .include line includes the model file but you should confirm that your model file should be in your current directory in which you are working.


          -

          LINE CORRESPONDING TO TRANSISTOR


          -           - -

          -
          -
          -
          - - - - - -
          - -
          - - -
          - - - - - - + + + + + + + - - - - - - - - - - \ No newline at end of file From 215a130210b8925822fb558b72c2d0171927592f Mon Sep 17 00:00:00 2001 From: mrudhvika940 Date: Thu, 14 May 2020 23:37:05 +0530 Subject: [PATCH 08/17] Updated new CSS in exp8 --- .../EXP_1sep2010/exp7/Objective.html | 3 +- .../EXP_1sep2010/exp8/Feedback.html | 419 ++++++------ .../EXP_1sep2010/exp8/Introduction.html | 458 +++++++------ .../final-build/EXP_1sep2010/exp8/Manual.html | 408 +++++------ .../EXP_1sep2010/exp8/Objective.html | 422 ++++++------ .../EXP_1sep2010/exp8/Procedure.html | 407 +++++------ .../final-build/EXP_1sep2010/exp8/Quiz.html | 637 +++++++++--------- .../EXP_1sep2010/exp8/References.html | 422 ++++++------ .../EXP_1sep2010/exp8/Simulator.html | 417 ++++++------ .../final-build/EXP_1sep2010/exp8/Theory.html | 541 ++++++++------- 10 files changed, 2130 insertions(+), 2004 deletions(-) diff --git a/src/lab/final-build/EXP_1sep2010/exp7/Objective.html b/src/lab/final-build/EXP_1sep2010/exp7/Objective.html index 33ec9db9..ac08366a 100755 --- a/src/lab/final-build/EXP_1sep2010/exp7/Objective.html +++ b/src/lab/final-build/EXP_1sep2010/exp7/Objective.html @@ -234,4 +234,5 @@

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          -

          - Inverter is a logic gate, with one input and one output. Its symbol is shown below:-
          -


          - The output of inverter is complement of the input i.e. if the input is 0, the output will be 1 and vice-versa . The truth table for inverter is shown below:-

          -
          - - - - - - - - - - - - - -
          InputOutput
          01
          10
          -


          - The transistor level schematic of inverter can be designed in many logics,following two logics will be used for designing in the experiment - * Complementary CMOS logic - * Pseudo NMOS logic -

          -
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          -(a) To design transistor level schematic of an Inverter using - - * Complementary CMOS logic - * Pseudo NMOS logic -
          -(b) To find the effect of load capacitance on the rise time and fall time and hence delay of output waveform. -
          - -(c) To find the effect of W/L of transistors on the output waveform. -
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          Design Of D-Flip Flop Using Verilog.

          - -

          -

          -

          Pre_Quiz


          -
            -
          • What is the relationship of input and output in T-FLip Flop?

            • -
          • What will be the output of a 4-bit down counter?

            • -
          • What is the difference between T-flip flop and D-flip flop?

            • -
          • What is the difference between asynchronous and synchronous counter?

            • -
          • Explain what do you mean by positive edge reset or negative edge clear?
            • -

          - -

          Post_Quiz


          -
          -
            -
          1. Does the order of input and output ports in the argument of module matters?
            - yes
            - no
            - may matter in some situation
            - may not matter in certain conditions

            -
            2. -
            -
            -
          2. Which of the following loops are supported by verilog?
            - if-else loop
            - for loop
            - while loop
            - all of these

            -
            3. -
            -
            -
          3. What defines the beginning and end of a loop
            - begin----end
            - curly brackets ()
            - none of these
            - both of them

            -
            4. -
            -
            -
          4. What defines high impedance state or floating state in verilog?
            - 1
            - X
            - Z
            - Both X and Z

            -
            5. -
            -
            -
          5. In the following figure A is input and B is output of inverter and C is clock. Tell whether inverter is working synchronously or asynchronously?

            - asynchronous
            - synchronous
            - unpredictable
            - sometimes synchronous and sometimes asynchronous

            -
            6. -
            -
            - -
          6. In the above figure, tell whether inverter is working on positive edge or negative edge of clock?
            -

            - negative edge
            - positive edge
            - both on positive edge and negative edge
            - middle of positive and negative edge of clock

            -
            7. -
            -
            -
          7. In the following figure tell whether reset is synchronous or asynchronous?
            -

            - asynchronous
            - synchronous
            - unpredictable
            - sometimes synchronous and sometimes asynchronous

            -
            8. -
            -
            -
          8. What is the similar system task in verilog as printf in C?
            - $monitor
            - $display

            - $print
            - all of these

            -
            9. -
            -
            -
          9. In the figure given in ques7, tell whether it is a positive edge reset or negative edge?
            - both positive and negative edge reset
            - negative edge reset
            - positive edge
            - unpredictable

            -
            10. -
            -
            -
          10. Can we include one source file in another in verilog?
            - no
            - yes using `include
            - yes using `define
            - yes by just writing the name of file in another file

            -
            11. -
            - -
          - - - -
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          Design Of D-Flip Flop Using Verilog.

          - -
            -
          • "Principles of cmos vlsi design" by Weste-Eshraghian
            • - -
          • CMOS: Circuit Design, Layout, and Simulation, Third Edition by Bacor, R. Jacob. Wiley-IEEE. pp. 1174. Chen, Wai-Kai (ed) (2006).
            • -
          • The VLSI Handbook, Second Edition (Electrical Engineering Handbook) by Boca Raton: CRC. ISBN 0-8493-4199-X.
            • -
          • http://jas.eng.buffalo.edu/education/fab/NMOS/nmos.html
            • -
          -


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          Design Of D-Flip Flop Using Verilog.

          - -Download GTKWAVE Tool to view .vcd file generated by below given experiment.


          -Experiment On Positive Edge D FlipFlop

          - Experiment On Negative Edge D FlipFlop - -
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          -

          - CMOS INVERTER -
          - In the transistor level design of CMOS inverter consists of nmos and pmos transistor in series.The PMOS transistor is connected between Vdd and output node,whereas the NMOS is connected betweeen the output node and gnd. -

          - WORKING OF CMOS INVERTER -
          - Before knowing the working of CMOS inverter we will see the regions of operation of transistor so that we can understand what is actually happening inside the inverter. MOS transistors have three regions of operations : - 1) cut-off region - 2) linear region - 3) saturation region -

          - The transistor is said to be in cut-off region when Vgs < Vt. Vgs is the voltage applied at gate with respect to source and Vt is the threshhold voltage below which the transistor does not work. So for transistor to work Vgs - Vt should be greater than zero always. -

          - The transistor is in linear region when Vgs - Vt > Vds where Vds is the voltage at drain with respect to source. -
          - The transistor is said to be in saturation region when vgs - Vt < Vds -

          - The transfer characteristic(i.e. the output voltage vs input voltage) is shown in the figure below. The operation is divided into 5 region depending on the range of input voltage(Move your mouse over the region to know about the region).The output voltage in every region is obtained by equating drain to source current of pmos and nmos. -

          -

          -

          - EFFECT OF W/L RATIO ON OUTPUT WAVEFORM -

          - Before proceeding to the study of effect please read the definition of β (gain factor). -

          - W/L ratio is directly proportional to β.The ratio βn/βp is crucial in determinig the transfer characteristic of the inverter.When the ratio is increased the transition shifts from left to right,but the output voltage transition remains sharp.For CMOS the ratio is desired to be 1 so that it requires equal time to charge and discharge. -

          - EFFECT OF CAPACITANCE ON THE RISE AND FALL TIME - The rise time is defined as the time required to charge the capacitor from 10% to 90% and fall time is defined as the time required for the capacitor to discharge from 90% to 10%. How the rise time and the fall time is calculated is shown in the figure below : -

          - Greater value of capacitor implies larger rise and fall time,which furthur implies large delay. The rise time and fall time are directly proportional to the capacitance, therefore, greater the value of capacitance, greater will be the time taken for rising and falling. -

          - PSEUDO NMOS -

          - The gate of p-device is permanently grounded which is equivalent to use of NMOS in depletion mode -

          -
          - SOME BASIC DEFINITIONS AND THEORY -
          -

          - TRANSISTOR -

          - Basically transistor consistes of three parts - GATE, SOURCE and DRAIN as shown in figure below: -

          - The gate is a control input which determines the flow of electric current between source and drain. Physically drain and source are equivalent and the two types of transistor i.e. n-transistor and p-transistor differ only in the way electric current flows between source and drain according to the different values applied at the controlling gate input. In n-transistor when logic 1 is aplied to gate, the current flows bwetween source and drain while no current flows when logic 0 is applied. The p-transistor works just the opposite way - the current flows between source and drain when logic 0 is applied and no current on logic 1. -

          - β - GAIN FACTOR -

          - β is the MOS transistor gain factor which depends both on process parameters and geometry parameters. -

          -
          - 
              		    β = k(W/L)
+    	
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          Design Of D-Flip Flop Using Verilog
          
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+                
          
+                  CMOS INVERTER
+                  
          
+                  In the transistor level design of CMOS
+                  inverter consists of nmos and pmos
+                  transistor in series. The PMOS transistor
+                  is connected between Vdd and output node, whereas the NMOS is connected betweeen the output node and gnd.
+                  

          
+                  WORKING OF CMOS INVERTER
+                  
          
+                  Before knowing the working of CMOS inverter we will see the regions of operation of transistor so that we can understand what is actually happening inside the inverter. MOS transistors have three regions of operations :
+                  1) cut-off region
+                  2) linear region
+                  3) saturation region 
+                  

          
+                  The transistor is said to be in cut-off region when Vgs < Vt. Vgs is the voltage applied at gate with respect to source and Vt is the threshhold voltage below which the transistor does not work. So for transistor to work Vgs - Vt should be greater than zero always.
+                  

          
+                  The transistor is in linear region when Vgs - Vt > Vds where Vds is the voltage at drain with respect to source.
+                  
          
+                  The transistor is said to be in saturation region when vgs - Vt < Vds
+                  

          
+                  The transfer characteristic(i.e. the output voltage vs
+                  input voltage) is shown in the figure below. The
+                  operation is divided into 5 region depending on the
+                  range of input voltage(Move your mouse over the
+                  region to know about the region). The output voltage in every region is obtained by equating drain to source current of pmos and nmos.
+                  

          
+                
          
+                
          
+                

          
+                EFFECT OF W/L RATIO ON OUTPUT WAVEFORM
+                

          
+                Before proceeding to the study of effect please read the definition of β (gain factor).
+                

          
+                W/L ratio is directly proportional to β. The ratio βn/βp
+                is crucial in determinig the transfer characteristic of
+                the inverter. When the ratio is increased the transition
+                shifts from left to right, but the output voltage
+                transition remains sharp. For CMOS the ratio is desired to be 1 so that it requires equal time to charge and discharge.
+                

          
+                EFFECT OF CAPACITANCE ON THE RISE AND FALL TIME
+                The rise time is defined as the time required to charge the capacitor from 10% to 90% and fall time is defined as the time required for the capacitor to discharge from 90% to 10%. How the rise time and the fall time is calculated is shown in the figure below :
+                

          
+                Greater value of capacitor implies larger
+                rise and fall time, which furthur implies large delay. The rise time and fall time are directly proportional to the capacitance. Therefore, greater the value of capacitance, greater will be the time taken for rising and falling.
+                

          
+                PSEUDO NMOS
+                

          
+                The gate of p-device is permanently grounded which is equivalent to use of NMOS in depletion mode
+                

          
+                
          
+                SOME BASIC DEFINITIONS AND THEORY
+                
          
+                

          
+                TRANSISTOR
+                

          
+                Basically transistor consistes of three parts - GATE, SOURCE and DRAIN as shown in figure below:
+                

          
+                The gate is a control input which determines the flow of electric current between source and drain. Physically drain and source are equivalent and the two types of transistor i.e., n-transistor and p-transistor differ only in the way electric current flows between source and drain according to the different values applied at the controlling gate input. In n-transistor when logic 1 is aplied to gate, the current flows bwetween source and drain while no current flows when logic 0 is applied. The p-transistor works just the opposite way - the current flows between source and drain when logic 0 is applied and no current on logic 1.
+                

          
+                β - GAIN FACTOR
+                

          
+                β is the MOS transistor gain factor which depends both on process parameters and geometry parameters.
+                

          
+                
          
+                  
              		    β = k(W/L)
     		where K is the factor which shows process dependencyand W & L shows geometry dependency
     		    For NMOS, gain factor is denoted by βn and for PMOS, gain factor is denoted by βp.
     	
          
-    
          
-    

          
-    DELAY
-    

          
-    Delay time is the time taken for the input transistion (50% level) into output (50% level). The single gate delay is given by the average of rise time and fall time, so delay also is directly proportional to the capacitance value
-    

          
-    DEPLETION MODE
-    

          
-    Using NMOS in depletion region means increasing negative voltage on the gate to reduce current flow or we can say to deplete the channel of free carriers which are electrons in n-channel.
-
          
-
          						
          
-					
          
-			
          
-			
-
-
-
-			
-	
           
-		
-
          +

          + DELAY +

          + Delay time is the time taken for the input transistion (50% level) into output (50% level). The single gate delay is given by the average of rise time and fall time, so delay also is directly proportional to the capacitance value +

          + DEPLETION MODE +

          + Using NMOS in depletion region means increasing negative voltage on the gate to reduce current flow or we can say to deplete the channel of free carriers which are electrons in n-channel. +

          +
          +
          +
          +
          +
          + +
          -
          -
          - - - -
          - - - + + + + + + + - - - - - - - - - - - - - \ No newline at end of file + From 9249926d7ac42b6d7d1e3e0a6c5554edcf6a8f86 Mon Sep 17 00:00:00 2001 From: mrudhvika940 Date: Fri, 15 May 2020 12:54:04 +0530 Subject: [PATCH 09/17] Updated new CSS in exp9 --- .../final-build/EXP_1sep2010/exp8/Theory.html | 3 +- .../EXP_1sep2010/exp9/Feedback.html | 423 +++++------ .../EXP_1sep2010/exp9/Introduction.html | 419 +++++------ .../final-build/EXP_1sep2010/exp9/Manual.html | 408 +++++------ .../EXP_1sep2010/exp9/Objective.html | 423 +++++------ .../EXP_1sep2010/exp9/Procedure.html | 404 +++++------ .../final-build/EXP_1sep2010/exp9/Quiz.html | 671 +++++++++--------- .../EXP_1sep2010/exp9/References.html | 418 +++++------ .../EXP_1sep2010/exp9/Simulator.html | 413 +++++------ .../final-build/EXP_1sep2010/exp9/Theory.html | 625 ++++++++-------- 10 files changed, 2166 insertions(+), 2041 deletions(-) diff --git a/src/lab/final-build/EXP_1sep2010/exp8/Theory.html b/src/lab/final-build/EXP_1sep2010/exp8/Theory.html index ef3555c5..04d0442e 100755 --- a/src/lab/final-build/EXP_1sep2010/exp8/Theory.html +++ b/src/lab/final-build/EXP_1sep2010/exp8/Theory.html @@ -297,4 +297,5 @@

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          Verilog is language commonly used in designing digital systems. It is a hardware description language, which means that it is substantially different from any other language you might have encountered so far. Even though it does have control flow statements and variables, it relies primarily on logic functions.It is a textual format for describing electronic circuits and systems.


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          Verilog has evolved as a standard hardware description language. Verilog offers many useful features for hardware design. it is easy to learn and easy to use as it is similar to C Programming language. Designers with C Programming experience will find it easy to learn Verilog.

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          -

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          Pre_Quiz


          -
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          • How is verilog different from software programming language?

            • -
          • Explain what do you mean by positive edge reset or negative edge clear?
            • -
          -
          -

          Post_Quiz


          -
          -
            -
          1. Which is correct assignment for two input and gate shown in Fig.1?
            -

            -     Wire Y; assign Y = A x B ;
            -     Wire Y; assign Y = A & B ;
            -     Wire Y; assign Y = A and B ;
            -     Wire Y; assign A & B = Y ;

            -
            2. - -
          2. Which is correct assignment for try state buffer shown in Fig.2?
            -

            -     Tri Y ; assign Y = (ENB) : A : Z ;
            -     Y = (ENB) ? A : Z ;
            -     Tri Y ; assign Y = (ENB) ? A : Z ;
            -     Tri Y ; Y = (ENB) ? A : Z ;

            -
            3. - -
          3. Which is not a logical operator ?
            -      |     logical OR
            -     ||     logical OR
            -     &&     logical AND
            -     !    logical NOT

            -
            4. - -
          4. Which is/are bitwise operator ?
            -     A) &
            -     B) ~
            -     C) |
            -     D) ~^

            - -     Only A.
            -     A and B.
            -     A, B and C.
            -     All Of These.

            -
            5. - -
          5. Which is not a correct statement?

            - -    (A) >> is a shift right operator.
            - -    (B) & is a reduction operator
            - -    (C) === is a case equality operator
            - -    (D) Y = (sel) ? A : B; is an example of conditional operator

            - -     A
            -     None
            -     All Of These.
            -     A, B and C.

            -
            6. - -
          6. Which is/are correct verilog code for Fig.3?

            -

            -     Only A.
            -     Only B.
            -     C and D.
            -     A and B.

            -
            7. - -
          7. Which is correct verilog code for Fig.4?
            -

            -


            -     Only A.
            -     Only B.
            -     Only C.
            -     A and D.

            -
            8. - -
          8. Which is not a correct port assignment for a module?
            -


            -     (i)
            -     (ii)
            -     (iii)
            -     (iv)

            -
            9. - -
          9. Which is/are not correct escaped characters?
            -    (A)   \n for new line
            -    (B)   \t for new tab
            -    (C)   %% for %
            -    (D)   \ for \
            -    (E)   \" for "
            -    (F)   \s for string

            -     A and B.
            -     C and D.
            -     Only E.
            -     Only F.

            -
            10. - -
          10. Which is/are showing incorrect result for given operands and operator ?
            -    (i) 1 > 0 -> 1
            -         'b1 x 1 <= 0 -> x
            -         10 < z -> x

            -    (ii) 4'b 1z0x == 4'b 1z0x -> x
            -         4'b 1z0x != 4'b 1z0x -> x

            -    (iii) One multi-bit operand -> One single-bit result
            -         a = 4'b1001;
            -         c = |a; // c = 1|0|0|1 = 1

            -    (iv) 4'b 1z0x === 4'b 1z0x -> 1
            -         4'b 1z0x !== 4'b 1z0x -> 0

            -
            -     (i), (ii) and (iii).
            -     Only (i).
            -     All of these
            -     None

            -
            11. - -
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          -       -2. "Verilog Tutorial" by Deepak Kumar Tala
          -       -3. "Verilog tutorial based on Weste and Harris" edited by Lukasz Strozek
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          Design Of Digital Circuits Using Verilog.

          -

          - -

          As we have seen in introduction what verilog is all about, why verilog was developed, what is its need, what is the advantages using verilog, now we are ready to make some digital designs using verilog. We will learn three basic designs which are listed below in this experiment.


          -
            -
          1. T-Flip Flop

            2. -
          2. Counter

            3. -
          3. T-Flip Flop usind D-Flip Flop
            4.  -

          - -

          T-FLIP FLOP


          - The verilog code for T-flip flop is given below with explaination of different parts of code.

          - -

          - -

          Some of the following points which are not explained in detail in the above image are explained here below


          -

          MODULE


          -

          Verilog provides the concept of a module. A module is the basic building block in verilog. A module can be an element or a collection of lower-level design blocks. Typically, elements are grouped int mmodules to provide common functonality that is used at many places in the design. A module provides the necessary functionality to the higher-level block through its port interface (inputs and outputs), but hides the internal implementation. This allows the designer to modify module internals without affecting the rest of the design.


          - -

          MODULE NAME


          - -

          Module name can be anything accordig to our own choice. It is just another name consisting of characters and numbers. It is used when module is instantiated in another module. We instantiate by calling the module using the name given to it. Instiating the module is explained in the third example code given below.


          - -

          ARGUMENTS IN MODULE


          - -

          Just as in C function we give some arguments to function, here also we give arguments which consists of all the input and output ports which that module is using to take input fromthe user and give output to the user.


          - -

          INPUT-OUTPUT PORTS - I/O PORTS


          - -

          Input and Output ports are the ports through user can give inputs and take outputs. Whatever arguments we have given to module should be mentioned inside the module that which arguments correspond to input ports and which correspond to output ports as done in the image above.


          - -

          DATA TYPES


          - -

          Here in this example we have used reg data type and in upcoming examples we will be using some more as wire and all. So to know about various kinds of operators in verilog just read the following chart carefully.


          - -
          -
          -

          ALWAYS BLOCK


          -

          All statements inside an always statement consists of always block. The always statement starts at time 0 and executes the always statement in the looping fashion continuously according to the condition given in the bracket of always block after "@".


          - -

          POSEDGE CLOCK


          - -

          Posedge clock is written in the bracket of always statement means that the statements inside the always block will be executed only at the positive edge of the clock, that is, only when clock goes from low level to high level or generally 0V level to 5V level.


          - -

          NEGEDGE RESET


          - -

          Reset is also a pulse here when the negative edge of reset is encountered then asynchronously that means irrespective of the clock the output will be set to zero. Negative edge means reset will go from high level to low level.


          - -

          OPERATORS AND OTHER LEXICAL CONVENTIONS


          - -

          ~ and ! opertars are used in the above code. Apart from these there are various operators, numbers and identifiers provided by verilog. All of these are shown in figure below


          - -

          - -

          LOOPS


          - -

          Verilog also supports for, if-else, while loops as in C. In the above example if and else are used. The syntax for all loops is same as C just the difference is that they have a begin and end to denote the statements inside a loop. -


          - -

          BLOCKING AND NON-BLOCKING ASSIGNMENT


          - -

          Blocking statement is specified by = operator and Non-Blocking statement is specified by <= operator. Suppose there are two statements
          -      -     a = b
          -      -     b = a
          - Then both a and b will get values equal to b but if in place of equal to sign we place less than equal to operator, that is, if we use non blocking assignment then bith statement will be executed at same time, that is a will get the value of b and b will get the value of a at the same time so the values will be swapped. Hence statements with non-blocking assignment is started executing simultaneously.


          -
          -
          - -

          COUNTER


          - The verilog code for counter is given below with explaination of different parts of code.
          -

          -

          In tha above code, everything is pretty much explained in the box on right hand side given above. Just the assign statement is new so it is explained here. When we use assign before a statement like in above example Q=tmp, it means Q will be updated as soon as the value in tmp register changes whether or not it comes in the execution sequence or not. This is the speciality of assign keyword.


          -
          -
          -

          T_FLIP FLOP USING D-FLIP FLOP


          -

          The verilog code for the T-flip flop using D-flip flop is given below with explaination of different parts of code.



          -

          -

          In the above example instantiation of module is used which is explained in detail here.


          -

          INSTANTIATION OF MODULE


          -

          We does not use module inside a module, thats why we instantiate it that means we call it as we call some function. One important thing to not while instantiating is that we call module with same name as we have given it while coding for it separately but when we are using it in other module we give it some other name and if it is instantiated more than one time then we have to give different name each time. Here in above example we have called the module with same name D_FF but given a new name dff0.


          - -

          NOT - VERILOG PROVIDED PRIMITIVE


          -

          There are many primitives already defined in verilog which provides some particular functionalities. not is one of them. In not first argument is output value and second is input value. So in above example d is output and q is input.




          -

          Verilog also provides us with some compiler directives and system tasks. These are not used in above programs but if you want to know about these functionalities, read the following flowcharts.


          -


          -


          - -

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          - - - - - -
          - -
          - - -
          - - - - - - - - - - - - - - - - - - - - \ No newline at end of file + + < + + + + + + \ No newline at end of file From 71b62a4977b727e726a673fec007674519ceff6d Mon Sep 17 00:00:00 2001 From: mrudhvika940 Date: Fri, 15 May 2020 16:06:40 +0530 Subject: [PATCH 10/17] Updated new CSS in exp10 and other fixes --- .../EXP_1sep2010/exp1/Objective.html | 7 +- .../EXP_1sep2010/exp2/Simulator.html | 2 +- .../EXP_1sep2010/exp3/Simulator.html | 5 +- .../EXP_1sep2010/exp4/Objective.html | 5 +- .../EXP_1sep2010/exp5/Objective.html | 5 +- .../EXP_1sep2010/exp6/Objective.html | 5 +- .../EXP_1sep2010/exp6/Simulator.html | 7 +- .../EXP_1sep2010/exp7/Objective.html | 3 +- .../EXP_1sep2010/exp7/Procedure.html | 3 +- .../EXP_1sep2010/exp7/References.html | 13 +- .../EXP_1sep2010/exp8/Objective.html | 8 +- .../EXP_1sep2010/exp9/Feedback.html | 3 +- .../EXP_1sep2010/exp9/Objective.html | 8 +- .../EXP_1sep2010/layout/Feedback.html | 424 +++++++------ .../EXP_1sep2010/layout/Introduction.html | 420 ++++++------- .../EXP_1sep2010/layout/Manual.html | 408 ++++++------ .../EXP_1sep2010/layout/Objective.html | 418 +++++++------ .../EXP_1sep2010/layout/Procedure.html | 452 +++++++------- .../final-build/EXP_1sep2010/layout/Quiz.html | 586 +++++++++--------- .../EXP_1sep2010/layout/References.html | 422 ++++++------- .../EXP_1sep2010/layout/Simulator.html | 446 ++++++------- .../EXP_1sep2010/layout/Theory.html | 527 ++++++++-------- 22 files changed, 2138 insertions(+), 2039 deletions(-) diff --git a/src/lab/final-build/EXP_1sep2010/exp1/Objective.html b/src/lab/final-build/EXP_1sep2010/exp1/Objective.html index dd3f6906..350f1d89 100755 --- a/src/lab/final-build/EXP_1sep2010/exp1/Objective.html +++ b/src/lab/final-build/EXP_1sep2010/exp1/Objective.html @@ -124,9 +124,9 @@

          Schematic Design Of Transistor Level Inverter.

          Complementary CMOS logic
        • Pseudo NMOS logic
          • - -
        • To find the effect of load capacitance on the rise time and fall time and hence delay of output waveform.
          • -
        • To find the effect of W/L of transistors on the output waveform.
          • +
          +
        • To find the effect of load capacitance on the rise time and fall time and hence delay of output waveform.

          • +
        • To find the effect of W/L of transistors on the output waveform.

          • @@ -231,4 +231,5 @@

          Follow Us

          + \ No newline at end of file diff --git a/src/lab/final-build/EXP_1sep2010/exp2/Simulator.html b/src/lab/final-build/EXP_1sep2010/exp2/Simulator.html index 87cbc238..ed63f163 100755 --- a/src/lab/final-build/EXP_1sep2010/exp2/Simulator.html +++ b/src/lab/final-build/EXP_1sep2010/exp2/Simulator.html @@ -116,7 +116,6 @@

          Schematic Design Of Transistor Level NAND & N

          Make sure that you have prerequisites installed to run experiment


          -

          Click here for the experiment

          @@ -223,4 +222,5 @@

          Follow Us

          + \ No newline at end of file diff --git a/src/lab/final-build/EXP_1sep2010/exp3/Simulator.html b/src/lab/final-build/EXP_1sep2010/exp3/Simulator.html index e6f60ddb..1547855a 100755 --- a/src/lab/final-build/EXP_1sep2010/exp3/Simulator.html +++ b/src/lab/final-build/EXP_1sep2010/exp3/Simulator.html @@ -113,9 +113,9 @@

          Feedback

          Schematic Design Of Transistor Level XOR & XNOR Gate

          -

          Make sure that you have prerequisites installed to run experiment +

          Make sure that you have prerequisites installed to run experiment


          -

          Click here for the experiment

          +

          Click here for the experiment

          @@ -218,4 +218,5 @@

          Follow Us

          + \ No newline at end of file diff --git a/src/lab/final-build/EXP_1sep2010/exp4/Objective.html b/src/lab/final-build/EXP_1sep2010/exp4/Objective.html index 6a8060b7..c3d1c286 100755 --- a/src/lab/final-build/EXP_1sep2010/exp4/Objective.html +++ b/src/lab/final-build/EXP_1sep2010/exp4/Objective.html @@ -114,7 +114,7 @@

          Feedback

          Schematic Design Of Pass Transistor Logic & Multiplexer

          -
            +
            1. To design positive level pass transistor logic

            2. To design a 2 input multiplexer using pass transistor logic for following logical expression : In1*CLK' + In2*CLK
              3. @@ -122,7 +122,7 @@

              Schematic Design Of Pass Transistor Logic & Mu
            3. To design negative level pass transistor logic


              4. -

          +
          @@ -226,4 +226,5 @@

          Follow Us

          + \ No newline at end of file diff --git a/src/lab/final-build/EXP_1sep2010/exp5/Objective.html b/src/lab/final-build/EXP_1sep2010/exp5/Objective.html index 2d833db1..435bfd04 100755 --- a/src/lab/final-build/EXP_1sep2010/exp5/Objective.html +++ b/src/lab/final-build/EXP_1sep2010/exp5/Objective.html @@ -114,10 +114,10 @@

          Feedback

          Delay Estimation In Chain Of Inverters

          -
            +
            1. To study the effect of gate sizing in chain of inverters on its output delay.

              2. -
          +
          @@ -220,4 +220,5 @@

          Follow Us

          + \ No newline at end of file diff --git a/src/lab/final-build/EXP_1sep2010/exp6/Objective.html b/src/lab/final-build/EXP_1sep2010/exp6/Objective.html index eae3a2ce..8ced3176 100755 --- a/src/lab/final-build/EXP_1sep2010/exp6/Objective.html +++ b/src/lab/final-build/EXP_1sep2010/exp6/Objective.html @@ -114,11 +114,11 @@

          Feedback

          Schematic Design Of D-Latch and D-Flip Flop

          -
            +
            1. To design D latch using pass transistor logic.

            2. To design Positive Edge Trigger D-flip flop.

            3. To design Negative Egde Trigger D-flip flop.

              4. -
          +
          @@ -223,4 +223,5 @@

          Follow Us

          + \ No newline at end of file diff --git a/src/lab/final-build/EXP_1sep2010/exp6/Simulator.html b/src/lab/final-build/EXP_1sep2010/exp6/Simulator.html index 0067c3f4..2ac10807 100755 --- a/src/lab/final-build/EXP_1sep2010/exp6/Simulator.html +++ b/src/lab/final-build/EXP_1sep2010/exp6/Simulator.html @@ -112,7 +112,9 @@

          Feedback

          Schematic Design Of D-Latch and D-Flip Flop

          -

          +

          Make sure that you have prerequisites installed to run experiment

          +
          +

          Virtual Experiment:
          Please make sure that you are going to perform experiment only after going through the following sections:

          1. Manual
          @@ -140,7 +142,7 @@

          Schematic Design Of D-Latch and D-Flip Flop

          • Start the Negative Edge D-FlipFlop Experiment
            • -
          +

          \ No newline at end of file diff --git a/src/lab/final-build/EXP_1sep2010/exp7/Objective.html b/src/lab/final-build/EXP_1sep2010/exp7/Objective.html index ac08366a..922b1391 100755 --- a/src/lab/final-build/EXP_1sep2010/exp7/Objective.html +++ b/src/lab/final-build/EXP_1sep2010/exp7/Objective.html @@ -119,7 +119,7 @@

          Spice Code Platform

          • To write and simulate spice codes for:

            • -
              +
              1. Simple Inverter

              2. Two input NAND gate
                3. @@ -235,4 +235,5 @@

                Follow Us

                + \ No newline at end of file diff --git a/src/lab/final-build/EXP_1sep2010/exp7/Procedure.html b/src/lab/final-build/EXP_1sep2010/exp7/Procedure.html index 34ad2c7d..df4a934e 100755 --- a/src/lab/final-build/EXP_1sep2010/exp7/Procedure.html +++ b/src/lab/final-build/EXP_1sep2010/exp7/Procedure.html @@ -113,7 +113,7 @@

                Feedback

          -

          Spice Code Platformx

          +

          Spice Code Platform

          Spice Code Design


          @@ -220,4 +220,5 @@

          Follow Us

          + \ No newline at end of file diff --git a/src/lab/final-build/EXP_1sep2010/exp7/References.html b/src/lab/final-build/EXP_1sep2010/exp7/References.html index 41972309..ee3910a0 100755 --- a/src/lab/final-build/EXP_1sep2010/exp7/References.html +++ b/src/lab/final-build/EXP_1sep2010/exp7/References.html @@ -105,7 +105,7 @@

          Simulation

          Quizzes

          -

          References

          +

          References

          Feedback

          @@ -118,21 +118,21 @@

          Spice Code Platform

            -
          1. The Spice Book, Andrei Vladimirescu, John Wiley & Sons, Inc.
            2. +
          2. The Spice Book, Andrei Vladimirescu, John Wiley & Sons, Inc.

            3.  -
          3. http://www.brunel.ac.uk/~eestmba/usergS.html
            4. +
          4. http://www.brunel.ac.uk/~eestmba/usergS.html

            5.  -
          5. http://www.seas.upenn.edu/~jan/spice/spice.overview.html
            6. +
          6. http://www.seas.upenn.edu/~jan/spice/spice.overview.html

            7.  -
          7. http://users.ece.utexas.edu/~adnan/vlsi-05-backup/lec7Spice.ppt
            8. +
          8. http://users.ece.utexas.edu/~adnan/vlsi-05-backup/lec7Spice.ppt

            9.  -
          9. A Guide to Circuit Simulation and Analysis Using PSpice, Paul Tuinenga, 3rd Edition, Prentice-Hall.
            10. +
          10. A Guide to Circuit Simulation and Analysis Using PSpice, Paul Tuinenga, 3rd Edition, Prentice-Hall.

          @@ -236,4 +236,5 @@

          Follow Us

          + \ No newline at end of file diff --git a/src/lab/final-build/EXP_1sep2010/exp8/Objective.html b/src/lab/final-build/EXP_1sep2010/exp8/Objective.html index 594b85c8..e3a483f2 100755 --- a/src/lab/final-build/EXP_1sep2010/exp8/Objective.html +++ b/src/lab/final-build/EXP_1sep2010/exp8/Objective.html @@ -115,9 +115,8 @@

          Feedback

          Design Of D-Flip Flop Using Verilog

          -
            -
          • To design transistor level schematic - of an Inverter using :
            • +
              +
            1. To design transistor level schematic of an Inverter using :
              1. Complementary CMOS logic
              2. Pseudo NMOS logic
                3. @@ -127,7 +126,7 @@

                Design Of D-Flip Flop Using Verilog


              3. To find the effect of W/L of transistors on the output waveform. -
          +
          @@ -231,4 +230,5 @@

          Follow Us

          + \ No newline at end of file diff --git a/src/lab/final-build/EXP_1sep2010/exp9/Feedback.html b/src/lab/final-build/EXP_1sep2010/exp9/Feedback.html index 9d88661e..d70ddbcb 100755 --- a/src/lab/final-build/EXP_1sep2010/exp9/Feedback.html +++ b/src/lab/final-build/EXP_1sep2010/exp9/Feedback.html @@ -232,4 +232,5 @@

          Follow Us

          - + + \ No newline at end of file diff --git a/src/lab/final-build/EXP_1sep2010/exp9/Objective.html b/src/lab/final-build/EXP_1sep2010/exp9/Objective.html index 18e1c2c5..16df25ff 100755 --- a/src/lab/final-build/EXP_1sep2010/exp9/Objective.html +++ b/src/lab/final-build/EXP_1sep2010/exp9/Objective.html @@ -116,9 +116,9 @@

          Feedback

          Design Of Digital Circuits Using Verilog

          -
            +
            1. To learn the basic concepts of verilog - programming

              + programming
            2. To design multiplexers, counters etc. using verilog coding.
              @@ -227,4 +227,6 @@

              Follow Us

              - + + + \ No newline at end of file diff --git a/src/lab/final-build/EXP_1sep2010/layout/Feedback.html b/src/lab/final-build/EXP_1sep2010/layout/Feedback.html index 3cc1ef23..4112cf20 100755 --- a/src/lab/final-build/EXP_1sep2010/layout/Feedback.html +++ b/src/lab/final-build/EXP_1sep2010/layout/Feedback.html @@ -1,212 +1,238 @@ - - + + - Welcome to Virtual Labs - A MHRD Govt of india Initiative - - - - + - - - - - - - + + + + - - - - -
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          \ No newline at end of file diff --git a/src/lab/final-build/EXP_1sep2010/layout/Introduction.html b/src/lab/final-build/EXP_1sep2010/layout/Introduction.html index af16adff..217c279f 100755 --- a/src/lab/final-build/EXP_1sep2010/layout/Introduction.html +++ b/src/lab/final-build/EXP_1sep2010/layout/Introduction.html @@ -1,223 +1,227 @@ - - + + - Welcome to Virtual Labs - A MHRD Govt of india Initiative - - - - + - - - - - - - + + + + - - - - -
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          - -
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          Layout Design.

          -

          - - - -In this experiment, layout design platform feature is included with layout design rule check (DRC). -

          - - -

          -
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          - Click Here For Experiment Manual -

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          Layout Design.

          - - -

          -(a) To design transistor level physical layout of different circuits.

          -(b) To check design rule violations present in layout design.
          -

          - - -
          -
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          - - - - - -
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          - -
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          Layout Design

          - - -

          1.Select and placing layers :


          -
            -
          • Select a layer from available icons on the left panel.The layer selected appears on the top left box.

            • -
          • Place the selected layer in the central grid.

            • -
          • Stretch the selected layer by using mouse left click and follow the pixels on grid.

            • -
          • Click on "freeze component size" button to fix the size of layer. - Note: Once freezing the layer size, this will not change in future.

            • -
          • Move this layer and place it.



            • -
          - -

          2.Layout completion and DRC check



          -
            -
          • Place all required layers and check DRC rule every time while placing layers.

            • -
          • Place wrong created layers outside the grid. - Note: There is no delete option.

            • -
          • Check DRC after completion of your layout design.

            • - -
          -
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          - - - - - - + + + + + + + - - - - - - - - - - \ No newline at end of file diff --git a/src/lab/final-build/EXP_1sep2010/layout/Quiz.html b/src/lab/final-build/EXP_1sep2010/layout/Quiz.html index 3057c0aa..3d9d5201 100755 --- a/src/lab/final-build/EXP_1sep2010/layout/Quiz.html +++ b/src/lab/final-build/EXP_1sep2010/layout/Quiz.html @@ -1,308 +1,310 @@ - - - + + - Welcome to Virtual Labs - A MHRD Govt of india Initiative - - - - + - - - - - - - + + + + - - - - - - - - -
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          - -
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          Layout Design.

          - -
          -
            -
          1. -What is the minimum width, minimum spacing rule of same potential and different potential Well ? -
            - 10,9 and 10,6.
            - 10,6 and 10,9.
            - 10,10 and 9,6.
            - 10,9 and 10,9.

            -
            2. -
            -
          2. Transistor gate form when two layers overlap. These two layers are -
            - Polysilicon and Select.
            - Polysilicon and Contact.
            - Polysilicon and Metal.
            - Polysilicon and Active.

            -
            3. -
            -
          3. How many physical layers are used in below given inverter layout design, excluding wells:
            -

            - 6.
            - 7.
            - 5.
            - 8.

            -
            4. -
            -
          4. The layout design rules are usually described by -
            - Separation rule.
            - Distance Rule.
            - Micron rule and Design Rule.
            - Micron Rule.

            -
            5. -
            -
          5. Lambda is known as -
             - sepaparation of layers.
            - minimum feature size.
            - distance of pixel.
            - all of these.

            -
            6. -
            - -
          6. The Length and width of a transistor are two most important dimensions of transistors that depend on -
            - drain dimentions.
            - gate dimention.
            - bulk dimention.
            - source dimention.

            -
            7. -
            -
          7. - - Which of these are wrong option regarding design rule -
            -a. Width rule
            b. space rule
            c. Overlap rule
            d. pixel rule.

            - a, b, c, and d.
            - b and d.
            - a and b.
            - a, b, and c.

            -
            8. -
            -
          8. - Minimum spacing rule of metal layer is -
            - 3 mm.
            - 3 lamada.
            - 6 lamada.
            - 10 lamada.

            -
            9. -
            -
          9. - DRC means -
            - Direct Rule Check.
            - Design Rule Check.
            - Design Right Check.
            - Direct Right Check.

            -
            10. -
            -
          10. - Overlapping is allowed in layers :
            - Poly and Metal.
            - Metal 1 and Metal 2.
            - Active and Poly.
            - All Of These.
            -
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          - - -
            -
          1. "CMOS Layout , concept, methodology and tools" by Dan Clein.

            2. - -
          2. "Priciples of CMOS VLSI design" by Weste-Eshraghian.

            3. - -
          3. "CMOS Circuit Design, Kayout, and Simulation" Third Edition by Baker, R. Jacob. Wiley-IEEE Press.

            4. -
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          - -

          - -Pre-Quiz Questions:

          -

          -Test your Understanding Layout Design, by going through the following quiz:
          -   -

          -



          -

          -Virtual Experiment:
          -Please make sure that you are going to perform experiment only after going through the following sections:

          -1. Manual
          -2. Procedure
          -3. Objectives
          -

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          • CLICK HERE TO START LAYOUT DESIGN EXPERIMENT
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          Computer Science & Engineering →VLSI Lab →List Of Experiments

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          - -
          - - -

          Layout Design.

          -

          - - -

          The physical mask layout of any circuit to be manufactured using a particular process must conform to a set of geometric constraints or rules, which are generally called layout design rules. These rules usually specify the minimum allowable line widths for physical objects on-chip such as metal and polysilicon interconnects or diffusion areas, minimum feature dimensions, and minimum allowable separations between two such features. If a metal line width is made too small, for example, it is possible for the line to break during the fabrication process or afterwards, resulting in an open circuit. If two lines are placed too close to each other in the layout, they may form an unwanted short circuit by merging during or after the fabrication process. The main objective of design rules is to achieve a high overall yield and reliability while using the smallest possible silicon area, for any circuit to be manufactured with a particular process. -


          - -

          We can say, in general, that observing the layout design rules significantly increases the probability of fabricating a successful product with high yield.


          - -
            -
          • The design rules are usually described in two ways :


            • -
          • Micron rules, in which the layout constraints such as minimum feature sizes and minimum allowable feature separations, are stated in terms of absolute dimensions in micrometers, or,
            • -
          • Lambda rules, which specify the layout constraints in terms of a single parameter Lambda and, thus, allow linear, proportional scaling of all geometrical constraints.
            • -
          - -


          -

          SOME DEFINED RULES :


          - Description : L-Rule

          - Minimum active area width : 3 L
          - Minimum active area spacing : 3 L
          - Minimum poly width : 2 L
          - Minimum poly spacing : 2 L
          - Minimum gate extension of poly over active : 2 L
          - - Minimum poly-active edge spacing : 1 L
          - (poly outside active area)
          - Minimum poly-active edge spacing : 3 L
          - (poly inside active area)
          - Minimum metal width : 3 L
          - Minimum metal spacing : 3 L
          - Poly contact size : 2 L
          - Minimum poly contact spacing : 2 L
          - Minimum poly contact to poly edge spacing : 1 L
          - Minimum poly contact to metal edge spacing : 1 L
          - Minimum poly contact to active edge spacing : 3 L
          - Active contact size : 2 L
          - Minimum active contact spacing : 2 L
          - (on the same active region)
          - Minimum active contact to active edge spacing : 1 L
          - Minimum active contact to metal edge spacing : 1 L
          - Minimum active contact to poly edge spacing : 3 L
          - Minimum active contact spacing : 6 L
          -

          -

          -
          - -

          Pictorial presentation of Layout Design Rules (DRCs) : Intra Layer Design Rules



          - Figure1: Intra Layer Design Rules.
          -


          Figure2: Transistor Layout.
          -


          Figure3: Vias and Contacts.
          -


          Figure4: CMOS Inverter Layout.
          -


          - -

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          - - - + + + + + + + - - - - - - - - - - - - \ No newline at end of file From ed3ab90b8c78538a7c311ac46b8ec5c1fbefec88 Mon Sep 17 00:00:00 2001 From: mrudhvika940 Date: Fri, 15 May 2020 18:07:36 +0530 Subject: [PATCH 11/17] Updated other fixes --- src/lab/Feedback.html | 6 +++--- src/lab/List of experiments.html | 21 +++++++++++---------- 2 files changed, 14 insertions(+), 13 deletions(-) diff --git a/src/lab/Feedback.html b/src/lab/Feedback.html index 6d0deca0..3c33c238 100644 --- a/src/lab/Feedback.html +++ b/src/lab/Feedback.html @@ -115,14 +115,13 @@

          -

          Data Structures

          +

          Very Large Scale Integration Lab

          Dear User,

          - Thanks for using Virtual Labs. Your opinion is valuable to us. To help us improve, we'd like to ask you a few questions about your experience. It will only take 3 minutes and your answers will help us - make Virtual Labs better for you and other users. + Thanks for using Virtual Labs. Your opinion is valuable to us. To help us improve, we'd like to ask you a few questions about your experience. It will only take 3 minutes and your answers will help us make Virtual Labs better for you and other users.


          @@ -242,4 +241,5 @@

          Follow Us

          + \ No newline at end of file diff --git a/src/lab/List of experiments.html b/src/lab/List of experiments.html index 19b8ef0c..1d540b15 100644 --- a/src/lab/List of experiments.html +++ b/src/lab/List of experiments.html @@ -207,11 +207,11 @@

          Very Large Scale Integration Lab

          In this experiment we will learn the basic design of an inverter. Inverter is the most basic component which we can make out using one NMOS and one PMOS transistor. Here you will learn about the basics how inverter works internally, how the transistor are placed inside inverter and how we get the inverted output corresponding to the inputs we provide. We will learn the layout designing and - effects of capacitance and effects of width and length of transistor on the output of an inverter. + effects of capacitance and effects of width and length of transistor on the output of an inverter
        • - Schematic Design Of Transistor Level NAND & NOR Gate. + Schematic Design Of Transistor Level NAND & NOR Gate

          • Click here to see Description

          @@ -221,7 +221,7 @@

          Very Large Scale Integration Lab

        • - Schematic Design Of Transistor Level XOR & XNOR Gate. + Schematic Design Of Transistor Level XOR & XNOR Gate

          • Click here to see Description

          @@ -230,7 +230,7 @@

          Very Large Scale Integration Lab

        • - Schematic Design Of Pass Transistor Logic & Multiplexer.
          + Schematic Design Of Pass Transistor Logic & Multiplexer

          • Click here to see Description

          @@ -240,7 +240,7 @@

          Very Large Scale Integration Lab

        • - Delay Estimation In Chain Of Inverters. + Delay Estimation In Chain Of Inverters

          • Click here to see Description

          @@ -250,7 +250,7 @@

          Very Large Scale Integration Lab

        • - Schematic Design Of D-Latch and D-Flip Flop. + Schematic Design Of D-Latch and D-Flip Flop

          • Click here to see Description

          @@ -261,7 +261,7 @@

          Very Large Scale Integration Lab

        • - Spice Code Platform. + Spice Code Platform

          • Click here to see Description

          @@ -272,7 +272,7 @@

          Very Large Scale Integration Lab

        • - Design Of D-Flip Flop Using Verilog. + Design Of D-Flip Flop Using Verilog

          • Click here to see Description

          @@ -287,7 +287,7 @@

          Very Large Scale Integration Lab

        • - Design Of Digital Circuits Using Verilog. + Design Of Digital Circuits Using Verilog

          • Click here to see Description

          @@ -297,7 +297,7 @@

          Very Large Scale Integration Lab

        • - Layout Design. + Layout Design

          • @@ -409,4 +409,5 @@

          Follow Us

          + \ No newline at end of file From a2c37aaa7e482b7f92cdb2d0df2bb3dc154c44a7 Mon Sep 17 00:00:00 2001 From: mrudhvika940 Date: Mon, 18 May 2020 16:29:59 +0530 Subject: [PATCH 12/17] fixed issues on baadal --- src/lab/Introduction.html | 558 +++++++++--------- src/lab/Prerequisites.html | 5 +- .../EXP_1sep2010/exp1/Introduction.html | 23 +- .../EXP_1sep2010/exp1/Objective.html | 5 +- .../EXP_1sep2010/exp1/References.html | 4 +- .../EXP_1sep2010/exp1/Simulator.html | 7 +- .../EXP_1sep2010/exp2/Procedure.html | 3 +- .../EXP_1sep2010/exp2/References.html | 4 +- .../final-build/EXP_1sep2010/exp2/Theory.html | 5 +- .../final-build/EXP_1sep2010/exp3/Theory.html | 3 +- .../EXP_1sep2010/exp4/Introduction.html | 9 +- .../final-build/EXP_1sep2010/exp4/Quiz.html | 5 +- .../EXP_1sep2010/exp4/Simulator.html | 3 +- .../final-build/EXP_1sep2010/exp4/Theory.html | 3 +- .../EXP_1sep2010/exp5/Simulator.html | 6 +- .../final-build/EXP_1sep2010/exp6/Manual.html | 434 +++++++------- .../final-build/EXP_1sep2010/exp6/Quiz.html | 11 +- .../final-build/EXP_1sep2010/exp6/Theory.html | 3 +- .../EXP_1sep2010/exp7/Introduction.html | 3 +- .../final-build/EXP_1sep2010/exp7/Manual.html | 27 +- .../EXP_1sep2010/exp7/Objective.html | 7 +- .../final-build/EXP_1sep2010/exp7/Quiz.html | 7 +- .../final-build/EXP_1sep2010/exp7/Theory.html | 3 +- .../EXP_1sep2010/exp8/Introduction.html | 3 +- .../EXP_1sep2010/exp9/Introduction.html | 12 +- .../EXP_1sep2010/exp9/Objective.html | 3 +- .../final-build/EXP_1sep2010/exp9/Theory.html | 5 +- .../EXP_1sep2010/layout/Procedure.html | 3 +- .../EXP_1sep2010/layout/Theory.html | 3 +- src/lab/index.html | 7 +- 30 files changed, 618 insertions(+), 556 deletions(-) diff --git a/src/lab/Introduction.html b/src/lab/Introduction.html index cfa0439b..ef3ed308 100644 --- a/src/lab/Introduction.html +++ b/src/lab/Introduction.html @@ -1,293 +1,291 @@ - - - - - - - - - - - Welcome to Virtual Labs - A MHRD Govt of india Initiative - - - - - - - - - - - - - - - - - - - - - - - -
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          Computer Science & Engineering

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          Introduction

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          Feedback

           -
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          Very Large Scale Integration Lab

          -
          -

          - A single chip sized of few millimeters may have Millions of transistors in it for example a microprocessor is a VLSI device. Very Large Scale Integration (VLSI) is the process of creating integrated - circuits by combining large numbers of transistors into a single chip.
          -

          -

          -
          -

          -
          -

          This lab provides good understanding and learning opportunity of VLSI designing for users. There are ten experiments in this lab, which covers following aspects of VLSI designing.

          -
          -

          -
            -

          • First six experiments provide GUI interface of schematic design and simulation results of various circuits.

            • -
            -

          • Seventh experiment provides WEB based Spice code simulation platform. User can learn circuit design using Spice coding.

            • -
            -
          • -

            - Eighth and ninth experiments provide digital circuit designing using Verilog code for which a web based Verilog simulation platform is provided. User can test any level of Verilog code in ninth - experiment. -

            -
            • -
            -
          • -

            - Tenth experiment provides GUI interface of physical (layout) design of various circuits. By this experiment user can learn design rules (DRCs) for layout design and can test design rules of their - designs. -

            -
            • -
            -
              -
              -
              -
            -

            - - -
            - - - -
            -
            -
            -
            + + + + + + + + + Welcome to Virtual Labs - A MHRD Govt of india Initiative + + + + + + + + + + + + + + + + +
            +
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            +
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            +
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            + + +
            +

            Computer Science & Engineering

            +
            +
            + + +

            Introduction

            +             + +

            List of experiments

            +             + +

            Target Audience

            +             + +

            Courses Aligned

            +             + +

            Prerequisites

            +             + +

            Feedback

            +             +
            +
            + +

            Very Large Scale Integration Lab

            +
            +

            + A single chip sized of few millimeters may have Millions of transistors in it for example a microprocessor is a VLSI device. Very Large Scale Integration (VLSI) is the process of creating integrated + circuits by combining large numbers of transistors into a single chip.
            +

            +

            +
            +

            +
            +

            This lab provides good understanding and learning opportunity of VLSI designing for users. There are ten experiments in this lab, which covers following aspects of VLSI designing.

            +
            +

            +
              +
            • +

              First six experiments provide GUI interface of schematic design and simulation results of various circuits.

              +
              • +
              +
            • +

              Seventh experiment provides WEB based Spice code simulation platform. User can learn circuit design using Spice coding.

              +
              • +
              +
            • +

              + Eighth and ninth experiments provide digital circuit designing using Verilog code for which a web based Verilog simulation platform is provided. User can test any level of Verilog code in ninth + experiment. +

              +
              • +
              +
            • +

              + Tenth experiment provides GUI interface of physical (layout) design of various circuits. By this experiment user can learn design rules (DRCs) for layout design and can test design rules of their + designs. +

              +
              • +
              +
                +
                +
                +
              +

              + +
              + + +
              +
              - - - -
              +
              + + + +
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              +
              - - - + +
              + + + + + + + - - - - - \ No newline at end of file diff --git a/src/lab/Prerequisites.html b/src/lab/Prerequisites.html index 545e9b83..0bc3a50b 100644 --- a/src/lab/Prerequisites.html +++ b/src/lab/Prerequisites.html @@ -144,8 +144,8 @@

              Very Large Scale Integration Lab

            • Java allows you to play online virtual labs.
            • Adobe Flash (formerly Macromedia Flash) is a multimedia platform used to add animation, video, and interactivity to web pages.
              • -

              - Install Java plugin run the simulation +

              Install Java + plugin to run the simulation.

              @@ -255,4 +255,5 @@

              Follow Us

              + \ No newline at end of file diff --git a/src/lab/final-build/EXP_1sep2010/exp1/Introduction.html b/src/lab/final-build/EXP_1sep2010/exp1/Introduction.html index 21db08bb..6f5e5cca 100755 --- a/src/lab/final-build/EXP_1sep2010/exp1/Introduction.html +++ b/src/lab/final-build/EXP_1sep2010/exp1/Introduction.html @@ -118,14 +118,16 @@

              Schematic Design Of Transistor Level Inverter

              Inverter is a logic gate, with one input - and one output. Its symbol is shown below :-

              + and one output. Its symbol is shown below :- +

              The output of inverter is complement of - the input i.e. if the input is 0, the - output will be 1 and vice-versa. The - truth table for inverter is shown below :-

              + the input i.e. if the input is 0, the + output will be 1 and vice-versa. The + truth table for inverter is shown below :- +

              @@ -148,11 +150,11 @@

              Schematic Design Of Transistor Level Inverter

              -

                -
              1. Complementary CMOS logic
                2. -
              2. Pseudo NMOS logic
                3. -
              - +

              +
                +
              1. Complementary CMOS logic
                2. +
              2. Pseudo NMOS logic
                3. +

              @@ -255,7 +257,4 @@

              Follow Us

              - - - \ No newline at end of file diff --git a/src/lab/final-build/EXP_1sep2010/exp1/Objective.html b/src/lab/final-build/EXP_1sep2010/exp1/Objective.html index 350f1d89..39276c96 100755 --- a/src/lab/final-build/EXP_1sep2010/exp1/Objective.html +++ b/src/lab/final-build/EXP_1sep2010/exp1/Objective.html @@ -113,10 +113,10 @@

              Feedback

              -

              Schematic Design Of Transistor Level Inverter.

              +

              Schematic Design Of Transistor Level Inverter

              -
                +
                1. To design transistor level schematic of an Inverter using :- @@ -232,4 +232,5 @@

                  Follow Us

                  + \ No newline at end of file diff --git a/src/lab/final-build/EXP_1sep2010/exp1/References.html b/src/lab/final-build/EXP_1sep2010/exp1/References.html index 09f8b916..4b5f9de4 100755 --- a/src/lab/final-build/EXP_1sep2010/exp1/References.html +++ b/src/lab/final-build/EXP_1sep2010/exp1/References.html @@ -119,7 +119,8 @@

                  Schematic Design Of Transistor Level Inverter

                    -
                  1. "Principles of cmos vlsi design"by Weste-Eshraghian
                    2. +
                  2. "Principles of cmos vlsi + design" by Weste-Eshraghian

                  3. CMOS: Circuit Design, Layout, and Simulation, Third Edition by Bacor, R. Jacob. Wiley-IEEE. pp. 1174.Chen, Wai-Kai (ed) (2006).
                    4. @@ -234,4 +235,5 @@

                    Follow Us

                    + \ No newline at end of file diff --git a/src/lab/final-build/EXP_1sep2010/exp1/Simulator.html b/src/lab/final-build/EXP_1sep2010/exp1/Simulator.html index a474313e..05b67b7c 100755 --- a/src/lab/final-build/EXP_1sep2010/exp1/Simulator.html +++ b/src/lab/final-build/EXP_1sep2010/exp1/Simulator.html @@ -115,11 +115,11 @@

                    Feedback

                    Schematic Design Of Transistor Level Inverter

                    - Make sure that you have prerequisites installed to run experiment +

                    Make sure that you have prerequisites installed to run experiment



                    - Click - here for the experiment

                    +

                    Click + here for the experiment

              @@ -222,4 +222,5 @@

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              + \ No newline at end of file diff --git a/src/lab/final-build/EXP_1sep2010/exp2/Procedure.html b/src/lab/final-build/EXP_1sep2010/exp2/Procedure.html index 80737fb0..db1449b5 100755 --- a/src/lab/final-build/EXP_1sep2010/exp2/Procedure.html +++ b/src/lab/final-build/EXP_1sep2010/exp2/Procedure.html @@ -54,7 +54,7 @@
              • - HOME + HOME
              • PARTNERS @@ -219,4 +219,5 @@

                Follow Us

                + \ No newline at end of file diff --git a/src/lab/final-build/EXP_1sep2010/exp2/References.html b/src/lab/final-build/EXP_1sep2010/exp2/References.html index 9ae8c233..8f11e2e2 100755 --- a/src/lab/final-build/EXP_1sep2010/exp2/References.html +++ b/src/lab/final-build/EXP_1sep2010/exp2/References.html @@ -115,7 +115,8 @@

                Schematic Design Of Transistor Level NAND & N
                  -
                1. "Principles of cmos vlsi design"by Weste-Eshraghian

                  2. +
                2. "Principles of cmos vlsi + design" by Weste-Eshraghian

                3. CMOS: Circuit Design, Layout, and Simulation, Third Edition by Bacor, R. Jacob. Wiley-IEEE. pp. 1174.Chen, Wai-Kai (ed) (2006).

                  4. @@ -228,4 +229,5 @@

                  Follow Us

                  + \ No newline at end of file diff --git a/src/lab/final-build/EXP_1sep2010/exp2/Theory.html b/src/lab/final-build/EXP_1sep2010/exp2/Theory.html index 7b5d3a25..1ca2e412 100755 --- a/src/lab/final-build/EXP_1sep2010/exp2/Theory.html +++ b/src/lab/final-build/EXP_1sep2010/exp2/Theory.html @@ -250,7 +250,9 @@

                  K-MAP FOR NAND


                  -

                  Thus for NAND gate PMOS devices are connected in parallel between Vdd and output node,whereas the NMOS devices are in series between output node and ground.

                  +

                  Thus for NAND gate PMOS devices are + connected in parallel between Vdd and output + node, whereas the NMOS devices are in series between output node and ground.


                  K-MAP FOR NOR


                  @@ -366,4 +368,5 @@

                  Follow Us

                  + \ No newline at end of file diff --git a/src/lab/final-build/EXP_1sep2010/exp3/Theory.html b/src/lab/final-build/EXP_1sep2010/exp3/Theory.html index 4884d451..a05ae28a 100755 --- a/src/lab/final-build/EXP_1sep2010/exp3/Theory.html +++ b/src/lab/final-build/EXP_1sep2010/exp3/Theory.html @@ -161,7 +161,7 @@

                  XNOR

                  PMOS. In that case B would be analougos to B in the above - example, + example, A to C and B to D.

                  @@ -269,4 +269,5 @@

                  Follow Us

                  + \ No newline at end of file diff --git a/src/lab/final-build/EXP_1sep2010/exp4/Introduction.html b/src/lab/final-build/EXP_1sep2010/exp4/Introduction.html index d02f5779..a568974a 100755 --- a/src/lab/final-build/EXP_1sep2010/exp4/Introduction.html +++ b/src/lab/final-build/EXP_1sep2010/exp4/Introduction.html @@ -139,15 +139,15 @@

                  Schematic Design Of Pass Transistor Logic & Mu 1. Transmission gates are typically used as building blocks for logic circuitry, such as a D Latch or D Flip-Flop

                  2. Transmission gates are basic building block for multiplexer

                  3. Transmission gates can be used for blocking particular component from live signal

                  -

                  +

                  Multiplexer


                  Multiplexer or MUX, which is also known as data selector, is a combinational circuit with multiple input and single output. At a time a single input is selected and given as output based on select signal.

                  -

                  +

                  A multiplexer selects binary information present on any one on the input line, depending upon logic status of the selection inputs and routes to the output line. If there are n selection line then number of possible routes input lines is 2n and then multiplexer is referred as a 2n x 1 multiplexer.

                  -

                  +

                  Advantages of Multiplexer based on pass transistor:

                  1. Pass transistor multiplexer uses fewer transistors as compared to fully complementary gates

                  @@ -254,4 +254,5 @@

                  Follow Us

                  -
                \ No newline at end of file + + \ No newline at end of file diff --git a/src/lab/final-build/EXP_1sep2010/exp4/Quiz.html b/src/lab/final-build/EXP_1sep2010/exp4/Quiz.html index 75e3b307..21bca90a 100755 --- a/src/lab/final-build/EXP_1sep2010/exp4/Quiz.html +++ b/src/lab/final-build/EXP_1sep2010/exp4/Quiz.html @@ -113,10 +113,10 @@

                Feedback

                Schematic Design Of Pass Transistor Logic & Multiplexer

                -

                +

                Pre Quiz Questions:

                -

                +

                Test your Understanding Pass Transistor and Multiplexer , by going through the following quiz:

                @@ -226,4 +226,5 @@

                Follow Us

                + \ No newline at end of file diff --git a/src/lab/final-build/EXP_1sep2010/exp4/Simulator.html b/src/lab/final-build/EXP_1sep2010/exp4/Simulator.html index 33efd77e..cc43fb41 100755 --- a/src/lab/final-build/EXP_1sep2010/exp4/Simulator.html +++ b/src/lab/final-build/EXP_1sep2010/exp4/Simulator.html @@ -126,7 +126,7 @@

                Schematic Design Of Pass Transistor Logic & Mu null,'scrollbars=yes, width=' + (screen.availWidth) +',height=' + (screen.availHeight));return false;">
                -

                +

                  @@ -249,4 +249,5 @@

                  Follow Us

                  + \ No newline at end of file diff --git a/src/lab/final-build/EXP_1sep2010/exp4/Theory.html b/src/lab/final-build/EXP_1sep2010/exp4/Theory.html index 23ebeb24..52040908 100755 --- a/src/lab/final-build/EXP_1sep2010/exp4/Theory.html +++ b/src/lab/final-build/EXP_1sep2010/exp4/Theory.html @@ -193,7 +193,7 @@

                  PASS TRANSISTOR LOGIC THROUGH PMOS


                  The above shown pass transistor will now be able to give a good one as well as good zero. At the time when S=1, both will be able to pass so whether the input signal is zero or one it will be passed almost as it is.

                  -

                  +

                  MULTIPLEXER


                  The multiplexer selects one of many analog or digital input. A multiplexer with 2n input lines have n select lines. The select lines can either be 0 or 1. Depending on the binary number(formed by combination of 1s and 0s) at the select lines. One of the input is selected and it is passed on to the output.

                  @@ -320,4 +320,5 @@

                  Follow Us

                  + \ No newline at end of file diff --git a/src/lab/final-build/EXP_1sep2010/exp5/Simulator.html b/src/lab/final-build/EXP_1sep2010/exp5/Simulator.html index 57600abb..b809abe6 100755 --- a/src/lab/final-build/EXP_1sep2010/exp5/Simulator.html +++ b/src/lab/final-build/EXP_1sep2010/exp5/Simulator.html @@ -114,7 +114,7 @@

                  Feedback

                  Delay Estimation In Chain Of Inverters

                  Make sure that you have prerequisites installed to run experiment.


                  -

                  +

                  Virtual Experiment:
                  Please make sure that you are going to perform experiment only after going through the following sections:

                  1. Manual
                  @@ -124,14 +124,13 @@

                  Delay Estimation In Chain Of Inverters

                  -

                  • Start the Experiment
                  -

                  +
                  @@ -237,4 +236,5 @@

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                  + \ No newline at end of file diff --git a/src/lab/final-build/EXP_1sep2010/exp6/Manual.html b/src/lab/final-build/EXP_1sep2010/exp6/Manual.html index a8ffbe56..d18ee672 100755 --- a/src/lab/final-build/EXP_1sep2010/exp6/Manual.html +++ b/src/lab/final-build/EXP_1sep2010/exp6/Manual.html @@ -1,222 +1,250 @@ - - + + - Welcome to Virtual Labs - A MHRD Govt of india Initiative - - - - + - - - - - - - + + + + - - - - -
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                  Computer Science & Engineering →VLSI Lab →List Of Experiments

                  - -
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                  - -<<<<<<< HEAD -

                  Introduction

                  Objective

                  Theory

                  Procedure

                  Manual

                  Simulator

                  Quiz

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                  -======= -

                  Introduction

                  Objective

                  Theory

                  Procedure

                  Simulator

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                  ->>>>>>> ee1b45c0d5e161a5d08dea1e3dab5f307d7ad6d6 - -
                  - - -

                  Schematic Design Of D-Latch and D-Flip Flop. -

                  -

                  - -Experiment Manual is under construction -

                  -
                  -
                  -
                  - - - - - -
                  - - - - - - - - - - + + + - - - + - - - - - + + + + + \ No newline at end of file diff --git a/src/lab/final-build/EXP_1sep2010/exp6/Quiz.html b/src/lab/final-build/EXP_1sep2010/exp6/Quiz.html index 03c33960..edb82117 100755 --- a/src/lab/final-build/EXP_1sep2010/exp6/Quiz.html +++ b/src/lab/final-build/EXP_1sep2010/exp6/Quiz.html @@ -146,17 +146,17 @@

                  Schematic Design Of Transistor Level Inverter

                  Only on input D


                  + 3. The timing diagram corresponds to:
                • - 3. The timing diagram corresponds to:
                  D latch
                  Positive edge triggered D flip flop
                  Negative edge triggered D flip flop
                  None of them


                  • + 4. The timing diagram corresponds to
                • - 4. The timing diagram corresponds to
                  - D latch
                  + D latch
                  Negative edge triggered flip flop
                  Positive edge triggered
                  None of them

                  @@ -180,7 +180,7 @@

                  Schematic Design Of Transistor Level Inverter

                  7. Which statement below is the apt definition of flip flop
                  Latch
                  Coupled latch
                  - De-coupled latch

                  + De-coupled latch
                  Clocked latch

                  • @@ -194,7 +194,7 @@

                  Schematic Design Of Transistor Level Inverter


                • 9. What kind of flip flop is generally preffered for constructing counters?
                   - J K-flip flop
                  + J K-flip flop
                  T flip flop
                  D flip flop
                  None of the above

                  @@ -317,4 +317,5 @@

                  Follow Us

                  + \ No newline at end of file diff --git a/src/lab/final-build/EXP_1sep2010/exp6/Theory.html b/src/lab/final-build/EXP_1sep2010/exp6/Theory.html index 84f41c6c..673271cf 100755 --- a/src/lab/final-build/EXP_1sep2010/exp6/Theory.html +++ b/src/lab/final-build/EXP_1sep2010/exp6/Theory.html @@ -126,8 +126,8 @@

                  Working of the latch when clock is 0.

                  When clock is 0 the pass transistor in red is on and the one connected to the input D is off thus any changes in D does not affect the circuit. If we observe the transistor in red is connected to the buffer at the output which loops back to its input thus the same value occurs at Q' again and again till this pass transistor is on.


                  -

                  POSITIVE EDGE TRIGGERED FLIP FLOP

                  +

                  From the introduction it is clear that for a positive edge triggered flip flop the changes in output occurs at the transition level. This is done by configuring two D latches in master slave configuration.A master slave D flip-flop is created by connecting two gated D latches in series, and inverting the clock input to one of them. It is called master slave because the second latch in the series only changes in response to a change in the first (master) latch. To understand the transistor level design of positive edge triggered flip flop study the two diagrams below

                  @@ -250,4 +250,5 @@

                  Follow Us

                  + \ No newline at end of file diff --git a/src/lab/final-build/EXP_1sep2010/exp7/Introduction.html b/src/lab/final-build/EXP_1sep2010/exp7/Introduction.html index 0d0ff5aa..d1bcb107 100755 --- a/src/lab/final-build/EXP_1sep2010/exp7/Introduction.html +++ b/src/lab/final-build/EXP_1sep2010/exp7/Introduction.html @@ -142,7 +142,7 @@

                  INTRODUCTION TO SPICE

                • Fourier analysis: calculates and plots the frequency spectrum.
                • Monte Carlo Analysis
                -
                All analyses can be done at different temperatures. The default temperature is 300K +
                All analyses can be done at different temperatures. The default temperature is 300K

                @@ -245,4 +245,5 @@

                Follow Us

                + \ No newline at end of file diff --git a/src/lab/final-build/EXP_1sep2010/exp7/Manual.html b/src/lab/final-build/EXP_1sep2010/exp7/Manual.html index c3b71cad..c23bd747 100755 --- a/src/lab/final-build/EXP_1sep2010/exp7/Manual.html +++ b/src/lab/final-build/EXP_1sep2010/exp7/Manual.html @@ -116,23 +116,23 @@

                Feedback

                Spice Code Platform

                -

                Click here for experiment manual

                +

                Click here for experiment

                -
                - - - + + + + - + -
                -
              • 8. What analysis should be performed to study variation of voltage over time?
                .op
                - .tran

                + .tran
                .dc
                - .sens
                + .sens

              • 9. Which of the following statement is false?
                First statement of a spice code is a comment
                @@ -314,4 +314,5 @@

                Follow Us

                + \ No newline at end of file diff --git a/src/lab/final-build/EXP_1sep2010/exp7/Theory.html b/src/lab/final-build/EXP_1sep2010/exp7/Theory.html index 40a94d28..27cd253c 100755 --- a/src/lab/final-build/EXP_1sep2010/exp7/Theory.html +++ b/src/lab/final-build/EXP_1sep2010/exp7/Theory.html @@ -216,7 +216,7 @@

                3.Output Statements



                - Complete example (Inverter-Netlist): + Complete example (Inverter-Netlist):


                @@ -345,4 +345,5 @@

                Follow Us

                + \ No newline at end of file diff --git a/src/lab/final-build/EXP_1sep2010/exp8/Introduction.html b/src/lab/final-build/EXP_1sep2010/exp8/Introduction.html index f8991080..31d74921 100755 --- a/src/lab/final-build/EXP_1sep2010/exp8/Introduction.html +++ b/src/lab/final-build/EXP_1sep2010/exp8/Introduction.html @@ -122,7 +122,7 @@

                Design Of D-Flip Flop Using Verilog


                The output of inverter is complement of the input i.e., if the input is 0, the output will be 1 and vice-versa. The truth table for inverter is shown below:-

                -
              +
              @@ -248,4 +248,5 @@

              Follow Us

              + \ No newline at end of file diff --git a/src/lab/final-build/EXP_1sep2010/exp9/Introduction.html b/src/lab/final-build/EXP_1sep2010/exp9/Introduction.html index e98acbb8..1b6b2c5d 100755 --- a/src/lab/final-build/EXP_1sep2010/exp9/Introduction.html +++ b/src/lab/final-build/EXP_1sep2010/exp9/Introduction.html @@ -120,9 +120,16 @@

              Design Of Digital Circuits Using Verilog

              INTRODUCTION TO VERILOG


              -

              Verilog is language commonly used in designing digital systems. It is a hardware description language, which means that it is substantially different from any other language you might have encountered so far. Even though it does have control flow statements and variables, it relies primarily on logic functions.It is a textual format for describing electronic circuits and systems.

              +

              Verilog is language commonly used in + designing digital systems. It is a hardware + description language, which means that it is + substantially different from any other + language you might have encountered so + far. Even though it does have control flow + statements and variables, it relies + primarily on logic functions. It is a textual format for describing electronic circuits and systems.


              -

              Verilog has evolved as a standard hardware description language. Verilog offers many useful features for hardware design. it is easy to learn and easy to use as it is similar to C Programming language. Designers with C Programming experience will find it easy to learn Verilog.

              +

              Verilog has evolved as a standard hardware description language. Verilog offers many useful features for hardware design. It is easy to learn and easy to use as it is similar to C Programming language. Designers with C Programming experience will find it easy to learn Verilog.

              @@ -226,4 +233,5 @@

              Follow Us

              + \ No newline at end of file diff --git a/src/lab/final-build/EXP_1sep2010/exp9/Objective.html b/src/lab/final-build/EXP_1sep2010/exp9/Objective.html index 16df25ff..a473b4cb 100755 --- a/src/lab/final-build/EXP_1sep2010/exp9/Objective.html +++ b/src/lab/final-build/EXP_1sep2010/exp9/Objective.html @@ -118,7 +118,7 @@

              Design Of Digital Circuits Using Verilog

              1. To learn the basic concepts of verilog - programming
                + programming

              2. To design multiplexers, counters etc. using verilog coding.
                @@ -229,4 +229,5 @@

                Follow Us

                + \ No newline at end of file diff --git a/src/lab/final-build/EXP_1sep2010/exp9/Theory.html b/src/lab/final-build/EXP_1sep2010/exp9/Theory.html index 93c3f1af..3eb04494 100755 --- a/src/lab/final-build/EXP_1sep2010/exp9/Theory.html +++ b/src/lab/final-build/EXP_1sep2010/exp9/Theory.html @@ -200,7 +200,6 @@

                BLOCKING AND NON-BLOCKING ASSIGNMENT


                -

                COUNTER

                @@ -230,10 +229,9 @@

                INSTANTIATION OF MODULE

                NOT - VERILOG PROVIDED PRIMITIVE


                There are many primitives already defined in verilog which provides some particular functionalities. not is one of them. In not first argument is output value and second is input value. So in above example d is output and q is input.

                -

                +
                -

                Verilog also provides us with some compiler directives and system tasks. These are not used in above programs but if you want to know about these functionalities, read the following flowcharts.


                @@ -344,4 +342,5 @@

                Follow Us

                + \ No newline at end of file diff --git a/src/lab/final-build/EXP_1sep2010/layout/Procedure.html b/src/lab/final-build/EXP_1sep2010/layout/Procedure.html index 0709f198..cb0bfc1f 100755 --- a/src/lab/final-build/EXP_1sep2010/layout/Procedure.html +++ b/src/lab/final-build/EXP_1sep2010/layout/Procedure.html @@ -134,7 +134,7 @@

                1.Select and placing layers :



                2.Layout completion and DRC check

                -

                +
                • Place all required layers and check DRC rule every time while placing layers.

                  • @@ -248,4 +248,5 @@

                  Follow Us

                  + \ No newline at end of file diff --git a/src/lab/final-build/EXP_1sep2010/layout/Theory.html b/src/lab/final-build/EXP_1sep2010/layout/Theory.html index 57595a3e..a576f046 100755 --- a/src/lab/final-build/EXP_1sep2010/layout/Theory.html +++ b/src/lab/final-build/EXP_1sep2010/layout/Theory.html @@ -133,7 +133,7 @@

                  Layout Design

                  The design rules are usually described in two ways :

                  • Micron rules : Micron rules, which the layout constraints such as minimum feature sizes and minimum allowable feature separations, are stated in terms of absolute dimensions in micrometers, or,
                    • -

                  • Lambda rules : Lambda rules, which specify the layout constraints in terms of a single parameter Lambda and, thus, allow linear, proportional scaling of all geometrical constraints.

                    • +
                  • Lambda rules : Lambda rules, which specify the layout constraints in terms of a single parameter Lambda and, thus, allow linear, proportional scaling of all geometrical constraints.


                  @@ -282,4 +282,5 @@

                  Follow Us

                  + \ No newline at end of file diff --git a/src/lab/index.html b/src/lab/index.html index f050bcce..e8a5be57 100644 --- a/src/lab/index.html +++ b/src/lab/index.html @@ -22,7 +22,7 @@ Welcome to Virtual Labs - A MHRD Govt of india Initiative - + @@ -51,7 +51,8 @@
                  -
                  - - - - + + - - - - - - - + + + + - - - - + --> + diff --git a/src/lab/final-build/EXP_1sep2010/exp5/preQuiz5.php b/src/lab/final-build/EXP_1sep2010/exp5/preQuiz5.php index e94cf963..7699b736 100755 --- a/src/lab/final-build/EXP_1sep2010/exp5/preQuiz5.php +++ b/src/lab/final-build/EXP_1sep2010/exp5/preQuiz5.php @@ -1,273 +1,263 @@ - - - - + + - Welcome to Virtual Labs - A MHRD Govt of india Initiative - - - - + - - - - - - - + + + + - - - - -
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                  +
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                  + +
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                  +

                  Computer Science & Engineering VLSI Lab Experiments

                  - -

                  Introduction

                  Objective

                  Theory

                  Procedure

                  Manual

                  Simulator

                  Quiz

                  References

                  Feedback
                  - + + +

                  Introduction

                  +                   + +

                  Objective

                  +                   + +

                  Theory

                  +                   + +

                  Procedure

                  +                   + +

                  Manual

                  +                   + +

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                  +                   + +

                  Quizzes

                  +                   + +

                  References

                  +                   + +

                  Feedback

                  +                   +
                  - -

                  Schematic Design Of Pass Transistor Logic & Multiplexer.

                  - -
                  -
                    -
                  1. What is the difference between a LATCH and a FLIP-FLOP?
                    - Latch is a level sensitive device while flip-flop is an edge sensitive device.
                    - Latches take more gates (also more power) to implement than flip-flops.
                    - Latches are slower than flip-flops.
                    - Flip flops are used as temporary buffer whereas latches are used as registers.
                    - -

                    2. - -
                  2. In a D latch __________ .
                    - a high D sets the latch and low D resets it .
                    - a low D sets the latch and high D resets it.
                    - race condition can occur .
                    - None of the above .
                    - -

                    3. - -
                  3. Which device has many input and one output ?
                    - Demultiplexer.
                    - Counter.
                    - Multiplexer.
                    - Flip flop .
                    - -

                    4. - -
                  4. A D flip-flop can be made from a _________
                    - JK flip-flop and an inverter .
                    - RS flip-flop .
                    - RS flip-flop and an inverter .
                    - both (a) and (b)..
                    - -

                    5. - -
                  5. Which of the following flip-flops does not have race around condition ?
                    - JK flip-flops .
                    - D flip-flops .
                    - S-R flip-flop converted to J-K flip-flop .
                    - Master slave JK flip flop.
                    -
                  -
                  -

                  - -
                  -
                  - - -
                  +

                  Schematic Design Of Pass Transistor Logic & Multiplexer

                  +
                  +
                  +
                    +
                  1. 1. What is the difference between a LATCH and a FLIP-FLOP?
                    + Latch is a level sensitive device while flip-flop is an edge sensitive device.
                    + Latches take more gates (also more power) to implement than flip-flops.
                    + Latches are slower than flip-flops.
                    + Flip flops are used as temporary buffer whereas latches are used as registers.
                    +
                    2. +
                    +
                  2. 2. In a D latch __________ .
                    + A high D sets the latch and low D resets it .
                    + A low D sets the latch and high D resets it.
                    + Race condition can occur .
                    + None of the above .
                    +
                    3. +
                    +
                  3. 3. Which device has many input and one output ?
                    + Demultiplexer
                    + Counter
                    + Multiplexer
                    + Flip flop
                    +
                    4. +
                    +
                  4. 4. A D flip-flop can be made from a _________
                    + JK flip-flop and an inverter .
                    + RS flip-flop .
                    + RS flip-flop and an inverter .
                    + Both (a) and (b)..
                    +
                    5. +
                    +
                  5. 5. Which of the following flip-flops does not have race around condition ?
                    + JK flip-flops .
                    + D flip-flops .
                    + S-R flip-flop converted to J-K flip-flop .
                    + Master slave JK flip flop.
                    +
                  +
                  +

                  + +
                  + +
                  + +
                  +
                  +
                  + - - - - - - - - - - - - - - - + + - - - - - - - + + + + - - - - + --> + diff --git a/src/lab/final-build/EXP_1sep2010/exp6/Manual.html b/src/lab/final-build/EXP_1sep2010/exp6/Manual.html index d18ee672..cf35d4e3 100755 --- a/src/lab/final-build/EXP_1sep2010/exp6/Manual.html +++ b/src/lab/final-build/EXP_1sep2010/exp6/Manual.html @@ -112,34 +112,7 @@

                  References

                  Feedback

                  - ======= - -

                  Introduction

                  -                   - -

                  Objective

                  -                   - -

                  Theory

                  -                   - -

                  Procedure

                  -                   - - -

                  Simulator

                  -                   - -

                  Quiz

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                  References

                  -                   - -

                  Feedback

                  -                   - - >>>>>>> ee1b45c0d5e161a5d08dea1e3dab5f307d7ad6d6 +

                  Schematic Design Of D-Latch and D-Flip Flop.

                  @@ -247,4 +220,5 @@

                  Follow Us

                  - \ No newline at end of file + +
                  \ No newline at end of file diff --git a/src/lab/final-build/EXP_1sep2010/exp6/preQuiz6.php b/src/lab/final-build/EXP_1sep2010/exp6/preQuiz6.php index 54788585..b3098be3 100755 --- a/src/lab/final-build/EXP_1sep2010/exp6/preQuiz6.php +++ b/src/lab/final-build/EXP_1sep2010/exp6/preQuiz6.php @@ -25,8 +25,9 @@ - - + +
                  @@ -42,7 +43,7 @@ - +
                  @@ -59,15 +60,15 @@ @@ -82,7 +83,7 @@
                  -
                  +
                  @@ -90,56 +91,60 @@
                  -

                  Computer Science & Engineering →VLSI Lab →List Of Experiments

                  +

                  Computer Science & Engineering VLSI Lab Experiments

                  -

                  Introduction

                  Objective

                  Theory

                  Procedure

                  Manual

                  Simulator

                  Quiz

                  References

                  Feedback
                  +

                  Introduction

                  Objective

                  Theory

                  Procedure

                  Manual

                  Simulation

                  Quizzes

                  References

                  Feedback
                  -

                  Schematic Design Of Pass Transistor Logic & Multiplexer.

                  +

                  Schematic Design Of Pass Transistor Logic & Multiplexer

                    -
                  1. Multiplex is a ?
                    - Combinational Circuit .
                    - Flip Flop .
                    - Sequential Circuit .
                    - None of the above .
                    +
                  2. 1. Multiplex is a ?
                    + Combinational Circuit .
                    + Flip Flop .
                    + Sequential Circuit .
                    + None of the above .

                    3. -
                  3. Transmission gate is a ?
                    - Parallel combination of two NMOS .
                    - Series combination of NMOS and PMOS .
                    - Parallel combination of NMOS and PMOS .
                    - None of the above .
                    +
                  4. 2. Transmission gate is a ?
                    + Parallel combination of two NMOS .
                    + Series combination of NMOS and PMOS .
                    + Parallel combination of NMOS and PMOS .
                    + None of the above .

                    5. -
                  5. Transmission gate is preferred over Complementary CMOS logic because ____
                    - Transistor count required to implement a logic function in transmission gate is low .
                    - Low Delay .
                    - Both of them .
                    - None of the above .
                    +
                  6. 3. Transmission gate is preferred over Complementary CMOS logic because ____
                    + Transistor count required to implement a logic function in transmission gate is low .
                    + Low Delay
                    + Both of them
                    + None of the above

                    7. -
                  7. How many 2x1 multiplexer will be require to design 8x1 multiplexer ?
                    - Three .
                    - Seven .
                    - Four .
                    - Eight .
                    +
                  8. 4. How many 2x1 multiplexer will be require to design 8x1 multiplexer ?
                    + Three
                    + Seven
                    + Four
                    + Eight

                    9. -
                  9. Multiplexer is also known as:
                    - Counter .
                    - Data Select .
                    - Single Input Many Output .
                    - None .
                    +
                  10. 5. Multiplexer is also known as:
                    + Counter
                    + Data Select
                    + Single Input Many Output
                    + None



                  @@ -158,62 +163,52 @@
                  - -
                  + diff --git a/src/lab/final-build/EXP_1sep2010/exp7/Manual.html b/src/lab/final-build/EXP_1sep2010/exp7/Manual.html index c23bd747..8544af2f 100755 --- a/src/lab/final-build/EXP_1sep2010/exp7/Manual.html +++ b/src/lab/final-build/EXP_1sep2010/exp7/Manual.html @@ -116,23 +116,23 @@

                  Feedback

                  Spice Code Platform

                  -

                  Click here for experiment

                  -

                  -
                  -
                  -
                  -
                  +

                  Click here for the manual +

                  +
                  + + + - + -
                  -
                @@ -99,10 +99,10 @@

                Procedure

                Manual

                -

                Simulator

                +

                Simulation

                 -

                Quiz

                +

                Quizzes

                References

                @@ -298,4 +298,5 @@

                Follow Us

                + \ No newline at end of file
              Input