@@ -335,17 +335,17 @@ uint16_t vsfhal_usart_rx_bytes(vsfhal_usart_t index, uint8_t *data, uint16_t siz
335
335
if (index >= VSFHAL_USART_NUM )
336
336
return 0 ;
337
337
338
- if ((rx_dma_buff_pos [index ] + size ) <= (VSFHAL_USART_NUM * 2 ))
338
+ if ((rx_dma_buff_pos [index ] + size ) <= (DMA_BUFF_SIZE * 2 ))
339
339
{
340
340
tail = size ;
341
341
head = 0 ;
342
342
}
343
343
else
344
344
{
345
- tail = VSFHAL_USART_NUM * 2 - rx_dma_buff_pos [index ];
345
+ tail = DMA_BUFF_SIZE * 2 - rx_dma_buff_pos [index ];
346
346
head = size - tail ;
347
347
}
348
-
348
+
349
349
if (tail )
350
350
memcpy (data , & rx_dma_buff [index ][rx_dma_buff_pos [index ]], tail );
351
351
if (head )
@@ -360,15 +360,15 @@ uint16_t vsfhal_usart_rx_bytes(vsfhal_usart_t index, uint8_t *data, uint16_t siz
360
360
361
361
uint16_t vsfhal_usart_rx_get_data_size (vsfhal_usart_t index )
362
362
{
363
- uint16_t dma_pos ;
363
+ uint32_t dma_pos ;
364
364
365
365
switch (index )
366
366
{
367
367
case 0 :
368
- dma_pos = VSFHAL_USART_NUM * 2 - DMA_CH2CNT ;
368
+ dma_pos = DMA_BUFF_SIZE * 2 - DMA_CH2CNT ;
369
369
break ;
370
370
case 1 :
371
- dma_pos = VSFHAL_USART_NUM * 2 - DMA_CH4CNT ;
371
+ dma_pos = DMA_BUFF_SIZE * 2 - DMA_CH4CNT ;
372
372
break ;
373
373
default :
374
374
return 0 ;
@@ -377,7 +377,7 @@ uint16_t vsfhal_usart_rx_get_data_size(vsfhal_usart_t index)
377
377
if (rx_dma_buff_pos [index ] <= dma_pos )
378
378
return dma_pos - rx_dma_buff_pos [index ];
379
379
else
380
- return dma_pos + VSFHAL_USART_NUM * 2 - rx_dma_buff_pos [index ];
380
+ return dma_pos + DMA_BUFF_SIZE * 2 - rx_dma_buff_pos [index ];
381
381
}
382
382
383
383
uint16_t vsfhal_usart_rx_get_free_size (vsfhal_usart_t index )
@@ -419,7 +419,7 @@ ROOT void USART0_IRQHandler(void)
419
419
if (USART_STAT (USART0 ) & USART_STAT_RTF )
420
420
{
421
421
USART_INTC (USART0 ) = USART_INTC_RTC ;
422
- dma_pos = VSFHAL_USART_NUM * 2 - DMA_CH2CNT ;
422
+ dma_pos = DMA_BUFF_SIZE * 2 - DMA_CH2CNT ;
423
423
if ((dma_pos != rx_dma_buff_pos [0 ]) && vsfhal_usart_onrx [0 ])
424
424
vsfhal_usart_onrx [0 ](vsfhal_usart_callback_param [0 ]);
425
425
}
@@ -436,9 +436,15 @@ ROOT void DMA_Channel1_2_IRQHandler(void)
436
436
vsfhal_usart_ontx [0 ](vsfhal_usart_callback_param [0 ]);
437
437
}
438
438
// rx dma
439
- if (DMA_INTF & (DMA_INTF_GIF << (0x2 * 4 )))
439
+ if (DMA_INTF & (DMA_INTF_HTFIF << (0x2 * 4 )))
440
+ {
441
+ DMA_INTC = DMA_INTF_HTFIF << (0x2 * 4 );
442
+ if (vsfhal_usart_onrx [0 ])
443
+ vsfhal_usart_onrx [0 ](vsfhal_usart_callback_param [0 ]);
444
+ }
445
+ if (DMA_INTF & (DMA_INTF_FTFIF << (0x2 * 4 )))
440
446
{
441
- DMA_INTC = DMA_INTC_GIFC << (0x2 * 4 );
447
+ DMA_INTC = DMA_INTF_FTFIF << (0x2 * 4 );
442
448
if (vsfhal_usart_onrx [0 ])
443
449
vsfhal_usart_onrx [0 ](vsfhal_usart_callback_param [0 ]);
444
450
}
@@ -448,9 +454,6 @@ ROOT void DMA_Channel1_2_IRQHandler(void)
448
454
// used for usart1 tx/rx
449
455
ROOT void DMA_Channel3_4_IRQHandler (void )
450
456
{
451
- DMA_INTC = (DMA_INTC_GIFC << (3 * 4 )) | (DMA_INTC_GIFC << (4 * 4 ));
452
- usart1_dma_handler ();
453
-
454
457
// tx dma
455
458
if (DMA_INTF & (DMA_INTF_GIF << (0x3 * 4 )))
456
459
{
@@ -471,9 +474,17 @@ void gd32f3x0_usart1_poll(void)
471
474
{
472
475
uint16_t dma_pos ;
473
476
474
- dma_pos = VSFHAL_USART_NUM * 2 - DMA_CH4CNT ;
475
- if ((dma_pos != rx_dma_buff_pos [1 ]) && vsfhal_usart_onrx [1 ])
476
- vsfhal_usart_onrx [1 ](vsfhal_usart_callback_param [1 ]);
477
+ if (DMA_CH4CTL & DMA_CHXCTL_CHEN )
478
+ {
479
+ istate_t gint = GET_GLOBAL_INTERRUPT_STATE ();
480
+ DISABLE_GLOBAL_INTERRUPT ();
481
+
482
+ dma_pos = DMA_BUFF_SIZE * 2 - DMA_CH4CNT ;
483
+ if ((dma_pos != rx_dma_buff_pos [1 ]) && vsfhal_usart_onrx [1 ])
484
+ vsfhal_usart_onrx [1 ](vsfhal_usart_callback_param [1 ]);
485
+
486
+ SET_GLOBAL_INTERRUPT_STATE (gint );
487
+ }
477
488
}
478
489
#endif
479
490
0 commit comments