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Cache question #227

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wbs12138 opened this issue Feb 12, 2025 · 0 comments
Open

Cache question #227

wbs12138 opened this issue Feb 12, 2025 · 0 comments

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@wbs12138
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Dear:
The article(Vortex: Extending the RISC-V ISA for GPGPU and 3D-Graphics Research) mentioned about the virtual port assignment to coalesce requests that map to the same bank and the same cache line. However i donot find any codes about it in related source code files. So I wonder in which part you team achieve it.
Yours sincerely.
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