Merge pull request The-OpenROAD-Project#2050 from The-OpenROAD-Projec…

…t-staging/secure-yosys0.42 update Yosys submodule to version 0.42
vvbandeira · Jun 9, 2024 · a078960 · a078960
2 parents c1a0f94 + 673fda2
commit a078960
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diff --git a/tools/OpenROAD b/tools/OpenROAD
diff --git a/tools/yosys b/tools/yosys
+117 −115		src/ant/include/ant/AntennaChecker.hh
+768 −1,795		src/ant/src/AntennaChecker.cc
+1 −1		src/ant/src/AntennaChecker.i
+1 −0		src/ant/src/CMakeLists.txt
+73 −0		src/ant/src/PinType.hh
+129 −0		src/ant/src/Polygon.cc
+75 −0		src/ant/src/Polygon.hh
+57 −75		src/ant/test/ant_check.ok
+14 −11		src/ant/test/ant_report.rptok
+56 −74		src/ant/test/check_api1.ok
+56 −74		src/ant/test/check_drt1.ok
+270 −350		src/ant/test/check_grt1.ok
+0 −19		src/dft/test/cpp_tests.ok
+0 −46		src/dft/test/cpp_tests.tcl
+0 −1		src/grt/src/RepairAntennas.cpp
+19 −21		src/grt/test/repair_antennas4.ok
+136 −108		src/gui/src/chartsWidget.cpp
+20 −17		src/gui/src/chartsWidget.h
+32 −22		src/mpl2/src/graphics.cpp
+2 −2		src/mpl2/src/graphics.h
+82 −65		src/mpl2/src/hier_rtlmp.cpp
+0 −4		src/mpl2/src/hier_rtlmp.h
+2 −4		src/mpl2/src/mpl.i
+2 −1		src/mpl2/src/mpl.tcl
+11 −27		src/mpl2/src/object.cpp
+16 −27		src/mpl2/src/object.h
+7 −7		src/mpl2/src/rtl_mp.cpp
+51 −49		test/ibex_sky130hs.metrics
+6 −6		test/ibex_sky130hs.metrics_limits
+55 −0		.github/ISSUE_TEMPLATE/docs_report.yml
+5 −0		.github/PULL_REQUEST_TEMPLATE.md
+33 −0		.github/actions/setup-build-env/action.yml
+2 −1		.github/workflows/codeql.yml
+0 −18		.github/workflows/emcc.yml
+97 −0		.github/workflows/extra-builds.yml
+181 −0		.github/workflows/test-build.yml
+79 −0		.github/workflows/test-compile.yml
+0 −42		.github/workflows/test-docs.yml
+0 −130		.github/workflows/test-linux.yml
+0 −75		.github/workflows/test-macos.yml
+19 −1		.github/workflows/test-verific.yml
+22 −0		.github/workflows/update-flake-lock.yml
+1 −0		.github/workflows/version.yml
+0 −31		.github/workflows/vs.yml
+0 −30		.github/workflows/wasi.yml
+1 −1		.gitignore
+3 −0		.gitmodules
+9 −0		CHANGELOG
+52 −102		Makefile
+1 −0		abc
+1 −0		backends/cxxrtl/cxxrtl_backend.cc
+5 −0		backends/smt2/smtbmc.py
+14 −0		docs/source/_static/yosyshq.css
+4 −4		docs/source/appendix/primer.rst
+1 −1		docs/source/conf.py
+16 −16		docs/source/getting_started/example_synth.rst
+3 −3		docs/source/getting_started/scripting_intro.rst
+1 −1		docs/source/introduction.rst
+12 −12		docs/source/using_yosys/more_scripting/interactive_investigation.rst
+13 −13		docs/source/using_yosys/more_scripting/selections.rst
+4 −4		docs/source/using_yosys/synthesis/cell_libs.rst
+20 −20		docs/source/using_yosys/synthesis/extract.rst
+2 −2		docs/source/using_yosys/synthesis/memory.rst
+4 −4		docs/source/using_yosys/synthesis/opt.rst
+3 −3		docs/source/using_yosys/synthesis/proc.rst
+2 −2		docs/source/yosys_internals/extending_yosys/extensions.rst
+1 −1		docs/source/yosys_internals/flow/control_and_data.rst
+1 −1		docs/source/yosys_internals/flow/overview.rst
+1 −1		docs/source/yosys_internals/flow/verilog_frontend.rst
+46 −2		docs/source/yosys_internals/formats/cell_library.rst
+1 −1		docs/source/yosys_internals/formats/rtlil_rep.rst
+5 −5		docs/source/yosys_internals/techmap.rst
+3 −2		docs/tests/macro_commands.py
+61 −0		flake.lock
+48 −0		flake.nix
+10 −2		frontends/verific/verific.cc
+1 −0		passes/cmds/Makefile.inc
+116 −0		passes/cmds/box_derive.cc
+33 −5		passes/cmds/logcmd.cc
+30 −11		passes/cmds/select.cc
+0 −3		techlibs/intel_alm/Makefile.inc
+1 −413		techlibs/intel_alm/common/alm_sim.v
+0 −33		techlibs/intel_alm/common/bram_m20k.txt
+0 −31		techlibs/intel_alm/common/bram_m20k_map.v
+0 −32		techlibs/intel_alm/common/dff_sim.v
+5 −51		techlibs/intel_alm/common/mem_sim.v
+0 −311		techlibs/intel_alm/common/quartus_rename.v
+10 −71		techlibs/intel_alm/synth_intel_alm.cc
+0 −9		tests/arch/intel_alm/add_sub.ys
+0 −46		tests/arch/intel_alm/adffs.ys
+1 −0		tests/arch/intel_alm/blockram.ys
+0 −14		tests/arch/intel_alm/counter.ys
+0 −22		tests/arch/intel_alm/dffs.ys
+0 −22		tests/arch/intel_alm/fsm.ys
+0 −13		tests/arch/intel_alm/logic.ys
+1 −0		tests/arch/intel_alm/lutram.ys
+0 −25		tests/arch/intel_alm/mul.ys
+0 −43		tests/arch/intel_alm/mux.ys
+0 −26		tests/arch/intel_alm/quartus_ice.ys
+0 −11		tests/arch/intel_alm/shifter.ys
+0 −14		tests/arch/intel_alm/tribuf.ys
+53 −0		tests/various/box_derive.ys