WorkLoad Optimize SOC (WLOS) Final Project

Simulation for FIR, Matrix Mult,qsort,uart(without FIFO)

cd /testbench/comb
source run_clean
source run_sim

Simualtion for UART(with FIFO)

cd /testbench/uart
source run_clean
source run_sim

Verification with Vivado

Synthesis and Generate bitstream

cd /lab-wlos_baseline/vivado
source run_vivado