From 6e046c5f7619a530106fc9d55d017cbc18c49868 Mon Sep 17 00:00:00 2001
From: Catherine <whitequark@whitequark.org>
Date: Wed, 3 Apr 2024 08:11:31 +0000
Subject: [PATCH] write_verilog: don't `assign` to a `reg`.

Fixes #2035.
---
 tests/simple/.gitignore        |  1 +
 tests/verilog/.gitignore       |  4 ++++
 tests/verilog/assign_to_reg.ys | 22 ++++++++++++++++++++++
 3 files changed, 27 insertions(+)
 create mode 100644 tests/verilog/assign_to_reg.ys

diff --git a/tests/simple/.gitignore b/tests/simple/.gitignore
index 073f46157e1..5daaadbd734 100644
--- a/tests/simple/.gitignore
+++ b/tests/simple/.gitignore
@@ -1,2 +1,3 @@
 *.log
 *.out
+*.err
diff --git a/tests/verilog/.gitignore b/tests/verilog/.gitignore
index 96ebe20ba26..cfd72076e4e 100644
--- a/tests/verilog/.gitignore
+++ b/tests/verilog/.gitignore
@@ -1,6 +1,10 @@
 /*.log
 /*.out
+/*.err
 /run-test.mk
 /const_arst.v
 /const_sr.v
 /doubleslash.v
+/roundtrip_proc_1.v
+/roundtrip_proc_2.v
+/assign_to_reg.v
diff --git a/tests/verilog/assign_to_reg.ys b/tests/verilog/assign_to_reg.ys
new file mode 100644
index 00000000000..80080e9f372
--- /dev/null
+++ b/tests/verilog/assign_to_reg.ys
@@ -0,0 +1,22 @@
+# https://github.com/yosyshq/yosys/issues/2035
+
+read_ilang <<END
+module \top
+  wire width 1 input 0 \halfbrite
+  wire width 2 output 1 \r_on
+  process $1
+    assign \r_on [1:0] 2'00
+    assign \r_on [1:0] 2'11
+    switch \halfbrite [0]
+      case 1'1
+        assign \r_on [1] 1'0
+    end
+  end
+end
+END
+proc_prune
+write_verilog assign_to_reg.v
+design -reset
+
+logger -expect-no-warnings
+read_verilog assign_to_reg.v