From 5604d19485beb4d4d763eb300f1a50bd20a74608 Mon Sep 17 00:00:00 2001 From: GitHub Action Date: Tue, 6 Feb 2024 15:06:52 +0000 Subject: [PATCH] ci update Rift2330 --- generated/Debug/Rift2330/Rift2Chip.anno.json | 12543 +++++++---------- generated/Debug/Rift2330/coremark.json | 2 +- generated/Debug/Rift2330/dhrystone.json | 2 +- 3 files changed, 4845 insertions(+), 7702 deletions(-) diff --git a/generated/Debug/Rift2330/Rift2Chip.anno.json b/generated/Debug/Rift2330/Rift2Chip.anno.json index 83b2353e..08994bf9 100644 --- a/generated/Debug/Rift2330/Rift2Chip.anno.json +++ b/generated/Debug/Rift2330/Rift2Chip.anno.json @@ -1,7890 +1,5033 @@ [ { - "class":"firrtl.transforms.DedupedResult", - "original":"~Rift2Chip|DatRAM", - "duplicate":"~Rift2Chip|Rift2Chip/i_rift2Core:Rift2Core/if2:IF2/datRAM_0:DatRAM", - "index":0.00539568345323741 - }, - { - "class":"firrtl.transforms.DedupedResult", - "original":"~Rift2Chip|TagRAM", - "duplicate":"~Rift2Chip|Rift2Chip/i_rift2Core:Rift2Core/if2:IF2/tagRAM_0:TagRAM", - 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"index":0.3920863309352518 + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~Rift2Chip|Issue>bufReqNum" }, { - "class":"firrtl.transforms.DedupedResult", - "original":"~Rift2Chip|AsyncValidSync_15", - "duplicate":"~Rift2Chip|Rift2Chip/i_debugger:Debugger/dmi:DMI/req_ToAsync_source:AsyncQueueSource/sink_valid:AsyncValidSync", - "index":0.39388489208633093 + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~Rift2Chip|Issue>bufReqNum" }, { - "class":"firrtl.transforms.DedupedResult", - "original":"~Rift2Chip|AsyncQueueSource_1", - "duplicate":"~Rift2Chip|Rift2Chip/i_debugger:Debugger/dmi:DMI/req_ToAsync_source:AsyncQueueSource", - "index":0.39568345323741005 + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~Rift2Chip|Issue>bufReqNum" }, { - "class":"firrtl.transforms.DedupedResult", - "original":"~Rift2Chip|plusarg_reader_2", - "duplicate":"~Rift2Chip|Rift2Chip/i_aclint:AClint/monitor:TLMonitor_1/plusarg_reader:plusarg_reader", - "index":0.4010791366906475 + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~Rift2Chip|Issue>bufReqNum" }, { - "class":"firrtl.transforms.DedupedResult", - "original":"~Rift2Chip|plusarg_reader_3", - "duplicate":"~Rift2Chip|Rift2Chip/i_aclint:AClint/monitor:TLMonitor_1/plusarg_reader_1:plusarg_reader", - "index":0.4028776978417266 + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~Rift2Chip|SRT4Divider>dividendIdx" }, { - "class":"firrtl.transforms.DedupedResult", - "original":"~Rift2Chip|plusarg_reader_4", - "duplicate":"~Rift2Chip|Rift2Chip/i_plic:Plic/monitor:TLMonitor_2/plusarg_reader:plusarg_reader", - "index":0.40827338129496404 + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~Rift2Chip|diff>io" }, { - "class":"firrtl.transforms.DedupedResult", - "original":"~Rift2Chip|plusarg_reader_5", - "duplicate":"~Rift2Chip|Rift2Chip/i_plic:Plic/monitor:TLMonitor_2/plusarg_reader_1:plusarg_reader", - "index":0.41007194244604317 + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~Rift2Chip|diff>XReg" }, { - "class":"firrtl.transforms.DedupedResult", - "original":"~Rift2Chip|plusarg_reader_6", - "duplicate":"~Rift2Chip|Rift2Chip/sifiveCache:InclusiveCache/monitor:TLMonitor_3/plusarg_reader:plusarg_reader", - "index":0.4172661870503597 + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~Rift2Chip|diff>FReg1" }, { - "class":"firrtl.transforms.DedupedResult", - "original":"~Rift2Chip|plusarg_reader_7", - "duplicate":"~Rift2Chip|Rift2Chip/sifiveCache:InclusiveCache/monitor:TLMonitor_3/plusarg_reader_1:plusarg_reader", - "index":0.41906474820143885 + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~Rift2Chip|diff>FReg2" }, { - "class":"firrtl.transforms.DedupedResult", - "original":"~Rift2Chip|MSHR", - "duplicate":"~Rift2Chip|Rift2Chip/sifiveCache:InclusiveCache/inclusive_cache_bank_sched:InclusiveCacheBankScheduler/abc_mshrs_0:MSHR", - "index":0.47302158273381295 + "class":"firrtl.transforms.BlackBoxInlineAnno", + "target":"Rift2Chip.plusarg_reader", + "name":"plusarg_reader.v", + "text":"// See LICENSE.SiFive for license details.\n\n//VCS coverage exclude_file\n\n// No default parameter values are intended, nor does IEEE 1800-2012 require them (clause A.2.4 param_assignment),\n// but Incisive demands them. These default values should never be used.\nmodule plusarg_reader #(\n parameter FORMAT=\"borked=%d\",\n parameter WIDTH=1,\n parameter [WIDTH-1:0] DEFAULT=0\n) (\n output [WIDTH-1:0] out\n);\n\n`ifdef SYNTHESIS\nassign out = DEFAULT;\n`else\nreg [WIDTH-1:0] myplus;\nassign out = myplus;\n\ninitial begin\n if (!$value$plusargs(FORMAT, myplus)) myplus = DEFAULT;\nend\n`endif\n\nendmodule\n" }, { - "class":"firrtl.transforms.DedupedResult", - "original":"~Rift2Chip|MSHR_1", - "duplicate":"~Rift2Chip|Rift2Chip/sifiveCache:InclusiveCache/inclusive_cache_bank_sched:InclusiveCacheBankScheduler/abc_mshrs_1:MSHR", - "index":0.4748201438848921 + "class":"firrtl.transforms.BlackBoxInlineAnno", + "target":"Rift2Chip.plusarg_reader_1", + "name":"plusarg_reader.v", + "text":"// See LICENSE.SiFive for license details.\n\n//VCS coverage exclude_file\n\n// No default parameter values are intended, nor does IEEE 1800-2012 require them (clause A.2.4 param_assignment),\n// but Incisive demands them. These default values should never be used.\nmodule plusarg_reader #(\n parameter FORMAT=\"borked=%d\",\n parameter WIDTH=1,\n parameter [WIDTH-1:0] DEFAULT=0\n) (\n output [WIDTH-1:0] out\n);\n\n`ifdef SYNTHESIS\nassign out = DEFAULT;\n`else\nreg [WIDTH-1:0] myplus;\nassign out = myplus;\n\ninitial begin\n if (!$value$plusargs(FORMAT, myplus)) myplus = DEFAULT;\nend\n`endif\n\nendmodule\n" }, { - "class":"firrtl.transforms.DedupedResult", - "original":"~Rift2Chip|MSHR_2", - "duplicate":"~Rift2Chip|Rift2Chip/sifiveCache:InclusiveCache/inclusive_cache_bank_sched:InclusiveCacheBankScheduler/abc_mshrs_2:MSHR", - "index":0.4766187050359712 + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~Rift2Chip|DebugModule>abstractDataMem_wen1" }, { - "class":"firrtl.transforms.DedupedResult", - "original":"~Rift2Chip|MSHR_3", - "duplicate":"~Rift2Chip|Rift2Chip/sifiveCache:InclusiveCache/inclusive_cache_bank_sched:InclusiveCacheBankScheduler/abc_mshrs_3:MSHR", - "index":0.4784172661870504 + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~Rift2Chip|DebugModule>abstractDataMem_ren1" }, { - "class":"firrtl.transforms.DedupedResult", - "original":"~Rift2Chip|MSHR_4", - "duplicate":"~Rift2Chip|Rift2Chip/sifiveCache:InclusiveCache/inclusive_cache_bank_sched:InclusiveCacheBankScheduler/abc_mshrs_4:MSHR", - "index":0.4802158273381295 + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~Rift2Chip|DebugModule>programBufferMem_wen1" }, { - "class":"firrtl.transforms.DedupedResult", - "original":"~Rift2Chip|MSHR_5", - "duplicate":"~Rift2Chip|Rift2Chip/sifiveCache:InclusiveCache/inclusive_cache_bank_sched:InclusiveCacheBankScheduler/abc_mshrs_5:MSHR", - "index":0.48201438848920863 + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~Rift2Chip|DebugModule>programBufferMem_ren1" }, { - "class":"firrtl.transforms.DedupedResult", - "original":"~Rift2Chip|MSHR_6", - "duplicate":"~Rift2Chip|Rift2Chip/sifiveCache:InclusiveCache/inclusive_cache_bank_sched:InclusiveCacheBankScheduler/abc_mshrs_6:MSHR", - "index":0.48381294964028776 - }, - { - "class":"firrtl.transforms.DedupedResult", - "original":"~Rift2Chip|MSHR_7", - "duplicate":"~Rift2Chip|Rift2Chip/sifiveCache:InclusiveCache/inclusive_cache_bank_sched:InclusiveCacheBankScheduler/abc_mshrs_7:MSHR", - "index":0.4856115107913669 - }, - { - "class":"firrtl.transforms.DedupedResult", - "original":"~Rift2Chip|MSHR_8", - "duplicate":"~Rift2Chip|Rift2Chip/sifiveCache:InclusiveCache/inclusive_cache_bank_sched:InclusiveCacheBankScheduler/abc_mshrs_8:MSHR", - "index":0.48741007194244607 - }, - { - "class":"firrtl.transforms.DedupedResult", - "original":"~Rift2Chip|MSHR_9", - "duplicate":"~Rift2Chip|Rift2Chip/sifiveCache:InclusiveCache/inclusive_cache_bank_sched:InclusiveCacheBankScheduler/abc_mshrs_9:MSHR", - "index":0.4892086330935252 - }, - { - "class":"firrtl.transforms.DedupedResult", - "original":"~Rift2Chip|MSHR_10", - "duplicate":"~Rift2Chip|Rift2Chip/sifiveCache:InclusiveCache/inclusive_cache_bank_sched:InclusiveCacheBankScheduler/abc_mshrs_10:MSHR", - "index":0.4910071942446043 - }, - { - "class":"firrtl.transforms.DedupedResult", - "original":"~Rift2Chip|MSHR_11", - "duplicate":"~Rift2Chip|Rift2Chip/sifiveCache:InclusiveCache/inclusive_cache_bank_sched:InclusiveCacheBankScheduler/abc_mshrs_11:MSHR", - "index":0.49280575539568344 - }, - { - "class":"firrtl.transforms.DedupedResult", - "original":"~Rift2Chip|MSHR_12", - "duplicate":"~Rift2Chip|Rift2Chip/sifiveCache:InclusiveCache/inclusive_cache_bank_sched:InclusiveCacheBankScheduler/abc_mshrs_12:MSHR", - "index":0.49460431654676257 - }, - { - "class":"firrtl.transforms.DedupedResult", - "original":"~Rift2Chip|MSHR_13", - "duplicate":"~Rift2Chip|Rift2Chip/sifiveCache:InclusiveCache/inclusive_cache_bank_sched:InclusiveCacheBankScheduler/abc_mshrs_13:MSHR", - "index":0.49640287769784175 - }, - { - "class":"firrtl.transforms.DedupedResult", - "original":"~Rift2Chip|MSHR_14", - "duplicate":"~Rift2Chip|Rift2Chip/sifiveCache:InclusiveCache/inclusive_cache_bank_sched:InclusiveCacheBankScheduler/abc_mshrs_14:MSHR", - "index":0.4982014388489209 - }, - { - "class":"firrtl.transforms.DedupedResult", - "original":"~Rift2Chip|MSHR_15", - "duplicate":"~Rift2Chip|Rift2Chip/sifiveCache:InclusiveCache/inclusive_cache_bank_sched:InclusiveCacheBankScheduler/abc_mshrs_15:MSHR", - "index":0.5 - }, - { - "class":"firrtl.transforms.DedupedResult", - "original":"~Rift2Chip|MSHR_16", - "duplicate":"~Rift2Chip|Rift2Chip/sifiveCache:InclusiveCache/inclusive_cache_bank_sched:InclusiveCacheBankScheduler/abc_mshrs_16:MSHR", - "index":0.5017985611510791 - }, - { - "class":"firrtl.transforms.DedupedResult", - "original":"~Rift2Chip|MSHR_17", - "duplicate":"~Rift2Chip|Rift2Chip/sifiveCache:InclusiveCache/inclusive_cache_bank_sched:InclusiveCacheBankScheduler/abc_mshrs_17:MSHR", - "index":0.5035971223021583 - }, - { - "class":"firrtl.transforms.DedupedResult", - "original":"~Rift2Chip|MSHR_18", - "duplicate":"~Rift2Chip|Rift2Chip/sifiveCache:InclusiveCache/inclusive_cache_bank_sched:InclusiveCacheBankScheduler/abc_mshrs_18:MSHR", - "index":0.5053956834532374 - }, - { - "class":"firrtl.transforms.DedupedResult", - "original":"~Rift2Chip|MSHR_19", - "duplicate":"~Rift2Chip|Rift2Chip/sifiveCache:InclusiveCache/inclusive_cache_bank_sched:InclusiveCacheBankScheduler/abc_mshrs_19:MSHR", - "index":0.5071942446043165 - }, - { - "class":"firrtl.transforms.DedupedResult", - "original":"~Rift2Chip|MSHR_20", - "duplicate":"~Rift2Chip|Rift2Chip/sifiveCache:InclusiveCache/inclusive_cache_bank_sched:InclusiveCacheBankScheduler/bc_mshr:MSHR", - "index":0.5089928057553957 - }, - { - "class":"firrtl.transforms.DedupedResult", - "original":"~Rift2Chip|MSHR_21", - "duplicate":"~Rift2Chip|Rift2Chip/sifiveCache:InclusiveCache/inclusive_cache_bank_sched:InclusiveCacheBankScheduler/c_mshr:MSHR", - "index":0.5107913669064749 - }, - { - "class":"firrtl.transforms.DedupedResult", - "original":"~Rift2Chip|plusarg_reader_8", - "duplicate":"~Rift2Chip|Rift2Chip/xbar:TLXbar/monitor:TLMonitor_4/plusarg_reader:plusarg_reader", - "index":0.5161870503597122 - }, - { - "class":"firrtl.transforms.DedupedResult", - "original":"~Rift2Chip|plusarg_reader_9", - "duplicate":"~Rift2Chip|Rift2Chip/xbar:TLXbar/monitor:TLMonitor_4/plusarg_reader_1:plusarg_reader", - "index":0.5179856115107914 - }, - { - "class":"firrtl.transforms.DedupedResult", - "original":"~Rift2Chip|plusarg_reader_10", - "duplicate":"~Rift2Chip|Rift2Chip/xbar:TLXbar/monitor_1:TLMonitor_5/plusarg_reader:plusarg_reader", - "index":0.5215827338129496 - }, - { - "class":"firrtl.transforms.DedupedResult", - "original":"~Rift2Chip|plusarg_reader_11", - "duplicate":"~Rift2Chip|Rift2Chip/xbar:TLXbar/monitor_1:TLMonitor_5/plusarg_reader_1:plusarg_reader", - "index":0.5233812949640287 - }, - { - "class":"firrtl.transforms.DedupedResult", - "original":"~Rift2Chip|plusarg_reader_12", - "duplicate":"~Rift2Chip|Rift2Chip/xbar_1:TLXbar_1/monitor:TLMonitor_6/plusarg_reader:plusarg_reader", - "index":0.5287769784172662 - }, - { - "class":"firrtl.transforms.DedupedResult", - "original":"~Rift2Chip|plusarg_reader_13", - "duplicate":"~Rift2Chip|Rift2Chip/xbar_1:TLXbar_1/monitor:TLMonitor_6/plusarg_reader_1:plusarg_reader", - "index":0.5305755395683454 - }, - { - "class":"firrtl.transforms.DedupedResult", - "original":"~Rift2Chip|plusarg_reader_14", - "duplicate":"~Rift2Chip|Rift2Chip/xbar_1:TLXbar_1/monitor_1:TLMonitor_7/plusarg_reader:plusarg_reader", - "index":0.5341726618705036 - }, - { - "class":"firrtl.transforms.DedupedResult", - "original":"~Rift2Chip|plusarg_reader_15", - "duplicate":"~Rift2Chip|Rift2Chip/xbar_1:TLXbar_1/monitor_1:TLMonitor_7/plusarg_reader_1:plusarg_reader", - "index":0.5359712230215827 - }, - { - "class":"firrtl.transforms.DedupedResult", - "original":"~Rift2Chip|plusarg_reader_16", - "duplicate":"~Rift2Chip|Rift2Chip/xbar_2:TLXbar_2/monitor:TLMonitor_8/plusarg_reader:plusarg_reader", - "index":0.5413669064748201 - }, - { - "class":"firrtl.transforms.DedupedResult", - "original":"~Rift2Chip|plusarg_reader_17", - "duplicate":"~Rift2Chip|Rift2Chip/xbar_2:TLXbar_2/monitor:TLMonitor_8/plusarg_reader_1:plusarg_reader", - "index":0.5431654676258992 - }, - { - "class":"firrtl.transforms.DedupedResult", - "original":"~Rift2Chip|plusarg_reader_18", - "duplicate":"~Rift2Chip|Rift2Chip/xbar_2:TLXbar_2/monitor_1:TLMonitor_9/plusarg_reader:plusarg_reader", - "index":0.5467625899280576 - }, - { - "class":"firrtl.transforms.DedupedResult", - "original":"~Rift2Chip|plusarg_reader_19", - "duplicate":"~Rift2Chip|Rift2Chip/xbar_2:TLXbar_2/monitor_1:TLMonitor_9/plusarg_reader_1:plusarg_reader", - "index":0.5485611510791367 - }, - { - "class":"firrtl.transforms.DedupedResult", - "original":"~Rift2Chip|plusarg_reader_20", - "duplicate":"~Rift2Chip|Rift2Chip/xbar_2:TLXbar_2/monitor_2:TLMonitor_10/plusarg_reader:plusarg_reader", - "index":0.552158273381295 - }, - { - "class":"firrtl.transforms.DedupedResult", - "original":"~Rift2Chip|plusarg_reader_21", - "duplicate":"~Rift2Chip|Rift2Chip/xbar_2:TLXbar_2/monitor_2:TLMonitor_10/plusarg_reader_1:plusarg_reader", - "index":0.5539568345323741 - }, - { - "class":"firrtl.transforms.DedupedResult", - "original":"~Rift2Chip|plusarg_reader_22", - "duplicate":"~Rift2Chip|Rift2Chip/xbar_2:TLXbar_2/monitor_3:TLMonitor_11/plusarg_reader:plusarg_reader", - "index":0.5575539568345323 - }, - { - "class":"firrtl.transforms.DedupedResult", - "original":"~Rift2Chip|plusarg_reader_23", - "duplicate":"~Rift2Chip|Rift2Chip/xbar_2:TLXbar_2/monitor_3:TLMonitor_11/plusarg_reader_1:plusarg_reader", - "index":0.5593525179856115 - }, - { - "class":"firrtl.transforms.DedupedResult", - "original":"~Rift2Chip|plusarg_reader_24", - "duplicate":"~Rift2Chip|Rift2Chip/xbar_3:TLXbar_3/monitor:TLMonitor_12/plusarg_reader:plusarg_reader", - "index":0.564748201438849 - }, - { - "class":"firrtl.transforms.DedupedResult", - "original":"~Rift2Chip|plusarg_reader_25", - "duplicate":"~Rift2Chip|Rift2Chip/xbar_3:TLXbar_3/monitor:TLMonitor_12/plusarg_reader_1:plusarg_reader", - "index":0.5665467625899281 - }, - { - "class":"firrtl.transforms.DedupedResult", - "original":"~Rift2Chip|plusarg_reader_26", - "duplicate":"~Rift2Chip|Rift2Chip/xbar_3:TLXbar_3/monitor_1:TLMonitor_13/plusarg_reader:plusarg_reader", - "index":0.5701438848920863 - }, - { - "class":"firrtl.transforms.DedupedResult", - "original":"~Rift2Chip|plusarg_reader_27", - "duplicate":"~Rift2Chip|Rift2Chip/xbar_3:TLXbar_3/monitor_1:TLMonitor_13/plusarg_reader_1:plusarg_reader", - "index":0.5719424460431655 - }, - { - "class":"firrtl.transforms.DedupedResult", - "original":"~Rift2Chip|Queue_42", - "duplicate":"~Rift2Chip|Rift2Chip/axi4yank:AXI4UserYanker/Queue:Queue_42", - "index":0.5773381294964028 - }, - { - "class":"firrtl.transforms.DedupedResult", - "original":"~Rift2Chip|Queue_43", - "duplicate":"~Rift2Chip|Rift2Chip/axi4yank:AXI4UserYanker/Queue_1:Queue_42", - "index":0.579136690647482 - }, - { - "class":"firrtl.transforms.DedupedResult", - "original":"~Rift2Chip|Queue_44", - "duplicate":"~Rift2Chip|Rift2Chip/axi4yank:AXI4UserYanker/Queue_2:Queue_42", - "index":0.5809352517985612 - }, - { - "class":"firrtl.transforms.DedupedResult", - "original":"~Rift2Chip|Queue_45", - "duplicate":"~Rift2Chip|Rift2Chip/axi4yank:AXI4UserYanker/Queue_3:Queue_42", - "index":0.5827338129496403 - }, - { - "class":"firrtl.transforms.DedupedResult", - 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"index":0.9676258992805755 - }, - { - "class":"firrtl.transforms.DedupedResult", - "original":"~Rift2Chip|plusarg_reader_65", - "duplicate":"~Rift2Chip|Rift2Chip/buffer_13:TLBuffer_13/monitor:TLMonitor_32/plusarg_reader_1:plusarg_reader", - "index":0.9694244604316546 - }, - { - "class":"firrtl.transforms.DedupedResult", - "original":"~Rift2Chip|plusarg_reader_66", - "duplicate":"~Rift2Chip|Rift2Chip/buffer_14:TLBuffer_14/monitor:TLMonitor_33/plusarg_reader:plusarg_reader", - "index":0.9784172661870504 - }, - { - "class":"firrtl.transforms.DedupedResult", - "original":"~Rift2Chip|plusarg_reader_67", - "duplicate":"~Rift2Chip|Rift2Chip/buffer_14:TLBuffer_14/monitor:TLMonitor_33/plusarg_reader_1:plusarg_reader", - "index":0.9802158273381295 - }, - { - "class":"firrtl.transforms.DedupedResult", - "original":"~Rift2Chip|Queue_178", - "duplicate":"~Rift2Chip|Rift2Chip/buffer_14:TLBuffer_14/bundleIn_0_d_q:Queue_178", - "index":0.9856115107913669 - }, - { - "class":"firrtl.transforms.DedupedResult", - "original":"~Rift2Chip|plusarg_reader_68", - "duplicate":"~Rift2Chip|Rift2Chip/buffer_15:TLBuffer_15/monitor:TLMonitor_34/plusarg_reader:plusarg_reader", - "index":0.9892086330935251 - }, - { - "class":"firrtl.transforms.DedupedResult", - "original":"~Rift2Chip|plusarg_reader_69", - "duplicate":"~Rift2Chip|Rift2Chip/buffer_15:TLBuffer_15/monitor:TLMonitor_34/plusarg_reader_1:plusarg_reader", - "index":0.9910071942446043 - }, - { - "class":"firrtl.transforms.DedupedResult", - "original":"~Rift2Chip|Queue_180", - "duplicate":"~Rift2Chip|Rift2Chip/buffer_15:TLBuffer_15/bundleIn_0_d_q:Queue_178", - "index":0.9964028776978417 - }, - { - "class":"firrtl.EmitAllModulesAnnotation", - "emitter":"firrtl.VerilogEmitter" - }, - { - "class":"firrtl.transforms.BlackBoxInlineAnno", - "target":"Rift2Chip.plusarg_reader", - "name":"plusarg_reader.v", - "text":"// See LICENSE.SiFive for license details.\n\n//VCS coverage exclude_file\n\n// No default parameter values are intended, nor does IEEE 1800-2012 require them (clause A.2.4 param_assignment),\n// but Incisive demands them. These default values should never be used.\nmodule plusarg_reader #(\n parameter FORMAT=\"borked=%d\",\n parameter WIDTH=1,\n parameter [WIDTH-1:0] DEFAULT=0\n) (\n output [WIDTH-1:0] out\n);\n\n`ifdef SYNTHESIS\nassign out = DEFAULT;\n`else\nreg [WIDTH-1:0] myplus;\nassign out = myplus;\n\ninitial begin\n if (!$value$plusargs(FORMAT, myplus)) myplus = DEFAULT;\nend\n`endif\n\nendmodule\n" - }, - { - "class":"firrtl.passes.InlineAnnotation", - "target":"Rift2Chip.TLWidthWidget_3" - }, - { - "class":"firrtl.passes.InlineAnnotation", - "target":"Rift2Chip.TLWidthWidget_2" - }, - { - "class":"firrtl.passes.InlineAnnotation", - "target":"Rift2Chip.TLWidthWidget_1" - }, - { - "class":"freechips.rocketchip.util.SRAMAnnotation", - "target":"Rift2Chip.BankedStore.cc_banks_3", - "address_width":13, - "name":"cc_banks_3", - "data_width":64, - "depth":8192, - "description":"Banked Store", - "write_mask_granularity":64 - }, - { - "class":"freechips.rocketchip.util.SRAMAnnotation", - "target":"Rift2Chip.BankedStore.cc_banks_2", - "address_width":13, - "name":"cc_banks_2", - "data_width":64, - "depth":8192, - "description":"Banked Store", - "write_mask_granularity":64 - }, - { - "class":"freechips.rocketchip.util.SRAMAnnotation", - "target":"Rift2Chip.BankedStore.cc_banks_1", - "address_width":13, - "name":"cc_banks_1", - "data_width":64, - "depth":8192, - "description":"Banked Store", - "write_mask_granularity":64 - }, - { - "class":"freechips.rocketchip.util.SRAMAnnotation", - "target":"Rift2Chip.BankedStore.cc_banks_0", - "address_width":13, - "name":"cc_banks_0", - "data_width":64, - "depth":8192, - "description":"Banked Store", - "write_mask_granularity":64 - }, - { - "class":"freechips.rocketchip.util.SRAMAnnotation", - "target":"Rift2Chip.Directory.cc_dir_0", - "address_width":11, - "name":"cc_dir", - "data_width":160, - "depth":2048, - "description":"Directory RAM", - "write_mask_granularity":20 - }, - { - "class":"freechips.rocketchip.util.SRAMAnnotation", - "target":"Rift2Chip.Directory.cc_dir_1", - "address_width":11, - "name":"cc_dir", - "data_width":160, - "depth":2048, - "description":"Directory RAM", - "write_mask_granularity":20 - }, - { - "class":"freechips.rocketchip.util.SRAMAnnotation", - "target":"Rift2Chip.Directory.cc_dir_2", - "address_width":11, - "name":"cc_dir", - "data_width":160, - "depth":2048, - "description":"Directory RAM", - "write_mask_granularity":20 - }, - { - "class":"freechips.rocketchip.util.SRAMAnnotation", - "target":"Rift2Chip.Directory.cc_dir_3", - "address_width":11, - "name":"cc_dir", - "data_width":160, - "depth":2048, - "description":"Directory RAM", - "write_mask_granularity":20 - }, - { - "class":"freechips.rocketchip.util.SRAMAnnotation", - "target":"Rift2Chip.Directory.cc_dir_4", - "address_width":11, - "name":"cc_dir", - "data_width":160, - "depth":2048, - "description":"Directory RAM", - "write_mask_granularity":20 - }, - { - "class":"freechips.rocketchip.util.SRAMAnnotation", - "target":"Rift2Chip.Directory.cc_dir_5", - "address_width":11, - "name":"cc_dir", - "data_width":160, - "depth":2048, - "description":"Directory RAM", - "write_mask_granularity":20 - }, - { - "class":"freechips.rocketchip.util.SRAMAnnotation", - "target":"Rift2Chip.Directory.cc_dir_6", - "address_width":11, - "name":"cc_dir", - "data_width":160, - "depth":2048, - "description":"Directory RAM", - "write_mask_granularity":20 - }, - { - "class":"freechips.rocketchip.util.SRAMAnnotation", - "target":"Rift2Chip.Directory.cc_dir_7", - "address_width":11, - "name":"cc_dir", - "data_width":160, - "depth":2048, - "description":"Directory RAM", - "write_mask_granularity":20 - }, - { - "class":"freechips.rocketchip.util.RegFieldDescMappingAnnotation", - "target":"Rift2Chip.Plic", - "regMappingSer":{ - "displayName":"Plic", - "deviceName":"Plic", - "baseAddress":268435456, - "regFields":[ - { - "byteOffset":"0x0", - "bitOffset":0, - "bitWidth":32, - "name":"reserved", - "resetValue":0, - "accessType":"R", - "wrType":"None", - "rdAction":"None", - "desc":"", - "group":"priority", - "groupDesc":"Acting priority of interrupt source", - "volatile":false, - "hasReset":true, - "enumerations":{ - - } - }, - { - "byteOffset":"0x0", - "bitOffset":32, - "bitWidth":32, - "name":"priority_0", - "resetValue":0, - "accessType":"RW", - "wrType":"None", - "rdAction":"None", - "desc":"Acting priority of interrupt source 0", - "group":"priority", - "groupDesc":"None", - "volatile":false, - "hasReset":false, - "enumerations":{ - - } - }, - { - "byteOffset":"0x0", - "bitOffset":64, - "bitWidth":32, - "name":"priority_1", - "resetValue":0, - "accessType":"RW", - "wrType":"None", - "rdAction":"None", - "desc":"Acting priority of interrupt source 1", - "group":"priority", - "groupDesc":"None", - "volatile":false, - "hasReset":false, - "enumerations":{ - - } - }, - { - "byteOffset":"0x0", - "bitOffset":96, - "bitWidth":32, - "name":"priority_2", - "resetValue":0, - "accessType":"RW", - "wrType":"None", - "rdAction":"None", - "desc":"Acting priority of interrupt source 2", - "group":"priority", - "groupDesc":"None", - "volatile":false, - "hasReset":false, - "enumerations":{ - - } - }, - { - "byteOffset":"0x0", - "bitOffset":128, - "bitWidth":32, - "name":"priority_3", - "resetValue":0, - "accessType":"RW", - "wrType":"None", - "rdAction":"None", - "desc":"Acting priority of interrupt source 3", - "group":"priority", - "groupDesc":"None", - "volatile":false, - "hasReset":false, - "enumerations":{ - - } - }, - { - "byteOffset":"0x0", - "bitOffset":160, - "bitWidth":32, - "name":"priority_4", - "resetValue":0, - "accessType":"RW", - "wrType":"None", - "rdAction":"None", - "desc":"Acting priority of interrupt source 4", - "group":"priority", - "groupDesc":"None", - "volatile":false, - "hasReset":false, - "enumerations":{ - - } - }, - { - "byteOffset":"0x0", - "bitOffset":192, - "bitWidth":32, - "name":"priority_5", - "resetValue":0, - "accessType":"RW", - "wrType":"None", - "rdAction":"None", - "desc":"Acting priority of interrupt source 5", - "group":"priority", - "groupDesc":"None", - "volatile":false, - "hasReset":false, - "enumerations":{ - - } - }, - { - "byteOffset":"0x0", - "bitOffset":224, - "bitWidth":32, - "name":"priority_6", - "resetValue":0, - "accessType":"RW", - "wrType":"None", - "rdAction":"None", - "desc":"Acting priority of interrupt source 6", - "group":"priority", - "groupDesc":"None", - "volatile":false, - "hasReset":false, - "enumerations":{ - - } - }, - { - "byteOffset":"0x0", - "bitOffset":256, - "bitWidth":32, - "name":"priority_7", - "resetValue":0, - "accessType":"RW", - "wrType":"None", - "rdAction":"None", - "desc":"Acting priority of interrupt source 7", - "group":"priority", - "groupDesc":"None", - "volatile":false, - "hasReset":false, - "enumerations":{ - - } - }, - { - "byteOffset":"0x0", - "bitOffset":288, - "bitWidth":32, - "name":"priority_8", - "resetValue":0, - "accessType":"RW", - "wrType":"None", - "rdAction":"None", - "desc":"Acting priority of interrupt source 8", - "group":"priority", - "groupDesc":"None", - "volatile":false, - "hasReset":false, - "enumerations":{ - - } - }, - { - "byteOffset":"0x0", - "bitOffset":320, - "bitWidth":32, - "name":"priority_9", - "resetValue":0, - "accessType":"RW", - "wrType":"None", - "rdAction":"None", - "desc":"Acting priority of interrupt source 9", - "group":"priority", - "groupDesc":"None", - "volatile":false, - "hasReset":false, - "enumerations":{ - - } - }, - { - "byteOffset":"0x0", - "bitOffset":352, - "bitWidth":32, - "name":"priority_10", - "resetValue":0, - "accessType":"RW", - "wrType":"None", - "rdAction":"None", - "desc":"Acting priority of interrupt source 10", - "group":"priority", - "groupDesc":"None", - "volatile":false, - "hasReset":false, - "enumerations":{ - - } - }, - { - "byteOffset":"0x0", - "bitOffset":384, - "bitWidth":32, - "name":"priority_11", - "resetValue":0, - "accessType":"RW", - "wrType":"None", - "rdAction":"None", - "desc":"Acting priority of interrupt source 11", - "group":"priority", - "groupDesc":"None", - "volatile":false, - "hasReset":false, - "enumerations":{ - - } - }, - { - "byteOffset":"0x0", - "bitOffset":416, - "bitWidth":32, - "name":"priority_12", - "resetValue":0, - "accessType":"RW", - "wrType":"None", - "rdAction":"None", - "desc":"Acting priority of interrupt source 12", - "group":"priority", - "groupDesc":"None", - "volatile":false, - "hasReset":false, - "enumerations":{ - - } - }, - { - "byteOffset":"0x0", - "bitOffset":448, - "bitWidth":32, - "name":"priority_13", - "resetValue":0, - "accessType":"RW", - "wrType":"None", - "rdAction":"None", - "desc":"Acting priority of interrupt source 13", - "group":"priority", - "groupDesc":"None", - "volatile":false, - "hasReset":false, - "enumerations":{ - - } - }, - { - "byteOffset":"0x0", - "bitOffset":480, - "bitWidth":32, - "name":"priority_14", - "resetValue":0, - "accessType":"RW", - "wrType":"None", - "rdAction":"None", - "desc":"Acting priority of interrupt source 14", - "group":"priority", - "groupDesc":"None", - "volatile":false, - "hasReset":false, - "enumerations":{ - - } - }, - { - "byteOffset":"0x0", - "bitOffset":512, - "bitWidth":32, - "name":"priority_15", - "resetValue":0, - "accessType":"RW", - "wrType":"None", - "rdAction":"None", - "desc":"Acting priority of interrupt source 15", - "group":"priority", - "groupDesc":"None", - "volatile":false, - "hasReset":false, - "enumerations":{ - - } - }, - { - "byteOffset":"0x0", - "bitOffset":544, - "bitWidth":32, - "name":"priority_16", - "resetValue":0, - "accessType":"RW", - "wrType":"None", - "rdAction":"None", - "desc":"Acting priority of interrupt source 16", - "group":"priority", - "groupDesc":"None", - "volatile":false, - "hasReset":false, - "enumerations":{ - - } - }, - { - "byteOffset":"0x0", - "bitOffset":576, - "bitWidth":32, - "name":"priority_17", - "resetValue":0, - "accessType":"RW", - "wrType":"None", - "rdAction":"None", - "desc":"Acting priority of interrupt source 17", - "group":"priority", - "groupDesc":"None", - "volatile":false, - "hasReset":false, - "enumerations":{ - - } - }, - { - "byteOffset":"0x0", - "bitOffset":608, - "bitWidth":32, - "name":"priority_18", - "resetValue":0, - "accessType":"RW", - "wrType":"None", - "rdAction":"None", - "desc":"Acting priority of interrupt source 18", - "group":"priority", - "groupDesc":"None", - "volatile":false, - "hasReset":false, - "enumerations":{ - - } - }, - { - "byteOffset":"0x0", - "bitOffset":640, - "bitWidth":32, - "name":"priority_19", - "resetValue":0, - "accessType":"RW", - "wrType":"None", - "rdAction":"None", - "desc":"Acting priority of interrupt source 19", - "group":"priority", - "groupDesc":"None", - "volatile":false, - "hasReset":false, - "enumerations":{ - - } - }, - { - "byteOffset":"0x0", - "bitOffset":672, - "bitWidth":32, - "name":"priority_20", - "resetValue":0, - "accessType":"RW", - "wrType":"None", - "rdAction":"None", - "desc":"Acting priority of interrupt source 20", - "group":"priority", - "groupDesc":"None", - "volatile":false, - "hasReset":false, - "enumerations":{ - - } - }, - { - "byteOffset":"0x0", - "bitOffset":704, - "bitWidth":32, - "name":"priority_21", - "resetValue":0, - "accessType":"RW", - "wrType":"None", - "rdAction":"None", - "desc":"Acting priority of interrupt source 21", - "group":"priority", - "groupDesc":"None", - "volatile":false, - "hasReset":false, - "enumerations":{ - - } - }, - { - "byteOffset":"0x0", - "bitOffset":736, - "bitWidth":32, - "name":"priority_22", - "resetValue":0, - "accessType":"RW", - "wrType":"None", - "rdAction":"None", - "desc":"Acting priority of interrupt source 22", - "group":"priority", - "groupDesc":"None", - "volatile":false, - "hasReset":false, - "enumerations":{ - - } - }, - { - "byteOffset":"0x0", - "bitOffset":768, - "bitWidth":32, - "name":"priority_23", - "resetValue":0, - "accessType":"RW", - "wrType":"None", - "rdAction":"None", - "desc":"Acting priority of interrupt source 23", - "group":"priority", - "groupDesc":"None", - "volatile":false, - "hasReset":false, - "enumerations":{ - - } - }, - { - "byteOffset":"0x0", - "bitOffset":800, - "bitWidth":32, - "name":"priority_24", - "resetValue":0, - "accessType":"RW", - "wrType":"None", - "rdAction":"None", - "desc":"Acting priority of interrupt source 24", - "group":"priority", - "groupDesc":"None", - "volatile":false, - "hasReset":false, - "enumerations":{ - - } - }, - { - "byteOffset":"0x0", - "bitOffset":832, - "bitWidth":32, - "name":"priority_25", - "resetValue":0, - "accessType":"RW", - "wrType":"None", - "rdAction":"None", - "desc":"Acting priority of interrupt source 25", - "group":"priority", - "groupDesc":"None", - "volatile":false, - "hasReset":false, - "enumerations":{ - - } - }, - { - "byteOffset":"0x0", - "bitOffset":864, - "bitWidth":32, - "name":"priority_26", - "resetValue":0, - "accessType":"RW", - "wrType":"None", - "rdAction":"None", - "desc":"Acting priority of interrupt source 26", - "group":"priority", - "groupDesc":"None", - "volatile":false, - "hasReset":false, - "enumerations":{ - - } - }, - { - "byteOffset":"0x0", - "bitOffset":896, - "bitWidth":32, - "name":"priority_27", - "resetValue":0, - "accessType":"RW", - "wrType":"None", - "rdAction":"None", - "desc":"Acting priority of interrupt source 27", - "group":"priority", - "groupDesc":"None", - "volatile":false, - "hasReset":false, - "enumerations":{ - - } - }, - { - "byteOffset":"0x0", - "bitOffset":928, - "bitWidth":32, - "name":"priority_28", - "resetValue":0, - "accessType":"RW", - "wrType":"None", - "rdAction":"None", - "desc":"Acting priority of interrupt source 28", - "group":"priority", - "groupDesc":"None", - "volatile":false, - "hasReset":false, - "enumerations":{ - - } - }, - { - "byteOffset":"0x0", - "bitOffset":960, - "bitWidth":32, - "name":"priority_29", - "resetValue":0, - "accessType":"RW", - "wrType":"None", - "rdAction":"None", - "desc":"Acting priority of interrupt source 29", - "group":"priority", - "groupDesc":"None", - "volatile":false, - "hasReset":false, - "enumerations":{ - - } - }, - { - "byteOffset":"0x0", - "bitOffset":992, - "bitWidth":32, - "name":"priority_30", - "resetValue":0, - "accessType":"RW", - "wrType":"None", - "rdAction":"None", - "desc":"Acting priority of interrupt source 30", - "group":"priority", - "groupDesc":"None", - "volatile":false, - "hasReset":false, - "enumerations":{ - - } - }, - { - "byteOffset":"0x1000", - "bitOffset":0, - "bitWidth":1, - "name":"reserved", - "resetValue":0, - "accessType":"R", - "wrType":"None", - "rdAction":"None", - "desc":"", - "group":"pending", - "groupDesc":"Pending Bit Array. 1 Bit for each interrupt source.", - "volatile":false, - "hasReset":true, - "enumerations":{ - - } - }, - { - "byteOffset":"0x1000", - "bitOffset":1, - "bitWidth":1, - "name":"pending_0", - "resetValue":0, - "accessType":"R", - "wrType":"None", - "rdAction":"None", - "desc":"Set to 1 if interrupt source 0 is pending, regardless of its enable or priority setting.", - "group":"pending", - "groupDesc":"None", - "volatile":true, - "hasReset":false, - "enumerations":{ - - } - }, - { - "byteOffset":"0x1000", - "bitOffset":2, - "bitWidth":1, - "name":"pending_1", - "resetValue":0, - "accessType":"R", - "wrType":"None", - "rdAction":"None", - "desc":"Set to 1 if interrupt source 1 is pending, regardless of its enable or priority setting.", - "group":"pending", - "groupDesc":"None", - "volatile":true, - "hasReset":false, - "enumerations":{ - - } - }, - { - "byteOffset":"0x1000", - "bitOffset":3, - "bitWidth":1, - "name":"pending_2", - "resetValue":0, - "accessType":"R", - "wrType":"None", - "rdAction":"None", - "desc":"Set to 1 if interrupt source 2 is pending, regardless of its enable or priority setting.", - "group":"pending", - "groupDesc":"None", - "volatile":true, - "hasReset":false, - "enumerations":{ - - } - }, - { - "byteOffset":"0x1000", - "bitOffset":4, - "bitWidth":1, - "name":"pending_3", - "resetValue":0, - "accessType":"R", - "wrType":"None", - "rdAction":"None", - "desc":"Set to 1 if interrupt source 3 is pending, regardless of its enable or priority setting.", - "group":"pending", - "groupDesc":"None", - "volatile":true, - "hasReset":false, - "enumerations":{ - - } - }, - { - "byteOffset":"0x1000", - "bitOffset":5, - "bitWidth":1, - "name":"pending_4", - "resetValue":0, - "accessType":"R", - "wrType":"None", - "rdAction":"None", - "desc":"Set to 1 if interrupt source 4 is pending, regardless of its enable or priority setting.", - "group":"pending", - "groupDesc":"None", - "volatile":true, - "hasReset":false, - "enumerations":{ - - } - }, - { - "byteOffset":"0x1000", - "bitOffset":6, - "bitWidth":1, - "name":"pending_5", - "resetValue":0, - "accessType":"R", - "wrType":"None", - "rdAction":"None", - "desc":"Set to 1 if interrupt source 5 is pending, regardless of its enable or priority setting.", - "group":"pending", - "groupDesc":"None", - "volatile":true, - "hasReset":false, - "enumerations":{ - - } - }, - { - "byteOffset":"0x1000", - "bitOffset":7, - "bitWidth":1, - "name":"pending_6", - "resetValue":0, - "accessType":"R", - "wrType":"None", - "rdAction":"None", - "desc":"Set to 1 if interrupt source 6 is pending, regardless of its enable or priority setting.", - "group":"pending", - "groupDesc":"None", - "volatile":true, - "hasReset":false, - "enumerations":{ - - } - }, - { - "byteOffset":"0x1000", - "bitOffset":8, - "bitWidth":1, - "name":"pending_7", - "resetValue":0, - "accessType":"R", - "wrType":"None", - "rdAction":"None", - "desc":"Set to 1 if interrupt source 7 is pending, regardless of its enable or priority setting.", - "group":"pending", - "groupDesc":"None", - "volatile":true, - "hasReset":false, - "enumerations":{ - - } - }, - { - "byteOffset":"0x1000", - "bitOffset":9, - "bitWidth":1, - "name":"pending_8", - "resetValue":0, - "accessType":"R", - "wrType":"None", - "rdAction":"None", - "desc":"Set to 1 if interrupt source 8 is pending, regardless of its enable or priority setting.", - "group":"pending", - "groupDesc":"None", - "volatile":true, - "hasReset":false, - "enumerations":{ - - } - }, - { - "byteOffset":"0x1000", - "bitOffset":10, - "bitWidth":1, - "name":"pending_9", - "resetValue":0, - "accessType":"R", - "wrType":"None", - "rdAction":"None", - "desc":"Set to 1 if interrupt source 9 is pending, regardless of its enable or priority setting.", - "group":"pending", - "groupDesc":"None", - "volatile":true, - "hasReset":false, - "enumerations":{ - - } - }, - { - "byteOffset":"0x1000", - "bitOffset":11, - "bitWidth":1, - "name":"pending_10", - "resetValue":0, - "accessType":"R", - "wrType":"None", - "rdAction":"None", - "desc":"Set to 1 if interrupt source 10 is pending, regardless of its enable or priority setting.", - "group":"pending", - "groupDesc":"None", - "volatile":true, - "hasReset":false, - "enumerations":{ - - } - }, - { - "byteOffset":"0x1000", - "bitOffset":12, - "bitWidth":1, - "name":"pending_11", - "resetValue":0, - "accessType":"R", - "wrType":"None", - "rdAction":"None", - "desc":"Set to 1 if interrupt source 11 is pending, regardless of its enable or priority setting.", - "group":"pending", - "groupDesc":"None", - "volatile":true, - "hasReset":false, - "enumerations":{ - - } - }, - { - "byteOffset":"0x1000", - "bitOffset":13, - "bitWidth":1, - "name":"pending_12", - "resetValue":0, - "accessType":"R", - "wrType":"None", - "rdAction":"None", - "desc":"Set to 1 if interrupt source 12 is pending, regardless of its enable or priority setting.", - "group":"pending", - "groupDesc":"None", - "volatile":true, - "hasReset":false, - "enumerations":{ - - } - }, - { - "byteOffset":"0x1000", - "bitOffset":14, - "bitWidth":1, - "name":"pending_13", - "resetValue":0, - "accessType":"R", - "wrType":"None", - "rdAction":"None", - "desc":"Set to 1 if interrupt source 13 is pending, regardless of its enable or priority setting.", - "group":"pending", - "groupDesc":"None", - "volatile":true, - "hasReset":false, - "enumerations":{ - - } - }, - { - "byteOffset":"0x1000", - "bitOffset":15, - "bitWidth":1, - "name":"pending_14", - "resetValue":0, - "accessType":"R", - "wrType":"None", - "rdAction":"None", - "desc":"Set to 1 if interrupt source 14 is pending, regardless of its enable or priority setting.", - "group":"pending", - "groupDesc":"None", - "volatile":true, - "hasReset":false, - "enumerations":{ - - } - }, - { - "byteOffset":"0x1000", - "bitOffset":16, - "bitWidth":1, - "name":"pending_15", - "resetValue":0, - "accessType":"R", - "wrType":"None", - "rdAction":"None", - "desc":"Set to 1 if interrupt source 15 is pending, regardless of its enable or priority setting.", - "group":"pending", - "groupDesc":"None", - "volatile":true, - "hasReset":false, - "enumerations":{ - - } - }, - { - "byteOffset":"0x1000", - "bitOffset":17, - "bitWidth":1, - "name":"pending_16", - "resetValue":0, - "accessType":"R", - "wrType":"None", - "rdAction":"None", - "desc":"Set to 1 if interrupt source 16 is pending, regardless of its enable or priority setting.", - "group":"pending", - "groupDesc":"None", - "volatile":true, - "hasReset":false, - "enumerations":{ - - } - }, - { - "byteOffset":"0x1000", - "bitOffset":18, - "bitWidth":1, - "name":"pending_17", - "resetValue":0, - "accessType":"R", - "wrType":"None", - "rdAction":"None", - "desc":"Set to 1 if interrupt source 17 is pending, regardless of its enable or priority setting.", - "group":"pending", - "groupDesc":"None", - "volatile":true, - "hasReset":false, - "enumerations":{ - - } - }, - { - "byteOffset":"0x1000", - "bitOffset":19, - "bitWidth":1, - "name":"pending_18", - "resetValue":0, - "accessType":"R", - "wrType":"None", - "rdAction":"None", - "desc":"Set to 1 if interrupt source 18 is pending, regardless of its enable or priority setting.", - "group":"pending", - "groupDesc":"None", - "volatile":true, - "hasReset":false, - "enumerations":{ - - } - }, - { - "byteOffset":"0x1000", - "bitOffset":20, - "bitWidth":1, - "name":"pending_19", - "resetValue":0, - "accessType":"R", - "wrType":"None", - "rdAction":"None", - "desc":"Set to 1 if interrupt source 19 is pending, regardless of its enable or priority setting.", - "group":"pending", - "groupDesc":"None", - "volatile":true, - "hasReset":false, - "enumerations":{ - - } - }, - { - "byteOffset":"0x1000", - "bitOffset":21, - "bitWidth":1, - "name":"pending_20", - "resetValue":0, - "accessType":"R", - "wrType":"None", - "rdAction":"None", - "desc":"Set to 1 if interrupt source 20 is pending, regardless of its enable or priority setting.", - "group":"pending", - "groupDesc":"None", - "volatile":true, - "hasReset":false, - "enumerations":{ - - } - }, - { - "byteOffset":"0x1000", - "bitOffset":22, - "bitWidth":1, - "name":"pending_21", - "resetValue":0, - "accessType":"R", - "wrType":"None", - "rdAction":"None", - "desc":"Set to 1 if interrupt source 21 is pending, regardless of its enable or priority setting.", - "group":"pending", - "groupDesc":"None", - "volatile":true, - "hasReset":false, - "enumerations":{ - - } - }, - { - "byteOffset":"0x1000", - "bitOffset":23, - "bitWidth":1, - "name":"pending_22", - "resetValue":0, - "accessType":"R", - "wrType":"None", - "rdAction":"None", - "desc":"Set to 1 if interrupt source 22 is pending, regardless of its enable or priority setting.", - "group":"pending", - "groupDesc":"None", - "volatile":true, - "hasReset":false, - "enumerations":{ - - } - }, - { - "byteOffset":"0x1000", - "bitOffset":24, - "bitWidth":1, - "name":"pending_23", - "resetValue":0, - "accessType":"R", - "wrType":"None", - "rdAction":"None", - "desc":"Set to 1 if interrupt source 23 is pending, regardless of its enable or priority setting.", - "group":"pending", - "groupDesc":"None", - "volatile":true, - "hasReset":false, - "enumerations":{ - - } - }, - { - "byteOffset":"0x1000", - "bitOffset":25, - "bitWidth":1, - "name":"pending_24", - "resetValue":0, - "accessType":"R", - "wrType":"None", - "rdAction":"None", - "desc":"Set to 1 if interrupt source 24 is pending, regardless of its enable or priority setting.", - "group":"pending", - "groupDesc":"None", - "volatile":true, - "hasReset":false, - "enumerations":{ - - } - }, - { - "byteOffset":"0x1000", - "bitOffset":26, - "bitWidth":1, - "name":"pending_25", - "resetValue":0, - "accessType":"R", - "wrType":"None", - "rdAction":"None", - "desc":"Set to 1 if interrupt source 25 is pending, regardless of its enable or priority setting.", - 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"name":"unnamedRegField800_640", + "resetValue":0, + "accessType":"None", + "wrType":"None", + "rdAction":"None", + "desc":"None", + "group":"None", + "groupDesc":"None", + "volatile":false, + "hasReset":false, + "enumerations":{ + + } + }, + { + "byteOffset":"0x800", + "bitOffset":648, + "bitWidth":8, + "name":"unnamedRegField800_648", + "resetValue":0, + "accessType":"None", + "wrType":"None", + "rdAction":"None", + "desc":"None", + "group":"None", + "groupDesc":"None", + "volatile":false, + "hasReset":false, + "enumerations":{ + + } + }, + { + "byteOffset":"0x800", + "bitOffset":656, + "bitWidth":8, + "name":"unnamedRegField800_656", + "resetValue":0, + "accessType":"None", + "wrType":"None", + "rdAction":"None", + "desc":"None", + "group":"None", + "groupDesc":"None", + "volatile":false, + "hasReset":false, + "enumerations":{ + + } + }, + { + "byteOffset":"0x800", + "bitOffset":664, + "bitWidth":8, + "name":"unnamedRegField800_664", + "resetValue":0, + "accessType":"None", + "wrType":"None", + "rdAction":"None", + "desc":"None", + "group":"None", + "groupDesc":"None", + "volatile":false, + "hasReset":false, + "enumerations":{ + + } + }, + { + "byteOffset":"0x800", + "bitOffset":672, + "bitWidth":8, + "name":"unnamedRegField800_672", + "resetValue":0, + "accessType":"None", + "wrType":"None", + "rdAction":"None", + "desc":"None", + "group":"None", + "groupDesc":"None", + "volatile":false, + "hasReset":false, + "enumerations":{ + + } + }, + { + "byteOffset":"0x800", + "bitOffset":680, + "bitWidth":8, + "name":"unnamedRegField800_680", + "resetValue":0, + "accessType":"None", + "wrType":"None", + "rdAction":"None", + "desc":"None", + "group":"None", + "groupDesc":"None", + "volatile":false, + "hasReset":false, + "enumerations":{ + + } + }, + { + "byteOffset":"0x800", + "bitOffset":688, + "bitWidth":8, + "name":"unnamedRegField800_688", + "resetValue":0, + "accessType":"None", + "wrType":"None", + "rdAction":"None", + "desc":"None", + "group":"None", + "groupDesc":"None", + "volatile":false, + "hasReset":false, + "enumerations":{ + + } + }, + { + "byteOffset":"0x800", + "bitOffset":696, + "bitWidth":8, + "name":"unnamedRegField800_696", + "resetValue":0, + "accessType":"None", + "wrType":"None", + "rdAction":"None", + "desc":"None", + "group":"None", + "groupDesc":"None", + "volatile":false, + "hasReset":false, + "enumerations":{ + + } + }, + { + "byteOffset":"0x800", + "bitOffset":704, + "bitWidth":8, + "name":"unnamedRegField800_704", + "resetValue":0, + "accessType":"None", + "wrType":"None", + "rdAction":"None", + "desc":"None", + "group":"None", + "groupDesc":"None", + "volatile":false, + "hasReset":false, + "enumerations":{ + + } + }, + { + "byteOffset":"0x800", + "bitOffset":712, + "bitWidth":8, + "name":"unnamedRegField800_712", + "resetValue":0, + "accessType":"None", + "wrType":"None", + "rdAction":"None", + "desc":"None", + "group":"None", + "groupDesc":"None", + "volatile":false, + "hasReset":false, + "enumerations":{ + + } + }, + { + "byteOffset":"0x800", + "bitOffset":720, + "bitWidth":8, + "name":"unnamedRegField800_720", + "resetValue":0, + "accessType":"None", + "wrType":"None", + "rdAction":"None", + "desc":"None", + "group":"None", + "groupDesc":"None", + "volatile":false, + "hasReset":false, + "enumerations":{ + + } + }, + { + "byteOffset":"0x800", + "bitOffset":728, + "bitWidth":8, + "name":"unnamedRegField800_728", + "resetValue":0, + "accessType":"None", + "wrType":"None", + "rdAction":"None", + "desc":"None", + "group":"None", + "groupDesc":"None", + "volatile":false, + "hasReset":false, + "enumerations":{ + + } + }, + { + "byteOffset":"0x800", + "bitOffset":736, + "bitWidth":8, + "name":"unnamedRegField800_736", + "resetValue":0, + "accessType":"None", + "wrType":"None", + "rdAction":"None", + "desc":"None", + "group":"None", + "groupDesc":"None", + "volatile":false, + "hasReset":false, + "enumerations":{ + + } + }, + { + "byteOffset":"0x800", + "bitOffset":744, + "bitWidth":8, + "name":"unnamedRegField800_744", + "resetValue":0, + "accessType":"None", + "wrType":"None", + "rdAction":"None", + "desc":"None", + "group":"None", + "groupDesc":"None", + "volatile":false, + "hasReset":false, + "enumerations":{ + + } + }, + { + "byteOffset":"0x800", + "bitOffset":752, + "bitWidth":8, + "name":"unnamedRegField800_752", + "resetValue":0, + "accessType":"None", + "wrType":"None", + "rdAction":"None", + "desc":"None", + "group":"None", + "groupDesc":"None", + "volatile":false, + "hasReset":false, + "enumerations":{ + + } + }, + { + "byteOffset":"0x800", + "bitOffset":760, + "bitWidth":8, + "name":"unnamedRegField800_760", + "resetValue":0, + "accessType":"None", + "wrType":"None", + "rdAction":"None", + "desc":"None", + "group":"None", + "groupDesc":"None", + "volatile":false, + "hasReset":false, + "enumerations":{ + + } + }, + { + "byteOffset":"0x800", + "bitOffset":768, + "bitWidth":8, + "name":"unnamedRegField800_768", + "resetValue":0, + "accessType":"None", + "wrType":"None", + "rdAction":"None", + "desc":"None", + "group":"None", + "groupDesc":"None", + "volatile":false, + "hasReset":false, + "enumerations":{ + + } + }, + { + "byteOffset":"0x800", + "bitOffset":776, + "bitWidth":8, + "name":"unnamedRegField800_776", + "resetValue":0, + "accessType":"None", + "wrType":"None", + "rdAction":"None", + "desc":"None", + "group":"None", + "groupDesc":"None", + "volatile":false, + "hasReset":false, + "enumerations":{ + + } + }, + { + "byteOffset":"0x800", + "bitOffset":784, + "bitWidth":8, + "name":"unnamedRegField800_784", + "resetValue":0, + "accessType":"None", + "wrType":"None", + "rdAction":"None", + "desc":"None", + "group":"None", + "groupDesc":"None", + "volatile":false, + "hasReset":false, + "enumerations":{ + + } + }, + { + "byteOffset":"0x800", + "bitOffset":792, + "bitWidth":8, + "name":"unnamedRegField800_792", + "resetValue":0, + "accessType":"None", + "wrType":"None", + "rdAction":"None", + "desc":"None", + "group":"None", + "groupDesc":"None", + "volatile":false, + "hasReset":false, + "enumerations":{ + + } + }, + { + "byteOffset":"0x800", + "bitOffset":800, + "bitWidth":8, + "name":"unnamedRegField800_800", + "resetValue":0, + "accessType":"None", + "wrType":"None", + "rdAction":"None", + "desc":"None", + "group":"None", + "groupDesc":"None", + "volatile":false, + "hasReset":false, + "enumerations":{ + + } + }, + { + "byteOffset":"0x800", + "bitOffset":808, + "bitWidth":8, + "name":"unnamedRegField800_808", + "resetValue":0, + "accessType":"None", + "wrType":"None", + "rdAction":"None", + "desc":"None", + "group":"None", + "groupDesc":"None", + "volatile":false, + "hasReset":false, + "enumerations":{ + + } + }, + { + "byteOffset":"0x800", + "bitOffset":816, + "bitWidth":8, + "name":"unnamedRegField800_816", + "resetValue":0, + "accessType":"None", + "wrType":"None", + "rdAction":"None", + "desc":"None", + "group":"None", + "groupDesc":"None", + "volatile":false, + "hasReset":false, + "enumerations":{ + + } + }, + { + "byteOffset":"0x800", + "bitOffset":824, + "bitWidth":8, + "name":"unnamedRegField800_824", + "resetValue":0, + "accessType":"None", + "wrType":"None", + "rdAction":"None", + "desc":"None", + "group":"None", + "groupDesc":"None", + "volatile":false, + "hasReset":false, + "enumerations":{ + + } + } + ] + } }, { - "class":"firrtl.transforms.DontTouchAnnotation", - "target":"~Rift2Chip|diff>io_csr_misa" + "class":"firrtl.transforms.BlackBoxInlineAnno", + "target":"Rift2Chip.plusarg_reader_2", + "name":"plusarg_reader.v", + "text":"// See LICENSE.SiFive for license details.\n\n//VCS coverage exclude_file\n\n// No default parameter values are intended, nor does IEEE 1800-2012 require them (clause A.2.4 param_assignment),\n// but Incisive demands them. These default values should never be used.\nmodule plusarg_reader #(\n parameter FORMAT=\"borked=%d\",\n parameter WIDTH=1,\n parameter [WIDTH-1:0] DEFAULT=0\n) (\n output [WIDTH-1:0] out\n);\n\n`ifdef SYNTHESIS\nassign out = DEFAULT;\n`else\nreg [WIDTH-1:0] myplus;\nassign out = myplus;\n\ninitial begin\n if (!$value$plusargs(FORMAT, myplus)) myplus = DEFAULT;\nend\n`endif\n\nendmodule\n" }, { - "class":"firrtl.transforms.DontTouchAnnotation", - "target":"~Rift2Chip|diff>io_csr_mie" + "class":"firrtl.transforms.BlackBoxInlineAnno", + "target":"Rift2Chip.plusarg_reader_3", + "name":"plusarg_reader.v", + "text":"// See LICENSE.SiFive for license details.\n\n//VCS coverage exclude_file\n\n// No default parameter values are intended, nor does IEEE 1800-2012 require them (clause A.2.4 param_assignment),\n// but Incisive demands them. These default values should never be used.\nmodule plusarg_reader #(\n parameter FORMAT=\"borked=%d\",\n parameter WIDTH=1,\n parameter [WIDTH-1:0] DEFAULT=0\n) (\n output [WIDTH-1:0] out\n);\n\n`ifdef SYNTHESIS\nassign out = DEFAULT;\n`else\nreg [WIDTH-1:0] myplus;\nassign out = myplus;\n\ninitial begin\n if (!$value$plusargs(FORMAT, myplus)) myplus = DEFAULT;\nend\n`endif\n\nendmodule\n" }, { - "class":"firrtl.transforms.DontTouchAnnotation", - "target":"~Rift2Chip|diff>io_csr_mip" + "class":"freechips.rocketchip.util.RegFieldDescMappingAnnotation", + "target":"Rift2Chip.AClint", + "regMappingSer":{ + "displayName":"AClint", + "deviceName":"AClint", + "baseAddress":131072, + "regFields":[ + { + "byteOffset":"0x0", + "bitOffset":0, + "bitWidth":64, + "name":"mtimecmp_0", + "resetValue":0, + "accessType":"RW", + "wrType":"None", + "rdAction":"None", + "desc":"mtimecmp_0", + "group":"mtimecmp", + "groupDesc":"MTIMECMP for hart x", + "volatile":false, + "hasReset":false, + "enumerations":{ + + } + }, + { + "byteOffset":"0x8000", + "bitOffset":0, + "bitWidth":64, + "name":"mtime", + "resetValue":0, + "accessType":"RW", + "wrType":"None", + "rdAction":"None", + "desc":"mtime", + "group":"mtime", + "groupDesc":"Timer Register", + "volatile":true, + "hasReset":true, + "enumerations":{ + + } + }, + { + "byteOffset":"0x9000", + "bitOffset":0, + "bitWidth":1, + "name":"msip_0", + "resetValue":0, + "accessType":"RW", + "wrType":"None", + "rdAction":"None", + "desc":"MSIP bit for Hart 0", + "group":"msip", + "groupDesc":"MSIP Bits", + "volatile":false, + "hasReset":true, + "enumerations":{ + + } + }, + { + "byteOffset":"0xa000", + "bitOffset":0, + "bitWidth":1, + "name":"ssip_0", + "resetValue":0, + "accessType":"RW", + "wrType":"None", + "rdAction":"None", + "desc":"SSIP bit for Hart 0", + "group":"ssip", + "groupDesc":"SSIP Bits", + "volatile":false, + "hasReset":true, + "enumerations":{ + + } + } + ] + } }, { - "class":"firrtl.transforms.DontTouchAnnotation", - "target":"~Rift2Chip|diff>io_csr_medeleg" + "class":"firrtl.transforms.BlackBoxInlineAnno", + "target":"Rift2Chip.plusarg_reader_4", + "name":"plusarg_reader.v", + "text":"// See LICENSE.SiFive for license details.\n\n//VCS coverage exclude_file\n\n// No default parameter values are intended, nor does IEEE 1800-2012 require them (clause A.2.4 param_assignment),\n// but Incisive demands them. These default values should never be used.\nmodule plusarg_reader #(\n parameter FORMAT=\"borked=%d\",\n parameter WIDTH=1,\n parameter [WIDTH-1:0] DEFAULT=0\n) (\n output [WIDTH-1:0] out\n);\n\n`ifdef SYNTHESIS\nassign out = DEFAULT;\n`else\nreg [WIDTH-1:0] myplus;\nassign out = myplus;\n\ninitial begin\n if (!$value$plusargs(FORMAT, myplus)) myplus = DEFAULT;\nend\n`endif\n\nendmodule\n" }, { - "class":"firrtl.transforms.DontTouchAnnotation", - "target":"~Rift2Chip|diff>io_csr_mideleg" + "class":"firrtl.transforms.BlackBoxInlineAnno", + "target":"Rift2Chip.plusarg_reader_5", + "name":"plusarg_reader.v", + "text":"// See LICENSE.SiFive for license details.\n\n//VCS coverage exclude_file\n\n// No default parameter values are intended, nor does IEEE 1800-2012 require them (clause A.2.4 param_assignment),\n// but Incisive demands them. These default values should never be used.\nmodule plusarg_reader #(\n parameter FORMAT=\"borked=%d\",\n parameter WIDTH=1,\n parameter [WIDTH-1:0] DEFAULT=0\n) (\n output [WIDTH-1:0] out\n);\n\n`ifdef SYNTHESIS\nassign out = DEFAULT;\n`else\nreg [WIDTH-1:0] myplus;\nassign out = myplus;\n\ninitial begin\n if (!$value$plusargs(FORMAT, myplus)) myplus = DEFAULT;\nend\n`endif\n\nendmodule\n" }, { - "class":"firrtl.transforms.DontTouchAnnotation", - "target":"~Rift2Chip|diff>io_csr_pmpcfg_0" + "class":"freechips.rocketchip.util.RegFieldDescMappingAnnotation", + "target":"Rift2Chip.Plic", + "regMappingSer":{ + "displayName":"Plic", + "deviceName":"Plic", + "baseAddress":268435456, + "regFields":[ + { + "byteOffset":"0x0", + "bitOffset":0, + "bitWidth":32, + "name":"reserved", + "resetValue":0, + "accessType":"R", + "wrType":"None", + "rdAction":"None", + "desc":"", + "group":"priority", + "groupDesc":"Acting priority of interrupt source", + "volatile":false, + "hasReset":true, + "enumerations":{ + + } + }, + { + "byteOffset":"0x0", + "bitOffset":32, + "bitWidth":32, + "name":"priority_0", + "resetValue":0, + "accessType":"RW", + "wrType":"None", + "rdAction":"None", + "desc":"Acting priority of interrupt source 0", + "group":"priority", + "groupDesc":"None", + "volatile":false, + "hasReset":false, + "enumerations":{ + + } + }, + { + "byteOffset":"0x0", + "bitOffset":64, + "bitWidth":32, + "name":"priority_1", + "resetValue":0, + "accessType":"RW", + "wrType":"None", + "rdAction":"None", + "desc":"Acting priority of interrupt source 1", + "group":"priority", + "groupDesc":"None", + "volatile":false, + "hasReset":false, + "enumerations":{ + + } + }, + { + "byteOffset":"0x0", + "bitOffset":96, + "bitWidth":32, + "name":"priority_2", + "resetValue":0, + "accessType":"RW", + "wrType":"None", + "rdAction":"None", + "desc":"Acting priority of interrupt source 2", + "group":"priority", + "groupDesc":"None", + "volatile":false, + "hasReset":false, + "enumerations":{ + + } + }, + { + "byteOffset":"0x0", + "bitOffset":128, + "bitWidth":32, + "name":"priority_3", + "resetValue":0, + "accessType":"RW", + "wrType":"None", + "rdAction":"None", + "desc":"Acting priority of interrupt source 3", + "group":"priority", + "groupDesc":"None", + "volatile":false, + "hasReset":false, + "enumerations":{ + + } + }, + { + "byteOffset":"0x0", + "bitOffset":160, + "bitWidth":32, + "name":"priority_4", + "resetValue":0, + "accessType":"RW", + "wrType":"None", + "rdAction":"None", + "desc":"Acting priority of interrupt source 4", + "group":"priority", + "groupDesc":"None", + "volatile":false, + "hasReset":false, + "enumerations":{ + + } + }, + { + "byteOffset":"0x0", + "bitOffset":192, + "bitWidth":32, + "name":"priority_5", + "resetValue":0, + "accessType":"RW", + "wrType":"None", + "rdAction":"None", + "desc":"Acting priority of interrupt source 5", + "group":"priority", + "groupDesc":"None", + "volatile":false, + "hasReset":false, + "enumerations":{ + + } + }, + { + "byteOffset":"0x0", + "bitOffset":224, + "bitWidth":32, + "name":"priority_6", + "resetValue":0, + "accessType":"RW", + "wrType":"None", + "rdAction":"None", + "desc":"Acting priority of interrupt source 6", + "group":"priority", + "groupDesc":"None", + "volatile":false, + "hasReset":false, + "enumerations":{ + + } + }, + { + "byteOffset":"0x0", + "bitOffset":256, + "bitWidth":32, + "name":"priority_7", + "resetValue":0, + "accessType":"RW", + "wrType":"None", + "rdAction":"None", + "desc":"Acting priority of interrupt source 7", + "group":"priority", + "groupDesc":"None", + "volatile":false, + "hasReset":false, + "enumerations":{ + + } + }, + { + "byteOffset":"0x0", + "bitOffset":288, + "bitWidth":32, + "name":"priority_8", + "resetValue":0, + "accessType":"RW", + "wrType":"None", + "rdAction":"None", + "desc":"Acting priority of interrupt source 8", + "group":"priority", + "groupDesc":"None", + "volatile":false, + "hasReset":false, + "enumerations":{ + + } + }, + { + "byteOffset":"0x0", + "bitOffset":320, + "bitWidth":32, + "name":"priority_9", + "resetValue":0, + "accessType":"RW", + "wrType":"None", + "rdAction":"None", + "desc":"Acting priority of interrupt source 9", + "group":"priority", + "groupDesc":"None", + "volatile":false, + "hasReset":false, + "enumerations":{ + + } + }, + { + "byteOffset":"0x0", + "bitOffset":352, + "bitWidth":32, + "name":"priority_10", + "resetValue":0, + "accessType":"RW", + "wrType":"None", + "rdAction":"None", + "desc":"Acting priority of interrupt source 10", + "group":"priority", + "groupDesc":"None", + "volatile":false, + "hasReset":false, + "enumerations":{ + + } + }, + { + "byteOffset":"0x0", + "bitOffset":384, + "bitWidth":32, + "name":"priority_11", + "resetValue":0, + "accessType":"RW", + "wrType":"None", + "rdAction":"None", + "desc":"Acting priority of interrupt source 11", + "group":"priority", + "groupDesc":"None", + "volatile":false, + "hasReset":false, + "enumerations":{ + + } + }, + { + "byteOffset":"0x0", + "bitOffset":416, + "bitWidth":32, + "name":"priority_12", + "resetValue":0, + "accessType":"RW", + "wrType":"None", + "rdAction":"None", + "desc":"Acting priority of interrupt source 12", + "group":"priority", + "groupDesc":"None", + "volatile":false, + "hasReset":false, + "enumerations":{ + + } + }, + { + "byteOffset":"0x0", + "bitOffset":448, + "bitWidth":32, + "name":"priority_13", + "resetValue":0, + "accessType":"RW", + "wrType":"None", + "rdAction":"None", + "desc":"Acting priority of interrupt source 13", + "group":"priority", + "groupDesc":"None", + "volatile":false, + "hasReset":false, + "enumerations":{ + + } + }, + { + "byteOffset":"0x0", + "bitOffset":480, + "bitWidth":32, + "name":"priority_14", + "resetValue":0, + "accessType":"RW", + "wrType":"None", + "rdAction":"None", + "desc":"Acting priority of interrupt source 14", + "group":"priority", + "groupDesc":"None", + "volatile":false, + "hasReset":false, + "enumerations":{ + + } + }, + { + "byteOffset":"0x0", + "bitOffset":512, + "bitWidth":32, + "name":"priority_15", + "resetValue":0, + "accessType":"RW", + "wrType":"None", + "rdAction":"None", + "desc":"Acting priority of interrupt source 15", + "group":"priority", + "groupDesc":"None", + "volatile":false, + "hasReset":false, + "enumerations":{ + + } + }, + { + "byteOffset":"0x0", + "bitOffset":544, + "bitWidth":32, + "name":"priority_16", + "resetValue":0, + "accessType":"RW", + "wrType":"None", + "rdAction":"None", + "desc":"Acting priority of interrupt source 16", + "group":"priority", + "groupDesc":"None", + "volatile":false, + "hasReset":false, + "enumerations":{ + + } + }, + { + "byteOffset":"0x0", + "bitOffset":576, + "bitWidth":32, + "name":"priority_17", + "resetValue":0, + "accessType":"RW", + "wrType":"None", + "rdAction":"None", + "desc":"Acting priority of interrupt source 17", + "group":"priority", + "groupDesc":"None", + "volatile":false, + "hasReset":false, + "enumerations":{ + + } + }, + { + "byteOffset":"0x0", + "bitOffset":608, + "bitWidth":32, + "name":"priority_18", + "resetValue":0, + "accessType":"RW", + "wrType":"None", + "rdAction":"None", + "desc":"Acting priority of interrupt source 18", + "group":"priority", + "groupDesc":"None", + "volatile":false, + "hasReset":false, + "enumerations":{ + + } + }, + { + "byteOffset":"0x0", + "bitOffset":640, + "bitWidth":32, + "name":"priority_19", + "resetValue":0, + "accessType":"RW", + "wrType":"None", + "rdAction":"None", + "desc":"Acting priority of interrupt source 19", + "group":"priority", + "groupDesc":"None", + "volatile":false, + "hasReset":false, + "enumerations":{ + + } + }, + { + "byteOffset":"0x0", + "bitOffset":672, + "bitWidth":32, + "name":"priority_20", + "resetValue":0, + "accessType":"RW", + "wrType":"None", + "rdAction":"None", + "desc":"Acting priority of interrupt source 20", + "group":"priority", + "groupDesc":"None", + "volatile":false, + "hasReset":false, + "enumerations":{ + + } + }, + { + "byteOffset":"0x0", + "bitOffset":704, + "bitWidth":32, + "name":"priority_21", + "resetValue":0, + "accessType":"RW", + "wrType":"None", + "rdAction":"None", + "desc":"Acting priority of interrupt source 21", + "group":"priority", + "groupDesc":"None", + "volatile":false, + "hasReset":false, + "enumerations":{ + + } + }, + { + "byteOffset":"0x0", + "bitOffset":736, + "bitWidth":32, + "name":"priority_22", + "resetValue":0, + "accessType":"RW", + "wrType":"None", + "rdAction":"None", + "desc":"Acting priority of interrupt source 22", + "group":"priority", + "groupDesc":"None", + "volatile":false, + "hasReset":false, + "enumerations":{ + + } + }, + { + "byteOffset":"0x0", + "bitOffset":768, + "bitWidth":32, + "name":"priority_23", + "resetValue":0, + "accessType":"RW", + "wrType":"None", + "rdAction":"None", + "desc":"Acting priority of interrupt source 23", + "group":"priority", + "groupDesc":"None", + "volatile":false, + "hasReset":false, + "enumerations":{ + + } + }, + { + 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"rdAction":"None", + "desc":"Set bits to 1 if interrupt should be enabled.", + "group":"enables_0", + "groupDesc":"None", + "volatile":false, + "hasReset":false, + "enumerations":{ + + } + }, + { + "byteOffset":"0x2000", + "bitOffset":17, + "bitWidth":1, + "name":"enables_16", + "resetValue":0, + "accessType":"RW", + "wrType":"None", + "rdAction":"None", + "desc":"Set bits to 1 if interrupt should be enabled.", + "group":"enables_0", + "groupDesc":"None", + "volatile":false, + "hasReset":false, + "enumerations":{ + + } + }, + { + "byteOffset":"0x2000", + "bitOffset":18, + "bitWidth":1, + "name":"enables_17", + "resetValue":0, + "accessType":"RW", + "wrType":"None", + "rdAction":"None", + "desc":"Set bits to 1 if interrupt should be enabled.", + "group":"enables_0", + "groupDesc":"None", + "volatile":false, + "hasReset":false, + "enumerations":{ + + } + }, + { + "byteOffset":"0x2000", + "bitOffset":19, + "bitWidth":1, + "name":"enables_18", + "resetValue":0, + "accessType":"RW", + "wrType":"None", + "rdAction":"None", + "desc":"Set bits to 1 if interrupt should be enabled.", + "group":"enables_0", + "groupDesc":"None", + "volatile":false, + "hasReset":false, + "enumerations":{ + + } + }, + { + "byteOffset":"0x2000", + "bitOffset":20, + "bitWidth":1, + "name":"enables_19", + "resetValue":0, + "accessType":"RW", + "wrType":"None", + "rdAction":"None", + "desc":"Set bits to 1 if interrupt should be enabled.", + "group":"enables_0", + "groupDesc":"None", + "volatile":false, + "hasReset":false, + "enumerations":{ + + } + }, + { + "byteOffset":"0x2000", + "bitOffset":21, + "bitWidth":1, + "name":"enables_20", + "resetValue":0, + "accessType":"RW", + "wrType":"None", + "rdAction":"None", + "desc":"Set bits to 1 if interrupt should be enabled.", + "group":"enables_0", + "groupDesc":"None", + "volatile":false, + "hasReset":false, + "enumerations":{ + + } + }, + { + "byteOffset":"0x2000", + "bitOffset":22, + "bitWidth":1, + "name":"enables_21", + "resetValue":0, + "accessType":"RW", + "wrType":"None", + "rdAction":"None", + "desc":"Set bits to 1 if interrupt should be enabled.", + "group":"enables_0", + "groupDesc":"None", + "volatile":false, + "hasReset":false, + "enumerations":{ + + } + }, + { + "byteOffset":"0x2000", + "bitOffset":23, + "bitWidth":1, + "name":"enables_22", + "resetValue":0, + "accessType":"RW", + "wrType":"None", + "rdAction":"None", + "desc":"Set bits to 1 if interrupt should be enabled.", + "group":"enables_0", + "groupDesc":"None", + "volatile":false, + "hasReset":false, + "enumerations":{ + + } + }, + { + "byteOffset":"0x2000", + "bitOffset":24, + "bitWidth":1, + "name":"enables_23", + "resetValue":0, + "accessType":"RW", + "wrType":"None", + "rdAction":"None", + "desc":"Set bits to 1 if interrupt should be enabled.", + "group":"enables_0", + "groupDesc":"None", + "volatile":false, + "hasReset":false, + "enumerations":{ + + } + }, + { + "byteOffset":"0x2000", + "bitOffset":25, + "bitWidth":1, + "name":"enables_24", + "resetValue":0, + "accessType":"RW", + "wrType":"None", + "rdAction":"None", + "desc":"Set bits to 1 if interrupt should be enabled.", + "group":"enables_0", + "groupDesc":"None", + "volatile":false, + "hasReset":false, + "enumerations":{ + + } + }, + { + "byteOffset":"0x2000", + "bitOffset":26, + "bitWidth":1, + "name":"enables_25", + "resetValue":0, + "accessType":"RW", + "wrType":"None", + "rdAction":"None", + "desc":"Set bits to 1 if interrupt should be enabled.", + "group":"enables_0", + "groupDesc":"None", + "volatile":false, + "hasReset":false, + "enumerations":{ + + } + }, + { + "byteOffset":"0x2000", + "bitOffset":27, + "bitWidth":1, + "name":"enables_26", + "resetValue":0, + "accessType":"RW", + "wrType":"None", + "rdAction":"None", + "desc":"Set bits to 1 if interrupt should be enabled.", + "group":"enables_0", + "groupDesc":"None", + "volatile":false, + "hasReset":false, + "enumerations":{ + + } + }, + { + "byteOffset":"0x2000", + "bitOffset":28, + "bitWidth":1, + "name":"enables_27", + "resetValue":0, + "accessType":"RW", + "wrType":"None", + "rdAction":"None", + "desc":"Set bits to 1 if interrupt should be enabled.", + "group":"enables_0", + "groupDesc":"None", + "volatile":false, + "hasReset":false, + "enumerations":{ + + } + }, + { + "byteOffset":"0x2000", + "bitOffset":29, + "bitWidth":1, + "name":"enables_28", + "resetValue":0, + "accessType":"RW", + "wrType":"None", + "rdAction":"None", + "desc":"Set bits to 1 if interrupt should be enabled.", + "group":"enables_0", + "groupDesc":"None", + "volatile":false, + "hasReset":false, + "enumerations":{ + + } + }, + { + "byteOffset":"0x2000", + "bitOffset":30, + "bitWidth":1, + "name":"enables_29", + "resetValue":0, + "accessType":"RW", + "wrType":"None", + "rdAction":"None", + "desc":"Set bits to 1 if interrupt should be enabled.", + "group":"enables_0", + "groupDesc":"None", + "volatile":false, + "hasReset":false, + "enumerations":{ + + } + }, + { + "byteOffset":"0x2000", + "bitOffset":31, + "bitWidth":1, + "name":"enables_30", + "resetValue":0, + "accessType":"RW", + "wrType":"None", + "rdAction":"None", + "desc":"Set bits to 1 if interrupt should be enabled.", + "group":"enables_0", + "groupDesc":"None", + "volatile":false, + "hasReset":false, + "enumerations":{ + + } + }, + { + "byteOffset":"0x200000", + "bitOffset":0, + "bitWidth":32, + "name":"threshold_0", + "resetValue":0, + "accessType":"RW", + "wrType":"None", + "rdAction":"None", + "desc":"Interrupt & claim threshold for target 0. Maximum value is 8.", + "group":"hart_0", + "groupDesc":"hart_0", + "volatile":false, + "hasReset":false, + "enumerations":{ + + } + }, + { + "byteOffset":"0x200000", + "bitOffset":32, + "bitWidth":32, + "name":"claim_complete_0", + "resetValue":0, + "accessType":"RW", + "wrType":"Some(MODIFY)", + "rdAction":"Some(MODIFY)", + "desc":"Claim/Complete register for Target 0. Reading this register returns the claimed interrupt number and makes it no longer pending.Writing the interrupt number back completes the interrupt.", + "group":"hart_0", + "groupDesc":"None", + "volatile":true, + "hasReset":false, + "enumerations":{ + + } + } + ] + } }, { - "class":"firrtl.transforms.DontTouchAnnotation", - "target":"~Rift2Chip|diff>io_csr_pmpaddr_0" + "class":"firrtl.transforms.BlackBoxInlineAnno", + "target":"Rift2Chip.plusarg_reader_6", + "name":"plusarg_reader.v", + "text":"// See LICENSE.SiFive for license details.\n\n//VCS coverage exclude_file\n\n// No default parameter values are intended, nor does IEEE 1800-2012 require them (clause A.2.4 param_assignment),\n// but Incisive demands them. These default values should never be used.\nmodule plusarg_reader #(\n parameter FORMAT=\"borked=%d\",\n parameter WIDTH=1,\n parameter [WIDTH-1:0] DEFAULT=0\n) (\n output [WIDTH-1:0] out\n);\n\n`ifdef SYNTHESIS\nassign out = DEFAULT;\n`else\nreg [WIDTH-1:0] myplus;\nassign out = myplus;\n\ninitial begin\n if (!$value$plusargs(FORMAT, myplus)) myplus = DEFAULT;\nend\n`endif\n\nendmodule\n" }, { - "class":"firrtl.transforms.DontTouchAnnotation", - "target":"~Rift2Chip|diff>io_csr_pmpaddr_1" + "class":"firrtl.transforms.BlackBoxInlineAnno", + "target":"Rift2Chip.plusarg_reader_7", + "name":"plusarg_reader.v", + "text":"// See LICENSE.SiFive for license details.\n\n//VCS coverage exclude_file\n\n// No default parameter values are intended, nor does IEEE 1800-2012 require them (clause A.2.4 param_assignment),\n// but Incisive demands them. These default values should never be used.\nmodule plusarg_reader #(\n parameter FORMAT=\"borked=%d\",\n parameter WIDTH=1,\n parameter [WIDTH-1:0] DEFAULT=0\n) (\n output [WIDTH-1:0] out\n);\n\n`ifdef SYNTHESIS\nassign out = DEFAULT;\n`else\nreg [WIDTH-1:0] myplus;\nassign out = myplus;\n\ninitial begin\n if (!$value$plusargs(FORMAT, myplus)) myplus = DEFAULT;\nend\n`endif\n\nendmodule\n" }, { - "class":"firrtl.transforms.DontTouchAnnotation", - "target":"~Rift2Chip|diff>io_csr_pmpaddr_2" + "class":"freechips.rocketchip.util.SRAMAnnotation", + "target":"Rift2Chip.Directory.cc_dir", + "address_width":6, + "name":"cc_dir", + "data_width":50, + "depth":64, + "description":"Directory RAM", + "write_mask_granularity":25 }, { - "class":"firrtl.transforms.DontTouchAnnotation", - "target":"~Rift2Chip|diff>io_csr_pmpaddr_3" + "class":"freechips.rocketchip.util.SRAMAnnotation", + "target":"Rift2Chip.BankedStore.cc_banks_0", + "address_width":6, + "name":"cc_banks_0", + "data_width":64, + "depth":64, + "description":"Banked Store", + "write_mask_granularity":64 }, { - "class":"firrtl.transforms.DontTouchAnnotation", - "target":"~Rift2Chip|diff>io_csr_pmpaddr_4" + "class":"freechips.rocketchip.util.SRAMAnnotation", + "target":"Rift2Chip.BankedStore.cc_banks_1", + "address_width":6, + "name":"cc_banks_1", + "data_width":64, + "depth":64, + "description":"Banked Store", + "write_mask_granularity":64 }, { - "class":"firrtl.transforms.DontTouchAnnotation", - "target":"~Rift2Chip|diff>io_csr_pmpaddr_5" + "class":"freechips.rocketchip.util.SRAMAnnotation", + "target":"Rift2Chip.BankedStore.cc_banks_2", + "address_width":6, + "name":"cc_banks_2", + "data_width":64, + "depth":64, + "description":"Banked Store", + "write_mask_granularity":64 }, { - "class":"firrtl.transforms.DontTouchAnnotation", - "target":"~Rift2Chip|diff>io_csr_pmpaddr_6" + "class":"freechips.rocketchip.util.SRAMAnnotation", + "target":"Rift2Chip.BankedStore.cc_banks_3", + "address_width":6, + "name":"cc_banks_3", + "data_width":64, + "depth":64, + "description":"Banked Store", + "write_mask_granularity":64 }, { - "class":"firrtl.transforms.DontTouchAnnotation", - "target":"~Rift2Chip|diff>io_csr_pmpaddr_7" + "class":"firrtl.transforms.BlackBoxInlineAnno", + "target":"Rift2Chip.plusarg_reader_8", + "name":"plusarg_reader.v", + "text":"// See LICENSE.SiFive for license details.\n\n//VCS coverage exclude_file\n\n// No default parameter values are intended, nor does IEEE 1800-2012 require them (clause A.2.4 param_assignment),\n// but Incisive demands them. These default values should never be used.\nmodule plusarg_reader #(\n parameter FORMAT=\"borked=%d\",\n parameter WIDTH=1,\n parameter [WIDTH-1:0] DEFAULT=0\n) (\n output [WIDTH-1:0] out\n);\n\n`ifdef SYNTHESIS\nassign out = DEFAULT;\n`else\nreg [WIDTH-1:0] myplus;\nassign out = myplus;\n\ninitial begin\n if (!$value$plusargs(FORMAT, myplus)) myplus = DEFAULT;\nend\n`endif\n\nendmodule\n" }, { - "class":"firrtl.transforms.DontTouchAnnotation", - "target":"~Rift2Chip|diff>io_csr_stvec" + "class":"firrtl.transforms.BlackBoxInlineAnno", + "target":"Rift2Chip.plusarg_reader_9", + "name":"plusarg_reader.v", + "text":"// See LICENSE.SiFive for license details.\n\n//VCS coverage exclude_file\n\n// No default parameter values are intended, nor does IEEE 1800-2012 require them (clause A.2.4 param_assignment),\n// but Incisive demands them. These default values should never be used.\nmodule plusarg_reader #(\n parameter FORMAT=\"borked=%d\",\n parameter WIDTH=1,\n parameter [WIDTH-1:0] DEFAULT=0\n) (\n output [WIDTH-1:0] out\n);\n\n`ifdef SYNTHESIS\nassign out = DEFAULT;\n`else\nreg [WIDTH-1:0] myplus;\nassign out = myplus;\n\ninitial begin\n if (!$value$plusargs(FORMAT, myplus)) myplus = DEFAULT;\nend\n`endif\n\nendmodule\n" }, { - "class":"firrtl.transforms.DontTouchAnnotation", - "target":"~Rift2Chip|diff>io_csr_sscratch" + "class":"firrtl.transforms.BlackBoxInlineAnno", + "target":"Rift2Chip.plusarg_reader_10", + "name":"plusarg_reader.v", + "text":"// See LICENSE.SiFive for license details.\n\n//VCS coverage exclude_file\n\n// No default parameter values are intended, nor does IEEE 1800-2012 require them (clause A.2.4 param_assignment),\n// but Incisive demands them. These default values should never be used.\nmodule plusarg_reader #(\n parameter FORMAT=\"borked=%d\",\n parameter WIDTH=1,\n parameter [WIDTH-1:0] DEFAULT=0\n) (\n output [WIDTH-1:0] out\n);\n\n`ifdef SYNTHESIS\nassign out = DEFAULT;\n`else\nreg [WIDTH-1:0] myplus;\nassign out = myplus;\n\ninitial begin\n if (!$value$plusargs(FORMAT, myplus)) myplus = DEFAULT;\nend\n`endif\n\nendmodule\n" }, { - "class":"firrtl.transforms.DontTouchAnnotation", - "target":"~Rift2Chip|diff>io_csr_sepc" + "class":"firrtl.transforms.BlackBoxInlineAnno", + "target":"Rift2Chip.plusarg_reader_11", + "name":"plusarg_reader.v", + "text":"// See LICENSE.SiFive for license details.\n\n//VCS coverage exclude_file\n\n// No default parameter values are intended, nor does IEEE 1800-2012 require them (clause A.2.4 param_assignment),\n// but Incisive demands them. These default values should never be used.\nmodule plusarg_reader #(\n parameter FORMAT=\"borked=%d\",\n parameter WIDTH=1,\n parameter [WIDTH-1:0] DEFAULT=0\n) (\n output [WIDTH-1:0] out\n);\n\n`ifdef SYNTHESIS\nassign out = DEFAULT;\n`else\nreg [WIDTH-1:0] myplus;\nassign out = myplus;\n\ninitial begin\n if (!$value$plusargs(FORMAT, myplus)) myplus = DEFAULT;\nend\n`endif\n\nendmodule\n" }, { - "class":"firrtl.transforms.DontTouchAnnotation", - "target":"~Rift2Chip|diff>io_csr_scause" + "class":"firrtl.transforms.BlackBoxInlineAnno", + "target":"Rift2Chip.plusarg_reader_12", + "name":"plusarg_reader.v", + "text":"// See LICENSE.SiFive for license details.\n\n//VCS coverage exclude_file\n\n// No default parameter values are intended, nor does IEEE 1800-2012 require them (clause A.2.4 param_assignment),\n// but Incisive demands them. These default values should never be used.\nmodule plusarg_reader #(\n parameter FORMAT=\"borked=%d\",\n parameter WIDTH=1,\n parameter [WIDTH-1:0] DEFAULT=0\n) (\n output [WIDTH-1:0] out\n);\n\n`ifdef SYNTHESIS\nassign out = DEFAULT;\n`else\nreg [WIDTH-1:0] myplus;\nassign out = myplus;\n\ninitial begin\n if (!$value$plusargs(FORMAT, myplus)) myplus = DEFAULT;\nend\n`endif\n\nendmodule\n" }, { - "class":"firrtl.transforms.DontTouchAnnotation", - "target":"~Rift2Chip|diff>io_csr_stval" + "class":"firrtl.transforms.BlackBoxInlineAnno", + "target":"Rift2Chip.plusarg_reader_13", + "name":"plusarg_reader.v", + "text":"// See LICENSE.SiFive for license details.\n\n//VCS coverage exclude_file\n\n// No default parameter values are intended, nor does IEEE 1800-2012 require them (clause A.2.4 param_assignment),\n// but Incisive demands them. These default values should never be used.\nmodule plusarg_reader #(\n parameter FORMAT=\"borked=%d\",\n parameter WIDTH=1,\n parameter [WIDTH-1:0] DEFAULT=0\n) (\n output [WIDTH-1:0] out\n);\n\n`ifdef SYNTHESIS\nassign out = DEFAULT;\n`else\nreg [WIDTH-1:0] myplus;\nassign out = myplus;\n\ninitial begin\n if (!$value$plusargs(FORMAT, myplus)) myplus = DEFAULT;\nend\n`endif\n\nendmodule\n" }, { - "class":"firrtl.transforms.DontTouchAnnotation", - "target":"~Rift2Chip|diff>io_csr_satp" + "class":"firrtl.transforms.BlackBoxInlineAnno", + "target":"Rift2Chip.plusarg_reader_14", + "name":"plusarg_reader.v", + "text":"// See LICENSE.SiFive for license details.\n\n//VCS coverage exclude_file\n\n// No default parameter values are intended, nor does IEEE 1800-2012 require them (clause A.2.4 param_assignment),\n// but Incisive demands them. These default values should never be used.\nmodule plusarg_reader #(\n parameter FORMAT=\"borked=%d\",\n parameter WIDTH=1,\n parameter [WIDTH-1:0] DEFAULT=0\n) (\n output [WIDTH-1:0] out\n);\n\n`ifdef SYNTHESIS\nassign out = DEFAULT;\n`else\nreg [WIDTH-1:0] myplus;\nassign out = myplus;\n\ninitial begin\n if (!$value$plusargs(FORMAT, myplus)) myplus = DEFAULT;\nend\n`endif\n\nendmodule\n" }, { - "class":"firrtl.transforms.DontTouchAnnotation", - "target":"~Rift2Chip|diff>io_csr_fflags" + "class":"firrtl.transforms.BlackBoxInlineAnno", + "target":"Rift2Chip.plusarg_reader_15", + "name":"plusarg_reader.v", + "text":"// See LICENSE.SiFive for license details.\n\n//VCS coverage exclude_file\n\n// No default parameter values are intended, nor does IEEE 1800-2012 require them (clause A.2.4 param_assignment),\n// but Incisive demands them. These default values should never be used.\nmodule plusarg_reader #(\n parameter FORMAT=\"borked=%d\",\n parameter WIDTH=1,\n parameter [WIDTH-1:0] DEFAULT=0\n) (\n output [WIDTH-1:0] out\n);\n\n`ifdef SYNTHESIS\nassign out = DEFAULT;\n`else\nreg [WIDTH-1:0] myplus;\nassign out = myplus;\n\ninitial begin\n if (!$value$plusargs(FORMAT, myplus)) myplus = DEFAULT;\nend\n`endif\n\nendmodule\n" }, { - "class":"firrtl.transforms.DontTouchAnnotation", - "target":"~Rift2Chip|diff>io_csr_frm" + "class":"firrtl.transforms.BlackBoxInlineAnno", + "target":"Rift2Chip.plusarg_reader_16", + "name":"plusarg_reader.v", + "text":"// See LICENSE.SiFive for license details.\n\n//VCS coverage exclude_file\n\n// No default parameter values are intended, nor does IEEE 1800-2012 require them (clause A.2.4 param_assignment),\n// but Incisive demands them. These default values should never be used.\nmodule plusarg_reader #(\n parameter FORMAT=\"borked=%d\",\n parameter WIDTH=1,\n parameter [WIDTH-1:0] DEFAULT=0\n) (\n output [WIDTH-1:0] out\n);\n\n`ifdef SYNTHESIS\nassign out = DEFAULT;\n`else\nreg [WIDTH-1:0] myplus;\nassign out = myplus;\n\ninitial begin\n if (!$value$plusargs(FORMAT, myplus)) myplus = DEFAULT;\nend\n`endif\n\nendmodule\n" }, { - "class":"firrtl.transforms.DontTouchAnnotation", - "target":"~Rift2Chip|diff>io_csr_mcycle" + "class":"firrtl.transforms.BlackBoxInlineAnno", + "target":"Rift2Chip.plusarg_reader_17", + "name":"plusarg_reader.v", + "text":"// See LICENSE.SiFive for license details.\n\n//VCS coverage exclude_file\n\n// No default parameter values are intended, nor does IEEE 1800-2012 require them (clause A.2.4 param_assignment),\n// but Incisive demands them. These default values should never be used.\nmodule plusarg_reader #(\n parameter FORMAT=\"borked=%d\",\n parameter WIDTH=1,\n parameter [WIDTH-1:0] DEFAULT=0\n) (\n output [WIDTH-1:0] out\n);\n\n`ifdef SYNTHESIS\nassign out = DEFAULT;\n`else\nreg [WIDTH-1:0] myplus;\nassign out = myplus;\n\ninitial begin\n if (!$value$plusargs(FORMAT, myplus)) myplus = DEFAULT;\nend\n`endif\n\nendmodule\n" }, { - "class":"firrtl.transforms.DontTouchAnnotation", - "target":"~Rift2Chip|diff>io_csr_minstret" + "class":"firrtl.transforms.BlackBoxInlineAnno", + "target":"Rift2Chip.plusarg_reader_18", + "name":"plusarg_reader.v", + "text":"// See LICENSE.SiFive for license details.\n\n//VCS coverage exclude_file\n\n// No default parameter values are intended, nor does IEEE 1800-2012 require them (clause A.2.4 param_assignment),\n// but Incisive demands them. These default values should never be used.\nmodule plusarg_reader #(\n parameter FORMAT=\"borked=%d\",\n parameter WIDTH=1,\n parameter [WIDTH-1:0] DEFAULT=0\n) (\n output [WIDTH-1:0] out\n);\n\n`ifdef SYNTHESIS\nassign out = DEFAULT;\n`else\nreg [WIDTH-1:0] myplus;\nassign out = myplus;\n\ninitial begin\n if (!$value$plusargs(FORMAT, myplus)) myplus = DEFAULT;\nend\n`endif\n\nendmodule\n" }, { - "class":"firrtl.transforms.DontTouchAnnotation", - "target":"~Rift2Chip|diff>io_csr_mhpmcounter_0" + "class":"firrtl.transforms.BlackBoxInlineAnno", + "target":"Rift2Chip.plusarg_reader_19", + "name":"plusarg_reader.v", + "text":"// See LICENSE.SiFive for license details.\n\n//VCS coverage exclude_file\n\n// No default parameter values are intended, nor does IEEE 1800-2012 require them (clause A.2.4 param_assignment),\n// but Incisive demands them. These default values should never be used.\nmodule plusarg_reader #(\n parameter FORMAT=\"borked=%d\",\n parameter WIDTH=1,\n parameter [WIDTH-1:0] DEFAULT=0\n) (\n output [WIDTH-1:0] out\n);\n\n`ifdef SYNTHESIS\nassign out = DEFAULT;\n`else\nreg [WIDTH-1:0] myplus;\nassign out = myplus;\n\ninitial begin\n if (!$value$plusargs(FORMAT, myplus)) myplus = DEFAULT;\nend\n`endif\n\nendmodule\n" }, { - "class":"firrtl.transforms.DontTouchAnnotation", - "target":"~Rift2Chip|diff>io_csr_mhpmcounter_1" + "class":"firrtl.transforms.BlackBoxInlineAnno", + "target":"Rift2Chip.plusarg_reader_20", + "name":"plusarg_reader.v", + "text":"// See LICENSE.SiFive for license details.\n\n//VCS coverage exclude_file\n\n// No default parameter values are intended, nor does IEEE 1800-2012 require them (clause A.2.4 param_assignment),\n// but Incisive demands them. These default values should never be used.\nmodule plusarg_reader #(\n parameter FORMAT=\"borked=%d\",\n parameter WIDTH=1,\n parameter [WIDTH-1:0] DEFAULT=0\n) (\n output [WIDTH-1:0] out\n);\n\n`ifdef SYNTHESIS\nassign out = DEFAULT;\n`else\nreg [WIDTH-1:0] myplus;\nassign out = myplus;\n\ninitial begin\n if (!$value$plusargs(FORMAT, myplus)) myplus = DEFAULT;\nend\n`endif\n\nendmodule\n" }, { - "class":"firrtl.transforms.DontTouchAnnotation", - "target":"~Rift2Chip|diff>io_csr_mhpmcounter_2" + "class":"firrtl.transforms.BlackBoxInlineAnno", + "target":"Rift2Chip.plusarg_reader_21", + "name":"plusarg_reader.v", + "text":"// See LICENSE.SiFive for license details.\n\n//VCS coverage exclude_file\n\n// No default parameter values are intended, nor does IEEE 1800-2012 require them (clause A.2.4 param_assignment),\n// but Incisive demands them. These default values should never be used.\nmodule plusarg_reader #(\n parameter FORMAT=\"borked=%d\",\n parameter WIDTH=1,\n parameter [WIDTH-1:0] DEFAULT=0\n) (\n output [WIDTH-1:0] out\n);\n\n`ifdef SYNTHESIS\nassign out = DEFAULT;\n`else\nreg [WIDTH-1:0] myplus;\nassign out = myplus;\n\ninitial begin\n if (!$value$plusargs(FORMAT, myplus)) myplus = DEFAULT;\nend\n`endif\n\nendmodule\n" }, { - "class":"firrtl.transforms.DontTouchAnnotation", - "target":"~Rift2Chip|diff>io_csr_mhpmcounter_3" + "class":"firrtl.transforms.BlackBoxInlineAnno", + "target":"Rift2Chip.plusarg_reader_22", + "name":"plusarg_reader.v", + "text":"// See LICENSE.SiFive for license details.\n\n//VCS coverage exclude_file\n\n// No default parameter values are intended, nor does IEEE 1800-2012 require them (clause A.2.4 param_assignment),\n// but Incisive demands them. These default values should never be used.\nmodule plusarg_reader #(\n parameter FORMAT=\"borked=%d\",\n parameter WIDTH=1,\n parameter [WIDTH-1:0] DEFAULT=0\n) (\n output [WIDTH-1:0] out\n);\n\n`ifdef SYNTHESIS\nassign out = DEFAULT;\n`else\nreg [WIDTH-1:0] myplus;\nassign out = myplus;\n\ninitial begin\n if (!$value$plusargs(FORMAT, myplus)) myplus = DEFAULT;\nend\n`endif\n\nendmodule\n" }, { - "class":"firrtl.transforms.DontTouchAnnotation", - "target":"~Rift2Chip|diff>io_csr_mhpmcounter_4" + "class":"firrtl.transforms.BlackBoxInlineAnno", + "target":"Rift2Chip.plusarg_reader_23", + "name":"plusarg_reader.v", + "text":"// See LICENSE.SiFive for license details.\n\n//VCS coverage exclude_file\n\n// No default parameter values are intended, nor does IEEE 1800-2012 require them (clause A.2.4 param_assignment),\n// but Incisive demands them. These default values should never be used.\nmodule plusarg_reader #(\n parameter FORMAT=\"borked=%d\",\n parameter WIDTH=1,\n parameter [WIDTH-1:0] DEFAULT=0\n) (\n output [WIDTH-1:0] out\n);\n\n`ifdef SYNTHESIS\nassign out = DEFAULT;\n`else\nreg [WIDTH-1:0] myplus;\nassign out = myplus;\n\ninitial begin\n if (!$value$plusargs(FORMAT, myplus)) myplus = DEFAULT;\nend\n`endif\n\nendmodule\n" }, { - "class":"firrtl.transforms.DontTouchAnnotation", - "target":"~Rift2Chip|diff>io_csr_mhpmcounter_5" + "class":"firrtl.transforms.BlackBoxInlineAnno", + "target":"Rift2Chip.plusarg_reader_24", + "name":"plusarg_reader.v", + "text":"// See LICENSE.SiFive for license details.\n\n//VCS coverage exclude_file\n\n// No default parameter values are intended, nor does IEEE 1800-2012 require them (clause A.2.4 param_assignment),\n// but Incisive demands them. These default values should never be used.\nmodule plusarg_reader #(\n parameter FORMAT=\"borked=%d\",\n parameter WIDTH=1,\n parameter [WIDTH-1:0] DEFAULT=0\n) (\n output [WIDTH-1:0] out\n);\n\n`ifdef SYNTHESIS\nassign out = DEFAULT;\n`else\nreg [WIDTH-1:0] myplus;\nassign out = myplus;\n\ninitial begin\n if (!$value$plusargs(FORMAT, myplus)) myplus = DEFAULT;\nend\n`endif\n\nendmodule\n" }, { - "class":"firrtl.transforms.DontTouchAnnotation", - "target":"~Rift2Chip|diff>io_csr_mhpmcounter_6" + "class":"firrtl.transforms.BlackBoxInlineAnno", + "target":"Rift2Chip.plusarg_reader_25", + "name":"plusarg_reader.v", + "text":"// See LICENSE.SiFive for license details.\n\n//VCS coverage exclude_file\n\n// No default parameter values are intended, nor does IEEE 1800-2012 require them (clause A.2.4 param_assignment),\n// but Incisive demands them. These default values should never be used.\nmodule plusarg_reader #(\n parameter FORMAT=\"borked=%d\",\n parameter WIDTH=1,\n parameter [WIDTH-1:0] DEFAULT=0\n) (\n output [WIDTH-1:0] out\n);\n\n`ifdef SYNTHESIS\nassign out = DEFAULT;\n`else\nreg [WIDTH-1:0] myplus;\nassign out = myplus;\n\ninitial begin\n if (!$value$plusargs(FORMAT, myplus)) myplus = DEFAULT;\nend\n`endif\n\nendmodule\n" }, { - "class":"firrtl.transforms.DontTouchAnnotation", - "target":"~Rift2Chip|diff>io_csr_mhpmcounter_7" + "class":"firrtl.transforms.BlackBoxInlineAnno", + "target":"Rift2Chip.plusarg_reader_26", + "name":"plusarg_reader.v", + "text":"// See LICENSE.SiFive for license details.\n\n//VCS coverage exclude_file\n\n// No default parameter values are intended, nor does IEEE 1800-2012 require them (clause A.2.4 param_assignment),\n// but Incisive demands them. These default values should never be used.\nmodule plusarg_reader #(\n parameter FORMAT=\"borked=%d\",\n parameter WIDTH=1,\n parameter [WIDTH-1:0] DEFAULT=0\n) (\n output [WIDTH-1:0] out\n);\n\n`ifdef SYNTHESIS\nassign out = DEFAULT;\n`else\nreg [WIDTH-1:0] myplus;\nassign out = myplus;\n\ninitial begin\n if (!$value$plusargs(FORMAT, myplus)) myplus = DEFAULT;\nend\n`endif\n\nendmodule\n" }, { - "class":"firrtl.transforms.DontTouchAnnotation", - "target":"~Rift2Chip|diff>io_csr_mhpmcounter_8" + "class":"firrtl.transforms.BlackBoxInlineAnno", + "target":"Rift2Chip.plusarg_reader_27", + "name":"plusarg_reader.v", + "text":"// See LICENSE.SiFive for license details.\n\n//VCS coverage exclude_file\n\n// No default parameter values are intended, nor does IEEE 1800-2012 require them (clause A.2.4 param_assignment),\n// but Incisive demands them. These default values should never be used.\nmodule plusarg_reader #(\n parameter FORMAT=\"borked=%d\",\n parameter WIDTH=1,\n parameter [WIDTH-1:0] DEFAULT=0\n) (\n output [WIDTH-1:0] out\n);\n\n`ifdef SYNTHESIS\nassign out = DEFAULT;\n`else\nreg [WIDTH-1:0] myplus;\nassign out = myplus;\n\ninitial begin\n if (!$value$plusargs(FORMAT, myplus)) myplus = DEFAULT;\nend\n`endif\n\nendmodule\n" }, { - "class":"firrtl.transforms.DontTouchAnnotation", - "target":"~Rift2Chip|diff>io_csr_mhpmcounter_9" + "class":"firrtl.transforms.BlackBoxInlineAnno", + "target":"Rift2Chip.plusarg_reader_28", + "name":"plusarg_reader.v", + "text":"// See LICENSE.SiFive for license details.\n\n//VCS coverage exclude_file\n\n// No default parameter values are intended, nor does IEEE 1800-2012 require them (clause A.2.4 param_assignment),\n// but Incisive demands them. These default values should never be used.\nmodule plusarg_reader #(\n parameter FORMAT=\"borked=%d\",\n parameter WIDTH=1,\n parameter [WIDTH-1:0] DEFAULT=0\n) (\n output [WIDTH-1:0] out\n);\n\n`ifdef SYNTHESIS\nassign out = DEFAULT;\n`else\nreg [WIDTH-1:0] myplus;\nassign out = myplus;\n\ninitial begin\n if (!$value$plusargs(FORMAT, myplus)) myplus = DEFAULT;\nend\n`endif\n\nendmodule\n" }, { - "class":"firrtl.transforms.DontTouchAnnotation", - "target":"~Rift2Chip|diff>io_csr_mhpmcounter_10" + "class":"firrtl.transforms.BlackBoxInlineAnno", + "target":"Rift2Chip.plusarg_reader_29", + "name":"plusarg_reader.v", + "text":"// See LICENSE.SiFive for license details.\n\n//VCS coverage exclude_file\n\n// No default parameter values are intended, nor does IEEE 1800-2012 require them (clause A.2.4 param_assignment),\n// but Incisive demands them. These default values should never be used.\nmodule plusarg_reader #(\n parameter FORMAT=\"borked=%d\",\n parameter WIDTH=1,\n parameter [WIDTH-1:0] DEFAULT=0\n) (\n output [WIDTH-1:0] out\n);\n\n`ifdef SYNTHESIS\nassign out = DEFAULT;\n`else\nreg [WIDTH-1:0] myplus;\nassign out = myplus;\n\ninitial begin\n if (!$value$plusargs(FORMAT, myplus)) myplus = DEFAULT;\nend\n`endif\n\nendmodule\n" }, { - "class":"firrtl.transforms.DontTouchAnnotation", - "target":"~Rift2Chip|diff>io_csr_mhpmcounter_11" + "class":"firrtl.transforms.BlackBoxInlineAnno", + "target":"Rift2Chip.plusarg_reader_30", + "name":"plusarg_reader.v", + "text":"// See LICENSE.SiFive for license details.\n\n//VCS coverage exclude_file\n\n// No default parameter values are intended, nor does IEEE 1800-2012 require them (clause A.2.4 param_assignment),\n// but Incisive demands them. These default values should never be used.\nmodule plusarg_reader #(\n parameter FORMAT=\"borked=%d\",\n parameter WIDTH=1,\n parameter [WIDTH-1:0] DEFAULT=0\n) (\n output [WIDTH-1:0] out\n);\n\n`ifdef SYNTHESIS\nassign out = DEFAULT;\n`else\nreg [WIDTH-1:0] myplus;\nassign out = myplus;\n\ninitial begin\n if (!$value$plusargs(FORMAT, myplus)) myplus = DEFAULT;\nend\n`endif\n\nendmodule\n" }, { - "class":"firrtl.transforms.DontTouchAnnotation", - "target":"~Rift2Chip|diff>io_csr_mhpmcounter_12" + "class":"firrtl.transforms.BlackBoxInlineAnno", + "target":"Rift2Chip.plusarg_reader_31", + "name":"plusarg_reader.v", + "text":"// See LICENSE.SiFive for license details.\n\n//VCS coverage exclude_file\n\n// No default parameter values are intended, nor does IEEE 1800-2012 require them (clause A.2.4 param_assignment),\n// but Incisive demands them. These default values should never be used.\nmodule plusarg_reader #(\n parameter FORMAT=\"borked=%d\",\n parameter WIDTH=1,\n parameter [WIDTH-1:0] DEFAULT=0\n) (\n output [WIDTH-1:0] out\n);\n\n`ifdef SYNTHESIS\nassign out = DEFAULT;\n`else\nreg [WIDTH-1:0] myplus;\nassign out = myplus;\n\ninitial begin\n if (!$value$plusargs(FORMAT, myplus)) myplus = DEFAULT;\nend\n`endif\n\nendmodule\n" }, { - "class":"firrtl.transforms.DontTouchAnnotation", - "target":"~Rift2Chip|diff>io_csr_mhpmcounter_13" + "class":"firrtl.transforms.BlackBoxInlineAnno", + "target":"Rift2Chip.plusarg_reader_32", + "name":"plusarg_reader.v", + "text":"// See LICENSE.SiFive for license details.\n\n//VCS coverage exclude_file\n\n// No default parameter values are intended, nor does IEEE 1800-2012 require them (clause A.2.4 param_assignment),\n// but Incisive demands them. These default values should never be used.\nmodule plusarg_reader #(\n parameter FORMAT=\"borked=%d\",\n parameter WIDTH=1,\n parameter [WIDTH-1:0] DEFAULT=0\n) (\n output [WIDTH-1:0] out\n);\n\n`ifdef SYNTHESIS\nassign out = DEFAULT;\n`else\nreg [WIDTH-1:0] myplus;\nassign out = myplus;\n\ninitial begin\n if (!$value$plusargs(FORMAT, myplus)) myplus = DEFAULT;\nend\n`endif\n\nendmodule\n" }, { - "class":"firrtl.transforms.DontTouchAnnotation", - "target":"~Rift2Chip|diff>io_csr_mhpmcounter_14" + "class":"firrtl.transforms.BlackBoxInlineAnno", + "target":"Rift2Chip.plusarg_reader_33", + "name":"plusarg_reader.v", + "text":"// See LICENSE.SiFive for license details.\n\n//VCS coverage exclude_file\n\n// No default parameter values are intended, nor does IEEE 1800-2012 require them (clause A.2.4 param_assignment),\n// but Incisive demands them. These default values should never be used.\nmodule plusarg_reader #(\n parameter FORMAT=\"borked=%d\",\n parameter WIDTH=1,\n parameter [WIDTH-1:0] DEFAULT=0\n) (\n output [WIDTH-1:0] out\n);\n\n`ifdef SYNTHESIS\nassign out = DEFAULT;\n`else\nreg [WIDTH-1:0] myplus;\nassign out = myplus;\n\ninitial begin\n if (!$value$plusargs(FORMAT, myplus)) myplus = DEFAULT;\nend\n`endif\n\nendmodule\n" }, { - "class":"firrtl.transforms.DontTouchAnnotation", - "target":"~Rift2Chip|diff>io_csr_mhpmcounter_15" + "class":"firrtl.passes.InlineAnnotation", + "target":"Rift2Chip.TLWidthWidget_1" }, { - "class":"firrtl.transforms.DontTouchAnnotation", - "target":"~Rift2Chip|diff>io_csr_mhpmcounter_16" + "class":"firrtl.transforms.BlackBoxInlineAnno", + "target":"Rift2Chip.plusarg_reader_34", + "name":"plusarg_reader.v", + "text":"// See LICENSE.SiFive for license details.\n\n//VCS coverage exclude_file\n\n// No default parameter values are intended, nor does IEEE 1800-2012 require them (clause A.2.4 param_assignment),\n// but Incisive demands them. These default values should never be used.\nmodule plusarg_reader #(\n parameter FORMAT=\"borked=%d\",\n parameter WIDTH=1,\n parameter [WIDTH-1:0] DEFAULT=0\n) (\n output [WIDTH-1:0] out\n);\n\n`ifdef SYNTHESIS\nassign out = DEFAULT;\n`else\nreg [WIDTH-1:0] myplus;\nassign out = myplus;\n\ninitial begin\n if (!$value$plusargs(FORMAT, myplus)) myplus = DEFAULT;\nend\n`endif\n\nendmodule\n" }, { - "class":"firrtl.transforms.DontTouchAnnotation", - "target":"~Rift2Chip|diff>io_csr_mhpmcounter_17" + "class":"firrtl.transforms.BlackBoxInlineAnno", + "target":"Rift2Chip.plusarg_reader_35", + "name":"plusarg_reader.v", + "text":"// See LICENSE.SiFive for license details.\n\n//VCS coverage exclude_file\n\n// No default parameter values are intended, nor does IEEE 1800-2012 require them (clause A.2.4 param_assignment),\n// but Incisive demands them. These default values should never be used.\nmodule plusarg_reader #(\n parameter FORMAT=\"borked=%d\",\n parameter WIDTH=1,\n parameter [WIDTH-1:0] DEFAULT=0\n) (\n output [WIDTH-1:0] out\n);\n\n`ifdef SYNTHESIS\nassign out = DEFAULT;\n`else\nreg [WIDTH-1:0] myplus;\nassign out = myplus;\n\ninitial begin\n if (!$value$plusargs(FORMAT, myplus)) myplus = DEFAULT;\nend\n`endif\n\nendmodule\n" }, { - "class":"firrtl.transforms.DontTouchAnnotation", - "target":"~Rift2Chip|diff>io_csr_mhpmcounter_18" + "class":"firrtl.transforms.BlackBoxInlineAnno", + "target":"Rift2Chip.plusarg_reader_36", + "name":"plusarg_reader.v", + "text":"// See LICENSE.SiFive for license details.\n\n//VCS coverage exclude_file\n\n// No default parameter values are intended, nor does IEEE 1800-2012 require them (clause A.2.4 param_assignment),\n// but Incisive demands them. These default values should never be used.\nmodule plusarg_reader #(\n parameter FORMAT=\"borked=%d\",\n parameter WIDTH=1,\n parameter [WIDTH-1:0] DEFAULT=0\n) (\n output [WIDTH-1:0] out\n);\n\n`ifdef SYNTHESIS\nassign out = DEFAULT;\n`else\nreg [WIDTH-1:0] myplus;\nassign out = myplus;\n\ninitial begin\n if (!$value$plusargs(FORMAT, myplus)) myplus = DEFAULT;\nend\n`endif\n\nendmodule\n" }, { - "class":"firrtl.transforms.DontTouchAnnotation", - "target":"~Rift2Chip|diff>io_csr_mhpmcounter_19" + "class":"firrtl.transforms.BlackBoxInlineAnno", + "target":"Rift2Chip.plusarg_reader_37", + "name":"plusarg_reader.v", + "text":"// See LICENSE.SiFive for license details.\n\n//VCS coverage exclude_file\n\n// No default parameter values are intended, nor does IEEE 1800-2012 require them (clause A.2.4 param_assignment),\n// but Incisive demands them. These default values should never be used.\nmodule plusarg_reader #(\n parameter FORMAT=\"borked=%d\",\n parameter WIDTH=1,\n parameter [WIDTH-1:0] DEFAULT=0\n) (\n output [WIDTH-1:0] out\n);\n\n`ifdef SYNTHESIS\nassign out = DEFAULT;\n`else\nreg [WIDTH-1:0] myplus;\nassign out = myplus;\n\ninitial begin\n if (!$value$plusargs(FORMAT, myplus)) myplus = DEFAULT;\nend\n`endif\n\nendmodule\n" }, { - "class":"firrtl.transforms.DontTouchAnnotation", - "target":"~Rift2Chip|diff>io_csr_mhpmcounter_20" + "class":"firrtl.transforms.BlackBoxInlineAnno", + "target":"Rift2Chip.plusarg_reader_38", + "name":"plusarg_reader.v", + "text":"// See LICENSE.SiFive for license details.\n\n//VCS coverage exclude_file\n\n// No default parameter values are intended, nor does IEEE 1800-2012 require them (clause A.2.4 param_assignment),\n// but Incisive demands them. These default values should never be used.\nmodule plusarg_reader #(\n parameter FORMAT=\"borked=%d\",\n parameter WIDTH=1,\n parameter [WIDTH-1:0] DEFAULT=0\n) (\n output [WIDTH-1:0] out\n);\n\n`ifdef SYNTHESIS\nassign out = DEFAULT;\n`else\nreg [WIDTH-1:0] myplus;\nassign out = myplus;\n\ninitial begin\n if (!$value$plusargs(FORMAT, myplus)) myplus = DEFAULT;\nend\n`endif\n\nendmodule\n" }, { - "class":"firrtl.transforms.DontTouchAnnotation", - "target":"~Rift2Chip|diff>io_csr_mhpmcounter_21" + "class":"firrtl.transforms.BlackBoxInlineAnno", + "target":"Rift2Chip.plusarg_reader_39", + "name":"plusarg_reader.v", + "text":"// See LICENSE.SiFive for license details.\n\n//VCS coverage exclude_file\n\n// No default parameter values are intended, nor does IEEE 1800-2012 require them (clause A.2.4 param_assignment),\n// but Incisive demands them. These default values should never be used.\nmodule plusarg_reader #(\n parameter FORMAT=\"borked=%d\",\n parameter WIDTH=1,\n parameter [WIDTH-1:0] DEFAULT=0\n) (\n output [WIDTH-1:0] out\n);\n\n`ifdef SYNTHESIS\nassign out = DEFAULT;\n`else\nreg [WIDTH-1:0] myplus;\nassign out = myplus;\n\ninitial begin\n if (!$value$plusargs(FORMAT, myplus)) myplus = DEFAULT;\nend\n`endif\n\nendmodule\n" }, { - "class":"firrtl.transforms.DontTouchAnnotation", - "target":"~Rift2Chip|diff>io_csr_mhpmcounter_22" + "class":"firrtl.transforms.BlackBoxInlineAnno", + "target":"Rift2Chip.plusarg_reader_40", + "name":"plusarg_reader.v", + "text":"// See LICENSE.SiFive for license details.\n\n//VCS coverage exclude_file\n\n// No default parameter values are intended, nor does IEEE 1800-2012 require them (clause A.2.4 param_assignment),\n// but Incisive demands them. These default values should never be used.\nmodule plusarg_reader #(\n parameter FORMAT=\"borked=%d\",\n parameter WIDTH=1,\n parameter [WIDTH-1:0] DEFAULT=0\n) (\n output [WIDTH-1:0] out\n);\n\n`ifdef SYNTHESIS\nassign out = DEFAULT;\n`else\nreg [WIDTH-1:0] myplus;\nassign out = myplus;\n\ninitial begin\n if (!$value$plusargs(FORMAT, myplus)) myplus = DEFAULT;\nend\n`endif\n\nendmodule\n" }, { - "class":"firrtl.transforms.DontTouchAnnotation", - "target":"~Rift2Chip|diff>io_csr_mhpmcounter_23" + "class":"firrtl.transforms.BlackBoxInlineAnno", + "target":"Rift2Chip.plusarg_reader_41", + "name":"plusarg_reader.v", + "text":"// See LICENSE.SiFive for license details.\n\n//VCS coverage exclude_file\n\n// No default parameter values are intended, nor does IEEE 1800-2012 require them (clause A.2.4 param_assignment),\n// but Incisive demands them. These default values should never be used.\nmodule plusarg_reader #(\n parameter FORMAT=\"borked=%d\",\n parameter WIDTH=1,\n parameter [WIDTH-1:0] DEFAULT=0\n) (\n output [WIDTH-1:0] out\n);\n\n`ifdef SYNTHESIS\nassign out = DEFAULT;\n`else\nreg [WIDTH-1:0] myplus;\nassign out = myplus;\n\ninitial begin\n if (!$value$plusargs(FORMAT, myplus)) myplus = DEFAULT;\nend\n`endif\n\nendmodule\n" }, { - "class":"firrtl.transforms.DontTouchAnnotation", - "target":"~Rift2Chip|diff>io_csr_mhpmcounter_24" + "class":"firrtl.passes.InlineAnnotation", + "target":"Rift2Chip.TLWidthWidget_2" }, { - "class":"firrtl.transforms.DontTouchAnnotation", - "target":"~Rift2Chip|diff>io_csr_mhpmcounter_25" + "class":"firrtl.transforms.BlackBoxInlineAnno", + "target":"Rift2Chip.plusarg_reader_42", + "name":"plusarg_reader.v", + "text":"// See LICENSE.SiFive for license details.\n\n//VCS coverage exclude_file\n\n// No default parameter values are intended, nor does IEEE 1800-2012 require them (clause A.2.4 param_assignment),\n// but Incisive demands them. These default values should never be used.\nmodule plusarg_reader #(\n parameter FORMAT=\"borked=%d\",\n parameter WIDTH=1,\n parameter [WIDTH-1:0] DEFAULT=0\n) (\n output [WIDTH-1:0] out\n);\n\n`ifdef SYNTHESIS\nassign out = DEFAULT;\n`else\nreg [WIDTH-1:0] myplus;\nassign out = myplus;\n\ninitial begin\n if (!$value$plusargs(FORMAT, myplus)) myplus = DEFAULT;\nend\n`endif\n\nendmodule\n" }, { - "class":"firrtl.transforms.DontTouchAnnotation", - "target":"~Rift2Chip|diff>io_csr_mhpmcounter_26" + "class":"firrtl.transforms.BlackBoxInlineAnno", + "target":"Rift2Chip.plusarg_reader_43", + "name":"plusarg_reader.v", + "text":"// See LICENSE.SiFive for license details.\n\n//VCS coverage exclude_file\n\n// No default parameter values are intended, nor does IEEE 1800-2012 require them (clause A.2.4 param_assignment),\n// but Incisive demands them. These default values should never be used.\nmodule plusarg_reader #(\n parameter FORMAT=\"borked=%d\",\n parameter WIDTH=1,\n parameter [WIDTH-1:0] DEFAULT=0\n) (\n output [WIDTH-1:0] out\n);\n\n`ifdef SYNTHESIS\nassign out = DEFAULT;\n`else\nreg [WIDTH-1:0] myplus;\nassign out = myplus;\n\ninitial begin\n if (!$value$plusargs(FORMAT, myplus)) myplus = DEFAULT;\nend\n`endif\n\nendmodule\n" }, { - "class":"firrtl.transforms.DontTouchAnnotation", - "target":"~Rift2Chip|diff>io_csr_mhpmcounter_27" + "class":"firrtl.passes.InlineAnnotation", + "target":"Rift2Chip.TLWidthWidget_3" }, { - "class":"firrtl.transforms.DontTouchAnnotation", - "target":"~Rift2Chip|diff>io_csr_mhpmcounter_28" + "class":"firrtl.transforms.BlackBoxInlineAnno", + "target":"Rift2Chip.plusarg_reader_44", + "name":"plusarg_reader.v", + "text":"// See LICENSE.SiFive for license details.\n\n//VCS coverage exclude_file\n\n// No default parameter values are intended, nor does IEEE 1800-2012 require them (clause A.2.4 param_assignment),\n// but Incisive demands them. These default values should never be used.\nmodule plusarg_reader #(\n parameter FORMAT=\"borked=%d\",\n parameter WIDTH=1,\n parameter [WIDTH-1:0] DEFAULT=0\n) (\n output [WIDTH-1:0] out\n);\n\n`ifdef SYNTHESIS\nassign out = DEFAULT;\n`else\nreg [WIDTH-1:0] myplus;\nassign out = myplus;\n\ninitial begin\n if (!$value$plusargs(FORMAT, myplus)) myplus = DEFAULT;\nend\n`endif\n\nendmodule\n" }, { - "class":"firrtl.transforms.DontTouchAnnotation", - "target":"~Rift2Chip|diff>io_csr_mhpmcounter_29" + "class":"firrtl.transforms.BlackBoxInlineAnno", + "target":"Rift2Chip.plusarg_reader_45", + "name":"plusarg_reader.v", + "text":"// See LICENSE.SiFive for license details.\n\n//VCS coverage exclude_file\n\n// No default parameter values are intended, nor does IEEE 1800-2012 require them (clause A.2.4 param_assignment),\n// but Incisive demands them. These default values should never be used.\nmodule plusarg_reader #(\n parameter FORMAT=\"borked=%d\",\n parameter WIDTH=1,\n parameter [WIDTH-1:0] DEFAULT=0\n) (\n output [WIDTH-1:0] out\n);\n\n`ifdef SYNTHESIS\nassign out = DEFAULT;\n`else\nreg [WIDTH-1:0] myplus;\nassign out = myplus;\n\ninitial begin\n if (!$value$plusargs(FORMAT, myplus)) myplus = DEFAULT;\nend\n`endif\n\nendmodule\n" }, { - "class":"firrtl.transforms.DontTouchAnnotation", - "target":"~Rift2Chip|diff>io_csr_mhpmcounter_30" + "class":"firrtl.transforms.BlackBoxInlineAnno", + "target":"Rift2Chip.plusarg_reader_46", + "name":"plusarg_reader.v", + "text":"// See LICENSE.SiFive for license details.\n\n//VCS coverage exclude_file\n\n// No default parameter values are intended, nor does IEEE 1800-2012 require them (clause A.2.4 param_assignment),\n// but Incisive demands them. These default values should never be used.\nmodule plusarg_reader #(\n parameter FORMAT=\"borked=%d\",\n parameter WIDTH=1,\n parameter [WIDTH-1:0] DEFAULT=0\n) (\n output [WIDTH-1:0] out\n);\n\n`ifdef SYNTHESIS\nassign out = DEFAULT;\n`else\nreg [WIDTH-1:0] myplus;\nassign out = myplus;\n\ninitial begin\n if (!$value$plusargs(FORMAT, myplus)) myplus = DEFAULT;\nend\n`endif\n\nendmodule\n" }, { - "class":"firrtl.transforms.DontTouchAnnotation", - "target":"~Rift2Chip|diff>io_csr_mhpmcounter_31" + "class":"firrtl.transforms.BlackBoxInlineAnno", + "target":"Rift2Chip.plusarg_reader_47", + "name":"plusarg_reader.v", + "text":"// See LICENSE.SiFive for license details.\n\n//VCS coverage exclude_file\n\n// No default parameter values are intended, nor does IEEE 1800-2012 require them (clause A.2.4 param_assignment),\n// but Incisive demands them. These default values should never be used.\nmodule plusarg_reader #(\n parameter FORMAT=\"borked=%d\",\n parameter WIDTH=1,\n parameter [WIDTH-1:0] DEFAULT=0\n) (\n output [WIDTH-1:0] out\n);\n\n`ifdef SYNTHESIS\nassign out = DEFAULT;\n`else\nreg [WIDTH-1:0] myplus;\nassign out = myplus;\n\ninitial begin\n if (!$value$plusargs(FORMAT, myplus)) myplus = DEFAULT;\nend\n`endif\n\nendmodule\n" }, { - "class":"firrtl.transforms.DontTouchAnnotation", - "target":"~Rift2Chip|SRT4Divider>dividendIdx" + "class":"firrtl.transforms.BlackBoxInlineAnno", + "target":"Rift2Chip.plusarg_reader_48", + "name":"plusarg_reader.v", + "text":"// See LICENSE.SiFive for license details.\n\n//VCS coverage exclude_file\n\n// No default parameter values are intended, nor does IEEE 1800-2012 require them (clause A.2.4 param_assignment),\n// but Incisive demands them. These default values should never be used.\nmodule plusarg_reader #(\n parameter FORMAT=\"borked=%d\",\n parameter WIDTH=1,\n parameter [WIDTH-1:0] DEFAULT=0\n) (\n output [WIDTH-1:0] out\n);\n\n`ifdef SYNTHESIS\nassign out = DEFAULT;\n`else\nreg [WIDTH-1:0] myplus;\nassign out = myplus;\n\ninitial begin\n if (!$value$plusargs(FORMAT, myplus)) myplus = DEFAULT;\nend\n`endif\n\nendmodule\n" }, { - "class":"firrtl.transforms.DontTouchAnnotation", - "target":"~Rift2Chip|Issue>bufReqNum_0_0" + "class":"firrtl.transforms.BlackBoxInlineAnno", + "target":"Rift2Chip.plusarg_reader_49", + "name":"plusarg_reader.v", + "text":"// See LICENSE.SiFive for license details.\n\n//VCS coverage exclude_file\n\n// No default parameter values are intended, nor does IEEE 1800-2012 require them (clause A.2.4 param_assignment),\n// but Incisive demands them. These default values should never be used.\nmodule plusarg_reader #(\n parameter FORMAT=\"borked=%d\",\n parameter WIDTH=1,\n parameter [WIDTH-1:0] DEFAULT=0\n) (\n output [WIDTH-1:0] out\n);\n\n`ifdef SYNTHESIS\nassign out = DEFAULT;\n`else\nreg [WIDTH-1:0] myplus;\nassign out = myplus;\n\ninitial begin\n if (!$value$plusargs(FORMAT, myplus)) myplus = DEFAULT;\nend\n`endif\n\nendmodule\n" }, { - "class":"firrtl.transforms.DontTouchAnnotation", - "target":"~Rift2Chip|Issue>bufReqNum_0_1" + "class":"firrtl.transforms.BlackBoxInlineAnno", + "target":"Rift2Chip.plusarg_reader_50", + "name":"plusarg_reader.v", + "text":"// See LICENSE.SiFive for license details.\n\n//VCS coverage exclude_file\n\n// No default parameter values are intended, nor does IEEE 1800-2012 require them (clause A.2.4 param_assignment),\n// but Incisive demands them. These default values should never be used.\nmodule plusarg_reader #(\n parameter FORMAT=\"borked=%d\",\n parameter WIDTH=1,\n parameter [WIDTH-1:0] DEFAULT=0\n) (\n output [WIDTH-1:0] out\n);\n\n`ifdef SYNTHESIS\nassign out = DEFAULT;\n`else\nreg [WIDTH-1:0] myplus;\nassign out = myplus;\n\ninitial begin\n if (!$value$plusargs(FORMAT, myplus)) myplus = DEFAULT;\nend\n`endif\n\nendmodule\n" }, { - "class":"firrtl.transforms.DontTouchAnnotation", - "target":"~Rift2Chip|Issue>bufReqNum_0_2" + "class":"firrtl.transforms.BlackBoxInlineAnno", + "target":"Rift2Chip.plusarg_reader_51", + "name":"plusarg_reader.v", + "text":"// See LICENSE.SiFive for license details.\n\n//VCS coverage exclude_file\n\n// No default parameter values are intended, nor does IEEE 1800-2012 require them (clause A.2.4 param_assignment),\n// but Incisive demands them. These default values should never be used.\nmodule plusarg_reader #(\n parameter FORMAT=\"borked=%d\",\n parameter WIDTH=1,\n parameter [WIDTH-1:0] DEFAULT=0\n) (\n output [WIDTH-1:0] out\n);\n\n`ifdef SYNTHESIS\nassign out = DEFAULT;\n`else\nreg [WIDTH-1:0] myplus;\nassign out = myplus;\n\ninitial begin\n if (!$value$plusargs(FORMAT, myplus)) myplus = DEFAULT;\nend\n`endif\n\nendmodule\n" }, { - "class":"firrtl.transforms.DontTouchAnnotation", - "target":"~Rift2Chip|Issue>bufReqNum_0_3" + "class":"firrtl.transforms.BlackBoxInlineAnno", + "target":"Rift2Chip.plusarg_reader_52", + "name":"plusarg_reader.v", + "text":"// See LICENSE.SiFive for license details.\n\n//VCS coverage exclude_file\n\n// No default parameter values are intended, nor does IEEE 1800-2012 require them (clause A.2.4 param_assignment),\n// but Incisive demands them. These default values should never be used.\nmodule plusarg_reader #(\n parameter FORMAT=\"borked=%d\",\n parameter WIDTH=1,\n parameter [WIDTH-1:0] DEFAULT=0\n) (\n output [WIDTH-1:0] out\n);\n\n`ifdef SYNTHESIS\nassign out = DEFAULT;\n`else\nreg [WIDTH-1:0] myplus;\nassign out = myplus;\n\ninitial begin\n if (!$value$plusargs(FORMAT, myplus)) myplus = DEFAULT;\nend\n`endif\n\nendmodule\n" }, { - "class":"firrtl.transforms.DontTouchAnnotation", - "target":"~Rift2Chip|Issue>bufReqNum_1_0" + "class":"firrtl.transforms.BlackBoxInlineAnno", + "target":"Rift2Chip.plusarg_reader_53", + "name":"plusarg_reader.v", + "text":"// See LICENSE.SiFive for license details.\n\n//VCS coverage exclude_file\n\n// No default parameter values are intended, nor does IEEE 1800-2012 require them (clause A.2.4 param_assignment),\n// but Incisive demands them. These default values should never be used.\nmodule plusarg_reader #(\n parameter FORMAT=\"borked=%d\",\n parameter WIDTH=1,\n parameter [WIDTH-1:0] DEFAULT=0\n) (\n output [WIDTH-1:0] out\n);\n\n`ifdef SYNTHESIS\nassign out = DEFAULT;\n`else\nreg [WIDTH-1:0] myplus;\nassign out = myplus;\n\ninitial begin\n if (!$value$plusargs(FORMAT, myplus)) myplus = DEFAULT;\nend\n`endif\n\nendmodule\n" }, { - "class":"firrtl.transforms.DontTouchAnnotation", - "target":"~Rift2Chip|Issue>bufReqNum_1_1" + "class":"firrtl.transforms.BlackBoxInlineAnno", + "target":"Rift2Chip.plusarg_reader_54", + "name":"plusarg_reader.v", + "text":"// See LICENSE.SiFive for license details.\n\n//VCS coverage exclude_file\n\n// No default parameter values are intended, nor does IEEE 1800-2012 require them (clause A.2.4 param_assignment),\n// but Incisive demands them. These default values should never be used.\nmodule plusarg_reader #(\n parameter FORMAT=\"borked=%d\",\n parameter WIDTH=1,\n parameter [WIDTH-1:0] DEFAULT=0\n) (\n output [WIDTH-1:0] out\n);\n\n`ifdef SYNTHESIS\nassign out = DEFAULT;\n`else\nreg [WIDTH-1:0] myplus;\nassign out = myplus;\n\ninitial begin\n if (!$value$plusargs(FORMAT, myplus)) myplus = DEFAULT;\nend\n`endif\n\nendmodule\n" }, { - "class":"firrtl.transforms.DontTouchAnnotation", - "target":"~Rift2Chip|Issue>bufReqNum_1_2" + "class":"firrtl.transforms.BlackBoxInlineAnno", + "target":"Rift2Chip.plusarg_reader_55", + "name":"plusarg_reader.v", + "text":"// See LICENSE.SiFive for license details.\n\n//VCS coverage exclude_file\n\n// No default parameter values are intended, nor does IEEE 1800-2012 require them (clause A.2.4 param_assignment),\n// but Incisive demands them. These default values should never be used.\nmodule plusarg_reader #(\n parameter FORMAT=\"borked=%d\",\n parameter WIDTH=1,\n parameter [WIDTH-1:0] DEFAULT=0\n) (\n output [WIDTH-1:0] out\n);\n\n`ifdef SYNTHESIS\nassign out = DEFAULT;\n`else\nreg [WIDTH-1:0] myplus;\nassign out = myplus;\n\ninitial begin\n if (!$value$plusargs(FORMAT, myplus)) myplus = DEFAULT;\nend\n`endif\n\nendmodule\n" }, { - "class":"firrtl.transforms.DontTouchAnnotation", - "target":"~Rift2Chip|Issue>bufReqNum_1_3" + "class":"firrtl.transforms.BlackBoxInlineAnno", + "target":"Rift2Chip.plusarg_reader_56", + "name":"plusarg_reader.v", + "text":"// See LICENSE.SiFive for license details.\n\n//VCS coverage exclude_file\n\n// No default parameter values are intended, nor does IEEE 1800-2012 require them (clause A.2.4 param_assignment),\n// but Incisive demands them. These default values should never be used.\nmodule plusarg_reader #(\n parameter FORMAT=\"borked=%d\",\n parameter WIDTH=1,\n parameter [WIDTH-1:0] DEFAULT=0\n) (\n output [WIDTH-1:0] out\n);\n\n`ifdef SYNTHESIS\nassign out = DEFAULT;\n`else\nreg [WIDTH-1:0] myplus;\nassign out = myplus;\n\ninitial begin\n if (!$value$plusargs(FORMAT, myplus)) myplus = DEFAULT;\nend\n`endif\n\nendmodule\n" }, { - "class":"firrtl.transforms.DontTouchAnnotation", - "target":"~Rift2Chip|Issue>bufReqNum_2_0" + "class":"firrtl.transforms.BlackBoxInlineAnno", + "target":"Rift2Chip.plusarg_reader_57", + "name":"plusarg_reader.v", + "text":"// See LICENSE.SiFive for license details.\n\n//VCS coverage exclude_file\n\n// No default parameter values are intended, nor does IEEE 1800-2012 require them (clause A.2.4 param_assignment),\n// but Incisive demands them. These default values should never be used.\nmodule plusarg_reader #(\n parameter FORMAT=\"borked=%d\",\n parameter WIDTH=1,\n parameter [WIDTH-1:0] DEFAULT=0\n) (\n output [WIDTH-1:0] out\n);\n\n`ifdef SYNTHESIS\nassign out = DEFAULT;\n`else\nreg [WIDTH-1:0] myplus;\nassign out = myplus;\n\ninitial begin\n if (!$value$plusargs(FORMAT, myplus)) myplus = DEFAULT;\nend\n`endif\n\nendmodule\n" }, { - "class":"firrtl.transforms.DontTouchAnnotation", - "target":"~Rift2Chip|Issue>bufReqNum_2_1" + "class":"firrtl.transforms.BlackBoxInlineAnno", + "target":"Rift2Chip.plusarg_reader_58", + "name":"plusarg_reader.v", + "text":"// See LICENSE.SiFive for license details.\n\n//VCS coverage exclude_file\n\n// No default parameter values are intended, nor does IEEE 1800-2012 require them (clause A.2.4 param_assignment),\n// but Incisive demands them. These default values should never be used.\nmodule plusarg_reader #(\n parameter FORMAT=\"borked=%d\",\n parameter WIDTH=1,\n parameter [WIDTH-1:0] DEFAULT=0\n) (\n output [WIDTH-1:0] out\n);\n\n`ifdef SYNTHESIS\nassign out = DEFAULT;\n`else\nreg [WIDTH-1:0] myplus;\nassign out = myplus;\n\ninitial begin\n if (!$value$plusargs(FORMAT, myplus)) myplus = DEFAULT;\nend\n`endif\n\nendmodule\n" }, { - "class":"firrtl.transforms.DontTouchAnnotation", - "target":"~Rift2Chip|Issue>bufReqNum_2_2" + "class":"firrtl.transforms.BlackBoxInlineAnno", + "target":"Rift2Chip.plusarg_reader_59", + "name":"plusarg_reader.v", + "text":"// See LICENSE.SiFive for license details.\n\n//VCS coverage exclude_file\n\n// No default parameter values are intended, nor does IEEE 1800-2012 require them (clause A.2.4 param_assignment),\n// but Incisive demands them. These default values should never be used.\nmodule plusarg_reader #(\n parameter FORMAT=\"borked=%d\",\n parameter WIDTH=1,\n parameter [WIDTH-1:0] DEFAULT=0\n) (\n output [WIDTH-1:0] out\n);\n\n`ifdef SYNTHESIS\nassign out = DEFAULT;\n`else\nreg [WIDTH-1:0] myplus;\nassign out = myplus;\n\ninitial begin\n if (!$value$plusargs(FORMAT, myplus)) myplus = DEFAULT;\nend\n`endif\n\nendmodule\n" }, { - "class":"firrtl.transforms.DontTouchAnnotation", - "target":"~Rift2Chip|Issue>bufReqNum_2_3" + "class":"firrtl.transforms.BlackBoxInlineAnno", + "target":"Rift2Chip.plusarg_reader_60", + "name":"plusarg_reader.v", + "text":"// See LICENSE.SiFive for license details.\n\n//VCS coverage exclude_file\n\n// No default parameter values are intended, nor does IEEE 1800-2012 require them (clause A.2.4 param_assignment),\n// but Incisive demands them. These default values should never be used.\nmodule plusarg_reader #(\n parameter FORMAT=\"borked=%d\",\n parameter WIDTH=1,\n parameter [WIDTH-1:0] DEFAULT=0\n) (\n output [WIDTH-1:0] out\n);\n\n`ifdef SYNTHESIS\nassign out = DEFAULT;\n`else\nreg [WIDTH-1:0] myplus;\nassign out = myplus;\n\ninitial begin\n if (!$value$plusargs(FORMAT, myplus)) myplus = DEFAULT;\nend\n`endif\n\nendmodule\n" }, { - "class":"firrtl.transforms.DontTouchAnnotation", - "target":"~Rift2Chip|Issue>bufReqNum_3_0" + "class":"firrtl.transforms.BlackBoxInlineAnno", + "target":"Rift2Chip.plusarg_reader_61", + "name":"plusarg_reader.v", + "text":"// See LICENSE.SiFive for license details.\n\n//VCS coverage exclude_file\n\n// No default parameter values are intended, nor does IEEE 1800-2012 require them (clause A.2.4 param_assignment),\n// but Incisive demands them. These default values should never be used.\nmodule plusarg_reader #(\n parameter FORMAT=\"borked=%d\",\n parameter WIDTH=1,\n parameter [WIDTH-1:0] DEFAULT=0\n) (\n output [WIDTH-1:0] out\n);\n\n`ifdef SYNTHESIS\nassign out = DEFAULT;\n`else\nreg [WIDTH-1:0] myplus;\nassign out = myplus;\n\ninitial begin\n if (!$value$plusargs(FORMAT, myplus)) myplus = DEFAULT;\nend\n`endif\n\nendmodule\n" }, { - "class":"firrtl.transforms.DontTouchAnnotation", - "target":"~Rift2Chip|Issue>bufReqNum_3_1" + "class":"firrtl.transforms.BlackBoxInlineAnno", + "target":"Rift2Chip.plusarg_reader_62", + "name":"plusarg_reader.v", + "text":"// See LICENSE.SiFive for license details.\n\n//VCS coverage exclude_file\n\n// No default parameter values are intended, nor does IEEE 1800-2012 require them (clause A.2.4 param_assignment),\n// but Incisive demands them. These default values should never be used.\nmodule plusarg_reader #(\n parameter FORMAT=\"borked=%d\",\n parameter WIDTH=1,\n parameter [WIDTH-1:0] DEFAULT=0\n) (\n output [WIDTH-1:0] out\n);\n\n`ifdef SYNTHESIS\nassign out = DEFAULT;\n`else\nreg [WIDTH-1:0] myplus;\nassign out = myplus;\n\ninitial begin\n if (!$value$plusargs(FORMAT, myplus)) myplus = DEFAULT;\nend\n`endif\n\nendmodule\n" }, { - "class":"firrtl.transforms.DontTouchAnnotation", - "target":"~Rift2Chip|Issue>bufReqNum_3_2" + "class":"firrtl.transforms.BlackBoxInlineAnno", + "target":"Rift2Chip.plusarg_reader_63", + "name":"plusarg_reader.v", + "text":"// See LICENSE.SiFive for license details.\n\n//VCS coverage exclude_file\n\n// No default parameter values are intended, nor does IEEE 1800-2012 require them (clause A.2.4 param_assignment),\n// but Incisive demands them. These default values should never be used.\nmodule plusarg_reader #(\n parameter FORMAT=\"borked=%d\",\n parameter WIDTH=1,\n parameter [WIDTH-1:0] DEFAULT=0\n) (\n output [WIDTH-1:0] out\n);\n\n`ifdef SYNTHESIS\nassign out = DEFAULT;\n`else\nreg [WIDTH-1:0] myplus;\nassign out = myplus;\n\ninitial begin\n if (!$value$plusargs(FORMAT, myplus)) myplus = DEFAULT;\nend\n`endif\n\nendmodule\n" }, { - "class":"firrtl.transforms.DontTouchAnnotation", - "target":"~Rift2Chip|Issue>bufReqNum_3_3" + "class":"firrtl.transforms.BlackBoxInlineAnno", + "target":"Rift2Chip.plusarg_reader_64", + "name":"plusarg_reader.v", + "text":"// See LICENSE.SiFive for license details.\n\n//VCS coverage exclude_file\n\n// No default parameter values are intended, nor does IEEE 1800-2012 require them (clause A.2.4 param_assignment),\n// but Incisive demands them. These default values should never be used.\nmodule plusarg_reader #(\n parameter FORMAT=\"borked=%d\",\n parameter WIDTH=1,\n parameter [WIDTH-1:0] DEFAULT=0\n) (\n output [WIDTH-1:0] out\n);\n\n`ifdef SYNTHESIS\nassign out = DEFAULT;\n`else\nreg [WIDTH-1:0] myplus;\nassign out = myplus;\n\ninitial begin\n if (!$value$plusargs(FORMAT, myplus)) myplus = DEFAULT;\nend\n`endif\n\nendmodule\n" }, { - "class":"firrtl.transforms.BlackBoxTargetDirAnno", - "targetDir":"generated/Debug/Rift2330" + "class":"firrtl.transforms.BlackBoxInlineAnno", + "target":"Rift2Chip.plusarg_reader_65", + "name":"plusarg_reader.v", + "text":"// See LICENSE.SiFive for license details.\n\n//VCS coverage exclude_file\n\n// No default parameter values are intended, nor does IEEE 1800-2012 require them (clause A.2.4 param_assignment),\n// but Incisive demands them. These default values should never be used.\nmodule plusarg_reader #(\n parameter FORMAT=\"borked=%d\",\n parameter WIDTH=1,\n parameter [WIDTH-1:0] DEFAULT=0\n) (\n output [WIDTH-1:0] out\n);\n\n`ifdef SYNTHESIS\nassign out = DEFAULT;\n`else\nreg [WIDTH-1:0] myplus;\nassign out = myplus;\n\ninitial begin\n if (!$value$plusargs(FORMAT, myplus)) myplus = DEFAULT;\nend\n`endif\n\nendmodule\n" }, { - "class":"firrtl.transforms.CombinationalPath", - "sink":"~Rift2Chip|Rift2Chip>memory_0_b_ready", - "sources":[ - "~Rift2Chip|Rift2Chip>memory_0_b_bits_id" - ] + "class":"firrtl.transforms.BlackBoxInlineAnno", + "target":"Rift2Chip.plusarg_reader_66", + "name":"plusarg_reader.v", + "text":"// See LICENSE.SiFive for license details.\n\n//VCS coverage exclude_file\n\n// No default parameter values are intended, nor does IEEE 1800-2012 require them (clause A.2.4 param_assignment),\n// but Incisive demands them. These default values should never be used.\nmodule plusarg_reader #(\n parameter FORMAT=\"borked=%d\",\n parameter WIDTH=1,\n parameter [WIDTH-1:0] DEFAULT=0\n) (\n output [WIDTH-1:0] out\n);\n\n`ifdef SYNTHESIS\nassign out = DEFAULT;\n`else\nreg [WIDTH-1:0] myplus;\nassign out = myplus;\n\ninitial begin\n if (!$value$plusargs(FORMAT, myplus)) myplus = DEFAULT;\nend\n`endif\n\nendmodule\n" }, { - "class":"firrtl.transforms.CombinationalPath", - "sink":"~Rift2Chip|Rift2Chip>system_0_b_ready", - "sources":[ - "~Rift2Chip|Rift2Chip>system_0_b_bits_id", - "~Rift2Chip|Rift2Chip>system_0_b_valid" - ] + "class":"firrtl.transforms.BlackBoxInlineAnno", + "target":"Rift2Chip.plusarg_reader_67", + "name":"plusarg_reader.v", + "text":"// See LICENSE.SiFive for license details.\n\n//VCS coverage exclude_file\n\n// No default parameter values are intended, nor does IEEE 1800-2012 require them (clause A.2.4 param_assignment),\n// but Incisive demands them. These default values should never be used.\nmodule plusarg_reader #(\n parameter FORMAT=\"borked=%d\",\n parameter WIDTH=1,\n parameter [WIDTH-1:0] DEFAULT=0\n) (\n output [WIDTH-1:0] out\n);\n\n`ifdef SYNTHESIS\nassign out = DEFAULT;\n`else\nreg [WIDTH-1:0] myplus;\nassign out = myplus;\n\ninitial begin\n if (!$value$plusargs(FORMAT, myplus)) myplus = DEFAULT;\nend\n`endif\n\nendmodule\n" }, { - "class":"firrtl.transforms.CombinationalPath", - "sink":"~Rift2Chip|Rift2Chip>memory_0_r_ready", - "sources":[ - "~Rift2Chip|Rift2Chip>memory_0_r_bits_id" - ] + "class":"firrtl.transforms.BlackBoxInlineAnno", + "target":"Rift2Chip.plusarg_reader_68", + "name":"plusarg_reader.v", + "text":"// See LICENSE.SiFive for license details.\n\n//VCS coverage exclude_file\n\n// No default parameter values are intended, nor does IEEE 1800-2012 require them (clause A.2.4 param_assignment),\n// but Incisive demands them. These default values should never be used.\nmodule plusarg_reader #(\n parameter FORMAT=\"borked=%d\",\n parameter WIDTH=1,\n parameter [WIDTH-1:0] DEFAULT=0\n) (\n output [WIDTH-1:0] out\n);\n\n`ifdef SYNTHESIS\nassign out = DEFAULT;\n`else\nreg [WIDTH-1:0] myplus;\nassign out = myplus;\n\ninitial begin\n if (!$value$plusargs(FORMAT, myplus)) myplus = DEFAULT;\nend\n`endif\n\nendmodule\n" }, { - "class":"firrtl.transforms.CombinationalPath", - "sink":"~Rift2Chip|Rift2Chip>system_0_r_ready", - "sources":[ - "~Rift2Chip|Rift2Chip>system_0_r_bits_id" - ] + "class":"firrtl.transforms.BlackBoxInlineAnno", + "target":"Rift2Chip.plusarg_reader_69", + "name":"plusarg_reader.v", + "text":"// See LICENSE.SiFive for license details.\n\n//VCS coverage exclude_file\n\n// No default parameter values are intended, nor does IEEE 1800-2012 require them (clause A.2.4 param_assignment),\n// but Incisive demands them. These default values should never be used.\nmodule plusarg_reader #(\n parameter FORMAT=\"borked=%d\",\n parameter WIDTH=1,\n parameter [WIDTH-1:0] DEFAULT=0\n) (\n output [WIDTH-1:0] out\n);\n\n`ifdef SYNTHESIS\nassign out = DEFAULT;\n`else\nreg [WIDTH-1:0] myplus;\nassign out = myplus;\n\ninitial begin\n if (!$value$plusargs(FORMAT, myplus)) myplus = DEFAULT;\nend\n`endif\n\nendmodule\n" } ] \ No newline at end of file diff --git a/generated/Debug/Rift2330/coremark.json b/generated/Debug/Rift2330/coremark.json index c523dbd6..b4bdca11 100644 --- a/generated/Debug/Rift2330/coremark.json +++ b/generated/Debug/Rift2330/coremark.json @@ -1,6 +1,6 @@ { "schemaVersion": 1, "label": "", - "message": "0.358729", + "message": "0.357430", "color": "368fb4" } \ No newline at end of file diff --git a/generated/Debug/Rift2330/dhrystone.json b/generated/Debug/Rift2330/dhrystone.json index 43539da7..caf4e631 100644 --- a/generated/Debug/Rift2330/dhrystone.json +++ b/generated/Debug/Rift2330/dhrystone.json @@ -1,6 +1,6 @@ { "schemaVersion": 1, "label": "", - "message": "0.148502", + "message": "0.147082", "color": "ff69b4" } \ No newline at end of file