diff --git a/.github/workflows/BuildAndTest.yml b/.github/workflows/BuildAndTest.yml
index 1d1db3fa..35515bd9 100644
--- a/.github/workflows/BuildAndTest.yml
+++ b/.github/workflows/BuildAndTest.yml
@@ -4,7 +4,7 @@ name: ChiselStage
 on:
   # Triggers the workflow on push or pull request events but only for the master branch
   push:
-    branches: [ master, develop ]
+    branches: [ master, develop, bump/mill_chisel5 ]
   # pull_request:
   #   branches: [ master ]
 
@@ -19,14 +19,19 @@ jobs:
     runs-on: [self-hosted, Linux, X64]
     name: chiselStage
     container:
-      image: whutddk/rift2env:riscvtest
+      image: whutddk/rift2env:chisel5
+      # options: >-
+      #   --memory 60g
+      #   --oom-kill-disable
+      #   --memory-swap -1
+
     # needs: clean
     # Steps represent a sequence of tasks that will be executed as part of the job
     steps:
       - name: set up apt
         run: |
           apt-get update
-          apt-get install -y wget git make
+          apt-get install -y wget git make curl
 
 
       - uses: actions/checkout@v3.3.0
@@ -41,8 +46,11 @@ jobs:
       - name: Compile
         run: |
           echo ${GITHUB_WORKSPACE}
-          sbt "test:runMain test.testAll"
-          sbt doc
+
+          rm dependencies/rocket-chip/src/main/resources/META-INF/services/firrtl.options.RegisteredLibrary
+          mill -i rift2Core[chisel].test.runMain test.testAll
+          mill --no-server show rift2Core[chisel].docJar
+          unzip -d ScalaDoc/ out/rift2Core/chisel/docJar.dest/out.jar
 
           echo $GITHUB_REF_NAME
           
@@ -53,19 +61,19 @@ jobs:
 
           cp ${GITHUB_WORKSPACE}/LICENSE.Apache ${GITHUB_WORKSPACE}/../
           cp ${GITHUB_WORKSPACE}/LICENSE.NPL ${GITHUB_WORKSPACE}/../
-          cp -R target/scala-2.13/api ${GITHUB_WORKSPACE}/../ScalaDoc/$GITHUB_REF_NAME
-
-          cd ${GITHUB_WORKSPACE}/generated/Release/
-          tar -cvf Rift2300-Release.tar Rift2300/*
-          tar -cvf Rift2310-Release.tar Rift2310/*
-          tar -cvf Rift2320-Release.tar Rift2320/*
-          tar -cvf Rift2330-Release.tar Rift2330/*
-          tar -cvf Rift2340-Release.tar Rift2340/*
-          tar -cvf Rift2350-Release.tar Rift2350/*
-          tar -cvf Rift2360-Release.tar Rift2360/*
-          tar -cvf Rift2370-Release.tar Rift2370/*
-          tar -cvf Rift2380-Release.tar Rift2380/*
-          tar -cvf Rift2390-Release.tar Rift2390/*
+          cp -R ScalaDoc/* ${GITHUB_WORKSPACE}/../ScalaDoc/$GITHUB_REF_NAME
+
+          # cd ${GITHUB_WORKSPACE}/generated/Release/
+          # tar -cvf Rift2300-Release.tar Rift2300/*
+          # tar -cvf Rift2310-Release.tar Rift2310/*
+          # tar -cvf Rift2320-Release.tar Rift2320/*
+          # tar -cvf Rift2330-Release.tar Rift2330/*
+          # tar -cvf Rift2340-Release.tar Rift2340/*
+          # tar -cvf Rift2350-Release.tar Rift2350/*
+          # tar -cvf Rift2360-Release.tar Rift2360/*
+          # tar -cvf Rift2370-Release.tar Rift2370/*
+          # tar -cvf Rift2380-Release.tar Rift2380/*
+          # tar -cvf Rift2390-Release.tar Rift2390/*
 
           cd ${GITHUB_WORKSPACE}/generated/Debug/
           tar -cvf Rift2300-Debug.tar  Rift2300/*
@@ -89,7 +97,7 @@ jobs:
           git checkout gh_pages
 
           rm -rf ${GITHUB_WORKSPACE}/ScalaDoc/$GITHUB_REF_NAME
-          cp -R ${GITHUB_WORKSPACE}/../ScalaDoc/$GITHUB_REF_NAME ${GITHUB_WORKSPACE}/ScalaDoc/$GITHUB_REF_NAME
+          cp -R ${GITHUB_WORKSPACE}/../ScalaDoc/* ${GITHUB_WORKSPACE}/ScalaDoc/
           cp ${GITHUB_WORKSPACE}/../LICENSE.Apache ${GITHUB_WORKSPACE}/
           cp ${GITHUB_WORKSPACE}/../LICENSE.NPL ${GITHUB_WORKSPACE}/
 
@@ -124,25 +132,25 @@ jobs:
           prerelease: true
           target_commitish: ${{github.ref_name}}
           files: |
-            ./generated/Release/Rift2300-Release.tar
+            # ./generated/Release/Rift2300-Release.tar
             ./generated/Debug/Rift2300-Debug.tar
-            ./generated/Release/Rift2310-Release.tar
+            # ./generated/Release/Rift2310-Release.tar
             ./generated/Debug/Rift2310-Debug.tar
-            ./generated/Release/Rift2320-Release.tar
+            # ./generated/Release/Rift2320-Release.tar
             ./generated/Debug/Rift2320-Debug.tar
-            ./generated/Release/Rift2330-Release.tar
+            # ./generated/Release/Rift2330-Release.tar
             ./generated/Debug/Rift2330-Debug.tar
-            ./generated/Release/Rift2340-Release.tar
+            # ./generated/Release/Rift2340-Release.tar
             ./generated/Debug/Rift2340-Debug.tar
-            ./generated/Release/Rift2350-Release.tar
+            # ./generated/Release/Rift2350-Release.tar
             ./generated/Debug/Rift2350-Debug.tar
-            ./generated/Release/Rift2360-Release.tar
+            # ./generated/Release/Rift2360-Release.tar
             ./generated/Debug/Rift2360-Debug.tar
-            ./generated/Release/Rift2370-Release.tar
+            # ./generated/Release/Rift2370-Release.tar
             ./generated/Debug/Rift2370-Debug.tar
-            ./generated/Release/Rift2380-Release.tar
+            # ./generated/Release/Rift2380-Release.tar
             ./generated/Debug/Rift2380-Debug.tar
-            ./generated/Release/Rift2390-Release.tar
+            # ./generated/Release/Rift2390-Release.tar
             ./generated/Debug/Rift2390-Debug.tar
             ./LICENSE.Apache
             ./LICENSE.NPL
@@ -160,25 +168,25 @@ jobs:
           prerelease: false
           target_commitish: ${{github.ref_name}}
           files: |
-            ./generated/Release/Rift2300-Release.tar
+            # ./generated/Release/Rift2300-Release.tar
             ./generated/Debug/Rift2300-Debug.tar
-            ./generated/Release/Rift2310-Release.tar
+            # ./generated/Release/Rift2310-Release.tar
             ./generated/Debug/Rift2310-Debug.tar
-            ./generated/Release/Rift2320-Release.tar
+            # ./generated/Release/Rift2320-Release.tar
             ./generated/Debug/Rift2320-Debug.tar
-            ./generated/Release/Rift2330-Release.tar
+            # ./generated/Release/Rift2330-Release.tar
             ./generated/Debug/Rift2330-Debug.tar
-            ./generated/Release/Rift2340-Release.tar
+            # ./generated/Release/Rift2340-Release.tar
             ./generated/Debug/Rift2340-Debug.tar
-            ./generated/Release/Rift2350-Release.tar
+            # ./generated/Release/Rift2350-Release.tar
             ./generated/Debug/Rift2350-Debug.tar
-            ./generated/Release/Rift2360-Release.tar
+            # ./generated/Release/Rift2360-Release.tar
             ./generated/Debug/Rift2360-Debug.tar
-            ./generated/Release/Rift2370-Release.tar
+            # ./generated/Release/Rift2370-Release.tar
             ./generated/Debug/Rift2370-Debug.tar
-            ./generated/Release/Rift2380-Release.tar
+            # ./generated/Release/Rift2380-Release.tar
             ./generated/Debug/Rift2380-Debug.tar
-            ./generated/Release/Rift2390-Release.tar
+            # ./generated/Release/Rift2390-Release.tar
             ./generated/Debug/Rift2390-Debug.tar
             ./LICENSE.Apache
             ./LICENSE.NPL
@@ -202,10 +210,14 @@ jobs:
     strategy:
       fail-fast: false
       matrix:
-        version: [Rift2330, Rift2340, Rift2350, Rift2360, Rift2370, Rift2380, Rift2390]
+        version: [Rift2330, Rift2370]
     runs-on: [self-hosted, Linux, X64]
     container:
-      image: whutddk/rift2env:riscvtest
+      image: whutddk/rift2env:chisel5
+      # options: >-
+      #   --memory 60g
+      #   --oom-kill-disable
+      #   --memory-swap -1
 
 
     # services:
@@ -253,7 +265,7 @@ jobs:
           cd /Rift2Core
 
           wget https://github.com/whutddk/Rift2Core/releases/download/${{ steps.getrelease.outputs.tag_name }}/${{matrix.version}}-Debug.tar
-          wget https://github.com/whutddk/Rift2Core/releases/download/${{ steps.getrelease.outputs.tag_name }}/${{matrix.version}}-Release.tar
+          # wget https://github.com/whutddk/Rift2Core/releases/download/${{ steps.getrelease.outputs.tag_name }}/${{matrix.version}}-Release.tar
 
 
 
@@ -262,10 +274,10 @@ jobs:
           cd /Rift2Core
           
           mkdir -p ./generated/Debug
-          mkdir -p ./generated/Release
+          # mkdir -p ./generated/Release
           
           tar -xvf ./${{matrix.version}}-Debug.tar -C ./generated/Debug
-          tar -xvf ./${{matrix.version}}-Release.tar -C ./generated/Release
+          # tar -xvf ./${{matrix.version}}-Release.tar -C ./generated/Release
 
 
 
@@ -276,7 +288,7 @@ jobs:
           cp /test/* ./tb/ci
           git restore -s ${{ github.ref_name }} -- ./tb
           git restore -s ${{ github.ref_name }} -- ./Makefile
-# git restore -s ${{ github.ref_name }} -- ./src/yosys/area.ys
+          # git restore -s ${{ github.ref_name }} -- ./src/yosys/area.ys
 
         
       - name: isa, dhrystone, coremark, yosys
@@ -292,7 +304,7 @@ jobs:
 
 
 
-# make area CONFIG=/Release/${{matrix.version}}/
+      # make area CONFIG=/Release/${{matrix.version}}/
 
       - name: commit result
         if: success() || failure()
@@ -304,7 +316,7 @@ jobs:
           git add ./generated/Debug/${{matrix.version}}/*.json
           git commit --no-gpg-sign --allow-empty -m "ci update ${{matrix.version}}"
 
-# git add ./generated/Release/${{matrix.version}}/area.json
+          # git add ./generated/Release/${{matrix.version}}/area.json
 
       - name: push
         if: success() || failure()
diff --git a/.gitignore b/.gitignore
index 3178f177..58d5aeee 100644
--- a/.gitignore
+++ b/.gitignore
@@ -367,3 +367,4 @@ VSimTop
 tb/sw/opensbi/fw_jump.dep
 tb/sw/opensbi/fw_jump.elf.ld
 mill
+ScalaDoc/
diff --git a/Makefile b/Makefile
index 5a742a9d..8f09db61 100644
--- a/Makefile
+++ b/Makefile
@@ -260,7 +260,7 @@ isa ?= $(aluisa) $(bruisa) $(lsuisa) $(privisa) $(mulisa)# $(fpuisa)
 
 
 
-.PHONY: compile clean VSimTop mill
+.PHONY: compile clean VSimTop mill doc
 
 module:
 	sbt "test:runMain test.testModule --target-dir generated --show-registrations --full-stacktrace -E verilog"
@@ -278,8 +278,13 @@ compile:
 
 mill:
 	rm -rf ./generated/Main/
+	./mill --no-server clean
 	./mill -i rift2Core[chisel].test.runMain test.testMain
 
+doc:
+	./mill --no-server show rift2Core[chisel].docJar
+	unzip -d ScalaDoc/ out/rift2Core/chisel/docJar.dest/out.jar
+
 noc:
 	rm -rf ./generated/Main/
 	sbt "test:runMain test.testNoC \
@@ -288,8 +293,9 @@ noc:
 
 line: 
 	rm -rf generated/Debug/
-	rm -rf generated/Release/
-	sbt "test:runMain test.testAll"
+	# rm -rf generated/Release/
+	./mill --no-server clean
+	./mill -i rift2Core[chisel].test.runMain test.testAll
 
 CONFIG ?= /Main/
 
@@ -316,7 +322,7 @@ VSimTop:
 	${R2}/tb/verilator/sim_main.cpp  \
 	${R2}/tb/verilator/diff.cpp \
 	-Mdir ./generated/build/$(CONFIG) \
-	-j 30
+	-j 1
 
 
 
diff --git a/README.md b/README.md
index afef5c02..c4c9555e 100644
--- a/README.md
+++ b/README.md
@@ -12,32 +12,29 @@
 --------------------------------------------
 
 
-Based on Chisel3, Rift2Core is a 9-stage, N-issue(Configurable), out-of-order, 64-bits RISC-V Core, which supports RV64GC and M, S, U mode.
+Based on Chisel, Rift2Core is a 9-stage, N-issue(Configurable), out-of-order, 64-bits RISC-V Core, which supports RV64GC and M, S, U mode.
 
 [RiftCore](https://github.com/whutddk/RiftCore) is the previous version of Rift2Core in Verilog.
 
 
 
 
-
-
-
-
-
 ----------------
 
 
 ## [How to Setup](doc/Setup.md)
 You can complete the deployment of the compilation and test environment following the steps below:
 * Setup Repo
-* Setup sbt
+* ~~Setup sbt~~
+* Setup mill
 * Setup verilator and gtkwave
-* Compile chisel3 to verilog
+* ~~Compile chisel3 to verilog~~
+* Compile chisel to verilog
 * Compile Model of Rif2Chip
 * Test a single ISA with waveform
 * Test all ISA without waveform
 
-Also we provide a [Docker-Image](https://hub.docker.com/repository/docker/whutddk/rift2env) mainly for CI, which can also be used for compiling and testing.
+Also we provide a [Docker-Image](https://hub.docker.com/repository/docker/whutddk/chisel5) mainly for CI, which can also be used for compiling and testing.
 
 ## [How to Config](doc/Configuration.md)
 
@@ -55,12 +52,12 @@ Download Pre-compile Version [Here](https://github.com/whutddk/Rift2Core/release
 |Rift-2310|N/A|N/A|N/A|
 |Rift-2320|N/A|N/A|N/A|
 |Rift-2330|![](https://img.shields.io/endpoint?url=https://raw.githubusercontent.com/whutddk/Rift2Core/gh_pages/generated/Debug/Rift2330/isa.json)|![](https://img.shields.io/endpoint?url=https://raw.githubusercontent.com/whutddk/Rift2Core/gh_pages/generated/Debug/Rift2330/dhrystone.json)|![](https://img.shields.io/endpoint?url=https://raw.githubusercontent.com/whutddk/Rift2Core/gh_pages/generated/Debug/Rift2330/coremark.json)|
-|Rift-2340|![](https://img.shields.io/endpoint?url=https://raw.githubusercontent.com/whutddk/Rift2Core/gh_pages/generated/Debug/Rift2340/isa.json)|![](https://img.shields.io/endpoint?url=https://raw.githubusercontent.com/whutddk/Rift2Core/gh_pages/generated/Debug/Rift2340/dhrystone.json)|![](https://img.shields.io/endpoint?url=https://raw.githubusercontent.com/whutddk/Rift2Core/gh_pages/generated/Debug/Rift2340/coremark.json)|
-|Rift-2350|![](https://img.shields.io/endpoint?url=https://raw.githubusercontent.com/whutddk/Rift2Core/gh_pages/generated/Debug/Rift2350/isa.json)|![](https://img.shields.io/endpoint?url=https://raw.githubusercontent.com/whutddk/Rift2Core/gh_pages/generated/Debug/Rift2350/dhrystone.json)|![](https://img.shields.io/endpoint?url=https://raw.githubusercontent.com/whutddk/Rift2Core/gh_pages/generated/Debug/Rift2350/coremark.json)|
-|Rift-2360|![](https://img.shields.io/endpoint?url=https://raw.githubusercontent.com/whutddk/Rift2Core/gh_pages/generated/Debug/Rift2360/isa.json)|![](https://img.shields.io/endpoint?url=https://raw.githubusercontent.com/whutddk/Rift2Core/gh_pages/generated/Debug/Rift2360/dhrystone.json)|![](https://img.shields.io/endpoint?url=https://raw.githubusercontent.com/whutddk/Rift2Core/gh_pages/generated/Debug/Rift2360/coremark.json)|
+|Rift-2340|N/A|N/A|N/A|
+|Rift-2350|N/A|N/A|N/A|
+|Rift-2360|N/A|N/A|N/A|
 |Rift-2370|![](https://img.shields.io/endpoint?url=https://raw.githubusercontent.com/whutddk/Rift2Core/gh_pages/generated/Debug/Rift2370/isa.json)|![](https://img.shields.io/endpoint?url=https://raw.githubusercontent.com/whutddk/Rift2Core/gh_pages/generated/Debug/Rift2370/dhrystone.json)|![](https://img.shields.io/endpoint?url=https://raw.githubusercontent.com/whutddk/Rift2Core/gh_pages/generated/Debug/Rift2370/coremark.json)|
-|Rift-2380|![](https://img.shields.io/endpoint?url=https://raw.githubusercontent.com/whutddk/Rift2Core/gh_pages/generated/Debug/Rift2380/isa.json)|![](https://img.shields.io/endpoint?url=https://raw.githubusercontent.com/whutddk/Rift2Core/gh_pages/generated/Debug/Rift2380/dhrystone.json)|![](https://img.shields.io/endpoint?url=https://raw.githubusercontent.com/whutddk/Rift2Core/gh_pages/generated/Debug/Rift2380/coremark.json)|
-|Rift-2390|![](https://img.shields.io/endpoint?url=https://raw.githubusercontent.com/whutddk/Rift2Core/gh_pages/generated/Debug/Rift2390/isa.json)|![](https://img.shields.io/endpoint?url=https://raw.githubusercontent.com/whutddk/Rift2Core/gh_pages/generated/Debug/Rift2390/dhrystone.json)|![](https://img.shields.io/endpoint?url=https://raw.githubusercontent.com/whutddk/Rift2Core/gh_pages/generated/Debug/Rift2390/coremark.json)|
+|Rift-2380|N/A|N/A|N/A|
+|Rift-2390|N/A|N/A|N/A|
 
 
 
@@ -87,11 +84,11 @@ Download Pre-compile Version [Here](https://github.com/whutddk/Rift2Core/release
 
 ## API
 
-Rift2Core is not only a highly configurable RISC-V CPU generator, but also provides configurable generation of submodules.
+Rift2Core is not only an extremely configurable RISC-V CPU generator, but also provides configurable generation of submodules.
 
 Search the provided API in the Scala Doc.
 
-[API Here](https://whutddk.github.io/Rift2Core/ScalaDoc/api/index.html)
+[API Here](https://whutddk.github.io/Rift2Core/ScalaDoc/index.html)
 
 ## Wiki
 
diff --git a/doc/Setup.md b/doc/Setup.md
index d7814218..091c2c02 100644
--- a/doc/Setup.md
+++ b/doc/Setup.md
@@ -13,13 +13,13 @@ git submodule update --init --recursive
 ```
 
 
-## Setup SBT
-As a lib of scala, [Chisel3](https://github.com/chipsalliance/chisel3) can compile under *the Scala Build Tool* (SBT).
-1. Java is needed
+## ~~Setup SBT~~
+~~As a lib of scala, [Chisel3](https://github.com/chipsalliance/chisel3) can compile under *the Scala Build Tool* (SBT).~~
+~~1. Java is needed~~
 ``` 
 sudo apt-get install default-jdk
 ```
-2. Install the [SBT](https://www.scala-sbt.org/release/docs/Installing-sbt-on-Linux.html)
+~~2. Install the [SBT](https://www.scala-sbt.org/release/docs/Installing-sbt-on-Linux.html)~~
 ``` 
 sudo apt-get update
 sudo apt-get install apt-transport-https curl gnupg -yqq
@@ -30,7 +30,24 @@ sudo chmod 644 /etc/apt/trusted.gpg.d/scalasbt-release.gpg
 sudo apt-get update
 sudo apt-get install sbt
 ```
-You can also install SBT in Windows
+~~You can also install SBT in Windows~~
+
+
+## Setup millw
+
+1. Download the `millw` in an executable **PATH**, which will take the place of the `sbt`
+
+
+>> curl -L https://raw.githubusercontent.com/lefou/millw/0.4.11/millw > mill && chmod +x mill
+
+
+2. Download the `firtool`, the backend, which will translate firrtl to verilog, make sure to unzip it in an executable **PATH**
+
+```
+wget https://github.com/llvm/circt/releases/download/firtool-1.59.0/circt-full-shared-linux-x64.tar.gz
+tar -zxvf circt-full-shared-linux-x64.tar.gz
+```
+
 
 
 ## Setup Verilator and GTKWave
@@ -51,7 +68,7 @@ make -j4096
 sudo make install
 ```
 
-## Compile chisel3 to verilog
+## ~~Compile chisel3 to verilog~~
 
 
 ```
@@ -59,16 +76,27 @@ cd .
 make compile
 ```
 
-The sbt will download the dependency (来自某些地区的赛博残障人士，请自行寻找稳定连接网络的方案，并从**Maven**下载依赖项) and than emits the verilog to `./generated`.
+~~The sbt will download the dependency (来自某些地区的赛博残障人士，请自行寻找稳定连接网络的方案，并从**Maven**下载依赖项) and than emits the verilog to `./generated`.~~
+
+
+## Compile chisel to verilog
+
+
+```
+cd .
+make mill
+```
+
+The mill will download the dependency (来自某些地区的赛博残障人士，请自行寻找稳定连接网络的方案，并从**Maven**下载依赖项) and than emits the verilog to `./generated`.
+
 
 ## Compile Model of Rif2Chip
 
-The Verilator will compile the Verilog-files emited by chisel3 and a top wrapper `SimTop.v` into a library `VSimTop__ALL`. Then a main function in `sim_main.cpp` will be built up to simulate the behavior of the Rift2Chip SoC. 
+The Verilator will compile the Verilog-files emited by chisel and a top wrapper `SimTop.v` into a library `VSimTop__ALL`. Then a main function in `sim_main.cpp` will be built up to simulate the behavior of the Rift2Chip SoC. 
 
 ```
 export R2=/PATH/TO/Rift2Core
-cd ./tb
-make sim 
+make VSimTop 
 ```
 
 We will get an executable file `./tb/build/VSimTop`.
@@ -78,15 +106,14 @@ We will get an executable file `./tb/build/VSimTop`.
 Make sure your executable riscv files are placed in `./tb/ci`.
 
 ```
-cd ./tb
-make single TESTFILE=./ci/FILENAME
+make single TESTFILE=FILENAME
 ```
 
 the FILENAME will be loaded for diff-test with Dromajo. The FILENAME.verilog will be loaded into the memory of Rift2Chip
 
 To check the waveform?
 ```
-make wave
+make fst
 ```
 
 
@@ -95,6 +122,5 @@ make wave
 Make sure your executable riscv files are placed in `./tb/ci`.
 
 ```
-cd ./tb
-make unit
+make isa
 ```
diff --git a/src/docker/chisel5.do b/src/docker/chisel5.do
new file mode 100644
index 00000000..0bd601b3
--- /dev/null
+++ b/src/docker/chisel5.do
@@ -0,0 +1,15 @@
+FROM whutddk/rift2env:riscvtest
+
+ENV RISCV=/RISCV/ PATH=$PATH:/RISCV/bin:/RISCV/lib:$YOSYS/bin:/firtool-1.59.0/bin
+
+RUN    apt-get update \
+	&& apt-get install -y curl wget zip\
+	&& cd /usr/local/bin \
+    && curl -L https://raw.githubusercontent.com/lefou/millw/0.4.11/millw > mill && chmod +x mill \
+    && cd / \
+    && wget https://github.com/llvm/circt/releases/download/firtool-1.59.0/circt-full-shared-linux-x64.tar.gz \
+    && tar -zxvf circt-full-shared-linux-x64.tar.gz \
+    && rm circt-full-shared-linux-x64.tar.gz \
+    && apt-get purge -y --auto-remove curl wget \
+    && apt-get clean \
+    && rm -rf /var/lib/apt/lists/*
diff --git a/src/main/scala/Config.scala b/src/main/scala/Config.scala
index 177817ae..35000ed4 100644
--- a/src/main/scala/Config.scala
+++ b/src/main/scala/Config.scala
@@ -62,7 +62,6 @@ class Rift2300 extends Config((_, _, _) => {
     ),
 
     dptEntry = 1,
-    fpuNum = 0,
     mulNum = 0,
 
     isMinArea = true,
@@ -126,7 +125,6 @@ class Rift2310 extends Config((_, _, _) => {
     ),
 
     dptEntry = 2,
-    fpuNum = 0,
     mulNum = 1,
 
     isMinArea = true,
@@ -186,7 +184,6 @@ class Rift2320 extends Config((_, _, _) => {
     ),
 
     dptEntry = 4,
-    fpuNum = 0,
     mulNum = 1,
 
     isMinArea = true,
@@ -244,7 +241,6 @@ class Rift2330 extends Config((_, _, _) => {
     ),
 
     dptEntry = 4,
-    fpuNum = 0,
 
     isMinArea = true,
     isLowPower = false,
@@ -300,7 +296,6 @@ class Rift2330D extends Config((_, _, _) => {
     ),
 
     dptEntry = 1,
-    fpuNum = 0,
     mulNum = 0,
 
     isMinArea = true,
@@ -345,7 +340,6 @@ class Rift2340 extends Config((_, _, _) => {
     ),
 
     dptEntry = 6,
-    fpuNum = 1,
 
     isMinArea = true,
     isLowPower = false,
@@ -388,7 +382,6 @@ class Rift2350 extends Config((_, _, _) => {
     ),
 
     dptEntry = 8,
-    fpuNum = 0,
 
     isMinArea = true,
     isLowPower = false,
@@ -431,7 +424,6 @@ class Rift2360 extends Config((_, _, _) => {
     ),
 
     dptEntry = 12,
-    fpuNum = 0,
 
     isMinArea = false,
     isLowPower = true,
@@ -517,7 +509,6 @@ class Rift2380 extends Config((_, _, _) => {
     ),
 
     dptEntry = 24,
-    fpuNum = 1,
     isMinArea = false,
     isLowPower = true,
   )
@@ -559,7 +550,6 @@ class Rift2390 extends Config((_, _, _) => {
     ),
 
     dptEntry = 32,
-    fpuNum = 1,
 
     isMinArea = false,
     isLowPower = true,
diff --git a/src/main/scala/Parameters.scala b/src/main/scala/Parameters.scala
index 2b5fe1b9..5d295e08 100644
--- a/src/main/scala/Parameters.scala
+++ b/src/main/scala/Parameters.scala
@@ -207,7 +207,7 @@ case class RiftSetting(
 
   aluNum: Int = 2,
   mulNum: Int = 1,
-  fpuNum: Int = 1,
+  fpuNum: Int = 0,
 
   vectorParameters: VectorParameters = VectorParameters(),
 
diff --git a/src/test/scala/rift2Core/rift2Chip_tb.scala b/src/test/scala/rift2Core/rift2Chip_tb.scala
index 2f738f2d..1c76135c 100644
--- a/src/test/scala/rift2Core/rift2Chip_tb.scala
+++ b/src/test/scala/rift2Core/rift2Chip_tb.scala
@@ -39,7 +39,7 @@ object testMain extends App {
   // val cfg = new NormalCfg
   // val cfg = new Rift2GoCfg
   // val cfg = new Rift2350
-  val cfg = new Rift2370
+  val cfg = new Rift2330
 
 
   // circt.stage.ChiselStage.emitSystemVerilogFile(
@@ -63,7 +63,22 @@ object testMain extends App {
       circt.stage.FirtoolOption("--disable-annotation-unknown"),
       circt.stage.FirtoolOption( "--dedup"),
     )
+
   )
+
+  // val fir = circt.stage.ChiselStage.emitCHIRRTL(
+  //   gen =  LazyModule(new Rift2Chip()(cfg)).module,
+  //   args = Array(
+  //     // "--target-dir", "generated/Main",
+  //     // "--target", "verilog",
+  //     // "--split-verilog",
+  //     // "--split-verilog",
+  //     ) ++ args,
+  // )
+  // import java.io._
+  // val writer = new PrintWriter(new File("Rift2Chip.fir" ))
+  // writer.write(s"$fir")
+  // writer.close()
 }
 
 // object testNoC extends App {
@@ -129,19 +144,30 @@ object testAll extends App {
   config.map{ cfg =>
     println("Compiling " + cfg._2)
 
-    (new circt.stage.ChiselStage).execute( Array( "--target-dir", "generated/Release/"++cfg._2, "-E", "verilog" ) ++ args, Seq(
-        ChiselGeneratorAnnotation(() => {
-      val soc = LazyModule(new Rift2Chip(isFlatten = true)(cfg._1))
-      soc.module
-    })
-    ))
+    // (new circt.stage.ChiselStage).execute( Array( "--target-dir", "generated/Release/"++cfg._2, "-E", "verilog" ) ++ args, Seq(
+    //     ChiselGeneratorAnnotation(() => {
+    //   val soc = LazyModule(new Rift2Chip(isFlatten = true)(cfg._1))
+    //   soc.module
+    // })
+    // ))
+
+    (new circt.stage.ChiselStage).execute(
+      Array(
+        "--target-dir", "generated/Debug/"++cfg._2,
+        "--target", "verilog",
+        "--split-verilog",
+        ) ++ args,
+      Seq(
+        chisel3.stage.ChiselGeneratorAnnotation( () => {
+          val soc = LazyModule(new Rift2Chip(isFlatten = false)(cfg._1))
+          soc.module
+        }),
+        circt.stage.FirtoolOption("--disable-annotation-unknown"),
+        circt.stage.FirtoolOption( "--dedup"),
+      )
+    )
+
 
-    (new circt.stage.ChiselStage).execute( Array( "--target-dir", "generated/Debug/"++cfg._2, "-e", "verilog" ) ++ args, Seq(
-        ChiselGeneratorAnnotation(() => {
-      val soc = LazyModule(new Rift2Chip(isFlatten = false)(cfg._1))
-      soc.module
-    })
-    ))
   }
 }
 
diff --git a/tb/ci/vec/testList.mk b/tb/ci/vec/testList.mk
new file mode 100644
index 00000000..f6dfb5b6
--- /dev/null
+++ b/tb/ci/vec/testList.mk
@@ -0,0 +1,945 @@
+
+vecisa += vsetivli-0
+vecisa += vsetvl-0
+vecisa += vsetvli-0
+
+vecisa += vle8.v-0
+vecisa += vle16.v-0
+vecisa += vle32.v-0
+vecisa += vle64.v-0
+
+vecisa += vse8.v-0
+vecisa += vse16.v-0
+vecisa += vse32.v-0
+vecisa += vse64.v-0
+
+vecisa += vlm.v-0
+vecisa += vsm.v-0
+
+vecisa += vlse8.v-0
+vecisa += vlse16.v-0
+vecisa += vlse32.v-0
+vecisa += vlse64.v-0
+
+vecisa += vsse8.v-0
+vecisa += vsse8.v-1
+vecisa += vsse16.v-0
+vecisa += vsse16.v-1
+vecisa += vsse32.v-0
+vecisa += vsse32.v-1
+vecisa += vsse64.v-0
+
+vecisa += vlseg2e8.v-0
+vecisa += vlseg2e16.v-0
+vecisa += vlseg2e32.v-0
+vecisa += vlseg2e64.v-0
+vecisa += vlseg3e8.v-0
+vecisa += vlseg3e16.v-0
+vecisa += vlseg3e32.v-0
+vecisa += vlseg3e64.v-0
+vecisa += vlseg4e8.v-0
+vecisa += vlseg4e16.v-0
+vecisa += vlseg4e32.v-0
+vecisa += vlseg4e64.v-0
+vecisa += vlseg5e8.v-0
+vecisa += vlseg5e16.v-0
+vecisa += vlseg5e32.v-0
+vecisa += vlseg5e64.v-0
+vecisa += vlseg6e8.v-0
+vecisa += vlseg6e16.v-0
+vecisa += vlseg6e32.v-0
+vecisa += vlseg6e64.v-0
+vecisa += vlseg7e8.v-0
+vecisa += vlseg7e16.v-0
+vecisa += vlseg7e32.v-0
+vecisa += vlseg7e64.v-0
+vecisa += vlseg8e8.v-0
+vecisa += vlseg8e16.v-0
+vecisa += vlseg8e32.v-0
+vecisa += vlseg8e64.v-0
+
+vecisa += vloxei8.v-0
+vecisa += vloxei16.v-0
+vecisa += vloxei32.v-0
+vecisa += vloxei64.v-0
+
+vecisa += vsoxei8.v-0
+vecisa += vsoxei16.v-0
+vecisa += vsoxei32.v-0
+vecisa += vsoxei64.v-0
+
+vecisa += vluxei8.v-0
+vecisa += vluxei16.v-0
+vecisa += vluxei32.v-0
+vecisa += vluxei64.v-0
+
+vecisa += vsuxei8.v-0
+vecisa += vsuxei16.v-0
+vecisa += vsuxei32.v-0
+vecisa += vsuxei64.v-0
+
+vecisa += vloxseg2ei16.v-0
+vecisa += vloxseg2ei32.v-0
+vecisa += vloxseg2ei64.v-0
+vecisa += vloxseg2ei8.v-0
+vecisa += vloxseg3ei16.v-0
+vecisa += vloxseg3ei32.v-0
+vecisa += vloxseg3ei64.v-0
+vecisa += vloxseg3ei8.v-0
+vecisa += vloxseg4ei16.v-0
+vecisa += vloxseg4ei32.v-0
+vecisa += vloxseg4ei64.v-0
+vecisa += vloxseg4ei8.v-0
+vecisa += vloxseg5ei16.v-0
+vecisa += vloxseg5ei32.v-0
+vecisa += vloxseg5ei64.v-0
+vecisa += vloxseg5ei8.v-0
+vecisa += vloxseg6ei16.v-0
+vecisa += vloxseg6ei32.v-0
+vecisa += vloxseg6ei64.v-0
+vecisa += vloxseg6ei8.v-0
+vecisa += vloxseg7ei16.v-0
+vecisa += vloxseg7ei32.v-0
+vecisa += vloxseg7ei64.v-0
+vecisa += vloxseg7ei8.v-0
+vecisa += vloxseg8ei16.v-0
+vecisa += vloxseg8ei32.v-0
+vecisa += vloxseg8ei64.v-0
+vecisa += vloxseg8ei8.v-0
+
+
+vecisa += vlsseg2e16.v-0
+vecisa += vlsseg2e32.v-0
+vecisa += vlsseg2e64.v-0
+vecisa += vlsseg2e8.v-0
+vecisa += vlsseg3e16.v-0
+vecisa += vlsseg3e32.v-0
+vecisa += vlsseg3e64.v-0
+vecisa += vlsseg3e8.v-0
+vecisa += vlsseg4e16.v-0
+vecisa += vlsseg4e32.v-0
+vecisa += vlsseg4e64.v-0
+vecisa += vlsseg4e8.v-0
+vecisa += vlsseg5e16.v-0
+vecisa += vlsseg5e32.v-0
+vecisa += vlsseg5e64.v-0
+vecisa += vlsseg5e8.v-0
+vecisa += vlsseg6e16.v-0
+vecisa += vlsseg6e32.v-0
+vecisa += vlsseg6e64.v-0
+vecisa += vlsseg6e8.v-0
+vecisa += vlsseg7e16.v-0
+vecisa += vlsseg7e32.v-0
+vecisa += vlsseg7e64.v-0
+vecisa += vlsseg7e8.v-0
+vecisa += vlsseg8e16.v-0
+vecisa += vlsseg8e32.v-0
+vecisa += vlsseg8e64.v-0
+vecisa += vlsseg8e8.v-0
+
+vecisa += vluxseg2ei16.v-0
+vecisa += vluxseg2ei32.v-0
+vecisa += vluxseg2ei64.v-0
+vecisa += vluxseg2ei8.v-0
+vecisa += vluxseg3ei16.v-0
+vecisa += vluxseg3ei32.v-0
+vecisa += vluxseg3ei64.v-0
+vecisa += vluxseg3ei8.v-0
+vecisa += vluxseg4ei16.v-0
+vecisa += vluxseg4ei32.v-0
+vecisa += vluxseg4ei64.v-0
+vecisa += vluxseg4ei8.v-0
+vecisa += vluxseg5ei16.v-0
+vecisa += vluxseg5ei32.v-0
+vecisa += vluxseg5ei64.v-0
+vecisa += vluxseg5ei8.v-0
+vecisa += vluxseg6ei16.v-0
+vecisa += vluxseg6ei32.v-0
+vecisa += vluxseg6ei64.v-0
+vecisa += vluxseg6ei8.v-0
+vecisa += vluxseg7ei16.v-0
+vecisa += vluxseg7ei32.v-0
+vecisa += vluxseg7ei64.v-0
+vecisa += vluxseg7ei8.v-0
+vecisa += vluxseg8ei16.v-0
+vecisa += vluxseg8ei32.v-0
+vecisa += vluxseg8ei64.v-0
+vecisa += vluxseg8ei8.v-0
+
+
+vecisa += vsseg2e16.v-0
+vecisa += vsseg2e32.v-0
+vecisa += vsseg2e64.v-0
+vecisa += vsseg2e8.v-0
+vecisa += vsseg3e16.v-0
+vecisa += vsseg3e32.v-0
+vecisa += vsseg3e64.v-0
+vecisa += vsseg3e8.v-0
+vecisa += vsseg4e16.v-0
+vecisa += vsseg4e32.v-0
+vecisa += vsseg4e64.v-0
+vecisa += vsseg4e8.v-0
+vecisa += vsseg5e16.v-0
+vecisa += vsseg5e32.v-0
+vecisa += vsseg5e64.v-0
+vecisa += vsseg5e8.v-0
+vecisa += vsseg6e16.v-0
+vecisa += vsseg6e32.v-0
+vecisa += vsseg6e64.v-0
+vecisa += vsseg6e8.v-0
+vecisa += vsseg7e16.v-0
+vecisa += vsseg7e32.v-0
+vecisa += vsseg7e64.v-0
+vecisa += vsseg7e8.v-0
+vecisa += vsseg8e16.v-0
+vecisa += vsseg8e32.v-0
+vecisa += vsseg8e64.v-0
+vecisa += vsseg8e8.v-0
+
+vecisa += vsoxseg2ei16.v-0
+vecisa += vsoxseg2ei32.v-0
+vecisa += vsoxseg2ei64.v-0
+vecisa += vsoxseg2ei8.v-0
+vecisa += vsoxseg3ei16.v-0
+vecisa += vsoxseg3ei32.v-0
+vecisa += vsoxseg3ei64.v-0
+vecisa += vsoxseg3ei8.v-0
+vecisa += vsoxseg4ei16.v-0
+vecisa += vsoxseg4ei32.v-0
+vecisa += vsoxseg4ei64.v-0
+vecisa += vsoxseg4ei8.v-0
+vecisa += vsoxseg5ei16.v-0
+vecisa += vsoxseg5ei32.v-0
+vecisa += vsoxseg5ei64.v-0
+vecisa += vsoxseg5ei8.v-0
+vecisa += vsoxseg6ei16.v-0
+vecisa += vsoxseg6ei32.v-0
+vecisa += vsoxseg6ei64.v-0
+vecisa += vsoxseg6ei8.v-0
+vecisa += vsoxseg7ei16.v-0
+vecisa += vsoxseg7ei32.v-0
+vecisa += vsoxseg7ei64.v-0
+vecisa += vsoxseg7ei8.v-0
+vecisa += vsoxseg8ei16.v-0
+vecisa += vsoxseg8ei32.v-0
+vecisa += vsoxseg8ei64.v-0
+vecisa += vsoxseg8ei8.v-0
+
+
+vecisa += vsuxseg2ei16.v-0
+vecisa += vsuxseg2ei32.v-0
+vecisa += vsuxseg2ei64.v-0
+vecisa += vsuxseg2ei8.v-0
+vecisa += vsuxseg3ei16.v-0
+vecisa += vsuxseg3ei32.v-0
+vecisa += vsuxseg3ei64.v-0
+vecisa += vsuxseg3ei8.v-0
+vecisa += vsuxseg4ei16.v-0
+vecisa += vsuxseg4ei32.v-0
+vecisa += vsuxseg4ei64.v-0
+vecisa += vsuxseg4ei8.v-0
+vecisa += vsuxseg5ei16.v-0
+vecisa += vsuxseg5ei32.v-0
+vecisa += vsuxseg5ei64.v-0
+vecisa += vsuxseg5ei8.v-0
+vecisa += vsuxseg6ei16.v-0
+vecisa += vsuxseg6ei32.v-0
+vecisa += vsuxseg6ei64.v-0
+vecisa += vsuxseg6ei8.v-0
+vecisa += vsuxseg7ei16.v-0
+vecisa += vsuxseg7ei32.v-0
+vecisa += vsuxseg7ei64.v-0
+vecisa += vsuxseg7ei8.v-0
+vecisa += vsuxseg8ei16.v-0
+vecisa += vsuxseg8ei32.v-0
+vecisa += vsuxseg8ei64.v-0
+vecisa += vsuxseg8ei8.v-0
+
+#                       vecisa += vssseg2e16.v-0
+# 						vecisa += vssseg2e16.v-1
+# 						vecisa += vssseg2e32.v-0
+# 						vecisa += vssseg2e64.v-0
+# 						vecisa += vssseg2e8.v-0
+# 						vecisa += vssseg2e8.v-1
+# 						vecisa += vssseg3e16.v-0
+# 						vecisa += vssseg3e32.v-0
+# 						vecisa += vssseg3e64.v-0
+# 						vecisa += vssseg3e8.v-0
+# 						vecisa += vssseg3e8.v-1
+# 						vecisa += vssseg4e16.v-0
+# 						vecisa += vssseg4e32.v-0
+# 						vecisa += vssseg4e64.v-0
+# 						vecisa += vssseg4e8.v-0
+# 						vecisa += vssseg4e8.v-1
+# 						vecisa += vssseg5e16.v-0
+# 						vecisa += vssseg5e32.v-0
+# 						vecisa += vssseg5e64.v-0
+# 						vecisa += vssseg5e8.v-0
+# 						vecisa += vssseg6e16.v-0
+# 						vecisa += vssseg6e32.v-0
+# 						vecisa += vssseg6e64.v-0
+# 						vecisa += vssseg6e8.v-0
+# 						vecisa += vssseg7e16.v-0
+# 						vecisa += vssseg7e32.v-0
+# 						vecisa += vssseg7e64.v-0
+# 						vecisa += vssseg7e8.v-0
+# 						vecisa += vssseg8e16.v-0
+# 						vecisa += vssseg8e32.v-0
+# 						vecisa += vssseg8e64.v-0
+# 						vecisa += vssseg8e8.v-0
+
+
+
+vecisa += vl1re8.v-0
+vecisa += vl1re16.v-0
+vecisa += vl1re32.v-0
+vecisa += vl1re64.v-0
+
+vecisa += vl2re16.v-0
+vecisa += vl2re32.v-0
+vecisa += vl2re64.v-0
+vecisa += vl2re8.v-0
+vecisa += vl4re16.v-0
+vecisa += vl4re32.v-0
+vecisa += vl4re64.v-0
+vecisa += vl4re8.v-0
+vecisa += vl8re16.v-0
+vecisa += vl8re32.v-0
+vecisa += vl8re64.v-0
+vecisa += vl8re8.v-0
+
+
+vecisa += vle8ff.v-0
+vecisa += vle16ff.v-0
+vecisa += vle32ff.v-0
+vecisa += vle64ff.v-0
+
+
+
+
+
+
+
+
+
+
+vecisa += vaadd.vv-0
+vecisa += vaadd.vv-1
+vecisa += vaadd.vx-0
+vecisa += vaadd.vx-1
+vecisa += vaadd.vx-2
+vecisa += vaadd.vx-3
+vecisa += vaaddu.vv-0
+vecisa += vaaddu.vv-1
+vecisa += vaaddu.vx-0
+vecisa += vaaddu.vx-1
+vecisa += vaaddu.vx-2
+vecisa += vaaddu.vx-3
+vecisa += vadc.vim-0
+vecisa += vadc.vim-1
+vecisa += vadc.vvm-0
+vecisa += vadc.vxm-0
+vecisa += vadc.vxm-1
+vecisa += vadd.vi-0
+vecisa += vadd.vi-1
+vecisa += vadd.vi-2
+vecisa += vadd.vv-0
+vecisa += vadd.vv-1
+vecisa += vadd.vx-0
+vecisa += vadd.vx-1
+vecisa += vadd.vx-2
+vecisa += vadd.vx-3
+vecisa += vand.vi-0
+vecisa += vand.vi-1
+vecisa += vand.vi-2
+vecisa += vand.vv-0
+vecisa += vand.vv-1
+vecisa += vand.vx-0
+vecisa += vand.vx-1
+vecisa += vand.vx-2
+vecisa += vand.vx-3
+vecisa += vasub.vv-0
+vecisa += vasub.vv-1
+vecisa += vasub.vx-0
+vecisa += vasub.vx-1
+vecisa += vasub.vx-2
+vecisa += vasub.vx-3
+vecisa += vasubu.vv-0
+vecisa += vasubu.vv-1
+vecisa += vasubu.vx-0
+vecisa += vasubu.vx-1
+vecisa += vasubu.vx-2
+vecisa += vasubu.vx-3
+vecisa += vcompress.vm-0
+vecisa += vcpop.m-0
+vecisa += vdiv.vv-0
+vecisa += vdiv.vv-1
+vecisa += vdiv.vx-0
+vecisa += vdiv.vx-1
+vecisa += vdiv.vx-2
+vecisa += vdiv.vx-3
+vecisa += vdiv.vx-4
+vecisa += vdivu.vv-0
+vecisa += vdivu.vv-1
+vecisa += vdivu.vx-0
+vecisa += vdivu.vx-1
+vecisa += vdivu.vx-2
+vecisa += vdivu.vx-3
+vecisa += vdivu.vx-4
+
+vecisa += vfadd.vf-0
+vecisa += vfadd.vv-0
+vecisa += vfclass.v-0
+vecisa += vfcvt.f.x.v-0
+vecisa += vfcvt.f.xu.v-0
+vecisa += vfcvt.rtz.x.f.v-0
+vecisa += vfcvt.rtz.xu.f.v-0
+vecisa += vfcvt.x.f.v-0
+vecisa += vfcvt.xu.f.v-0
+vecisa += vfdiv.vf-0
+vecisa += vfdiv.vv-0
+vecisa += vfirst.m-0
+vecisa += vfmacc.vf-0
+vecisa += vfmacc.vv-0
+vecisa += vfmadd.vf-0
+vecisa += vfmadd.vv-0
+vecisa += vfmax.vf-0
+vecisa += vfmax.vv-0
+vecisa += vfmerge.vfm-0
+vecisa += vfmin.vf-0
+vecisa += vfmin.vv-0
+vecisa += vfmsac.vf-0
+vecisa += vfmsac.vv-0
+vecisa += vfmsub.vf-0
+vecisa += vfmsub.vv-0
+vecisa += vfmul.vf-0
+vecisa += vfmul.vv-0
+vecisa += vfmv.f.s-0
+vecisa += vfmv.s.f-0
+vecisa += vfmv.v.f-0
+vecisa += vfncvt.f.f.w-0
+vecisa += vfncvt.f.x.w-0
+vecisa += vfncvt.f.xu.w-0
+vecisa += vfncvt.rod.f.f.w-0
+vecisa += vfncvt.rtz.x.f.w-0
+vecisa += vfncvt.rtz.xu.f.w-0
+vecisa += vfncvt.x.f.w-0
+vecisa += vfncvt.xu.f.w-0
+vecisa += vfnmacc.vf-0
+vecisa += vfnmacc.vv-0
+vecisa += vfnmadd.vf-0
+vecisa += vfnmadd.vv-0
+vecisa += vfnmsac.vf-0
+vecisa += vfnmsac.vv-0
+vecisa += vfnmsub.vf-0
+vecisa += vfnmsub.vv-0
+vecisa += vfrdiv.vf-0
+vecisa += vfrec7.v-0
+vecisa += vfredmax.vs-0
+vecisa += vfredmin.vs-0
+vecisa += vfredosum.vs-0
+vecisa += vfredusum.vs-0
+vecisa += vfrsqrt7.v-0
+vecisa += vfrsub.vf-0
+vecisa += vfsgnj.vf-0
+vecisa += vfsgnj.vv-0
+vecisa += vfsgnjn.vf-0
+vecisa += vfsgnjn.vv-0
+vecisa += vfsgnjx.vf-0
+vecisa += vfsgnjx.vv-0
+vecisa += vfslide1down.vf-0
+vecisa += vfslide1up.vf-0
+vecisa += vfsqrt.v-0
+vecisa += vfsub.vf-0
+vecisa += vfsub.vv-0
+vecisa += vfwadd.vf-0
+vecisa += vfwadd.vv-0
+vecisa += vfwadd.wf-0
+vecisa += vfwadd.wv-0
+vecisa += vfwcvt.f.f.v-0
+vecisa += vfwcvt.f.x.v-0
+vecisa += vfwcvt.f.xu.v-0
+vecisa += vfwcvt.rtz.x.f.v-0
+vecisa += vfwcvt.rtz.xu.f.v-0
+vecisa += vfwcvt.x.f.v-0
+vecisa += vfwcvt.xu.f.v-0
+vecisa += vfwmacc.vf-0
+vecisa += vfwmacc.vv-0
+vecisa += vfwmsac.vf-0
+vecisa += vfwmsac.vv-0
+vecisa += vfwmul.vf-0
+vecisa += vfwmul.vv-0
+vecisa += vfwnmacc.vf-0
+vecisa += vfwnmacc.vv-0
+vecisa += vfwnmsac.vf-0
+vecisa += vfwnmsac.vv-0
+vecisa += vfwredosum.vs-0
+vecisa += vfwredusum.vs-0
+vecisa += vfwsub.vf-0
+vecisa += vfwsub.vv-0
+vecisa += vfwsub.wf-0
+vecisa += vfwsub.wv-0
+vecisa += vid.v-0
+vecisa += viota.m-0
+vecisa += vmacc.vv-0
+vecisa += vmacc.vv-1
+vecisa += vmacc.vx-0
+vecisa += vmacc.vx-1
+vecisa += vmacc.vx-2
+vecisa += vmacc.vx-3
+vecisa += vmadc.vi-0
+vecisa += vmadc.vi-1
+vecisa += vmadc.vim-0
+vecisa += vmadc.vim-1
+vecisa += vmadc.vv-0
+vecisa += vmadc.vvm-0
+vecisa += vmadc.vx-0
+vecisa += vmadc.vx-1
+vecisa += vmadc.vxm-0
+vecisa += vmadc.vxm-1
+vecisa += vmadd.vv-0
+vecisa += vmadd.vv-1
+vecisa += vmadd.vx-0
+vecisa += vmadd.vx-1
+vecisa += vmadd.vx-2
+vecisa += vmadd.vx-3
+vecisa += vmand.mm-0
+vecisa += vmandn.mm-0
+vecisa += vmax.vv-0
+vecisa += vmax.vv-1
+vecisa += vmax.vx-0
+vecisa += vmax.vx-1
+vecisa += vmax.vx-2
+vecisa += vmax.vx-3
+vecisa += vmaxu.vv-0
+vecisa += vmaxu.vv-1
+vecisa += vmaxu.vx-0
+vecisa += vmaxu.vx-1
+vecisa += vmaxu.vx-2
+vecisa += vmaxu.vx-3
+vecisa += vmerge.vim-0
+vecisa += vmerge.vim-1
+vecisa += vmerge.vvm-0
+vecisa += vmerge.vxm-0
+vecisa += vmfeq.vf-0
+vecisa += vmfeq.vv-0
+vecisa += vmfge.vf-0
+vecisa += vmfgt.vf-0
+vecisa += vmfle.vf-0
+vecisa += vmfle.vv-0
+vecisa += vmflt.vf-0
+vecisa += vmflt.vv-0
+vecisa += vmfne.vf-0
+vecisa += vmfne.vv-0
+vecisa += vmin.vv-0
+vecisa += vmin.vv-1
+vecisa += vmin.vx-0
+vecisa += vmin.vx-1
+vecisa += vmin.vx-2
+vecisa += vmin.vx-3
+vecisa += vminu.vv-0
+vecisa += vminu.vv-1
+vecisa += vminu.vx-0
+vecisa += vminu.vx-1
+vecisa += vminu.vx-2
+vecisa += vminu.vx-3
+vecisa += vmnand.mm-0
+vecisa += vmnor.mm-0
+vecisa += vmor.mm-0
+vecisa += vmorn.mm-0
+vecisa += vmsbc.vv-0
+vecisa += vmsbc.vvm-0
+vecisa += vmsbc.vx-0
+vecisa += vmsbc.vx-1
+vecisa += vmsbc.vxm-0
+vecisa += vmsbc.vxm-1
+vecisa += vmsbf.m-0
+vecisa += vmseq.vi-0
+vecisa += vmseq.vi-1
+vecisa += vmseq.vi-2
+vecisa += vmseq.vv-0
+vecisa += vmseq.vv-1
+vecisa += vmseq.vx-0
+vecisa += vmseq.vx-1
+vecisa += vmseq.vx-2
+vecisa += vmseq.vx-3
+vecisa += vmsgt.vi-0
+vecisa += vmsgt.vi-1
+vecisa += vmsgt.vi-2
+vecisa += vmsgt.vv-0
+vecisa += vmsgt.vv-1
+vecisa += vmsgt.vx-0
+vecisa += vmsgt.vx-1
+vecisa += vmsgt.vx-2
+vecisa += vmsgt.vx-3
+vecisa += vmsgtu.vi-0
+vecisa += vmsgtu.vi-1
+vecisa += vmsgtu.vi-2
+vecisa += vmsgtu.vv-0
+vecisa += vmsgtu.vv-1
+vecisa += vmsgtu.vx-0
+vecisa += vmsgtu.vx-1
+vecisa += vmsgtu.vx-2
+vecisa += vmsgtu.vx-3
+vecisa += vmsif.m-0
+vecisa += vmsle.vi-0
+vecisa += vmsle.vi-1
+vecisa += vmsle.vi-2
+vecisa += vmsle.vv-0
+vecisa += vmsle.vv-1
+vecisa += vmsle.vx-0
+vecisa += vmsle.vx-1
+vecisa += vmsle.vx-2
+vecisa += vmsle.vx-3
+vecisa += vmsleu.vi-0
+vecisa += vmsleu.vi-1
+vecisa += vmsleu.vi-2
+vecisa += vmsleu.vv-0
+vecisa += vmsleu.vv-1
+vecisa += vmsleu.vx-0
+vecisa += vmsleu.vx-1
+vecisa += vmsleu.vx-2
+vecisa += vmsleu.vx-3
+vecisa += vmslt.vv-0
+vecisa += vmslt.vv-1
+vecisa += vmslt.vx-0
+vecisa += vmslt.vx-1
+vecisa += vmslt.vx-2
+vecisa += vmslt.vx-3
+vecisa += vmsltu.vv-0
+vecisa += vmsltu.vv-1
+vecisa += vmsltu.vx-0
+vecisa += vmsltu.vx-1
+vecisa += vmsltu.vx-2
+vecisa += vmsltu.vx-3
+vecisa += vmsne.vi-0
+vecisa += vmsne.vi-1
+vecisa += vmsne.vi-2
+vecisa += vmsne.vv-0
+vecisa += vmsne.vv-1
+vecisa += vmsne.vx-0
+vecisa += vmsne.vx-1
+vecisa += vmsne.vx-2
+vecisa += vmsne.vx-3
+vecisa += vmsof.m-0
+vecisa += vmul.vv-0
+vecisa += vmul.vv-1
+vecisa += vmul.vx-0
+vecisa += vmul.vx-1
+vecisa += vmul.vx-2
+vecisa += vmul.vx-3
+vecisa += vmul.vx-4
+vecisa += vmulh.vv-0
+vecisa += vmulh.vv-1
+vecisa += vmulh.vx-0
+vecisa += vmulh.vx-1
+vecisa += vmulh.vx-2
+vecisa += vmulh.vx-3
+vecisa += vmulh.vx-4
+vecisa += vmulhsu.vv-0
+vecisa += vmulhsu.vv-1
+vecisa += vmulhsu.vx-0
+vecisa += vmulhsu.vx-1
+vecisa += vmulhsu.vx-2
+vecisa += vmulhsu.vx-3
+vecisa += vmulhsu.vx-4
+vecisa += vmulhu.vv-0
+vecisa += vmulhu.vv-1
+vecisa += vmulhu.vx-0
+vecisa += vmulhu.vx-1
+vecisa += vmulhu.vx-2
+vecisa += vmulhu.vx-3
+vecisa += vmulhu.vx-4
+vecisa += vmv.s.x-0
+vecisa += vmv.v.i-0
+vecisa += vmv.v.v-0
+vecisa += vmv.v.x-0
+vecisa += vmv.x.s-0
+vecisa += vmv1r.v-0
+vecisa += vmv2r.v-0
+vecisa += vmv4r.v-0
+vecisa += vmv8r.v-0
+vecisa += vmxnor.mm-0
+vecisa += vmxor.mm-0
+vecisa += vnclip.wi-0
+vecisa += vnclip.wi-1
+vecisa += vnclip.wv-0
+vecisa += vnclip.wx-0
+vecisa += vnclip.wx-1
+vecisa += vnclip.wx-2
+vecisa += vnclipu.wi-0
+vecisa += vnclipu.wi-1
+vecisa += vnclipu.wv-0
+vecisa += vnclipu.wx-0
+vecisa += vnclipu.wx-1
+vecisa += vnclipu.wx-2
+vecisa += vnmsac.vv-0
+vecisa += vnmsac.vv-1
+vecisa += vnmsac.vx-0
+vecisa += vnmsac.vx-1
+vecisa += vnmsac.vx-2
+vecisa += vnmsac.vx-3
+vecisa += vnmsub.vv-0
+vecisa += vnmsub.vv-1
+vecisa += vnmsub.vx-0
+vecisa += vnmsub.vx-1
+vecisa += vnmsub.vx-2
+vecisa += vnmsub.vx-3
+vecisa += vnsra.wi-0
+vecisa += vnsra.wi-1
+vecisa += vnsra.wv-0
+vecisa += vnsra.wx-0
+vecisa += vnsra.wx-1
+vecisa += vnsra.wx-2
+vecisa += vnsrl.wi-0
+vecisa += vnsrl.wi-1
+vecisa += vnsrl.wv-0
+vecisa += vnsrl.wx-0
+vecisa += vnsrl.wx-1
+vecisa += vnsrl.wx-2
+vecisa += vor.vi-0
+vecisa += vor.vi-1
+vecisa += vor.vi-2
+vecisa += vor.vv-0
+vecisa += vor.vv-1
+vecisa += vor.vx-0
+vecisa += vor.vx-1
+vecisa += vor.vx-2
+vecisa += vor.vx-3
+vecisa += vredand.vs-0
+vecisa += vredand.vs-1
+vecisa += vredmax.vs-0
+vecisa += vredmax.vs-1
+vecisa += vredmaxu.vs-0
+vecisa += vredmaxu.vs-1
+vecisa += vredmin.vs-0
+vecisa += vredmin.vs-1
+vecisa += vredminu.vs-0
+vecisa += vredminu.vs-1
+vecisa += vredor.vs-0
+vecisa += vredor.vs-1
+vecisa += vredsum.vs-0
+vecisa += vredsum.vs-1
+vecisa += vredxor.vs-0
+vecisa += vredxor.vs-1
+vecisa += vrem.vv-0
+vecisa += vrem.vv-1
+vecisa += vrem.vx-0
+vecisa += vrem.vx-1
+vecisa += vrem.vx-2
+vecisa += vrem.vx-3
+vecisa += vrem.vx-4
+vecisa += vremu.vv-0
+vecisa += vremu.vv-1
+vecisa += vremu.vx-0
+vecisa += vremu.vx-1
+vecisa += vremu.vx-2
+vecisa += vremu.vx-3
+vecisa += vremu.vx-4
+vecisa += vrgather.vi-0
+vecisa += vrgather.vi-1
+vecisa += vrgather.vv-0
+vecisa += vrgather.vv-1
+vecisa += vrgather.vx-0
+vecisa += vrgather.vx-1
+vecisa += vrgather.vx-2
+vecisa += vrgather.vx-3
+vecisa += vrgatherei16.vv-0
+vecisa += vrsub.vi-0
+vecisa += vrsub.vi-1
+vecisa += vrsub.vi-2
+vecisa += vrsub.vx-0
+vecisa += vrsub.vx-1
+vecisa += vrsub.vx-2
+vecisa += vrsub.vx-3
+vecisa += vs1r.v-0
+vecisa += vs2r.v-0
+vecisa += vs4r.v-0
+vecisa += vs8r.v-0
+vecisa += vsadd.vi-0
+vecisa += vsadd.vi-1
+vecisa += vsadd.vi-2
+vecisa += vsadd.vv-0
+vecisa += vsadd.vv-1
+vecisa += vsadd.vx-0
+vecisa += vsadd.vx-1
+vecisa += vsadd.vx-2
+vecisa += vsadd.vx-3
+vecisa += vsaddu.vi-0
+vecisa += vsaddu.vi-1
+vecisa += vsaddu.vi-2
+vecisa += vsaddu.vv-0
+vecisa += vsaddu.vv-1
+vecisa += vsaddu.vx-0
+vecisa += vsaddu.vx-1
+vecisa += vsaddu.vx-2
+vecisa += vsaddu.vx-3
+vecisa += vsbc.vvm-0
+vecisa += vsbc.vxm-0
+vecisa += vsbc.vxm-1
+vecisa += vsbc.vxm-2
+vecisa += vsext.vf2-0
+vecisa += vsext.vf4-0
+vecisa += vsext.vf8-0
+vecisa += vslide1down.vx-0
+vecisa += vslide1down.vx-1
+vecisa += vslide1down.vx-2
+vecisa += vslide1down.vx-3
+vecisa += vslide1up.vx-0
+vecisa += vslide1up.vx-1
+vecisa += vslide1up.vx-2
+vecisa += vslide1up.vx-3
+vecisa += vslidedown.vi-0
+vecisa += vslidedown.vi-1
+vecisa += vslidedown.vx-0
+vecisa += vslidedown.vx-1
+vecisa += vslidedown.vx-2
+vecisa += vslidedown.vx-3
+vecisa += vslideup.vi-0
+vecisa += vslideup.vi-1
+vecisa += vslideup.vx-0
+vecisa += vslideup.vx-1
+vecisa += vslideup.vx-2
+vecisa += vslideup.vx-3
+vecisa += vsll.vi-0
+vecisa += vsll.vi-1
+vecisa += vsll.vv-0
+vecisa += vsll.vv-1
+vecisa += vsll.vx-0
+vecisa += vsll.vx-1
+vecisa += vsll.vx-2
+vecisa += vsll.vx-3
+vecisa += vsmul.vv-0
+vecisa += vsmul.vv-1
+vecisa += vsmul.vx-0
+vecisa += vsmul.vx-1
+vecisa += vsmul.vx-2
+vecisa += vsmul.vx-3
+vecisa += vsra.vi-0
+vecisa += vsra.vi-1
+vecisa += vsra.vv-0
+vecisa += vsra.vv-1
+vecisa += vsra.vx-0
+vecisa += vsra.vx-1
+vecisa += vsra.vx-2
+vecisa += vsra.vx-3
+vecisa += vsrl.vi-0
+vecisa += vsrl.vi-1
+vecisa += vsrl.vv-0
+vecisa += vsrl.vv-1
+vecisa += vsrl.vx-0
+vecisa += vsrl.vx-1
+vecisa += vsrl.vx-2
+vecisa += vsrl.vx-3
+vecisa += vssra.vi-0
+vecisa += vssra.vi-1
+vecisa += vssra.vv-0
+vecisa += vssra.vv-1
+vecisa += vssra.vx-0
+vecisa += vssra.vx-1
+vecisa += vssra.vx-2
+vecisa += vssra.vx-3
+vecisa += vssra.vx-4
+vecisa += vssrl.vi-0
+vecisa += vssrl.vi-1
+vecisa += vssrl.vv-0
+vecisa += vssrl.vv-1
+vecisa += vssrl.vx-0
+vecisa += vssrl.vx-1
+vecisa += vssrl.vx-2
+vecisa += vssrl.vx-3
+vecisa += vssrl.vx-4
+vecisa += vssub.vv-0
+vecisa += vssub.vv-1
+vecisa += vssub.vx-0
+vecisa += vssub.vx-1
+vecisa += vssub.vx-2
+vecisa += vssub.vx-3
+vecisa += vssub.vx-4
+vecisa += vssubu.vv-0
+vecisa += vssubu.vv-1
+vecisa += vssubu.vx-0
+vecisa += vssubu.vx-1
+vecisa += vssubu.vx-2
+vecisa += vssubu.vx-3
+vecisa += vssubu.vx-4
+vecisa += vsub.vv-0
+vecisa += vsub.vv-1
+vecisa += vsub.vx-0
+vecisa += vsub.vx-1
+vecisa += vsub.vx-2
+vecisa += vsub.vx-3
+vecisa += vsub.vx-4
+vecisa += vwadd.vv-0
+vecisa += vwadd.vx-0
+vecisa += vwadd.vx-1
+vecisa += vwadd.vx-2
+vecisa += vwadd.wv-0
+vecisa += vwadd.wx-0
+vecisa += vwadd.wx-1
+vecisa += vwadd.wx-2
+vecisa += vwaddu.vv-0
+vecisa += vwaddu.vx-0
+vecisa += vwaddu.vx-1
+vecisa += vwaddu.vx-2
+vecisa += vwaddu.wv-0
+vecisa += vwaddu.wx-0
+vecisa += vwaddu.wx-1
+vecisa += vwaddu.wx-2
+vecisa += vwmacc.vv-0
+vecisa += vwmacc.vx-0
+vecisa += vwmacc.vx-1
+vecisa += vwmacc.vx-2
+vecisa += vwmaccsu.vv-0
+vecisa += vwmaccsu.vx-0
+vecisa += vwmaccsu.vx-1
+vecisa += vwmaccsu.vx-2
+vecisa += vwmaccu.vv-0
+vecisa += vwmaccu.vx-0
+vecisa += vwmaccu.vx-1
+vecisa += vwmaccu.vx-2
+vecisa += vwmaccus.vx-0
+vecisa += vwmaccus.vx-1
+vecisa += vwmaccus.vx-2
+vecisa += vwmul.vv-0
+vecisa += vwmul.vx-0
+vecisa += vwmul.vx-1
+vecisa += vwmul.vx-2
+vecisa += vwmulsu.vv-0
+vecisa += vwmulsu.vx-0
+vecisa += vwmulsu.vx-1
+vecisa += vwmulsu.vx-2
+vecisa += vwmulu.vv-0
+vecisa += vwmulu.vx-0
+vecisa += vwmulu.vx-1
+vecisa += vwmulu.vx-2
+vecisa += vwredsum.vs-0
+vecisa += vwredsumu.vs-0
+vecisa += vwsub.vv-0
+vecisa += vwsub.vx-0
+vecisa += vwsub.vx-1
+vecisa += vwsub.vx-2
+vecisa += vwsub.wv-0
+vecisa += vwsub.wx-0
+vecisa += vwsub.wx-1
+vecisa += vwsub.wx-2
+vecisa += vwsubu.vv-0
+vecisa += vwsubu.vx-0
+vecisa += vwsubu.vx-1
+vecisa += vwsubu.vx-2
+vecisa += vwsubu.wv-0
+vecisa += vwsubu.wx-0
+vecisa += vwsubu.wx-1
+vecisa += vwsubu.wx-2
+vecisa += vxor.vi-0
+vecisa += vxor.vi-1
+vecisa += vxor.vi-2
+vecisa += vxor.vv-0
+vecisa += vxor.vv-1
+vecisa += vxor.vx-0
+vecisa += vxor.vx-1
+vecisa += vxor.vx-2
+vecisa += vxor.vx-3
+vecisa += vzext.vf2-0
+vecisa += vzext.vf4-0
+vecisa += vzext.vf8-0