diff --git a/src/main/scala/Config.scala b/src/main/scala/Config.scala
index c73c3416..177817ae 100644
--- a/src/main/scala/Config.scala
+++ b/src/main/scala/Config.scala
@@ -440,42 +440,42 @@ class Rift2360 extends Config((_, _, _) => {
 
 class Rift2370 extends Config((_, _, _) => {
   case RiftParamsKey => RiftSetting(
-    hasVector = true,
-
-    opChn = 2,
-    wbChn = 2,
-
-    pmpNum = 1,
-    hpmNum = 0,
-
-    icacheParameters = IcacheParameters(
-      bk = 1,
-      cb = 2,
-      cl = 8
-    ),
-
-    dcacheParameters = DcacheParameters(
-      bk = 2,
-      cb = 2,
-      cl = 8,
-      stEntry = 16,
-      sbEntry = 2,
-    ),
-
-    ifetchParameters = IFParameters(
-      uBTB_entry = 4,
-      btb_cl = 8,
-      bim_cl = 8,
-      ras_dp = 4,
-    ),
-
-    dptEntry = 4,
-
-    aluNum = 1,
-
-    xRegNum = 36,
-    fRegNum = 36,
-    tlbEntry = 4,
+    // hasVector = true,
+
+    // opChn = 2,
+    // wbChn = 2,
+
+    // pmpNum = 1,
+    // hpmNum = 0,
+
+    // icacheParameters = IcacheParameters(
+    //   bk = 1,
+    //   cb = 2,
+    //   cl = 8
+    // ),
+
+    // dcacheParameters = DcacheParameters(
+    //   bk = 2,
+    //   cb = 2,
+    //   cl = 8,
+    //   stEntry = 16,
+    //   sbEntry = 2,
+    // ),
+
+    // ifetchParameters = IFParameters(
+    //   uBTB_entry = 4,
+    //   btb_cl = 8,
+    //   bim_cl = 8,
+    //   ras_dp = 4,
+    // ),
+
+    // dptEntry = 4,
+
+    // aluNum = 1,
+
+    // xRegNum = 36,
+    // fRegNum = 36,
+    // tlbEntry = 4,
   )
 
 
diff --git a/src/main/scala/rift2Core/backend/LSU/DcacheStage.scala b/src/main/scala/rift2Core/backend/LSU/DcacheStage.scala
index 00a41523..0bcb7c30 100644
--- a/src/main/scala/rift2Core/backend/LSU/DcacheStage.scala
+++ b/src/main/scala/rift2Core/backend/LSU/DcacheStage.scala
@@ -380,7 +380,7 @@ trait DcacheStageRTN{ this: DcacheStageBase =>
         res := reAlign_data( from = dw, to = 64, overlap_data, paddr )
         res
       }
-      val res_pre = get_loadRes( fun, pipeStage1Bits.vAttach.get.vsew, paddr, res_pre_pre ) //align 8
+      val res_pre = get_loadRes( fun, (if(hasVector){pipeStage1Bits.vAttach.get.vsew} else {0.U}), paddr, res_pre_pre ) //align 8
 
       val res = MuxCase(res_pre, Seq(
         pipeStage1Bits.fun.is_sc    -> Mux( is_sc_fail, 1.U, 0.U ),
diff --git a/src/main/scala/rift2Core/backend/LSU/IO_Lsu.scala b/src/main/scala/rift2Core/backend/LSU/IO_Lsu.scala
index 4ba097bc..12349fdf 100644
--- a/src/main/scala/rift2Core/backend/LSU/IO_Lsu.scala
+++ b/src/main/scala/rift2Core/backend/LSU/IO_Lsu.scala
@@ -115,7 +115,7 @@ class IO_Lsu(edge: TLEdgeOut)(implicit p: Parameters) extends RiftModule{
     //   val (new_data, new_strb) = overlap_wr( rdata, 0.U, overlap_wdata, overlap_wstrb)
     //   new_data
     // }
-    val res_pre = get_loadRes( fun, pending.vAttach.get.vsew, paddr, rdata )
+    val res_pre = get_loadRes( fun, (if(hasVector){pending.vAttach.get.vsew} else{0.U}), paddr, rdata )
     res_pre
   }