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artyz7_dsp_2020-2.xpr
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artyz7_dsp_2020-2.xpr
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<?xml version="1.0" encoding="UTF-8"?>
<!-- Product Version: Vivado v2020.2 (64-bit) -->
<!-- -->
<!-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. -->
<Project Version="7" Minor="54" Path="/home/parallels/artyz7_dsp_2020-2/artyz7_dsp_2020-2.xpr">
<DefaultLaunch Dir="$PRUNDIR"/>
<Configuration>
<Option Name="Id" Val="df638c7c6b3749ce8cf0efd52d42d648"/>
<Option Name="Part" Val="xc7z020clg400-1"/>
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
<Option Name="CompiledLibDirXSim" Val=""/>
<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
<Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
<Option Name="CompiledLibDirIES" Val="$PCACHEDIR/compile_simlib/ies"/>
<Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
<Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
<Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
<Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
<Option Name="SimulatorInstallDirModelSim" Val=""/>
<Option Name="SimulatorInstallDirQuesta" Val=""/>
<Option Name="SimulatorInstallDirIES" Val=""/>
<Option Name="SimulatorInstallDirXcelium" Val=""/>
<Option Name="SimulatorInstallDirVCS" Val=""/>
<Option Name="SimulatorInstallDirRiviera" Val=""/>
<Option Name="SimulatorInstallDirActiveHdl" Val=""/>
<Option Name="SimulatorGccInstallDirModelSim" Val=""/>
<Option Name="SimulatorGccInstallDirQuesta" Val=""/>
<Option Name="SimulatorGccInstallDirIES" Val=""/>
<Option Name="SimulatorGccInstallDirXcelium" Val=""/>
<Option Name="SimulatorGccInstallDirVCS" Val=""/>
<Option Name="SimulatorGccInstallDirRiviera" Val=""/>
<Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
<Option Name="BoardPart" Val="digilentinc.com:arty-z7-20:part0:1.0"/>
<Option Name="ActiveSimSet" Val="sim_1"/>
<Option Name="DefaultLib" Val="xil_defaultlib"/>
<Option Name="ProjectType" Val="Default"/>
<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
<Option Name="IPDefaultOutputPath" Val="$PGENDIR/sources_1"/>
<Option Name="IPCachePermission" Val="read"/>
<Option Name="IPCachePermission" Val="write"/>
<Option Name="EnableCoreContainer" Val="FALSE"/>
<Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
<Option Name="EnableBDX" Val="FALSE"/>
<Option Name="DSABoardId" Val="arty-z7-20"/>
<Option Name="WTXSimLaunchSim" Val="0"/>
<Option Name="WTModelSimLaunchSim" Val="0"/>
<Option Name="WTQuestaLaunchSim" Val="0"/>
<Option Name="WTIesLaunchSim" Val="0"/>
<Option Name="WTVcsLaunchSim" Val="0"/>
<Option Name="WTRivieraLaunchSim" Val="0"/>
<Option Name="WTActivehdlLaunchSim" Val="0"/>
<Option Name="WTXSimExportSim" Val="0"/>
<Option Name="WTModelSimExportSim" Val="0"/>
<Option Name="WTQuestaExportSim" Val="0"/>
<Option Name="WTIesExportSim" Val="0"/>
<Option Name="WTVcsExportSim" Val="0"/>
<Option Name="WTRivieraExportSim" Val="0"/>
<Option Name="WTActivehdlExportSim" Val="0"/>
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
<Option Name="XSimRadix" Val="hex"/>
<Option Name="XSimTimeUnit" Val="ns"/>
<Option Name="XSimArrayDisplayLimit" Val="1024"/>
<Option Name="XSimTraceLimit" Val="65536"/>
<Option Name="SimTypes" Val="rtl"/>
<Option Name="SimTypes" Val="bfm"/>
<Option Name="SimTypes" Val="tlm"/>
<Option Name="SimTypes" Val="tlm_dpi"/>
<Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
<Option Name="DcpsUptoDate" Val="TRUE"/>
<Option Name="DSAExtensible" Val="FALSE"/>
</Configuration>
<FileSets Version="1" Minor="31">
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
<Filter Type="Srcs"/>
<File Path="$PSRCDIR/sources_1/bd/artyz7_bd/artyz7_bd.bd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
<CompFileExtendedInfo CompFileName="artyz7_bd.bd" FileRelPathName="ip/artyz7_bd_processing_system7_0_0/artyz7_bd_processing_system7_0_0.xci">
<Proxy FileSetName="artyz7_bd_processing_system7_0_0"/>
</CompFileExtendedInfo>
<CompFileExtendedInfo CompFileName="artyz7_bd.bd" FileRelPathName="ip/artyz7_bd_clk_wiz_0_0/artyz7_bd_clk_wiz_0_0.xci">
<Proxy FileSetName="artyz7_bd_clk_wiz_0_0"/>
</CompFileExtendedInfo>
<CompFileExtendedInfo CompFileName="artyz7_bd.bd" FileRelPathName="ip/artyz7_bd_axi_gpio_0_0/artyz7_bd_axi_gpio_0_0.xci">
<Proxy FileSetName="artyz7_bd_axi_gpio_0_0"/>
</CompFileExtendedInfo>
<CompFileExtendedInfo CompFileName="artyz7_bd.bd" FileRelPathName="ip/artyz7_bd_xbar_0/artyz7_bd_xbar_0.xci">
<Proxy FileSetName="artyz7_bd_xbar_0"/>
</CompFileExtendedInfo>
<CompFileExtendedInfo CompFileName="artyz7_bd.bd" FileRelPathName="ip/artyz7_bd_rst_ps7_0_100M_0/artyz7_bd_rst_ps7_0_100M_0.xci">
<Proxy FileSetName="artyz7_bd_rst_ps7_0_100M_0"/>
</CompFileExtendedInfo>
<CompFileExtendedInfo CompFileName="artyz7_bd.bd" FileRelPathName="ip/artyz7_bd_axi_quad_spi_0_0/artyz7_bd_axi_quad_spi_0_0.xci">
<Proxy FileSetName="artyz7_bd_axi_quad_spi_0_0"/>
</CompFileExtendedInfo>
<CompFileExtendedInfo CompFileName="artyz7_bd.bd" FileRelPathName="ip/artyz7_bd_axi_gpio_1_0/artyz7_bd_axi_gpio_1_0.xci">
<Proxy FileSetName="artyz7_bd_axi_gpio_1_0"/>
</CompFileExtendedInfo>
<CompFileExtendedInfo CompFileName="artyz7_bd.bd" FileRelPathName="ip/artyz7_bd_axi_gpio_2_0/artyz7_bd_axi_gpio_2_0.xci">
<Proxy FileSetName="artyz7_bd_axi_gpio_2_0"/>
</CompFileExtendedInfo>
<CompFileExtendedInfo CompFileName="artyz7_bd.bd" FileRelPathName="ip/artyz7_bd_axi_dma_0_0/artyz7_bd_axi_dma_0_0.xci">
<Proxy FileSetName="artyz7_bd_axi_dma_0_0"/>
</CompFileExtendedInfo>
<CompFileExtendedInfo CompFileName="artyz7_bd.bd" FileRelPathName="ip/artyz7_bd_xbar_1/artyz7_bd_xbar_1.xci">
<Proxy FileSetName="artyz7_bd_xbar_1"/>
</CompFileExtendedInfo>
<CompFileExtendedInfo CompFileName="artyz7_bd.bd" FileRelPathName="ip/artyz7_bd_axis_data_fifo_0_0/artyz7_bd_axis_data_fifo_0_0.xci">
<Proxy FileSetName="artyz7_bd_axis_data_fifo_0_0"/>
</CompFileExtendedInfo>
</File>
<File Path="$PGENDIR/sources_1/bd/artyz7_bd/hdl/artyz7_bd_wrapper.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/FIR_15taps.v">
<FileInfo>
<Attr Name="UserDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/divideby5_mask.v">
<FileInfo>
<Attr Name="UserDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="artyz7_bd_wrapper"/>
<Option Name="TopAutoSet" Val="TRUE"/>
</Config>
</FileSet>
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
<Filter Type="Constrs"/>
<Config>
<Option Name="ConstrsType" Val="XDC"/>
</Config>
</FileSet>
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
<Filter Type="Srcs"/>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="artyz7_bd_wrapper"/>
<Option Name="TopLib" Val="xil_defaultlib"/>
<Option Name="TopAutoSet" Val="TRUE"/>
<Option Name="TransportPathDelay" Val="0"/>
<Option Name="TransportIntDelay" Val="0"/>
<Option Name="SelectedSimModel" Val="rtl"/>
<Option Name="PamDesignTestbench" Val=""/>
<Option Name="PamDutBypassFile" Val="xil_dut_bypass"/>
<Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/>
<Option Name="PamPseudoTop" Val="pseudo_tb"/>
<Option Name="SrcSet" Val="sources_1"/>
</Config>
</FileSet>
<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
<Filter Type="Utils"/>
<Config>
<Option Name="TopAutoSet" Val="TRUE"/>
</Config>
</FileSet>
<FileSet Name="artyz7_bd_processing_system7_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/artyz7_bd_processing_system7_0_0" RelGenDir="$PGENDIR/artyz7_bd_processing_system7_0_0">
<Config>
<Option Name="TopModule" Val="artyz7_bd_processing_system7_0_0"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="artyz7_bd_clk_wiz_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/artyz7_bd_clk_wiz_0_0" RelGenDir="$PGENDIR/artyz7_bd_clk_wiz_0_0">
<Config>
<Option Name="TopModule" Val="artyz7_bd_clk_wiz_0_0"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="artyz7_bd_axi_gpio_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/artyz7_bd_axi_gpio_0_0" RelGenDir="$PGENDIR/artyz7_bd_axi_gpio_0_0">
<Config>
<Option Name="TopModule" Val="artyz7_bd_axi_gpio_0_0"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="artyz7_bd_axi_gpio_2_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/artyz7_bd_axi_gpio_2_0" RelGenDir="$PGENDIR/artyz7_bd_axi_gpio_2_0">
<Config>
<Option Name="TopModule" Val="artyz7_bd_axi_gpio_2_0"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="artyz7_bd_axi_gpio_1_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/artyz7_bd_axi_gpio_1_0" RelGenDir="$PGENDIR/artyz7_bd_axi_gpio_1_0">
<Config>
<Option Name="TopModule" Val="artyz7_bd_axi_gpio_1_0"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="artyz7_bd_xbar_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/artyz7_bd_xbar_0" RelGenDir="$PGENDIR/artyz7_bd_xbar_0">
<Config>
<Option Name="TopModule" Val="artyz7_bd_xbar_0"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="artyz7_bd_rst_ps7_0_100M_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/artyz7_bd_rst_ps7_0_100M_0" RelGenDir="$PGENDIR/artyz7_bd_rst_ps7_0_100M_0">
<Config>
<Option Name="TopModule" Val="artyz7_bd_rst_ps7_0_100M_0"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="artyz7_bd_axi_quad_spi_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/artyz7_bd_axi_quad_spi_0_0" RelGenDir="$PGENDIR/artyz7_bd_axi_quad_spi_0_0">
<Config>
<Option Name="TopModule" Val="artyz7_bd_axi_quad_spi_0_0"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="artyz7_bd_axis_data_fifo_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/artyz7_bd_axis_data_fifo_0_0" RelGenDir="$PGENDIR/artyz7_bd_axis_data_fifo_0_0">
<Config>
<Option Name="TopModule" Val="artyz7_bd_axis_data_fifo_0_0"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="artyz7_bd_axi_dma_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/artyz7_bd_axi_dma_0_0" RelGenDir="$PGENDIR/artyz7_bd_axi_dma_0_0">
<Config>
<Option Name="TopModule" Val="artyz7_bd_axi_dma_0_0"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="artyz7_bd_xbar_1" Type="BlockSrcs" RelSrcDir="$PSRCDIR/artyz7_bd_xbar_1" RelGenDir="$PGENDIR/artyz7_bd_xbar_1">
<Config>
<Option Name="TopModule" Val="artyz7_bd_xbar_1"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
</FileSets>
<Simulators>
<Simulator Name="XSim">
<Option Name="Description" Val="Vivado Simulator"/>
<Option Name="CompiledLib" Val="0"/>
</Simulator>
<Simulator Name="ModelSim">
<Option Name="Description" Val="ModelSim Simulator"/>
</Simulator>
<Simulator Name="Questa">
<Option Name="Description" Val="Questa Advanced Simulator"/>
</Simulator>
<Simulator Name="IES">
<Option Name="Description" Val="Incisive Enterprise Simulator (IES)"/>
</Simulator>
<Simulator Name="Xcelium">
<Option Name="Description" Val="Xcelium Parallel Simulator"/>
</Simulator>
<Simulator Name="VCS">
<Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
</Simulator>
<Simulator Name="Riviera">
<Option Name="Description" Val="Riviera-PRO Simulator"/>
</Simulator>
</Simulators>
<Runs Version="1" Minor="15">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7z020clg400-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2020"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="artyz7_bd_processing_system7_0_0_synth_1" Type="Ft3:Synth" SrcSet="artyz7_bd_processing_system7_0_0" Part="xc7z020clg400-1" ConstrsSet="artyz7_bd_processing_system7_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/artyz7_bd_processing_system7_0_0_synth_1" IncludeInArchive="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/artyz7_bd_processing_system7_0_0_synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2020"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="artyz7_bd_clk_wiz_0_0_synth_1" Type="Ft3:Synth" SrcSet="artyz7_bd_clk_wiz_0_0" Part="xc7z020clg400-1" ConstrsSet="artyz7_bd_clk_wiz_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/artyz7_bd_clk_wiz_0_0_synth_1" IncludeInArchive="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/artyz7_bd_clk_wiz_0_0_synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2020"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="artyz7_bd_axi_gpio_0_0_synth_1" Type="Ft3:Synth" SrcSet="artyz7_bd_axi_gpio_0_0" Part="xc7z020clg400-1" ConstrsSet="artyz7_bd_axi_gpio_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/artyz7_bd_axi_gpio_0_0_synth_1" IncludeInArchive="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/artyz7_bd_axi_gpio_0_0_synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2020"/>
<Step Id="synth_design"/>
</Strategy>
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<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
</Gadget>
<Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
<GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
<GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
<GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
</Gadget>
<Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
</Gadget>
</Gadgets>
</Dashboard>
<CurrentDashboard>default_dashboard</CurrentDashboard>
</Dashboards>
</DashboardSummary>
</Project>