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psu_init.tcl
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psu_init.tcl
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#****************************************************************************
###
#
# @file psu_init.tcl
#
# This file is automatically generated
#
#****************************************************************************
set psu_pll_init_data {
# : RPLL INIT
# Register : RPLL_CFG @ 0XFF5E0034</p>
# PLL loop filter resistor control
# PSU_CRL_APB_RPLL_CFG_RES 0x2
# PLL charge pump control
# PSU_CRL_APB_RPLL_CFG_CP 0x3
# PLL loop filter high frequency capacitor control
# PSU_CRL_APB_RPLL_CFG_LFHF 0x3
# Lock circuit counter setting
# PSU_CRL_APB_RPLL_CFG_LOCK_CNT 0x258
# Lock circuit configuration settings for lock windowsize
# PSU_CRL_APB_RPLL_CFG_LOCK_DLY 0x3f
# Helper data. Values are to be looked up in a table from Data Sheet
#(OFFSET, MASK, VALUE) (0XFF5E0034, 0xFE7FEDEFU ,0x7E4B0C62U) */
mask_write 0XFF5E0034 0xFE7FEDEF 0x7E4B0C62
# : UPDATE FB_DIV
# Register : RPLL_CTRL @ 0XFF5E0030</p>
# Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk i
# s the source 100 video clk is the source 101 pss_alt_ref_clk is the sour
# ce 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source
# PSU_CRL_APB_RPLL_CTRL_PRE_SRC 0x0
# The integer portion of the feedback divider to the PLL
# PSU_CRL_APB_RPLL_CTRL_FBDIV 0x46
# This turns on the divide by 2 that is inside of the PLL. This does not c
# hange the VCO frequency, just the output frequency
# PSU_CRL_APB_RPLL_CTRL_DIV2 0x1
# PLL Basic Control
#(OFFSET, MASK, VALUE) (0XFF5E0030, 0x00717F00U ,0x00014600U) */
mask_write 0XFF5E0030 0x00717F00 0x00014600
# : BY PASS PLL
# Register : RPLL_CTRL @ 0XFF5E0030</p>
# Bypasses the PLL clock. The usable clock will be determined from the POS
# T_SRC field. (This signal may only be toggled after 4 cycles of the old
# clock and 4 cycles of the new clock. This is not usually an issue, but d
# esigners must be aware.)
# PSU_CRL_APB_RPLL_CTRL_BYPASS 1
# PLL Basic Control
#(OFFSET, MASK, VALUE) (0XFF5E0030, 0x00000008U ,0x00000008U) */
mask_write 0XFF5E0030 0x00000008 0x00000008
# : ASSERT RESET
# Register : RPLL_CTRL @ 0XFF5E0030</p>
# Asserts Reset to the PLL. When asserting reset, the PLL must already be
# in BYPASS.
# PSU_CRL_APB_RPLL_CTRL_RESET 1
# PLL Basic Control
#(OFFSET, MASK, VALUE) (0XFF5E0030, 0x00000001U ,0x00000001U) */
mask_write 0XFF5E0030 0x00000001 0x00000001
# : DEASSERT RESET
# Register : RPLL_CTRL @ 0XFF5E0030</p>
# Asserts Reset to the PLL. When asserting reset, the PLL must already be
# in BYPASS.
# PSU_CRL_APB_RPLL_CTRL_RESET 0
# PLL Basic Control
#(OFFSET, MASK, VALUE) (0XFF5E0030, 0x00000001U ,0x00000000U) */
mask_write 0XFF5E0030 0x00000001 0x00000000
# : CHECK PLL STATUS
# Register : PLL_STATUS @ 0XFF5E0040</p>
# RPLL is locked
# PSU_CRL_APB_PLL_STATUS_RPLL_LOCK 1
mask_poll 0XFF5E0040 0x00000002
# : REMOVE PLL BY PASS
# Register : RPLL_CTRL @ 0XFF5E0030</p>
# Bypasses the PLL clock. The usable clock will be determined from the POS
# T_SRC field. (This signal may only be toggled after 4 cycles of the old
# clock and 4 cycles of the new clock. This is not usually an issue, but d
# esigners must be aware.)
# PSU_CRL_APB_RPLL_CTRL_BYPASS 0
# PLL Basic Control
#(OFFSET, MASK, VALUE) (0XFF5E0030, 0x00000008U ,0x00000000U) */
mask_write 0XFF5E0030 0x00000008 0x00000000
# Register : RPLL_TO_FPD_CTRL @ 0XFF5E0048</p>
# Divisor value for this clock.
# PSU_CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0 0x3
# Control for a clock that will be generated in the LPD, but used in the F
# PD as a clock source for the peripheral clock muxes.
#(OFFSET, MASK, VALUE) (0XFF5E0048, 0x00003F00U ,0x00000300U) */
mask_write 0XFF5E0048 0x00003F00 0x00000300
# : RPLL FRAC CFG
# Register : RPLL_FRAC_CFG @ 0XFF5E0038</p>
# Fractional SDM bypass control. When 0, PLL is in integer mode and it ign
# ores all fractional data. When 1, PLL is in fractional mode and uses DAT
# A of this register for the fractional portion of the feedback divider.
# PSU_CRL_APB_RPLL_FRAC_CFG_ENABLED 0x1
# Fractional value for the Feedback value.
# PSU_CRL_APB_RPLL_FRAC_CFG_DATA 0xc76c
# Fractional control for the PLL
#(OFFSET, MASK, VALUE) (0XFF5E0038, 0x8000FFFFU ,0x8000C76CU) */
mask_write 0XFF5E0038 0x8000FFFF 0x8000C76C
# : SYSMON CLOCK PRESET TO RPLL AGAIN TO AVOID GLITCH WHEN NEXT IOPLL WILL BE PUT IN BYPASS MODE
# Register : AMS_REF_CTRL @ 0XFF5E0108</p>
# 6 bit divider
# PSU_CRL_APB_AMS_REF_CTRL_DIVISOR1 1
# 6 bit divider
# PSU_CRL_APB_AMS_REF_CTRL_DIVISOR0 35
# 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af
# ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
# usually an issue, but designers must be aware.)
# PSU_CRL_APB_AMS_REF_CTRL_SRCSEL 0
# Clock active signal. Switch to 0 to disable the clock
# PSU_CRL_APB_AMS_REF_CTRL_CLKACT 1
# This register controls this reference clock
#(OFFSET, MASK, VALUE) (0XFF5E0108, 0x013F3F07U ,0x01012300U) */
mask_write 0XFF5E0108 0x013F3F07 0x01012300
# : IOPLL INIT
# Register : IOPLL_CFG @ 0XFF5E0024</p>
# PLL loop filter resistor control
# PSU_CRL_APB_IOPLL_CFG_RES 0xc
# PLL charge pump control
# PSU_CRL_APB_IOPLL_CFG_CP 0x3
# PLL loop filter high frequency capacitor control
# PSU_CRL_APB_IOPLL_CFG_LFHF 0x3
# Lock circuit counter setting
# PSU_CRL_APB_IOPLL_CFG_LOCK_CNT 0x339
# Lock circuit configuration settings for lock windowsize
# PSU_CRL_APB_IOPLL_CFG_LOCK_DLY 0x3f
# Helper data. Values are to be looked up in a table from Data Sheet
#(OFFSET, MASK, VALUE) (0XFF5E0024, 0xFE7FEDEFU ,0x7E672C6CU) */
mask_write 0XFF5E0024 0xFE7FEDEF 0x7E672C6C
# : UPDATE FB_DIV
# Register : IOPLL_CTRL @ 0XFF5E0020</p>
# Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk i
# s the source 100 video clk is the source 101 pss_alt_ref_clk is the sour
# ce 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source
# PSU_CRL_APB_IOPLL_CTRL_PRE_SRC 0x0
# The integer portion of the feedback divider to the PLL
# PSU_CRL_APB_IOPLL_CTRL_FBDIV 0x2d
# This turns on the divide by 2 that is inside of the PLL. This does not c
# hange the VCO frequency, just the output frequency
# PSU_CRL_APB_IOPLL_CTRL_DIV2 0x0
# PLL Basic Control
#(OFFSET, MASK, VALUE) (0XFF5E0020, 0x00717F00U ,0x00002D00U) */
mask_write 0XFF5E0020 0x00717F00 0x00002D00
# : BY PASS PLL
# Register : IOPLL_CTRL @ 0XFF5E0020</p>
# Bypasses the PLL clock. The usable clock will be determined from the POS
# T_SRC field. (This signal may only be toggled after 4 cycles of the old
# clock and 4 cycles of the new clock. This is not usually an issue, but d
# esigners must be aware.)
# PSU_CRL_APB_IOPLL_CTRL_BYPASS 1
# PLL Basic Control
#(OFFSET, MASK, VALUE) (0XFF5E0020, 0x00000008U ,0x00000008U) */
mask_write 0XFF5E0020 0x00000008 0x00000008
# : ASSERT RESET
# Register : IOPLL_CTRL @ 0XFF5E0020</p>
# Asserts Reset to the PLL. When asserting reset, the PLL must already be
# in BYPASS.
# PSU_CRL_APB_IOPLL_CTRL_RESET 1
# PLL Basic Control
#(OFFSET, MASK, VALUE) (0XFF5E0020, 0x00000001U ,0x00000001U) */
mask_write 0XFF5E0020 0x00000001 0x00000001
# : DEASSERT RESET
# Register : IOPLL_CTRL @ 0XFF5E0020</p>
# Asserts Reset to the PLL. When asserting reset, the PLL must already be
# in BYPASS.
# PSU_CRL_APB_IOPLL_CTRL_RESET 0
# PLL Basic Control
#(OFFSET, MASK, VALUE) (0XFF5E0020, 0x00000001U ,0x00000000U) */
mask_write 0XFF5E0020 0x00000001 0x00000000
# : CHECK PLL STATUS
# Register : PLL_STATUS @ 0XFF5E0040</p>
# IOPLL is locked
# PSU_CRL_APB_PLL_STATUS_IOPLL_LOCK 1
mask_poll 0XFF5E0040 0x00000001
# : REMOVE PLL BY PASS
# Register : IOPLL_CTRL @ 0XFF5E0020</p>
# Bypasses the PLL clock. The usable clock will be determined from the POS
# T_SRC field. (This signal may only be toggled after 4 cycles of the old
# clock and 4 cycles of the new clock. This is not usually an issue, but d
# esigners must be aware.)
# PSU_CRL_APB_IOPLL_CTRL_BYPASS 0
# PLL Basic Control
#(OFFSET, MASK, VALUE) (0XFF5E0020, 0x00000008U ,0x00000000U) */
mask_write 0XFF5E0020 0x00000008 0x00000000
# Register : IOPLL_TO_FPD_CTRL @ 0XFF5E0044</p>
# Divisor value for this clock.
# PSU_CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0 0x3
# Control for a clock that will be generated in the LPD, but used in the F
# PD as a clock source for the peripheral clock muxes.
#(OFFSET, MASK, VALUE) (0XFF5E0044, 0x00003F00U ,0x00000300U) */
mask_write 0XFF5E0044 0x00003F00 0x00000300
# : IOPLL FRAC CFG
# Register : IOPLL_FRAC_CFG @ 0XFF5E0028</p>
# Fractional SDM bypass control. When 0, PLL is in integer mode and it ign
# ores all fractional data. When 1, PLL is in fractional mode and uses DAT
# A of this register for the fractional portion of the feedback divider.
# PSU_CRL_APB_IOPLL_FRAC_CFG_ENABLED 0x0
# Fractional value for the Feedback value.
# PSU_CRL_APB_IOPLL_FRAC_CFG_DATA 0x0
# Fractional control for the PLL
#(OFFSET, MASK, VALUE) (0XFF5E0028, 0x8000FFFFU ,0x00000000U) */
mask_write 0XFF5E0028 0x8000FFFF 0x00000000
# : APU_PLL INIT
# Register : APLL_CFG @ 0XFD1A0024</p>
# PLL loop filter resistor control
# PSU_CRF_APB_APLL_CFG_RES 0x2
# PLL charge pump control
# PSU_CRF_APB_APLL_CFG_CP 0x3
# PLL loop filter high frequency capacitor control
# PSU_CRF_APB_APLL_CFG_LFHF 0x3
# Lock circuit counter setting
# PSU_CRF_APB_APLL_CFG_LOCK_CNT 0x258
# Lock circuit configuration settings for lock windowsize
# PSU_CRF_APB_APLL_CFG_LOCK_DLY 0x3f
# Helper data. Values are to be looked up in a table from Data Sheet
#(OFFSET, MASK, VALUE) (0XFD1A0024, 0xFE7FEDEFU ,0x7E4B0C62U) */
mask_write 0XFD1A0024 0xFE7FEDEF 0x7E4B0C62
# : UPDATE FB_DIV
# Register : APLL_CTRL @ 0XFD1A0020</p>
# Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk i
# s the source 100 video clk is the source 101 pss_alt_ref_clk is the sour
# ce 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source
# PSU_CRF_APB_APLL_CTRL_PRE_SRC 0x0
# The integer portion of the feedback divider to the PLL
# PSU_CRF_APB_APLL_CTRL_FBDIV 0x48
# This turns on the divide by 2 that is inside of the PLL. This does not c
# hange the VCO frequency, just the output frequency
# PSU_CRF_APB_APLL_CTRL_DIV2 0x1
# PLL Basic Control
#(OFFSET, MASK, VALUE) (0XFD1A0020, 0x00717F00U ,0x00014800U) */
mask_write 0XFD1A0020 0x00717F00 0x00014800
# : BY PASS PLL
# Register : APLL_CTRL @ 0XFD1A0020</p>
# Bypasses the PLL clock. The usable clock will be determined from the POS
# T_SRC field. (This signal may only be toggled after 4 cycles of the old
# clock and 4 cycles of the new clock. This is not usually an issue, but d
# esigners must be aware.)
# PSU_CRF_APB_APLL_CTRL_BYPASS 1
# PLL Basic Control
#(OFFSET, MASK, VALUE) (0XFD1A0020, 0x00000008U ,0x00000008U) */
mask_write 0XFD1A0020 0x00000008 0x00000008
# : ASSERT RESET
# Register : APLL_CTRL @ 0XFD1A0020</p>
# Asserts Reset to the PLL. When asserting reset, the PLL must already be
# in BYPASS.
# PSU_CRF_APB_APLL_CTRL_RESET 1
# PLL Basic Control
#(OFFSET, MASK, VALUE) (0XFD1A0020, 0x00000001U ,0x00000001U) */
mask_write 0XFD1A0020 0x00000001 0x00000001
# : DEASSERT RESET
# Register : APLL_CTRL @ 0XFD1A0020</p>
# Asserts Reset to the PLL. When asserting reset, the PLL must already be
# in BYPASS.
# PSU_CRF_APB_APLL_CTRL_RESET 0
# PLL Basic Control
#(OFFSET, MASK, VALUE) (0XFD1A0020, 0x00000001U ,0x00000000U) */
mask_write 0XFD1A0020 0x00000001 0x00000000
# : CHECK PLL STATUS
# Register : PLL_STATUS @ 0XFD1A0044</p>
# APLL is locked
# PSU_CRF_APB_PLL_STATUS_APLL_LOCK 1
mask_poll 0XFD1A0044 0x00000001
# : REMOVE PLL BY PASS
# Register : APLL_CTRL @ 0XFD1A0020</p>
# Bypasses the PLL clock. The usable clock will be determined from the POS
# T_SRC field. (This signal may only be toggled after 4 cycles of the old
# clock and 4 cycles of the new clock. This is not usually an issue, but d
# esigners must be aware.)
# PSU_CRF_APB_APLL_CTRL_BYPASS 0
# PLL Basic Control
#(OFFSET, MASK, VALUE) (0XFD1A0020, 0x00000008U ,0x00000000U) */
mask_write 0XFD1A0020 0x00000008 0x00000000
# Register : APLL_TO_LPD_CTRL @ 0XFD1A0048</p>
# Divisor value for this clock.
# PSU_CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0 0x3
# Control for a clock that will be generated in the FPD, but used in the L
# PD as a clock source for the peripheral clock muxes.
#(OFFSET, MASK, VALUE) (0XFD1A0048, 0x00003F00U ,0x00000300U) */
mask_write 0XFD1A0048 0x00003F00 0x00000300
# : APLL FRAC CFG
# Register : APLL_FRAC_CFG @ 0XFD1A0028</p>
# Fractional SDM bypass control. When 0, PLL is in integer mode and it ign
# ores all fractional data. When 1, PLL is in fractional mode and uses DAT
# A of this register for the fractional portion of the feedback divider.
# PSU_CRF_APB_APLL_FRAC_CFG_ENABLED 0x0
# Fractional value for the Feedback value.
# PSU_CRF_APB_APLL_FRAC_CFG_DATA 0x0
# Fractional control for the PLL
#(OFFSET, MASK, VALUE) (0XFD1A0028, 0x8000FFFFU ,0x00000000U) */
mask_write 0XFD1A0028 0x8000FFFF 0x00000000
# : DDR_PLL INIT
# Register : DPLL_CFG @ 0XFD1A0030</p>
# PLL loop filter resistor control
# PSU_CRF_APB_DPLL_CFG_RES 0x2
# PLL charge pump control
# PSU_CRF_APB_DPLL_CFG_CP 0x3
# PLL loop filter high frequency capacitor control
# PSU_CRF_APB_DPLL_CFG_LFHF 0x3
# Lock circuit counter setting
# PSU_CRF_APB_DPLL_CFG_LOCK_CNT 0x258
# Lock circuit configuration settings for lock windowsize
# PSU_CRF_APB_DPLL_CFG_LOCK_DLY 0x3f
# Helper data. Values are to be looked up in a table from Data Sheet
#(OFFSET, MASK, VALUE) (0XFD1A0030, 0xFE7FEDEFU ,0x7E4B0C62U) */
mask_write 0XFD1A0030 0xFE7FEDEF 0x7E4B0C62
# : UPDATE FB_DIV
# Register : DPLL_CTRL @ 0XFD1A002C</p>
# Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk i
# s the source 100 video clk is the source 101 pss_alt_ref_clk is the sour
# ce 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source
# PSU_CRF_APB_DPLL_CTRL_PRE_SRC 0x0
# The integer portion of the feedback divider to the PLL
# PSU_CRF_APB_DPLL_CTRL_FBDIV 0x40
# This turns on the divide by 2 that is inside of the PLL. This does not c
# hange the VCO frequency, just the output frequency
# PSU_CRF_APB_DPLL_CTRL_DIV2 0x1
# PLL Basic Control
#(OFFSET, MASK, VALUE) (0XFD1A002C, 0x00717F00U ,0x00014000U) */
mask_write 0XFD1A002C 0x00717F00 0x00014000
# : BY PASS PLL
# Register : DPLL_CTRL @ 0XFD1A002C</p>
# Bypasses the PLL clock. The usable clock will be determined from the POS
# T_SRC field. (This signal may only be toggled after 4 cycles of the old
# clock and 4 cycles of the new clock. This is not usually an issue, but d
# esigners must be aware.)
# PSU_CRF_APB_DPLL_CTRL_BYPASS 1
# PLL Basic Control
#(OFFSET, MASK, VALUE) (0XFD1A002C, 0x00000008U ,0x00000008U) */
mask_write 0XFD1A002C 0x00000008 0x00000008
# : ASSERT RESET
# Register : DPLL_CTRL @ 0XFD1A002C</p>
# Asserts Reset to the PLL. When asserting reset, the PLL must already be
# in BYPASS.
# PSU_CRF_APB_DPLL_CTRL_RESET 1
# PLL Basic Control
#(OFFSET, MASK, VALUE) (0XFD1A002C, 0x00000001U ,0x00000001U) */
mask_write 0XFD1A002C 0x00000001 0x00000001
# : DEASSERT RESET
# Register : DPLL_CTRL @ 0XFD1A002C</p>
# Asserts Reset to the PLL. When asserting reset, the PLL must already be
# in BYPASS.
# PSU_CRF_APB_DPLL_CTRL_RESET 0
# PLL Basic Control
#(OFFSET, MASK, VALUE) (0XFD1A002C, 0x00000001U ,0x00000000U) */
mask_write 0XFD1A002C 0x00000001 0x00000000
# : CHECK PLL STATUS
# Register : PLL_STATUS @ 0XFD1A0044</p>
# DPLL is locked
# PSU_CRF_APB_PLL_STATUS_DPLL_LOCK 1
mask_poll 0XFD1A0044 0x00000002
# : REMOVE PLL BY PASS
# Register : DPLL_CTRL @ 0XFD1A002C</p>
# Bypasses the PLL clock. The usable clock will be determined from the POS
# T_SRC field. (This signal may only be toggled after 4 cycles of the old
# clock and 4 cycles of the new clock. This is not usually an issue, but d
# esigners must be aware.)
# PSU_CRF_APB_DPLL_CTRL_BYPASS 0
# PLL Basic Control
#(OFFSET, MASK, VALUE) (0XFD1A002C, 0x00000008U ,0x00000000U) */
mask_write 0XFD1A002C 0x00000008 0x00000000
# Register : DPLL_TO_LPD_CTRL @ 0XFD1A004C</p>
# Divisor value for this clock.
# PSU_CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0 0x3
# Control for a clock that will be generated in the FPD, but used in the L
# PD as a clock source for the peripheral clock muxes.
#(OFFSET, MASK, VALUE) (0XFD1A004C, 0x00003F00U ,0x00000300U) */
mask_write 0XFD1A004C 0x00003F00 0x00000300
# : DPLL FRAC CFG
# Register : DPLL_FRAC_CFG @ 0XFD1A0034</p>
# Fractional SDM bypass control. When 0, PLL is in integer mode and it ign
# ores all fractional data. When 1, PLL is in fractional mode and uses DAT
# A of this register for the fractional portion of the feedback divider.
# PSU_CRF_APB_DPLL_FRAC_CFG_ENABLED 0x0
# Fractional value for the Feedback value.
# PSU_CRF_APB_DPLL_FRAC_CFG_DATA 0x0
# Fractional control for the PLL
#(OFFSET, MASK, VALUE) (0XFD1A0034, 0x8000FFFFU ,0x00000000U) */
mask_write 0XFD1A0034 0x8000FFFF 0x00000000
# : VIDEO_PLL INIT
# Register : VPLL_CFG @ 0XFD1A003C</p>
# PLL loop filter resistor control
# PSU_CRF_APB_VPLL_CFG_RES 0x2
# PLL charge pump control
# PSU_CRF_APB_VPLL_CFG_CP 0x3
# PLL loop filter high frequency capacitor control
# PSU_CRF_APB_VPLL_CFG_LFHF 0x3
# Lock circuit counter setting
# PSU_CRF_APB_VPLL_CFG_LOCK_CNT 0x258
# Lock circuit configuration settings for lock windowsize
# PSU_CRF_APB_VPLL_CFG_LOCK_DLY 0x3f
# Helper data. Values are to be looked up in a table from Data Sheet
#(OFFSET, MASK, VALUE) (0XFD1A003C, 0xFE7FEDEFU ,0x7E4B0C62U) */
mask_write 0XFD1A003C 0xFE7FEDEF 0x7E4B0C62
# : UPDATE FB_DIV
# Register : VPLL_CTRL @ 0XFD1A0038</p>
# Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk i
# s the source 100 video clk is the source 101 pss_alt_ref_clk is the sour
# ce 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source
# PSU_CRF_APB_VPLL_CTRL_PRE_SRC 0x0
# The integer portion of the feedback divider to the PLL
# PSU_CRF_APB_VPLL_CTRL_FBDIV 0x47
# This turns on the divide by 2 that is inside of the PLL. This does not c
# hange the VCO frequency, just the output frequency
# PSU_CRF_APB_VPLL_CTRL_DIV2 0x1
# PLL Basic Control
#(OFFSET, MASK, VALUE) (0XFD1A0038, 0x00717F00U ,0x00014700U) */
mask_write 0XFD1A0038 0x00717F00 0x00014700
# : BY PASS PLL
# Register : VPLL_CTRL @ 0XFD1A0038</p>
# Bypasses the PLL clock. The usable clock will be determined from the POS
# T_SRC field. (This signal may only be toggled after 4 cycles of the old
# clock and 4 cycles of the new clock. This is not usually an issue, but d
# esigners must be aware.)
# PSU_CRF_APB_VPLL_CTRL_BYPASS 1
# PLL Basic Control
#(OFFSET, MASK, VALUE) (0XFD1A0038, 0x00000008U ,0x00000008U) */
mask_write 0XFD1A0038 0x00000008 0x00000008
# : ASSERT RESET
# Register : VPLL_CTRL @ 0XFD1A0038</p>
# Asserts Reset to the PLL. When asserting reset, the PLL must already be
# in BYPASS.
# PSU_CRF_APB_VPLL_CTRL_RESET 1
# PLL Basic Control
#(OFFSET, MASK, VALUE) (0XFD1A0038, 0x00000001U ,0x00000001U) */
mask_write 0XFD1A0038 0x00000001 0x00000001
# : DEASSERT RESET
# Register : VPLL_CTRL @ 0XFD1A0038</p>
# Asserts Reset to the PLL. When asserting reset, the PLL must already be
# in BYPASS.
# PSU_CRF_APB_VPLL_CTRL_RESET 0
# PLL Basic Control
#(OFFSET, MASK, VALUE) (0XFD1A0038, 0x00000001U ,0x00000000U) */
mask_write 0XFD1A0038 0x00000001 0x00000000
# : CHECK PLL STATUS
# Register : PLL_STATUS @ 0XFD1A0044</p>
# VPLL is locked
# PSU_CRF_APB_PLL_STATUS_VPLL_LOCK 1
mask_poll 0XFD1A0044 0x00000004
# : REMOVE PLL BY PASS
# Register : VPLL_CTRL @ 0XFD1A0038</p>
# Bypasses the PLL clock. The usable clock will be determined from the POS
# T_SRC field. (This signal may only be toggled after 4 cycles of the old
# clock and 4 cycles of the new clock. This is not usually an issue, but d
# esigners must be aware.)
# PSU_CRF_APB_VPLL_CTRL_BYPASS 0
# PLL Basic Control
#(OFFSET, MASK, VALUE) (0XFD1A0038, 0x00000008U ,0x00000000U) */
mask_write 0XFD1A0038 0x00000008 0x00000000
# Register : VPLL_TO_LPD_CTRL @ 0XFD1A0050</p>
# Divisor value for this clock.
# PSU_CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0 0x3
# Control for a clock that will be generated in the FPD, but used in the L
# PD as a clock source for the peripheral clock muxes.
#(OFFSET, MASK, VALUE) (0XFD1A0050, 0x00003F00U ,0x00000300U) */
mask_write 0XFD1A0050 0x00003F00 0x00000300
# : VIDEO FRAC CFG
# Register : VPLL_FRAC_CFG @ 0XFD1A0040</p>
# Fractional SDM bypass control. When 0, PLL is in integer mode and it ign
# ores all fractional data. When 1, PLL is in fractional mode and uses DAT
# A of this register for the fractional portion of the feedback divider.
# PSU_CRF_APB_VPLL_FRAC_CFG_ENABLED 0x1
# Fractional value for the Feedback value.
# PSU_CRF_APB_VPLL_FRAC_CFG_DATA 0x497f
# Fractional control for the PLL
#(OFFSET, MASK, VALUE) (0XFD1A0040, 0x8000FFFFU ,0x8000497FU) */
mask_write 0XFD1A0040 0x8000FFFF 0x8000497F
}
set psu_clock_init_data {
# : CLOCK CONTROL SLCR REGISTER
# Register : USB0_BUS_REF_CTRL @ 0XFF5E0060</p>
# Clock active signal. Switch to 0 to disable the clock
# PSU_CRL_APB_USB0_BUS_REF_CTRL_CLKACT 0x1
# 6 bit divider
# PSU_CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1 0x1
# 6 bit divider
# PSU_CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0 0x6
# 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af
# ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
# usually an issue, but designers must be aware.)
# PSU_CRL_APB_USB0_BUS_REF_CTRL_SRCSEL 0x0
# This register controls this reference clock
#(OFFSET, MASK, VALUE) (0XFF5E0060, 0x023F3F07U ,0x02010600U) */
mask_write 0XFF5E0060 0x023F3F07 0x02010600
# Register : USB1_BUS_REF_CTRL @ 0XFF5E0064</p>
# Clock active signal. Switch to 0 to disable the clock
# PSU_CRL_APB_USB1_BUS_REF_CTRL_CLKACT 0x1
# 6 bit divider
# PSU_CRL_APB_USB1_BUS_REF_CTRL_DIVISOR1 0x1
# 6 bit divider
# PSU_CRL_APB_USB1_BUS_REF_CTRL_DIVISOR0 0x6
# 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af
# ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
# usually an issue, but designers must be aware.)
# PSU_CRL_APB_USB1_BUS_REF_CTRL_SRCSEL 0x0
# This register controls this reference clock
#(OFFSET, MASK, VALUE) (0XFF5E0064, 0x023F3F07U ,0x02010600U) */
mask_write 0XFF5E0064 0x023F3F07 0x02010600
# Register : USB3_DUAL_REF_CTRL @ 0XFF5E004C</p>
# Clock active signal. Switch to 0 to disable the clock
# PSU_CRL_APB_USB3_DUAL_REF_CTRL_CLKACT 0x1
# 6 bit divider
# PSU_CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1 0xf
# 6 bit divider
# PSU_CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0 0x5
# 000 = IOPLL; 010 = RPLL; 011 = DPLL. (This signal may only be toggled af
# ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
# usually an issue, but designers must be aware.)
# PSU_CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL 0x0
# This register controls this reference clock
#(OFFSET, MASK, VALUE) (0XFF5E004C, 0x023F3F07U ,0x020F0500U) */
mask_write 0XFF5E004C 0x023F3F07 0x020F0500
# Register : SDIO0_REF_CTRL @ 0XFF5E006C</p>
# Clock active signal. Switch to 0 to disable the clock
# PSU_CRL_APB_SDIO0_REF_CTRL_CLKACT 0x1
# 6 bit divider
# PSU_CRL_APB_SDIO0_REF_CTRL_DIVISOR1 0x1
# 6 bit divider
# PSU_CRL_APB_SDIO0_REF_CTRL_DIVISOR0 0x8
# 000 = IOPLL; 010 = RPLL; 011 = VPLL; (This signal may only be toggled af
# ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
# usually an issue, but designers must be aware.)
# PSU_CRL_APB_SDIO0_REF_CTRL_SRCSEL 0x0
# This register controls this reference clock
#(OFFSET, MASK, VALUE) (0XFF5E006C, 0x013F3F07U ,0x01010800U) */
mask_write 0XFF5E006C 0x013F3F07 0x01010800
# Register : SDIO1_REF_CTRL @ 0XFF5E0070</p>
# Clock active signal. Switch to 0 to disable the clock
# PSU_CRL_APB_SDIO1_REF_CTRL_CLKACT 0x1
# 6 bit divider
# PSU_CRL_APB_SDIO1_REF_CTRL_DIVISOR1 0x1
# 6 bit divider
# PSU_CRL_APB_SDIO1_REF_CTRL_DIVISOR0 0x8
# 000 = IOPLL; 010 = RPLL; 011 = VPLL; (This signal may only be toggled af
# ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
# usually an issue, but designers must be aware.)
# PSU_CRL_APB_SDIO1_REF_CTRL_SRCSEL 0x0
# This register controls this reference clock
#(OFFSET, MASK, VALUE) (0XFF5E0070, 0x013F3F07U ,0x01010800U) */
mask_write 0XFF5E0070 0x013F3F07 0x01010800
# Register : SDIO_CLK_CTRL @ 0XFF18030C</p>
# MIO pad selection for sdio0_rx_clk (feedback clock from the PAD) 00: MIO
# [22] 01: MIO [38] 10: MIO [64] 11: MIO [64]
# PSU_IOU_SLCR_SDIO_CLK_CTRL_SDIO0_RX_SRC_SEL 0
# MIO pad selection for sdio1_rx_clk (feedback clock from the PAD) 0: MIO
# [51] 1: MIO [76]
# PSU_IOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL 0
# SoC Debug Clock Control
#(OFFSET, MASK, VALUE) (0XFF18030C, 0x00020003U ,0x00000000U) */
mask_write 0XFF18030C 0x00020003 0x00000000
# Register : UART0_REF_CTRL @ 0XFF5E0074</p>
# Clock active signal. Switch to 0 to disable the clock
# PSU_CRL_APB_UART0_REF_CTRL_CLKACT 0x1
# 6 bit divider
# PSU_CRL_APB_UART0_REF_CTRL_DIVISOR1 0x1
# 6 bit divider
# PSU_CRL_APB_UART0_REF_CTRL_DIVISOR0 0xf
# 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af
# ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
# usually an issue, but designers must be aware.)
# PSU_CRL_APB_UART0_REF_CTRL_SRCSEL 0x0
# This register controls this reference clock
#(OFFSET, MASK, VALUE) (0XFF5E0074, 0x013F3F07U ,0x01010F00U) */
mask_write 0XFF5E0074 0x013F3F07 0x01010F00
# Register : UART1_REF_CTRL @ 0XFF5E0078</p>
# Clock active signal. Switch to 0 to disable the clock
# PSU_CRL_APB_UART1_REF_CTRL_CLKACT 0x1
# 6 bit divider
# PSU_CRL_APB_UART1_REF_CTRL_DIVISOR1 0x1
# 6 bit divider
# PSU_CRL_APB_UART1_REF_CTRL_DIVISOR0 0xf
# 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af
# ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
# usually an issue, but designers must be aware.)
# PSU_CRL_APB_UART1_REF_CTRL_SRCSEL 0x0
# This register controls this reference clock
#(OFFSET, MASK, VALUE) (0XFF5E0078, 0x013F3F07U ,0x01010F00U) */
mask_write 0XFF5E0078 0x013F3F07 0x01010F00
# Register : I2C1_REF_CTRL @ 0XFF5E0124</p>
# Clock active signal. Switch to 0 to disable the clock
# PSU_CRL_APB_I2C1_REF_CTRL_CLKACT 0x1
# 6 bit divider
# PSU_CRL_APB_I2C1_REF_CTRL_DIVISOR1 0x1
# 6 bit divider
# PSU_CRL_APB_I2C1_REF_CTRL_DIVISOR0 0xf
# 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af
# ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
# usually an issue, but designers must be aware.)
# PSU_CRL_APB_I2C1_REF_CTRL_SRCSEL 0x0
# This register controls this reference clock
#(OFFSET, MASK, VALUE) (0XFF5E0124, 0x013F3F07U ,0x01010F00U) */
mask_write 0XFF5E0124 0x013F3F07 0x01010F00
# Register : SPI0_REF_CTRL @ 0XFF5E007C</p>
# Clock active signal. Switch to 0 to disable the clock
# PSU_CRL_APB_SPI0_REF_CTRL_CLKACT 0x1
# 6 bit divider
# PSU_CRL_APB_SPI0_REF_CTRL_DIVISOR1 0x1
# 6 bit divider
# PSU_CRL_APB_SPI0_REF_CTRL_DIVISOR0 0x8
# 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af
# ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
# usually an issue, but designers must be aware.)
# PSU_CRL_APB_SPI0_REF_CTRL_SRCSEL 0x0
# This register controls this reference clock
#(OFFSET, MASK, VALUE) (0XFF5E007C, 0x013F3F07U ,0x01010800U) */
mask_write 0XFF5E007C 0x013F3F07 0x01010800
# Register : SPI1_REF_CTRL @ 0XFF5E0080</p>
# Clock active signal. Switch to 0 to disable the clock
# PSU_CRL_APB_SPI1_REF_CTRL_CLKACT 0x1
# 6 bit divider
# PSU_CRL_APB_SPI1_REF_CTRL_DIVISOR1 0x1
# 6 bit divider
# PSU_CRL_APB_SPI1_REF_CTRL_DIVISOR0 0x8
# 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af
# ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
# usually an issue, but designers must be aware.)
# PSU_CRL_APB_SPI1_REF_CTRL_SRCSEL 0x0
# This register controls this reference clock
#(OFFSET, MASK, VALUE) (0XFF5E0080, 0x013F3F07U ,0x01010800U) */
mask_write 0XFF5E0080 0x013F3F07 0x01010800
# Register : CPU_R5_CTRL @ 0XFF5E0090</p>
# Turing this off will shut down the OCM, some parts of the APM, and preve
# nt transactions going from the FPD to the LPD and could lead to system h
# ang
# PSU_CRL_APB_CPU_R5_CTRL_CLKACT 0x1
# 6 bit divider
# PSU_CRL_APB_CPU_R5_CTRL_DIVISOR0 0x3
# 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af
# ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
# usually an issue, but designers must be aware.)
# PSU_CRL_APB_CPU_R5_CTRL_SRCSEL 0x2
# This register controls this reference clock
#(OFFSET, MASK, VALUE) (0XFF5E0090, 0x01003F07U ,0x01000302U) */
mask_write 0XFF5E0090 0x01003F07 0x01000302
# Register : IOU_SWITCH_CTRL @ 0XFF5E009C</p>
# Clock active signal. Switch to 0 to disable the clock
# PSU_CRL_APB_IOU_SWITCH_CTRL_CLKACT 0x1
# 6 bit divider
# PSU_CRL_APB_IOU_SWITCH_CTRL_DIVISOR0 0x6
# 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af
# ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
# usually an issue, but designers must be aware.)
# PSU_CRL_APB_IOU_SWITCH_CTRL_SRCSEL 0x2
# This register controls this reference clock
#(OFFSET, MASK, VALUE) (0XFF5E009C, 0x01003F07U ,0x01000602U) */
mask_write 0XFF5E009C 0x01003F07 0x01000602
# Register : PCAP_CTRL @ 0XFF5E00A4</p>
# Clock active signal. Switch to 0 to disable the clock
# PSU_CRL_APB_PCAP_CTRL_CLKACT 0x1
# 6 bit divider
# PSU_CRL_APB_PCAP_CTRL_DIVISOR0 0x8
# 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af
# ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
# usually an issue, but designers must be aware.)
# PSU_CRL_APB_PCAP_CTRL_SRCSEL 0x0
# This register controls this reference clock
#(OFFSET, MASK, VALUE) (0XFF5E00A4, 0x01003F07U ,0x01000800U) */
mask_write 0XFF5E00A4 0x01003F07 0x01000800
# Register : LPD_SWITCH_CTRL @ 0XFF5E00A8</p>
# Clock active signal. Switch to 0 to disable the clock
# PSU_CRL_APB_LPD_SWITCH_CTRL_CLKACT 0x1
# 6 bit divider
# PSU_CRL_APB_LPD_SWITCH_CTRL_DIVISOR0 0x3
# 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af
# ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
# usually an issue, but designers must be aware.)
# PSU_CRL_APB_LPD_SWITCH_CTRL_SRCSEL 0x2
# This register controls this reference clock
#(OFFSET, MASK, VALUE) (0XFF5E00A8, 0x01003F07U ,0x01000302U) */
mask_write 0XFF5E00A8 0x01003F07 0x01000302
# Register : LPD_LSBUS_CTRL @ 0XFF5E00AC</p>
# Clock active signal. Switch to 0 to disable the clock
# PSU_CRL_APB_LPD_LSBUS_CTRL_CLKACT 0x1
# 6 bit divider
# PSU_CRL_APB_LPD_LSBUS_CTRL_DIVISOR0 0xf
# 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af
# ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
# usually an issue, but designers must be aware.)
# PSU_CRL_APB_LPD_LSBUS_CTRL_SRCSEL 0x2
# This register controls this reference clock
#(OFFSET, MASK, VALUE) (0XFF5E00AC, 0x01003F07U ,0x01000F02U) */
mask_write 0XFF5E00AC 0x01003F07 0x01000F02
# Register : DBG_LPD_CTRL @ 0XFF5E00B0</p>
# Clock active signal. Switch to 0 to disable the clock
# PSU_CRL_APB_DBG_LPD_CTRL_CLKACT 0x1
# 6 bit divider
# PSU_CRL_APB_DBG_LPD_CTRL_DIVISOR0 0x6
# 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af
# ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
# usually an issue, but designers must be aware.)
# PSU_CRL_APB_DBG_LPD_CTRL_SRCSEL 0x2
# This register controls this reference clock
#(OFFSET, MASK, VALUE) (0XFF5E00B0, 0x01003F07U ,0x01000602U) */
mask_write 0XFF5E00B0 0x01003F07 0x01000602
# Register : ADMA_REF_CTRL @ 0XFF5E00B8</p>
# Clock active signal. Switch to 0 to disable the clock
# PSU_CRL_APB_ADMA_REF_CTRL_CLKACT 0x1
# 6 bit divider
# PSU_CRL_APB_ADMA_REF_CTRL_DIVISOR0 0x3
# 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af
# ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
# usually an issue, but designers must be aware.)
# PSU_CRL_APB_ADMA_REF_CTRL_SRCSEL 0x2
# This register controls this reference clock
#(OFFSET, MASK, VALUE) (0XFF5E00B8, 0x01003F07U ,0x01000302U) */
mask_write 0XFF5E00B8 0x01003F07 0x01000302
# Register : PL0_REF_CTRL @ 0XFF5E00C0</p>
# Clock active signal. Switch to 0 to disable the clock
# PSU_CRL_APB_PL0_REF_CTRL_CLKACT 0x1
# 6 bit divider
# PSU_CRL_APB_PL0_REF_CTRL_DIVISOR1 0x1
# 6 bit divider
# PSU_CRL_APB_PL0_REF_CTRL_DIVISOR0 0xf
# 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af
# ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
# usually an issue, but designers must be aware.)
# PSU_CRL_APB_PL0_REF_CTRL_SRCSEL 0x0
# This register controls this reference clock
#(OFFSET, MASK, VALUE) (0XFF5E00C0, 0x013F3F07U ,0x01010F00U) */
mask_write 0XFF5E00C0 0x013F3F07 0x01010F00
# Register : AMS_REF_CTRL @ 0XFF5E0108</p>
# 6 bit divider
# PSU_CRL_APB_AMS_REF_CTRL_DIVISOR1 0x1
# 6 bit divider
# PSU_CRL_APB_AMS_REF_CTRL_DIVISOR0 0x1d
# 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af
# ter 4 cycles of the old clock and 4 cycles of the new clock. This is not
# usually an issue, but designers must be aware.)
# PSU_CRL_APB_AMS_REF_CTRL_SRCSEL 0x2
# Clock active signal. Switch to 0 to disable the clock
# PSU_CRL_APB_AMS_REF_CTRL_CLKACT 0x1
# This register controls this reference clock
#(OFFSET, MASK, VALUE) (0XFF5E0108, 0x013F3F07U ,0x01011D02U) */
mask_write 0XFF5E0108 0x013F3F07 0x01011D02
# Register : DLL_REF_CTRL @ 0XFF5E0104</p>
# 000 = IOPLL; 001 = RPLL; (This signal may only be toggled after 4 cycles
# of the old clock and 4 cycles of the new clock. This is not usually an
# issue, but designers must be aware.)
# PSU_CRL_APB_DLL_REF_CTRL_SRCSEL 0
# This register controls this reference clock
#(OFFSET, MASK, VALUE) (0XFF5E0104, 0x00000007U ,0x00000000U) */
mask_write 0XFF5E0104 0x00000007 0x00000000
# Register : TIMESTAMP_REF_CTRL @ 0XFF5E0128</p>
# 6 bit divider
# PSU_CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0 0xf
# 1XX = pss_ref_clk; 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may
# only be toggled after 4 cycles of the old clock and 4 cycles of the new
# clock. This is not usually an issue, but designers must be aware.)
# PSU_CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL 0x0
# Clock active signal. Switch to 0 to disable the clock
# PSU_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT 0x1
# This register controls this reference clock
#(OFFSET, MASK, VALUE) (0XFF5E0128, 0x01003F07U ,0x01000F00U) */
mask_write 0XFF5E0128 0x01003F07 0x01000F00
# Register : DP_VIDEO_REF_CTRL @ 0XFD1A0070</p>
# 6 bit divider
# PSU_CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1 0x1
# 6 bit divider
# PSU_CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0 0x4
# 000 = VPLL; 010 = DPLL; 011 = RPLL_TO_FPD - might be using extra mux; (T
# his signal may only be toggled after 4 cycles of the old clock and 4 cyc
# les of the new clock. This is not usually an issue, but designers must b
# e aware.)
# PSU_CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL 0x0
# Clock active signal. Switch to 0 to disable the clock
# PSU_CRF_APB_DP_VIDEO_REF_CTRL_CLKACT 0x1
# This register controls this reference clock
#(OFFSET, MASK, VALUE) (0XFD1A0070, 0x013F3F07U ,0x01010400U) */
mask_write 0XFD1A0070 0x013F3F07 0x01010400
# Register : DP_AUDIO_REF_CTRL @ 0XFD1A0074</p>
# 6 bit divider
# PSU_CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1 0x1
# 6 bit divider