Arch file format for vpr

[at3e]

Hello,
Trying to figure out the correct arch file to be input to vpr, kindly help me with the following issue

/home/thoth/vtr-verilog-to-routing/vpr/vpr ./arch/4LUT_DSP/L1/k4_N8_topology-1.0sL1_22nm.xml /home/thoth/vtr-verilog-to-routing/vtr_flow/benchmarks/4LUT_DSP_vtr_benchmarks_blif/sha.pre-vpr.blif --pack --place --route --route_chan_width 60

Using up to 1 parallel worker(s)

Architecture file: ./arch/4LUT_DSP/L1/k4_N8_topology-1.0sL1_22nm.xml
Circuit name: sha.pre-vpr

# Loading Architecture Description
Warning 1: Model 'multiply' input port 'b' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 2: Model 'multiply' input port 'a' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 3: Model 'multiply' output port 'out' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output)
Warning 4: Model 'single_port_ram' input port 'data' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 5: Model 'single_port_ram' input port 'addr' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 6: Model 'single_port_ram' input port 'we' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 7: Model 'single_port_ram' output port 'out' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output)
Warning 8: Model 'dual_port_ram' input port 'data2' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 9: Model 'dual_port_ram' input port 'data1' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 10: Model 'dual_port_ram' input port 'addr2' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 11: Model 'dual_port_ram' input port 'addr1' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 12: Model 'dual_port_ram' input port 'we2' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 13: Model 'dual_port_ram' input port 'we1' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 14: Model 'dual_port_ram' output port 'out2' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output)
Warning 15: Model 'dual_port_ram' output port 'out1' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output)
# Loading Architecture Description took 0.00 seconds (max_rss 15.9 MiB, delta_rss +1.3 MiB)
Error 1: ./arch/4LUT_DSP/L1/k4_N8_topology-1.0sL1_22nm.xml:51 Unexpected attribute 'auto' found on node 'layout'.
The entire flow of VPR took 0.00 seconds (max_rss 15.9 MiB)

I updated the arch file using vtr-flow and this time,

PR was run with the following command-line:
/home/thoth/vtr-verilog-to-routing/vpr/vpr ./arch/4LUT_DSP/L1/k4_N8_topology-1.0sL1_22nm.xml /home/thoth/vtr-verilog-to-routing/vtr_flow/benchmarks/4LUT_DSP_vtr_benchmarks_blif/sha.pre-vpr.blif --pack --place --route --route_chan_width 60

Using up to 1 parallel worker(s)

Architecture file: ./arch/4LUT_DSP/L1/k4_N8_topology-1.0sL1_22nm.xml
Circuit name: sha.pre-vpr

# Loading Architecture Description
# Loading Architecture Description took 0.00 seconds (max_rss 16.1 MiB, delta_rss +1.4 MiB)
Error 1: ./arch/4LUT_DSP/L1/k4_N8_topology-1.0sL1_22nm.xml:171 Unexpected attribute 'FT' found on node 'wireconn'. Expected (possibly) one of: 'num_conns', 'from_type', 'to_type', 'from_switchpoint', 'to_switchpoint', 'from_order', 'to_order', or 'switch_override'.
The entire flow of VPR took 0.00 seconds (max_rss 16.1 MiB)