From de94085558f12bdac6f3135f92927192433cfbc0 Mon Sep 17 00:00:00 2001 From: Wayne Warthen Date: Fri, 24 Jan 2025 11:24:55 -0800 Subject: [PATCH] Minor Config File Cleanups --- Source/HBIOS/Config/RCZ180_nat_std.asm | 2 +- Source/HBIOS/Config/RCZ280_nat_std.asm | 3 +- Source/HBIOS/Config/RCZ280_zzrcc_std.asm | 2 +- Source/HBIOS/cfg_RCEZ80.asm | 432 ----------------------- 4 files changed, 3 insertions(+), 436 deletions(-) delete mode 100644 Source/HBIOS/cfg_RCEZ80.asm diff --git a/Source/HBIOS/Config/RCZ180_nat_std.asm b/Source/HBIOS/Config/RCZ180_nat_std.asm index 487609b4..fd34de40 100644 --- a/Source/HBIOS/Config/RCZ180_nat_std.asm +++ b/Source/HBIOS/Config/RCZ180_nat_std.asm @@ -74,7 +74,7 @@ VRCENABLE .SET FALSE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM) EFENABLE .SET FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM) ; FDENABLE .SET TRUE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM) -FDMODE .SET FDMODE_RCWDC ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]] +FDMODE .SET FDMODE_RCWDC ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC] ; IDEENABLE .SET TRUE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM) ; diff --git a/Source/HBIOS/Config/RCZ280_nat_std.asm b/Source/HBIOS/Config/RCZ280_nat_std.asm index c8e7473c..765435b1 100644 --- a/Source/HBIOS/Config/RCZ280_nat_std.asm +++ b/Source/HBIOS/Config/RCZ280_nat_std.asm @@ -61,7 +61,6 @@ FPSW_ENABLE .SET TRUE ; FP: ENABLES FRONT PANEL SWITCHES CRTACT .SET FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP VDAEMU_SERKBD .SET 0 ; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD ; -; UARTENABLE .SET TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM) Z2UENABLE .SET TRUE ; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM) ACIAENABLE .SET FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM) @@ -81,7 +80,7 @@ IDEENABLE .SET TRUE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM) PPIDEENABLE .SET TRUE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM) ; SDENABLE .SET FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) -SDCNT .SET 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT SC ONLY +SDCNT .SET 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY ; PRPENABLE .SET FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM) SN76489ENABLE .SET FALSE ; SN: ENABLE SN76489 SOUND DRIVER diff --git a/Source/HBIOS/Config/RCZ280_zzrcc_std.asm b/Source/HBIOS/Config/RCZ280_zzrcc_std.asm index a8103aba..58edbf2e 100644 --- a/Source/HBIOS/Config/RCZ280_zzrcc_std.asm +++ b/Source/HBIOS/Config/RCZ280_zzrcc_std.asm @@ -87,7 +87,6 @@ MDRAM .SET TRUE ; MD: ENABLE RAM DISK FDENABLE .SET TRUE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM) FDMODE .SET FDMODE_RCWDC ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC] ; -; IDEENABLE .SET TRUE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM) ; PPIDEENABLE .SET TRUE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM) @@ -99,3 +98,4 @@ PRPENABLE .SET FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM) SN76489ENABLE .SET FALSE ; SN: ENABLE SN76489 SOUND DRIVER AY38910ENABLE .SET FALSE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER AYMODE .SET AYMODE_RCZ80 ; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU] +AY_FORCE .SET FALSE ; AY: BYPASS AUTO-DETECT, FORCED PRESENT diff --git a/Source/HBIOS/cfg_RCEZ80.asm b/Source/HBIOS/cfg_RCEZ80.asm deleted file mode 100644 index d9ec4dfb..00000000 --- a/Source/HBIOS/cfg_RCEZ80.asm +++ /dev/null @@ -1,432 +0,0 @@ -; -;================================================================================================== -; ROMWBW PLATFORM CONFIGURATION DEFAULTS FOR PLATFORM: RCZE80 -;================================================================================================== -; -; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM -; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. INSTEAD, -; YOU SHOULD OVERRIDE SETTINGS YOU WANT USING A CONFIGURATION FILE IN -; THE CONFIG DIRECTORY UNDER THIS DIRECTORY. -; -; THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. IT IS MAINTAINED BY THE -; AUTHORS OF ROMWBW. TO OVERRIDE SETTINGS YOU SHOULD USE A -; CONFIGURATION FILE IN THE CONFIG DIRECTORY UNDER THIS DIRECTORY. -; -; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW: -; -; cfg_MASTER.asm - MASTER: CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS -; | -; +-> cfg_.asm - PLATFORM: DEFAULT SETTINGS FOR SPECIFIC PLATFORM -; | -; +-> Config/_std.asm - BUILD: SETTINGS FOR EACH OFFICIAL DIST BUILD -; | -; +-> Config/_.asm - USER: CUSTOM USER BUILD SETTINGS -; -; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW -; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE -; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY -; OVERRIDE THESE SETTINGS AS DESIRED. -; -; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT -; FILE (SEE #INCLUDE STATEMENT BELOW). THE TOP TWO FILES SHOULD NOT BE -; MODIFIED. TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THE -; DEFAULT BUILD SETTINGS (Config/_std.asm) OR PREFERABLY -; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT -; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm). -; -; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE -; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL BE INHERITING MOST -; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES. -; -; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE -; ".SET" TO OVERRIDE SETTINGS. THE ASSEMBLER WILL ERROR IF YOU ATTEMPT -; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU". -; -#DEFINE PLATFORM_NAME "RCBus", " [", CONFIG, "]" -#DEFINE DEFSERCFG SER_115200_8N1 | SER_RTS -; -#INCLUDE "cfg_MASTER.asm" -; -PLATFORM .SET PLT_RCEZ80 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80] -CPUFAM .SET CPU_EZ80 ; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80] -BIOS .SET BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA] -BATCOND .SET FALSE ; ENABLE LOW BATTERY WARNING MESSAGE -HBIOS_MUTEX .SET FALSE ; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD) -USELZSA2 .SET TRUE ; ENABLE FONT COMPRESSION -TICKFREQ .SET 50 ; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ) -; -BOOT_TIMEOUT .SET -1 ; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE -BOOT_DELAY .SET 0 ; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT -AUTOCON .SET TRUE ; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT -; -CPUSPDCAP .SET SPD_FIXED ; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO -CPUSPDDEF .SET SPD_HIGH ; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW -CPUOSC .SET 20000000 ; CPU OSC FREQ IN MHZ -INTMODE .SET 1 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280) -;;;DEFSERCFG .SET SER_115200_8N1 | SER_RTS ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM) -; -RAMSIZE .SET 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!) -ROMSIZE .SET 512 ; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!) -APP_BNKS .SET $FF ; BANKS TO RESERVE FOR APP USE ($FF FOR AUTO SIZING) -MEMMGR .SET MM_Z2 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON|EZ512] -MPGSEL_0 .SET $78 ; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY) -MPGSEL_1 .SET $79 ; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY) -MPGSEL_2 .SET $7A ; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY) -MPGSEL_3 .SET $7B ; Z2 MEM MGR BANK 3 PAGE SELECT REG (WRITE ONLY) -MPGENA .SET $7C ; Z2 MEM MGR PAGING ENABLE REGISTER (BIT 0, WRITE ONLY) -; -RTCIO .SET $C0 ; RTC LATCH REGISTER ADR -; -KIOENABLE .SET FALSE ; ENABLE ZILOG KIO SUPPORT -KIOBASE .SET $80 ; KIO BASE I/O ADDRESS -; -CTCENABLE .SET TRUE ; ENABLE ZILOG CTC SUPPORT -CTCDEBUG .SET FALSE ; ENABLE CTC DRIVER DEBUG OUTPUT -CTCBASE .SET $88 ; CTC BASE I/O ADDRESS -CTCTIMER .SET FALSE ; ENABLE CTC PERIODIC TIMER -CTCMODE .SET CTCMODE_TIM16 ; CTC MODE: CTCMODE_[NONE|CTR|TIM16|TIM256] -CTCPRE .SET 256 ; PRESCALE CONSTANT (1-256) -CTCPRECH .SET 2 ; PRESCALE CHANNEL (0-3) -CTCTIMCH .SET 3 ; TIMER CHANNEL (0-3) -CTCOSC .SET CPUOSC ; CTC CLOCK FREQUENCY -; -PCFENABLE .SET FALSE ; ENABLE PCF8584 I2C CONTROLLER -PCFBASE .SET $F0 ; PCF8584 BASE I/O ADDRESS -; -EIPCENABLE .SET FALSE ; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION -; -SKZENABLE .SET FALSE ; ENABLE SERGEY'S Z80-512K FEATURES -SKZDIV .SET DIV_1 ; UART CLK (CLK2) DIVIDER FOR Z80-512K -; -WDOGMODE .SET WDOG_NONE ; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ] -WDOGIO .SET $6E ; WATCHDOG REGISTER ADR -; -FPLED_ENABLE .SET FALSE ; FP: ENABLES FRONT PANEL LEDS -FPLED_IO .SET $00 ; FP: PORT ADDRESS FOR FP LEDS -FPLED_INV .SET FALSE ; FP: LED BITS ARE INVERTED -FPLED_DSKACT .SET TRUE ; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS -FPSW_ENABLE .SET FALSE ; FP: ENABLES FRONT PANEL SWITCHES -FPSW_IO .SET $00 ; FP: PORT ADDRESS FOR FP SWITCHES -FPSW_INV .SET FALSE ; FP: SWITCH BITS ARE INVERTED -; -DIAGLVL .SET DL_CRITICAL ; ERROR LEVEL REPORTING -; -LEDENABLE .SET FALSE ; ENABLES STATUS LED (SINGLE LED) -LEDMODE .SET LEDMODE_STD ; LEDMODE_[STD|SC|RTC|NABU] -LEDPORT .SET $0E ; STATUS LED PORT ADDRESS -LEDDISKIO .SET TRUE ; ENABLES DISK I/O ACTIVITY ON STATUS LED -; -DSKYENABLE .SET FALSE ; ENABLES DSKY FUNCTIONALITY -DSKYDSKACT .SET TRUE ; ENABLES DISK ACTIVITY ON DSKY DISPLAY -ICMENABLE .SET FALSE ; ENABLES ORIGINAL DSKY ICM DRIVER (7218) -ICMPPIBASE .SET $60 ; BASE I/O ADDRESS OF ICM PPI -PKDENABLE .SET FALSE ; ENABLES DSKY NG PKD DRIVER (8259) -PKDPPIBASE .SET $60 ; BASE I/O ADDRESS OF PKD PPI -PKDOSC .SET 3000000 ; OSCILLATOR FREQ FOR PKD (IN HZ) -H8PENABLE .SET FALSE ; ENABLES HEATH H8 FRONT PANEL -LCDENABLE .SET TRUE ; ENABLE LCD DISPLAY -LCDBASE .SET $DA ; BASE I/O ADDRESS OF LCD CONTROLLER -GM7303ENABLE .SET FALSE ; ENABLES THE GM7303 BOARD WITH 16X2 LCD -; -BOOTCON .SET 0 ; BOOT CONSOLE DEVICE -SECCON .SET $FF ; SECONDARY CONSOLE DEVICE -CRTACT .SET FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP -VDAEMU .SET EMUTYP_ANSI ; VDA EMULATION: EMUTYP_[TTY|ANSI] -VDAEMU_SERKBD .SET $FF ; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD -ANSITRACE .SET 1 ; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -PPKTRACE .SET 1 ; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -KBDTRACE .SET 1 ; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -PPKKBLOUT .SET KBD_US ; PPK KEYBOARD LANGUAGE: KBD_[US|DE] -KBDKBLOUT .SET KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE] -MKYKBLOUT .SET KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE] -; -DSRTCENABLE .SET FALSE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM) -DSRTCMODE .SET DSRTCMODE_STD ; DSRTC: OPERATING MODE: DSRTCMODE_[STD|MFPIC|K80W] -DSRTCCHG .SET FALSE ; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!) -; -DS1501RTCENABLE .SET FALSE ; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM) -DS1501RTC_BASE .SET $50 ; DS1501RTC: I/O BASE ADDRESS -; -BQRTCENABLE .SET FALSE ; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM) -BQRTC_BASE .SET $50 ; BQRTC: I/O BASE ADDRESS -; -INTRTCENABLE .SET FALSE ; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM) -; -RP5RTCENABLE .SET FALSE ; RP5C01 RTC BASED CLOCK (RP5RTC.ASM) -; -HTIMENABLE .SET FALSE ; ENABLE SIMH TIMER SUPPORT -SIMRTCENABLE .SET FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM) -; -DS7RTCENABLE .SET FALSE ; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM) -DS7RTCMODE .SET DS7RTCMODE_PCF ; DS7RTC: OPERATING MODE: DS7RTC_[PCF] -; -DS5RTCENABLE .SET FALSE ; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM) -; -SSERENABLE .SET FALSE ; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM) -SSERCFG .SET SER_9600_8N1 ; SSER: SERIAL LINE CONFIG -SSERSTATUS .SET $FF ; SSER: STATUS PORT -SSERDATA .SET $FF ; SSER: DATA PORT -SSERIRDY .SET %00000001 ; SSER: INPUT READY BIT MASK -SSERIINV .SET FALSE ; SSER: INPUT READY BIT INVERTED -SSERORDY .SET %00000010 ; SSER: OUTPUT READY BIT MASK -SSEROINV .SET FALSE ; SSER: OUTPUT READY BIT INVERTED -; -DUARTENABLE .SET FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM) -DUARTCNT .SET 1 ; DUART: NUMBER OF CHIPS TO DETECT (1-2) -DUART0BASE .SET $A0 ; DUART 0: BASE ADDRESS OF CHIP -DUART0ACFG .SET DEFSERCFG ; DUART 0A: SERIAL LINE CONFIG -DUART0BCFG .SET DEFSERCFG ; DUART 0B: SERIAL LINE CONFIG -DUART1BASE .SET $40 ; DUART 1: BASE ADDRESS OF CHIP -DUART1ACFG .SET DEFSERCFG ; DUART 1A: SERIAL LINE CONFIG -DUART1BCFG .SET DEFSERCFG ; DUART 1B: SERIAL LINE CONFIG -; -UARTENABLE .SET FALSE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM) -UARTCNT .SET 4 ; UART: NUMBER OF CHIPS TO DETECT (1-8) -UARTOSC .SET 1843200 ; UART: OSC FREQUENCY IN MHZ -UARTINTS .SET FALSE ; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3 -UART4UART .SET FALSE ; UART: SUPPORT 4UART ECB BOARD -UART4UARTBASE .SET $C0 ; UART: BASE IO ADDRESS OF 4UART ECB BOARD -UART0BASE .SET $80 ; UART 0: REGISTERS BASE ADR -UART0CFG .SET DEFSERCFG ; UART 0: SERIAL LINE CONFIG -UART1BASE .SET $88 ; UART 1: REGISTERS BASE ADR -UART1CFG .SET DEFSERCFG ; UART 1: SERIAL LINE CONFIG -UART2BASE .SET $A0 ; UART 2: REGISTERS BASE ADR -UART2CFG .SET DEFSERCFG ; UART 2: SERIAL LINE CONFIG -UART3BASE .SET $A8 ; UART 3: REGISTERS BASE ADR -UART3CFG .SET DEFSERCFG ; UART 3: SERIAL LINE CONFIG -UART4BASE .SET $FF ; UART 4: REGISTERS BASE ADR -UART4CFG .SET DEFSERCFG ; UART 4: SERIAL LINE CONFIG -UART5BASE .SET $FF ; UART 5: REGISTERS BASE ADR -UART5CFG .SET DEFSERCFG ; UART 5: SERIAL LINE CONFIG -UART6BASE .SET $FF ; UART 6: REGISTERS BASE ADR -UART6CFG .SET DEFSERCFG ; UART 6: SERIAL LINE CONFIG -UART7BASE .SET $FF ; UART 7: REGISTERS BASE ADR -UART7CFG .SET DEFSERCFG ; UART 7: SERIAL LINE CONFIG -; -ASCIENABLE .SET FALSE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM) -; -Z2UENABLE .SET FALSE ; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM) -; -ACIAENABLE .SET FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM) -ACIADEBUG .SET FALSE ; ACIA: ENABLE DEBUG OUTPUT -ACIACNT .SET 1 ; ACIA: NUMBER OF CHIPS TO DETECT (1-2) -ACIA0BASE .SET $80 ; ACIA 0: REGISTERS BASE ADR -ACIA0CLK .SET CPUOSC ; ACIA 0: OSC FREQ IN HZ -ACIA0DIV .SET 1 ; ACIA 0: SERIAL CLOCK DIVIDER -ACIA0CFG .SET DEFSERCFG ; ACIA 0: SERIAL LINE CONFIG (SEE STD.ASM) -ACIA1BASE .SET $40 ; ACIA 1: REGISTERS BASE ADR -ACIA1CLK .SET CPUOSC ; ACIA 1: OSC FREQ IN HZ -ACIA1DIV .SET 1 ; ACIA 1: SERIAL CLOCK DIVIDER -ACIA1CFG .SET DEFSERCFG ; ACIA 1: SERIAL LINE CONFIG (SEE STD.ASM) -; -SIOENABLE .SET FALSE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM) -SIODEBUG .SET FALSE ; SIO: ENABLE DEBUG OUTPUT -SIOBOOT .SET 0 ; SIO: REBOOT ON RCV CHAR (0=DISABLED) -SIOCNT .SET 2 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP -SIOINTS .SET TRUE ; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3 -SIO0MODE .SET SIOMODE_RC ; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R] -SIO0BASE .SET $80 ; SIO 0: REGISTERS BASE ADR -SIO0ACLK .SET CPUOSC ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 -SIO0ACFG .SET DEFSERCFG ; SIO 0A: SERIAL LINE CONFIG -SIO0ACTCC .SET -1 ; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE -SIO0BCLK .SET CPUOSC ; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 -SIO0BCFG .SET DEFSERCFG ; SIO 0B: SERIAL LINE CONFIG -SIO0BCTCC .SET -1 ; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE -SIO1MODE .SET SIOMODE_RC ; SIO 1: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R] -SIO1BASE .SET $84 ; SIO 1: REGISTERS BASE ADR -SIO1ACLK .SET CPUOSC ; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 -SIO1ACFG .SET DEFSERCFG ; SIO 1A: SERIAL LINE CONFIG -SIO1ACTCC .SET -1 ; SIO 1A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE -SIO1BCLK .SET CPUOSC ; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 -SIO1BCFG .SET DEFSERCFG ; SIO 1B: SERIAL LINE CONFIG -SIO1BCTCC .SET -1 ; SIO 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE -; -XIOCFG .SET DEFSERCFG ; XIO: SERIAL LINE CONFIG -; -VDUENABLE .SET FALSE ; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM) -CVDUENABLE .SET FALSE ; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM) -GDCENABLE .SET FALSE ; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM) -TMSENABLE .SET FALSE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM) -TMSMODE .SET TMSMODE_MSX ; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU] -TMS80COLS .SET FALSE ; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958 -TMSTIMENABLE .SET FALSE ; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1) -VGAENABLE .SET FALSE ; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM) -VRCENABLE .SET FALSE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM) -SCONENABLE .SET FALSE ; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM) -EFENABLE .SET FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM) -FVENABLE .SET FALSE ; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM) -; -MDENABLE .SET TRUE ; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM) -MDROM .SET TRUE ; MD: ENABLE ROM DISK -MDRAM .SET TRUE ; MD: ENABLE RAM DISK -MDTRACE .SET 1 ; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -MDFFENABLE .SET FALSE ; MD: ENABLE FLASH FILE SYSTEM -; -FDENABLE .SET FALSE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM) -FDMODE .SET FDMODE_RCWDC ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC] -FDCNT .SET 2 ; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2) -FDTRACE .SET 1 ; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL) -FDMAUTO .SET TRUE ; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS -FD0TYPE .SET FDT_3HD ; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8] -FD1TYPE .SET FDT_3HD ; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8] -; -RFENABLE .SET FALSE ; RF: ENABLE RAM FLOPPY DRIVER -; -IDEENABLE .SET FALSE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM) -IDETRACE .SET 1 ; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -IDECNT .SET 1 ; IDE: NUMBER OF IDE INTERFACES TO DETECT (1-3), 2 DRIVES EACH -IDE0MODE .SET IDEMODE_RC ; IDE 0: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC|GIDE] -IDE0BASE .SET $10 ; IDE 0: IO BASE ADDRESS -IDE0DATLO .SET $00 ; IDE 0: DATA LO PORT FOR 16-BIT I/O -IDE0DATHI .SET $00 ; IDE 0: DATA HI PORT FOR 16-BIT I/O -IDE0A8BIT .SET TRUE ; IDE 0A (MASTER): 8 BIT XFER -IDE0B8BIT .SET TRUE ; IDE 0B (MASTER): 8 BIT XFER -IDE1MODE .SET IDEMODE_NONE ; IDE 1: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC|GIDE] -IDE1BASE .SET $00 ; IDE 1: IO BASE ADDRESS -IDE1DATLO .SET $00 ; IDE 1: DATA LO PORT FOR 16-BIT I/O -IDE1DATHI .SET $00 ; IDE 1: DATA HI PORT FOR 16-BIT I/O -IDE1A8BIT .SET TRUE ; IDE 1A (MASTER): 8 BIT XFER -IDE1B8BIT .SET TRUE ; IDE 1B (MASTER): 8 BIT XFER -IDE2MODE .SET IDEMODE_NONE ; IDE 2: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC|GIDE] -IDE2BASE .SET $00 ; IDE 2: IO BASE ADDRESS -IDE2DATLO .SET $00 ; IDE 2: DATA LO PORT FOR 16-BIT I/O -IDE2DATHI .SET $00 ; IDE 2: DATA HI PORT FOR 16-BIT I/O -IDE2A8BIT .SET TRUE ; IDE 2A (MASTER): 8 BIT XFER -IDE2B8BIT .SET TRUE ; IDE 2B (MASTER): 8 BIT XFER -; -PPIDEENABLE .SET FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM) -PPIDETRACE .SET 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -PPIDECNT .SET 1 ; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP -PPIDE0BASE .SET $20 ; PPIDE 0: PPI REGISTERS BASE ADR -PPIDE0A8BIT .SET FALSE ; PPIDE 0A (MASTER): 8 BIT XFER -PPIDE0B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER -PPIDE1BASE .SET $00 ; PPIDE 1: PPI REGISTERS BASE ADR -PPIDE1A8BIT .SET FALSE ; PPIDE 1A (MASTER): 8 BIT XFER -PPIDE1B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER -PPIDE2BASE .SET $00 ; PPIDE 2: PPI REGISTERS BASE ADR -PPIDE2A8BIT .SET FALSE ; PPIDE 2A (MASTER): 8 BIT XFER -PPIDE2B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER -; -SDENABLE .SET FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) -SDMODE .SET SDMODE_MT ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80|GM|EZ512|K80W] -SDPPIBASE .SET $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE -SDCNT .SET 2 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY -SDTRACE .SET 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -SDCSIOFAST .SET FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE -SDMTSWAP .SET FALSE ; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011 -; -CHENABLE .SET TRUE ; CH: ENABLE CH375/376 USB SUPPORT -CHTRACE .SET 1 ; CH: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -CHUSBTRACE .SET 1 ; CHUSB: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -CHSDTRACE .SET 1 ; CHSD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -CHCNT .SET 2 ; CH: NUMBER OF BOARDS TO DETECT (1-2) -CH0BASE .SET $3E ; CH 0: BASE I/O ADDRESS -CH0USBENABLE .SET TRUE ; CH 0: ENABLE USB DISK -CH0SDENABLE .SET FALSE ; CH 0: ENABLE SD DISK -CH1BASE .SET $3C ; CH 1: BASE I/O ADDRESS -CH1USBENABLE .SET TRUE ; CH 1: ENABLE USB DISK -CH1SDENABLE .SET FALSE ; CH 1: ENABLE SD DISK -; -PRPENABLE .SET FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM) -PRPSDENABLE .SET TRUE ; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT -PRPSDTRACE .SET 1 ; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -PRPCONENABLE .SET TRUE ; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT -; -PPPENABLE .SET FALSE ; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM) -; -ESPENABLE .SET FALSE ; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM) -; -HDSKENABLE .SET FALSE ; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM) -; -PIOENABLE .SET FALSE ; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM) -PIOCNT .SET 2 ; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP -PIO0BASE .SET $B8 ; PIO 0: REGISTERS BASE ADR -PIO1BASE .SET $BC ; PIO 1: REGISTERS BASE ADR -; -LPTENABLE .SET FALSE ; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM) -LPTMODE .SET LPTMODE_MG014 ; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014] -LPTCNT .SET 1 ; LPT: NUMBER OF CHIPS TO DETECT (1-2) -LPTTRACE .SET 1 ; LPT: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -LPT0BASE .SET $0C ; LPT 0: REGISTERS BASE ADR -LPT1BASE .SET $00 ; LPT 1: REGISTERS BASE ADR -; -PPAENABLE .SET FALSE ; PPA: ENABLE PPA DISK DRIVER (PPA.ASM) -PPACNT .SET 1 ; PPA: NUMBER OF PPA DEVICES (1-2) -PPATRACE .SET 1 ; PPA: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -PPAMODE .SET PPAMODE_MG014 ; PPA: DRIVER MODE: PPAMODE_[NONE|SPP|MG014] -PPA0BASE .SET LPT0BASE ; PPA 0: BASE I/O ADDRESS OF PPI FOR PPA -PPA1BASE .SET LPT1BASE ; PPA 1: BASE I/O ADDRESS OF PPI FOR PPA -; -IMMENABLE .SET FALSE ; IMM: ENABLE IMM DISK DRIVER (IMM.ASM) -IMMCNT .SET 1 ; IMM: NUMBER OF IMM DEVICES (1-2) -IMMTRACE .SET 1 ; IMM: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -IMMMODE .SET IMMMODE_MG014 ; IMM: DRIVER MODE: IMMMODE_[NONE|SPP|MG014] -IMM0BASE .SET LPT0BASE ; IMM 0: BASE I/O ADDRESS OF PPI FOR IMM -IMM1BASE .SET LPT1BASE ; IMM 1: BASE I/O ADDRESS OF PPI FOR IMM -; -SYQENABLE .SET FALSE ; SYQ: ENABLE IMM DISK DRIVER (SYQ.ASM) -SYQCNT .SET 1 ; SYQ: NUMBER OF SYQ DEVICES (1-2) -SYQTRACE .SET 1 ; SYQ: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -SYQMODE .SET IMMMODE_MG014 ; SYQ: DRIVER MODE: SYQMODE_[NONE|SPP|MG014] -SYQ0BASE .SET LPT0BASE ; SYQ 0: BASE I/O ADDRESS OF PPI FOR SYQ -SYQ1BASE .SET LPT1BASE ; SYQ 1: BASE I/O ADDRESS OF PPI FOR SYQ -; -PIO_4P .SET FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD -PIO_ZP .SET FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM) -PIO_SBC .SET FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP -; -UFENABLE .SET FALSE ; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM) -; -SN76489ENABLE .SET FALSE ; SN: ENABLE SN76489 SOUND DRIVER -AUDIOTRACE .SET FALSE ; ENABLE TRACING TO CONSOLE OF SOUND DRIVER -SN7CLK .SET CPUOSC/4 ; SN: PSG CLOCK FREQ, ASSUME MSX STD -SNMODE .SET SNMODE_RC ; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM|DUO] -; -AY38910ENABLE .SET FALSE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER -AY_CLK .SET CPUOSC/4 ; AY: PSG CLOCK FREQ, ASSUME MSX STD -AYMODE .SET AYMODE_RCZ80 ; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU] -; -SPKENABLE .SET FALSE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM) -AY_FORCE .SET FALSE ; AY: BYPASS AUTO-DETECT, FORCED PRESENT -; -DMAENABLE .SET FALSE ; DMA: ENABLE DMA DRIVER (DMA.ASM) -DMABASE .SET $E0 ; DMA: DMA BASE ADDRESS -DMAMODE .SET DMAMODE_RC ; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO) -; -YM2612ENABLE .SET FALSE ; YM2612: ENABLE YM2612 DRIVER -VGMBASE .SET $C0 ; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC) -; -; EZ80 SETTINGS -; -EZ80TMR_NONE .SET 0 ; DO NOT USE ON-BOARD TIMER TO GENERATE TICKS -EZ80TMR_INT .SET 1 ; MARSHALL TIMER TICK INTERRUPTS FROM EZ80 TO HBIOS -EZ80TMR_FIRM .SET 2 ; DELEGATE SYS TIMER HBIOS CALL TO EZ80 FIRMWARE (TIMER TICK INTS DISABLED) -; -EZ80UARTENABLE .SET TRUE ; EZ80 UART: ENABLE EZ80 UART0 DRIVER (EZ80UART.ASM) -EZ80RTCENABLE .SET TRUE ; EZ80 ON CHIP RTC -EZ80TIMER .SET EZ80TMR_FIRM ; EZ80: TIMER TICK MODEL: EZ80TMR_[INT|FIRM] -EZ80IOBASE .SET $FF ; EZ80 I/O BASE ADDRESS FOR EXTERNAL IO -; -; BUS TIMING FOR PAGED MEMORY ACCESS (CS3) -EZ80_MEM_CYCLES .SET 3 ; MEMORY BUS CYCLES (1-15) TO APPLY, IF EZ80_WSMD_TYP = EZ80WSMD_CYCLES -EZ80_MEM_MIN_NS .SET 100 ; CALCULATE AT BOOT TIME THE REQUIRED W/S OR B/C, IF EZ80_WSMD_TYP = EZ80WSMD_CALC -EZ80_MEM_WS .SET 5 ; MEMORY WAIT STATES (0-7) TO APPLY, IF EZ80_WSMD_TYP = EZ80WSMD_WAIT -EZ80_MEM_MIN_WS .SET 0 ; MINIMUM WAIT STATES TO APPLY, IF EZ80_WSMD_TYP = EZ80WSMD_CALC -; -; BUS TIMING FOR EXTERNAL I/O ACCESS (CS2) -EZ80_IO_CYCLES .SET 4 ; IO BUS CYCLES (1-15) TO APPLY, IF EZ80_WSMD_TYP = EZ80WSMD_CYCLES -EZ80_IO_WS .SET 7 ; IO WAIT STATES (0-7) TO APPLY, IF EZ80_WSMD_TYP = EZ80WSMD_WAIT -EZ80_IO_MIN_NS .SET 250 ; CALCULATE AT BOOT TIME THE REQUIRED W/S OR B/C, IF EZ80_WSMD_TYP = EZ80WSMD_CALC - -; THE MINMUM W/S SHOULD BE AT LEAST 1 GREATER THAN THE HOLD TRIGGER COUNT PROGRAMMED WITHIN THE PLD OF THE -; EZ80 INTERFACE MODULE. SEE THE EZ80-CPU.PLD FILE WITHIN THE EZ80 FIRMWARE CODE BASE -EZ80_IO_MIN_WS .SET 7 ; MINIMUM WAIT STATES TO APPLY, IF EZ80_WSMD_TYP = EZ80WSMD_CALC -; -; APPLY CYCLES, W/S OR CALCULATE CYCLES BASED ON DESIRED PERIOD -EZ80_WSMD_TYP .SET EZ80WSMD_CALC ; BUS WAIT STATE CONFIG: EZ80WSMD_[CALC|CYCLES|WAIT] -; -; BUS TIMING FOR ON CHIP ROM -; -EZ80_FLSH_WS .SET 1 ; WAIT STATES FOR ON CHIP FLASH (0-7) -EZ80_FLSH_MIN_NS .SET 60 ; MINIMUM WAIT STATES TO APPLY TO ON-CHIP FLASH, IF EZ80_WSMD_TYP = EZ80WSMD_CALC -EZ80_FWSMD_TYP .SET EZ80WSMD_CALC ; WAIT STATE TYPE: EZ80RMMD_[CALC|WAIT] (CYCLES NOT ALLOWED)