-
Notifications
You must be signed in to change notification settings - Fork 0
/
Copy pathid.v
347 lines (326 loc) · 13.7 KB
/
id.v
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
/*
Copyright 2019 Blue Liang, [email protected]
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
`include "../header/defines.vh"
// 译码模块
// 纯组合逻辑电路
module id(
input wire rst,
// from if_id
input wire[`InstBus] inst_i, // 指令内容
input wire[`InstAddrBus] inst_addr_i, // 指令地址
input wire prdt_taken_i,
// from regs
input wire[`RegBus] reg1_rdata_i, // 通用寄存器1输入数据
input wire[`RegBus] reg2_rdata_i, // 通用寄存器2输入数据
// from csr reg
input wire[`RegBus] csr_rdata_i, // CSR寄存器输入数据
// from ex
input wire ex_jump_flag_i, // 跳转标志
// to regs
output reg[`RegAddrBus] reg1_raddr_o, // 读通用寄存器1地址
output reg[`RegAddrBus] reg2_raddr_o, // 读通用寄存器2地址
// to csr reg
output reg[`MemAddrBus] csr_raddr_o, // 读CSR寄存器地址
// to ex
output wire prdt_taken_o,
output reg[`MemAddrBus] op1_o,
output reg[`MemAddrBus] op2_o,
output reg[`MemAddrBus] op1_jump_o,
output reg[`MemAddrBus] op2_jump_o,
output reg[`InstBus] inst_o, // 指令内容
output reg[`InstAddrBus] inst_addr_o, // 指令地址
output reg[`RegBus] reg1_rdata_o, // 通用寄存器1数据
output reg[`RegBus] reg2_rdata_o, // 通用寄存器2数据
output reg reg_we_o, // 写通用寄存器标志
output reg[`RegAddrBus] reg_waddr_o, // 写通用寄存器地址
output reg csr_we_o, // 写CSR寄存器标志
output reg[`RegBus] csr_rdata_o, // CSR寄存器数据
output reg[`MemAddrBus] csr_waddr_o // 写CSR寄存器地址
);
wire[6:0] opcode = inst_i[6:0];
wire[2:0] funct3 = inst_i[14:12];
wire[6:0] funct7 = inst_i[31:25];
wire[4:0] rd = inst_i[11:7];
wire[4:0] rs1 = inst_i[19:15];
wire[4:0] rs2 = inst_i[24:20];
wire[11:0] imm = inst_i[31:20];
assign prdt_taken_o = prdt_taken_i;
always @ (*) begin
inst_o = inst_i;
inst_addr_o = inst_addr_i;
reg1_rdata_o = reg1_rdata_i;
reg2_rdata_o = reg2_rdata_i;
csr_rdata_o = csr_rdata_i;
csr_raddr_o = `ZeroWord;
csr_waddr_o = `ZeroWord;
csr_we_o = `WriteDisable;
op1_o = `ZeroWord;
op2_o = `ZeroWord;
op1_jump_o = `ZeroWord;
op2_jump_o = `ZeroWord;
case (opcode)
`INST_TYPE_EXT: begin
case (funct3)
`INST_SID: begin
reg_we_o = `WriteDisable;
reg_waddr_o = rd;
reg1_raddr_o = rs1;
reg2_raddr_o = `ZeroReg;
op1_o = 32'h30000000;
op2_o = `ZeroReg;
end
`INST_RT: begin
reg_we_o = `WriteEnable;
reg_waddr_o = rd;
reg1_raddr_o = rs1;
reg2_raddr_o = `ZeroReg;
op1_o = 32'h70030000;
op2_o = `ZeroReg;
end
`INST_IF: begin
reg_we_o = `WriteEnable;
reg_waddr_o = rd;
reg1_raddr_o = rs1;
reg2_raddr_o = 5'd31;
op1_o = reg1_rdata_i;
if (imm == 12'b0) begin
op2_o = reg2_rdata_i;
end
else begin
op2_o = {{20{inst_i[31]}}, inst_i[31:20]};
end
end
default: begin
reg_we_o = `WriteDisable;
reg_waddr_o = `ZeroReg;
reg1_raddr_o = `ZeroReg;
reg2_raddr_o = `ZeroReg;
end
endcase
end
`INST_TYPE_I: begin
case (funct3)
`INST_ADDI, `INST_SLTI, `INST_SLTIU, `INST_XORI, `INST_ORI, `INST_ANDI, `INST_SLLI, `INST_SRI: begin
reg_we_o = `WriteEnable;
reg_waddr_o = rd;
reg1_raddr_o = rs1;
reg2_raddr_o = `ZeroReg;
op1_o = reg1_rdata_i;
op2_o = {{20{inst_i[31]}}, inst_i[31:20]};
end
default: begin
reg_we_o = `WriteDisable;
reg_waddr_o = `ZeroReg;
reg1_raddr_o = `ZeroReg;
reg2_raddr_o = `ZeroReg;
end
endcase
end
`INST_TYPE_R_M: begin
if ((funct7 == 7'b0000000) || (funct7 == 7'b0100000)) begin
case (funct3)
`INST_ADD_SUB, `INST_SLL, `INST_SLT, `INST_SLTU, `INST_XOR, `INST_SR, `INST_OR, `INST_AND: begin
reg_we_o = `WriteEnable;
reg_waddr_o = rd;
reg1_raddr_o = rs1;
reg2_raddr_o = rs2;
op1_o = reg1_rdata_i;
op2_o = reg2_rdata_i;
end
default: begin
reg_we_o = `WriteDisable;
reg_waddr_o = `ZeroReg;
reg1_raddr_o = `ZeroReg;
reg2_raddr_o = `ZeroReg;
end
endcase
end else if (funct7 == 7'b0000001) begin
case (funct3)
`INST_MUL, `INST_MULHU, `INST_MULH, `INST_MULHSU: begin
reg_we_o = `WriteEnable;
reg_waddr_o = rd;
reg1_raddr_o = rs1;
reg2_raddr_o = rs2;
op1_o = reg1_rdata_i;
op2_o = reg2_rdata_i;
end
`INST_DIV, `INST_DIVU, `INST_REM, `INST_REMU: begin
reg_we_o = `WriteDisable;
reg_waddr_o = rd;
reg1_raddr_o = rs1;
reg2_raddr_o = rs2;
op1_o = reg1_rdata_i;
op2_o = reg2_rdata_i;
op1_jump_o = inst_addr_i;
op2_jump_o = 32'h4;
end
default: begin
reg_we_o = `WriteDisable;
reg_waddr_o = `ZeroReg;
reg1_raddr_o = `ZeroReg;
reg2_raddr_o = `ZeroReg;
end
endcase
end else begin
reg_we_o = `WriteDisable;
reg_waddr_o = `ZeroReg;
reg1_raddr_o = `ZeroReg;
reg2_raddr_o = `ZeroReg;
end
end
`INST_TYPE_L: begin
case (funct3)
`INST_LB, `INST_LH, `INST_LW, `INST_LBU, `INST_LHU: begin
reg1_raddr_o = rs1;
reg2_raddr_o = `ZeroReg;
reg_we_o = `WriteEnable;
reg_waddr_o = rd;
op1_o = reg1_rdata_i;
op2_o = {{20{inst_i[31]}}, inst_i[31:20]};
end
default: begin
reg1_raddr_o = `ZeroReg;
reg2_raddr_o = `ZeroReg;
reg_we_o = `WriteDisable;
reg_waddr_o = `ZeroReg;
end
endcase
end
`INST_TYPE_S: begin
case (funct3)
`INST_SB, `INST_SW, `INST_SH: begin
reg1_raddr_o = rs1;
reg2_raddr_o = rs2;
reg_we_o = `WriteDisable;
reg_waddr_o = `ZeroReg;
op1_o = reg1_rdata_i;
op2_o = {{20{inst_i[31]}}, inst_i[31:25], inst_i[11:7]};
end
default: begin
reg1_raddr_o = `ZeroReg;
reg2_raddr_o = `ZeroReg;
reg_we_o = `WriteDisable;
reg_waddr_o = `ZeroReg;
end
endcase
end
`INST_TYPE_B: begin
case (funct3)
`INST_BEQ, `INST_BNE, `INST_BLT, `INST_BGE, `INST_BLTU, `INST_BGEU: begin
reg1_raddr_o = rs1;
reg2_raddr_o = rs2;
reg_we_o = `WriteDisable;
reg_waddr_o = `ZeroReg;
op1_o = reg1_rdata_i;
op2_o = reg2_rdata_i;
op1_jump_o = inst_addr_i;
op2_jump_o = inst_i[31] ? 32'h4 : {{20{inst_i[31]}}, inst_i[7], inst_i[30:25], inst_i[11:8], 1'b0};
end
default: begin
reg1_raddr_o = `ZeroReg;
reg2_raddr_o = `ZeroReg;
reg_we_o = `WriteDisable;
reg_waddr_o = `ZeroReg;
end
endcase
end
`INST_JAL: begin
reg_we_o = `WriteEnable;
reg_waddr_o = rd;
reg1_raddr_o = `ZeroReg;
reg2_raddr_o = `ZeroReg;
op1_o = inst_addr_i;
op2_o = 32'h4;
op1_jump_o = `ZeroWord;
op2_jump_o = `ZeroWord;
end
`INST_JALR: begin
reg_we_o = `WriteEnable;
reg1_raddr_o = rs1;
reg2_raddr_o = `ZeroReg;
reg_waddr_o = rd;
op1_o = inst_addr_i;
op2_o = 32'h4;
op1_jump_o = reg1_rdata_i;
op2_jump_o = {{20{inst_i[31]}}, inst_i[31:20]};
end
`INST_LUI: begin
reg_we_o = `WriteEnable;
reg_waddr_o = rd;
reg1_raddr_o = `ZeroReg;
reg2_raddr_o = `ZeroReg;
op1_o = {inst_i[31:12], 12'b0};
op2_o = `ZeroWord;
end
`INST_AUIPC: begin
reg_we_o = `WriteEnable;
reg_waddr_o = rd;
reg1_raddr_o = `ZeroReg;
reg2_raddr_o = `ZeroReg;
op1_o = inst_addr_i;
op2_o = {inst_i[31:12], 12'b0};
end
`INST_NOP_OP: begin
reg_we_o = `WriteDisable;
reg_waddr_o = `ZeroReg;
reg1_raddr_o = `ZeroReg;
reg2_raddr_o = `ZeroReg;
end
`INST_FENCE: begin
reg_we_o = `WriteDisable;
reg_waddr_o = `ZeroReg;
reg1_raddr_o = `ZeroReg;
reg2_raddr_o = `ZeroReg;
op1_jump_o = inst_addr_i;
op2_jump_o = 32'h4;
end
`INST_CSR: begin
reg_we_o = `WriteDisable;
reg_waddr_o = `ZeroReg;
reg1_raddr_o = `ZeroReg;
reg2_raddr_o = `ZeroReg;
csr_raddr_o = {20'h0, inst_i[31:20]};
csr_waddr_o = {20'h0, inst_i[31:20]};
case (funct3)
`INST_CSRRW, `INST_CSRRS, `INST_CSRRC: begin
reg1_raddr_o = rs1;
reg2_raddr_o = `ZeroReg;
reg_we_o = `WriteEnable;
reg_waddr_o = rd;
csr_we_o = `WriteEnable;
end
`INST_CSRRWI, `INST_CSRRSI, `INST_CSRRCI: begin
reg1_raddr_o = `ZeroReg;
reg2_raddr_o = `ZeroReg;
reg_we_o = `WriteEnable;
reg_waddr_o = rd;
csr_we_o = `WriteEnable;
end
default: begin
reg_we_o = `WriteDisable;
reg_waddr_o = `ZeroReg;
reg1_raddr_o = `ZeroReg;
reg2_raddr_o = `ZeroReg;
csr_we_o = `WriteDisable;
end
endcase
end
default: begin
reg_we_o = `WriteDisable;
reg_waddr_o = `ZeroReg;
reg1_raddr_o = `ZeroReg;
reg2_raddr_o = `ZeroReg;
end
endcase
end
endmodule