A simple SoC Based on Cortex-m0.
Install Verilator. Install arm-none-elf-gcc(if used) or
sudo apt install gcc-arm-none-eabi
You can also use keil to compile C source.
Follow these steps to build the simulation environment.
cd simulation
make sim
make image.hex # GNU gcc only
./sim_main -h
For more detail, read the source code please.
| Address Range | Description |
|---|---|
| 0X00000000 .. 0X0000FFFF | RAMCODE |
| 0X20000000 .. 0X2000FFFF | RAMDATA |
| 0X40000010 .. 0X4000001B | UART |
| 0X40000020 .. 0X4000002B | SPI |
| 0X40010000 .. 0X4001FFFF | VGA |
This Verilog file contains the following Verilog modules:
| File | Description |
|---|---|
XC-SoC.xpr |
Vivado Project |
ebaz4205.xdc |
Constraints File for EBAZ4205 Board |
The IP core clk_wiz is not included currently.
RTL Source, core_m0 included.
| File | Description |
|---|---|
cortexm0ds_logic.v |
Cortex-m0 Core |
XC_SoC.v |
Top File of The Project |
…… |
…… |
Source file for simulation. Current simulation is finished by verilator. VCS(or more) will be supported soon.
| File/Folder | Description |
|---|---|
makefile |
Makefile for Simulation |
src_verilator |
Folder of CPP Source for Simulation |
verilator.vc |
Simulation Script for Verilator |
Software source for XC-SoC.
| File/Folder | Description |
|---|---|
gcc |
Startup File and Makefile Based on GNU GCC |
keil |
Startup File and Keil Project |
main.c |
main.c |
XC-SoC.h |
Core Config for XC-SoC |
include |
M0 Core Headfile |
uart_api.h/c |
API for UART |
spi_api.h/c |
API for SPI |
\^_^
src_verilator/sim_main.cpp:1:10: fatal error: verilated.h: No such file or directory
Check whether verilator is installed correctly and make clean.
- IIC (Waiting for board T_T)
- FM (Waiting for board T_T)