diff --git a/src/Convert/AlwaysKW.hs b/src/Convert/AlwaysKW.hs
index d70aa9eb..a88138ea 100644
--- a/src/Convert/AlwaysKW.hs
+++ b/src/Convert/AlwaysKW.hs
@@ -12,9 +12,11 @@
 
 module Convert.AlwaysKW (convert) where
 
+import Control.Monad (when, zipWithM, (>=>))
 import Control.Monad.State.Strict
 import Control.Monad.Writer.Strict
 import Data.Maybe (fromMaybe, mapMaybe)
+import Data.Monoid (Any(Any), getAny)
 
 import Convert.Scoper
 import Convert.Traverse
diff --git a/src/Convert/Cast.hs b/src/Convert/Cast.hs
index b51f5264..e9921405 100644
--- a/src/Convert/Cast.hs
+++ b/src/Convert/Cast.hs
@@ -27,9 +27,11 @@
 
 module Convert.Cast (convert) where
 
+import Control.Monad (when)
 import Control.Monad.Writer.Strict
 import Data.List (isPrefixOf)
 import Data.Maybe (isJust)
+import Data.Monoid (Any(Any), getAny)
 
 import Convert.ExprUtils
 import Convert.Scoper
diff --git a/src/Convert/GenvarName.hs b/src/Convert/GenvarName.hs
index 52a6a76e..e2082543 100644
--- a/src/Convert/GenvarName.hs
+++ b/src/Convert/GenvarName.hs
@@ -7,6 +7,7 @@
 
 module Convert.GenvarName (convert) where
 
+import Control.Monad (when)
 import Control.Monad.State.Strict
 import Control.Monad.Writer.Strict
 import Data.Functor ((<&>))
diff --git a/src/Convert/Inside.hs b/src/Convert/Inside.hs
index 223d53bc..cd125cb0 100644
--- a/src/Convert/Inside.hs
+++ b/src/Convert/Inside.hs
@@ -21,6 +21,7 @@ import Language.SystemVerilog.AST
 
 import Control.Monad.Writer
 import Data.Maybe (fromMaybe)
+import Data.Monoid (Any(Any), getAny)
 
 convert :: [AST] -> [AST]
 convert = map $ traverseDescriptions $ traverseModuleItems convertModuleItem
diff --git a/src/Convert/Interface.hs b/src/Convert/Interface.hs
index b2be2813..337db5eb 100644
--- a/src/Convert/Interface.hs
+++ b/src/Convert/Interface.hs
@@ -8,6 +8,8 @@ module Convert.Interface (convert, disambiguate) where
 
 import Data.List (intercalate, (\\))
 import Data.Maybe (isJust, isNothing, mapMaybe)
+import Data.Monoid (Any(Any), getAny)
+import Control.Monad (when, (>=>))
 import Control.Monad.Writer.Strict
 import Text.Read (readMaybe)
 import qualified Data.Map.Strict as Map
diff --git a/src/Convert/Jump.hs b/src/Convert/Jump.hs
index 9bc86547..e37c087b 100644
--- a/src/Convert/Jump.hs
+++ b/src/Convert/Jump.hs
@@ -11,6 +11,7 @@ module Convert.Jump (convert) where
 
 import Control.Monad.State.Strict
 import Control.Monad.Writer.Strict
+import Data.Monoid (Any(Any), getAny)
 
 import Convert.Traverse
 import Language.SystemVerilog.AST
diff --git a/src/Convert/Logic.hs b/src/Convert/Logic.hs
index f41c7369..caa79d19 100644
--- a/src/Convert/Logic.hs
+++ b/src/Convert/Logic.hs
@@ -25,6 +25,7 @@
 
 module Convert.Logic (convert) where
 
+import Control.Monad (when)
 import Control.Monad.Writer.Strict
 import qualified Data.Map.Strict as Map
 import qualified Data.Set as Set
diff --git a/src/Convert/Package.hs b/src/Convert/Package.hs
index 91ee749c..495f9cc8 100644
--- a/src/Convert/Package.hs
+++ b/src/Convert/Package.hs
@@ -23,6 +23,7 @@ module Convert.Package
     , prefixItems
     ) where
 
+import Control.Monad (when, (>=>))
 import Control.Monad.State.Strict
 import Control.Monad.Writer.Strict
 import Data.Functor ((<&>))
diff --git a/src/Convert/ParamNoDefault.hs b/src/Convert/ParamNoDefault.hs
index 659f4aec..b09f7d2a 100644
--- a/src/Convert/ParamNoDefault.hs
+++ b/src/Convert/ParamNoDefault.hs
@@ -14,6 +14,7 @@
 
 module Convert.ParamNoDefault (convert) where
 
+import Control.Monad (when)
 import Control.Monad.Writer.Strict
 import Data.List (intercalate)
 import qualified Data.Map.Strict as Map
diff --git a/src/Convert/ParamType.hs b/src/Convert/ParamType.hs
index c074bd3b..9b48a5e7 100644
--- a/src/Convert/ParamType.hs
+++ b/src/Convert/ParamType.hs
@@ -10,6 +10,7 @@ import Control.Monad.Writer.Strict
 import Data.Either (isRight, lefts)
 import qualified Data.Map.Strict as Map
 import qualified Data.Set as Set
+import Data.Monoid (Any(Any), getAny)
 
 import Convert.Traverse
 import Language.SystemVerilog.AST
diff --git a/src/Convert/Scoper.hs b/src/Convert/Scoper.hs
index f297311c..22279f38 100644
--- a/src/Convert/Scoper.hs
+++ b/src/Convert/Scoper.hs
@@ -70,6 +70,7 @@ module Convert.Scoper
     , LookupResult
     ) where
 
+import Control.Monad (join, when)
 import Control.Monad.State.Strict
 import Data.List (findIndices, intercalate, isPrefixOf, partition)
 import Data.Maybe (isNothing)
diff --git a/src/Convert/StringParam.hs b/src/Convert/StringParam.hs
index 1ec2afa9..46ca8850 100644
--- a/src/Convert/StringParam.hs
+++ b/src/Convert/StringParam.hs
@@ -11,6 +11,7 @@
 
 module Convert.StringParam (convert) where
 
+import Control.Monad (when)
 import Control.Monad.Writer.Strict
 import Data.Maybe (mapMaybe)
 import qualified Data.Set as Set
diff --git a/src/Convert/StructConst.hs b/src/Convert/StructConst.hs
index 9cfca3dd..b5315042 100644
--- a/src/Convert/StructConst.hs
+++ b/src/Convert/StructConst.hs
@@ -9,6 +9,7 @@
 
 module Convert.StructConst (convert) where
 
+import Control.Monad (join, mplus, when)
 import Control.Monad.State.Strict
 import Data.Maybe (fromMaybe)
 import Data.Tuple (swap)
diff --git a/src/Convert/Traverse.hs b/src/Convert/Traverse.hs
index 3c3dcf4e..53ba6a29 100644
--- a/src/Convert/Traverse.hs
+++ b/src/Convert/Traverse.hs
@@ -112,6 +112,7 @@ module Convert.Traverse
 
 import Data.Bitraversable (bimapM)
 import Data.Functor.Identity (Identity, runIdentity)
+import Control.Monad ((>=>))
 import Control.Monad.Writer.Strict
 import Language.SystemVerilog.AST
 
diff --git a/src/Convert/UnbasedUnsized.hs b/src/Convert/UnbasedUnsized.hs
index b39ff6da..6ca100dd 100644
--- a/src/Convert/UnbasedUnsized.hs
+++ b/src/Convert/UnbasedUnsized.hs
@@ -20,6 +20,7 @@ import Control.Monad.Writer.Strict
 import Data.Either (isLeft)
 import Data.Maybe (isNothing, mapMaybe)
 import qualified Data.Map.Strict as Map
+import Data.Monoid (Any(Any), getAny)
 
 import Convert.Package (inject, prefixItems)
 import Convert.Traverse
diff --git a/src/Convert/UnnamedGenBlock.hs b/src/Convert/UnnamedGenBlock.hs
index c2802248..d6c05ce9 100644
--- a/src/Convert/UnnamedGenBlock.hs
+++ b/src/Convert/UnnamedGenBlock.hs
@@ -10,6 +10,7 @@
 
 module Convert.UnnamedGenBlock (convert) where
 
+import Control.Monad (when)
 import Control.Monad.State.Strict
 import Data.List (isPrefixOf)
 
diff --git a/src/Convert/UnpackedArray.hs b/src/Convert/UnpackedArray.hs
index 3dd2632f..ef7d5b60 100644
--- a/src/Convert/UnpackedArray.hs
+++ b/src/Convert/UnpackedArray.hs
@@ -11,6 +11,7 @@
 
 module Convert.UnpackedArray (convert) where
 
+import Control.Monad (when, (>=>))
 import Control.Monad.State.Strict
 import qualified Data.Map.Strict as Map
 
diff --git a/src/Language/SystemVerilog/Parser.hs b/src/Language/SystemVerilog/Parser.hs
index 46fd6083..8ed9f5f3 100644
--- a/src/Language/SystemVerilog/Parser.hs
+++ b/src/Language/SystemVerilog/Parser.hs
@@ -6,6 +6,8 @@ module Language.SystemVerilog.Parser
     , Config(..)
     ) where
 
+import Control.Monad (when)
+import Control.Monad.IO.Class (liftIO)
 import Control.Monad.Except
 import Data.List (elemIndex)
 import Data.Maybe (catMaybes)
diff --git a/src/Language/SystemVerilog/Parser/Parse.y b/src/Language/SystemVerilog/Parser/Parse.y
index 64ef2253..23092fbf 100644
--- a/src/Language/SystemVerilog/Parser/Parse.y
+++ b/src/Language/SystemVerilog/Parser/Parse.y
@@ -15,6 +15,7 @@
 {-# LANGUAGE BlockArguments #-}
 module Language.SystemVerilog.Parser.Parse (parse) where
 
+import Control.Monad (when)
 import Control.Monad.Except
 import Control.Monad.State.Strict
 import Data.Maybe (catMaybes, fromMaybe)
diff --git a/src/Language/SystemVerilog/Parser/Preprocess.hs b/src/Language/SystemVerilog/Parser/Preprocess.hs
index 9822f72d..6688f221 100644
--- a/src/Language/SystemVerilog/Parser/Preprocess.hs
+++ b/src/Language/SystemVerilog/Parser/Preprocess.hs
@@ -14,6 +14,7 @@ module Language.SystemVerilog.Parser.Preprocess
     , Contents
     ) where
 
+import Control.Monad (when)
 import Control.Monad.Except
 import Control.Monad.State.Strict
 import Data.Char (ord)
diff --git a/stack.yaml b/stack.yaml
index 7c2ed354..90aab604 100644
--- a/stack.yaml
+++ b/stack.yaml
@@ -1,4 +1,4 @@
-resolver: lts-21.25
+resolver: lts-22.19
 pvp-bounds: both
 ghc-options:
     $locals: -j2
diff --git a/stack.yaml.lock b/stack.yaml.lock
index f823d294..f8f20981 100644
--- a/stack.yaml.lock
+++ b/stack.yaml.lock
@@ -6,7 +6,7 @@
 packages: []
 snapshots:
 - completed:
-    sha256: a81fb3877c4f9031e1325eb3935122e608d80715dc16b586eb11ddbff8671ecd
-    size: 640086
-    url: https://raw.githubusercontent.com/commercialhaskell/stackage-snapshots/master/lts/21/25.yaml
-  original: lts-21.25
+    sha256: e5cac927cf7ccbd52aa41476baa68b88c564ee6ddc3bc573dbf4210069287fe7
+    size: 713340
+    url: https://raw.githubusercontent.com/commercialhaskell/stackage-snapshots/master/lts/22/19.yaml
+  original: lts-22.19