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hal: ra: Add source code for supporting custom eth phy driver
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This update is for Ethernet driver to better fit into Zephyr
standard.
Add in ETHER_CFG_USE_CUSTOM_PHY_DRIVER to Ethernet controller
driver to skip the phy control and allow the use of Zephyr
phy driver.
Add phy link speed to Ethernet controller driver instance
control.
Add phy_lsi_address to Ethernet phy instance control to
allow the control of phy address as input

Signed-off-by: Duy Nguyen <[email protected]>
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@duynguyenxa
duynguyenxa committed Nov 21, 2024
1 parent dc1be98 commit 961b3f9
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Showing 12 changed files with 51 additions and 434 deletions.
10 changes: 3 additions & 7 deletions drivers/ra/CMakeLists.txt
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Original file line number Diff line number Diff line change
Expand Up @@ -69,12 +69,8 @@ if(CONFIG_USE_RA_FSP_SCE)
endif()
endif()

zephyr_library_sources_ifdef(CONFIG_USE_RA_FSP_ETHER_PHY
fsp/src/r_ether_phy/r_ether_phy.c)

zephyr_library_sources_ifdef(CONFIG_USE_RA_FSP_ETHER
fsp/src/r_ether/r_ether.c)

if (CONFIG_USE_RA_FSP_ETHER)
file(GLOB ether_phy_srcs
"fsp/src/r_ether_phy/r_ether_phy.c"
"fsp/src/r_ether_phy/targets/*/*.c")
zephyr_sources(${ether_phy_srcs})
endif()
15 changes: 15 additions & 0 deletions drivers/ra/README
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Original file line number Diff line number Diff line change
Expand Up @@ -58,3 +58,18 @@ Patch List:
* Move the include for cmsis_compiler.h after include for Renesas CMSIS header file
Impacted files:
drivers/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/renesas.h

* Add in ETHER_CFG_USE_CUSTOM_PHY_DRIVER to Ethernet controller driver to skip the phy control and allow the use of Zephyr phy driver.
Add phy link speed to Ethernet controller driver instance control.
Remove static definition of some internal function is ethernet driver to allow their usage in Zephyr side
Add phy_lsi_address to Ethernet phy instance control to allow the control of phy address as input.
Remove the phy target settings as they are not used.
Impacted files:
drivers/ra/fsp/src/r_ether/r_ether.c
drivers/ra/fsp/src/r_ether_phy/r_ether_phy.c
drivers/ra/fsp/src/r_ether_phy/targets/DP83620/r_ether_phy_target_dp83620.c
drivers/ra/fsp/src/r_ether_phy/targets/ICS1894/r_ether_phy_target_ics1894.c
drivers/ra/fsp/src/r_ether_phy/targets/KSZ8041/r_ether_phy_target_ksz8041.c
drivers/ra/fsp/src/r_ether_phy/targets/KSZ8091RNB/r_ether_phy_target_ksz8091rnb.c
drivers/ra/fsp/inc/instances/r_ether_phy.h
drivers/ra/fsp/inc/instances/r_ether.h
1 change: 1 addition & 0 deletions drivers/ra/fsp/inc/instances/r_ether.h
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Original file line number Diff line number Diff line change
Expand Up @@ -105,6 +105,7 @@ typedef struct st_ether_instance_ctrl
ether_link_change_t link_change; ///< status of link change
ether_magic_packet_t magic_packet; ///< status of magic packet detection
ether_link_establish_status_t link_establish_status; ///< Current Link status
uint32_t link_speed_duplex; ///< Current Link speed and duplex status

/* Pointer to callback and optional working memory */
void (* p_callback)(ether_callback_args_t *);
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1 change: 1 addition & 0 deletions drivers/ra/fsp/inc/instances/r_ether_phy.h
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Original file line number Diff line number Diff line change
Expand Up @@ -42,6 +42,7 @@ typedef enum e_ether_phy_interface_status
typedef struct st_ether_phy_instance_ctrl
{
uint32_t open; ///< Used to determine if the channel is configured
uint8_t phy_lsi_address; ///< Address of PHY-LSI

/* Configuration of Ethernet PHY-LSI module. */
ether_phy_cfg_t const * p_ether_phy_cfg; ///< Pointer to initial configurations.
Expand Down
32 changes: 24 additions & 8 deletions drivers/ra/fsp/src/r_ether/r_ether.c
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Original file line number Diff line number Diff line change
Expand Up @@ -161,7 +161,7 @@ static void ether_enable_icu(ether_instance_ctrl_t * const p_instance_ctrl)
static void ether_disable_icu(ether_instance_ctrl_t * const p_instance_ctrl);
static void ether_reset_mac(R_ETHERC_EDMAC_Type * const p_reg);
static void ether_init_descriptors(ether_instance_ctrl_t * const p_instance_ctrl);
static void ether_init_buffers(ether_instance_ctrl_t * const p_instance_ctrl);
void ether_init_buffers(ether_instance_ctrl_t * const p_instance_ctrl);
static fsp_err_t ether_buffer_get(ether_instance_ctrl_t * const p_instance_ctrl,
void ** const p_buffer,
uint32_t * p_buffer_size);
Expand All @@ -170,10 +170,10 @@ static void ether_pause_resolution(uint32_t const local_ability,
uint32_t const partner_ability,
uint32_t * ptx_pause,
uint32_t * prx_pause);
static void ether_configure_mac(ether_instance_ctrl_t * const p_instance_ctrl,
void ether_configure_mac(ether_instance_ctrl_t * const p_instance_ctrl,
const uint8_t mac_addr[],
const uint8_t mode);
static fsp_err_t ether_do_link(ether_instance_ctrl_t * const p_instance_ctrl, const uint8_t mode);
fsp_err_t ether_do_link(ether_instance_ctrl_t * const p_instance_ctrl, const uint8_t mode);
static fsp_err_t ether_link_status_check(ether_instance_ctrl_t const * const p_instance_ctrl);
static uint8_t ether_check_magic_packet_detection_bit(ether_instance_ctrl_t const * const p_instance_ctrl);
static void ether_configure_padding(ether_instance_ctrl_t * const p_instance_ctrl);
Expand Down Expand Up @@ -307,14 +307,14 @@ fsp_err_t R_ETHER_Open (ether_ctrl_t * const p_ctrl, ether_cfg_t const * const p
p_instance_ctrl->p_context = p_cfg->p_context;
p_instance_ctrl->p_callback_memory = NULL;

R_BSP_MODULE_START(FSP_IP_ETHER, p_instance_ctrl->p_ether_cfg->channel);

/* Software reset */
ether_reset_mac(p_instance_ctrl->p_reg_edmac);

/* Setting the padding function */
ether_configure_padding(p_instance_ctrl);

#if !ETHER_CFG_USE_CUSTOM_PHY_DRIVER
/* Software reset the PHY */
phy_ret = p_instance_ctrl->p_ether_cfg->p_ether_phy_instance->p_api->open(
p_instance_ctrl->p_ether_cfg->p_ether_phy_instance->p_ctrl,
Expand All @@ -330,11 +330,16 @@ fsp_err_t R_ETHER_Open (ether_ctrl_t * const p_ctrl, ether_cfg_t const * const p
p_instance_ctrl->p_ether_cfg->p_ether_phy_instance->p_cfg);
}
#endif
#else
phy_ret = FSP_SUCCESS;
#endif

if (FSP_SUCCESS == phy_ret)
{
#if !ETHER_CFG_USE_CUSTOM_PHY_DRIVER
p_instance_ctrl->p_ether_cfg->p_ether_phy_instance->p_api->startAutoNegotiate(
p_instance_ctrl->p_ether_cfg->p_ether_phy_instance->p_ctrl);
#endif

/* Clear all ETHERC status BFR, PSRTO, LCHNG, MPD, ICD */
p_reg_etherc->ECSR = ETHER_ETHERC_INTERRUPT_FACTOR_ALL;
Expand Down Expand Up @@ -398,8 +403,10 @@ fsp_err_t R_ETHER_Close (ether_ctrl_t * const p_ctrl)
/* Disable Ethernet interrupt. */
ether_disable_icu(p_instance_ctrl);

#if !ETHER_CFG_USE_CUSTOM_PHY_DRIVER
p_instance_ctrl->p_ether_cfg->p_ether_phy_instance->p_api->close(
p_instance_ctrl->p_ether_cfg->p_ether_phy_instance->p_ctrl);
#endif

p_reg_etherc->ECSIPR_b.LCHNGIP = 0;
p_reg_edmac->EESIPR_b.ECIIP = 0;
Expand Down Expand Up @@ -1328,7 +1335,7 @@ static void ether_init_descriptors (ether_instance_ctrl_t * const p_instance_ctr
* ETHERC control block.
* Return Value : none
***********************************************************************************************************************/
static void ether_init_buffers (ether_instance_ctrl_t * const p_instance_ctrl)
void ether_init_buffers (ether_instance_ctrl_t * const p_instance_ctrl)
{
uint32_t i;
uint32_t buffer_num;
Expand Down Expand Up @@ -1547,7 +1554,7 @@ static void ether_pause_resolution (uint32_t const local_ability,
* USE_MAGIC_PACKET_DETECT (1) - Magic packet detection mode
* Return Value : none
***********************************************************************************************************************/
static void ether_configure_mac (ether_instance_ctrl_t * const p_instance_ctrl,
void ether_configure_mac (ether_instance_ctrl_t * const p_instance_ctrl,
const uint8_t mac_addr[],
const uint8_t mode)
{
Expand Down Expand Up @@ -1603,7 +1610,7 @@ static void ether_configure_mac (ether_instance_ctrl_t * const p_instance_ctrl,
* or result of Auto-negotiation is abnormal.
*
***********************************************************************************************************************/
static fsp_err_t ether_do_link (ether_instance_ctrl_t * const p_instance_ctrl, const uint8_t mode)
fsp_err_t ether_do_link (ether_instance_ctrl_t * const p_instance_ctrl, const uint8_t mode)
{
fsp_err_t err;
R_ETHERC0_Type * p_reg_etherc;
Expand All @@ -1625,12 +1632,17 @@ static fsp_err_t ether_do_link (ether_instance_ctrl_t * const p_instance_ctrl, c
p_reg_etherc = (R_ETHERC0_Type *) p_instance_ctrl->p_reg_etherc;
p_reg_edmac = (R_ETHERC_EDMAC_Type *) p_instance_ctrl->p_reg_edmac;

#if !ETHER_CFG_USE_CUSTOM_PHY_DRIVER
/* Set the link status */
link_result = p_instance_ctrl->p_ether_cfg->p_ether_phy_instance->p_api->linkPartnerAbilityGet(
p_instance_ctrl->p_ether_cfg->p_ether_phy_instance->p_ctrl,
&link_speed_duplex,
&local_pause_bits,
&partner_pause_bits);
#else
link_result = FSP_SUCCESS;
link_speed_duplex = p_instance_ctrl->link_speed_duplex;
#endif

if (FSP_SUCCESS == link_result)
{
Expand Down Expand Up @@ -1807,11 +1819,15 @@ static uint8_t ether_check_magic_packet_detection_bit (ether_instance_ctrl_t con
**********************************************************************************************************************/
static fsp_err_t ether_link_status_check (ether_instance_ctrl_t const * const p_instance_ctrl)
{
fsp_err_t err = FSP_SUCCESS;
fsp_err_t err;
fsp_err_t link_status;

#if !ETHER_CFG_USE_CUSTOM_PHY_DRIVER
link_status = p_instance_ctrl->p_ether_cfg->p_ether_phy_instance->p_api->linkStatusGet(
p_instance_ctrl->p_ether_cfg->p_ether_phy_instance->p_ctrl);
#else
link_status = FSP_SUCCESS;
#endif

if (FSP_ERR_ETHER_PHY_ERROR_LINK == link_status)
{
Expand Down
5 changes: 2 additions & 3 deletions drivers/ra/fsp/src/r_ether_phy/r_ether_phy.c
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Original file line number Diff line number Diff line change
Expand Up @@ -213,8 +213,7 @@ fsp_err_t R_ETHER_PHY_Open (ether_phy_ctrl_t * const p_ctrl, ether_phy_cfg_t con
/* Initialize configuration of ethernet phy module. */
p_instance_ctrl->p_ether_phy_cfg = p_cfg;

/* Configure pins for MII or RMII. Set PHYMODE0 if MII is selected. */
R_PMISC->PFENET = (uint8_t) ((ETHER_PHY_MII_TYPE_MII == p_cfg->mii_type) << R_PMISC_PFENET_PHYMODE0_Pos);
R_BSP_MODULE_START(FSP_IP_ETHER, p_instance_ctrl->p_ether_phy_cfg->channel);

#if ETHER_PHY_CFG_INIT_PHY_LSI_AUTOMATIC
uint32_t reg = 0;
Expand Down Expand Up @@ -670,7 +669,7 @@ static void ether_phy_reg_set (ether_phy_instance_ctrl_t * p_instance_ctrl, uint
data |= (ETHER_PHY_MII_WRITE << 12); /* OP code(WT) */
}

data |= (uint32_t) (p_instance_ctrl->p_ether_phy_cfg->phy_lsi_address << 7); /* PHY Address */
data |= (uint32_t) (p_instance_ctrl->phy_lsi_address << 7); /* PHY Address */

data |= (reg_addr << 2); /* Reg Address */

Expand Down
94 changes: 0 additions & 94 deletions drivers/ra/fsp/src/r_ether_phy/targets/DP83620/r_ether_phy_target_dp83620.c
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