From 337d27141fc0704afc222ab2a2692b37f886e238 Mon Sep 17 00:00:00 2001 From: Junho Lee Date: Wed, 20 Nov 2024 16:36:50 +0900 Subject: [PATCH] boards: raspberrypi: add PCIe support for Raspberry Pi 5 Enable two PCIe controllers for Raspberry Pi 5. Signed-off-by: Junho Lee --- boards/raspberrypi/rpi_5/doc/index.rst | 3 +++ boards/raspberrypi/rpi_5/rpi_5.dts | 1 + boards/raspberrypi/rpi_5/rpi_5_defconfig | 3 +++ dts/arm64/broadcom/bcm2712.dtsi | 14 ++++++++++++++ 4 files changed, 21 insertions(+) diff --git a/boards/raspberrypi/rpi_5/doc/index.rst b/boards/raspberrypi/rpi_5/doc/index.rst index d503f573df356c..6285e425c252e1 100644 --- a/boards/raspberrypi/rpi_5/doc/index.rst +++ b/boards/raspberrypi/rpi_5/doc/index.rst @@ -49,6 +49,9 @@ The Raspberry Pi 5 board configuration supports the following hardware features: * - UART - :kconfig:option:`CONFIG_SERIAL` - :dtcompatible:`arm,pl011` + * - PCIE + - :kconfig:option:`CONFIG_PCIE` + - :dtcompatible:`brcm,brcmstb-pcie` Not all hardware features are supported yet. See `Raspberry Pi hardware`_ for the complete list of hardware features. diff --git a/boards/raspberrypi/rpi_5/rpi_5.dts b/boards/raspberrypi/rpi_5/rpi_5.dts index adba94d94748fc..3f942d4e6f5011 100644 --- a/boards/raspberrypi/rpi_5/rpi_5.dts +++ b/boards/raspberrypi/rpi_5/rpi_5.dts @@ -23,6 +23,7 @@ zephyr,sram = &sram0; zephyr,console = &uart10; zephyr,shell-uart = &uart10; + zephyr,pcie-controller = &pcie1; }; leds { diff --git a/boards/raspberrypi/rpi_5/rpi_5_defconfig b/boards/raspberrypi/rpi_5/rpi_5_defconfig index bc0375e8120347..55855307b4daa5 100644 --- a/boards/raspberrypi/rpi_5/rpi_5_defconfig +++ b/boards/raspberrypi/rpi_5/rpi_5_defconfig @@ -8,3 +8,6 @@ CONFIG_TIMER_READS_ITS_FREQUENCY_AT_RUNTIME=y CONFIG_SERIAL=y CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y + +CONFIG_PCIE=y +CONFIG_PCIE_CONTROLLER=y diff --git a/dts/arm64/broadcom/bcm2712.dtsi b/dts/arm64/broadcom/bcm2712.dtsi index 07084ffe75dc00..e99a640eb2efb0 100644 --- a/dts/arm64/broadcom/bcm2712.dtsi +++ b/dts/arm64/broadcom/bcm2712.dtsi @@ -92,6 +92,20 @@ #address-cells = <2>; #size-cells = <1>; + pcie1: pcie@1000110000 { + compatible = "brcm,brcmstb-pcie"; + reg = <0x10 0x110000 0x9310>, + <0x0 0x0 0x8000000>, + <0x0 0x8000000 0x10000>, + <0x0 0x0 0x10>; + #address-cells = <3>; + #size-cells = <2>; + status = "okay"; + ranges = <0x02000000 0x0 0x0 0x1b 0x0 0x00 0xfffffffc>, + <0x43000000 0x4 0x0 0x18 0x0 0x03 0x00000000>, + <0x03000000 0x0 0x0 0x10 0x0 0x10 0x00000000>; + }; + pcie2: pcie@1000120000 { compatible = "brcm,brcmstb-pcie"; reg = <0x10 0x120000 0x9310>,