From a9bdaf428a1307dfeba219852f8ed7ab185a219a Mon Sep 17 00:00:00 2001 From: Martin Stumpf Date: Wed, 4 Dec 2024 11:04:00 +0100 Subject: [PATCH] drivers: flash: flexspi: Add 4-byte addressing support for MT25 family Currently, MT25 flashes were running in 3-byte mode. This is not compatible with the chip we use in our project (MT25QU01GBBB), as only 128 Mbit of its 1 Gbit can be addressed. Signed-off-by: Martin Stumpf --- doc/releases/release-notes-4.1.rst | 2 ++ drivers/flash/flash_mcux_flexspi_nor.c | 43 ++++++++++++++++++++++++-- 2 files changed, 42 insertions(+), 3 deletions(-) diff --git a/doc/releases/release-notes-4.1.rst b/doc/releases/release-notes-4.1.rst index 39cfce2556aba6..bce53b59836d0b 100644 --- a/doc/releases/release-notes-4.1.rst +++ b/doc/releases/release-notes-4.1.rst @@ -150,6 +150,8 @@ Drivers and Sensors * Flash + * NXP MCUX FlexSPI: Add support for 4-byte addressing mode of Micron MT25Q flash family (:github:`82532`) + * FPGA * Extracted from :dtcompatible:`lattice,ice40-fpga` the compatible and driver for diff --git a/drivers/flash/flash_mcux_flexspi_nor.c b/drivers/flash/flash_mcux_flexspi_nor.c index fedd8d541b9cf7..d7a73c9df28cbb 100644 --- a/drivers/flash/flash_mcux_flexspi_nor.c +++ b/drivers/flash/flash_mcux_flexspi_nor.c @@ -1012,7 +1012,7 @@ static int flash_flexspi_nor_check_jedec(struct flash_flexspi_nor_data *data, kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_SE_4B, kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 32); flexspi_lut[ERASE_BLOCK][0] = FLEXSPI_LUT_SEQ( - kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0xDC, + kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_BE_4B, kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 32), /* Read instruction used for polling is 0x05 */ data->legacy_poll = true; @@ -1043,7 +1043,7 @@ static int flash_flexspi_nor_check_jedec(struct flash_flexspi_nor_data *data, kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_SE_4B, kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 32); flexspi_lut[ERASE_BLOCK][0] = FLEXSPI_LUT_SEQ( - kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0xDC, + kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_BE_4B, kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 32), /* Read instruction used for polling is 0x05 */ data->legacy_poll = true; @@ -1074,7 +1074,7 @@ static int flash_flexspi_nor_check_jedec(struct flash_flexspi_nor_data *data, kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_SE_4B, kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 32); flexspi_lut[ERASE_BLOCK][0] = FLEXSPI_LUT_SEQ( - kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0xDC, + kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_BE_4B, kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 32), /* Read instruction used for polling is 0x05 */ data->legacy_poll = true; @@ -1083,6 +1083,43 @@ static int flash_flexspi_nor_check_jedec(struct flash_flexspi_nor_data *data, kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x01); /* Device uses bit 6 of status reg 1 for QE */ return flash_flexspi_nor_quad_enable(data, flexspi_lut, JESD216_DW15_QER_VAL_S1B6); + case 0x19ba20: /* MT25QL256 */ + case 0x20ba20: /* MT25QL512 */ + case 0x21ba20: /* MT25QL01G */ + case 0x22ba20: /* MT25QL02G */ + case 0x19bb20: /* MT25QU256 */ + case 0x20bb20: /* MT25QU512 */ + case 0x21bb20: /* MT25QU01G */ + case 0x22bb20: /* MT25QU02G */ + /* MT25Q flash with more than 32MB, use 4 byte read/write */ + flexspi_lut[READ][0] = FLEXSPI_LUT_SEQ( + kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_4READ_4B, + kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_4PAD, 32); + /* Flash needs 10 dummy cycles */ + flexspi_lut[READ][1] = FLEXSPI_LUT_SEQ( + kFLEXSPI_Command_DUMMY_SDR, kFLEXSPI_4PAD, 10, + kFLEXSPI_Command_READ_SDR, kFLEXSPI_4PAD, 0x04); + /* Update PROGRAM commands for 4 byte 1S-4S-4S mode */ + flexspi_lut[PAGE_PROGRAM][0] = FLEXSPI_LUT_SEQ( + kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_PP_1_4_4_4B, + kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_4PAD, 32); + flexspi_lut[PAGE_PROGRAM][1] = FLEXSPI_LUT_SEQ( + kFLEXSPI_Command_WRITE_SDR, kFLEXSPI_4PAD, 0x4, + kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x0); + /* Update ERASE commands for 4 byte mode */ + flexspi_lut[ERASE_SECTOR][0] = FLEXSPI_LUT_SEQ( + kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_SE_4B, + kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 32); + flexspi_lut[ERASE_BLOCK][0] = FLEXSPI_LUT_SEQ( + kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_BE_4B, + kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 32), + /* Read instruction used for polling is 0x05 */ + data->legacy_poll = true; + flexspi_lut[READ_STATUS_REG][0] = FLEXSPI_LUT_SEQ( + kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_RDSR, + kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x01); + /* Device has no QE bit, 1-4-4 and 1-1-4 is always enabled */ + return 0; default: return -ENOTSUP; }