diff --git a/drivers/dai/intel/ssp/ssp.c b/drivers/dai/intel/ssp/ssp.c
index 6fa7c9a0446404..7292b8200edb79 100644
--- a/drivers/dai/intel/ssp/ssp.c
+++ b/drivers/dai/intel/ssp/ssp.c
@@ -1962,15 +1962,16 @@ static int dai_ssp_parse_tlv(struct dai_intel_ssp *dp, const uint8_t *aux_ptr, s
 		case SSP_LINK_CLK_SOURCE:
 #ifdef CONFIG_SOC_SERIES_INTEL_ADSP_ACE
 			link = (struct ssp_intel_link_ctl *)&aux_tlv->val;
-
 #if CONFIG_SOC_INTEL_ACE15_MTPM
-			sys_write32(sys_read32(dai_ip_base(dp) + I2SLCTL_OFFSET) |
+			sys_write32((sys_read32(dai_ip_base(dp) + I2SLCTL_OFFSET) &
+				    ~I2CLCTL_MLCS(0x7)) |
 				    I2CLCTL_MLCS(link->clock_source), dai_ip_base(dp) +
 				    I2SLCTL_OFFSET);
 #elif CONFIG_SOC_INTEL_ACE20_LNL || CONFIG_SOC_INTEL_ACE30_PTL
-			sys_write32(sys_read32(dai_i2svss_base(dp) + I2SLCTL_OFFSET) |
-				    I2CLCTL_MLCS(link->clock_source), dai_i2svss_base(dp) +
-				    I2SLCTL_OFFSET);
+			sys_write32((sys_read32(dai_i2svss_base(dp) + I2SLCTL_OFFSET) &
+				    ~I2CLCTL_MLCS(0x7)) |
+				    I2CLCTL_MLCS(link->clock_source),
+				    dai_i2svss_base(dp) + I2SLCTL_OFFSET);
 #endif
 			LOG_INF("link clock_source %u", link->clock_source);
 #endif
diff --git a/drivers/dai/intel/ssp/ssp_regs_v1.h b/drivers/dai/intel/ssp/ssp_regs_v1.h
index a821ab8733a63e..ba76de12f33c05 100644
--- a/drivers/dai/intel/ssp/ssp_regs_v1.h
+++ b/drivers/dai/intel/ssp/ssp_regs_v1.h
@@ -215,7 +215,7 @@
 #define I2SLCTL_SPA(x)		BIT(0 + x)
 #define I2SLCTL_CPA(x)		BIT(8 + x)
 
-#define I2CLCTL_MLCS(x)		DAI_INTEL_SSP_SET_BITS(30, 27, x)
+#define I2CLCTL_MLCS(x)		DAI_INTEL_SSP_SET_BITS(29, 27, x)
 #define SHIM_CLKCTL		0x78
 #define SHIM_CLKCTL_I2SFDCGB(x)		BIT(20 + x)
 #define SHIM_CLKCTL_I2SEFDCGB(x)	BIT(18 + x)
diff --git a/drivers/dai/intel/ssp/ssp_regs_v2.h b/drivers/dai/intel/ssp/ssp_regs_v2.h
index e2d1c826d075c3..72ff40b70ad621 100644
--- a/drivers/dai/intel/ssp/ssp_regs_v2.h
+++ b/drivers/dai/intel/ssp/ssp_regs_v2.h
@@ -218,7 +218,7 @@
 #define PCMS0CM_OFFSET		0x16
 #define PCMS1CM_OFFSET		0x1A
 
-#define I2CLCTL_MLCS(x)		DAI_INTEL_SSP_SET_BITS(30, 27, x)
+#define I2CLCTL_MLCS(x)		DAI_INTEL_SSP_SET_BITS(29, 27, x)
 #define SHIM_CLKCTL		0x78
 #define SHIM_CLKCTL_I2SFDCGB(x)		BIT(20 + x)
 #define SHIM_CLKCTL_I2SEFDCGB(x)	BIT(18 + x)
diff --git a/drivers/dai/intel/ssp/ssp_regs_v3.h b/drivers/dai/intel/ssp/ssp_regs_v3.h
index 5990404c6f7fb5..e11f5543cce207 100644
--- a/drivers/dai/intel/ssp/ssp_regs_v3.h
+++ b/drivers/dai/intel/ssp/ssp_regs_v3.h
@@ -215,7 +215,7 @@
 #define I2SLCTL_SPA(x)		BIT(16 + x)
 #define I2SLCTL_CPA(x)		BIT(23 + x)
 
-#define I2CLCTL_MLCS(x)		DAI_INTEL_SSP_SET_BITS(30, 27, x)
+#define I2CLCTL_MLCS(x)		DAI_INTEL_SSP_SET_BITS(29, 27, x)
 #define SHIM_CLKCTL		0x78
 #define SHIM_CLKCTL_I2SFDCGB(x)		BIT(20 + x)
 #define SHIM_CLKCTL_I2SEFDCGB(x)	BIT(18 + x)
diff --git a/dts/xtensa/intel/intel_adsp_ace30_ptl.dtsi b/dts/xtensa/intel/intel_adsp_ace30_ptl.dtsi
index 2ee5213fee5aa1..97be77eb7570b6 100644
--- a/dts/xtensa/intel/intel_adsp_ace30_ptl.dtsi
+++ b/dts/xtensa/intel/intel_adsp_ace30_ptl.dtsi
@@ -205,6 +205,7 @@
 			#size-cells = <0>;
 			reg = <0x00028100 0x1000
 				   0x00079C00 0x200>;
+			i2svss = <0x00028C00 0x1000>;
 			interrupts = <0x00 0 0>;
 			interrupt-parent = <&ace_intc>;
 			dmas = <&hda_link_out 1
@@ -269,6 +270,7 @@
 			#size-cells = <0>;
 			reg = <0x00029100 0x1000
 				   0x00079C00 0x200>;
+			i2svss = <0x00029C00 0x1000>;
 			interrupts = <0x01 0 0>;
 			interrupt-parent = <&ace_intc>;
 			dmas = <&hda_link_out 2
@@ -333,6 +335,7 @@
 			#size-cells = <0>;
 			reg = <0x0002a100 0x1000
 				   0x00079C00 0x200>;
+			i2svss = <0x0002AC00 0x1000>;
 			interrupts = <0x02 0 0>;
 			interrupt-parent = <&ace_intc>;
 			dmas = <&hda_link_out 3