logging: uart_backend: add uncached async uart buffers support #87846
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When async UART is used & DCache is enabled, some SoCs, like STM32H7, require UART buffers to be placed in nocache memory to avoid cache coherence issues. Fixes issue 87795 Signed-off-by: Abderrahmane JARMOUNI <git@jarmouni.me>
Enable the sample to run on stm32h750b-dk board with async UART backend Signed-off-by: Abderrahmane JARMOUNI <git@jarmouni.me>
| (.uart_dev = DEVICE_DT_GET(node_id),)) \ | ||
| .data = &lbu_data##__VA_ARGS__, \ | ||
| (.uart_dev = DEVICE_DT_GET(node_id),)) .data = \ | ||
| &lbu_data##__VA_ARGS__, \ |
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To keep Clang-format happy :)
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No need to add this, clang-format isn't enforced.
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But it doesn't pass in CI too, is that okey?
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It's excluded in CI
zephyr/.github/workflows/compliance.yml
Line 75 in 19c6240
| @@ -225,8 +225,15 @@ const struct log_backend_api log_backend_uart_api = { | |||
| .format_set = format_set, | |||
| }; | |||
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| #ifdef CONFIG_LOG_BACKEND_UART_ASYNC | |||
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Maybe we should add && (defined(CONFIG_SOC_SERIES_STM32H7X) || defined(CONFIG_SOC_SERIES_STM32H7RSX)) here as well since it's the (only) series concerned by this AFAIK.
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Putting buffer in __nocache will help but it will slow down the performance. Maybe it would be better to use STM guards for now. Other vendors may prefer to use cache line aligned memory and do the cache writeback which would have better performance. Nordic is using different appraoch. We have generic module used in drivers that detects if input buffer requires special action and uses memory pool to allocate buffer from a special location, do the copy and writeback if necessary.
| #ifdef CONFIG_LOG_BACKEND_UART_ASYNC | ||
| #define NOCACHE_ATTR __nocache | ||
| #else | ||
| #define ALIGN_BUF |
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is this used somewhere?
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No, just a leftover, will remove.
| @@ -225,8 +225,15 @@ const struct log_backend_api log_backend_uart_api = { | |||
| .format_set = format_set, | |||
| }; | |||
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| #ifdef CONFIG_LOG_BACKEND_UART_ASYNC | |||
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Putting buffer in __nocache will help but it will slow down the performance. Maybe it would be better to use STM guards for now. Other vendors may prefer to use cache line aligned memory and do the cache writeback which would have better performance. Nordic is using different appraoch. We have generic module used in drivers that detects if input buffer requires special action and uses memory pool to allocate buffer from a special location, do the copy and writeback if necessary.
When async UART is used & DCache is enabled, some SoCs, like STM32H7, require UART buffers to be placed in nocache memory to avoid cache coherence issues.
__nocacheattribute will have no effect ifCONFIG_NOCACHE_MEMORY=nFixes #87795