From 73245a83e1e88ed55d5e6cf101d2ba784321dc16 Mon Sep 17 00:00:00 2001 From: Marcin Niestroj Date: Tue, 8 Oct 2024 20:55:46 +0200 Subject: [PATCH 1/3] drivers: usb: stm32: support 'st,stm32-usbphyc' on non-STM32F7 LL_APB2_GRP1_PERIPH_OTGPHYC is only provided by STM32F7 HAL layer, so add 'defined(CONFIG_SOC_SERIES_STM32F7X)' to support build on other platforms. Signed-off-by: Marcin Niestroj --- drivers/usb/device/usb_dc_stm32.c | 2 +- drivers/usb/udc/udc_stm32.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/usb/device/usb_dc_stm32.c b/drivers/usb/device/usb_dc_stm32.c index b5fc75c3c2ea..b1bfe8eb67b3 100644 --- a/drivers/usb/device/usb_dc_stm32.c +++ b/drivers/usb/device/usb_dc_stm32.c @@ -317,7 +317,7 @@ static int usb_dc_stm32_clock_enable(void) LL_AHB1_GRP1_DisableClockLowPower(LL_AHB1_GRP1_PERIPH_OTGHSULPI); #endif -#if USB_OTG_HS_EMB_PHY +#if USB_OTG_HS_EMB_PHY && defined(CONFIG_SOC_SERIES_STM32F7X) LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_OTGPHYC); #endif #endif /* USB_OTG_HS_ULPI_PHY */ diff --git a/drivers/usb/udc/udc_stm32.c b/drivers/usb/udc/udc_stm32.c index 627d22997560..0bc916d5dd64 100644 --- a/drivers/usb/udc/udc_stm32.c +++ b/drivers/usb/udc/udc_stm32.c @@ -1076,7 +1076,7 @@ static int priv_clock_enable(void) LL_AHB1_GRP1_DisableClockLowPower(LL_AHB1_GRP1_PERIPH_OTGHSULPI); #endif /* defined(CONFIG_SOC_SERIES_STM32H7X) */ -#if USB_OTG_HS_EMB_PHY +#if USB_OTG_HS_EMB_PHY && defined(CONFIG_SOC_SERIES_STM32F7X) LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_OTGPHYC); #endif #elif defined(CONFIG_SOC_SERIES_STM32H7X) && DT_HAS_COMPAT_STATUS_OKAY(st_stm32_otgfs) From af145ce8c674759e3e3e660fe05943092cbd9838 Mon Sep 17 00:00:00 2001 From: Marcin Niestroj Date: Tue, 8 Oct 2024 20:34:37 +0200 Subject: [PATCH 2/3] boards: st: nucleo_u5a5zj_q: use HSE as PLL input source HSE is populated on Nucleo board, so it is better to use it due to increased accuracy. Additionally HSE will be reused to drive USB HS peripheral, which is not possible with MSIS. Signed-off-by: Marcin Niestroj --- boards/st/nucleo_u5a5zj_q/nucleo_u5a5zj_q-common.dtsi | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/boards/st/nucleo_u5a5zj_q/nucleo_u5a5zj_q-common.dtsi b/boards/st/nucleo_u5a5zj_q/nucleo_u5a5zj_q-common.dtsi index ecc9e862c990..03dc8f37629c 100644 --- a/boards/st/nucleo_u5a5zj_q/nucleo_u5a5zj_q-common.dtsi +++ b/boards/st/nucleo_u5a5zj_q/nucleo_u5a5zj_q-common.dtsi @@ -59,18 +59,17 @@ status = "okay"; }; -&clk_msis { +&clk_hse { status = "okay"; - msi-range = <4>; - msi-pll-mode; + clock-frequency = ; }; &pll1 { div-m = <1>; - mul-n = <80>; + mul-n = <20>; div-q = <2>; div-r = <2>; - clocks = <&clk_msis>; + clocks = <&clk_hse>; status = "okay"; }; From 1046eb499bad9acdd5e4d9c6a2f4fb27da983bba Mon Sep 17 00:00:00 2001 From: Marcin Niestroj Date: Tue, 8 Oct 2024 20:37:25 +0200 Subject: [PATCH 3/3] boards: st: nucleo_u5a5zj_q: enable USB HS Provide configuration for USB HS with embedded USB HS PHY. Disable USB_DC_STM32_CLOCK_CHECK, since USB PLL is expected to be sourced by 16MHz clock, instead of 48MHz. Signed-off-by: Marcin Niestroj --- boards/st/nucleo_u5a5zj_q/Kconfig.defconfig | 5 +++++ boards/st/nucleo_u5a5zj_q/doc/index.rst | 2 ++ boards/st/nucleo_u5a5zj_q/nucleo_u5a5zj_q.dts | 17 +++++++++++++++++ boards/st/nucleo_u5a5zj_q/nucleo_u5a5zj_q.yaml | 1 + 4 files changed, 25 insertions(+) create mode 100644 boards/st/nucleo_u5a5zj_q/Kconfig.defconfig diff --git a/boards/st/nucleo_u5a5zj_q/Kconfig.defconfig b/boards/st/nucleo_u5a5zj_q/Kconfig.defconfig new file mode 100644 index 000000000000..e114349bfd62 --- /dev/null +++ b/boards/st/nucleo_u5a5zj_q/Kconfig.defconfig @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Marcin Niestroj +# SPDX-License-Identifier: Apache-2.0 + +configdefault USB_DC_STM32_CLOCK_CHECK + default n diff --git a/boards/st/nucleo_u5a5zj_q/doc/index.rst b/boards/st/nucleo_u5a5zj_q/doc/index.rst index ea919c4f10ee..62717c05f88a 100644 --- a/boards/st/nucleo_u5a5zj_q/doc/index.rst +++ b/boards/st/nucleo_u5a5zj_q/doc/index.rst @@ -204,6 +204,8 @@ The Zephyr nucleo_u5a5zj_q board configuration supports the following hardware f +-----------+------------+-------------------------------------+ | RTC | on-chip | rtc | +-----------+------------+-------------------------------------+ +| USB | on-chip | USB high-speed host/device bus | ++-----------+------------+-------------------------------------+ Other hardware features are not yet supported on this Zephyr port. diff --git a/boards/st/nucleo_u5a5zj_q/nucleo_u5a5zj_q.dts b/boards/st/nucleo_u5a5zj_q/nucleo_u5a5zj_q.dts index a9907afe6142..ecefffe7ebeb 100644 --- a/boards/st/nucleo_u5a5zj_q/nucleo_u5a5zj_q.dts +++ b/boards/st/nucleo_u5a5zj_q/nucleo_u5a5zj_q.dts @@ -32,6 +32,14 @@ volt-sensor0 = &vref1; volt-sensor1 = &vbat4; }; + + soc { + usbphyc: usbphyc@40017c00 { + compatible = "st,stm32-usbphyc"; + reg = <0x40017c00 0x400>; + #phy-cells = <0>; + }; + }; }; &flash0 { @@ -74,3 +82,12 @@ &gpdma1 { status = "okay"; }; + +zephyr_udc0: &usbotg_hs { + pinctrl-0 = <&usb_otg_hs_dm_pa11 &usb_otg_hs_dp_pa12>; + pinctrl-names = "default"; + clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x0000c000>, + <&rcc STM32_SRC_HSE USBPHYC_SEL(0)>; + phys = <&usbphyc>; + status = "okay"; +}; diff --git a/boards/st/nucleo_u5a5zj_q/nucleo_u5a5zj_q.yaml b/boards/st/nucleo_u5a5zj_q/nucleo_u5a5zj_q.yaml index cd9370804141..57c0712ffedb 100644 --- a/boards/st/nucleo_u5a5zj_q/nucleo_u5a5zj_q.yaml +++ b/boards/st/nucleo_u5a5zj_q/nucleo_u5a5zj_q.yaml @@ -21,5 +21,6 @@ supported: - backup_sram - dma - rtc + - usb_device ram: 2450 flash: 4096