From 5ebd51338654dafe0ec19712d89bcf10e73bb71a Mon Sep 17 00:00:00 2001 From: Simon Gilbert Date: Sat, 23 Nov 2024 17:23:34 +0000 Subject: [PATCH 01/11] i2c: stm32: Add config option to enable DMA support Add option to enable DMA support Signed-off-by: Simon Gilbert --- drivers/i2c/Kconfig.stm32 | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/i2c/Kconfig.stm32 b/drivers/i2c/Kconfig.stm32 index b07dc5ca589c70..e4d22c486a2b29 100644 --- a/drivers/i2c/Kconfig.stm32 +++ b/drivers/i2c/Kconfig.stm32 @@ -55,4 +55,12 @@ config I2C_STM32_V2_TIMING help Enable STM32 driver bus to calculate the Timing. +config I2C_DMA + bool "DMA support" + depends on I2C_STM32_V2 + select DMA + select CACHE_MANAGEMENT if CPU_HAS_DCACHE + help + Enable DMA support for the STM32 I2C driver. + endif # I2C_STM32 From 253557b6712643aa1d094d28fc1b1b7de169493d Mon Sep 17 00:00:00 2001 From: Simon Gilbert Date: Sat, 23 Nov 2024 17:25:29 +0000 Subject: [PATCH 02/11] i2c: stm32: Add dma settings structs to config and data structs Add initial DMA settings structs to stm32 i2c config and data structs Signed-off-by: Simon Gilbert --- drivers/i2c/i2c_ll_stm32.h | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/i2c/i2c_ll_stm32.h b/drivers/i2c/i2c_ll_stm32.h index ec6db5b32a0834..2eddd12d5ae174 100644 --- a/drivers/i2c/i2c_ll_stm32.h +++ b/drivers/i2c/i2c_ll_stm32.h @@ -15,6 +15,8 @@ #include #endif /* CONFIG_I2C_STM32_BUS_RECOVERY */ +#include + typedef void (*irq_config_func_t)(const struct device *port); #if DT_HAS_COMPAT_STATUS_OKAY(st_stm32_i2c_v2) @@ -48,6 +50,12 @@ struct i2c_stm32_config { const struct i2c_config_timing *timings; size_t n_timings; #endif +#ifdef CONFIG_I2C_DMA + const struct device *dev_dma_tx; + int32_t dma_tx_channel; + const struct device *dev_dma_rx; + int32_t dma_rx_channel; +#endif /* CONFIG_I2C_DMA */ }; struct i2c_stm32_data { @@ -91,6 +99,14 @@ struct i2c_stm32_data { i2c_stm32_smbalert_cb_func_t smbalert_cb_func; const struct device *smbalert_cb_dev; #endif +#ifdef CONFIG_I2C_DMA + struct dma_config dma_tx_cfg; + struct dma_block_config dma_tx_blk_cfg; + struct k_sem dma_tx_sem; + struct dma_config dma_rx_cfg; + struct dma_block_config dma_rx_blk_cfg; + struct k_sem dma_rx_sem; +#endif /* CONFIG_I2C_DMA */ }; int32_t stm32_i2c_transaction(const struct device *dev, From ee3915e5c85be6cf69f058afaf07c1b069b6ee7a Mon Sep 17 00:00:00 2001 From: Simon Gilbert Date: Sat, 23 Nov 2024 17:26:51 +0000 Subject: [PATCH 03/11] i2c: stm32: Add macros to get settings from device tree Add macrobatics to pull DMA settings from device tree Signed-off-by: Simon Gilbert --- drivers/i2c/i2c_ll_stm32.c | 88 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 88 insertions(+) diff --git a/drivers/i2c/i2c_ll_stm32.c b/drivers/i2c/i2c_ll_stm32.c index 677d1f688e5a27..3413b43fcd3919 100644 --- a/drivers/i2c/i2c_ll_stm32.c +++ b/drivers/i2c/i2c_ll_stm32.c @@ -535,6 +535,52 @@ void i2c_stm32_smbalert_disable(const struct device *dev) } #endif /* CONFIG_SMBUS_STM32 */ +#ifdef CONFIG_I2C_DMA +/* This function is executed in the interrupt context */ +static void dma_rx_callback(const struct device *dma_dev, void *user_data, + uint32_t channel, int status) +{ + struct i2c_stm32_data *data = (struct i2c_stm32_data *)user_data; + + switch (status) { + case DMA_STATUS_COMPLETE: + data->current.is_err = 0; + dma_stop(dma_dev, channel); + break; + case DMA_STATUS_BLOCK: + break; + default: + data->current.is_err = 1; + break; + } + + k_sem_give(&data->device_sync_sem); +} + +/* This function is executed in the interrupt context */ +static void dma_tx_callback(const struct device *dma_dev, void *user_data, + uint32_t channel, int status) +{ + struct i2c_stm32_data *data = (struct i2c_stm32_data *)user_data; + + switch (status) { + case DMA_STATUS_COMPLETE: + data->current.is_err = 0; + dma_stop(dma_dev, channel); + break; + case DMA_STATUS_BLOCK: + break; + default: + data->current.is_err = 1; + break; + } + + LOG_DBG("Giving semaphore"); + k_sem_give(&data->device_sync_sem); +} + +#endif /* CONFIG_I2C_DMA */ + /* Macros for I2C instance declaration */ #ifdef CONFIG_I2C_STM32_INTERRUPT @@ -582,6 +628,46 @@ static void i2c_stm32_irq_config_func_##index(const struct device *dev) \ #endif /* CONFIG_I2C_STM32_INTERRUPT */ +#ifdef CONFIG_I2C_DMA + +#define I2C_DMA_INIT(index, dir) \ + .dev_dma_##dir = COND_CODE_1(DT_INST_DMAS_HAS_NAME(index, dir), \ + (DEVICE_DT_GET(STM32_DMA_CTLR(index, dir))), (NULL)), \ + .dma_##dir##_channel = COND_CODE_1(DT_INST_DMAS_HAS_NAME(index, dir), \ + (DT_INST_DMAS_CELL_BY_NAME(index, dir, channel)), (-1)), + +#define I2C_DMA_SLOT_INIT(index, dir) \ + .dma_slot = COND_CODE_1(DT_INST_DMAS_HAS_NAME(index, dir), \ + (DT_INST_DMAS_CELL_BY_NAME(index, dir, slot)), (0)) + +#define I2C_DMA_CFG_INIT(index, name, dir, src, dest, src_addr_incr, dest_addr_incr) \ +.dma_##dir##_cfg = { \ + I2C_DMA_SLOT_INIT(index, dir), \ + .channel_direction = STM32_DMA_CONFIG_DIRECTION(STM32_DMA_CHANNEL_CONFIG(index, dir)), \ + .source_data_size = STM32_DMA_CONFIG_##src##_DATA_SIZE( \ + STM32_DMA_CHANNEL_CONFIG(index, dir)), \ + .dest_data_size = STM32_DMA_CONFIG_##dest##_DATA_SIZE( \ + STM32_DMA_CHANNEL_CONFIG(index, dir)), \ + .source_burst_length = 1, \ + .dest_burst_length = 1, \ + .channel_priority = STM32_DMA_CONFIG_PRIORITY(STM32_DMA_CHANNEL_CONFIG(index, dir)), \ + .dma_callback = dma_##dir##_callback, \ +}, \ +.dma_##dir##_blk_cfg = { \ + .source_addr_adj = src_addr_incr, \ + .dest_addr_adj = dest_addr_incr, \ +}, + +#else + +#define I2C_DMA_INIT(index, dir) + +#define I2C_DMA_SLOT_INIT(index, dir) + +#define I2C_DMA_CFG_INIT(index, name, dir, src, dest, src_addr_incr, dest_addr_incr) + +#endif + #define STM32_I2C_INIT(index) \ STM32_I2C_IRQ_HANDLER_DECL(index); \ \ @@ -607,6 +693,8 @@ static const struct i2c_stm32_config i2c_stm32_cfg_##index = { \ IF_ENABLED(DT_HAS_COMPAT_STATUS_OKAY(st_stm32_i2c_v2), \ (.timings = (const struct i2c_config_timing *) i2c_timings_##index,\ .n_timings = ARRAY_SIZE(i2c_timings_##index),)) \ + I2C_DMA_INIT(index, tx) \ + I2C_DMA_INIT(index, rx) \ }; \ \ static struct i2c_stm32_data i2c_stm32_dev_data_##index; \ From 5b8e89fd0988d6326cb168a1eb08b5086c9443bb Mon Sep 17 00:00:00 2001 From: Simon Gilbert Date: Sat, 23 Nov 2024 17:28:07 +0000 Subject: [PATCH 04/11] i2c: stm32: Add dma header files Add DMA header files Signed-off-by: Simon Gilbert --- drivers/i2c/i2c_ll_stm32.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/i2c/i2c_ll_stm32.c b/drivers/i2c/i2c_ll_stm32.c index 3413b43fcd3919..fa4292aad2e548 100644 --- a/drivers/i2c/i2c_ll_stm32.c +++ b/drivers/i2c/i2c_ll_stm32.c @@ -5,6 +5,8 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include +#include #include #include #include From 63538cccb6fd76fb5ffa19abacaef1a6fabb767c Mon Sep 17 00:00:00 2001 From: Simon Gilbert Date: Sat, 23 Nov 2024 17:29:01 +0000 Subject: [PATCH 05/11] i2c: stm32: Add DMA settings to yaml file Add DMA options (phandle-array and names) to yaml file Signed-off-by: Simon Gilbert --- dts/bindings/i2c/st,stm32-i2c-v2.yaml | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/dts/bindings/i2c/st,stm32-i2c-v2.yaml b/dts/bindings/i2c/st,stm32-i2c-v2.yaml index bc859873ac05d3..80283d518b10e6 100644 --- a/dts/bindings/i2c/st,stm32-i2c-v2.yaml +++ b/dts/bindings/i2c/st,stm32-i2c-v2.yaml @@ -55,3 +55,15 @@ properties: description: | GPIO to which the I2C SDA signal is routed. This is only needed for I2C bus recovery support. + + dmas: + type: phandle-array + description: | + Optional DMA channels used by the I2C peripheral. If specified, these + channels can be used to handle RX and TX transactions over DMA. + + dma-names: + type: string-array + description: | + Names of the optional DMA channels. Expected values are "tx" for + the TX channel and "rx" for the RX channel. From ff5602ba51d53f6a631ac0ff4f3096d19b3d3c96 Mon Sep 17 00:00:00 2001 From: Simon Gilbert Date: Sat, 23 Nov 2024 17:29:46 +0000 Subject: [PATCH 06/11] i2c: stm32: Minor refactor of i2c_stm32_transfer function Tidy up of i2c_stm32_transfer and added TX and RX semaphore inits --- drivers/i2c/i2c_ll_stm32.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/i2c/i2c_ll_stm32.c b/drivers/i2c/i2c_ll_stm32.c index fa4292aad2e548..9f201861dda0db 100644 --- a/drivers/i2c/i2c_ll_stm32.c +++ b/drivers/i2c/i2c_ll_stm32.c @@ -145,7 +145,8 @@ static int i2c_stm32_transfer(const struct device *dev, struct i2c_msg *msg, uint8_t num_msgs, uint16_t slave) { struct i2c_stm32_data *data = dev->data; - struct i2c_msg *current, *next; + struct i2c_msg *current; + struct i2c_msg *next = NULL; int ret = 0; /* Check for validity of all messages, to prevent having to abort @@ -393,6 +394,11 @@ static int i2c_stm32_init(const struct device *dev) cfg->irq_config_func(dev); #endif +#ifdef CONFIG_I2C_DMA + k_sem_init(&data->dma_rx_sem, 1, K_SEM_MAX_LIMIT); + k_sem_init(&data->dma_tx_sem, 1, K_SEM_MAX_LIMIT); +#endif + data->is_configured = false; data->mode = I2CSTM32MODE_I2C; From 207cf56a43988f81b28f3bd201964e3515e812c4 Mon Sep 17 00:00:00 2001 From: Simon Gilbert Date: Sat, 23 Nov 2024 17:32:48 +0000 Subject: [PATCH 07/11] i2c: stm32: Added DMA stop for various i2c comms conditions Added stop DMA fot transmit complete or other master end conditions --- drivers/i2c/i2c_ll_stm32_v2.c | 104 ++++++++++++++++++++++++++++++++++ 1 file changed, 104 insertions(+) diff --git a/drivers/i2c/i2c_ll_stm32_v2.c b/drivers/i2c/i2c_ll_stm32_v2.c index 8e97fffbf09b8b..0dbd6ed1873d83 100644 --- a/drivers/i2c/i2c_ll_stm32_v2.c +++ b/drivers/i2c/i2c_ll_stm32_v2.c @@ -117,6 +117,42 @@ static struct stm32_i2c_timings_t i2c_valid_timing[STM32_I2C_VALID_TIMING_NBR]; static uint32_t i2c_valid_timing_nbr; #endif /* CONFIG_I2C_STM32_V2_TIMING */ +#ifdef CONFIG_I2C_DMA +static int configure_dma(const struct device *dma_dev, uint32_t dma_channel, + struct dma_config *dma_cfg, struct dma_block_config *blk_cfg, + uint32_t source_address, uint32_t dest_address, struct i2c_msg *msg, + struct k_sem *dma_sem, const char *direction) +{ + if (!device_is_ready(dma_dev)) { + LOG_ERR("DMA device not ready for %s", direction); + return -ENODEV; + } + + k_sem_take(dma_sem, K_FOREVER); + + blk_cfg->source_address = source_address; + blk_cfg->dest_address = dest_address; + blk_cfg->block_size = msg->len; + + dma_cfg->head_block = blk_cfg; + dma_cfg->block_count = 1; + + int ret = dma_config(dma_dev, dma_channel, dma_cfg); + if (ret != 0) { + LOG_ERR("Problem setting up %s DMA: %d", direction, ret); + return ret; + } + + ret = dma_start(dma_dev, dma_channel); + if (ret != 0) { + LOG_ERR("Problem starting %s DMA: %d", direction, ret); + return ret; + } + + return 0; +} +#endif + static inline void msg_init(const struct device *dev, struct i2c_msg *msg, uint8_t *next_msg_flags, uint16_t slave, uint32_t transfer) @@ -151,6 +187,48 @@ static inline void msg_init(const struct device *dev, struct i2c_msg *msg, #if defined(CONFIG_I2C_TARGET) data->master_active = true; #endif + +#ifdef CONFIG_I2C_DMA + if (msg->len) { + if (msg->flags & I2C_MSG_READ) { + // Configure RX DMA + if (configure_dma(cfg->dev_dma_rx, cfg->dma_rx_channel, + &data->dma_rx_cfg, &data->dma_rx_blk_cfg, + LL_I2C_DMA_GetRegAddr( + cfg->i2c, LL_I2C_DMA_REG_DATA_RECEIVE), + (uint32_t)msg->buf, msg, &data->dma_rx_sem, + "RX") != 0) { + return; + } + data->current.buf += msg->len; + data->current.len -= msg->len; + LL_I2C_EnableDMAReq_RX(i2c); + } else { + // Preload the TX register for the first byte + + LL_I2C_TransmitData8(i2c, *data->current.buf); + data->current.buf++; + data->current.len--; + + if (msg->len) { + // Configure TX DMA + if (configure_dma( + cfg->dev_dma_tx, cfg->dma_tx_channel, + &data->dma_tx_cfg, &data->dma_tx_blk_cfg, + (uint32_t)msg->buf, + LL_I2C_DMA_GetRegAddr( + cfg->i2c, LL_I2C_DMA_REG_DATA_TRANSMIT), + msg, &data->dma_tx_sem, "TX") != 0) { + return; + } + data->current.buf += msg->len; + data->current.len -= msg->len; + LL_I2C_EnableDMAReq_TX(i2c); + } + } + } +#endif + LL_I2C_Enable(i2c); LL_I2C_GenerateStartCondition(i2c); @@ -209,6 +287,19 @@ static void stm32_i2c_master_mode_end(const struct device *dev) LL_I2C_Disable(i2c); } #endif + +#ifdef CONFIG_I2C_DMA + if (data->current.msg->flags & I2C_MSG_READ) { + dma_stop(cfg->dev_dma_rx, cfg->dma_rx_channel); + k_sem_give(&data->dma_rx_sem); + LL_I2C_DisableDMAReq_RX(i2c); + } else { + dma_stop(cfg->dev_dma_tx, cfg->dma_tx_channel); + k_sem_give(&data->dma_tx_sem); + LL_I2C_DisableDMAReq_TX(i2c); + } +#endif + k_sem_give(&data->device_sync_sem); } @@ -508,6 +599,19 @@ static void stm32_i2c_event(const struct device *dev) LL_I2C_GenerateStopCondition(i2c); } else { stm32_i2c_disable_transfer_interrupts(dev); + +#ifdef CONFIG_I2C_DMA + if (data->current.msg->flags & I2C_MSG_READ) { + dma_stop(cfg->dev_dma_rx, cfg->dma_rx_channel); + k_sem_give(&data->dma_rx_sem); + LL_I2C_DisableDMAReq_RX(i2c); + } else { + dma_stop(cfg->dev_dma_tx, cfg->dma_tx_channel); + k_sem_give(&data->dma_tx_sem); + LL_I2C_DisableDMAReq_TX(i2c); + } +#endif + k_sem_give(&data->device_sync_sem); } } From b394ecb6a5e2def3deec573cbd9aa2378b686c2c Mon Sep 17 00:00:00 2001 From: Simon Gilbert Date: Mon, 25 Nov 2024 09:25:59 +0000 Subject: [PATCH 08/11] i2c: stm32: Clang format Clang format Signed-off-by: Simon Gilbert --- drivers/i2c/i2c_ll_stm32.c | 263 ++++++++++++------------ drivers/i2c/i2c_ll_stm32_v2.c | 371 ++++++++++++++++------------------ 2 files changed, 297 insertions(+), 337 deletions(-) diff --git a/drivers/i2c/i2c_ll_stm32.c b/drivers/i2c/i2c_ll_stm32.c index 9f201861dda0db..8db5a94ae17440 100644 --- a/drivers/i2c/i2c_ll_stm32.c +++ b/drivers/i2c/i2c_ll_stm32.c @@ -65,16 +65,13 @@ int i2c_stm32_get_config(const struct device *dev, uint32_t *config) /* I2C BIT RATE */ if (data->current_timing.i2c_speed == 100000) { LOG_INF("timings = <%d I2C_BITRATE_STANDARD 0x%X>;", - data->current_timing.periph_clock, - data->current_timing.timing_setting); + data->current_timing.periph_clock, data->current_timing.timing_setting); } else if (data->current_timing.i2c_speed == 400000) { - LOG_INF("timings = <%d I2C_BITRATE_FAST 0x%X>;", - data->current_timing.periph_clock, + LOG_INF("timings = <%d I2C_BITRATE_FAST 0x%X>;", data->current_timing.periph_clock, data->current_timing.timing_setting); } else if (data->current_timing.i2c_speed == 1000000) { LOG_INF("timings = <%d I2C_SPEED_FAST_PLUS 0x%X>;", - data->current_timing.periph_clock, - data->current_timing.timing_setting); + data->current_timing.periph_clock, data->current_timing.timing_setting); } #endif /* CONFIG_I2C_STM32_V2_TIMING */ @@ -139,10 +136,10 @@ int i2c_stm32_runtime_configure(const struct device *dev, uint32_t config) return ret; } -#define OPERATION(msg) (((struct i2c_msg *) msg)->flags & I2C_MSG_RW_MASK) +#define OPERATION(msg) (((struct i2c_msg *)msg)->flags & I2C_MSG_RW_MASK) -static int i2c_stm32_transfer(const struct device *dev, struct i2c_msg *msg, - uint8_t num_msgs, uint16_t slave) +static int i2c_stm32_transfer(const struct device *dev, struct i2c_msg *msg, uint8_t num_msgs, + uint16_t slave) { struct i2c_stm32_data *data = dev->data; struct i2c_msg *current; @@ -372,8 +369,7 @@ static int i2c_stm32_activate(const struct device *dev) } /* Enable device clock. */ - if (clock_control_on(clk, - (clock_control_subsys_t) &cfg->pclken[0]) != 0) { + if (clock_control_on(clk, (clock_control_subsys_t)&cfg->pclken[0]) != 0) { LOG_ERR("i2c: failure enabling clock"); return -EIO; } @@ -381,7 +377,6 @@ static int i2c_stm32_activate(const struct device *dev) return 0; } - static int i2c_stm32_init(const struct device *dev) { const struct device *const clk = DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE); @@ -418,9 +413,7 @@ static int i2c_stm32_init(const struct device *dev) if (IS_ENABLED(STM32_I2C_DOMAIN_CLOCK_SUPPORT) && (cfg->pclk_len > 1)) { /* Enable I2C clock source */ - ret = clock_control_configure(clk, - (clock_control_subsys_t) &cfg->pclken[1], - NULL); + ret = clock_control_configure(clk, (clock_control_subsys_t)&cfg->pclken[1], NULL); if (ret < 0) { return -EIO; } @@ -545,46 +538,46 @@ void i2c_stm32_smbalert_disable(const struct device *dev) #ifdef CONFIG_I2C_DMA /* This function is executed in the interrupt context */ -static void dma_rx_callback(const struct device *dma_dev, void *user_data, - uint32_t channel, int status) +static void dma_rx_callback(const struct device *dma_dev, void *user_data, uint32_t channel, + int status) { - struct i2c_stm32_data *data = (struct i2c_stm32_data *)user_data; - - switch (status) { - case DMA_STATUS_COMPLETE: - data->current.is_err = 0; - dma_stop(dma_dev, channel); - break; - case DMA_STATUS_BLOCK: - break; - default: - data->current.is_err = 1; - break; - } - - k_sem_give(&data->device_sync_sem); + struct i2c_stm32_data *data = (struct i2c_stm32_data *)user_data; + + switch (status) { + case DMA_STATUS_COMPLETE: + data->current.is_err = 0; + dma_stop(dma_dev, channel); + break; + case DMA_STATUS_BLOCK: + break; + default: + data->current.is_err = 1; + break; + } + + k_sem_give(&data->device_sync_sem); } /* This function is executed in the interrupt context */ -static void dma_tx_callback(const struct device *dma_dev, void *user_data, - uint32_t channel, int status) +static void dma_tx_callback(const struct device *dma_dev, void *user_data, uint32_t channel, + int status) { - struct i2c_stm32_data *data = (struct i2c_stm32_data *)user_data; - - switch (status) { - case DMA_STATUS_COMPLETE: - data->current.is_err = 0; - dma_stop(dma_dev, channel); - break; - case DMA_STATUS_BLOCK: - break; - default: - data->current.is_err = 1; - break; - } - - LOG_DBG("Giving semaphore"); - k_sem_give(&data->device_sync_sem); + struct i2c_stm32_data *data = (struct i2c_stm32_data *)user_data; + + switch (status) { + case DMA_STATUS_COMPLETE: + data->current.is_err = 0; + dma_stop(dma_dev, channel); + break; + case DMA_STATUS_BLOCK: + break; + default: + data->current.is_err = 1; + break; + } + + LOG_DBG("Giving semaphore"); + k_sem_give(&data->device_sync_sem); } #endif /* CONFIG_I2C_DMA */ @@ -594,40 +587,35 @@ static void dma_tx_callback(const struct device *dma_dev, void *user_data, #ifdef CONFIG_I2C_STM32_INTERRUPT #ifdef CONFIG_I2C_STM32_COMBINED_INTERRUPT -#define STM32_I2C_IRQ_CONNECT_AND_ENABLE(index) \ - do { \ - IRQ_CONNECT(DT_INST_IRQN(index), \ - DT_INST_IRQ(index, priority), \ - stm32_i2c_combined_isr, \ - DEVICE_DT_INST_GET(index), 0); \ - irq_enable(DT_INST_IRQN(index)); \ +#define STM32_I2C_IRQ_CONNECT_AND_ENABLE(index) \ + do { \ + IRQ_CONNECT(DT_INST_IRQN(index), DT_INST_IRQ(index, priority), \ + stm32_i2c_combined_isr, DEVICE_DT_INST_GET(index), 0); \ + irq_enable(DT_INST_IRQN(index)); \ } while (false) #else -#define STM32_I2C_IRQ_CONNECT_AND_ENABLE(index) \ - do { \ - IRQ_CONNECT(DT_INST_IRQ_BY_NAME(index, event, irq), \ - DT_INST_IRQ_BY_NAME(index, event, priority),\ - stm32_i2c_event_isr, \ - DEVICE_DT_INST_GET(index), 0); \ - irq_enable(DT_INST_IRQ_BY_NAME(index, event, irq)); \ - \ - IRQ_CONNECT(DT_INST_IRQ_BY_NAME(index, error, irq), \ - DT_INST_IRQ_BY_NAME(index, error, priority),\ - stm32_i2c_error_isr, \ - DEVICE_DT_INST_GET(index), 0); \ - irq_enable(DT_INST_IRQ_BY_NAME(index, error, irq)); \ +#define STM32_I2C_IRQ_CONNECT_AND_ENABLE(index) \ + do { \ + IRQ_CONNECT(DT_INST_IRQ_BY_NAME(index, event, irq), \ + DT_INST_IRQ_BY_NAME(index, event, priority), stm32_i2c_event_isr, \ + DEVICE_DT_INST_GET(index), 0); \ + irq_enable(DT_INST_IRQ_BY_NAME(index, event, irq)); \ + \ + IRQ_CONNECT(DT_INST_IRQ_BY_NAME(index, error, irq), \ + DT_INST_IRQ_BY_NAME(index, error, priority), stm32_i2c_error_isr, \ + DEVICE_DT_INST_GET(index), 0); \ + irq_enable(DT_INST_IRQ_BY_NAME(index, error, irq)); \ } while (false) #endif /* CONFIG_I2C_STM32_COMBINED_INTERRUPT */ -#define STM32_I2C_IRQ_HANDLER_DECL(index) \ -static void i2c_stm32_irq_config_func_##index(const struct device *dev) -#define STM32_I2C_IRQ_HANDLER_FUNCTION(index) \ - .irq_config_func = i2c_stm32_irq_config_func_##index, -#define STM32_I2C_IRQ_HANDLER(index) \ -static void i2c_stm32_irq_config_func_##index(const struct device *dev) \ -{ \ - STM32_I2C_IRQ_CONNECT_AND_ENABLE(index); \ -} +#define STM32_I2C_IRQ_HANDLER_DECL(index) \ + static void i2c_stm32_irq_config_func_##index(const struct device *dev) +#define STM32_I2C_IRQ_HANDLER_FUNCTION(index) .irq_config_func = i2c_stm32_irq_config_func_##index, +#define STM32_I2C_IRQ_HANDLER(index) \ + static void i2c_stm32_irq_config_func_##index(const struct device *dev) \ + { \ + STM32_I2C_IRQ_CONNECT_AND_ENABLE(index); \ + } #else #define STM32_I2C_IRQ_HANDLER_DECL(index) @@ -639,32 +627,35 @@ static void i2c_stm32_irq_config_func_##index(const struct device *dev) \ #ifdef CONFIG_I2C_DMA #define I2C_DMA_INIT(index, dir) \ - .dev_dma_##dir = COND_CODE_1(DT_INST_DMAS_HAS_NAME(index, dir), \ - (DEVICE_DT_GET(STM32_DMA_CTLR(index, dir))), (NULL)), \ - .dma_##dir##_channel = COND_CODE_1(DT_INST_DMAS_HAS_NAME(index, dir), \ + .dev_dma_##dir = COND_CODE_1(DT_INST_DMAS_HAS_NAME(index, dir), \ + (DEVICE_DT_GET(STM32_DMA_CTLR(index, dir))), (NULL)), \ + .dma_##dir##_channel = COND_CODE_1(DT_INST_DMAS_HAS_NAME(index, dir), \ (DT_INST_DMAS_CELL_BY_NAME(index, dir, channel)), (-1)), #define I2C_DMA_SLOT_INIT(index, dir) \ - .dma_slot = COND_CODE_1(DT_INST_DMAS_HAS_NAME(index, dir), \ + .dma_slot = COND_CODE_1(DT_INST_DMAS_HAS_NAME(index, dir), \ (DT_INST_DMAS_CELL_BY_NAME(index, dir, slot)), (0)) #define I2C_DMA_CFG_INIT(index, name, dir, src, dest, src_addr_incr, dest_addr_incr) \ -.dma_##dir##_cfg = { \ - I2C_DMA_SLOT_INIT(index, dir), \ - .channel_direction = STM32_DMA_CONFIG_DIRECTION(STM32_DMA_CHANNEL_CONFIG(index, dir)), \ - .source_data_size = STM32_DMA_CONFIG_##src##_DATA_SIZE( \ - STM32_DMA_CHANNEL_CONFIG(index, dir)), \ - .dest_data_size = STM32_DMA_CONFIG_##dest##_DATA_SIZE( \ - STM32_DMA_CHANNEL_CONFIG(index, dir)), \ - .source_burst_length = 1, \ - .dest_burst_length = 1, \ - .channel_priority = STM32_DMA_CONFIG_PRIORITY(STM32_DMA_CHANNEL_CONFIG(index, dir)), \ - .dma_callback = dma_##dir##_callback, \ -}, \ -.dma_##dir##_blk_cfg = { \ - .source_addr_adj = src_addr_incr, \ - .dest_addr_adj = dest_addr_incr, \ -}, + .dma_##dir##_cfg = \ + { \ + I2C_DMA_SLOT_INIT(index, dir), \ + .channel_direction = \ + STM32_DMA_CONFIG_DIRECTION(STM32_DMA_CHANNEL_CONFIG(index, dir)), \ + .source_data_size = STM32_DMA_CONFIG_##src##_DATA_SIZE( \ + STM32_DMA_CHANNEL_CONFIG(index, dir)), \ + .dest_data_size = STM32_DMA_CONFIG_##dest##_DATA_SIZE( \ + STM32_DMA_CHANNEL_CONFIG(index, dir)), \ + .source_burst_length = 1, \ + .dest_burst_length = 1, \ + .channel_priority = \ + STM32_DMA_CONFIG_PRIORITY(STM32_DMA_CHANNEL_CONFIG(index, dir)), \ + .dma_callback = dma_##dir##_callback, \ + }, \ + .dma_##dir##_blk_cfg = { \ + .source_addr_adj = src_addr_incr, \ + .dest_addr_adj = dest_addr_incr, \ + }, #else @@ -676,46 +667,42 @@ static void i2c_stm32_irq_config_func_##index(const struct device *dev) \ #endif -#define STM32_I2C_INIT(index) \ -STM32_I2C_IRQ_HANDLER_DECL(index); \ - \ -IF_ENABLED(DT_HAS_COMPAT_STATUS_OKAY(st_stm32_i2c_v2), \ - (static const uint32_t i2c_timings_##index[] = \ - DT_INST_PROP_OR(index, timings, {});)) \ - \ -PINCTRL_DT_INST_DEFINE(index); \ - \ -static const struct stm32_pclken pclken_##index[] = \ - STM32_DT_INST_CLOCKS(index); \ - \ -static const struct i2c_stm32_config i2c_stm32_cfg_##index = { \ - .i2c = (I2C_TypeDef *)DT_INST_REG_ADDR(index), \ - .pclken = pclken_##index, \ - .pclk_len = DT_INST_NUM_CLOCKS(index), \ - STM32_I2C_IRQ_HANDLER_FUNCTION(index) \ - .bitrate = DT_INST_PROP(index, clock_frequency), \ - .pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(index), \ - IF_ENABLED(CONFIG_I2C_STM32_BUS_RECOVERY, \ +#define STM32_I2C_INIT(index) \ + STM32_I2C_IRQ_HANDLER_DECL(index); \ + \ + IF_ENABLED(DT_HAS_COMPAT_STATUS_OKAY(st_stm32_i2c_v2), \ + (static const uint32_t i2c_timings_##index[] = \ + DT_INST_PROP_OR(index, timings, {});)) \ + \ + PINCTRL_DT_INST_DEFINE(index); \ + \ + static const struct stm32_pclken pclken_##index[] = STM32_DT_INST_CLOCKS(index); \ + \ + static const struct i2c_stm32_config i2c_stm32_cfg_##index = { \ + .i2c = (I2C_TypeDef *)DT_INST_REG_ADDR(index), \ + .pclken = pclken_##index, \ + .pclk_len = DT_INST_NUM_CLOCKS(index), \ + STM32_I2C_IRQ_HANDLER_FUNCTION(index).bitrate = \ + DT_INST_PROP(index, clock_frequency), \ + .pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(index), \ + IF_ENABLED(CONFIG_I2C_STM32_BUS_RECOVERY, \ (.scl = GPIO_DT_SPEC_INST_GET_OR(index, scl_gpios, {0}),\ - .sda = GPIO_DT_SPEC_INST_GET_OR(index, sda_gpios, {0}),))\ - IF_ENABLED(DT_HAS_COMPAT_STATUS_OKAY(st_stm32_i2c_v2), \ + .sda = GPIO_DT_SPEC_INST_GET_OR(index, sda_gpios, {0}),)) \ + IF_ENABLED(DT_HAS_COMPAT_STATUS_OKAY(st_stm32_i2c_v2), \ (.timings = (const struct i2c_config_timing *) i2c_timings_##index,\ - .n_timings = ARRAY_SIZE(i2c_timings_##index),)) \ - I2C_DMA_INIT(index, tx) \ - I2C_DMA_INIT(index, rx) \ -}; \ - \ -static struct i2c_stm32_data i2c_stm32_dev_data_##index; \ - \ -PM_DEVICE_DT_INST_DEFINE(index, i2c_stm32_pm_action); \ - \ -I2C_DEVICE_DT_INST_DEFINE(index, i2c_stm32_init, \ - PM_DEVICE_DT_INST_GET(index), \ - &i2c_stm32_dev_data_##index, \ - &i2c_stm32_cfg_##index, \ - POST_KERNEL, CONFIG_I2C_INIT_PRIORITY, \ - &api_funcs); \ - \ -STM32_I2C_IRQ_HANDLER(index) + .n_timings = ARRAY_SIZE(i2c_timings_##index),)) \ + I2C_DMA_INIT(index, tx) \ + I2C_DMA_INIT(index, \ + rx)}; \ + \ + static struct i2c_stm32_data i2c_stm32_dev_data_##index; \ + \ + PM_DEVICE_DT_INST_DEFINE(index, i2c_stm32_pm_action); \ + \ + I2C_DEVICE_DT_INST_DEFINE(index, i2c_stm32_init, PM_DEVICE_DT_INST_GET(index), \ + &i2c_stm32_dev_data_##index, &i2c_stm32_cfg_##index, \ + POST_KERNEL, CONFIG_I2C_INIT_PRIORITY, &api_funcs); \ + \ + STM32_I2C_IRQ_HANDLER(index) DT_INST_FOREACH_STATUS_OKAY(STM32_I2C_INIT) diff --git a/drivers/i2c/i2c_ll_stm32_v2.c b/drivers/i2c/i2c_ll_stm32_v2.c index 0dbd6ed1873d83..1a915120c433e4 100644 --- a/drivers/i2c/i2c_ll_stm32_v2.c +++ b/drivers/i2c/i2c_ll_stm32_v2.c @@ -27,90 +27,93 @@ LOG_MODULE_REGISTER(i2c_ll_stm32_v2); #include "i2c-priv.h" -#define STM32_I2C_TRANSFER_TIMEOUT_MSEC 500 +#define STM32_I2C_TRANSFER_TIMEOUT_MSEC 500 #ifdef CONFIG_I2C_STM32_V2_TIMING /* Use the algorithm to calcuate the I2C timing */ #ifndef STM32_I2C_VALID_TIMING_NBR -#define STM32_I2C_VALID_TIMING_NBR 128U +#define STM32_I2C_VALID_TIMING_NBR 128U #endif -#define STM32_I2C_SPEED_FREQ_STANDARD 0U /* 100 kHz */ -#define STM32_I2C_SPEED_FREQ_FAST 1U /* 400 kHz */ -#define STM32_I2C_SPEED_FREQ_FAST_PLUS 2U /* 1 MHz */ -#define STM32_I2C_ANALOG_FILTER_DELAY_MIN 50U /* ns */ -#define STM32_I2C_ANALOG_FILTER_DELAY_MAX 260U /* ns */ -#define STM32_I2C_USE_ANALOG_FILTER 1U -#define STM32_I2C_DIGITAL_FILTER_COEF 0U -#define STM32_I2C_PRESC_MAX 16U -#define STM32_I2C_SCLDEL_MAX 16U -#define STM32_I2C_SDADEL_MAX 16U -#define STM32_I2C_SCLH_MAX 256U -#define STM32_I2C_SCLL_MAX 256U +#define STM32_I2C_SPEED_FREQ_STANDARD 0U /* 100 kHz */ +#define STM32_I2C_SPEED_FREQ_FAST 1U /* 400 kHz */ +#define STM32_I2C_SPEED_FREQ_FAST_PLUS 2U /* 1 MHz */ +#define STM32_I2C_ANALOG_FILTER_DELAY_MIN 50U /* ns */ +#define STM32_I2C_ANALOG_FILTER_DELAY_MAX 260U /* ns */ +#define STM32_I2C_USE_ANALOG_FILTER 1U +#define STM32_I2C_DIGITAL_FILTER_COEF 0U +#define STM32_I2C_PRESC_MAX 16U +#define STM32_I2C_SCLDEL_MAX 16U +#define STM32_I2C_SDADEL_MAX 16U +#define STM32_I2C_SCLH_MAX 256U +#define STM32_I2C_SCLL_MAX 256U /* I2C_DEVICE_Private_Types */ struct stm32_i2c_charac_t { - uint32_t freq; /* Frequency in Hz */ - uint32_t freq_min; /* Minimum frequency in Hz */ - uint32_t freq_max; /* Maximum frequency in Hz */ - uint32_t hddat_min; /* Minimum data hold time in ns */ - uint32_t vddat_max; /* Maximum data valid time in ns */ - uint32_t sudat_min; /* Minimum data setup time in ns */ - uint32_t lscl_min; /* Minimum low period of the SCL clock in ns */ - uint32_t hscl_min; /* Minimum high period of SCL clock in ns */ - uint32_t trise; /* Rise time in ns */ - uint32_t tfall; /* Fall time in ns */ - uint32_t dnf; /* Digital noise filter coefficient */ + uint32_t freq; /* Frequency in Hz */ + uint32_t freq_min; /* Minimum frequency in Hz */ + uint32_t freq_max; /* Maximum frequency in Hz */ + uint32_t hddat_min; /* Minimum data hold time in ns */ + uint32_t vddat_max; /* Maximum data valid time in ns */ + uint32_t sudat_min; /* Minimum data setup time in ns */ + uint32_t lscl_min; /* Minimum low period of the SCL clock in ns */ + uint32_t hscl_min; /* Minimum high period of SCL clock in ns */ + uint32_t trise; /* Rise time in ns */ + uint32_t tfall; /* Fall time in ns */ + uint32_t dnf; /* Digital noise filter coefficient */ }; struct stm32_i2c_timings_t { - uint32_t presc; /* Timing prescaler */ - uint32_t tscldel; /* SCL delay */ - uint32_t tsdadel; /* SDA delay */ - uint32_t sclh; /* SCL high period */ - uint32_t scll; /* SCL low period */ + uint32_t presc; /* Timing prescaler */ + uint32_t tscldel; /* SCL delay */ + uint32_t tsdadel; /* SDA delay */ + uint32_t sclh; /* SCL high period */ + uint32_t scll; /* SCL low period */ }; /* I2C_DEVICE Private Constants */ static const struct stm32_i2c_charac_t stm32_i2c_charac[] = { - [STM32_I2C_SPEED_FREQ_STANDARD] = { - .freq = 100000, - .freq_min = 80000, - .freq_max = 120000, - .hddat_min = 0, - .vddat_max = 3450, - .sudat_min = 250, - .lscl_min = 4700, - .hscl_min = 4000, - .trise = 640, - .tfall = 20, - .dnf = STM32_I2C_DIGITAL_FILTER_COEF, - }, - [STM32_I2C_SPEED_FREQ_FAST] = { - .freq = 400000, - .freq_min = 320000, - .freq_max = 480000, - .hddat_min = 0, - .vddat_max = 900, - .sudat_min = 100, - .lscl_min = 1300, - .hscl_min = 600, - .trise = 250, - .tfall = 100, - .dnf = STM32_I2C_DIGITAL_FILTER_COEF, - }, - [STM32_I2C_SPEED_FREQ_FAST_PLUS] = { - .freq = 1000000, - .freq_min = 800000, - .freq_max = 1200000, - .hddat_min = 0, - .vddat_max = 450, - .sudat_min = 50, - .lscl_min = 500, - .hscl_min = 260, - .trise = 60, - .tfall = 100, - .dnf = STM32_I2C_DIGITAL_FILTER_COEF, - }, + [STM32_I2C_SPEED_FREQ_STANDARD] = + { + .freq = 100000, + .freq_min = 80000, + .freq_max = 120000, + .hddat_min = 0, + .vddat_max = 3450, + .sudat_min = 250, + .lscl_min = 4700, + .hscl_min = 4000, + .trise = 640, + .tfall = 20, + .dnf = STM32_I2C_DIGITAL_FILTER_COEF, + }, + [STM32_I2C_SPEED_FREQ_FAST] = + { + .freq = 400000, + .freq_min = 320000, + .freq_max = 480000, + .hddat_min = 0, + .vddat_max = 900, + .sudat_min = 100, + .lscl_min = 1300, + .hscl_min = 600, + .trise = 250, + .tfall = 100, + .dnf = STM32_I2C_DIGITAL_FILTER_COEF, + }, + [STM32_I2C_SPEED_FREQ_FAST_PLUS] = + { + .freq = 1000000, + .freq_min = 800000, + .freq_max = 1200000, + .hddat_min = 0, + .vddat_max = 450, + .sudat_min = 50, + .lscl_min = 500, + .hscl_min = 260, + .trise = 60, + .tfall = 100, + .dnf = STM32_I2C_DIGITAL_FILTER_COEF, + }, }; static struct stm32_i2c_timings_t i2c_valid_timing[STM32_I2C_VALID_TIMING_NBR]; @@ -153,9 +156,8 @@ static int configure_dma(const struct device *dma_dev, uint32_t dma_channel, } #endif -static inline void msg_init(const struct device *dev, struct i2c_msg *msg, - uint8_t *next_msg_flags, uint16_t slave, - uint32_t transfer) +static inline void msg_init(const struct device *dev, struct i2c_msg *msg, uint8_t *next_msg_flags, + uint16_t slave, uint32_t transfer) { const struct i2c_stm32_config *cfg = dev->config; struct i2c_stm32_data *data = dev->data; @@ -165,13 +167,11 @@ static inline void msg_init(const struct device *dev, struct i2c_msg *msg, LL_I2C_SetTransferSize(i2c, msg->len); } else { if (I2C_ADDR_10_BITS & data->dev_config) { - LL_I2C_SetMasterAddressingMode(i2c, - LL_I2C_ADDRESSING_MODE_10BIT); - LL_I2C_SetSlaveAddr(i2c, (uint32_t) slave); + LL_I2C_SetMasterAddressingMode(i2c, LL_I2C_ADDRESSING_MODE_10BIT); + LL_I2C_SetSlaveAddr(i2c, (uint32_t)slave); } else { - LL_I2C_SetMasterAddressingMode(i2c, - LL_I2C_ADDRESSING_MODE_7BIT); - LL_I2C_SetSlaveAddr(i2c, (uint32_t) slave << 1); + LL_I2C_SetMasterAddressingMode(i2c, LL_I2C_ADDRESSING_MODE_7BIT); + LL_I2C_SetSlaveAddr(i2c, (uint32_t)slave << 1); } if (!(msg->flags & I2C_MSG_STOP) && next_msg_flags && @@ -317,11 +317,9 @@ static void stm32_i2c_slave_event(const struct device *dev) /* Choose the right slave from the address match code */ slave_address = LL_I2C_GetAddressMatchCode(i2c) >> 1; - if (data->slave_cfg != NULL && - slave_address == data->slave_cfg->address) { + if (data->slave_cfg != NULL && slave_address == data->slave_cfg->address) { slave_cfg = data->slave_cfg; - } else if (data->slave2_cfg != NULL && - slave_address == data->slave2_cfg->address) { + } else if (data->slave2_cfg != NULL && slave_address == data->slave2_cfg->address) { slave_cfg = data->slave2_cfg; } else { __ASSERT_NO_MSG(0); @@ -408,8 +406,7 @@ static void stm32_i2c_slave_event(const struct device *dev) } /* Attach and start I2C as target */ -int i2c_stm32_target_register(const struct device *dev, - struct i2c_target_config *config) +int i2c_stm32_target_register(const struct device *dev, struct i2c_target_config *config) { const struct i2c_stm32_config *cfg = dev->config; struct i2c_stm32_data *data = dev->data; @@ -451,7 +448,7 @@ int i2c_stm32_target_register(const struct device *dev, if (!data->slave_cfg) { data->slave_cfg = config; - if (data->slave_cfg->flags == I2C_TARGET_FLAGS_ADDR_10_BITS) { + if (data->slave_cfg->flags == I2C_TARGET_FLAGS_ADDR_10_BITS) { LL_I2C_SetOwnAddress1(i2c, config->address, LL_I2C_OWNADDRESS1_10BIT); LOG_DBG("i2c: target #1 registered with 10-bit address"); } else { @@ -465,11 +462,10 @@ int i2c_stm32_target_register(const struct device *dev, } else { data->slave2_cfg = config; - if (data->slave2_cfg->flags == I2C_TARGET_FLAGS_ADDR_10_BITS) { + if (data->slave2_cfg->flags == I2C_TARGET_FLAGS_ADDR_10_BITS) { return -EINVAL; } - LL_I2C_SetOwnAddress2(i2c, config->address << 1U, - LL_I2C_OWNADDRESS2_NOMASK); + LL_I2C_SetOwnAddress2(i2c, config->address << 1U, LL_I2C_OWNADDRESS2_NOMASK); LL_I2C_EnableOwnAddress2(i2c); LOG_DBG("i2c: target #2 registered"); } @@ -481,8 +477,7 @@ int i2c_stm32_target_register(const struct device *dev, return 0; } -int i2c_stm32_target_unregister(const struct device *dev, - struct i2c_target_config *config) +int i2c_stm32_target_unregister(const struct device *dev, struct i2c_target_config *config) { const struct i2c_stm32_config *cfg = dev->config; struct i2c_stm32_data *data = dev->data; @@ -512,7 +507,7 @@ int i2c_stm32_target_unregister(const struct device *dev, /* Return if there is a slave remaining */ if (data->slave_cfg || data->slave2_cfg) { - LOG_DBG("i2c: target#%c still registered", data->slave_cfg?'1':'2'); + LOG_DBG("i2c: target#%c still registered", data->slave_cfg ? '1' : '2'); return 0; } @@ -592,8 +587,7 @@ static void stm32_i2c_event(const struct device *dev) } /* Transfer Complete or Transfer Complete Reload */ - if (LL_I2C_IsActiveFlag_TC(i2c) || - LL_I2C_IsActiveFlag_TCR(i2c)) { + if (LL_I2C_IsActiveFlag_TC(i2c) || LL_I2C_IsActiveFlag_TCR(i2c)) { /* Issue stop condition if necessary */ if (data->current.msg->flags & I2C_MSG_STOP) { LL_I2C_GenerateStopCondition(i2c); @@ -665,7 +659,7 @@ static int stm32_i2c_error(const struct device *dev) #ifdef CONFIG_I2C_STM32_COMBINED_INTERRUPT void stm32_i2c_combined_isr(void *arg) { - const struct device *dev = (const struct device *) arg; + const struct device *dev = (const struct device *)arg; if (stm32_i2c_error(dev)) { return; @@ -676,21 +670,21 @@ void stm32_i2c_combined_isr(void *arg) void stm32_i2c_event_isr(void *arg) { - const struct device *dev = (const struct device *) arg; + const struct device *dev = (const struct device *)arg; stm32_i2c_event(dev); } void stm32_i2c_error_isr(void *arg) { - const struct device *dev = (const struct device *) arg; + const struct device *dev = (const struct device *)arg; stm32_i2c_error(dev); } #endif static int stm32_i2c_msg_write(const struct device *dev, struct i2c_msg *msg, - uint8_t *next_msg_flags, uint16_t slave) + uint8_t *next_msg_flags, uint16_t slave) { const struct i2c_stm32_config *cfg = dev->config; struct i2c_stm32_data *data = dev->data; @@ -709,23 +703,20 @@ static int stm32_i2c_msg_write(const struct device *dev, struct i2c_msg *msg, stm32_i2c_enable_transfer_interrupts(dev); LL_I2C_EnableIT_TX(i2c); - if (k_sem_take(&data->device_sync_sem, - K_MSEC(STM32_I2C_TRANSFER_TIMEOUT_MSEC)) != 0) { + if (k_sem_take(&data->device_sync_sem, K_MSEC(STM32_I2C_TRANSFER_TIMEOUT_MSEC)) != 0) { stm32_i2c_master_mode_end(dev); k_sem_take(&data->device_sync_sem, K_FOREVER); is_timeout = true; } - if (data->current.is_nack || data->current.is_err || - data->current.is_arlo || is_timeout) { + if (data->current.is_nack || data->current.is_err || data->current.is_arlo || is_timeout) { goto error; } return 0; error: if (data->current.is_arlo) { - LOG_DBG("%s: ARLO %d", __func__, - data->current.is_arlo); + LOG_DBG("%s: ARLO %d", __func__, data->current.is_arlo); data->current.is_arlo = 0U; } @@ -735,8 +726,7 @@ static int stm32_i2c_msg_write(const struct device *dev, struct i2c_msg *msg, } if (data->current.is_err) { - LOG_DBG("%s: ERR %d", __func__, - data->current.is_err); + LOG_DBG("%s: ERR %d", __func__, data->current.is_err); data->current.is_err = 0U; } @@ -748,7 +738,7 @@ static int stm32_i2c_msg_write(const struct device *dev, struct i2c_msg *msg, } static int stm32_i2c_msg_read(const struct device *dev, struct i2c_msg *msg, - uint8_t *next_msg_flags, uint16_t slave) + uint8_t *next_msg_flags, uint16_t slave) { const struct i2c_stm32_config *cfg = dev->config; struct i2c_stm32_data *data = dev->data; @@ -768,23 +758,20 @@ static int stm32_i2c_msg_read(const struct device *dev, struct i2c_msg *msg, stm32_i2c_enable_transfer_interrupts(dev); LL_I2C_EnableIT_RX(i2c); - if (k_sem_take(&data->device_sync_sem, - K_MSEC(STM32_I2C_TRANSFER_TIMEOUT_MSEC)) != 0) { + if (k_sem_take(&data->device_sync_sem, K_MSEC(STM32_I2C_TRANSFER_TIMEOUT_MSEC)) != 0) { stm32_i2c_master_mode_end(dev); k_sem_take(&data->device_sync_sem, K_FOREVER); is_timeout = true; } - if (data->current.is_nack || data->current.is_err || - data->current.is_arlo || is_timeout) { + if (data->current.is_nack || data->current.is_err || data->current.is_arlo || is_timeout) { goto error; } return 0; error: if (data->current.is_arlo) { - LOG_DBG("%s: ARLO %d", __func__, - data->current.is_arlo); + LOG_DBG("%s: ARLO %d", __func__, data->current.is_arlo); data->current.is_arlo = 0U; } @@ -794,8 +781,7 @@ static int stm32_i2c_msg_read(const struct device *dev, struct i2c_msg *msg, } if (data->current.is_err) { - LOG_DBG("%s: ERR %d", __func__, - data->current.is_err); + LOG_DBG("%s: ERR %d", __func__, data->current.is_err); data->current.is_err = 0U; } @@ -844,8 +830,7 @@ static inline int check_errors(const struct device *dev, const char *funcname) return -EIO; } -static inline int msg_done(const struct device *dev, - unsigned int current_msg_flags) +static inline int msg_done(const struct device *dev, unsigned int current_msg_flags) { const struct i2c_stm32_config *cfg = dev->config; I2C_TypeDef *i2c = cfg->i2c; @@ -870,7 +855,7 @@ static inline int msg_done(const struct device *dev, } static int stm32_i2c_msg_write(const struct device *dev, struct i2c_msg *msg, - uint8_t *next_msg_flags, uint16_t slave) + uint8_t *next_msg_flags, uint16_t slave) { const struct i2c_stm32_config *cfg = dev->config; I2C_TypeDef *i2c = cfg->i2c; @@ -900,7 +885,7 @@ static int stm32_i2c_msg_write(const struct device *dev, struct i2c_msg *msg, } static int stm32_i2c_msg_read(const struct device *dev, struct i2c_msg *msg, - uint8_t *next_msg_flags, uint16_t slave) + uint8_t *next_msg_flags, uint16_t slave) { const struct i2c_stm32_config *cfg = dev->config; I2C_TypeDef *i2c = cfg->i2c; @@ -932,24 +917,23 @@ static int stm32_i2c_msg_read(const struct device *dev, struct i2c_msg *msg, * "DEEP_INDENTATION: Too many leading tabs - consider code refactoring * in the i2c_compute_scll_sclh() function below */ -#define I2C_LOOP_SCLH(); \ - if ((tscl >= clk_min) && \ - (tscl <= clk_max) && \ - (tscl_h >= stm32_i2c_charac[i2c_speed].hscl_min) && \ - (ti2cclk < tscl_h)) { \ - \ - int32_t error = (int32_t)tscl - (int32_t)ti2cspeed; \ - \ - if (error < 0) { \ - error = -error; \ - } \ - \ - if ((uint32_t)error < prev_error) { \ - prev_error = (uint32_t)error; \ - i2c_valid_timing[count].scll = scll; \ - i2c_valid_timing[count].sclh = sclh; \ - ret = count; \ - } \ +#define I2C_LOOP_SCLH() \ + ; \ + if ((tscl >= clk_min) && (tscl <= clk_max) && \ + (tscl_h >= stm32_i2c_charac[i2c_speed].hscl_min) && (ti2cclk < tscl_h)) { \ + \ + int32_t error = (int32_t)tscl - (int32_t)ti2cspeed; \ + \ + if (error < 0) { \ + error = -error; \ + } \ + \ + if ((uint32_t)error < prev_error) { \ + prev_error = (uint32_t)error; \ + i2c_valid_timing[count].scll = scll; \ + i2c_valid_timing[count].sclh = sclh; \ + ret = count; \ + } \ } /* @@ -971,11 +955,9 @@ uint32_t i2c_compute_scll_sclh(uint32_t clock_src_freq, uint32_t i2c_speed) ti2cclk = (NSEC_PER_SEC + (clock_src_freq / 2U)) / clock_src_freq; ti2cspeed = (NSEC_PER_SEC + (stm32_i2c_charac[i2c_speed].freq / 2U)) / - stm32_i2c_charac[i2c_speed].freq; + stm32_i2c_charac[i2c_speed].freq; - tafdel_min = (STM32_I2C_USE_ANALOG_FILTER == 1U) ? - STM32_I2C_ANALOG_FILTER_DELAY_MIN : - 0U; + tafdel_min = (STM32_I2C_USE_ANALOG_FILTER == 1U) ? STM32_I2C_ANALOG_FILTER_DELAY_MIN : 0U; /* tDNF = DNF x tI2CCLK */ dnf_delay = stm32_i2c_charac[i2c_speed].dnf * ti2cclk; @@ -991,27 +973,27 @@ uint32_t i2c_compute_scll_sclh(uint32_t clock_src_freq, uint32_t i2c_speed) for (scll = 0; scll < STM32_I2C_SCLL_MAX; scll++) { /* tLOW(min) <= tAF(min) + tDNF + 2 x tI2CCLK + [(SCLL+1) x tPRESC ] */ - uint32_t tscl_l = tafdel_min + dnf_delay + - (2U * ti2cclk) + ((scll + 1U) * tpresc); + uint32_t tscl_l = + tafdel_min + dnf_delay + (2U * ti2cclk) + ((scll + 1U) * tpresc); /* * The I2CCLK period tI2CCLK must respect the following conditions: * tI2CCLK < (tLOW - tfilters) / 4 and tI2CCLK < tHIGH */ if ((tscl_l > stm32_i2c_charac[i2c_speed].lscl_min) && - (ti2cclk < ((tscl_l - tafdel_min - dnf_delay) / 4U))) { + (ti2cclk < ((tscl_l - tafdel_min - dnf_delay) / 4U))) { for (sclh = 0; sclh < STM32_I2C_SCLH_MAX; sclh++) { /* * tHIGH(min) <= tAF(min) + tDNF + * 2 x tI2CCLK + [(SCLH+1) x tPRESC] */ - uint32_t tscl_h = tafdel_min + dnf_delay + - (2U * ti2cclk) + ((sclh + 1U) * tpresc); + uint32_t tscl_h = tafdel_min + dnf_delay + (2U * ti2cclk) + + ((sclh + 1U) * tpresc); /* tSCL = tf + tLOW + tr + tHIGH */ - uint32_t tscl = tscl_l + - tscl_h + stm32_i2c_charac[i2c_speed].trise + - stm32_i2c_charac[i2c_speed].tfall; + uint32_t tscl = tscl_l + tscl_h + + stm32_i2c_charac[i2c_speed].trise + + stm32_i2c_charac[i2c_speed].tfall; /* get timings with the lowest clock error */ I2C_LOOP_SCLH(); @@ -1028,21 +1010,21 @@ uint32_t i2c_compute_scll_sclh(uint32_t clock_src_freq, uint32_t i2c_speed) * "DEEP_INDENTATION: Too many leading tabs - consider code refactoring * in the i2c_compute_presc_scldel_sdadel() function below */ -#define I2C_LOOP_SDADEL(); \ - \ - if ((tsdadel >= (uint32_t)tsdadel_min) && \ - (tsdadel <= (uint32_t)tsdadel_max)) { \ - if (presc != prev_presc) { \ - i2c_valid_timing[i2c_valid_timing_nbr].presc = presc; \ - i2c_valid_timing[i2c_valid_timing_nbr].tscldel = scldel; \ - i2c_valid_timing[i2c_valid_timing_nbr].tsdadel = sdadel; \ - prev_presc = presc; \ - i2c_valid_timing_nbr++; \ - \ - if (i2c_valid_timing_nbr >= STM32_I2C_VALID_TIMING_NBR) { \ - break; \ - } \ - } \ +#define I2C_LOOP_SDADEL() \ + ; \ + \ + if ((tsdadel >= (uint32_t)tsdadel_min) && (tsdadel <= (uint32_t)tsdadel_max)) { \ + if (presc != prev_presc) { \ + i2c_valid_timing[i2c_valid_timing_nbr].presc = presc; \ + i2c_valid_timing[i2c_valid_timing_nbr].tscldel = scldel; \ + i2c_valid_timing[i2c_valid_timing_nbr].tsdadel = sdadel; \ + prev_presc = presc; \ + i2c_valid_timing_nbr++; \ + \ + if (i2c_valid_timing_nbr >= STM32_I2C_VALID_TIMING_NBR) { \ + break; \ + } \ + } \ } /* @@ -1055,17 +1037,15 @@ void i2c_compute_presc_scldel_sdadel(uint32_t clock_src_freq, uint32_t i2c_speed { uint32_t prev_presc = STM32_I2C_PRESC_MAX; uint32_t ti2cclk; - int32_t tsdadel_min, tsdadel_max; - int32_t tscldel_min; + int32_t tsdadel_min, tsdadel_max; + int32_t tscldel_min; uint32_t presc, scldel, sdadel; uint32_t tafdel_min, tafdel_max; - ti2cclk = (NSEC_PER_SEC + (clock_src_freq / 2U)) / clock_src_freq; + ti2cclk = (NSEC_PER_SEC + (clock_src_freq / 2U)) / clock_src_freq; - tafdel_min = (STM32_I2C_USE_ANALOG_FILTER == 1U) ? - STM32_I2C_ANALOG_FILTER_DELAY_MIN : 0U; - tafdel_max = (STM32_I2C_USE_ANALOG_FILTER == 1U) ? - STM32_I2C_ANALOG_FILTER_DELAY_MAX : 0U; + tafdel_min = (STM32_I2C_USE_ANALOG_FILTER == 1U) ? STM32_I2C_ANALOG_FILTER_DELAY_MIN : 0U; + tafdel_max = (STM32_I2C_USE_ANALOG_FILTER == 1U) ? STM32_I2C_ANALOG_FILTER_DELAY_MAX : 0U; /* * tDNF = DNF x tI2CCLK * tPRESC = (PRESC+1) x tI2CCLK @@ -1073,20 +1053,16 @@ void i2c_compute_presc_scldel_sdadel(uint32_t clock_src_freq, uint32_t i2c_speed * SDADEL <= {tVD;DAT(max) - tr - tAF(max) - tDNF- [4 x tI2CCLK]} / {tPRESC} */ tsdadel_min = (int32_t)stm32_i2c_charac[i2c_speed].tfall + - (int32_t)stm32_i2c_charac[i2c_speed].hddat_min - - (int32_t)tafdel_min - - (int32_t)(((int32_t)stm32_i2c_charac[i2c_speed].dnf + 3) * - (int32_t)ti2cclk); + (int32_t)stm32_i2c_charac[i2c_speed].hddat_min - (int32_t)tafdel_min - + (int32_t)(((int32_t)stm32_i2c_charac[i2c_speed].dnf + 3) * (int32_t)ti2cclk); tsdadel_max = (int32_t)stm32_i2c_charac[i2c_speed].vddat_max - - (int32_t)stm32_i2c_charac[i2c_speed].trise - - (int32_t)tafdel_max - - (int32_t)(((int32_t)stm32_i2c_charac[i2c_speed].dnf + 4) * - (int32_t)ti2cclk); + (int32_t)stm32_i2c_charac[i2c_speed].trise - (int32_t)tafdel_max - + (int32_t)(((int32_t)stm32_i2c_charac[i2c_speed].dnf + 4) * (int32_t)ti2cclk); /* {[tr+ tSU;DAT(min)] / [tPRESC]} - 1 <= SCLDEL */ tscldel_min = (int32_t)stm32_i2c_charac[i2c_speed].trise + - (int32_t)stm32_i2c_charac[i2c_speed].sudat_min; + (int32_t)stm32_i2c_charac[i2c_speed].sudat_min; if (tsdadel_min <= 0) { tsdadel_min = 0; @@ -1131,18 +1107,17 @@ int stm32_i2c_configure_timing(const struct device *dev, uint32_t clock) i2c_valid_timing_nbr = 0; if ((clock != 0U) && (i2c_freq != 0U)) { - for (speed = 0 ; speed <= (uint32_t)STM32_I2C_SPEED_FREQ_FAST_PLUS ; speed++) { + for (speed = 0; speed <= (uint32_t)STM32_I2C_SPEED_FREQ_FAST_PLUS; speed++) { if ((i2c_freq >= stm32_i2c_charac[speed].freq_min) && - (i2c_freq <= stm32_i2c_charac[speed].freq_max)) { + (i2c_freq <= stm32_i2c_charac[speed].freq_max)) { i2c_compute_presc_scldel_sdadel(clock, speed); idx = i2c_compute_scll_sclh(clock, speed); if (idx < STM32_I2C_VALID_TIMING_NBR) { - timing = ((i2c_valid_timing[idx].presc & - 0x0FU) << 28) | - ((i2c_valid_timing[idx].tscldel & 0x0FU) << 20) | - ((i2c_valid_timing[idx].tsdadel & 0x0FU) << 16) | - ((i2c_valid_timing[idx].sclh & 0xFFU) << 8) | - ((i2c_valid_timing[idx].scll & 0xFFU) << 0); + timing = ((i2c_valid_timing[idx].presc & 0x0FU) << 28) | + ((i2c_valid_timing[idx].tscldel & 0x0FU) << 20) | + ((i2c_valid_timing[idx].tsdadel & 0x0FU) << 16) | + ((i2c_valid_timing[idx].sclh & 0xFFU) << 8) | + ((i2c_valid_timing[idx].scll & 0xFFU) << 0); } break; } @@ -1158,7 +1133,7 @@ int stm32_i2c_configure_timing(const struct device *dev, uint32_t clock) return 0; } -#else/* CONFIG_I2C_STM32_V2_TIMING */ +#else /* CONFIG_I2C_STM32_V2_TIMING */ int stm32_i2c_configure_timing(const struct device *dev, uint32_t clock) { @@ -1175,8 +1150,8 @@ int stm32_i2c_configure_timing(const struct device *dev, uint32_t clock) const struct i2c_config_timing *preset = &cfg->timings[i]; uint32_t speed = i2c_map_dt_bitrate(preset->i2c_speed); - if ((I2C_SPEED_GET(speed) == I2C_SPEED_GET(data->dev_config)) - && (preset->periph_clock == clock)) { + if ((I2C_SPEED_GET(speed) == I2C_SPEED_GET(data->dev_config)) && + (preset->periph_clock == clock)) { /* Found a matching periph clock and i2c speed */ LL_I2C_SetTiming(i2c, preset->timing_setting); return 0; @@ -1199,7 +1174,7 @@ int stm32_i2c_configure_timing(const struct device *dev, uint32_t clock) break; default: LOG_ERR("i2c: speed above \"fast\" requires manual timing configuration, " - "see \"timings\" property of st,stm32-i2c-v2 devicetree binding"); + "see \"timings\" property of st,stm32-i2c-v2 devicetree binding"); return -EINVAL; } @@ -1212,7 +1187,7 @@ int stm32_i2c_configure_timing(const struct device *dev, uint32_t clock) uint32_t sdadel = i2c_hold_time_min / ns_presc; uint32_t scldel = i2c_setup_time_min / ns_presc; - if ((sclh - 1) > 255 || (scll - 1) > 255) { + if ((sclh - 1) > 255 || (scll - 1) > 255) { ++presc; continue; } @@ -1222,8 +1197,8 @@ int stm32_i2c_configure_timing(const struct device *dev, uint32_t clock) continue; } - timing = __LL_I2C_CONVERT_TIMINGS(presc - 1, - scldel - 1, sdadel, sclh - 1, scll - 1); + timing = + __LL_I2C_CONVERT_TIMINGS(presc - 1, scldel - 1, sdadel, sclh - 1, scll - 1); break; } while (presc < 16); @@ -1239,9 +1214,8 @@ int stm32_i2c_configure_timing(const struct device *dev, uint32_t clock) } #endif /* CONFIG_I2C_STM32_V2_TIMING */ -int stm32_i2c_transaction(const struct device *dev, - struct i2c_msg msg, uint8_t *next_msg_flags, - uint16_t periph) +int stm32_i2c_transaction(const struct device *dev, struct i2c_msg msg, uint8_t *next_msg_flags, + uint16_t periph) { /* * Perform a I2C transaction, while taking into account the STM32 I2C V2 @@ -1257,8 +1231,7 @@ int stm32_i2c_transaction(const struct device *dev, */ const uint32_t i2c_stm32_maxchunk = 255U; const uint8_t saved_flags = msg.flags; - uint8_t combine_flags = - saved_flags & ~(I2C_MSG_STOP | I2C_MSG_RESTART); + uint8_t combine_flags = saved_flags & ~(I2C_MSG_STOP | I2C_MSG_RESTART); uint8_t *flagsp = NULL; uint32_t rest = msg.len; int ret = 0; From dee3c6e861a90824ba8b5a2c8aaf3852e815493b Mon Sep 17 00:00:00 2001 From: Simon Gilbert Date: Tue, 26 Nov 2024 17:35:59 +0000 Subject: [PATCH 09/11] i2c: stm32: Add assert catches in callbacks Add assert catches in DMA callbacks Signed-off-by: Simon Gilbert --- drivers/i2c/i2c_ll_stm32.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/i2c/i2c_ll_stm32.c b/drivers/i2c/i2c_ll_stm32.c index 8db5a94ae17440..415da67ff332c9 100644 --- a/drivers/i2c/i2c_ll_stm32.c +++ b/drivers/i2c/i2c_ll_stm32.c @@ -549,6 +549,7 @@ static void dma_rx_callback(const struct device *dma_dev, void *user_data, uint3 dma_stop(dma_dev, channel); break; case DMA_STATUS_BLOCK: + __ASSERT(false, "Unsupported feature"); break; default: data->current.is_err = 1; @@ -570,6 +571,7 @@ static void dma_tx_callback(const struct device *dma_dev, void *user_data, uint3 dma_stop(dma_dev, channel); break; case DMA_STATUS_BLOCK: + __ASSERT(false, "Unsupported feature"); break; default: data->current.is_err = 1; From 9a6a2f555b7c9bf6a22c5df4d42d3a8c142b0b73 Mon Sep 17 00:00:00 2001 From: Simon Gilbert Date: Tue, 26 Nov 2024 17:55:24 +0000 Subject: [PATCH 10/11] i2c: stm32: refactor use of DMA device config and settings use structs to pass dma device and config settings more easily Signed-off-by: Simon Gilbert --- drivers/i2c/i2c_ll_stm32.c | 8 ++-- drivers/i2c/i2c_ll_stm32.h | 13 ++++-- drivers/i2c/i2c_ll_stm32_v2.c | 75 +++++++++++++++-------------------- 3 files changed, 46 insertions(+), 50 deletions(-) diff --git a/drivers/i2c/i2c_ll_stm32.c b/drivers/i2c/i2c_ll_stm32.c index 415da67ff332c9..9a7ec08465e7d8 100644 --- a/drivers/i2c/i2c_ll_stm32.c +++ b/drivers/i2c/i2c_ll_stm32.c @@ -629,10 +629,10 @@ static void dma_tx_callback(const struct device *dma_dev, void *user_data, uint3 #ifdef CONFIG_I2C_DMA #define I2C_DMA_INIT(index, dir) \ - .dev_dma_##dir = COND_CODE_1(DT_INST_DMAS_HAS_NAME(index, dir), \ - (DEVICE_DT_GET(STM32_DMA_CTLR(index, dir))), (NULL)), \ - .dma_##dir##_channel = COND_CODE_1(DT_INST_DMAS_HAS_NAME(index, dir), \ - (DT_INST_DMAS_CELL_BY_NAME(index, dir, channel)), (-1)), + .dir##_dma = {.dev_dma = COND_CODE_1(DT_INST_DMAS_HAS_NAME(index, dir), \ + (DEVICE_DT_GET(STM32_DMA_CTLR(index, dir))), (NULL)), \ + .dma_channel = COND_CODE_1(DT_INST_DMAS_HAS_NAME(index, dir), \ + (DT_INST_DMAS_CELL_BY_NAME(index, dir, channel)), (-1))}, #define I2C_DMA_SLOT_INIT(index, dir) \ .dma_slot = COND_CODE_1(DT_INST_DMAS_HAS_NAME(index, dir), \ diff --git a/drivers/i2c/i2c_ll_stm32.h b/drivers/i2c/i2c_ll_stm32.h index 2eddd12d5ae174..d2fde00a762627 100644 --- a/drivers/i2c/i2c_ll_stm32.h +++ b/drivers/i2c/i2c_ll_stm32.h @@ -33,6 +33,13 @@ struct i2c_config_timing { }; #endif +#ifdef CONFIG_I2C_DMA +struct stream { + const struct device *dev_dma; + int32_t dma_channel; +}; +#endif /* CONFIG_I2C_DMA */ + struct i2c_stm32_config { #ifdef CONFIG_I2C_STM32_INTERRUPT irq_config_func_t irq_config_func; @@ -51,10 +58,8 @@ struct i2c_stm32_config { size_t n_timings; #endif #ifdef CONFIG_I2C_DMA - const struct device *dev_dma_tx; - int32_t dma_tx_channel; - const struct device *dev_dma_rx; - int32_t dma_rx_channel; + struct stream tx_dma; + struct stream rx_dma; #endif /* CONFIG_I2C_DMA */ }; diff --git a/drivers/i2c/i2c_ll_stm32_v2.c b/drivers/i2c/i2c_ll_stm32_v2.c index 1a915120c433e4..d768c6e24496b0 100644 --- a/drivers/i2c/i2c_ll_stm32_v2.c +++ b/drivers/i2c/i2c_ll_stm32_v2.c @@ -121,34 +121,26 @@ static uint32_t i2c_valid_timing_nbr; #endif /* CONFIG_I2C_STM32_V2_TIMING */ #ifdef CONFIG_I2C_DMA -static int configure_dma(const struct device *dma_dev, uint32_t dma_channel, - struct dma_config *dma_cfg, struct dma_block_config *blk_cfg, - uint32_t source_address, uint32_t dest_address, struct i2c_msg *msg, - struct k_sem *dma_sem, const char *direction) +static int configure_dma(struct stream const *dma, struct dma_config *dma_cfg, + struct dma_block_config *blk_cfg) { - if (!device_is_ready(dma_dev)) { - LOG_ERR("DMA device not ready for %s", direction); + if (!device_is_ready(dma->dev_dma)) { + LOG_ERR("DMA device not ready"); return -ENODEV; } - k_sem_take(dma_sem, K_FOREVER); - - blk_cfg->source_address = source_address; - blk_cfg->dest_address = dest_address; - blk_cfg->block_size = msg->len; - dma_cfg->head_block = blk_cfg; dma_cfg->block_count = 1; - int ret = dma_config(dma_dev, dma_channel, dma_cfg); + int ret = dma_config(dma->dev_dma, dma->dma_channel, dma_cfg); if (ret != 0) { - LOG_ERR("Problem setting up %s DMA: %d", direction, ret); + LOG_ERR("Problem setting up DMA: %d", ret); return ret; } - ret = dma_start(dma_dev, dma_channel); + ret = dma_start(dma->dev_dma, dma->dma_channel); if (ret != 0) { - LOG_ERR("Problem starting %s DMA: %d", direction, ret); + LOG_ERR("Problem starting DMA: %d", ret); return ret; } @@ -192,37 +184,36 @@ static inline void msg_init(const struct device *dev, struct i2c_msg *msg, uint8 if (msg->len) { if (msg->flags & I2C_MSG_READ) { // Configure RX DMA - if (configure_dma(cfg->dev_dma_rx, cfg->dma_rx_channel, - &data->dma_rx_cfg, &data->dma_rx_blk_cfg, - LL_I2C_DMA_GetRegAddr( - cfg->i2c, LL_I2C_DMA_REG_DATA_RECEIVE), - (uint32_t)msg->buf, msg, &data->dma_rx_sem, - "RX") != 0) { + k_sem_take(&data->dma_rx_sem, K_FOREVER); + data->dma_rx_blk_cfg.source_address = LL_I2C_DMA_GetRegAddr( + cfg->i2c, LL_I2C_DMA_REG_DATA_RECEIVE); + data->dma_rx_blk_cfg.dest_address = (uint32_t)msg->buf; + data->dma_rx_blk_cfg.block_size = msg->len; + + if (configure_dma(&cfg->rx_dma, &data->dma_rx_cfg, + &data->dma_rx_blk_cfg) != 0) { + k_sem_give(&data->dma_rx_sem); return; } data->current.buf += msg->len; data->current.len -= msg->len; LL_I2C_EnableDMAReq_RX(i2c); } else { - // Preload the TX register for the first byte - - LL_I2C_TransmitData8(i2c, *data->current.buf); - data->current.buf++; - data->current.len--; - - if (msg->len) { + if (data->current.len) { // Configure TX DMA - if (configure_dma( - cfg->dev_dma_tx, cfg->dma_tx_channel, - &data->dma_tx_cfg, &data->dma_tx_blk_cfg, - (uint32_t)msg->buf, - LL_I2C_DMA_GetRegAddr( - cfg->i2c, LL_I2C_DMA_REG_DATA_TRANSMIT), - msg, &data->dma_tx_sem, "TX") != 0) { + k_sem_take(&data->dma_tx_sem, K_FOREVER); + data->dma_tx_blk_cfg.source_address = + (uint32_t)data->current.buf; + data->dma_tx_blk_cfg.dest_address = LL_I2C_DMA_GetRegAddr( + cfg->i2c, LL_I2C_DMA_REG_DATA_TRANSMIT); + data->dma_tx_blk_cfg.block_size = msg->len; + if (configure_dma(&cfg->tx_dma, &data->dma_tx_cfg, + &data->dma_tx_blk_cfg) != 0) { + k_sem_give(&data->dma_tx_sem); return; } - data->current.buf += msg->len; - data->current.len -= msg->len; + data->current.buf += data->current.len; + data->current.len -= data->current.len; LL_I2C_EnableDMAReq_TX(i2c); } } @@ -290,11 +281,11 @@ static void stm32_i2c_master_mode_end(const struct device *dev) #ifdef CONFIG_I2C_DMA if (data->current.msg->flags & I2C_MSG_READ) { - dma_stop(cfg->dev_dma_rx, cfg->dma_rx_channel); + dma_stop(cfg->rx_dma.dev_dma, cfg->rx_dma.dma_channel); k_sem_give(&data->dma_rx_sem); LL_I2C_DisableDMAReq_RX(i2c); } else { - dma_stop(cfg->dev_dma_tx, cfg->dma_tx_channel); + dma_stop(cfg->tx_dma.dev_dma, cfg->tx_dma.dma_channel); k_sem_give(&data->dma_tx_sem); LL_I2C_DisableDMAReq_TX(i2c); } @@ -596,11 +587,11 @@ static void stm32_i2c_event(const struct device *dev) #ifdef CONFIG_I2C_DMA if (data->current.msg->flags & I2C_MSG_READ) { - dma_stop(cfg->dev_dma_rx, cfg->dma_rx_channel); + dma_stop(cfg->rx_dma.dev_dma, cfg->rx_dma.dma_channel); k_sem_give(&data->dma_rx_sem); LL_I2C_DisableDMAReq_RX(i2c); } else { - dma_stop(cfg->dev_dma_tx, cfg->dma_tx_channel); + dma_stop(cfg->tx_dma.dev_dma, cfg->tx_dma.dma_channel); k_sem_give(&data->dma_tx_sem); LL_I2C_DisableDMAReq_TX(i2c); } From 8c030eab0b74261cb36b80e5477f86705edd259b Mon Sep 17 00:00:00 2001 From: Simon Gilbert Date: Wed, 27 Nov 2024 09:00:11 +0000 Subject: [PATCH 11/11] i2c: stm32: Clang format Second pass at applying Clang Format Signed-off-by: Simon Gilbert --- drivers/i2c/i2c_ll_stm32.c | 80 +++++++++++++++++------------------ drivers/i2c/i2c_ll_stm32_v2.c | 6 ++- 2 files changed, 44 insertions(+), 42 deletions(-) diff --git a/drivers/i2c/i2c_ll_stm32.c b/drivers/i2c/i2c_ll_stm32.c index 9a7ec08465e7d8..6d0e5a86c87ee2 100644 --- a/drivers/i2c/i2c_ll_stm32.c +++ b/drivers/i2c/i2c_ll_stm32.c @@ -629,14 +629,14 @@ static void dma_tx_callback(const struct device *dma_dev, void *user_data, uint3 #ifdef CONFIG_I2C_DMA #define I2C_DMA_INIT(index, dir) \ - .dir##_dma = {.dev_dma = COND_CODE_1(DT_INST_DMAS_HAS_NAME(index, dir), \ - (DEVICE_DT_GET(STM32_DMA_CTLR(index, dir))), (NULL)), \ - .dma_channel = COND_CODE_1(DT_INST_DMAS_HAS_NAME(index, dir), \ - (DT_INST_DMAS_CELL_BY_NAME(index, dir, channel)), (-1))}, + .dir##_dma = {.dev_dma = COND_CODE_1(DT_INST_DMAS_HAS_NAME(index, dir), \ + (DEVICE_DT_GET(STM32_DMA_CTLR(index, dir))), (NULL)), \ + .dma_channel = COND_CODE_1(DT_INST_DMAS_HAS_NAME(index, dir), \ + (DT_INST_DMAS_CELL_BY_NAME(index, dir, channel)), (-1))}, #define I2C_DMA_SLOT_INIT(index, dir) \ - .dma_slot = COND_CODE_1(DT_INST_DMAS_HAS_NAME(index, dir), \ - (DT_INST_DMAS_CELL_BY_NAME(index, dir, slot)), (0)) + .dma_slot = COND_CODE_1(DT_INST_DMAS_HAS_NAME(index, dir), \ + (DT_INST_DMAS_CELL_BY_NAME(index, dir, slot)), (0)) #define I2C_DMA_CFG_INIT(index, name, dir, src, dest, src_addr_incr, dest_addr_incr) \ .dma_##dir##_cfg = \ @@ -669,42 +669,42 @@ static void dma_tx_callback(const struct device *dma_dev, void *user_data, uint3 #endif -#define STM32_I2C_INIT(index) \ - STM32_I2C_IRQ_HANDLER_DECL(index); \ - \ - IF_ENABLED(DT_HAS_COMPAT_STATUS_OKAY(st_stm32_i2c_v2), \ - (static const uint32_t i2c_timings_##index[] = \ - DT_INST_PROP_OR(index, timings, {});)) \ - \ - PINCTRL_DT_INST_DEFINE(index); \ - \ - static const struct stm32_pclken pclken_##index[] = STM32_DT_INST_CLOCKS(index); \ - \ - static const struct i2c_stm32_config i2c_stm32_cfg_##index = { \ - .i2c = (I2C_TypeDef *)DT_INST_REG_ADDR(index), \ - .pclken = pclken_##index, \ - .pclk_len = DT_INST_NUM_CLOCKS(index), \ - STM32_I2C_IRQ_HANDLER_FUNCTION(index).bitrate = \ - DT_INST_PROP(index, clock_frequency), \ - .pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(index), \ - IF_ENABLED(CONFIG_I2C_STM32_BUS_RECOVERY, \ - (.scl = GPIO_DT_SPEC_INST_GET_OR(index, scl_gpios, {0}),\ - .sda = GPIO_DT_SPEC_INST_GET_OR(index, sda_gpios, {0}),)) \ - IF_ENABLED(DT_HAS_COMPAT_STATUS_OKAY(st_stm32_i2c_v2), \ +#define STM32_I2C_INIT(index) \ + STM32_I2C_IRQ_HANDLER_DECL(index); \ + \ + IF_ENABLED(DT_HAS_COMPAT_STATUS_OKAY(st_stm32_i2c_v2), \ + (static const uint32_t i2c_timings_##index[] = \ + DT_INST_PROP_OR(index, timings, {});)) \ + \ + PINCTRL_DT_INST_DEFINE(index); \ + \ + static const struct stm32_pclken pclken_##index[] = STM32_DT_INST_CLOCKS(index); \ + \ + static const struct i2c_stm32_config i2c_stm32_cfg_##index = { \ + .i2c = (I2C_TypeDef *)DT_INST_REG_ADDR(index), \ + .pclken = pclken_##index, \ + .pclk_len = DT_INST_NUM_CLOCKS(index), \ + STM32_I2C_IRQ_HANDLER_FUNCTION(index).bitrate = \ + DT_INST_PROP(index, clock_frequency), \ + .pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(index), \ + IF_ENABLED(CONFIG_I2C_STM32_BUS_RECOVERY, \ + (.scl = GPIO_DT_SPEC_INST_GET_OR(index, scl_gpios, {0}), \ + .sda = GPIO_DT_SPEC_INST_GET_OR(index, sda_gpios, {0}),)) \ + IF_ENABLED(DT_HAS_COMPAT_STATUS_OKAY(st_stm32_i2c_v2), \ (.timings = (const struct i2c_config_timing *) i2c_timings_##index,\ .n_timings = ARRAY_SIZE(i2c_timings_##index),)) \ - I2C_DMA_INIT(index, tx) \ - I2C_DMA_INIT(index, \ - rx)}; \ - \ - static struct i2c_stm32_data i2c_stm32_dev_data_##index; \ - \ - PM_DEVICE_DT_INST_DEFINE(index, i2c_stm32_pm_action); \ - \ - I2C_DEVICE_DT_INST_DEFINE(index, i2c_stm32_init, PM_DEVICE_DT_INST_GET(index), \ - &i2c_stm32_dev_data_##index, &i2c_stm32_cfg_##index, \ - POST_KERNEL, CONFIG_I2C_INIT_PRIORITY, &api_funcs); \ - \ + I2C_DMA_INIT(index, tx) \ + I2C_DMA_INIT(index, \ + rx)}; \ + \ + static struct i2c_stm32_data i2c_stm32_dev_data_##index; \ + \ + PM_DEVICE_DT_INST_DEFINE(index, i2c_stm32_pm_action); \ + \ + I2C_DEVICE_DT_INST_DEFINE(index, i2c_stm32_init, PM_DEVICE_DT_INST_GET(index), \ + &i2c_stm32_dev_data_##index, &i2c_stm32_cfg_##index, \ + POST_KERNEL, CONFIG_I2C_INIT_PRIORITY, &api_funcs); \ + \ STM32_I2C_IRQ_HANDLER(index) DT_INST_FOREACH_STATUS_OKAY(STM32_I2C_INIT) diff --git a/drivers/i2c/i2c_ll_stm32_v2.c b/drivers/i2c/i2c_ll_stm32_v2.c index d768c6e24496b0..fcd4a65fe28b40 100644 --- a/drivers/i2c/i2c_ll_stm32_v2.c +++ b/drivers/i2c/i2c_ll_stm32_v2.c @@ -133,12 +133,14 @@ static int configure_dma(struct stream const *dma, struct dma_config *dma_cfg, dma_cfg->block_count = 1; int ret = dma_config(dma->dev_dma, dma->dma_channel, dma_cfg); + if (ret != 0) { LOG_ERR("Problem setting up DMA: %d", ret); return ret; } ret = dma_start(dma->dev_dma, dma->dma_channel); + if (ret != 0) { LOG_ERR("Problem starting DMA: %d", ret); return ret; @@ -183,7 +185,7 @@ static inline void msg_init(const struct device *dev, struct i2c_msg *msg, uint8 #ifdef CONFIG_I2C_DMA if (msg->len) { if (msg->flags & I2C_MSG_READ) { - // Configure RX DMA + /* Configure RX DMA */ k_sem_take(&data->dma_rx_sem, K_FOREVER); data->dma_rx_blk_cfg.source_address = LL_I2C_DMA_GetRegAddr( cfg->i2c, LL_I2C_DMA_REG_DATA_RECEIVE); @@ -200,7 +202,7 @@ static inline void msg_init(const struct device *dev, struct i2c_msg *msg, uint8 LL_I2C_EnableDMAReq_RX(i2c); } else { if (data->current.len) { - // Configure TX DMA + /* Configure TX DMA */ k_sem_take(&data->dma_tx_sem, K_FOREVER); data->dma_tx_blk_cfg.source_address = (uint32_t)data->current.buf;