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// Copyright (c) 2009-2011, Tor M. Aamodt, Wilson W.L. Fung, Ali Bakhoda,
// George L. Yuan, Andrew Turner, Inderpreet Singh
// The University of British Columbia
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// Redistributions of source code must retain the above copyright notice, this
// list of conditions and the following disclaimer.
// Redistributions in binary form must reproduce the above copyright notice, this
// list of conditions and the following disclaimer in the documentation and/or
// other materials provided with the distribution.
// Neither the name of The University of British Columbia nor the names of its
// contributors may be used to endorse or promote products derived from this
// software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#include <float.h>
#include "shader.h"
#include "gpu-sim.h"
#include "addrdec.h"
#include "dram.h"
#include "stat-tool.h"
#include "gpu-misc.h"
#include "../cuda-sim/ptx_sim.h"
#include "../cuda-sim/ptx-stats.h"
#include "../cuda-sim/cuda-sim.h"
#include "gpu-sim.h"
#include "mem_fetch.h"
#include "mem_latency_stat.h"
#include "visualizer.h"
#include "../intersim/statwraper.h"
#include "../intersim/interconnect_interface.h"
#include "icnt_wrapper.h"
#include <string.h>
#include <limits.h>
#define PRIORITIZE_MSHR_OVER_WB 1
#define MAX(a,b) (((a)>(b))?(a):(b))
/////////////////////////////////////////////////////////////////////////////
std::list<unsigned> shader_core_ctx::get_regs_written( const inst_t &fvt ) const
{
std::list<unsigned> result;
for( unsigned op=0; op < MAX_REG_OPERANDS; op++ ) {
int reg_num = fvt.arch_reg.dst[op]; // this math needs to match that used in function_info::ptx_decode_inst
if( reg_num >= 0 ) // valid register
result.push_back(reg_num);
}
return result;
}
shader_core_ctx::shader_core_ctx( class gpgpu_sim *gpu,
class simt_core_cluster *cluster,
unsigned shader_id,
unsigned tpc_id,
const struct shader_core_config *config,
const struct memory_config *mem_config,
shader_core_stats *stats )
: m_barriers( config->max_warps_per_shader, config->max_cta_per_core )
{
m_kernel = NULL;
m_gpu = gpu;
m_cluster = cluster;
m_config = config;
m_memory_config = mem_config;
m_stats = stats;
unsigned warp_size=config->warp_size;
m_sid = shader_id;
m_tpc = tpc_id;
m_pipeline_reg.reserve(N_PIPELINE_STAGES);
for (int j = 0; j<N_PIPELINE_STAGES; j++) {
m_pipeline_reg.push_back(register_set(m_config->pipe_widths[j],pipeline_stage_name_decode[j]));
}
m_threadState = (thread_ctx_t*) calloc(sizeof(thread_ctx_t), config->n_thread_per_shader);
m_thread = (ptx_thread_info**) calloc(sizeof(ptx_thread_info*), config->n_thread_per_shader);
m_not_completed = 0;
m_active_threads.reset();
m_n_active_cta = 0;
for (unsigned i = 0; i<MAX_CTA_PER_SHADER; i++ )
m_cta_status[i]=0;
for (unsigned i = 0; i<config->n_thread_per_shader; i++) {
m_thread[i]= NULL;
m_threadState[i].m_cta_id = -1;
m_threadState[i].m_active = false;
}
// m_icnt = new shader_memory_interface(this,cluster);
if ( m_config->gpgpu_perfect_mem ) {
m_icnt = new perfect_memory_interface(this,cluster);
} else {
m_icnt = new shader_memory_interface(this,cluster);
}
m_mem_fetch_allocator = new shader_core_mem_fetch_allocator(shader_id,tpc_id,mem_config);
// fetch
m_last_warp_fetched = 0;
#define STRSIZE 1024
char name[STRSIZE];
snprintf(name, STRSIZE, "L1I_%03d", m_sid);
m_L1I = new read_only_cache( name,m_config->m_L1I_config,m_sid,get_shader_instruction_cache_id(),m_icnt,IN_L1I_MISS_QUEUE);
m_warp.resize(m_config->max_warps_per_shader, shd_warp_t(this, warp_size));
initilizeSIMTStack(config->max_warps_per_shader,this->get_config()->warp_size);
m_scoreboard = new Scoreboard(m_sid, m_config->max_warps_per_shader);
//scedulers
//must currently occur after all inputs have been initialized.
for (int i = 0; i < m_config->gpgpu_num_sched_per_core; i++) {
schedulers.push_back(scheduler_unit(m_stats,this,m_scoreboard,m_simt_stack,&m_warp,
&m_pipeline_reg[ID_OC_SP],
&m_pipeline_reg[ID_OC_SFU],
&m_pipeline_reg[ID_OC_MEM]));
}
for (unsigned i = 0; i < m_warp.size(); i++) {
//distribute i's evenly though schedulers;
schedulers[i%m_config->gpgpu_num_sched_per_core].add_supervised_warp_id(i);
}
//op collector configuration
enum { SP_CUS, SFU_CUS, MEM_CUS, GEN_CUS };
m_operand_collector.add_cu_set(SP_CUS, m_config->gpgpu_operand_collector_num_units_sp, m_config->gpgpu_operand_collector_num_out_ports_sp);
m_operand_collector.add_cu_set(SFU_CUS, m_config->gpgpu_operand_collector_num_units_sfu, m_config->gpgpu_operand_collector_num_out_ports_sfu);
m_operand_collector.add_cu_set(MEM_CUS, m_config->gpgpu_operand_collector_num_units_mem, m_config->gpgpu_operand_collector_num_out_ports_mem);
m_operand_collector.add_cu_set(GEN_CUS, m_config->gpgpu_operand_collector_num_units_gen, m_config->gpgpu_operand_collector_num_out_ports_gen);
opndcoll_rfu_t::port_vector_t in_ports;
opndcoll_rfu_t::port_vector_t out_ports;
opndcoll_rfu_t::uint_vector_t cu_sets;
for (unsigned i = 0; i < m_config->gpgpu_operand_collector_num_in_ports_sp; i++) {
in_ports.push_back(&m_pipeline_reg[ID_OC_SP]);
out_ports.push_back(&m_pipeline_reg[OC_EX_SP]);
cu_sets.push_back((unsigned)SP_CUS);
cu_sets.push_back((unsigned)GEN_CUS);
m_operand_collector.add_port(in_ports,out_ports,cu_sets);
in_ports.clear(),out_ports.clear(),cu_sets.clear();
}
for (unsigned i = 0; i < m_config->gpgpu_operand_collector_num_in_ports_sfu; i++) {
in_ports.push_back(&m_pipeline_reg[ID_OC_SFU]);
out_ports.push_back(&m_pipeline_reg[OC_EX_SFU]);
cu_sets.push_back((unsigned)SFU_CUS);
cu_sets.push_back((unsigned)GEN_CUS);
m_operand_collector.add_port(in_ports,out_ports,cu_sets);
in_ports.clear(),out_ports.clear(),cu_sets.clear();
}
for (unsigned i = 0; i < m_config->gpgpu_operand_collector_num_in_ports_mem; i++) {
in_ports.push_back(&m_pipeline_reg[ID_OC_MEM]);
out_ports.push_back(&m_pipeline_reg[OC_EX_MEM]);
cu_sets.push_back((unsigned)MEM_CUS);
cu_sets.push_back((unsigned)GEN_CUS);
m_operand_collector.add_port(in_ports,out_ports,cu_sets);
in_ports.clear(),out_ports.clear(),cu_sets.clear();
}
for (unsigned i = 0; i < m_config->gpgpu_operand_collector_num_in_ports_gen; i++) {
in_ports.push_back(&m_pipeline_reg[ID_OC_SP]);
in_ports.push_back(&m_pipeline_reg[ID_OC_SFU]);
in_ports.push_back(&m_pipeline_reg[ID_OC_MEM]);
out_ports.push_back(&m_pipeline_reg[OC_EX_SP]);
out_ports.push_back(&m_pipeline_reg[OC_EX_SFU]);
out_ports.push_back(&m_pipeline_reg[OC_EX_MEM]);
cu_sets.push_back((unsigned)GEN_CUS);
m_operand_collector.add_port(in_ports,out_ports,cu_sets);
in_ports.clear(),out_ports.clear(),cu_sets.clear();
}
m_operand_collector.init( m_config->gpgpu_num_reg_banks, this );
// execute
m_num_function_units = m_config->gpgpu_num_sp_units + m_config->gpgpu_num_sfu_units + 1; // sp_unit, sfu, ldst_unit
//m_dispatch_port = new enum pipeline_stage_name_t[ m_num_function_units ];
//m_issue_port = new enum pipeline_stage_name_t[ m_num_function_units ];
//m_fu = new simd_function_unit*[m_num_function_units];
for (int k = 0; k < m_config->gpgpu_num_sp_units; k++) {
m_fu.push_back(new sp_unit( &m_pipeline_reg[EX_WB], m_config ));
m_dispatch_port.push_back(ID_OC_SP);
m_issue_port.push_back(OC_EX_SP);
}
for (int k = 0; k < m_config->gpgpu_num_sfu_units; k++) {
m_fu.push_back(new sfu( &m_pipeline_reg[EX_WB], m_config ));
m_dispatch_port.push_back(ID_OC_SFU);
m_issue_port.push_back(OC_EX_SFU);
}
m_ldst_unit = new ldst_unit( m_icnt, m_mem_fetch_allocator, this, &m_operand_collector, m_scoreboard, config, mem_config, stats, shader_id, tpc_id );
m_fu.push_back(m_ldst_unit);
m_dispatch_port.push_back(ID_OC_MEM);
m_issue_port.push_back(OC_EX_MEM);
assert(m_num_function_units == m_fu.size() and m_fu.size() == m_dispatch_port.size() and m_fu.size() == m_issue_port.size());
//there are as many result buses as the width of the EX_WB stage
num_result_bus = config->pipe_widths[EX_WB];
for(unsigned i=0; i<num_result_bus; i++){
this->m_result_bus.push_back(new std::bitset<MAX_ALU_LATENCY>());
}
m_last_inst_gpu_sim_cycle = 0;
m_last_inst_gpu_tot_sim_cycle = 0;
}
void shader_core_ctx::reinit(unsigned start_thread, unsigned end_thread, bool reset_not_completed )
{
if( reset_not_completed ) {
m_not_completed = 0;
m_active_threads.reset();
}
for (unsigned i = start_thread; i<end_thread; i++) {
m_threadState[i].n_insn = 0;
m_threadState[i].m_cta_id = -1;
}
for (unsigned i = start_thread / m_config->warp_size; i < end_thread / m_config->warp_size; ++i) {
m_warp[i].reset();
m_simt_stack[i]->reset();
}
}
void shader_core_ctx::init_warps( unsigned cta_id, unsigned start_thread, unsigned end_thread )
{
address_type start_pc = next_pc(start_thread);
if (m_config->model == POST_DOMINATOR) {
unsigned start_warp = start_thread / m_config->warp_size;
unsigned end_warp = end_thread / m_config->warp_size + ((end_thread % m_config->warp_size)? 1 : 0);
for (unsigned i = start_warp; i < end_warp; ++i) {
unsigned n_active=0;
simt_mask_t active_threads;
for (unsigned t = 0; t < m_config->warp_size; t++) {
unsigned hwtid = i * m_config->warp_size + t;
if ( hwtid < end_thread ) {
n_active++;
assert( !m_active_threads.test(hwtid) );
m_active_threads.set( hwtid );
active_threads.set(t);
}
}
m_simt_stack[i]->launch(start_pc,active_threads);
m_warp[i].init(start_pc,cta_id,i,active_threads);
m_not_completed += n_active;
}
}
}
// return the next pc of a thread
address_type shader_core_ctx::next_pc( int tid ) const
{
if( tid == -1 )
return -1;
ptx_thread_info *the_thread = m_thread[tid];
if ( the_thread == NULL )
return -1;
return the_thread->get_pc(); // PC should already be updatd to next PC at this point (was set in shader_decode() last time thread ran)
}
void gpgpu_sim::get_pdom_stack_top_info( unsigned sid, unsigned tid, unsigned *pc, unsigned *rpc )
{
unsigned cluster_id = m_shader_config->sid_to_cluster(sid);
m_cluster[cluster_id]->get_pdom_stack_top_info(sid,tid,pc,rpc);
}
void shader_core_ctx::get_pdom_stack_top_info( unsigned tid, unsigned *pc, unsigned *rpc ) const
{
unsigned warp_id = tid/m_config->warp_size;
m_simt_stack[warp_id]->get_pdom_stack_top_info(pc,rpc);
}
void shader_core_stats::print( FILE* fout ) const
{
unsigned icount_uarch=0;
for(unsigned i=0; i < m_config->num_shader(); i++) {
icount_uarch += m_num_sim_insn[i];
}
fprintf(fout,"gpgpu_n_tot_icount = %u\n", icount_uarch);
fprintf(fout,"gpgpu_n_stall_shd_mem = %d\n", gpgpu_n_stall_shd_mem );
fprintf(fout,"gpgpu_n_mem_read_local = %d\n", gpgpu_n_mem_read_local);
fprintf(fout,"gpgpu_n_mem_write_local = %d\n", gpgpu_n_mem_write_local);
fprintf(fout,"gpgpu_n_mem_read_global = %d\n", gpgpu_n_mem_read_global);
fprintf(fout,"gpgpu_n_mem_write_global = %d\n", gpgpu_n_mem_write_global);
fprintf(fout,"gpgpu_n_mem_texture = %d\n", gpgpu_n_mem_texture);
fprintf(fout,"gpgpu_n_mem_const = %d\n", gpgpu_n_mem_const);
/*
unsigned a,m;
for (unsigned i=0, a=0, m=0;i<m_n_shader;i++)
m_sc[i]->L1cache_print(stdout,a,m);
printf("L1 Data Cache Total Miss Rate = %0.3f\n", (float)m/a);
for (i=0,a=0,m=0;i<m_n_shader;i++)
m_sc[i]->L1texcache_print(stdout,a,m);
printf("L1 Texture Cache Total Miss Rate = %0.3f\n", (float)m/a);
for (i=0,a=0,m=0;i<m_n_shader;i++)
m_sc[i]->L1constcache_print(stdout,a,m);
printf("L1 Const Cache Total Miss Rate = %0.3f\n", (float)m/a);
*/
fprintf(fout, "gpgpu_n_load_insn = %d\n", gpgpu_n_load_insn);
fprintf(fout, "gpgpu_n_store_insn = %d\n", gpgpu_n_store_insn);
fprintf(fout, "gpgpu_n_shmem_insn = %d\n", gpgpu_n_shmem_insn);
fprintf(fout, "gpgpu_n_tex_insn = %d\n", gpgpu_n_tex_insn);
fprintf(fout, "gpgpu_n_const_mem_insn = %d\n", gpgpu_n_const_insn);
fprintf(fout, "gpgpu_n_param_mem_insn = %d\n", gpgpu_n_param_insn);
fprintf(fout, "gpgpu_n_shmem_bkconflict = %d\n", gpgpu_n_shmem_bkconflict);
fprintf(fout, "gpgpu_n_cache_bkconflict = %d\n", gpgpu_n_cache_bkconflict);
fprintf(fout, "gpgpu_n_intrawarp_mshr_merge = %d\n", gpgpu_n_intrawarp_mshr_merge);
fprintf(fout, "gpgpu_n_cmem_portconflict = %d\n", gpgpu_n_cmem_portconflict);
fprintf(fout, "gpgpu_stall_shd_mem[c_mem][bk_conf] = %d\n", gpu_stall_shd_mem_breakdown[C_MEM][BK_CONF]);
fprintf(fout, "gpgpu_stall_shd_mem[c_mem][mshr_rc] = %d\n", gpu_stall_shd_mem_breakdown[C_MEM][MSHR_RC_FAIL]);
fprintf(fout, "gpgpu_stall_shd_mem[c_mem][icnt_rc] = %d\n", gpu_stall_shd_mem_breakdown[C_MEM][ICNT_RC_FAIL]);
fprintf(fout, "gpgpu_stall_shd_mem[t_mem][mshr_rc] = %d\n", gpu_stall_shd_mem_breakdown[T_MEM][MSHR_RC_FAIL]);
fprintf(fout, "gpgpu_stall_shd_mem[t_mem][icnt_rc] = %d\n", gpu_stall_shd_mem_breakdown[T_MEM][ICNT_RC_FAIL]);
fprintf(fout, "gpgpu_stall_shd_mem[s_mem][bk_conf] = %d\n", gpu_stall_shd_mem_breakdown[S_MEM][BK_CONF]);
fprintf(fout, "gpgpu_stall_shd_mem[gl_mem][bk_conf] = %d\n",
gpu_stall_shd_mem_breakdown[G_MEM_LD][BK_CONF] +
gpu_stall_shd_mem_breakdown[G_MEM_ST][BK_CONF] +
gpu_stall_shd_mem_breakdown[L_MEM_LD][BK_CONF] +
gpu_stall_shd_mem_breakdown[L_MEM_ST][BK_CONF]
); // coalescing stall at data cache
fprintf(fout, "gpgpu_stall_shd_mem[gl_mem][coal_stall] = %d\n",
gpu_stall_shd_mem_breakdown[G_MEM_LD][COAL_STALL] +
gpu_stall_shd_mem_breakdown[G_MEM_ST][COAL_STALL] +
gpu_stall_shd_mem_breakdown[L_MEM_LD][COAL_STALL] +
gpu_stall_shd_mem_breakdown[L_MEM_ST][COAL_STALL]
); // coalescing stall + bank conflict at data cache
fprintf(fout, "gpgpu_stall_shd_mem[g_mem_ld][mshr_rc] = %d\n", gpu_stall_shd_mem_breakdown[G_MEM_LD][MSHR_RC_FAIL]);
fprintf(fout, "gpgpu_stall_shd_mem[g_mem_ld][icnt_rc] = %d\n", gpu_stall_shd_mem_breakdown[G_MEM_LD][ICNT_RC_FAIL]);
fprintf(fout, "gpgpu_stall_shd_mem[g_mem_ld][wb_icnt_rc] = %d\n", gpu_stall_shd_mem_breakdown[G_MEM_LD][WB_ICNT_RC_FAIL]);
fprintf(fout, "gpgpu_stall_shd_mem[g_mem_ld][wb_rsrv_fail] = %d\n", gpu_stall_shd_mem_breakdown[G_MEM_LD][WB_CACHE_RSRV_FAIL]);
fprintf(fout, "gpgpu_stall_shd_mem[g_mem_st][mshr_rc] = %d\n", gpu_stall_shd_mem_breakdown[G_MEM_ST][MSHR_RC_FAIL]);
fprintf(fout, "gpgpu_stall_shd_mem[g_mem_st][icnt_rc] = %d\n", gpu_stall_shd_mem_breakdown[G_MEM_ST][ICNT_RC_FAIL]);
fprintf(fout, "gpgpu_stall_shd_mem[g_mem_st][wb_icnt_rc] = %d\n", gpu_stall_shd_mem_breakdown[G_MEM_ST][WB_ICNT_RC_FAIL]);
fprintf(fout, "gpgpu_stall_shd_mem[g_mem_st][wb_rsrv_fail] = %d\n", gpu_stall_shd_mem_breakdown[G_MEM_ST][WB_CACHE_RSRV_FAIL]);
fprintf(fout, "gpgpu_stall_shd_mem[l_mem_ld][mshr_rc] = %d\n", gpu_stall_shd_mem_breakdown[L_MEM_LD][MSHR_RC_FAIL]);
fprintf(fout, "gpgpu_stall_shd_mem[l_mem_ld][icnt_rc] = %d\n", gpu_stall_shd_mem_breakdown[L_MEM_LD][ICNT_RC_FAIL]);
fprintf(fout, "gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = %d\n", gpu_stall_shd_mem_breakdown[L_MEM_LD][WB_ICNT_RC_FAIL]);
fprintf(fout, "gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = %d\n", gpu_stall_shd_mem_breakdown[L_MEM_LD][WB_CACHE_RSRV_FAIL]);
fprintf(fout, "gpgpu_stall_shd_mem[l_mem_st][mshr_rc] = %d\n", gpu_stall_shd_mem_breakdown[L_MEM_ST][MSHR_RC_FAIL]);
fprintf(fout, "gpgpu_stall_shd_mem[l_mem_st][icnt_rc] = %d\n", gpu_stall_shd_mem_breakdown[L_MEM_ST][ICNT_RC_FAIL]);
fprintf(fout, "gpgpu_stall_shd_mem[l_mem_ld][wb_icnt_rc] = %d\n", gpu_stall_shd_mem_breakdown[L_MEM_ST][WB_ICNT_RC_FAIL]);
fprintf(fout, "gpgpu_stall_shd_mem[l_mem_ld][wb_rsrv_fail] = %d\n", gpu_stall_shd_mem_breakdown[L_MEM_ST][WB_CACHE_RSRV_FAIL]);
fprintf(fout, "gpu_reg_bank_conflict_stalls = %d\n", gpu_reg_bank_conflict_stalls);
fprintf(fout, "Warp Occupancy Distribution:\n");
fprintf(fout, "Stall:%d\t", shader_cycle_distro[2]);
fprintf(fout, "W0_Idle:%d\t", shader_cycle_distro[0]);
fprintf(fout, "W0_Scoreboard:%d", shader_cycle_distro[1]);
for (unsigned i = 3; i < m_config->warp_size + 3; i++)
fprintf(fout, "\tW%d:%d", i-2, shader_cycle_distro[i]);
fprintf(fout, "\n");
}
void shader_core_stats::visualizer_print( gzFile visualizer_file )
{
// warp divergence breakdown
gzprintf(visualizer_file, "WarpDivergenceBreakdown:");
unsigned int total=0;
unsigned int cf = (m_config->gpgpu_warpdistro_shader==-1)?m_config->num_shader():1;
gzprintf(visualizer_file, " %d", (shader_cycle_distro[0] - last_shader_cycle_distro[0]) / cf );
gzprintf(visualizer_file, " %d", (shader_cycle_distro[1] - last_shader_cycle_distro[1]) / cf );
gzprintf(visualizer_file, " %d", (shader_cycle_distro[2] - last_shader_cycle_distro[2]) / cf );
for (unsigned i=0; i<m_config->warp_size+3; i++) {
if ( i>=3 ) {
total += (shader_cycle_distro[i] - last_shader_cycle_distro[i]);
if ( ((i-3) % (m_config->warp_size/8)) == ((m_config->warp_size/8)-1) ) {
gzprintf(visualizer_file, " %d", total / cf );
total=0;
}
}
last_shader_cycle_distro[i] = shader_cycle_distro[i];
}
gzprintf(visualizer_file,"\n");
// overall cache miss rates
gzprintf(visualizer_file, "gpgpu_n_cache_bkconflict: %d\n", gpgpu_n_cache_bkconflict);
gzprintf(visualizer_file, "gpgpu_n_shmem_bkconflict: %d\n", gpgpu_n_shmem_bkconflict);
// instruction count per shader core
gzprintf(visualizer_file, "shaderinsncount: ");
for (unsigned i=0;i<m_config->num_shader();i++)
gzprintf(visualizer_file, "%u ", m_num_sim_insn[i] );
gzprintf(visualizer_file, "\n");
// warp instruction count per shader core
gzprintf(visualizer_file, "shaderwarpinsncount: ");
for (unsigned i=0;i<m_config->num_shader();i++)
gzprintf(visualizer_file, "%u ", m_num_sim_winsn[i] );
gzprintf(visualizer_file, "\n");
// warp divergence per shader core
gzprintf(visualizer_file, "shaderwarpdiv: ");
for (unsigned i=0;i<m_config->num_shader();i++)
gzprintf(visualizer_file, "%u ", m_n_diverge[i] );
gzprintf(visualizer_file, "\n");
}
#define PROGRAM_MEM_START 0xF0000000 /* should be distinct from other memory spaces...
check ptx_ir.h to verify this does not overlap
other memory spaces */
void shader_core_ctx::decode()
{
if( m_inst_fetch_buffer.m_valid ) {
// decode 1 or 2 instructions and place them into ibuffer
address_type pc = m_inst_fetch_buffer.m_pc;
const warp_inst_t* pI1 = ptx_fetch_inst(pc);
m_warp[m_inst_fetch_buffer.m_warp_id].ibuffer_fill(0,pI1);
m_warp[m_inst_fetch_buffer.m_warp_id].inc_inst_in_pipeline();
if( pI1 ) {
const warp_inst_t* pI2 = ptx_fetch_inst(pc+pI1->isize);
if( pI2 ) {
m_warp[m_inst_fetch_buffer.m_warp_id].ibuffer_fill(1,pI2);
m_warp[m_inst_fetch_buffer.m_warp_id].inc_inst_in_pipeline();
}
}
m_inst_fetch_buffer.m_valid = false;
}
}
void shader_core_ctx::fetch()
{
if( !m_inst_fetch_buffer.m_valid ) {
// find an active warp with space in instruction buffer that is not already waiting on a cache miss
// and get next 1-2 instructions from i-cache...
for( unsigned i=0; i < m_config->max_warps_per_shader; i++ ) {
unsigned warp_id = (m_last_warp_fetched+1+i) % m_config->max_warps_per_shader;
// this code checks if this warp has finished executing and can be reclaimed
if( m_warp[warp_id].hardware_done() && !m_scoreboard->pendingWrites(warp_id) && !m_warp[warp_id].done_exit() ) {
bool did_exit=false;
for( unsigned t=0; t<m_config->warp_size;t++) {
unsigned tid=warp_id*m_config->warp_size+t;
if( m_threadState[tid].m_active == true ) {
m_threadState[tid].m_active = false;
unsigned cta_id = m_warp[warp_id].get_cta_id();
register_cta_thread_exit(cta_id);
m_not_completed -= 1;
m_active_threads.reset(tid);
assert( m_thread[tid]!= NULL );
did_exit=true;
}
}
if( did_exit )
m_warp[warp_id].set_done_exit();
}
// this code fetches instructions from the i-cache or generates memory requests
if( !m_warp[warp_id].functional_done() && !m_warp[warp_id].imiss_pending() && m_warp[warp_id].ibuffer_empty() ) {
address_type pc = m_warp[warp_id].get_pc();
address_type ppc = pc + PROGRAM_MEM_START;
unsigned nbytes=16;
unsigned offset_in_block = pc & (m_config->m_L1I_config.get_line_sz()-1);
if( (offset_in_block+nbytes) > m_config->m_L1I_config.get_line_sz() )
nbytes = (m_config->m_L1I_config.get_line_sz()-offset_in_block);
// TODO: replace with use of allocator
// mem_fetch *mf = m_mem_fetch_allocator->alloc()
mem_access_t acc(INST_ACC_R,ppc,nbytes,false);
mem_fetch *mf = new mem_fetch(acc,
NULL/*we don't have an instruction yet*/,
READ_PACKET_SIZE,
warp_id,
m_sid,
m_tpc,
m_memory_config );
std::list<cache_event> events;
enum cache_request_status status = m_L1I->access( (new_addr_type)ppc, mf, gpu_sim_cycle+gpu_tot_sim_cycle,events);
if( status == MISS ) {
m_last_warp_fetched=warp_id;
m_warp[warp_id].set_imiss_pending();
m_warp[warp_id].set_last_fetch(gpu_sim_cycle);
} else if( status == HIT ) {
m_last_warp_fetched=warp_id;
m_inst_fetch_buffer = ifetch_buffer_t(pc,nbytes,warp_id);
m_warp[warp_id].set_last_fetch(gpu_sim_cycle);
delete mf;
} else {
m_last_warp_fetched=warp_id;
assert( status == RESERVATION_FAIL );
delete mf;
}
break;
}
}
}
m_L1I->cycle();
if( m_L1I->access_ready() ) {
mem_fetch *mf = m_L1I->next_access();
m_warp[mf->get_wid()].clear_imiss_pending();
delete mf;
}
}
void shader_core_ctx::func_exec_inst( warp_inst_t &inst )
{
execute_warp_inst_t(inst, m_config->warp_size);
if( inst.is_load() || inst.is_store() )
inst.generate_mem_accesses();
}
class KAIN_warp_inst
{
public:
warp_inst_t *inst;
simt_mask_t *thread_done;
addr_vector_t *next_pc;
unsigned reconvergence_pc;
KAIN_warp_inst()
{
inst = new warp_inst_t;
thread_done= new simt_mask_t;
next_pc = new addr_vector_t;
}
~KAIN_warp_inst()
{
delete inst;
delete thread_done;
delete next_pc;
}
};
extern class KAIN_warp_inst **block_warpid[4000][100];
unsigned Count_Block_C[7000];
extern unsigned Count_Block_P[7000];
void shader_core_ctx::issue_warp( register_set& pipe_reg_set, const warp_inst_t* next_inst, const active_mask_t &active_mask, unsigned warp_id )
{
warp_inst_t** pipe_reg = pipe_reg_set.get_free();
assert(pipe_reg);
m_warp[warp_id].ibuffer_free();
assert(next_inst->valid());
**pipe_reg = *next_inst; // static instruction information
(*pipe_reg)->issue( active_mask, warp_id, gpu_tot_sim_cycle + gpu_sim_cycle ); // dynamic instruction information
m_stats->shader_cycle_distro[2+(*pipe_reg)->active_count()]++;
////////////////////////?KAIN moved here
m_scoreboard->reserveRegisters(*pipe_reg);
m_warp[warp_id].set_next_pc(next_inst->pc + next_inst->isize);
unsigned int tid = m_config->warp_size*(**pipe_reg).warp_id()+0;
unsigned BlockID;
unsigned WarpID;
m_thread[tid]->KAIN_get_cta_num(m_config->warp_size,next_inst->pc,&BlockID,&WarpID);
int warp_ID_all = BlockID * KAIN_Warp_counts + WarpID;// KAIN_Warp_counts is the suppose that the warp per block less than "KAIN_Warp_counts
int index_new = Count_Block_C[warp_ID_all];
// printf("indexnew is %d\n",index_new);
index_new = index_new % 15000;
printf("before while C is %ld,P is %ld, warpID_all is %d\n",Count_Block_C[warp_ID_all],Count_Block_P[warp_ID_all],warp_ID_all);
while(Count_Block_C[warp_ID_all] >= Count_Block_P[warp_ID_all]-100)//100 used for data compete
{
;
printf("sleep in perfomrance,Block is %d, Warp is %d\n",BlockID,WarpID);
sleep(1);
}
printf("before assert C is %ld,P is %ld, warpID_all is %d\n",Count_Block_C[warp_ID_all],Count_Block_P[warp_ID_all],warp_ID_all);
assert(Count_Block_C[warp_ID_all] < Count_Block_P[warp_ID_all]);
class KAIN_warp_inst *this_inst = block_warpid[BlockID][WarpID][index_new];
warp_inst_t &inst = *(this_inst->inst);
inst.KAIN_copy_issue( active_mask, warp_id, gpu_tot_sim_cycle + gpu_sim_cycle );
unsigned wtid = warp_id * m_config->warp_size;
simt_mask_t thread_done = *(this_inst->thread_done);
addr_vector_t next_pc = *(this_inst->next_pc);
(**pipe_reg).reconvergence_pc = (this_inst->reconvergence_pc);
if(thread_done.count()>0)
for(unsigned i = 0; i < m_config->warp_size;i++)
{
if(thread_done[i]){
printf("in kain world, theread_%d done\n",wtid+i);
m_thread[wtid+i]->set_done();
m_thread[wtid+i]->exitCore();
m_thread[wtid+i]->registerExit();
}
}
for ( unsigned t=0; t < m_config->warp_size; t++ ) {
if( inst.active(t) ) {
unsigned tid=m_config->warp_size*warp_id+t;
if( inst.has_callback(t) )
{
m_warp[warp_id].inc_n_atomic();
}
if (inst.space.is_local() && (inst.is_load() || inst.is_store())) {
new_addr_type localaddrs[MAX_ACCESSES_PER_INSN_PER_THREAD];
unsigned num_addrs;
num_addrs = translate_local_memaddr(inst.get_addr(t), tid, m_config->n_simt_clusters*m_config->n_simt_cores_per_cluster,
inst.data_size, (new_addr_type*) localaddrs );
// printf("local address is %d\n",localaddrs[0]);
inst.set_addr(t, (new_addr_type*) localaddrs, num_addrs);
}
if( ptx_thread_done(tid) ) {
printf("come here>>>>>>>>. ptx %ddone\n",tid);
m_warp[warp_id].set_completed(t);
m_warp[warp_id].ibuffer_flush();
}
}
}
if( inst.is_load() || inst.is_store() )
{
// printf("generate mem access,in kain's world\n");
inst.generate_mem_accesses();
}
(**pipe_reg)= inst;
m_simt_stack[warp_id]->update(thread_done,next_pc,(**pipe_reg).reconvergence_pc);
Count_Block_C[warp_ID_all]++;
//delete this_inst;
//func_exec_inst( **pipe_reg );
if( next_inst->op == BARRIER_OP )
m_barriers.warp_reaches_barrier(m_warp[warp_id].get_cta_id(),warp_id);
else if( next_inst->op == MEMORY_BARRIER_OP )
m_warp[warp_id].set_membar();
//updateSIMTStack(warp_id,m_config->warp_size,*pipe_reg);
//m_scoreboard->reserveRegisters(*pipe_reg);
//m_warp[warp_id].set_next_pc(next_inst->pc + next_inst->isize);
}
void shader_core_ctx::issue(){
//really is issue;
for (unsigned i = 0; i < schedulers.size(); i++) {
schedulers[i].cycle();
}
}
shd_warp_t& scheduler_unit::warp(int i){
return (*m_warp)[i];
}
void scheduler_unit::cycle()
{
bool valid_inst = false; // there was one warp with a valid instruction to issue (didn't require flush due to control hazard)
bool ready_inst = false; // of the valid instructions, there was one not waiting for pending register writes
bool issued_inst = false; // of these we issued one
for ( unsigned i=0; i < supervised_warps.size(); i++ ) {
unsigned supervised_id = (m_last_sup_id_issued+1+i) % supervised_warps.size();
unsigned warp_id = supervised_warps[supervised_id];
unsigned checked=0;
unsigned issued=0;
unsigned max_issue = m_shader->m_config->gpgpu_max_insn_issue_per_warp;
while( !warp(warp_id).waiting() && !warp(warp_id).ibuffer_empty() && (checked < max_issue) && (checked <= issued) && (issued < max_issue) ) {
const warp_inst_t *pI = warp(warp_id).ibuffer_next_inst();
bool valid = warp(warp_id).ibuffer_next_valid();
bool warp_inst_issued = false;
unsigned pc,rpc;
m_simt_stack[warp_id]->get_pdom_stack_top_info(&pc,&rpc);
if( pI ) {
assert(valid);
if( pc != pI->pc ) {
// control hazard
warp(warp_id).set_next_pc(pc);
warp(warp_id).ibuffer_flush();
} else {
valid_inst = true;
if ( !m_scoreboard->checkCollision(warp_id, pI) ) {
ready_inst = true;
const active_mask_t &active_mask = m_simt_stack[warp_id]->get_active_mask();
assert( warp(warp_id).inst_in_pipeline() );
if ( (pI->op == LOAD_OP) || (pI->op == STORE_OP) || (pI->op == MEMORY_BARRIER_OP) ) {
if( m_mem_out->has_free() ) {
m_shader->issue_warp(*m_mem_out,pI,active_mask,warp_id);
issued++;
issued_inst=true;
warp_inst_issued = true;
}
} else {
bool sp_pipe_avail = m_sp_out->has_free();
bool sfu_pipe_avail = m_sfu_out->has_free();
if( sp_pipe_avail && (pI->op != SFU_OP) ) {
// always prefer SP pipe for operations that can use both SP and SFU pipelines
m_shader->issue_warp(*m_sp_out,pI,active_mask,warp_id);
issued++;
issued_inst=true;
warp_inst_issued = true;
} else if ( (pI->op == SFU_OP) || (pI->op == ALU_SFU_OP) ) {
if( sfu_pipe_avail ) {
m_shader->issue_warp(*m_sfu_out,pI,active_mask,warp_id);
issued++;
issued_inst=true;
warp_inst_issued = true;
}
}
}
}
}
} else if( valid ) {
// this case can happen after a return instruction in diverged warp
warp(warp_id).set_next_pc(pc);
warp(warp_id).ibuffer_flush();
}
if(warp_inst_issued)
warp(warp_id).ibuffer_step();
checked++;
}
if ( issued ) {
m_last_sup_id_issued=supervised_id;
break;
}
}
// issue stall statistics:
if( !valid_inst )
m_stats->shader_cycle_distro[0]++; // idle or control hazard
else if( !ready_inst )
m_stats->shader_cycle_distro[1]++; // waiting for RAW hazards (possibly due to memory)
else if( !issued_inst )
m_stats->shader_cycle_distro[2]++; // pipeline stalled
}
void shader_core_ctx::read_operands()
{
}
address_type coalesced_segment(address_type addr, unsigned segment_size_lg2bytes)
{
return (addr >> segment_size_lg2bytes);
}
// Returns numbers of addresses in translated_addrs, each addr points to a 4B (32-bit) word
unsigned shader_core_ctx::translate_local_memaddr( address_type localaddr, unsigned tid, unsigned num_shader, unsigned datasize, new_addr_type* translated_addrs )
{
// During functional execution, each thread sees its own memory space for local memory, but these
// need to be mapped to a shared address space for timing simulation. We do that mapping here.
address_type thread_base = 0;
unsigned max_concurrent_threads=0;
if (m_config->gpgpu_local_mem_map) {
// Dnew = D*N + T%nTpC + nTpC*C
// N = nTpC*nCpS*nS (max concurent threads)
// C = nS*K + S (hw cta number per gpu)
// K = T/nTpC (hw cta number per core)
// D = data index
// T = thread
// nTpC = number of threads per CTA
// nCpS = number of CTA per shader
//
// for a given local memory address threads in a CTA map to contiguous addresses,
// then distribute across memory space by CTAs from successive shader cores first,
// then by successive CTA in same shader core
thread_base = 4*(kernel_padded_threads_per_cta * (m_sid + num_shader * (tid / kernel_padded_threads_per_cta))
+ tid % kernel_padded_threads_per_cta);
max_concurrent_threads = kernel_padded_threads_per_cta * kernel_max_cta_per_shader * num_shader;
} else {
// legacy mapping that maps the same address in the local memory space of all threads
// to a single contiguous address region
thread_base = 4*(m_config->n_thread_per_shader * m_sid + tid);
max_concurrent_threads = num_shader * m_config->n_thread_per_shader;
}
assert( thread_base < 4/*word size*/*max_concurrent_threads );
// If requested datasize > 4B, split into multiple 4B accesses
// otherwise do one sub-4 byte memory access
unsigned num_accesses = 0;
if(datasize >= 4) {
// >4B access, split into 4B chunks
assert(datasize%4 == 0); // Must be a multiple of 4B
num_accesses = datasize/4;
assert(num_accesses <= MAX_ACCESSES_PER_INSN_PER_THREAD); // max 32B
assert(localaddr%4 == 0); // Address must be 4B aligned - required if accessing 4B per request, otherwise access will overflow into next thread's space
for(unsigned i=0; i<num_accesses; i++) {
address_type local_word = localaddr/4 + i;
address_type linear_address = local_word*max_concurrent_threads*4 + thread_base + LOCAL_GENERIC_START;
translated_addrs[i] = linear_address;
}
} else {
// Sub-4B access, do only one access
assert(datasize > 0);
num_accesses = 1;
address_type local_word = localaddr/4;
address_type local_word_offset = localaddr%4;
assert( (localaddr+datasize-1)/4 == local_word ); // Make sure access doesn't overflow into next 4B chunk
address_type linear_address = local_word*max_concurrent_threads*4 + local_word_offset + thread_base + LOCAL_GENERIC_START;
translated_addrs[0] = linear_address;
}
return num_accesses;
}
/////////////////////////////////////////////////////////////////////////////////////////
int shader_core_ctx::test_res_bus(int latency){
for(unsigned i=0; i<num_result_bus; i++){
if(!m_result_bus[i]->test(latency)){return i;}
}
return -1;
}
void shader_core_ctx::execute()
{
for(unsigned i=0; i<num_result_bus; i++){
*(m_result_bus[i]) >>=1;
}
for( unsigned n=0; n < m_num_function_units; n++ ) {
unsigned multiplier = m_fu[n]->clock_multiplier();
for( unsigned c=0; c < multiplier; c++ )
m_fu[n]->cycle();
enum pipeline_stage_name_t issue_port = m_issue_port[n];
register_set& issue_inst = m_pipeline_reg[ issue_port ];
warp_inst_t** ready_reg = issue_inst.get_ready();
if( issue_inst.has_ready() && m_fu[n]->can_issue( **ready_reg ) ) {
bool schedule_wb_now = !m_fu[n]->stallable();
int resbus = -1;
if( schedule_wb_now && (resbus=test_res_bus( (*ready_reg)->latency ))!=-1 ) {
assert( (*ready_reg)->latency < MAX_ALU_LATENCY );
m_result_bus[resbus]->set( (*ready_reg)->latency );
m_fu[n]->issue( issue_inst );
} else if( !schedule_wb_now ) {
m_fu[n]->issue( issue_inst );
} else {
// stall issue (cannot reserve result bus)
}
}
}
}
void ldst_unit::print_cache_stats( FILE *fp, unsigned& dl1_accesses, unsigned& dl1_misses ) {
if( m_L1D ) {
m_L1D->print( fp, dl1_accesses, dl1_misses );
}
}
void shader_core_ctx::warp_inst_complete(const warp_inst_t &inst)
{
#if 0
printf("[warp_inst_complete] uid=%u core=%u warp=%u pc=%#x @ time=%llu issued@%llu\n",
inst.get_uid(), m_sid, inst.warp_id(), inst.pc, gpu_tot_sim_cycle + gpu_sim_cycle, inst.get_issue_cycle());
#endif
m_stats->m_num_sim_insn[m_sid] += inst.active_count();
m_stats->m_num_sim_winsn[m_sid]++;
m_gpu->gpu_sim_insn += inst.active_count();
inst.completed(gpu_tot_sim_cycle + gpu_sim_cycle);
}
void shader_core_ctx::writeback()
{
warp_inst_t** preg = m_pipeline_reg[EX_WB].get_ready();
warp_inst_t* pipe_reg = (preg==NULL)? NULL:*preg;
while( preg and !pipe_reg->empty() ) {
/*
* Right now, the writeback stage drains all waiting instructions
* assuming there are enough ports in the register file or the
* conflicts are resolved at issue.
*/
/*
* The operand collector writeback can generally generate a stall
* However, here, the pipelines should be un-stallable. This is
* guaranteed because this is the first time the writeback function
* is called after the operand collector's step function, which
* resets the allocations. There is one case which could result in
* the writeback function returning false (stall), which is when
* an instruction tries to modify two registers (GPR and predicate)
* To handle this case, we ignore the return value (thus allowing
* no stalling).
*/
m_operand_collector.writeback(*pipe_reg);
unsigned warp_id = pipe_reg->warp_id();
m_scoreboard->releaseRegisters( pipe_reg );
m_warp[warp_id].dec_inst_in_pipeline();
warp_inst_complete(*pipe_reg);
m_gpu->gpu_sim_insn_last_update_sid = m_sid;
m_gpu->gpu_sim_insn_last_update = gpu_sim_cycle;
m_last_inst_gpu_sim_cycle = gpu_sim_cycle;
m_last_inst_gpu_tot_sim_cycle = gpu_tot_sim_cycle;
pipe_reg->clear();
preg = m_pipeline_reg[EX_WB].get_ready();
pipe_reg = (preg==NULL)? NULL:*preg;
}
}
bool ldst_unit::shared_cycle( warp_inst_t &inst, mem_stage_stall_type &rc_fail, mem_stage_access_type &fail_type)
{
if( inst.space.get_type() != shared_space )
return true;
bool stall = inst.dispatch_delay();
if( stall ) {
fail_type = S_MEM;
rc_fail = BK_CONF;
} else
rc_fail = NO_RC_FAIL;
return !stall;
}
mem_stage_stall_type ldst_unit::process_memory_access_queue( cache_t *cache, warp_inst_t &inst )
{
mem_stage_stall_type result = NO_RC_FAIL;
if( inst.accessq_empty() )
return result;
//const mem_access_t &access = inst.accessq_back();
mem_fetch *mf = m_mf_allocator->alloc(inst,inst.accessq_back());
std::list<cache_event> events;
enum cache_request_status status = cache->access(mf->get_addr(),mf,gpu_sim_cycle+gpu_tot_sim_cycle,events);
bool write_sent = was_write_sent(events);
bool read_sent = was_read_sent(events);
if( write_sent )
m_core->inc_store_req( inst.warp_id() );
if ( status == HIT ) {
assert( !read_sent );
inst.accessq_pop_back();
if ( inst.is_load() ) {
for ( unsigned r=0; r < 4; r++)
if (inst.out[r] > 0)
m_pending_writes[inst.warp_id()][inst.out[r]]--;
}
if( !write_sent )
delete mf;
} else if ( status == RESERVATION_FAIL ) {
result = COAL_STALL;
assert( !read_sent );
assert( !write_sent );
delete mf;
} else {
assert( status == MISS || status == HIT_RESERVED );
//inst.clear_active( access.get_warp_mask() ); // threads in mf writeback when mf returns
inst.accessq_pop_back();
}
if( !inst.accessq_empty() )
result = BK_CONF;
return result;
}
bool ldst_unit::constant_cycle( warp_inst_t &inst, mem_stage_stall_type &rc_fail, mem_stage_access_type &fail_type)
{
if( inst.empty() || ((inst.space.get_type() != const_space) && (inst.space.get_type() != param_space_kernel)) )
return true;
if( inst.active_count() == 0 )
return true;
mem_stage_stall_type fail = process_memory_access_queue(m_L1C,inst);
if (fail != NO_RC_FAIL){
rc_fail = fail; //keep other fails if this didn't fail.
fail_type = C_MEM;
if (rc_fail == BK_CONF or rc_fail == COAL_STALL) {
m_stats->gpgpu_n_cmem_portconflict++; //coal stalls aren't really a bank conflict, but this maintains previous behavior.
}
}
return inst.accessq_empty(); //done if empty.
}
bool ldst_unit::texture_cycle( warp_inst_t &inst, mem_stage_stall_type &rc_fail, mem_stage_access_type &fail_type)
{
if( inst.empty() || inst.space.get_type() != tex_space )
return true;
if( inst.active_count() == 0 )
return true;
mem_stage_stall_type fail = process_memory_access_queue(m_L1T,inst);
if (fail != NO_RC_FAIL){
rc_fail = fail; //keep other fails if this didn't fail.
fail_type = T_MEM;
}
return inst.accessq_empty(); //done if empty.
}
bool ldst_unit::memory_cycle( warp_inst_t &inst, mem_stage_stall_type &stall_reason, mem_stage_access_type &access_type )
{
if( inst.empty() ||
((inst.space.get_type() != global_space) &&
(inst.space.get_type() != local_space) &&
(inst.space.get_type() != param_space_local)) )
return true;
if( inst.active_count() == 0 )
return true;
assert( !inst.accessq_empty() );
mem_stage_stall_type stall_cond = NO_RC_FAIL;
const mem_access_t &access = inst.accessq_back();
unsigned size = access.get_size();