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[Backend][SystemC] Stratus HLS Codegen Backend Support (Re-opened) (cornell-zhang#451)
* [Backend][SystemC] Add StratusHLS backend implementation * [Backend][SystemC] Add Python API and harness files * [Backend][SystemC] Ruling out illegal loop label string * [Backend][SystemC] Rename and move PortDirection and Hierarchy to ir_utils.h
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lines changed

‎python/heterocl/api.py

+4-1
Original file line numberDiff line numberDiff line change
@@ -323,7 +323,10 @@ def build(schedule, target=None, name="default_function", stmt=None):
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new_inputs.append(i.var)
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# auto data moving to dev
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if len(schedule.placement) == 0 and (target is not None):
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if hasattr(target, "name") and target.name == "cadence_stratus":
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# Cadence stratus does not support auto data moving
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pass
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elif len(schedule.placement) == 0 and (target is not None):
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if not isinstance(target, str):
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# TODO: print clean info for auto placement
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# import builtins as __builtin__

‎python/heterocl/harness/stratus/Makefile

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###############################################################################
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#
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# Copyright (c) 2017 Cadence Design Systems, Inc. All rights reserved worldwide.
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#
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# The code contained herein is the proprietary and confidential information
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# of Cadence or its licensors, and is supplied subject to a previously
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# executed license and maintenance agreement between Cadence and customer.
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# This code is intended for use with Cadence high-level synthesis tools and
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# may not be used with other high-level synthesis tools. Permission is only
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# granted to distribute the code as indicated. Cadence grants permission for
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# customer to distribute a copy of this code to any partner to aid in designing
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# or verifying the customer's intellectual property, as long as such
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# distribution includes a restriction of no additional distributions from the
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# partner, unless the partner receives permission directly from Cadence.
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#
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# ALL CODE FURNISHED BY CADENCE IS PROVIDED "AS IS" WITHOUT WARRANTY OF ANY
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# KIND, AND CADENCE SPECIFICALLY DISCLAIMS ANY WARRANTY OF NONINFRINGEMENT,
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# FITNESS FOR A PARTICULAR PURPOSE OR MERCHANTABILITY. CADENCE SHALL NOT BE
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# LIABLE FOR ANY COSTS OF PROCUREMENT OF SUBSTITUTES, LOSS OF PROFITS,
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# INTERRUPTION OF BUSINESS, OR FOR ANY OTHER SPECIAL, CONSEQUENTIAL OR
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# INCIDENTAL DAMAGES, HOWEVER CAUSED, WHETHER FOR BREACH OF WARRANTY,
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# CONTRACT, TORT, NEGLIGENCE, STRICT LIABILITY OR OTHERWISE.
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#
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################################################################################
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# Include the Makefile.prj file extracted from project.tcl
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-include Makefile.prj
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# Rule to update Makefile.prj anytime project.tcl changes
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Makefile.prj : project.tcl
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@bdw_makegen
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# List subdirectories that contain memory libraries
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MEMLIBS =
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# List subdirectories that contain interface libraries
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IFLIBS =
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# Uncomment this line to use the Insight debugger
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BDW_DEBUG = 1
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# The cmp_result target compares the golden results file (golden.dat) with
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# the simulation results file (data.out) written by the testbench into the
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# BDW_SIM_CONFIG simulation configuration directory. This is run automatically
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# at the end of each simulation (endOfSimCommand in project.tcl).
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GOLD_FILE = DRAM/golden.bin
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RESULTS_FILE = DRAM/result.bin
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# cmp_result:
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# @if [ -f $(RESULTS_FILE) ] ; then \
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# echo "****************************************" ; \
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# echo `date` ; \
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# echo "Performing Simulation Results Comparison" ; \
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# echo "for $(BDW_SIM_CONFIG) Simulation..." ; \
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# if diff $(RESULTS_FILE) $(GOLD_FILE) ; then \
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# echo " $(BDW_SIM_CONFIG): SIMULATION PASSED" ; \
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# bdw_sim_pass ; \
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# else \
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# echo " $(BDW_SIM_CONFIG): SIMULATION FAILED" ; \
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# bdw_sim_fail ; \
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# fi ; \
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# echo "****************************************" ; \
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# else \
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# echo "****************************************" ; \
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# echo `date` ; \
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# echo "ERROR: Simulation output doesn't exist" ; \
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# echo "for $(BDW_SIM_CONFIG) Simulation..." ; \
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# echo " $(BDW_SIM_CONFIG): SIMULATION FAILED" ; \
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# bdw_sim_fail ; \
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# echo "****************************************" ; \
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# fi
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cmp_result:
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@if [ -f $(RESULTS_FILE) ] ; then \
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echo "****************************************" ; \
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echo `date` ; \
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echo "for $(BDW_SIM_CONFIG) Simulation..." ; \
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echo " $(BDW_SIM_CONFIG): SIMULATION PASSED" ; \
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bdw_sim_pass ; \
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echo "****************************************" ; \
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else \
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echo "****************************************" ; \
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echo `date` ; \
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echo "ERROR: Simulation output doesn't exist" ; \
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echo "for $(BDW_SIM_CONFIG) Simulation..." ; \
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echo " $(BDW_SIM_CONFIG): SIMULATION FAILED" ; \
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bdw_sim_fail ; \
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echo "****************************************" ; \
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fi
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# Clean out undesirable junk files from the project directory
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# Uses the automatically created clean_all target from Makefile.prj
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clean: clean_all
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@rm -rf bdw_work vsim* *.wlf data.out *~ *.bak *.BAK Makefile.prj
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@rm -rf core *.pro *.user *.log .*.qws .*.check .stack* .parts*
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@rm -rf rc.* fv .stratus*
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CLEAN: clean

‎python/heterocl/harness/stratus/main.cc

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///////////////////////////////////////////////////////////////////////////////
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//
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// Copyright (c) 2017 Cadence Design Systems, Inc. All rights reserved worldwide.
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//
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// The code contained herein is the proprietary and confidential information
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// of Cadence or its licensors, and is supplied subject to a previously
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// executed license and maintenance agreement between Cadence and customer.
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// This code is intended for use with Cadence high-level synthesis tools and
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// may not be used with other high-level synthesis tools. Permission is only
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// granted to distribute the code as indicated. Cadence grants permission for
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// customer to distribute a copy of this code to any partner to aid in designing
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// or verifying the customer's intellectual property, as long as such
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// distribution includes a restriction of no additional distributions from the
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// partner, unless the partner receives permission directly from Cadence.
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//
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// ALL CODE FURNISHED BY CADENCE IS PROVIDED "AS IS" WITHOUT WARRANTY OF ANY
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// KIND, AND CADENCE SPECIFICALLY DISCLAIMS ANY WARRANTY OF NONINFRINGEMENT,
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// FITNESS FOR A PARTICULAR PURPOSE OR MERCHANTABILITY. CADENCE SHALL NOT BE
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// LIABLE FOR ANY COSTS OF PROCUREMENT OF SUBSTITUTES, LOSS OF PROFITS,
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// INTERRUPTION OF BUSINESS, OR FOR ANY OTHER SPECIAL, CONSEQUENTIAL OR
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// INCIDENTAL DAMAGES, HOWEVER CAUSED, WHETHER FOR BREACH OF WARRANTY,
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// CONTRACT, TORT, NEGLIGENCE, STRICT LIABILITY OR OTHERWISE.
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//
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////////////////////////////////////////////////////////////////////////////////
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#include <systemc.h> // SystemC definitions
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#include "system.h" // Top-level System module header file
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static System * m_system = NULL; // The pointer that holds the top-level System module instance.
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void esc_elaborate() // This function is required by Stratus to support SystemC-Verilog
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{ // cosimulation. It instances the top-level module.
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m_system = new System( "system" );
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}
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void esc_cleanup() // This function is called at the end of simulation by the
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{ // Stratus co-simulation hub. It should delete the top-level
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delete m_system; // module instance.
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}
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int sc_main( int argc, char ** argv ) // This function is called by the SystemC kernel for pure SystemC simulations
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{
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esc_initialize( argc, argv ); // esc_initialize() passes in the cmd-line args. This initializes the Stratus simulation
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// environment (such as opening report files for later logging and analysis).
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esc_elaborate(); // esc_elaborate() (defined above) creates the top-level module instance. In a SystemC-Verilog
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// co-simulation, this is called during cosim initialization rather than from sc_main.
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sc_start(); // Starts the simulation. Returns when a module calls esc_stop(), which finishes the simulation.
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// esc_cleanup() (defined above) is automatically called before sc_start() returns.
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return 0; // Returns the status of the simulation. Required by most C compilers.
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}

‎python/heterocl/harness/stratus/memlib/c_parts/dram.cc

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@@ -0,0 +1,161 @@
1+
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///////////////////////////////////////////////////////////////////////////////
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//
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// Copyright (c) 2021 Cadence Design Systems, Inc. All rights reserved worldwide.
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//
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// The code contained herein is the proprietary and confidential information
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// of Cadence or its licensors, and is supplied subject to a previously
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// executed license and maintenance agreement between Cadence and customer.
9+
// This code is intended for use with Cadence high-level synthesis tools and
10+
// may not be used with other high-level synthesis tools. Permission is only
11+
// granted to distribute the code as indicated. Cadence grants permission for
12+
// customer to distribute a copy of this code to any partner to aid in designing
13+
// or verifying the customer's intellectual property, as long as such
14+
// distribution includes a restriction of no additional distributions from the
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// partner, unless the partner receives permission directly from Cadence.
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//
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// ALL CODE FURNISHED BY CADENCE IS PROVIDED "AS IS" WITHOUT WARRANTY OF ANY
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// KIND, AND CADENCE SPECIFICALLY DISCLAIMS ANY WARRANTY OF NONINFRINGEMENT,
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// FITNESS FOR A PARTICULAR PURPOSE OR MERCHANTABILITY. CADENCE SHALL NOT BE
20+
// LIABLE FOR ANY COSTS OF PROCUREMENT OF SUBSTITUTES, LOSS OF PROFITS,
21+
// INTERRUPTION OF BUSINESS, OR FOR ANY OTHER SPECIAL, CONSEQUENTIAL OR
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// INCIDENTAL DAMAGES, HOWEVER CAUSED, WHETHER FOR BREACH OF WARRANTY,
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// CONTRACT, TORT, NEGLIGENCE, STRICT LIABILITY OR OTHERWISE.
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//
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////////////////////////////////////////////////////////////////////////////////
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// Generated by bdw_memgen 20.23-s100
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// Thu Jun 24 09:00:48 CST 2021
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#if ! defined dram_CC
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#define dram_CC 1
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#if defined STRATUS && ! defined CYN_DONT_SUPPRESS_MSGS
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#pragma cyn_suppress_msgs NOTE
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#endif // STRATUS && CYN_DONT_SUPPRESS_MSGS
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#include "dram.h"
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#ifdef STRATUS_HLS
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sc_uint<8> dram::read0(sc_uint<28> A0, bool WE0) {
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sc_uint<8> DOUT0;
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CYN_BIND(WE0,this->WE0);
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CYN_BIND(A0,this->A0);
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CYN_BIND(DOUT0,this->DOUT0);
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HLS_CONFIG_INSTRUCTION( "access_port", 1 );
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DOUT0 = mem[A0];
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return DOUT0;
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}
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#endif // STRATUS_HLS
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#ifdef STRATUS_HLS
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sc_uint<8> dram::write0(sc_uint<28> A0, sc_uint<8> DIN0, bool WE0) {
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CYN_BIND(WE0,this->WE0);
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CYN_BIND(A0,this->A0);
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CYN_BIND(DIN0,this->DIN0);
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HLS_CONFIG_INSTRUCTION( "access_port", 1 );
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mem[A0] = DIN0;
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return DIN0;
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}
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#endif // STRATUS_HLS
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#ifdef STRATUS_HLS
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void dram::nop0(bool WE0) {
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CYN_BIND(WE0,this->WE0);
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HLS_CONFIG_INSTRUCTION( "access_port", 1 );
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}
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#endif // STRATUS_HLS
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void dram::thread0() {
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#if defined(__GNUC__) && BDW_USE_SCV
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if ( m_p1_tx_0.is_active() ) {
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m_p1_tx_stream->end_tx( m_p1_tx_0, DOUT0.read() );
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}
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#endif
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#if defined(__GNUC__)
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// Perform an address range check to prevent crashes on out of bounds
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// accesses in SystemC behavioral simulations.
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if((int)(A0.read()) <= WORDCOUNT) {
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#endif
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if(WE0.read() == 0) {
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#if defined(__GNUC__) && BDW_USE_SCV
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m_p1_tx_0 = m_p1_tx_stream->begin_write_tx( A0.read(), DIN0.read() );
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#endif
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#if defined(__GNUC__) && defined(BDW_TRACE_MEMS)
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fprintf(stderr,"TRACE: %s%s: %s: write 0x%s to 0x%x\n", name(), "", sc_time_stamp().to_string().c_str(), DIN0.read().to_string(SC_HEX).c_str(), (int)A0.read().to_uint());
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#endif
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mem[A0.read().to_uint()] = DIN0.read();
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#if defined(__GNUC__)
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sync_put(A0.read().to_uint());
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#endif
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} else {
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#if defined(__GNUC__)
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#if BDW_USE_SCV
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m_p1_tx_0 = m_p1_tx_stream->begin_read_tx( A0.read() );
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#endif
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sync_get(A0.read().to_uint());
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#endif
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#if defined(__GNUC__) && defined(BDW_TRACE_MEMS)
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fprintf(stderr,"TRACE: %s: %s: read 0x%s from 0x%x\n", name(), sc_time_stamp().to_string().c_str(), mem[A0.read().to_uint()].to_string(SC_HEX).c_str(), (int)A0.read().to_uint());
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#endif
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DOUT0 = mem[A0.read().to_uint()];
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}
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#if defined(__GNUC__)
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}
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#endif
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}
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#if defined(STRATUS_VLG)
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dram::dram(const sc_module_name name)
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: sc_module( name ) ,CLK("CLK"),WE0("WE0"),DIN0("DIN0"),DOUT0("DOUT0"),A0("A0"), mem()
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#else
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dram::dram( sc_module_name name)
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: sc_module( name ) ,CLK("CLK"),WE0("WE0"),DIN0("DIN0"),DOUT0("DOUT0"),A0("A0"), mem()
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#if defined(__GNUC__)
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, m_iface(0)
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#endif
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#endif
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{
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#ifdef STRATUS_HLS
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SC_CTHREAD( thread0, (CLK).pos() );
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#else
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SC_METHOD( thread0 );
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sensitive << (CLK).pos();
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#endif
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#ifndef STRATUS_HLS
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dont_initialize();
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#endif
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#if defined(__GNUC__) && BDW_USE_SCV
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esc_enable_scv_logging();
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m_p1_tx_stream = new cynw_scv_memory_tx_stream< sc_uint<28>, sc_uint<8> >( (std::string("sc_main.") + std::string(this->name())).c_str(), esc_get_scv_tr_db() );
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#endif
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}
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const unsigned long dram::implemented = 1;
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const unsigned long dram::pipelined = 1;
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const float dram::area = 0;
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const float dram::delay = 1;
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const float dram::setup_time = 1;
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const unsigned long dram::latency_WE0 = 1;
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const unsigned long dram::latency_DIN0 = 1;
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const unsigned long dram::latency_A0 = 1;
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const unsigned long dram::bits_per_maskbit_WM0 = 0;
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const unsigned long dram::reg_mem_inputs = 0;
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const unsigned long dram::reg_mem_outputs = 0;
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const unsigned long dram::regs_at_mem_inputs = 0;
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const unsigned long dram::regs_at_mem_outputs = 0;
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const unsigned long dram::no_spec_reads = 1;
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const unsigned long dram::is_mem = 1;
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const unsigned long dram::clock_multiplier = 0;
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const bool dram::has_extra_ports = false;
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const bool dram::is_prototype = false;
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const char* dram::naming_convention = 0;
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#endif // dram_CC
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