Fix crash when using FDCAN3 RX IRQ on STM32G473 (and others)

[josephduchesne]

Summary of changes

• Fixed a crash that occurred whenever a can_irq fired on FDCAN3 (for stm32 targets with 3 FDCAN devices, such as STM32G473xx) by allocating sufficient can_irq_contexts[] for all FDCAN devices, rather than a hard-coded 2.

Impact of changes

No impact expected, aside from FDCAN3 ISR registration working correctly on STM32 devices with 3 FDCAN peripherals.

Documentation

STM32G473 (and others in its family) have 3 CANFD devices, but TARGET_STM/can_api.c has a hard-coded array of can_irq_contexts[2]. As a result, registering an RX ISR handler for a device using FDCAN3 results in a crash.

It's unclear how can_irq_init(...) avoids this crash, but can_irq(...) crashes on the line irq_handler(can_irq_contexts[id], IRQ_RX);.

• FDCAN3 exists on the stm32g473xx line, but the hard coded can_irq_contexts[2] static array does not allow registering an ISR handler. When you attempt to register one, the program crashes due to an out-of-bounds array access, trying to access can_irq_contexts[2] the array containing only indices 0 and 1.

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Pull request type

[x] Patch update (Bug fix / Target update / Docs update / Test update / Refactor)
[] Feature update (New feature / Functionality change / New API)
[] Major update (Breaking change E.g. Return code change / API behaviour change)

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Test results

[] No Tests required for this change (E.g docs only update)
[] Covered by existing mbed-os tests (Greentea or Unittest)
[x] Tests / results supplied as part of this PR

Prior to change:

Crash Info:
        Crash location = __exidx_start [0x20006430] (based on PC value)
        Caller location = can_irq [0x08006283] (based on LR value)
        Stack Pointer at the time of crash = [2001FFB0]
        Target and Fault Info:
                Processor Arch: ARM-V7M or above
                Processor Variant: C24
                Forced exception, a fault with configurable priority has been escalated to HardFault
                MPU or Execute Never (XN) default memory map access violation on an instruction fetch has occurred 

After change:

• FDCAN3 ISR works correctly (only verified experimentally, but better than nothing I suppose), and FDCAN1+FDCAN2 ISRs continue to work properly as well.

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Reviewers

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[jeromecoutant]

Good catch.

For information, here is a "grep" result to get the affected MCU:

targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/CMSIS/stm32g473xx.h:#define FDCAN3              ((FDCAN_GlobalTypeDef *) FDCAN3_BASE)
targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/CMSIS/stm32g474xx.h:#define FDCAN3              ((FDCAN_GlobalTypeDef *) FDCAN3_BASE)
targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/CMSIS/stm32g483xx.h:#define FDCAN3              ((FDCAN_GlobalTypeDef *) FDCAN3_BASE)
targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/CMSIS/stm32g484xx.h:#define FDCAN3              ((FDCAN_GlobalTypeDef *) FDCAN3_BASE)
targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/CMSIS/stm32h723xx.h:#define FDCAN3              ((FDCAN_GlobalTypeDef *) FDCAN3_BASE)
targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/CMSIS/stm32h725xx.h:#define FDCAN3              ((FDCAN_GlobalTypeDef *) FDCAN3_BASE)
targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/CMSIS/stm32h730xx.h:#define FDCAN3              ((FDCAN_GlobalTypeDef *) FDCAN3_BASE)
targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/CMSIS/stm32h730xxq.h:#define FDCAN3              ((FDCAN_GlobalTypeDef *) FDCAN3_BASE)
targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/CMSIS/stm32h733xx.h:#define FDCAN3              ((FDCAN_GlobalTypeDef *) FDCAN3_BASE)
targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/CMSIS/stm32h735xx.h:#define FDCAN3              ((FDCAN_GlobalTypeDef *) FDCAN3_BASE)

[0xc0170]

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